Circuit device and physical quantity detection device

Abstract

To provide a circuit device or the like that can execute processing on a physical quantity and processing of temperature correction operation or fault diagnosis by allotting them to a DSP and a CPU, respectively.SOLUTION: A circuit device 20 includes: a driving circuit 30 that drives a physical quantity transducer 10; a detection circuit 60 that detects a physical quantity on the basis of a detection signal from the physical quantity transducer 10 and outputs detection data of the physical quantity; a DSP 100 that performs digital signal processing including digital filter processing on the detection data; a storage unit 160 that stores a program in which a plurality of commands are described; and a CPU 130 that operates on the basis of the program and performs at least one of temperature correction operation and fault diagnosis for the detection data.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a circuit device, a physical quantity detection device, and the like. [Background technology]

[0002] Patent Document 1 discloses a sensor failure prediction system that detects in advance the state leading up to failure of a physical quantity sensor by having a processor generate predictive information regarding the step-by-step or continuous state leading up to failure of the physical quantity sensor based on signal information regarding the measurement values ​​of a drive signal or a detection signal and reference information. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2020-153891 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the conventional technology of Patent Document 1, it was not clear how the failure prediction information and the detection signal of the physical quantity were generated and by what kind of processor configuration. [Means for solving the problem]

[0005] One aspect of the present disclosure relates to a circuit device including: a drive circuit that drives a physical quantity transducer; a detection circuit that detects a physical quantity based on a detection signal from the physical quantity transducer and outputs detection data of the physical quantity; a DSP that performs digital signal processing including digital filter processing on the detection data; a memory unit that stores a program in which a plurality of instructions are written; and a CPU that operates based on the program to perform at least one of a temperature correction calculation of the detection data and a fault diagnosis.

[0006] Another aspect of the present disclosure relates to a physical quantity detection device including the above-described circuit device and the physical quantity transducer. [Brief description of the drawings]

[0007] [Figure 1] 3 shows an example of the configuration of a circuit device and a physical quantity detection device according to the present embodiment. [Diagram 2] 3 shows an example of a detailed configuration of the circuit device and the physical quantity detection device according to the present embodiment. [Diagram 3] 1 shows an example of a fault detection circuit configuration. [Figure 4] An example of a physical quantity transducer. [Diagram 5] FIG. 4 is a signal waveform diagram illustrating the operation of the present embodiment. [Figure 6] FIG. 4 is a signal waveform diagram illustrating the operation of the present embodiment. [Figure 7] 5 is a graph for explaining the angular velocity dependency of a fault diagnosis result in the embodiment. FIG. [Figure 8] FIG. 1 is a block diagram showing a detailed configuration example of a DSP and CPU. [Figure 9] An example of CPU hardware configuration. [Figure 10] FIG. 4 is a signal waveform diagram illustrating the operation of a CPU. [Figure 11] A state transition diagram explaining the operation of a CPU. [Figure 12] An explanatory diagram of the cooperative operation of a DSP and a CPU. [Figure 13] FIG. 2 is an explanatory diagram of a DSP execution sequence. [Figure 14] FIG. 4 is an explanatory diagram of low-pass filter processing. [Figure 15] FIG. 4 is an explanatory diagram of a notch filter process. [Figure 16] Diagram of user-defined filtering. [Figure 17] FIG. 4 is a diagram illustrating the operation of a CPU of a comparative example. [Figure 18] 5 is a diagram illustrating noise generated depending on the cycle of fault diagnosis. [Figure 19] FIG. 2 is a diagram illustrating the operation of the DSP and CPU according to the embodiment. [Figure 20]An explanatory diagram of the operating frequencies of DSP and CPU. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] The present embodiment will be described below. Note that the present embodiment described below does not unduly limit the contents of the claims. Furthermore, not all of the configurations described in the present embodiment are necessarily essential configurations.

[0009] 1. Circuit devices, physical quantity detection devices 1 shows an example of the configuration of a circuit device 20 and a physical quantity detection device 5 according to this embodiment. The physical quantity detection device 5, which is a sensor device, includes a physical quantity transducer 10 and a circuit device 20. The physical quantity detection device 5 can also be called a physical quantity measuring device. Note that the circuit device 20 and the physical quantity detection device 5 are not limited to the configuration shown in FIG. 1, and various modifications are possible, such as omitting some of the components or adding other components.

[0010] The physical quantity transducer 10 is an element for detecting a physical quantity, and an example of the element is a vibrator. When the physical quantity transducer 10 is a vibrator, the physical quantity transducer 10 has a vibrating piece, and the physical quantity is detected by utilizing the vibration of the vibrating piece. For example, when the physical quantity transducer 10 is a gyro sensor element, the angular velocity is detected as the physical quantity. The gyro sensor element may be a sensor element having a piezoelectric vibrating piece formed from a thin plate of a piezoelectric material such as quartz. Specifically, the gyro sensor element is a sensor element having a vibrating piece such as a double T-shaped, tuning fork-shaped, or H-shaped vibrating piece formed from a quartz substrate such as a Z-cut. Alternatively, a MEMS (Micro Electro Mechanical Systems) type sensor element may be used as the gyro sensor element. The physical quantity detected by the physical quantity transducer 10 may be a physical quantity other than the angular velocity, such as angular acceleration, angle, acceleration, speed, moving distance, or pressure.

[0011] The circuit device 20 is, for example, a semiconductor circuit device, and an example of the circuit device is an integrated circuit device called an IC (Integrated Circuit). The circuit device 20 can also be called a physical quantity detection circuit. In FIG. 1, the circuit device 20 includes a drive circuit 30, a detection circuit 60, a DSP (Digital Signal Processor) 100, a CPU (Central Processing Unit) 130, and a storage unit 160.

[0012] The driving circuit 30 is a circuit that drives the physical quantity transducer 10. For example, the driving circuit 30 drives the physical quantity transducer 10 by outputting a driving signal DS to the physical quantity transducer 10. For example, if the physical quantity transducer 10 has a vibrating piece, the vibrating piece is driven to vibrate by the driving signal DS from the driving circuit 30. The driving signal DS is, for example, a square wave signal, but may be a sine wave signal. Taking a gyro sensor element as an example, the vibrating piece is vibrated by driving the driving circuit 30, and the angular velocity is detected by detecting the Coriolis force.

[0013] The detection circuit 60 detects a physical quantity based on the detection signal S from the physical quantity transducer 10. For example, the detection circuit 60 detects the physical quantity based on the detection signal S and outputs detection data DQA of the physical quantity. The detection signal S is a detection signal of the physical quantity with, for example, the driving frequency of the driving signal DS as a carrier frequency. The detection circuit 60 detects the physical quantity in the detection signal S by, for example, synchronously detecting the signal based on the detection signal S using a synchronization signal. The detection data DQA output by the detection circuit 60 is digital data, and is, for example, data indicating the detection level of the detected physical quantity.

[0014] The DSP100 is a processor that performs digital signal processing. The DSP100 performs digital signal processing, including digital filtering, on the detection data DQA of the physical quantity from the detection circuit 60. Then, the detection data after the digital filtering by the DSP100 is output as, for example, the final detection value of the physical quantity of the physical quantity detection device 5. The digital filtering that the DSP100 can perform includes various filtering such as low-pass filtering, notch filtering, high-pass filtering, band-pass filtering, and user-defined filtering. The digital signal processing that the DSP100 performs is not limited to digital filtering, and can perform various types of digital signal processing such as digital temperature compensation processing and various types of correction processing. The DSP100 is a digital signal processing circuit that is configured by hardware circuits for performing various types of digital signal processing.

[0015] The storage unit 160 stores a program in which a plurality of instructions are described. The storage unit 160 is a storage circuit configured by a memory or a register circuit. A plurality of instructions executable by the CPU 130 are described in the program stored in the storage unit 160. The plurality of instructions are an instruction set. Examples of such instructions include arithmetic operation instructions such as addition, subtraction, immediate value addition, immediate value subtraction, comparison, or immediate value comparison, shift operation instructions such as right logical shift, right arithmetic shift, or left logical shift, logical operation instructions such as AND, OR, XOR, or NOT, transfer instructions between a register or SRAM, or various conditional branch instructions. The storage unit 160 may store information other than the program, such as information such as filter coefficients required for digital filter processing of the DSP 100. The storage unit 160 may be realized by a volatile memory such as a RAM, or may be realized by a non-volatile memory such as an EPROM, an EEPROM, or a ROM, or may be realized by both a volatile memory and a non-volatile memory.

[0016] The CPU 130 operates based on a program stored in the storage unit 160. For example, the CPU 130 decodes each of a plurality of instructions written in the program and executes various arithmetic processing based on the decoding results. The CPU 130 operates based on the program in this way to perform at least one of a temperature correction calculation of the detection data of the detection circuit 60 and a fault diagnosis. For example, the instructions written in the program are various instructions for executing such a temperature correction calculation and a fault diagnosis. For example, the temperature correction calculation is a process of calculating a temperature correction value for a temperature compensation process of the detection data. For example, the temperature correction calculation is a process of calculating a temperature correction value for a zero point correction or a temperature correction value for a sensitivity correction. The temperature compensation process is a process of suppressing and compensating for a fluctuation in the detection value of a physical quantity due to a temperature fluctuation. The fault diagnosis is a diagnosis of an abnormal state of the circuit device 20 and the physical quantity detection device 5 including the circuit device 20. Examples of the fault diagnosis include a fault diagnosis using an electrostatic leakage component, a fault diagnosis using a mechanical leakage component, or a fault diagnosis of a computing unit such as the DSP 100 or the CPU 130, which will be described later. The CPU 130 may include peripheral circuits in addition to the CPU core circuit, such as a watchdog timer circuit, a clock counter, or a threshold determination circuit.

[0017] The DSP 100 and the CPU 130 are prepared, for example, as macroblocks and laid out in the circuit device 20, which is a semiconductor IC. For example, the macroblocks of the DSP 100 and the CPU 130 are shared by the circuit devices 20 and physical quantity detection devices 5 of a plurality of types of products.

[0018] As described above, the circuit device 20 of the present embodiment includes a driving circuit 30 for driving the physical quantity transducer 10, a detection circuit 60 for detecting a physical quantity based on a detection signal S from the physical quantity transducer 10, a DSP for performing digital signal processing on the detection data DQA of the detection circuit 60, and a CPU 130 for performing temperature correction calculation and fault diagnosis of the detection data based on a program stored in the storage unit 160. In this manner, the detection data DQA of the physical quantity in the detection circuit 60 can be subjected to digital signal processing including digital filter processing by the DSP 100 to obtain the detection value of the physical quantity. For example, it is possible to output the detection value of the physical quantity with a higher throughput by using the DSP 100 that is faster than the CPU 130. On the other hand, the temperature correction calculation or fault diagnosis can be performed by the CPU 130 that operates based on a program stored in the storage unit 160. For example, it is possible to perform a temperature correction calculation or fault diagnosis with a high degree of freedom by using a rewritable program by the CPU 130. That is, it is possible to realize a circuit device 20 and a physical quantity detection device 5 that can share the processing of physical quantities with temperature correction calculation or fault diagnosis. In addition, for example, by transferring data between the DSP 100 and the CPU 130, it is also possible to realize cooperative operation using two computing units (DSP, CPU).

[0019] 2. Detailed configuration example 2 shows a detailed configuration example of the circuit device 20 and the physical quantity detection device 5 of this embodiment. The circuit device 20 includes a drive circuit 30, a detection circuit 60, a DSP 100, a CPU 130, and a storage unit 160. The circuit device 20 may also include a fault detection circuit 170 and an interface circuit 180. Note that the circuit device 20 and the physical quantity detection device 5 are not limited to the configurations shown in FIG. 2, and various modifications are possible, such as omitting some of the components and adding other components.

[0020] The physical quantity transducer 10, which is a sensor element, has vibrating bars 11 and 12, driving electrodes 13 and 14, detection electrodes 15 and 16, and a ground electrode 17. The vibrating bars 11 and 12 are piezoelectric vibrating bars formed from a thin plate of a piezoelectric material such as quartz. Specifically, the vibrating bars 11 and 12 are vibrating bars formed from a Z-cut quartz substrate. The piezoelectric material of the vibrating bars 11 and 12 may be a material other than quartz, such as ceramics or silicon.

[0021] A drive signal DS is supplied to the drive electrode 13 from the drive circuit 30, which causes the drive vibrating arm 11 to vibrate. A feedback signal DG from the drive electrode 14 is input to the drive circuit 30. For example, the feedback signal DG generated by the vibration of the vibrating arm 11 is input to the drive circuit 30. The vibration of the drive vibrating arm 11 causes the detection vibrating arm 12 to vibrate, and charges generated by this vibration are input to the detection circuit 60 from the detection electrodes 15 and 16 as detection signals S1 and S2. Here, the ground electrode 17 is set to GND, which is the ground potential. The circuit device 20 detects physical quantities such as angular velocity corresponding to the detection signals S1 and S2 based on these detection signals S1 and S2.

[0022] The drive circuit 30 includes an amplifier circuit 32 , a gain control circuit 40 , a drive signal output circuit 50 , and a synchronization signal output circuit 52 .

[0023] The amplifier circuit 32 amplifies the feedback signal DG from the physical quantity transducer 10. For example, the amplifier circuit 32, which is an I / V conversion circuit, converts the current feedback signal DG from the physical quantity transducer 10 into a voltage signal DV and outputs it. This amplifier circuit 32 can be realized by an operational amplifier, a feedback resistor element, a feedback capacitor, etc.

[0024] The gain control circuit 40 outputs a control voltage VC to the drive signal output circuit 50 to control the amplitude of the drive signal DS. Specifically, the gain control circuit 40, which is an AGC circuit, monitors the signal DV and controls the gain of the oscillation loop. For example, in the drive circuit 30, in order to keep the sensitivity of the sensor constant, it is necessary to keep the amplitude of the drive voltage supplied to the physical quantity transducer 10 constant. For this reason, a gain control circuit 40 for automatically adjusting the gain is provided in the oscillation loop of the drive vibration system. The gain control circuit 40 automatically adjusts the gain variably so that the amplitude of the feedback signal DG from the physical quantity transducer 10 becomes constant.

[0025] The gain control circuit 40 includes a full-wave rectifier circuit 42 and an integrator circuit 44. The full-wave rectifier circuit 42 performs full-wave rectification of the AC signal DV output by the amplifier circuit 32. The integrator circuit 44 performs integration processing of the signal from the full-wave rectifier circuit 42. Specifically, the integrator circuit 44 performs integration processing of the signal full-wave rectified by the full-wave rectifier circuit 42, and outputs a control voltage VC obtained by the integration processing to the drive signal output circuit 50. In this way, it becomes possible to output to the drive signal output circuit 50 a control voltage VC corresponding to a DC voltage obtained by smoothing the full-wave rectified signal.

[0026] The drive signal output circuit 50 outputs a drive signal DS based on the signal DV amplified by the amplifier circuit 32. The drive signal output circuit 50 outputs, for example, a rectangular wave drive signal DS such that the control voltage VC from the gain control circuit 40 becomes a high-level voltage that is a voltage on the high potential side. When the drive signal output circuit 50 outputs a rectangular wave drive signal DS in this way, the drive signal output circuit 50 can be realized by a comparator or the like. Note that modifications such as the drive signal output circuit 50 outputting a sine wave drive signal DS are also possible.

[0027] The synchronization signal output circuit 52 outputs a synchronization signal SYC. The synchronization signal SYC is a signal based on the drive signal DS. For example, the synchronization signal SYC is a signal generated based on the drive signal DS. Specifically, the synchronization signal SYC is a signal corresponding to the drive signal DS, and is, for example, a clock signal of a first frequency that is the same frequency as the drive signal DS of the first frequency. For example, the synchronization signal SYC is a signal in phase (in phase) with the drive signal DS. Here, in phase includes a case where the signals are approximately in phase. Specifically, in FIG. 2, the synchronization signal output circuit 52 generates the synchronization signal SYC based on a signal DV from the amplifier circuit 32. For example, as shown in FIG. 2, when the drive circuit 30 receives a feedback signal DG caused by the drive of the drive signal DS from the physical quantity transducer 10 and performs feedback control, the synchronization signal SYC is a signal generated based on this feedback signal DG. Specifically, the synchronization signal SYC is a signal generated based on a signal DV obtained by amplifying the feedback signal DG by the amplifier circuit 32. For example, the synchronization signal output circuit 52 outputs the synchronization signal SYC by shaping the sine wave signal DV into a square wave signal using a comparator or the like. Alternatively, the synchronization signal SYC may be a signal generated by buffering the drive signal DS. The synchronization signal SYC may also be called, for example, a reference signal or a detection clock signal.

[0028] The detection circuit 60 includes an amplifier circuit 61 , a synchronous detection circuit 90 , a filter section 92 , and an A / D conversion circuit 94 .

[0029] The amplifier circuit 61 receives the detection signals S1 and S2 from the physical quantity transducer 10, and performs charge-to-voltage conversion, signal amplification, and gain adjustment. The detection signals S1 and S2 form a differential signal. The amplifier circuit 61 includes Q / V conversion circuits 62 and 63, a differential amplifier circuit 64, and an AC amplifier circuit 66.

[0030] The Q / V conversion circuits 62 and 63 convert the detection signals S1 and S2, which are charge signals from the physical quantity transducer 10, into voltage signals. The Q / V conversion circuits 62 and 63 are continuous-type charge-voltage conversion circuits having a feedback resistor.

[0031] The differential amplifier circuit 64 performs differential amplification of the signals VS1 and VS2 from the Q / V conversion circuits 62 and 63. This realizes amplification of the physical quantity signals contained in the signals VS1 and VS2. That is, since the physical quantity signals contained in the signals VS1 and VS2 are differential signals, the signals are amplified by performing differential amplification. The AC amplifier circuit 66 amplifies the output signal of the differential amplifier circuit 64 and outputs it as the output signal AQA of the amplifier circuit 61. The AC amplifier circuit 66 performs, for example, signal gain adjustment.

[0032] The synchronous detection circuit 90 performs synchronous detection on the output signal AQA of the amplifier circuit 61 based on the synchronization signal SYC. This makes it possible to extract the physical quantity signal, which is the desired signal, contained in the output signal AQA, and detect the physical quantity.

[0033] For example, the detection signals S1 and S2, which are charge signals from the physical quantity transducer 10, are delayed in phase by 90 degrees relative to the drive signal DS, which is a voltage signal. Also, the phase is delayed by 90 degrees in the Q / V conversion circuits 62, 63, etc. of the amplifier circuit 61. For this reason, the output signal AQA of the amplifier circuit 61 is delayed in phase by 180 degrees relative to the drive signal DS. Therefore, by performing synchronous detection using, for example, a synchronous signal SYC that is in phase with the drive signal DS, it becomes possible to remove unnecessary signals, etc., whose phase is delayed by 90 degrees relative to the drive signal DS, and detect the physical quantity.

[0034] The filter unit 92 performs filtering such as low-pass filtering on the output signal SQA from the synchronous detection circuit 90. The filter unit 92 functions as a pre-filter for the A / D conversion circuit 94 in the subsequent stage. The filter unit 92 also functions as a circuit for attenuating unnecessary signals that could not be completely removed by the synchronous detection. The A / D conversion circuit 94 performs A / D conversion on the analog output signal FQA from the filter unit 92, and outputs digital detection data DQA.

[0035] The DSP 100 performs various digital signal processing on the detection data DQA of the physical quantity from the detection circuit 60. The CPU 130 performs temperature correction calculation based on the detection data DQA and the temperature detection data. The DSP 100 performs temperature compensation processing on the detection data DQA based on a temperature correction value obtained by the temperature correction calculation of the CPU 130. The DSP 100 then performs digital filtering such as low-pass filtering and notch filtering on the detection data after the temperature compensation processing. The CPU 130 also performs fault diagnosis processing based on the fault detection data DQB and DQC from the fault detection circuit 170. Details of the fault detection circuit 170 will be described later.

[0036] The storage unit 160 includes a register unit 162 and a non-volatile memory 164. The non-volatile memory 164 stores various information necessary for the operation of the circuit device 20. For example, a program for operating the CPU 130 is stored in the non-volatile memory 164. For example, an EPROM, an EEPROM, or a flash memory can be used as the non-volatile memory 164. The information stored in the non-volatile memory 164 is transferred to the register unit 162. Each circuit of the circuit device 20, such as the DSP 100 and the CPU 130, operates based on information from the register unit 162 and writes various status information to the register unit 162. The register unit 162 is accessible from the outside via the interface circuit 180. The register unit 162 can be realized by, for example, a RAM or a flip-flop circuit.

[0037] The interface circuit 180 is a circuit for communicating with an external processing device, etc. For example, the interface circuit 180 performs communication with the external processing device based on a given communication standard. For example, the interface circuit 180 performs serial communication such as I2C (Inter-Integrated Circuit) or SPI (Serial Peripheral Interface).

[0038] Fig. 3 shows an example of the configuration of the fault detection circuit 170. Note that the fault detection circuit 170 is not limited to the configuration shown in Fig. 3, and various modifications are possible, such as omitting some of the components or adding other components. The fault detection circuit 170 includes an adder circuit 65, an AC amplifier circuit 67, an FLL circuit 70, a diagnostic synchronization signal generation circuit 80, synchronous detection circuits 91 and 96, filter sections 93 and 97, A / D conversion circuits 95 and 99, and a frequency divider circuit 98.

[0039] The adder circuit 65 performs summing amplification of the signals VS1 and VS2 from the Q / V conversion circuits 62 and 63 in Fig. 2. This realizes amplification of the electrostatic leakage signal contained in the signals VS1 and VS2. That is, since the electrostatic leakage signals contained in the signals VS1 and VS2 are in-phase signals, the signals are amplified by performing summing amplification. The AC amplifier circuit 67 amplifies the output signal of the adder circuit 65 and outputs it as the output signal AQB of the amplifier circuit 61.

[0040] The FLL circuit 70 has an oscillation circuit and generates a clock signal CK of a target frequency by the oscillation circuit. FLL is an abbreviation of Frequency Locked Loop. For example, the FLL circuit 70 compares the frequency of the clock signal CK with the target frequency and generates a clock signal CK of a frequency that matches the target frequency by the oscillation circuit. The FLL circuit 70 generates the clock signal CK of the target frequency by using a synchronization signal SYC based on the drive signal DS as a reference clock signal. For example, the FLL circuit 70 generates a clock signal CK whose frequency ratio with respect to the synchronization signal SYC, which is the reference clock signal, is kept constant. The frequency ratio is a multiplication rate, and constant includes approximately constant. In the FLL circuit 70, the frequency ratio of the clock signal CK to the synchronization signal SYC is locked. The synchronization signal SYC is, for example, a clock signal of a first frequency that is the same frequency as the drive signal DS of the first frequency. The synchronization signal SYC can also be called, for example, a reference signal or a detection clock signal.

[0041] The diagnostic synchronization signal generating circuit 80 generates a fault diagnostic synchronization signal SYC2 of a second frequency based on the clock signal CK. For example, the synchronization signal SYC based on the drive signal DS of a first frequency is a signal of a first frequency, whereas the diagnostic synchronization signal SYC2 is a signal of a second frequency. As an example, the diagnostic synchronization signal SYC2 is a signal of twice the frequency of the synchronization signal SYC. In this embodiment, for example, the FLL circuit 70 and the diagnostic synchronization signal generating circuit 80 perform a synchronization process such that the edge of the diagnostic synchronization signal SYC2 approaches the edge of the synchronization signal SYC. For example, a synchronization process is performed such that the edge of the diagnostic synchronization signal SYC2 falls within a given range with respect to the edge of the synchronization signal SYC. This range is, for example, a range of one clock period or less of the clock signal CK. The edge of the signal is a rising edge or a falling edge of the signal.

[0042] The synchronous detection circuit 91 performs synchronous detection on the output signal AQB of the AC amplifier circuit 67 based on the diagnostic synchronization signal SYC2. The output signal AQB is a signal obtained by adding and amplifying the signals VS1 and VS2, and therefore includes an electrostatic leakage signal, and the electrostatic leakage signal is, for example, a signal of a second frequency. Therefore, by synchronously detecting the output signal AQB using the diagnostic synchronization signal SYC2 of the second frequency, the electrostatic leakage signal included in the output signal AQB can be extracted. The filter unit 93 performs filtering such as low-pass filtering on the output signal SQB of the synchronous detection circuit 91. The A / D conversion circuit 95 performs A / D conversion on the analog output signal FQB from the filter unit 93, and outputs fault detection data DQB. This allows the CPU 130 to perform fault diagnosis by detecting the presence or absence of an electrostatic leakage signal.

[0043] On the other hand, the synchronous detection circuit 96 performs synchronous detection on the output signal AQB of the AC amplifier circuit 67 based on the diagnostic synchronization signal SYC3. The diagnostic synchronization signal SYC3 is, for example, a square wave voltage signal whose phase is advanced by 90 degrees with respect to the synchronization signal SYC for detecting the physical quantity signal. Therefore, the synchronous detection circuit 96 performs synchronous detection on the output signal AQB based on the diagnostic synchronization signal SYC3, thereby extracting the vibration leakage signal contained in the output signal AQB. Then, the filter unit 97 performs filtering such as low-pass filtering on the output signal SQC of the synchronous detection circuit 96. The A / D conversion circuit 99 performs A / D conversion on the analog output signal FQC from the filter unit 97, and outputs fault detection data DQC. This allows the CPU 130 to perform fault diagnosis by detecting the presence or absence of a vibration leakage signal.

[0044] The frequency divider circuit 98 divides the clock signal CK from the FLL circuit 70 to output a clock signal ADCK for A / D conversion and a master clock signal MCK for the circuit device 20 used in the DSP 100 or the like. The A / D conversion circuits 94, 95, and 99 perform A / D conversion based on the clock signal ADCK. As an example, the clock signal CK is, for example, 8 MHz, the master clock signal MCK is, for example, 4 MHz, and the clock signal ADCK is, for example, about 47 to 48 kHz. For example, by shifting the clock signal ADCK for A / D conversion from the drive frequency of 50 kHz, it becomes possible to prevent noise due to A / D conversion from adversely affecting the detection accuracy of angular velocity and the like.

[0045] For example, in this embodiment, fault diagnosis is performed using an electrostatic leakage component generated by a coupling capacitance between the driving electrode 13 and the detection electrodes 15 and 16. The coupling capacitance is an electrostatic coupling capacitance. For example, a coupling capacitance is formed between the driving electrode 13 to which the driving signal DS is supplied and the detection electrode 15 to which the detection signal S1 is output, and a coupling capacitance is also formed between the driving electrode 13 and the detection electrode 16 to which the detection signal S2 is output. In this way, a coupling capacitance is formed due to the physical structure of the electrodes of the physical quantity transducer 10, and an electrostatic leakage component caused by this coupling capacitance appears in the detection signals S1 and S2. An electrostatic leakage signal, which is a signal of this electrostatic leakage component, is detected by synchronous detection of the synchronous detection circuit 91 based on the diagnostic synchronization signal SYC2, thereby making it possible to realize fault diagnosis using the detection of the electrostatic leakage signal.

[0046] FIG. 4 shows a double-T shaped gyro sensor element as an example of the physical quantity transducer 10.

[0047] The physical quantity transducer 10 in FIG. 4 has driving arms 18A, 18B, 18C, and 18D, detection arms 19A and 19B, a base 21, and connecting arms 22A and 22B. The detection arms 19A and 19B extend from the rectangular base 21 in the +Y-axis direction and the -Y-axis direction. The connecting arms 22A and 22B extend from the base 21 in the +X-axis direction and the -X-axis direction. The driving arms 18A and 18B extend from the tip of the connecting arm 22A in the +Y-axis direction and the -Y-axis direction. The driving arms 18C and 18D extend from the tip of the connecting arm 22B in the +Y-axis direction and the -Y-axis direction. The hammer heads provided on the tip sides of the driving arms 18A, 18B, 18C, and 18D and the detection arms 19A and 19B are used, for example, as weights for adjusting the frequency. If the Z-axis is the thickness direction of the physical quantity transducer 10, the physical quantity transducer 10, which is a gyro sensor element, detects an angular velocity around the Z-axis. The X-axis and the Y-axis are coordinate axes perpendicular to the Z-axis, and the X-axis and the Y-axis are perpendicular to each other. The vibration arm of the physical quantity transducer 10 can be formed of a piezoelectric material such as quartz, lithium tantalate, or lithium niobate. Among these, it is preferable to use quartz as a constituent material of the vibration arm. The X-axis, the Y-axis, and the Z-axis are also called the electric axis, the mechanical axis, and the optical axis of the quartz substrate, respectively. The quartz substrate is formed of a plate-shaped Z-cut quartz plate having a thickness in the Z-axis direction.

[0048] Drive electrodes 13 are formed on the upper and lower surfaces of the drive arms 18A and 18B, and drive electrodes 14 are formed on the right and left sides of the drive arms 18A and 18B. Drive electrodes 14 are formed on the upper and lower surfaces of the drive arms 18C and 18D, and drive electrodes 13 are formed on the right and left sides of the drive arms 18C and 18D. A drive signal DS from a drive circuit 30 is supplied to the drive electrode 13, and a feedback signal DG from the drive electrode 14 is input to the drive circuit 30.

[0049] A detection electrode 15 is formed on the upper and lower surfaces of the detection arm 19A, and a ground electrode 17 is formed on the right and left sides of the detection arm 19A. A detection electrode 16 is formed on the upper and lower surfaces of the detection arm 19B, and a ground electrode 17 is formed on the right and left sides of the detection arm 19B. Detection signals S1 and S2 from the detection electrodes 15 and 16 are input to a detection circuit 60.

[0050] Grooves (not shown) are provided on the upper and lower surfaces of the drive arms 18A, 18B, 18C, and 18D and the detection arms 19A and 19B to improve the electric field effect between the electrodes. Providing the grooves makes it possible to generate a relatively large amount of charge with a relatively small amount of distortion. The upper surface is the surface on the +Z axis direction, and the lower surface is the surface on the -Z axis direction. The right side surface is the side surface on the +X axis direction, and the left side surface is the side surface on the -X axis direction.

[0051] Next, the operation of the physical quantity transducer 10 in FIG. 4 will be described. When a drive signal DS is applied to the drive electrode 13 by the drive circuit 30, the drive arms 18A, 18B, 18C, and 18D perform bending vibration as shown by the arrow A1 in FIG. 4 due to the inverse piezoelectric effect. The bending vibration is also called excitation vibration. For example, the vibration mode shown by the solid line of the arrow A1 and the vibration mode shown by the dotted line are repeated at a predetermined frequency. That is, the tips of the drive arms 18A and 18C repeat approaching and separating from each other, and the tips of the drive arms 18B and 18D also perform bending vibration in which they repeat approaching and separating from each other. At this time, the drive arms 18A and 18B and the drive arms 18C and 18D perform vibrations that are symmetrical with respect to the X-axis that passes through the center of gravity of the base 21, so that the base 21, the connecting arms 22A and 22B, and the detection arms 19A and 19B hardly vibrate.

[0052] In this state, when an angular velocity with the Z-axis as the rotation axis acts on the physical quantity transducer 10 and the physical quantity transducer 10 rotates around the Z-axis, the Coriolis force causes the drive arms 18A, 18B, 18C, and 18D to vibrate as shown by the arrow A2. That is, the Coriolis force in the direction of the arrow A2 perpendicular to the direction of the arrow A1 and the direction of the Z-axis acts on the drive arms 18A, 18B, 18C, and 18D, generating a vibration component in the direction of the arrow A2. This vibration of the arrow A2 is transmitted to the base 21 via the connecting arms 22A and 22B, and this causes the detection arms 19A and 19B to perform bending vibration in the direction of the arrow A3. The charge signals generated by the piezoelectric effect due to the bending vibration of the detection arms 19A and 19B are input to the detection circuit 60 as the detection signals S1 and S2, and the angular velocity around the Z-axis is detected.

[0053] For example, if the angular velocity of the physical quantity transducer 10 around the Z axis is ω, the mass is m, and the vibration velocity is v, then the Coriolis force is expressed as Fc = 2m v ω. Therefore, the detection circuit 60 can obtain the angular velocity ω around the Z axis by detecting a desired signal, which is a physical quantity signal that is a signal corresponding to the Coriolis force.

[0054] In FIG. 4, a coupling capacitance C1 exists between the driving electrode 13 and the detection electrode 15, and a coupling capacitance C2 exists between the driving electrode 13 and the detection electrode 16. Therefore, when the driving electrode 13 is driven by the driving signal DS, the AC frequency component contained in the driving signal DS is propagated to the detection electrode 16, and an AC charge signal based on the frequency component appears in the detection signals S1 and S2. Therefore, when the driving signal DS has a second frequency component, an AC charge signal based on the second frequency component appears in the detection signals S1 and S2. Then, the signals of the second frequency component appearing in the detection signals S1 and S2 are added and amplified by the adder circuit 65, and are detected in the synchronous detection circuit 91 based on the diagnostic synchronous signal SYC2 of the second frequency. Then, the CPU 130 judges whether or not a failure has occurred based on the detection result.

[0055] Next, the operation of this embodiment will be described with reference to the signal waveform diagrams of Fig. 5 and Fig. 6. Fig. 5 is a signal waveform diagram for explaining detection of physical quantity components contained in the detection signals S1 and S2 of the physical quantity transducer 10.

[0056] The signal DV is an output signal of the amplifier circuit 32 of the drive circuit 30, and is an AC signal of a first frequency f1. The first frequency f1 is, for example, the drive frequency of the drive circuit 30, and is, for example, 50 kHz. The drive signal DS is a signal generated by the drive signal output circuit 50 based on the signal DV from the amplifier circuit 32. The drive signal DS is a signal in phase with the signal DV, and is a square wave voltage signal whose high-level voltage is set based on the control voltage VC from the gain control circuit 40. The drive signal DS has a component of the first frequency f1, which is the drive frequency, and also has a component of the second frequency f2=2×f1. The signal of the first frequency can also be called an ω signal, and the signal of the second frequency can also be called a 2ω signal. For example, the drive signal DS has a component of the second frequency f2 superimposed on a high-level voltage. This component of the second frequency f2 is a component generated by the full-wave rectifier circuit 42 of the gain control circuit 40. For example, a signal obtained by full-wave rectifying the signal DV by the full-wave rectifier circuit 42 has a component of a second frequency f2 that is twice the first frequency f1, in addition to a component of a first frequency f1. This component of the second frequency f2 is superimposed on the control voltage VC from the integration circuit 44, which integrates the full-wave rectified signal from the full-wave rectifier circuit 42, so that the component of the second frequency f2 appears in the high-level voltage of the drive signal DS.

[0057] The synchronization signal SYC is generated, for example, by shaping the sine wave (AC) signal DV into a square wave signal by the synchronization signal output circuit 52. The synchronization signal SYC is a signal in phase with the drive signal DS and is a square wave voltage signal with a first frequency f1.

[0058] The signals VS1 and VS2 in FIG. 5 indicate signals of physical quantity components included in the output signals of the Q / V conversion circuits 62 and 63. In this embodiment, the signals of physical quantity components are also referred to as physical quantity signals as appropriate. The signals VS1 and VS2 form differential signals having opposite phases to each other. The amplifier circuit 61 outputs an output signal AQA generated by differentially amplifying the signals VS1 and VS2 using the differential amplifier circuit 64. The synchronous detection circuit 90 outputs an output signal SQA by synchronously detecting the output signal AQA of the amplifier circuit 61 based on a synchronous signal SYC. This output signal SQA is a full-wave rectified signal. The filter unit 92 outputs a DC voltage signal obtained by smoothing the output signal SQA, which is a full-wave rectified signal, as an output signal FQA. This DC voltage output signal FQA is A / D converted by the A / D conversion circuit 94 and input to the DSP 100 or the like as digital detection data DQA. The DSP 100 detects the angular velocity, which is a physical quantity, based on this detection data DQA.

[0059] FIG. 6 is a signal waveform diagram for explaining detection of electrostatic leakage components contained in the detection signals S1 and S2 of the physical quantity transducer 10. In FIG.

[0060] The signal DV, the drive signal DS, and the synchronization signal SYC are the same as those in FIG. 5, and therefore detailed description thereof will be omitted. As shown in FIG. 6, in this embodiment, the diagnostic synchronization signal SYC2 of the second frequency f2 is digitally generated by the FLL circuit 70 and the diagnostic synchronization signal generation circuit 80. That is, the FLL circuit 70 generates a clock signal CK of a target frequency using the synchronization signal SYC based on the drive signal DS as a reference clock signal. The clock signal CK is a high-speed clock signal of, for example, 8 MHz. Then, the diagnostic synchronization signal generation circuit 80 generates the diagnostic synchronization signal SYC2 of the second frequency f2 based on this high-speed clock signal CK. The diagnostic synchronization signal SYC2 is a signal of the second frequency f2, which is twice the synchronization signal SYC of the first frequency f1. And, for example, the diagnostic synchronization signal SYC2 is a signal whose rising edge is within, for example, one clock period of the clock signal CK with respect to the rising edge of the synchronization signal SYC.

[0061] The signals VS1 and VS2 in FIG. 6 indicate electrostatic leakage component signals included in the output signals of the Q / V conversion circuits 62 and 63. The electrostatic leakage component signals in the signals VS1 and VS2 are signals in phase with each other, which are signals in which the second frequency component of the drive signal DS is propagated through the coupling capacitances C1 and C2 described in FIG. 4. The amplifier circuit 61 outputs an output signal AQB generated by adding and amplifying the signals VS1 and VS2 using the adder circuit 65. The synchronous detection circuit 91 outputs an output signal SQB, which is a full-wave rectified signal, by synchronously detecting the output signal AQB of the amplifier circuit 61 based on the diagnostic synchronization signal SYC2. The electrostatic leakage component signals in the signals VS1 and VS2 are signals of the second frequency f2, which are signals in which the second frequency component of the drive signal DS is propagated through the coupling capacitances C1 and C2. Therefore, the electrostatic leakage component can be detected by synchronous detection using the diagnostic synchronization signal SYC2 of the second frequency f2. 3 outputs a DC voltage signal obtained by smoothing the output signal SQB, which is a full-wave rectified signal, as an output signal FQB. This DC voltage output signal FQB is A / D converted by an A / D conversion circuit 95 and input to the CPU 130 as digital fault detection data DQB. The CPU 130 performs fault diagnosis based on this fault detection data DQB. For example, when a signal of an electrostatic leakage component is detected by the synchronous detection circuit 91, the CPU 130 determines that no fault has occurred. On the other hand, when a signal of an electrostatic leakage component is not detected by the synchronous detection circuit 91, the CPU 130 determines that a fault such as a broken wire has occurred.

[0062] The CPU 130 also performs a fault diagnosis using mechanical leakage based on the fault detection data DQC due to mechanical leakage from the fault detection circuit 170.

[0063] 5, since the differential amplifier circuit 64 performs differential amplification of the signals VS1 and VS2, the signal of the electrostatic leakage component of the same phase appearing in the signals VS1 and VS2 in Fig. 6 hardly appears in the output signal AQA and is not detected by the synchronous detection circuit 90. On the other hand, since the adder circuit 65 performs summing amplification of the signals VS1 and VS2 in Fig. 6, the signal of the physical quantity component of the differential signal appearing in the signals VS1 and VS2 in Fig. 5 hardly appears in the output signal AQB and is not detected by the synchronous detection circuit 91.

[0064] FIG. 7 is an explanatory diagram of the angular velocity dependency of the fault diagnosis result in this embodiment. The horizontal axis represents the angular velocity, which is a physical quantity, and the vertical axis represents the output fluctuation based on the normal state. The output fluctuation based on the normal state represents a change amount corrected to 0 in normal state when no disconnection occurs. VT is a threshold value used in fault diagnosis. Since the output fluctuation is below the threshold value VT in normal state, the CPU 130 can determine that no abnormality occurs. On the other hand, in the case of a double-sided disconnection where disconnection occurs on both the detection signal S1 side and the detection signal S2 side, the output fluctuation exceeds the threshold value VT, so the CPU 130 can determine that an abnormality has occurred. Also, in the case of a single-sided disconnection where disconnection occurs only on the detection signal S1 side or only on the detection signal S2 side, the output fluctuation exceeds the threshold value VT, so the CPU 130 can determine that an abnormality has occurred.

[0065] For example, when one-side disconnection occurs, even if the signals VS1 and VS2 are added and amplified by the adder circuit 65 in FIG. 2, the signals of the physical quantity components are not cancelled out and remain in the output signal AQB of the amplifier circuit 61. That is, the signal of the physical quantity component corresponding to the signal DV in FIG. 6 remains in the output signal AQB. In this case, if the duty ratio of the diagnostic synchronization signal SYC2 is 50%, the signal of the physical quantity component after synchronous detection in the period TA of the diagnostic synchronization signal SYC2 in FIG. 6 and the signal of the physical quantity component after synchronous detection in the period TB cancel each other out and do not appear in the output signal FQB of the filter unit 93. This is because, when the duty ratio of the diagnostic synchronization signal SYC2 is 50%, the periods TA and TB have the same length. Similarly, the signal of the physical quantity component after synchronous detection in the period TC and the signal of the physical quantity component after synchronous detection in the period TD cancel each other out and do not appear in the output signal FQB of the filter unit 93. Therefore, no signal of the physical quantity component appears in the output signal FQB of the filter section 93, and it becomes possible to detect only the signal of the electrostatic leakage component.

[0066] On the other hand, if the duty ratio of the diagnostic synchronization signal SYC2 cannot be maintained, the lengths of the periods TA and TB will differ, or the lengths of the periods TC and TD will differ. Therefore, the signal of the physical quantity component after synchronous detection in the period TA in FIG. 6 and the signal of the physical quantity component after synchronous detection in the period TB will remain without canceling each other. Also, the signal of the physical quantity component after synchronous detection in the period TC and the signal of the physical quantity component after synchronous detection in the period TD will remain without canceling each other. As a result, the signal of the physical quantity component will remain in the output signal FQB of the filter unit 93, and for example, in the case of a one-side break, the fault diagnosis result will have angular velocity dependency. Therefore, if it is determined whether or not an abnormality has occurred by comparing with the threshold value VT, a problem occurs in that an erroneous abnormality diagnosis will be performed.

[0067] In this embodiment, the diagnostic synchronization signal SYC2 is generated by digital processing using the FLL circuit 70 and the diagnostic synchronization signal generating circuit 80. Therefore, it is possible to prevent the diagnostic synchronization signal SYC2 from being generated with a mixed duty ratio, and the duty ratio of the diagnostic synchronization signal SYC2 can be maintained. For example, the periods TA and TB, and the periods TC and TD in FIG. 6 can be made to have the same length, and the diagnostic synchronization signal SYC2 with a duty ratio of, for example, 50% can be digitally generated. This prevents the output fluctuation from having angular velocity dependency even in the case of a one-side break. Therefore, if the output fluctuation is below the threshold value VT, it can be determined that no abnormality has occurred and that a normal state has been established, and if the output fluctuation is above the threshold value VT, it can be properly determined that an abnormality has occurred, such as a one-side break or a both-side break.

[0068] As described above, the circuit device 20 of the present embodiment includes a driving circuit 30 that drives the physical quantity transducer 10, a detection circuit 60 that detects a physical quantity based on the detection signals S1 and S2 from the physical quantity transducer 10 and outputs detection data DQA of the physical quantity, and a DSP 100 that performs digital signal processing on the detection data DQA. The circuit device 20 also includes a storage unit 160 that stores a program in which a plurality of instructions are described, and a CPU 130 that operates based on the stored program to perform at least one of a temperature correction calculation for the detection data DQA and a fault diagnosis. For example, the CPU 130 performs a temperature correction calculation to obtain a temperature correction value for temperature compensation processing based on the detection data DQA of the detection circuit 60. Alternatively, the CPU 130 performs a fault diagnosis of the circuit device 20 or the physical quantity detection device 5 based on the fault detection data DQB, DQB, etc. from the fault detection circuit 170.

[0069] In this way, the calculation of the detection data DQA of the physical quantity such as angular velocity can be performed by the high-speed DSP100, and the calculation of temperature correction, fault diagnosis, etc. can be performed by the CPU130 with a high degree of freedom. For example, since the DSP100 is a circuit specialized for the calculation of the detection data DQA, it can perform digital signal processing such as digital filter processing on the detection data DQA at high speed. Furthermore, since the CPU130 operates based on a program stored in the storage unit 160, it can perform calculation processing with a high degree of freedom. For example, by performing detection processing of the physical quantity by the DSP100 capable of high-speed processing, the detection value of the physical quantity can be output without delay. Furthermore, it is possible to perform fault diagnosis, temperature calculation, etc. with a high degree of freedom by the CPU130 operating based on a program. For example, by preparing two calculators of the circuit device 20 and operating them in cooperation, high-speed operation and high reliability operation are possible. One of the two calculators is the CPU130, which can be operated programmably by a program stored in the storage unit 160. For example, the CPU 130 can perform calculations of temperature correction values ​​such as temperature characteristic coefficients to be passed to the DSP 100, calculations for fault diagnosis, comparison of the detection results of the DSP 100 and the CPU 130, core calculations of a neural network, or angle calculations based on angular velocity. One of the two calculators is the DSP 100, which performs calculations of physical quantities such as angular velocity calculations, and the DSP 100 performs temperature compensation processing using the temperature correction values ​​received from the CPU 130, and various digital filter processing such as low-pass filters, notch filters, and user-defined filters. For example, the CPU 130 and the DSP 100 cooperate with each other while exchanging data. For example, the CPU 130 performs complex calculations, and the results are reflected in the DSP 100 after the results are determined, so that even if complex and highly accurate calculations are performed, it is possible to prevent the output interval of physical quantities such as angular velocity from being affected. For example, calculations for fault diagnosis can be performed without affecting the calculation of physical quantities such as angular velocity. In addition, the operating speed of the fault diagnosis itself is increased, and the probability of erroneous determination of a fault can be reduced.

[0070] 3. DSP, CPU Next, a specific example of the DSP 100 and the CPU 130 will be described. In this embodiment, the CPU 130 is provided for controlling the physical quantity transducer 10. A program for operating the CPU 130 is transferred from the non-volatile memory 164 to a volatile memory such as an SRAM, for example, when the power is turned on. The volatile memory is provided in the storage unit 160. The CPU 130 reads the program from the volatile memory and operates. The volatile memory is used as a data memory, and an initial value can be transferred to the data memory during the CPU boot operation. It is also possible to transfer the initial value to the data memory when the power is turned on by setting. The CPU 130 operates, for example, according to a program with a 16-bit instruction length set and a 5-bit opcode. For example, up to 512 instructions can be stored in the volatile memory. The CPU 130 can execute, for example, 16-bit fixed-point calculations and 32-bit floating-point calculations, and can also perform conversion calculations between fixed-point and floating-point. The operation cycle of the CPU 130 is fixed at, for example, 3 cycles, but a NOP instruction is inserted after a branch instruction. It also has a built-in stack frame and stack pointer, and supports the calling of subroutines (functions). CPU130 also supports neural network calculations, and has a built-in watchdog timer for monitoring the operation of CPU130. CPU130 also has built-in peripheral circuits, such as a crystal clock counter, a threshold judgment circuit, a PWM waveform output circuit, a GPIO control circuit, and a comparison circuit for fault diagnosis. For example, the operating frequency of DSP100 is about 12 kHz, and CPU130 operates at an operating frequency that is, for example, 1, 4, 6, or 12 times the operating frequency of DSP100.

[0071] The DSP100 is equipped with, for example, a 2nd to 4th order IIR low-pass filter, a digital calculation unit, clip processing, a 4th order notch filter, and a user-defined filter. The low-pass filter can be set to on / off, its order, and its cut-off frequency. Since the cut-off frequency of the low-pass filter varies depending on the drive frequency of the physical quantity transducer 10 such as a gyro sensor, the DSP100 has a function of automatically adjusting the filter coefficient. The notch filter can be set to on / off. The output scale and output polarity can be changed by a register. Even if the gain is lowered by the user-defined filter, a clip processing unit that clips to, for example, ±500 dps is installed in front of the user-defined filter so as not to violate the judgment. A watchdog timer is also installed.

[0072] 8 is a block diagram showing a detailed configuration example of the DSP 100 and the CPU 130. Detection data DQA of a physical quantity such as an angular velocity is input to the DSP 100 and the CPU 130 via a common filter section 190. A temperature detection signal TQ is input to the CPU 130 via a common filter section 192. The common filter sections 190 and 192 perform filtering processing such as moving average. The temperature detection signal TQ is input from a temperature sensor (not shown).

[0073] The DSP 100 includes an adder 101, a gain processor 102, a low-pass filter 104, a notch filter 106, and a user-defined filter 108. The CPU 130 includes a low-pass filter 131, a temperature correction calculator 132, an adder 136, a gain processor 137, a self-diagnosis unit 138, a neural network calculator 139, and an angle calculator 140. The temperature correction calculator 132 includes a temperature calculator 133, a zero-point corrector 134, and a sensitivity corrector 135. The programs stored in the memory 160 are programs for operating the CPU 130 as each of these components of the CPU 130. The DSP 100 and the CPU 130 are not limited to the configuration shown in FIG. 8, and various modifications are possible, such as omitting some of the components or adding other components.

[0074] The low-pass filter unit 131 of the CPU 130 performs low-pass filtering, for example, by IIR (Infinite Impulse Response), on the temperature detection signal TQ input via the common filter unit 192. The temperature calculation unit 133 of the temperature correction calculation unit 132 performs processing to calculate temperature data TDA based on the temperature detection signal TQ after the low-pass filtering.

[0075] The zero point correction unit 134 of the temperature correction calculation unit 132 determines a temperature correction value ZC for zero point correction based on the temperature data TDA. The zero point correction is also called offset correction, and is a correction for making the detected value of the angular velocity zero when the angular velocity is zero. For example, the zero point correction unit 134 approximates the output fluctuation characteristic of the angular velocity with respect to the temperature by, for example, a quartic function, and determines the temperature correction value ZC by inverting the sign of the approximation value. Then, the adder 101 of the DSP 101 performs an addition process of the temperature correction value ZC, which is the offset correction value, thereby realizing the zero point correction of the detection data DQA.

[0076] The sensitivity correction unit 135 of the temperature correction calculation unit 132 obtains a temperature correction value SC for sensitivity correction based on the temperature data TDA. Sensitivity correction is also called gain correction. For example, the sensitivity correction unit 135 approximates the output sensitivity variation characteristic of the angular velocity with respect to temperature using, for example, a quartic function, and obtains the temperature correction value SC by inverting the sign of the approximate value. Then, the gain processing unit 102 of the DSP 101 performs gain adjustment processing using the temperature correction value SC, which is the gain correction value, thereby achieving sensitivity correction of the detection data DQA.

[0077] By performing such zero point correction and sensitivity correction, a temperature compensation process is realized for the detection data DQA of the detection circuit 60. For example, a temperature compensation process is realized that suppresses fluctuations in the detection value PQ of the angular velocity due to temperature fluctuations.

[0078] The low-pass filter unit 104 of the DSP 100 performs digital low-pass filter processing on the data DPQ after the zero point correction and sensitivity correction. The filter coefficients for this low-pass filter processing are stored in the register unit 162 of the storage unit 160, for example.

[0079] Furthermore, the notch filter unit 106 performs notch filtering on the data after the low-pass filtering. The notch filtering is, for example, filtering for attenuating (removing) detuning frequency components. The filter coefficients for this notch filtering are stored in, for example, the register unit 162 of the storage unit 160.

[0080] Furthermore, the user-defined filter unit 108 performs user-defined filtering on the data after the low-pass filtering and notch filtering. For example, the user-defined filter unit 108 outputs a detection value PQ of an angular velocity, which is a physical quantity. The user-defined filtering is filtering in which the characteristics, such as a filter coefficient, can be set by the user. For example, the user-defined filtering is filtering in which the characteristics can be set via the interface circuit 180 in FIG. 2. The characteristics of the filtering are, for example, the order of the filter and the frequency characteristics. Information on the characteristics of the user-defined filtering is written and stored in the register unit 162 of the storage unit 160 via the interface circuit 180, for example.

[0081] The adder 136 of the CPU 130 performs an addition process of a temperature correction value ZC, which is an offset correction value, to perform zero point correction of the detection data DQA. The gain processor 137 of the CPU 130 performs a gain process using a temperature correction value SC, which is a gain correction value, to perform sensitivity correction of the detection data DQA.

[0082] The self-diagnosis unit 138 then performs a comparison process between the data DPQ generated by the zero point correction and sensitivity correction by the DSP 100 and the data CPQ generated by the CPU 130. Then, based on the result of the comparison process between the DSP-generated data DPQ and the CPU-generated data CPQ, the self-diagnosis unit 138 performs a fault diagnosis of the DSP 100 and the CPU 130. For example, if the DSP-generated data DPQ and the CPU-generated data CPQ match within a given judgment range (reference range), the self-diagnosis unit 138 determines that no fault has occurred, and if they do not match, it determines that a fault has occurred. The self-diagnosis unit 138 then outputs fault detection data DQD indicating the diagnosis result.

[0083] The neural network calculation unit 139 performs various calculation processes using a neural network. For example, the storage unit 160 in FIG. 2 stores a trained model using a neural network. The neural network calculation unit 139 inputs data to be processed into the trained model and outputs output data of the trained model as calculation result data of the neural network. For example, a trained model that has learned temperature compensation processing that cannot be approximated by a quartic function and temperature compensation processing of DIP in temperature characteristics is prepared. For example, a trained model that has been trained to output a temperature correction value of these temperature compensation processes in response to input of temperature data TDA is prepared and stored in the storage unit 160. The neural network calculation unit 139 then performs neural network calculation using the trained model to realize these temperature compensation processes.

[0084] The angle calculation unit 140 performs a calculation process to obtain an angle based on the detected value of the angular velocity output by the DSP 100. For example, the angle calculation unit 140 obtains the angle by performing an integration process on the detected value of the angular velocity.

[0085] As described above, in this embodiment, the CPU 130 obtains the temperature correction values ​​ZC and SC by performing a temperature correction calculation based on the temperature data TDA. For example, the zero point correction unit 134 of the CPU 130 performs a calculation process of the zero point correction based on the temperature data TDA to obtain the temperature correction value ZC for the zero point correction. Also, the sensitivity correction unit 135 of the CPU 130 performs a calculation process of the sensitivity correction based on the temperature data TDA to obtain the temperature correction value SC for the sensitivity correction. Then, the DSP 130 performs a temperature compensation process of the detection data DQA based on the temperature correction values ​​ZC and SC. For example, the addition unit 101 of the DSP 100 performs an addition process based on the temperature correction value ZC from the CPU 130 to realize the zero point correction in the temperature compensation process. Also, the gain processing unit 102 of the DSP 100 performs a gain process based on the temperature correction value SC from the CPU 130 to realize the sensitivity correction in the temperature compensation process. In this way, the CPU 130 executes the temperature correction calculation, which is a complex calculation process, to obtain an appropriate temperature correction value. Moreover, since the CPU 130 can be programmably operated based on a program stored in the storage unit 160, it has an advantage that it can realize, for example, various variations of temperature correction calculations. Meanwhile, the temperature compensation process based on the temperature correction value is executed by the DSP 100, which can operate at a higher speed than the CPU 130. This makes it possible to realize high-speed temperature compensation process for the detection data DQA of the physical quantity.

[0086] In this embodiment, the CPU 130 performs a comparison process between the DSP-generated data DPQ generated by the DSP 100 performing a temperature compensation process based on the temperature correction values ​​ZC and SC, and the CPU-generated data CPQ generated by the CPU 130 performing a temperature compensation process based on the temperature correction values ​​ZC and SC. Then, the CPU 130 performs a fault diagnosis of the DSP 100 and the CPU 130 based on the result of the comparison process. In FIG. 8, the comparison process and the fault diagnosis process are performed by the self-diagnosis unit 138. For example, when the CPU 130 determines that the DSP-generated data DPQ and the CPU-generated data CPQ match, it determines that no fault has occurred in the DSP 100 or the CPU 130. On the other hand, when the CPU 130 determines that the DSP-generated data DPQ and the CPU-generated data CPQ do not match, it determines that a fault has occurred in the DSP 100 or the CPU 130. For example, when the data DPQ generated by the DSP and the data CPQ generated by the CPU do not match, it is considered that a malfunction has occurred in the temperature compensation calculation of the temperature compensation calculation unit 132, or a malfunction has occurred in the temperature compensation process by the zero point correction or sensitivity correction of the DSP100. Therefore, in this case, it is determined that a malfunction has occurred in the DSP100 or the CPU130. In this way, by comparing the result of the temperature compensation process of the DSP100 based on the temperature compensation value calculated by the CPU130 with the result of the temperature compensation process of the CPU130 based on the temperature compensation value calculated by the CPU130, it is possible to perform self-fault diagnosis of the DSP100 and the CPU130. By performing such self-fault diagnosis, it is possible to improve the reliability, etc. of the circuit device 20 and the physical quantity detection device 5.

[0087] FIG. 9 shows an example of the hardware configuration of the CPU 130. As shown in FIG. 9, the CPU 130 includes a fetch circuit 142, an instruction decoder 144, and an arithmetic circuit 146. These circuits are provided in the core circuit of the CPU 130. The fetch circuit 142 fetches instructions of a program. For example, a program stored in the storage unit 160 describes a plurality of instructions IS1, IS2, and IS3. The fetch circuit 142 fetches each of these plurality of instructions. Then, the instruction decoder 144 decodes the instruction fetched by the fetch circuit 142. For example, the instruction decoder 144 decodes the instruction by performing a decoding process of the code of the instruction. The arithmetic circuit 146 performs an arithmetic process based on the result of the decoding by the instruction decoder 144. For example, the arithmetic circuit 146 performs an arithmetic operation such as addition or subtraction, a shift operation such as a logical shift or an arithmetic shift, and a logical operation such as AND, OR, or XOR. In this way, the instructions of the program stored in the storage unit 160 can be fetched by the fetch circuit 142, the fetched instructions can be interpreted by the instruction decoder 144, and arithmetic processing based on the interpretation result can be executed by the arithmetic circuit 146. This makes it possible to use the CPU 130, which is capable of performing various operations based on the program, to execute various processes for detecting physical quantities and the like.

[0088] FIG. 10 is a signal waveform diagram for explaining an example of the operation of the CPU 130. CKCP in FIG. 10 is an operation clock signal of the CPU 130. The CPU 130 starts processing when the trigger start signal TSC becomes active. DATME represents the data of the memory of the storage unit 160, and CKME is a clock signal for the memory. Since the bus width of the memory of the storage unit 160 is 8 bits, as shown in B1 of FIG. 10, a period of two cycles is required to read inst[15:0], which is a 16-bit instruction. After the instruction is read, an 8-bit EDC for detecting / correcting bit errors is read, and if it is determined that there is no bit error, the instruction is fetched to the CPU 130. Thereafter, as shown in B2 and B3, the CPU 130 executes three cycles of instruction decoding (Decode), ALU (Arithmetic Logic Unit) execution (Exe), and write-back (WB) for each instruction.

[0089] FIG. 11 is a state transition diagram for explaining the operation of the CPU 130. After a power-on reset (POR), the CPU 130 transitions to an idle state. The CPU 130 waits until the trigger start signal TSC in FIG. 10 is issued. When the trigger start signal TSC and the trigger boost signal TBC are issued simultaneously, the operation mode of the CPU 130 becomes a boot operation mode. When only the trigger start signal TSC is issued, the operation mode of the CPU 130 becomes a normal operation mode. The difference between the boot operation and the normal operation is that the start position of the program counter is different. In the case of the boot operation, the program counter starts from ADR:1. In the case of the normal operation, the program counter starts from 0. In either case, after the END command is issued, the CPU 130 transitions to an idle state and waits until the trigger start signal TSC is issued again. The boot operation is assumed to be executed only once, for example, after power-on. In the normal operation mode, when a branch command to a neural network is executed, the mode transitions to a neural network operation mode, and when the processing is completed, the mode returns to the normal operation mode.

[0090] FIG. 12 is an explanatory diagram of the cooperative operation of the CPU 130 and the DSP 100. In FIG. 12, CP1 to CP4 represent the processes executed by the CPU 130, and DP11 to DP32 represent the processes executed by the DSP 100. For example, the DSP 100 executes the processes DP11 to DP14 using the temperature correction value TCV1 obtained by the CPU 130 in the process CP1. For example, the temperature correction value TCV1 obtained by the CPU 130 in the process CP1 is latched in the register unit 162, and the DSP 100 executes the processes DP11 to DP14 using the latched temperature correction value TCV1. Also, the DSP 100 executes the processes DP21 to DP24 using the temperature correction value TCV2 obtained by the CPU 130 in the process CP2. For example, the temperature correction value TCV2 obtained by the CPU 130 in the process CP2 is latched in the register unit 162, and the DSP 100 executes the processes DP21 to DP24 using the latched temperature correction value TCV2. Similarly, the DSP 100 executes processes DP31 to DP32 using the temperature correction value TCV3 obtained by the CPU 130 in process CP3. In this manner, in this embodiment, the CPU 130 executes relatively complicated processes such as temperature correction calculations, and the DSP 100, which is capable of high-speed operation, executes a plurality of processes at high speed using the temperature correction value obtained by the CPU 130 through this process, thereby enabling cooperative operation.

[0091] FIG. 13 is a diagram showing an example of an execution sequence of the DSP100. idle indicates idle, and Culc indicates digital processing such as temperature compensation processing. NF1 and NF2 indicate notch filter processing, IIR1 to IIR4 indicate low-pass filter processing by IIR, Clip indicates clip processing, and UF1 and UF2 indicate user-defined filter processing. The DSP100 executes each process of the execution sequence in FIG. 13 in sequence. In this embodiment, in order to prevent problems such as a change in zero point caused by a change in current consumption due to a difference in the number of execution sequences of the DSP100, the DSP100 executes all the sequences in FIG. 13. For example, if a jump is made to a non-existent state, an error flag is set.

[0092] Next, the details of the digital filter processing performed by the DSP 100 will be described. FIG. 14 is an explanatory diagram of the low-pass filter processing performed by the low-pass filter unit 104 in FIG. 8. In the low-pass filter processing, the order and cutoff frequency can be set as filter settings. For example, as shown in FIG. 14, the order of, for example, second order, third order, or fourth order can be set by LPOD[1:0]. Also, the cutoff frequency of, for example, 1, 10, 25, 50, 100, 200, 400, 500, 1000, 2000, or 3000 Hz can be set by LPFC[3:0]. This cutoff frequency is set to a frequency corresponding to the drive frequency of the drive circuit 30, for example. Note that the default setting is a normal filter setting (for example, second order with a cutoff frequency of 100 Hz).

[0093] Also, the notch filter unit 106 performs notch filter processing to attenuate components in a given frequency band. For example, the notch filter unit 106 performs notch filter processing to attenuate detuned frequency components. For example, in a physical quantity transducer 10 such as a gyro sensor, generation of unnecessary signals of detuned frequencies caused by mechanical vibrations such as disturbances becomes a problem. For this reason, the notch filter unit 106, which is a band elimination filter, performs notch filter processing to attenuate detuned frequency components. For example, when the resonant frequency on the driving side is fd and the resonant frequency on the detection side is fs, the notch filter unit 106 performs notch filter processing to attenuate components of the detuned frequency Δf=|fd-fs|. This makes it possible to prevent deterioration of detection accuracy, etc. caused by unnecessary signals of detuned frequencies. For example, the notch filter unit 106 can select a second or fourth order as the order. The left side of FIG. 15 shows an example of a transfer function of notch filter processing when the order is second order, and the right side of FIG. 15 shows an example of a transfer function of notch filter processing when the order is fourth order. The coefficients of these transfer functions can be set by setting the registers in the register section 162 .

[0094] FIG. 16 is an explanatory diagram of the user-defined filter processing performed by the user-defined filter unit 108. In the user-defined filter processing, a maximum of four filter units (FUs) capable of processing up to the second order can be cascaded for use. This makes it possible to handle orders up to 8 (2nd order x 4 units). The number of filter units to be used in cascade connection can be set by UFU[1:0], which is the setting value of the filter unit usage number setting register. For example, as shown in FIG. 16, when UFU[1:0]=00, only one filter unit FU1 is connected. When UFU[1:0]=01, two filter units FU1 and FU2 are cascaded. When UFU[1:0]=10, three filter units FU1, FU2, and FU3 are cascaded. When UFU[1:0]=11, four filter units FU1, FU2, FU3, and FU4 are cascaded.

[0095] In this manner, in this embodiment, the DSP 100 performs low-pass filter processing in which the cutoff frequency is set according to the drive frequency of the drive circuit 30 as the digital filter processing. For example, the cutoff frequency of the low-pass filter processing shown in FIG. 14 is set according to the drive frequency of the drive circuit 30. Specifically, LPFC[3:0] in FIG. 14 is set according to the drive frequency. For example, when the drive frequency is low, the cutoff frequency is set to a low frequency, and when the drive frequency is high, the cutoff frequency is set to a high frequency. For example, in FIG. 2, the optimum drive frequency for the vibration of the vibrating pieces 11 and 12 differs according to the characteristics, material, or type of the vibrating pieces 11 and 12 of the physical quantity transducer 10. Therefore, when the optimum drive frequency is high, the cutoff frequency is set to a high frequency, and when the optimum drive frequency is low, the cutoff frequency is set to a low frequency. In this manner, the cutoff frequency of the low-pass filter processing can be set to an appropriate cutoff frequency according to the optimum drive frequency of the physical quantity transducer 10. As a result, the frequency components of the unnecessary signals that deteriorate the detection accuracy can be appropriately attenuated by the low-pass filter processing, thereby improving the detection accuracy.

[0096] Furthermore, the DSP100 performs notch filter processing as the digital filter processing. For example, as described in FIG. 15, the DSP100 performs notch filter processing to attenuate components in a given frequency band. For example, in the case where an unwanted signal of a detuned frequency is generated in a physical quantity transducer 10 such as a gyro sensor, the DSP100 performs notch filter processing to attenuate the component of the detuned frequency. In this way, the frequency component that deteriorates the detection accuracy is attenuated by notch filter processing, thereby improving the detection accuracy.

[0097] Furthermore, the DSP 100 performs a filter process with configurable characteristics as a digital filter process. For example, in the example shown in FIG. 16, the characteristics of the filter process defined by the user can be set by setting the number of filter units to be cascade-connected. The characteristics of the filter process can be set via the interface circuit 180 shown in FIG. 2. For example, the characteristics of the filter process can be set by an external processing device writing setting information for the characteristics of the filter process to the register unit 162 via the interface circuit 180. In this way, it is possible to cause the DSP 100 to perform the filter process desired by the user and to cause the circuit device 20 to output the detection value of the physical quantity that has been subjected to the desired filter process. Therefore, it is possible to provide a circuit device 20 and a physical quantity detection device 5 that can meet various user needs.

[0098] Next, the operation cycle and operation frequency of the DSP100 and the CPU130 will be described. For example, FIG. 17 is a diagram for explaining the operation of the CPU130 in a comparative example of this embodiment. In this comparative example, the DSP100 is not provided in the circuit device 20, and various processes are performed only by the CPU130. For example, in FIG. 17, the operation cycle of the CPU130 corresponds to an operation frequency of 3 kHz, and in each operation cycle, processing for angular velocity and fault diagnosis are performed. EQ1 to EQ8 in FIG. 17 represent fault diagnosis processing, and as an example, EQ1 is a fault diagnosis processing using electrostatic leakage components described in FIG. 3 and FIG. 7, and EQ2 is a fault diagnosis processing using mechanical leakage components. Also, EQ3 is a self-fault diagnosis processing using the data DPQ generated by the DSP and the data CPQ generated by the CPU described in FIG. 8. Also, EQ4 to EQ8 are other fault diagnosis processing. Then, in the last operation cycle of the CPU130, a final fault diagnosis judgment processing is performed using the results of EQ1 to EQ8. As a result, the fault diagnosis cycle becomes a cycle equivalent to 9 cycles of the CPU130, which corresponds to an operation frequency of 330 Hz.

[0099] However, in the method of this comparative example, the processing of the angular velocity is performed in an operation cycle corresponding to a slow frequency of 3 kHz, and there is a problem that high-speed processing cannot be realized. In addition, noise of a frequency corresponding to the cycle of the fault diagnosis occurs, and this noise cannot be sufficiently attenuated by low-pass filter processing, which leads to problems such as a decrease in detection accuracy. For example, when a pause period occurs during which the processing of the fault diagnosis is not performed, the current consumption during the pause period becomes less than the current consumption during the operation period other than the pause period, and noise of a frequency corresponding to the cycle of the fault diagnosis occurs. For example, FIG. 18 shows an example of noise characteristics in the comparative example. The horizontal axis is frequency, and the vertical axis is noise level. F1 in FIG. 18 is noise of a detuning frequency. In FIG. 18, noises shown in F2, F3, and F4 are generated in addition to the noise of the detuning frequency shown in F1. These noises are noises of a frequency corresponding to the cycle of the fault diagnosis. Noise of a frequency of 330 Hz corresponding to the cycle of the fault diagnosis cannot be sufficiently attenuated by low-pass filter processing with a cutoff frequency of about 500 Hz, for example, and becomes an unnecessary signal component, which reduces the detection accuracy of the physical quantity.

[0100] Fig. 19 is an explanatory diagram of the operation of the DSP100 and CPU130 in this embodiment. In Fig. 19, the DSP100 operates at an operation cycle corresponding to an operation frequency of 12 kHz, and the CPU130 operates at an operation cycle corresponding to an operation frequency of 1 kHz. The operation frequency of the DSP100, 12 kHz, is a first operation frequency, and the operation frequency of the CPU130, 1 kHz, is a second operation frequency. The second operation frequency is an operation frequency lower than the first operation frequency. The operation cycle corresponds to the reciprocal of the operation frequency, for example.

[0101] The DSP 100 performs processing on the angular velocity in each operation cycle corresponding to 12 kHz. For example, the DSP 100 performs digital signal processing such as the temperature compensation processing and digital filter processing described with reference to FIG. 8 in each operation cycle of FIG.

[0102] On the other hand, the CPU 130 executes the fault diagnosis process in an operation cycle corresponding to 1 kHz. For example, the CPU 130 executes the fault diagnosis process for EQ1 to EQ8, etc. in an operation cycle of 1 kHz.

[0103] In this way, the processing of the angular velocity can be executed at a high operating frequency of 12 kHz using the DSP 100. That is, the processing of the angular velocity can be executed at a high speed compared to the comparative example of FIG. 17, and the detected value of the angular velocity can be output.

[0104] In the comparative example of Fig. 17, the fault diagnosis cycle corresponds to 330 Hz, so there is a problem that the detection accuracy is reduced by the noise shown at F2, F3, and F3 in Fig. 18. In contrast, in the present embodiment of Fig. 19, the fault diagnosis cycle corresponds to 1 kHz, so even if noise corresponding to this fault diagnosis cycle occurs, it can be attenuated by low-pass filter processing with a cutoff frequency of, for example, about 500 Hz. Therefore, it is possible to prevent a reduction in detection accuracy caused by the fault diagnosis cycle.

[0105] FIG. 20 is an explanatory diagram of the operating frequencies of the DSP100 and the CPU130. As shown in FIG. 20, the DSP100 operates at a first operating frequency fp1. On the other hand, the CPU130 operates at a second operating frequency fp2. The first operating frequency fp1 of the DSP100 is, for example, 12 kHz. The second operating frequency fp2 of the CPU130 is, for example, 1 kHz, 2 kHz, 3 kHz, or 12 kHz, which is a frequency lower than the first operating frequency fp1. The second operating frequency fp2 of the CPU130 is a variable frequency such as 1 kHz, 2 kHz, 3 kHz, or 12 kHz. For example, the DSP100 operates based on an operating clock signal CKDP, and the CPU130 operates based on an operating clock signal CKCP. The frequency divider circuit 194 divides the operating clock signal CKDP for the DSP to output the operating clock signal CKCP for the CPU. The frequency division ratio of the frequency divider circuit 194 is set by a frequency division ratio setting value. The division ratio setting value is stored in, for example, the non-volatile memory 164 or the register unit 162 in FIG. 2. In this way, by changing the division ratio of the division circuit 194 according to the division ratio setting value, the second operating frequency fp2 of the CPU 130 can be variably set to 1 kHz, 2 kHz, 3 kHz, or 12 kHz. For example, when the CPU 130 performs many processes or the load of the processes performed by the CPU 130 is heavy, the second operating frequency fp2 is set to a high frequency. On the other hand, when the CPU 130 performs few processes or the load of the processes performed by the CPU 130 is light, the second operating frequency fp2 is set to a low frequency. This makes it possible to set the second operating frequency fp2 of the CPU 130 to an appropriate frequency according to the number of processes, the contents of the processes, or the processing load of the CPU 130.

[0106] In this embodiment, the DSP100 operates at the first operating frequency fp1, and the CPU130 operates at the second operating frequency fp2 that is equal to or lower than the first operating frequency fp1. That is, the DSP100 operates at a frequency equal to or higher than the operating frequency of the CPU130, and the CPU130 operates at a frequency equal to or lower than the operating frequency of the DSP100. In this way, processing of physical quantities such as angular velocity can be executed by the DSP100 operating at the high first operating frequency fp1. This makes it possible to output the detected value of the physical quantity with a high throughput, for example. Meanwhile, the CPU130 operates at the second operating frequency fp2 that is equal to or lower than the first operating frequency fp1 of the DSP100, thereby making it possible to prevent situations such as unnecessary power consumption in the CPU130.

[0107] In addition, the second operating frequency fp2 of the CPU 130 is variable. For example, in FIG. 20, the second operating frequency fp2 is a variable frequency such as 1 kHz, 2 kHz, 3 kHz, or 12 kHz. In this way, for example, while the DSP 100 is operated at the high-speed first operating frequency fp1, the CPU 130 can be operated at the second operating frequency fp2, which is an appropriate frequency according to the number of processes, the processing contents, or the processing load. For example, since the CPU 130 operates programmably based on a program stored in the storage unit 160, it can be operated at the second operating frequency fp2, which is an appropriate frequency according to the processing of this program. This makes it possible to provide the circuit device 20 and the physical quantity detection device 5 of various products that are compatible with various processes.

[0108] In this embodiment, when the first operating frequency is fp1, the second operating frequency is fp2, and m is an integer equal to or greater than 1, the relationship fp2=fp1 / m is established. Taking FIG. 20 as an example, when fp1=12kHz, m is set to 12, 6, 4, and 1, and fp2 is set to 1kHz, 2kHz, 3kHz, and 12kHz. In either case, fp2≦fp1, and fp2 becomes a variable frequency. In this way, for example, the CPU 130 can be operated at the second operating frequency fp2 obtained by dividing the first operating frequency fp1, and the CPU 130 can be made to execute various processes with various processing numbers, processing contents, or processing loads. For example, the CPU 130 can be operated at the operating clock signal CKCP obtained by dividing the operating clock signal CKDP of the DSP 100 by the frequency divider circuit 194, and the CPU 130 can be made to execute various processes.

[0109] As described above, the circuit device of this embodiment includes a drive circuit that drives the physical quantity transducer, and a detection circuit that detects a physical quantity based on a detection signal from the physical quantity transducer and outputs detection data of the physical quantity. The circuit device also includes a DSP that performs digital signal processing including digital filter processing on the detection data, a storage unit that stores a program in which a plurality of instructions are written, and a CPU that operates based on the program to perform at least one of a temperature correction calculation of the detection data and a fault diagnosis.

[0110] In this way, the detection data of the physical quantity in the detection circuit can be subjected to digital signal processing including digital filtering by the DSP, thereby processing the physical quantity. Meanwhile, the temperature correction calculation or fault diagnosis can be performed by the CPU operating according to a program stored in the storage unit. Therefore, it is possible to realize a circuit device or the like in which the processing of the physical quantity and the processing of the temperature correction calculation or fault diagnosis can be shared between the DSP and the CPU.

[0111] In this embodiment, the CPU may obtain a temperature correction value by performing a temperature correction calculation based on the temperature data, and the DSP may perform temperature compensation processing of the detection data based on the temperature correction value.

[0112] In this way, the CPU can execute the temperature correction calculation, which is a complex calculation process, to obtain an appropriate temperature correction value, while the DSP, which can operate at high speed, executes the temperature compensation process based on the temperature correction value, thereby realizing high-speed temperature compensation process for the detection data of physical quantities.

[0113] In addition, in this embodiment, the CPU may perform a comparison process between data generated by the DSP performing temperature compensation processing based on the temperature correction value and data generated by the CPU performing temperature compensation processing based on the temperature correction value, and perform fault diagnosis of the DSP and the CPU based on the result of the comparison process.

[0114] In this way, self-fault diagnosis of the DSP and CPU becomes possible by comparing the result of the DSP's temperature compensation processing based on the temperature compensation value calculated by the CPU with the result of the CPU's temperature compensation processing based on the temperature compensation value calculated by the CPU.

[0115] In this embodiment, the CPU may also include a fetch circuit that fetches instructions, an instruction decoder that decodes the fetched instructions, and an arithmetic circuit that performs arithmetic processing based on the results of the decoding by the instruction decoder.

[0116] In this way, the instructions of the program stored in the memory unit can be fetched by the fetch circuit, the fetched instructions can be interpreted by the instruction decoder, and arithmetic processing based on the interpretation results can be executed by the arithmetic circuit.

[0117] Furthermore, in this embodiment, the DSP may perform, as the digital filtering process, a low-pass filtering process in which a cutoff frequency is set according to the driving frequency of the driving circuit.

[0118] In this way, the cutoff frequency of the low-pass filter process can be set to an appropriate cutoff frequency according to the optimum drive frequency of the physical quantity transducer.

[0119] Furthermore, in this embodiment, the DSP may perform notch filtering, which attenuates a given frequency component, as the digital filtering process.

[0120] In this way, frequency components that deteriorate the detection accuracy are attenuated by notch filter processing, thereby making it possible to improve the detection accuracy.

[0121] In this embodiment, the DSP may perform digital filtering by setting filter characteristics via an interface circuit.

[0122] In this way, it becomes possible for the user to cause the DSP to perform the filter processing desired by the user, and to output the detection value of the physical quantity that has been subjected to the desired filter processing.

[0123] In this embodiment, the DSP may operate at a first operating frequency, and the CPU may operate at a second operating frequency that is lower than or equal to the first operating frequency.

[0124] In this way, processing of physical quantities can be performed by the DSP operating at a high first operating frequency, while the CPU can be operated at a second operating frequency that is lower than the first operating frequency of the DSP.

[0125] In this embodiment, the second operating frequency of the CPU may be variable.

[0126] In this way, it is possible to operate the DSP at a high-speed first operating frequency, while operating the CPU at a second operating frequency that is an appropriate frequency according to the number of processes, the process contents, or the processing load.

[0127] In this embodiment, when the first operating frequency is fp1, the second operating frequency is fp2, and m is an integer equal to or greater than 1, fp2=fp1 / m may be satisfied.

[0128] In this way, for example, the CPU can be operated at a second operating frequency obtained by dividing the first operating frequency, and the CPU can be made to execute various processes with different numbers of processes, process contents, or processing loads.

[0129] Moreover, the physical quantity detection device of the present embodiment may include the circuit device described above and a physical quantity transducer.

[0130] Although the present embodiment has been described in detail as above, it will be easily understood by those skilled in the art that many modifications are possible without substantially departing from the novel matters and effects of the present invention. Therefore, all such modifications are intended to be included in the scope of the present invention. For example, a term described at least once in the specification or drawings together with a different term having a broader meaning or the same meaning may be replaced with that different term anywhere in the specification or drawings. Furthermore, the configurations of the circuit device, physical quantity detection device, physical quantity transducer, etc. are not limited to those described in the present embodiment, and various modifications are possible. [Explanation of symbols]

[0131] 5...physical quantity detection device, 10...physical quantity transducer, 11, 12...vibration piece, 13, 14...driving electrode, 15, 16...detection electrode, 17...ground electrode, 18A, 18B, 18C, 18D...driving arm, 19A, 19B...detection arm, 20...circuit device, 21...base, 22A, 22B...connecting arm, 30...driving circuit, 32...amplifying circuit, 40...gain control circuit, 42...full-wave rectifying circuit, 44...integrating circuit, 50...driving signal output circuit, 52...synchronizing signal output circuit, 60...detection circuit, 61...amplifying circuit, 62, 63...Q / V conversion circuit, 64...differential amplifier circuit circuit, 65...addition circuit, 66, 67...AC amplifier circuit, 70...FLL circuit, 80...diagnostic synchronization signal generation circuit, 90, 91...synchronous detection circuit, 92, 93...filter section, 94, 95...A / D conversion circuit, 96...synchronous detection circuit, 97...filter section, 98...frequency division circuit, 99...A / D conversion circuit, 101...addition section, 102...gain processing section, 104...low-pass filter section, 106...notch filter section, 108...user-defined filter section, 130...CPU, 131...low-pass filter section, 132...temperature compensation calculation section, 133...temperature calculation section, 34...zero point correction unit, 135...sensitivity correction unit, 136...addition unit, 137...gain processing unit, 138...self-diagnosis unit, 139...neural network calculation unit, 140...angle calculation unit, 142...fetch circuit, 144...command decoder, 146...arithmetic circuit, 160...storage unit, 162...register unit, 164...non-volatile memory, 170...fault detection circuit, 180...interface circuit, 190...common filter unit, 192...common filter unit, 194...frequency division circuit, C1, C2...coupling capacitance, CK...clock signal, CKCP, CKDP...operation operation clock signal, CPQ, DPQ...data, DG...feedback signal, DQA...detection data, DQB, DQC, DQD...fault detection data, DS...drive signal, DV...signal, MCK...master clock signal, PQ...detection value, S, S1, S2...detection signal, SC, ZC...temperature correction value, SYC...synchronization signal, SYC2, SYC3...diagnosis synchronization signal, TDA...temperature data, TQ...temperature detection signal, VC...control voltage, VS1, VS2...signal, VT...threshold, f1...first frequency, f2...second frequency, fp1...first operation frequency, fp2...second operation frequency

Claims

1. A drive circuit for driving the physical quantity transducer; a detection circuit that detects a physical quantity based on a detection signal from the physical quantity transducer and outputs detection data of the physical quantity; A DSP that performs digital signal processing including digital filtering on the detection data; A storage unit that stores a program in which a plurality of instructions are written; a CPU that operates based on the program and performs at least one of a temperature correction calculation of the detection data and a fault diagnosis; A circuit device comprising:

2. 2. The circuit device according to claim 1, The CPU includes: A temperature correction value is obtained by performing the temperature correction calculation based on the temperature data; The DSP includes: A circuit device comprising: a circuit for performing temperature compensation processing on the detection data based on the temperature correction value.

3. 3. The circuit device according to claim 2, The CPU includes: A circuit device characterized in that a comparison process is performed between data generated by the DSP performing temperature compensation processing based on the temperature correction value and data generated by the CPU performing temperature compensation processing based on the temperature correction value, and fault diagnosis is performed on the DSP and the CPU based on the result of the comparison process.

4. 2. The circuit device according to claim 1, The CPU includes: a fetch circuit for fetching the instruction; an instruction decoder for decoding the fetched instructions; an arithmetic circuit for performing arithmetic processing based on a result of decoding by the instruction decoder; A circuit device comprising:

5. 2. The circuit device according to claim 1, The DSP includes: The circuit device is characterized in that, as the digital filtering process, a low-pass filtering process is performed in which a cutoff frequency is set in accordance with a driving frequency of the driving circuit.

6. 2. The circuit device according to claim 1, The DSP includes: The circuit device is characterized in that the digital filtering process includes a notch filtering process for attenuating a given frequency component.

7. 2. The circuit device according to claim 1, The DSP includes: The circuit device is characterized in that the digital filtering process is a filtering process whose characteristics can be set via an interface circuit.

8. 2. The circuit device according to claim 1, the DSP operates at a first operating frequency; The circuit device, wherein the CPU operates at a second operating frequency that is lower than the first operating frequency.

9. 9. The circuit arrangement according to claim 8, The circuit device according to claim 1, wherein the second operating frequency of the CPU is variable.

10. 9. The circuit arrangement according to claim 8, A circuit device characterized in that, when the first operating frequency is fp1, the second operating frequency is fp2, and m is an integer equal to or greater than 1, fp2=fp1 / m.

11. A circuit arrangement according to any one of claims 1 to 10; The physical quantity transducer; A physical quantity detection device comprising:

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