Switch circuit

Abstract

To accurately control a slew rate of a gate voltage of an output switching element.SOLUTION: A switch circuit includes: an output switching element (M1) provided between first and second nodes; a driver circuit (130) connected to gate wiring of the output switching element and driving wiring to which a driving voltage is applied, and for driving a gate of the output switching element according to a control signal; and a slew rate adjustment circuit (200) for adjusting a slew rate of a gate voltage in a target period in which the driver circuit increases the gate voltage of the output switching element based on the driving voltage. The slew rate adjustment circuit has: a feedback capacitor (202) inserted between the gate wiring or the driving wiring and a third node (ND3); a constant current circuit (203) for drawing constant current from the third node during the target period; and current drawing circuits (201, 204) for drawing current from the gate wiring or the driving wiring according to a voltage of the third node.SELECTED DRAWING: Figure 12

Description

[Technical field]

[0001] The present disclosure relates to a switch circuit. [Background technology]

[0002] The switch circuit has an output switching element inserted between two nodes, and turns the output switching element on or off in response to a given control signal, thereby establishing or blocking conduction between the two nodes. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2022-188429 A

[0004] [overview] When switching an output switching element from off to on, it is necessary to appropriately control the slew rate of the gate voltage of the output switching element in order to suppress rush current. There is room for improvement in the control of the slew rate.

[0005] A switch circuit according to one embodiment of the present disclosure includes an output switching element provided between a first node and a second node, a drive circuit connected to a gate wiring to which a gate of the output switching element is connected and to a drive wiring to which a drive voltage is applied, and configured to drive the gate of the output switching element in response to a control signal, and a slew rate adjustment circuit configured to adjust the slew rate of the gate voltage of the output switching element during a target period in which the drive circuit increases the gate voltage of the output switching element based on the drive voltage to switch the output switching element from OFF to ON, wherein the slew rate adjustment circuit has a feedback capacitor inserted between the gate wiring or the drive wiring and a third node, a constant current circuit configured to draw a constant current from the third node during the target period, and a current sink circuit configured to draw a current from the gate wiring or the drive wiring in response to the voltage of the third node. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic configuration diagram of a semiconductor device according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 is an external perspective view of the semiconductor device according to the embodiment of the present disclosure. [Diagram 3] FIG. 3 is a configuration diagram of a switch circuit according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is a timing chart of the switch circuit according to the embodiment of the present disclosure. [Diagram 5] FIG. 5 is a diagram illustrating the charging and discharging currents to the gate of the output transistor according to an embodiment of the present disclosure. [Figure 6] FIG. 6 is a configuration diagram of a switch circuit according to a reference example. [Figure 7] FIG. 7 is a timing chart of the switch circuit according to the reference example. [Figure 8] FIG. 8 is a configuration diagram of a ramp circuit using a DAC according to a reference example. [Figure 9]FIG. 9 is a diagram showing a change in an ideal output voltage (ramp signal) of a DAC according to a reference example. [Figure 10] FIG. 10 is a diagram showing a change in the output voltage (ramp signal) of a non-ideal DAC according to a reference example. [Figure 11] FIG. 11 is a configuration diagram of a lamp circuit using a constant current circuit according to a reference example. [Figure 12] FIG. 12 is a configuration diagram of a switch circuit according to a first example of an embodiment of the present disclosure. [Figure 13] FIG. 13 is a timing chart of a switch circuit according to a first example of an embodiment of the present disclosure. [Figure 14] FIG. 14 is a configuration diagram of a switch circuit according to a second embodiment of the present disclosure. [Figure 15] FIG. 15 is a diagram illustrating the operation of a switched capacitor circuit according to a second example of an embodiment of the present disclosure. [Figure 16] FIG. 16 is a diagram illustrating the operation of a switched capacitor circuit according to a second example of an embodiment of the present disclosure. [Figure 17] FIG. 17 is a configuration diagram of a switch circuit according to a third embodiment of the present disclosure. [Figure 18] FIG. 18 is a configuration diagram of a switch circuit according to a fourth embodiment of the present disclosure. [Figure 19] FIG. 19 is a diagram showing a partial internal configuration of a driver according to a fifth embodiment of the present disclosure. [Figure 20] FIG. 20 is a configuration diagram of a switch circuit according to a fifth embodiment of the present disclosure. [Figure 21] FIG. 21 is a configuration diagram of a switch circuit according to a fifth embodiment of the present disclosure. [Figure 22] FIG. 22 is a configuration diagram of a switch circuit according to a fifth embodiment of the present disclosure. [Diagram 23] FIG. 23 is a configuration diagram of a switch circuit according to a fifth embodiment of the present disclosure. [Figure 24] FIG. 24 is a configuration diagram of a switch circuit according to a fifth embodiment of the present disclosure. [Diagram 25] FIG. 25 is a configuration diagram of a switch circuit according to a fifth embodiment of the present disclosure.

[0007] [Detailed Description] Hereinafter, examples of embodiments of the present disclosure will be specifically described with reference to the drawings. In each of the drawings, the same parts are given the same reference numerals, and duplicated descriptions of the same parts are generally omitted. In this specification, for the sake of simplicity, by writing a symbol or code referring to information, signal, physical quantity, functional part, circuit, element, or part, the name of the information, signal, physical quantity, functional part, circuit, element, or part corresponding to the symbol or code may be omitted or abbreviated.

[0008] First, some terms used in the description of the embodiments of the present disclosure will be explained. Ground refers to a reference conductive part having a reference potential of 0V (zero volts), or refers to the potential of 0V itself. The reference conductive part may be formed using a conductor such as a metal. The potential of 0V may also be called ground potential. In the embodiments of the present disclosure, a voltage shown without a particular reference represents a potential seen from ground.

[0009] A level refers to a level of electric potential, and a high level has a higher electric potential than a low level for any signal or voltage of interest.

[0010] For any transistor configured as a FET (field effect transistor) such as a MOSFET, the on-state refers to the state where conduction exists between the drain and source of the transistor, and the off-state refers to the state where non-conduction (cut-off state) exists between the drain and source of the transistor. The same applies to transistors not classified as FETs. Unless otherwise specified, a MOSFET is understood to be an enhancement-mode MOSFET. MOSFET is an abbreviation of "metal-oxide-semiconductor field-effect transistor". Also, unless otherwise specified, in any MOSFET, the back gate may be considered short-circuited to the source.

[0011] Hereinafter, for any transistor, the on-state and off-state may also be simply expressed as on and off. Also, for any transistor, the period during which the transistor is in the on-state is referred to as the on-period, and the period during which the transistor is in the off-state is referred to as the off-period. The same applies to any switch. Any switch can be formed using one or more FETs (field effect transistors).

[0012] For any signal taking a high-level or low-level signal level, the period during which the level of the signal is high is referred to as the high-level period, and the period during which the level of the signal is low is referred to as the low-level period. The same applies to any voltage taking a high-level or low-level voltage level.

[0013] Unless otherwise specified, the connection between a plurality of parts forming a circuit, such as any circuit element, wiring, node, etc., may be understood to refer to an electrical connection.

[0014] When any two voltages to be compared are voltage v1 and v2, "v1>v2" represents that voltage v1 is higher than voltage v2, and "v1<v2" represents that voltage v1 is lower than voltage v2. The same applies to other expressions including physical quantities other than voltage.

[0015] FIG. 1 is a schematic diagram of a semiconductor device 1 according to an embodiment of the present disclosure. FIG. 2 is an external perspective view of the semiconductor device 1. The semiconductor device 1 is an electronic component including a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a housing CS (package) for accommodating the semiconductor chip, and a plurality of external terminals exposed from the housing CS to the outside of the semiconductor device 1. The semiconductor device 1 is formed by sealing the semiconductor chip in a housing CS made of resin. Note that the number of external terminals of the semiconductor device 1 and the type of the housing CS of the semiconductor device 1 shown in FIG. 2 are merely examples, and can be designed arbitrarily. In FIG. 1, an input terminal IN, an output terminal OUT, a ground terminal GND, and an enable terminal EN are shown as some or all of the external terminals provided in the semiconductor device 1. External terminals other than these may also be provided in the semiconductor device 1.

[0016] Incidentally, the wiring provided outside the semiconductor device 1 is particularly referred to as external wiring, and the wiring provided inside the semiconductor device 1 is particularly referred to as internal wiring.

[0017] An input voltage V is applied to an input terminal IN through an external wiring from a voltage source VS provided outside the semiconductor device 1. IN The input voltage V IN has a positive voltage value. OUT An output capacitor C OUT The first end of the output capacitor C OUT The second end of the output terminal OUT is connected to ground. OUT Therefore, the output capacitor C OUT The output voltage V OUT are added. Two or more external terminals functioning as input terminals IN may be provided in the semiconductor device 1. Three or more external terminals functioning as output terminals OUT may be provided in the semiconductor device 1. The ground terminal GND is connected to the ground.

[0018] The semiconductor device 1 includes, as main circuits, a switch circuit 10, an internal power supply circuit 20, and a protection circuit 30. An enable signal S is sent from an external circuit (not shown) to an enable terminal EN of the semiconductor device 1. EN An enable signal S EN is input to the switch circuit 10.

[0019] The switch circuit 10 receives an enable signal S EN When the input terminal IN and the output terminal OUT are connected, in the steady state, the input voltage V IN An output voltage V having substantially the same voltage value as OUT appears at the output terminal OUT, and the output voltage V OUT is supplied to an arbitrary load (not shown) connected to the output terminal OUT. After the input terminal IN and the output terminal OUT are connected, if the input terminal IN and the output terminal OUT are cut off, the output voltage V OUT decreases towards 0V.

[0020] The internal power supply circuit 20 is connected to the input terminal IN via the input voltage V IN The protection circuit 30 detects various abnormalities that may occur in the semiconductor device 1. The detection results of the protection circuit 30 are transmitted to the switch circuit 10. The switch circuit 10 and the protection circuit 30 are driven by any one of the internal power supply voltages generated by the internal power supply circuit 20.

[0021] In this way, the semiconductor device 1 functions as a switch device for establishing or breaking electrical continuity between the input terminal IN and the output terminal OUT. The semiconductor device 1 may be a device classified as an electronic fuse, or may be a high-side switch device inserted into any power bus. The semiconductor device 1 may be used in applications where hot swapping (live insertion and removal) is anticipated. Here, attention is focused on one switch circuit 10, but multiple switch circuits 10 may be provided within the semiconductor device 1.

[0022] Enable signal S ENThe enable signal S has a value of "1" or "0". EN When the enable signal S has a value of "0", the switch circuit 10 cuts off the connection between the input terminal IN and the output terminal OUT. EN When the enable signal S has a value of "1", the switch circuit 10, in principle, brings the input terminal IN and the output terminal OUT into conduction. EN Even if the value of V has a value of “1”, when a specific abnormality is detected in the protection circuit 30, the switch circuit 10 cuts off the connection between the input terminal IN and the output terminal OUT. IN These include an overvoltage abnormality where the voltage exceeds a predetermined threshold voltage, an overcurrent abnormality where the current flowing between the input terminal IN and the output terminal OUT exceeds a predetermined threshold current, and a high temperature abnormality where the temperature at the temperature detection position within the semiconductor device 1 exceeds a predetermined temperature.

[0023] 3 shows the configuration of the switch circuit 10. The switch circuit 10 includes an output transistor M1 which is an output switching element, a control circuit 110, a level shifter 120, a driver 130 which is a drive circuit, a charge pump circuit 140, and a slew rate adjustment circuit 150. The output transistor M1 is an N-channel MOSFET. In FIG. 3, C P represents the parasitic capacitance added to the gate of the output transistor M1.

[0024] The node ND1 is connected to the input terminal IN. Therefore, the voltage at the node ND1 is equal to the input voltage V IN The node ND2 is connected to the output terminal OUT. Therefore, the voltage at the node ND2 is equal to the output voltage V OUT The nodes ND1 and ND2 may be interpreted as the input terminal IN and the output terminal OUT, respectively. The output transistor M1 is provided between the nodes ND1 and ND2. Specifically, the drain of the output transistor M1 is connected to the node ND1, and the input voltage V INThe source of the output transistor M1 is connected to the node ND2. Therefore, when the output transistor M1 is on, the input terminal IN and the output terminal OUT are electrically connected, and when the output transistor M1 is off, the input terminal IN and the output terminal OUT are electrically disconnected.

[0025] The wirings WR1 to WR3 are internal wirings. The voltage on the wiring WR1 is the driving voltage V BST That is, the wiring WR1 is driven by the driving voltage V BST The wiring WR2 is connected to the node ND2. Therefore, the voltage at the wiring WR2 is the output voltage V OUT The wiring WR3 is a gate wiring connected to the gate of the output transistor M1. The voltage on the wiring WR3 is the gate voltage V G and corresponds to a drive signal for driving the output transistor M1.

[0026] The control circuit 110 is a logic circuit that operates with the internal power supply voltage VDD as a positive power supply voltage and the voltage VSS as a negative power supply voltage. The internal power supply voltage VDD is one of the internal power supply voltages generated by the internal power supply circuit 20, and has a positive DC voltage value. The voltage VSS is the voltage at the reference potential end. The reference potential end is connected to the ground terminal GND. Therefore, the reference potential end is equivalent to the ground and has a voltage of 0V. An enable signal S EN Although not shown in the figure, signals indicating the results of detection of various abnormalities are also input from the protection circuit 30 to the control circuit 110.

[0027] When the specific abnormality described above is not detected, the control circuit 110 outputs the enable signal S EN has a value of "1", it outputs a high-level control signal CNT1 and an enable signal S EN When the enable signal S has a value of "0", the control signal CNT1 is output at a low level. When a signal indicating that a specific abnormality has been detected is supplied to the control signal 110, the control signal 110 is ENIn the following, it is assumed that a specific abnormality will not be detected unless there is a particular need.

[0028] The control signal CNT1 is a signal (original control signal) that specifies the state of the output transistor M1. A high-level control signal CNT1 specifies that the output transistor M1 is set to an on state, and a low-level control signal CNT1 specifies that the output transistor M1 is set to an off state. The high-level control signal CNT1 has substantially the potential of the internal power supply voltage VDD, and the low-level control signal CNT1 has substantially the ground potential (the potential of the voltage VSS).

[0029] A control signal CNT1 is input to the level shifter 120. The level shifter 120 shifts the level of the control signal CNT1 to a level within the voltage range of the input signal to the driver 130, and supplies the shifted control signal to the driver 130. The shifted control signal is called a shift control signal CNT2. When the control signal CNT1 has a high level, the shift control signal CNT2 also has a high level, and when the control signal CNT1 has a low level, the shift control signal CNT2 also has a low level. However, the high-level shift control signal CNT2 has a different potential from the high-level control signal CNT1, and the low-level shift control signal CNT2 has a different potential from the low-level control signal CNT1. Since the configuration of the level shifter itself is well known, illustration and description of its internal configuration will be omitted.

[0030] The driver 130 is connected to the wirings WR1 to WR3. A driving voltage V BST and the output voltage V OUT (In other words, the source voltage of the output transistor M1) is supplied to the driver 130. The driver 130 is also connected to the level shifter 120 and receives a shift control signal CNT2 from the level shifter 120. The driver 130 receives a driving voltage V BST is the positive power supply voltage and the output voltage V OUTThe driver 130 is a buffer circuit that drives the shift control signal CNT2 by applying a gate voltage V G is supplied to the gate of the output transistor M1 through the wiring WR3, thereby driving the output transistor M1 (in other words, driving the gate of the output transistor M1). By driving the output transistor M1, the output transistor M1 is turned on or off.

[0031] When the shift control signal CNT2 is at a low level, the driver 130 supplies a low-level gate voltage V G The output transistor M1 is set to the off state by supplying a low-level gate voltage V G is the output voltage V OUT (i.e., a voltage based on the source voltage of the output transistor M1), which is substantially the output voltage V OUT The output voltage V OUT The low-level gate voltage V G is supplied to the output transistor M1, the gate-source voltage of the output transistor M1 is less than the gate threshold voltage of the output transistor M1.

[0032] When the shift control signal CNT2 is at a high level, the driver 130 outputs a high-level gate voltage V G The output transistor M1 is set to the on state by supplying a high-level gate voltage V G is the driving voltage V BST A voltage based on the driving voltage V BST and the driving voltage V BST However, in reality, as shown in FIG. 4, after the shift control signal CNT2 is switched from low level to high level, the gate voltage V G is the output voltage V OUT from the level of the voltage V GMAX Further explanation regarding FIG. 4 is provided below.

[0033] The charge pump circuit 140 is an example of a drive voltage generating circuit that operates or does not operate in response to a control signal CNT1 from the control circuit 110. The control signal CNT1 is input to the charge pump circuit 140. During a high-level period of the control signal CNT1, the charge pump circuit 140 is in an operating state, and a drive voltage V for turning on the output transistor M1 is supplied to the wiring WR1. BST The charge pump circuit 140 is composed of a combination of an oscillator circuit, a capacitor, and a diode. Here, the charge pump circuit 140 is composed of an oscillator circuit 141, a capacitor 142, and diodes 143 and 144, but the charge pump circuit 140 may have two or more capacitors and three or more diodes.

[0034] When the charge pump circuit 140 is in an operating state, the charge pump circuit 140 supplies charges to the wiring WR1 by a charge pump operation using the oscillation operation of the oscillation circuit 141, thereby increasing the potential of the wiring WR1 based on the potential of the wiring WR2. As a result, the voltage (V OUT ) is the driving voltage V BST A charge is generated on the wiring WR1 as a charge pump circuit 140. The charge pump circuit 140 stops during a low level period of the control signal CNT1. The charge pump circuit 140 stopping means that the charge pump circuit 140 is in a stopped state. When the charge pump circuit 140 is in a stopped state, the oscillation circuit 141 does not oscillate, and no charge is supplied from the charge pump circuit 140 to the wiring WR1.

[0035] More specifically, a control signal CNT1 is input to an input terminal of the oscillation circuit 141, and an output terminal of the oscillation circuit 141 is connected to a first terminal of the capacitor 142. The oscillation circuit 141 supplies a square wave signal to the first terminal of the capacitor 141 by performing an oscillation operation during a high-level period of the control signal CNT1. The square wave signal alternates between a low level and a high level. For example, a low-level square wave signal has a potential of the voltage VSS, and a high-level square wave signal has a potential of the internal power supply voltage VDD. The oscillation circuit 141 does not perform an oscillation operation during a low-level period of the control signal CNT1, and keeps the first terminal of the capacitor 142 at the potential of the voltage VSS. The second terminal of the capacitor 142 is connected to the cathode of the diode 143 and the anode of the diode 144. The anode of the diode 143 is connected to the wiring WR2, and the cathode of the diode 144 is connected to the wiring WR1.

[0036] Therefore, when the control signal CNT1 switches from a low level to a high level, the charge pump circuit 140 supplies electric charge to the wiring WR1, and the driving voltage V BST rises, and the driving voltage V BST is the voltage of wire WR2 (i.e. the output voltage V OUT ) increases by a certain voltage, the driving voltage V BST After that, when the control signal CNT1 switches from high level to low level, the driving voltage V BST drops to the voltage level of the wire WR2.

[0037] A control signal CNT1 is input to the slew rate adjustment circuit 150. The slew rate adjustment circuit 150 is also connected to the wiring WR3 (i.e., connected to the gate of the output transistor M1), and a gate voltage V G The slew rate control is performed to adjust (in other words, control) the slew rate of the input signal.

[0038] The slew rate control will be described with reference to FIG. 4. FIG. 4 is a timing chart of the switch circuit 10, focusing on the slew rate control. The slew rate control described here is performed by controlling the gate voltage V GThis is the slew rate control when increasing the output voltage V OUT In response to the change of the control signal CNT1 to a high level, the gate voltage V G If the voltage rises sharply, the output capacitor C connected from the input terminal IN (node ​​ND1) to the output terminal OUT (ND2) OUT A large rush current flows to the output transistor M1. A large rush current is not good for the output transistor M1 and the components connected to the output transistor M1. The gate voltage V G The rush current can be reduced by controlling the slew rate (soft start control) when increasing the input.

[0039] FIG. 4 shows the control signals CNT1 and CNT2 and the voltage V G and V OUT As time progresses, times T1, T2, T3, and T4 arrive in this order. Before time T1, the control signals CNT1 and CNT2 are maintained at a low level, and the output voltage V OUT has 0V. Before time T1, the gate voltage V G is kept low, and the output voltage V OUT Therefore, before time T1, the gate voltage V G and the output voltage V OUT The waveforms overlap.

[0040] At time T1, the control signal CNT1 switches from low level to high level, and in response to this switching, the shift control signal CNT2 also switches from low level to high level. Here, the propagation delay in the level shifter 120 is ignored as it is sufficiently small.

[0041] In response to the control signal CNT1 switching to a high level, the charge pump circuit 140 starts supplying charges to the wiring WR1. On the other hand, in response to the shift control signal CNT2 switching to a high level, the driver 130 reduces the voltage (V BST ) based on the gate voltage V G The voltage of WR1 (VBST The driver 130 has a switching element provided between WR1 and WR3, and turns on the switching element during the high-level period of the shift control signal CNT2 to increase the voltage (V BST ) is applied to the wiring WR3. Therefore, during the high level period of the shift control signal CNT2, the gate voltage V G is the driving voltage V BST substantially coincides with

[0042] 5 shows currents input to and output from the wiring WR3 during a high-level period of the control signal CNT1. The current I1 is a current supplied from the wiring WR1 to the wiring WR3 via the driver 130. The current I2 is a current drawn from the wiring WR3 toward the slew rate adjustment circuit 150. The current I1 is a current that flows through the parasitic capacitance C P is the charging current to charge the gate voltage V G The current I2 increases the parasitic capacitance C P is the discharge current that discharges the gate voltage V G The currents I1 and I2 decrease as the gate voltage V G This occurs during the transient response period until the gate voltage V G After increases sufficiently (after time T4), currents I1 and I2 may become zero or substantially zero.

[0043] Drive voltage V from time T1 BST In conjunction with the rise in gate voltage V G is the voltage of wire WR2 (V OUT ) and then rises. The gate threshold voltage of the output transistor M1 is represented by the symbol “V GTH The gate voltage V G At time T2 during the rise of the gate voltage V G is the voltage of wire WR2 (V OUT ) the gate threshold voltage V of the output transistor M1 GTHTherefore, from time T2, a current starts to flow from node ND1 to node ND2 via output transistor M1, and the output voltage V OUT starts to rise from 0V.

[0044] Then, at time T3, the output voltage V OUT is effectively the input voltage V IN When the output voltage V OUT The rise in the differential voltage (V G -V OUT ) is approximately the gate threshold voltage V GTH After time T3, the difference voltage (V G -V OUT ) is the gate threshold voltage V GTH As the gate voltage V G The gate voltage V G The rise in continues until time T4, at which point the gate voltage V G is the voltage V GMAX The voltage V GMAX is the voltage of the wiring WR2 at time T4 (V OUT ) voltage V CPUP Voltage V CPUP is a positive voltage amount that depends on the characteristics of the charge pump circuit 140. CPUP is the gate threshold voltage V of the output transistor M1 GTH Greater than.

[0045] To switch the output transistor M1 from off to on, the driver 130 applies a gate voltage V G For convenience, the period during which the gate voltage V is increased is hereinafter referred to as the target period. The period from time T1 to time T4 corresponds to the target period (see FIG. 4). The target period is included in the high-level period of the control signal CNT1 (and therefore the high-level period of the shift control signal CNT2). During the target period, the slew rate adjustment circuit 150 increases the gate voltage V G Adjust the slew rate of the

[0046] <<Reference example>> A switch circuit 10ref according to a reference example is shown in Fig. 6. The switch circuit 10ref is provided with a slew rate adjustment circuit 910. The slew rate adjustment circuit 910 has a series circuit of a transistor 911 and a resistor 912, a series circuit of voltage dividing resistors 913 and 914, a ramp circuit 915, and a differential amplifier 916. The series circuit of the transistor 911 and the resistor 912 is inserted between the wiring WR3 and the reference potential end. The series circuit of the voltage dividing resistors 913 and 914 is inserted between the node ND2 and the reference potential end, and an output voltage V OUT Voltage V DIV The ramp circuit 915 generates a ramp signal SS that gradually and monotonically rises from the potential of the voltage VSS (0V) to a positive predetermined voltage when the control signal CNT1 transitions from a low level to a high level. DIV The gate potential of the transistor 911 is controlled so that the voltage of the ramp signal SS coincides with that of the ramp signal SS.

[0047] 7 shows a signal waveform in the switch circuit 10ref. In the slew rate adjustment circuit 910, the drain current of the transistor 911 corresponds to the discharge current I2 in FIG. 5. The difference between the charge current I1 from the charge pump circuit 140 and the drain current (I2) of the transistor 911 causes a parasitic capacitance C P The gate voltage V G and the output voltage V OUT is rising.

[0048] The slew rate control by the slew rate adjustment circuit 910 is performed based on the input voltage V IN When the input voltage V is high, problems in circuit design are likely to occur. This will be explained. The slew rate adjustment circuit 910 operates based on an internal power supply voltage generated within a semiconductor device having the slew rate adjustment circuit 910. The internal power supply voltage that drives the slew rate adjustment circuit 910 can be 1.8V, 3.3V, or 5.0V, but let us assume an internal power supply voltage of 1.8V. In this case, when the input voltage V INWhen is 30V, the output voltage V OUT also reaches 30V, but the output voltage V OUT To monitor the output voltage V OUT By dividing the voltage, the voltage V DIV In addition, due to the configuration of the differential amplifier 916, the internal power supply voltage of 1.8V to approximately -0.8V is outside the normal operating range, so in reality, the voltage V DIV In other words, the output voltage V OUT It is necessary to divide the voltage to 1 / 30 or less.

[0049] Output voltage V OUT When compressing the information to 1 / 30, the slew rate of the ramp signal SS also becomes the original slew rate ("V DIV =V OUT This is equivalent to making the slew rate of the ramp signal SS 30 times slower than in the case where slew rate compression is not required.

[0050] A ramp circuit 915 can be configured using a general DAC (digital-analog converter) as shown in FIG. 8. In this case, the output voltage of the DAC becomes the ramp signal SS. When using a DAC, a first method for easing the slew rate is to increase the number of bits of the DAC and reduce the amount of change in the ramp signal SS per step. A second method for easing the slew rate is to lengthen the switching period of the input code to the DAC. However, an increase in the switching period leads to an increase in the amount of voltage change per step (amount of change in the output voltage of the DAC). If the amount of voltage change per step increases, the smoothness of the change in the ramp signal SS is lost, and the rush current at the time of voltage switching increases.

[0051] When the number of bits of the DAC is increased as in the first method, there is a concern that the linearity may deteriorate due to the variation in voltage for each bit. In particular, in an R-2R ladder type DAC, if a mismatch occurs between the resistance value of the higher bits and the resistance value of the lower bits, the output voltage of the DAC may not increase monotonically or may rise sharply and significantly at the timing when the value of many bits in the input code to the DAC changes (for example, the timing when the input code changes from "01111111" to "10000000"). FIG. 9 shows the change in the output voltage (ramp signal SS) of an ideal DAC, and FIG. 10 shows the change in the output voltage (ramp signal SS) of a non-ideal DAC. In FIG. 10, there is a timing when the output voltage (ramp signal SS) of the DAC does not increase monotonically, and at that timing, the output voltage V OUT In Fig. 10, there is a timing when the DAC output voltage (ramp signal SS) rises sharply, and a large rush current occurs at that timing. Using a high-precision DAC can eliminate or reduce these concerns, but increasing the precision of the DAC leads to an increase in the circuit area or circuit current.

[0052] Alternatively, as shown in FIG. 11, there is a method of generating the ramp signal SS using a constant current circuit and a capacitor. In this case, however, in order to keep the slew rate of the ramp signal SS low, it is necessary to reduce the constant current value or increase the capacitance value of the capacitor. However, when the constant current value is reduced, the variation of the constant current circuit is likely to increase. Also, a large resistor is required to generate a small current. On the other hand, increasing the capacitance of the capacitor leads to an increase in the size of the capacitor, making it difficult to incorporate it into a semiconductor device. Below, several embodiments that take these circumstances into consideration are shown.

[0053] <<First Example>> A first embodiment will be described. Fig. 12 shows the configuration of a switch circuit 10 according to the first embodiment. The switch circuit 10 according to the first embodiment has a slew rate adjustment circuit 200 as the slew rate adjustment circuit 150 (see Fig. 3). The slew rate adjustment circuit 200 includes an adjustment transistor 201, a feedback capacitor 202, a constant current circuit 203, a differential amplifier 204, a switch 205, and a resistor 206. The adjustment transistor 201 is an N-channel MOSFET.

[0054] The drain of the adjustment transistor 202 and a first end of the feedback capacitor 202 are connected to the wiring WR3 (and thus to the gate of the output transistor M1). The second end of the feedback capacitor 202 is connected to a node ND3. The voltage at the node ND3 is referred to as a feedback voltage V FB The non-inverting input terminal of the differential amplifier 204 is connected to the node ND3, and the feedback voltage V FB The inverting input terminal of the differential amplifier 204 receives a predetermined reference voltage V REF is connected to the application terminal 207, and the reference voltage V REF The reference voltage V REF Here, it is the internal power supply voltage VDD. However, the reference voltage V REF may be a positive DC voltage different from the internal power supply voltage VDD.

[0055] The differential amplifier 204 operates with the internal power supply voltage VDD or an internal power supply voltage higher than the internal power supply voltage VDD as the positive power supply voltage and with the voltage VSS as the negative power supply voltage. The output terminal of the differential amplifier 204 is connected to the gate of the adjustment transistor 201. The source of the adjustment transistor 201 is connected to the reference potential end via a resistor 206. As described above, the reference potential end has a potential of 0V.

[0056] The constant current circuit 203 is provided between the node ND3 and the reference potential end. The constant current circuit 203 supplies a constant current I REF It operates so that a constant current I REFhas a predetermined constant current value. However, the constant current circuit 203 does not have the ability to lower the potential of the node ND3 to a negative potential. Therefore, when the potential of the node ND3 is lowered to 0V, the constant current I REF does not occur. The constant current circuit 203 supplies a constant current I having a constant current value from the node ND3 to the reference potential terminal at least during the target period (between times T1 and T4). REF Pull in.

[0057] Switch 205 is connected to the reference voltage V REF That is, the first terminal of the switch 205 is connected to the reference voltage V REF The second end of the switch 205 is connected to the application end 207 of the voltage source 201, and the second end of the switch 205 is connected to the node ND3.

[0058] The differential amplifier 204 is connected to the feedback voltage V FB is the reference voltage V REF (here, the internal power supply voltage VDD) and controls the gate potential of the adjustment transistor 201 depending on the comparison result. A drain current may flow through the adjustment transistor 201 depending on the gate potential of the adjustment transistor 201. The drain current of the adjustment transistor 201 is a current that flows from the gate of the output transistor M1 through the adjustment transistor 201, and is included in the above-mentioned discharge current I2 (see FIG. 5).

[0059] During the target period, the differential amplifier 204 FB is the reference voltage V REF When the feedback voltage V FB is the reference voltage V REF When the gate potential of the adjustment transistor 201 is lower, the drain current of the adjustment transistor 201 is reduced.

[0060] The operation of the switch circuit 10 of Fig. 12 will be further described with reference to Fig. 13. Fig. 13 is a timing chart of the switch circuit 10 according to the first embodiment, and shows a difference between the feedback voltage V FBThe waveforms of the control signals CNT1 and CNT2 and the voltage V G and V OUT The relationship between the reference voltage V and the reference voltage V is as described above with reference to FIG. 4. A control signal CNT1 is supplied to the switch 205. The switch 205 is set to ON during a low level period of the control signal CNT1, and the switch 205 is set to OFF during a high level period of the control signal CNT1. When the switch 205 is ON, the reference voltage V REF The application terminal 207 of the reference voltage V is connected to the node ND3 through the switch 205. That is, the slew rate adjustment circuit 200 keeps the switch 205 in the on state during the low level period of the control signal CNT1 (i.e., before the target period) to apply the reference voltage V REF to the node ND3, and keeps the switch 205 in the off state during the high-level period of the control signal CNT1 (hence during the target period). When the switch 205 is off, the reference voltage V REF The connection between the application terminal 207 and the node ND3 is cut off.

[0061] First, consider a first hypothetical configuration in which the slew rate adjustment circuit 200 is removed from the switch circuit 10 in FIG. 12. In the first hypothetical configuration, when the control signal CNT1 switches from a low level to a high level, the parasitic capacitances of the wirings WR1 and WR3 are quickly charged by the current capacity of the charge pump circuit 140, and the gate voltage V G rises rapidly, and the output voltage V OUT also rises rapidly.

[0062] Next, consider a second hypothetical configuration in which only the constant current circuit 203 is removed from the switch circuit 10 in FIG. 12. When the switch 205 is off in the second hypothetical configuration, the gate voltage V G When increases, the feedback voltage V FB Then, the current drawn from the gate of the output transistor M1 through the adjustment transistor 201 increases, so the gate voltage V G Therefore, in the second hypothetical configuration, the output voltage V OUT is not rising.

[0063] In the actual switch circuit 10 of FIG. 12, a constant current I REF By pulling out the output voltage V OUT gradually increases.

[0064] Between times T1 and T4, the driver 130 is connected to the parasitic capacitance C P A current I1 is provided to charge the parasitic capacitance C P A current I2 discharging the constant current I is drawn from the gate of the output transistor M1 to the slew rate adjustment circuit 200 (see FIG. 5). REF The feedback voltage V FB When the gate potential of the adjustment transistor 201 decreases, the drain current of the adjustment transistor 201 is suppressed, and the gate voltage V G and the output voltage V OUT The gate voltage V G The feedback voltage V FB The feedback voltage V FB The increase in the drain current of the adjustment transistor 201 increases the constant current I REF The feedback voltage V FB The gate voltage V G and the output voltage V OUT The rise in the gate voltage V G increases gradually and monotonically.

[0065] Here, “V OUT =V G -V GS " V GS represents the gate-source voltage of the output transistor M1. Therefore, the output voltage V OUT During the period when V rises (i.e., between times T2 and T3), the output voltage V OUT The slew rate of the gate voltage V G These slew rates are approximately equal to the values ​​(IREF / C FB ), and the value (I REF / C FB ), where C FB represents the capacitance value of the feedback capacitor 202.

[0066] The adjustment transistor 201 and the differential amplifier 204 adjust the voltage of the node ND3 (V FB ) from the gate of the output transistor M1. The current drawn by the current draw circuit is included in the discharge current I2. Meanwhile, the driver 130 supplies a charging current I1 to the gate of the output transistor M1 during the target period. Therefore, during the target period, the gate voltage V G increases.

[0067] Gate voltage V G During the rise period of the feedback voltage V FB is the reference voltage V REF At time T4, the gate voltage V G After the rise in the gate voltage V G The effect of raising the potential of node ND3 due to the rise in REF This causes the voltage of node ND3 (V FB ) is the reference voltage V REF It will continue to decline. FB <V REF When the voltage of the node ND3 (V FB ) drops to 0V, the constant current I REF will no longer flow.

[0068] In the switch circuit 10ref according to the reference example (see FIG. 6), the output voltage V OUT When monitoring the information of the output voltage V OUT The information is compressed to a voltage level that can be handled by the internal circuit and then fed back to the differential amplifier 916. In contrast, in the switch circuit 10 of FIG.OUT The gate voltage V G is fed back to the differential amplifier 204 with an AC gain of 1 by capacitive coupling. In other words, no signal compression is required. IN Even when the output voltage V OUT A temporary voltage drop and a discontinuous rise do not occur during the rise process of the voltage. Since there is no need for signal compression, the feedback capacitor 202 can be small in size, and a large-capacity capacitor as required in the example of FIG.

[0069] <<Second Example>> The second embodiment will be described. The second embodiment and the third to sixth embodiments described later are based on the first embodiment, and for matters not specifically mentioned in the second to sixth embodiments, the description of the first embodiment also applies to the second to sixth embodiments unless there is a contradiction. However, when interpreting the description of the second embodiment, the description of the second embodiment may take precedence for matters that contradict between the first and second embodiments (the same applies to the third to sixth embodiments described later). As long as there is no contradiction, any two or more of the first to sixth embodiments may be combined.

[0070] In the second embodiment, an example of the configuration of the constant current circuit 203 will be given. Fig. 14 is a configuration diagram of a switch circuit 10 according to the second embodiment. In the switch circuit 10 according to the second embodiment, the constant current circuit 203 is configured to have a switched capacitor circuit. The switched capacitor circuit in the constant current circuit 203 includes a capacitor 203a, switches 203b and 203c, and a switch changeover circuit 203d.

[0071] Except for the fact that the constant current circuit 203 is configured to have a switched capacitor circuit, the switch circuit 10 according to the second embodiment is similar to the switch circuit 10 according to the first embodiment. REF For convenience of illustration, a plurality of application terminals 207 are shown, but the plurality of application terminals 207 shown in the drawings refer to the same one.

[0072] Each of the switches 203b and 203c has a common end, a first end, and a second end, and is a change-over switch that connects the common end to either the first end or the second end. The common end of the switch 203b is connected to the first end of the capacitor 203a, the first end of the switch 203b is connected to a node ND3, and the second end of the switch 203b is connected to a reference voltage V REF The common terminal of the switch 203c is connected to the second terminal of the capacitor 203a, and the first terminal of the switch 203c is connected to the application terminal 207 of the reference voltage V REF The second terminal of the switch 203c is connected to an application terminal 207 of the constant current I, and the second terminal of the switch 203c is connected to a reference potential terminal having a potential of 0 V. The switch changeover circuit 203d generates a signal SSCLK. REF When generating the output signal (see FIG. 12), the switch changeover circuit 203d executes control to change over the states of the switches 203b and 203c based on the signal SSCLK (hereinafter referred to as switch changeover control).

[0073] During the execution period of the switch changeover control, the signal SSCLK alternately and periodically has a low level and a high level. When the signal SSCLK has a low level, as shown in FIG. 15, the common terminal is connected to the second terminal by the switch 203b, so that the reference voltage V REF is supplied, and the switch 203c connects the common terminal to the first terminal, so that the second terminal of the capacitor 203a is also supplied with the reference voltage V REF When the signal SSCLK has a high level, as shown in Fig. 16, the switch 203b connects the common end to the first end, thereby connecting the first end of the capacitor 203a to the node ND3, and the switch 203c connects the common end to the second end, thereby connecting the second end of the capacitor 203a to the reference potential end having a potential of 0V.

[0074] Therefore, during the execution period of the switch changeover control, a constant current I REF flows, and a constant current I REF The value of is determined by the capacitance value of the capacitor 203a, the frequency of the signal SSCLK, and the reference voltage V REFThe gate voltage V during the period of interest (between times T1 and T4) is proportional to the value of G The slew rate of “I REF / C FB " (as mentioned above, C FB represents the capacitance value of the feedback capacitor 202). Therefore, the capacitors 202 and 203a can be configured with the same type of capacitor (capacitors having the same structure manufactured by the same manufacturing process), and this cancels out the cause of the variation in the capacitor. That is, the gate voltage V G The slew rate of the signal SSCLK is calculated by the frequency of the signal SSCLK and the reference voltage V REF It can be precisely controlled by the value of

[0075] The constant current circuit 203 in Fig. 14 is a circuit using digital control, similar to the DAC-based ramp circuit 915 in Fig. 8, but does not have the linearity problem that occurs with the DAC. The constant current circuit 203 in Fig. 14 is a circuit that extracts a certain amount of charge from the node ND3 each time the states of the switches 203b and 203c are switched, so that the output voltage V OUT There is no momentary voltage drop or discontinuous rise during the rise process.

[0076] The switch control is performed during a high-level period of the control signal CNT1. During a low-level period of the control signal CNT1, the switch control is not performed and the signal SSCLK is fixed at a low level. Therefore, the constant current circuit 203 in FIG. 14 supplies the reference current I REF However, even during the high level period of the control signal CNT1, the feedback voltage V FB is the reference voltage V REFAfter the signal SSCLK falls below T1, the signal SSCLK may be fixed at a low level. In practice, for example, the switch circuit 203d may start switch control in response to the control signal CNT1 switching from a low level to a high level, and then, after a predetermined time has elapsed, stop the switch control and fix the signal SSCLK at a low level. The predetermined time here is preset to be longer than the time difference between times T1 and T4.

[0077] <<Third Example>> A third embodiment will be described. In the switch circuit 10 of FIG. 12 according to the first embodiment, the adjustment transistor 201 and the differential amplifier 204 adjust the voltage (V FB ) to form a current sink circuit that sinks a current from the gate of the output transistor M1. However, the current sink circuit may be formed of a so-called single-transistor amplifier. Specifically, the switch circuit 10 shown in FIG. 17 may be formed. FIG. 17 is a configuration diagram of the switch circuit 10 according to the third embodiment. The switch circuit 10 according to the third embodiment has a slew rate adjustment circuit 300 as the slew rate adjustment circuit 150 (see FIG. 3).

[0078] The slew rate adjustment circuit 300 includes an adjustment transistor 201, a feedback capacitor 202, a constant current circuit 203, and a switch 205. That is, the slew rate adjustment circuit 300 in FIG. 17 is obtained by deleting the differential amplifier 204 and the resistor 206 from the slew rate adjustment circuit 200 in FIG. 12. With this deletion, in the slew rate adjustment circuit 300, the gate of the adjustment transistor 201 is connected to the node ND3 and the source of the adjustment transistor 201 is directly connected to a reference potential point having a potential of 0V. In other respects, the slew rate adjustment circuit 300 in FIG. 17 has the same configuration as the slew rate adjustment circuit 200 in FIG. 12 and performs the same operation as the slew rate adjustment circuit 200 (except for the operation related to the differential amplifier 204).

[0079] In the slew rate adjustment circuit 300, a single-source common amplifier circuit is formed by the adjustment transistor 201, and a negative feedback operation similar to that in the case of using the differential amplifier 204 in FIG. 12 can be realized. That is, in the slew rate adjustment circuit 300, the gate of the adjustment transistor 201 is supplied with a feedback voltage V FB is supplied, and the feedback voltage V FB A drain current may flow through the adjustment transistor 201 depending on the voltage of the output transistor M1. The drain current of the adjustment transistor 201 is a current that flows from the gate of the output transistor M1 through the adjustment transistor 201, and is included in the above-mentioned discharge current I2 (see FIG. 5). During the target period, FB ) rises, the drain current of the adjustment transistor 201 increases, and the voltage of the node ND3 (V FB ) decreases, the drain current of the adjustment transistor 201 decreases.

[0080] Reference voltage V REF corresponds to the initial voltage of the node ND3 at the time when the switch 205 is switched from on to off (i.e., at time T1). REF Care must be taken when setting this.

[0081] First, the reference voltage V REF Consider the first case in which the reference voltage V coincides with the gate threshold voltage of the adjustment transistor 201. In the first case, the timing chart of the switch circuit 10 according to the third embodiment is the same as that shown in FIG. 13. Referring to FIG. 13, the slew rate adjustment circuit 300 adjusts the reference voltage V by keeping the switch 205 in the on state during the low-level period of the control signal CNT1 (i.e., before the target period). REF to the node ND3, thereby keeping the switch 205 in the off state during the high-level period of the control signal CNT1 (hence during the target period).

[0082] Between times T1 and T4, the driver 130 is connected to the parasitic capacitance C P A current I1 is provided to charge the parasitic capacitance C PA current I2 discharging the constant current I is drawn from the gate of the output transistor M1 to the slew rate adjustment circuit 300 (see FIG. 5). REF The feedback voltage V FB When the gate potential of the adjustment transistor 201 decreases, the drain current of the adjustment transistor 201 is suppressed, and the gate voltage V G and the output voltage V OUT The gate voltage V G The feedback voltage V FB The feedback voltage V FB The increase in the drain current of the adjustment transistor 201 increases the constant current I REF The feedback voltage V FB The gate voltage V G and the output voltage V OUT The rise in the gate voltage V G increases gradually and monotonically.

[0083] As mentioned above, “V OUT =V G -V GS " Therefore, the output voltage V OUT During the period when V rises (i.e., between times T2 and T3), the output voltage V OUT The slew rate of the gate voltage V G The slew rate is approximately equal to that of the

[0084] In this way, in the slew rate adjustment circuit 300, the adjustment transistor 201 adjusts the voltage of the node ND3 (V FB ) from the gate of the output transistor M1. The current drawn by the current draw circuit is included in the discharge current I2. Meanwhile, the driver 130 supplies a charging current I1 to the gate of the output transistor M1 during the target period. Therefore, during the target period, the gate voltage V G increases.

[0085] Gate voltage V G During the rise period of the feedback voltage V FB is the reference voltage V REF At time T4, the gate voltage V G After the rise in the gate voltage V G The effect of raising the potential of node ND3 due to the rise in REF This causes the voltage of node ND3 (V FB ) is the reference voltage V REF In the first case, “V FB <V REF When the voltage of the node ND3 (V FB ) drops to 0V, the constant current I REF will no longer flow.

[0086] Next, the reference voltage V REF Consider a second case in which the gate threshold voltage V is higher than the gate threshold voltage of the adjustment transistor 201. In the second case, immediately after the switch 205 is switched from on to off (i.e., immediately after time T1), the current I1 flowing from the driver circuit 130 to the wiring WR3 is entirely drawn by the adjustment transistor 201, so that the gate voltage V G does not rise. On the other hand, after time T1, the constant current I REF The voltage at node ND3 (V FB ) is the reference voltage V REF Then, the voltage at node ND3 (V FB ) is reduced to the gate threshold voltage of the adjustment transistor 201, G is the output voltage V OUT The gate voltage V G The behavior after the start of the rise is the same as in the first case.

[0087] Next, the reference voltage V REFConsider a third case in which the gate threshold voltage of the adjustment transistor 201 is lower than the gate threshold voltage of the adjustment transistor 201. In the third case, the adjustment transistor 201 is off immediately after the switch 205 is switched from on to off (i.e., immediately after time T1), so that the current I1 flowing from the driver circuit 130 to the wiring WR3 flows entirely through the parasitic capacitance C P contributes to charging the gate voltage V G rises at a high slew rate. G In conjunction with the rise in FB ) rises to the gate threshold voltage of the adjustment transistor 201, a drain current starts to flow through the adjustment transistor 201. When the drain current starts to flow through the adjustment transistor 201, the gate voltage V G The operation after the drain current starts to flow through the adjustment transistor 201 is the same as in the first case.

[0088] Reference voltage V REF It is preferable to design based on the gate threshold voltage of the adjustment transistor 201. REF is lower than the gate threshold voltage of the adjustment transistor 201, the gate voltage V G This can temporarily increase the slew rate of the reference voltage V REF It is preferable to set the reference voltage V to be equal to or higher than the gate threshold voltage of the adjustment transistor 201. REF is preferably set higher than the gate threshold voltage of the adjustment transistor 201, and the internal power supply voltage VDD is set to the reference voltage V REF However, the reference voltage V REF may be slightly lower than the gate threshold voltage of the adjustment transistor 201.

[0089] <<Fourth Example>> A fourth embodiment will be described. The second embodiment can also be applied to the third embodiment. That is, the constant current circuit 203 using the switched capacitor circuit shown in the second embodiment may be used as the constant current circuit 203 of the slew rate adjustment circuit 300 according to the third embodiment. FIG. 18 is a configuration diagram of a switch circuit 10 according to the fourth embodiment. The switch circuit 10 according to the fourth embodiment has the slew rate adjustment circuit 300 shown in the third embodiment, and the constant current circuit 203 in the slew rate adjustment circuit 300 is the constant current circuit 203 shown in the second embodiment. In the switch circuit 10 according to the fourth embodiment, the constant current circuit 203 is configured to have a switched capacitor circuit, and the operation of the switched capacitor circuit is as shown in the second embodiment.

[0090] <<Fifth Example>> A fifth embodiment will be described. The driver 130 supplies the gate voltage V G During the period when the gate voltage V G The level of the drive voltage V BST The level of the feedback capacitor 202 is set to be the same as that of the line WR1 and the node ND3 in the first to fourth embodiments. Therefore, in the first to fourth embodiments, the feedback capacitor 202 may be inserted between the line WR1 and the node ND3, instead of between the line WR3 and the node ND3. Similarly, in the first to fourth embodiments, the drain of the adjustment transistor 201 may be connected to the line WR1, instead of to the line WR3. An additional explanation will be given below.

[0091] 19 shows a part of the internal configuration of the driver 130. The driver 130 has an output stage consisting of transistors 131 and 132. The transistor 131 is a P-channel MOSFET, and the transistor 132 is an N-channel MOSFET. The source of the transistor 131 is connected to a wiring WR1, the drains of the transistors 131 and 132 are connected to a wiring WR3, and the source of the transistor 132 is connected to a wiring WR2. A parasitic diode having a forward direction from the drain to the source is added to the transistor 131. A parasitic diode having a forward direction from the source to the drain is added to the transistor 132.

[0092] 19, during a high-level period of the shift control signal CNT2, the transistor 131 is controlled to be on and the transistor 132 is controlled to be off. Therefore, during a high-level period of the shift control signal CNT2, the wiring WR1 is connected to the wiring WR3 through the transistor 131. At this time, the drain-source voltage of the transistor 131 can be considered to be sufficiently small, so that the gate voltage V G The level of the drive voltage V BST 19, during a low-level period of the shift control signal CNT2, the transistor 131 is controlled to be off and the transistor 132 is controlled to be on. Therefore, during a low-level period of the shift control signal CNT2, the wiring WR2 is connected to the wiring WR3 through the transistor 132, and at this time, the drain-source voltage of the transistor 132 can be considered to be sufficiently small, so that the gate voltage V G The level of the output voltage V OUT is equal to the level of

[0093] Therefore, in the above-mentioned first to fourth embodiments, a modification (hereinafter referred to as the first modification) in which the feedback capacitor 202 is inserted between the wiring WR1 and the node ND3, instead of between the wiring WR3 and the node ND3, may be applied, and the first modification also provides the same actions and effects as the first to fourth embodiments. Also, in the above-mentioned first to fourth embodiments, a modification (hereinafter referred to as the second modification) in which the drain of the adjustment transistor 201 is connected to the wiring WR1, instead of the wiring WR3, may be applied, and the second modification also provides the same actions and effects as the first to fourth embodiments. In the first to fourth embodiments, only one of the first and second modifications may be applied, or both the first and second modifications may be applied.

[0094] FIG. 20 shows a switch circuit 10 obtained by applying only the first modification of the first and second modifications to the switch circuit 10 (FIG. 12) according to the first embodiment. FIG. 21 shows a switch circuit 10 obtained by applying only the second modification of the first and second modifications to the switch circuit 10 (FIG. 12) according to the first embodiment. FIG. 22 shows a switch circuit 10 obtained by applying both the first and second modifications to the switch circuit 10 (FIG. 12) according to the first embodiment. In the switch circuits 10 of FIGS. 20 and 22, a first end of the feedback capacitor 202 is connected to the wiring WR1 (drive wiring) instead of the wiring WR3 (gate wiring), and a second end of the feedback capacitor 202 is connected to a node ND3. In the switch circuits 10 of FIGS. 21 and 22, a drain of the adjustment transistor 203 is connected to the wiring WR1 (drive wiring) instead of the wiring WR3 (gate wiring). The constant current circuit 203 of the switch circuit 10 in each of FIGS. 20 to 22 may be the constant current circuit 203 according to the second embodiment (see FIG. 14).

[0095] FIG. 23 shows a switch circuit 10 obtained by applying only the first modification of the first and second modifications to the switch circuit 10 (FIG. 17) according to the third embodiment. FIG. 24 shows a switch circuit 10 obtained by applying only the second modification of the first and second modifications to the switch circuit 10 (FIG. 17) according to the third embodiment. FIG. 25 shows a switch circuit 10 obtained by applying both the first and second modifications to the switch circuit 10 (FIG. 17) according to the third embodiment. In the switch circuits 10 of FIGS. 23 and 25, the first end of the feedback capacitor 202 is connected to the wiring WR1 (drive wiring) instead of the wiring WR3 (gate wiring), and the second end of the feedback capacitor 202 is connected to the node ND3. In the switch circuits 10 of FIGS. 24 and 25, the drain of the adjustment transistor 203 is connected to the wiring WR1 (drive wiring) instead of the wiring WR3 (gate wiring). The constant current circuit 203 of the switch circuit 10 in each of FIGS. 23 to 25 may be the constant current circuit 203 according to the fourth embodiment (see FIG. 18).

[0096] In the switch circuit 10 to which the first modification is not applied (see, for example, FIGS. 12 and 17), the driving voltage V BST When the driving voltage V BST The gate voltage V G At this time, the feedback capacitor 202 is connected to the gate voltage V G The feedback voltage V FB In the switch circuit 10 to which the first modification is applied (see, for example, FIG. 22 and FIG. 25), the driving voltage V BST When the driving voltage V BST The gate voltage V G At this time, the feedback capacitor 202 is driven by the driving voltage V BST (hence the gate voltage V G The feedback voltage V FB Therefore, the effect of the feedback capacitor 202 in the target period does not depend on whether the first modification is applied or not.

[0097] In the switch circuit 10 to which the second modification is not applied (see, for example, FIG. 12 and FIG. 17), the drain current of the adjustment transistor 201 flows from the wiring WR3 (gate wiring) through the adjustment transistor 201 to the reference potential terminal, and the gate voltage V G In the switch circuit 10 to which the second modification is applied (see, for example, FIG. 22 and FIG. 25), the drain current of the adjustment transistor 201 flows from the wiring WR1 (drive wiring) through the adjustment transistor 201 to the reference potential terminal, and the drive voltage V BST During the target period, the driving voltage V BST The decrease in the gate voltage V G Therefore, the effect of the drain current of the adjustment transistor 201 during the target period does not depend on whether the second variant is applied or not.

[0098] During the high-level period of the control signal CNT1 (hence, the high-level period of the shift control signal CNT2), the charge pump circuit 140 outputs a current to the wiring WR1 (drive wiring) to generate a drive voltage V BST Increase.

[0099] In a switch circuit 10 to which the second modification is not applied (for example, the switch circuit 10 in FIG. 12 or FIG. 17), a current is supplied from the driver 130 to the wiring WR3 (gate wiring) and a current is drawn from the wiring WR3 (gate wiring) to the slew rate adjustment circuit (200, 300) during the target period (between times T1 and T4), and a gate voltage V G rises (the former current is larger than the latter current). Note that during the target period, substantially all of the output current of the charge pump circuit 140 (the current that the charge pump circuit 140 outputs to the wiring WR1) is supplied to the wiring WR3 via the driver 130.

[0100] In contrast, in the switch circuit 10 to which the second modification is applied (for example, the switch circuit 10 in FIG. 22 or FIG. 25), during the target period (between times T1 and T4), a current is output from the charge pump circuit 140 to the wiring WR1 (drive wiring) and a current is drawn from the wiring WR1 (drive wiring) to the slew rate adjustment circuit (200, 300), and the difference between the former current and the latter current is supplied to the wiring WR3 (gate wiring), thereby causing the gate voltage V G rises (the former current is larger than the latter current). In the switch circuit 10 to which the second modification is applied, the current drawn from the wiring WR1 (drive wiring) to the slew rate adjustment circuit (200, 300) is the drain current of the adjustment transistor 201.

[0101] <<Sixth Example>> A sixth embodiment will now be described. In the sixth embodiment, applied techniques, modified techniques, or supplementary matters for the above-mentioned items will be described.

[0102] A switched capacitor circuit is shown as an example of the configuration of the constant current circuit 203. However, the constant current circuit 203 has a constant current I REF Any circuit capable of generating the above signal may be used, and may be formed using an analog circuit such as a current mirror circuit.

[0103] For any signal or voltage, the relationship between the high level and the low level thereof may be reversed to that described above without prejudice to the spirit of the above.

[0104] The channel types of FETs (field effect transistors) shown in each embodiment are merely examples, and the channel type of any FET may be changed between P-channel and N-channel without departing from the spirit of the above.

[0105] Any of the transistors described above may be any type of transistor, provided that no disadvantage occurs. For example, any of the transistors described above as MOSFETs may be replaced with junction FETs, IGBTs (Insulated Gate Bipolar Transistors), or bipolar transistors, provided that no disadvantage occurs. Any of the transistors has a first electrode, a second electrode, and a control electrode. In a FET, one of the first and second electrodes is a drain, the other is a source, and the control electrode is a gate. In an IGBT, one of the first and second electrodes is a collector, the other is an emitter, and the control electrode is a gate. In a bipolar transistor that does not belong to an IGBT, one of the first and second electrodes is a collector, the other is an emitter, and the control electrode is a base.

[0106] The embodiments of the present disclosure can be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The above embodiments are merely examples of the embodiments of the present disclosure, and the meanings of the terms of the present disclosure or each component are not limited to those described in the above embodiments. The specific numerical values ​​shown in the above description are merely examples, and can be changed to various numerical values ​​as a matter of course.

[0107] <<Additional Notes>> Regarding the present disclosure, specific configuration examples of which have been shown in the above-mentioned embodiments, additional notes will be provided.

[0108] A switch circuit (10) according to an aspect of the present disclosure includes an output switching element (M1) provided between a first node (ND1) and a second node (ND2), a gate wiring (WR3) to which a gate of the output switching element is connected, and a drive voltage (V BST ) is applied to a drive wiring (WR1) and configured to drive the gate of the output switching element in response to control signals (CNT1, CNT2); and a drive circuit (130) configured to drive a gate voltage (V G and a slew rate adjustment circuit (150, 200, 300) configured to adjust the slew rate of the gate voltage of the output switching element during a target period in which a constant current (I REF ) and a current sink circuit configured to sink a current from the gate wiring or the drive wiring in response to the voltage of the third node (first configuration).

[0109] This makes it possible to accurately control the slew rate of the gate voltage of the output switching element, thereby enabling the output voltage obtained through the increase in the gate voltage to be increased gradually with high accuracy.

[0110] Regarding the switch circuit of the above first configuration, a configuration (second configuration) may be adopted in which, during the target period, the gate voltage of the output switching element increases based on the difference between the current supplied to the gate wiring by the drive circuit and the current drawn from the gate wiring to the slew rate adjustment circuit, or, during the target period, the difference between the current output to the drive wiring from the circuit generating the drive voltage and the current drawn from the drive wiring to the slew rate adjustment circuit is supplied to the gate wiring, thereby increasing the gate voltage of the output switching element.

[0111] In the switch circuit according to the second configuration (see FIG. 12), the current sink circuit includes an adjustment transistor (201) inserted between the gate wiring or the drive wiring and a reference potential terminal, and a feedback voltage (V FB ) and the feedback voltage and a specified voltage (V REF ), and a differential amplifier (204) configured to control the gate potential of the adjustment transistor in accordance with the comparison result with the third node, and a configuration (third configuration) in which a current is drawn from the gate wiring or the drive wiring through the adjustment transistor in accordance with the voltage of the third node.

[0112] In the switch circuit according to the third configuration, the differential amplifier may be configured (fourth configuration) to control the gate potential of the adjustment transistor so that, during the target period, when the feedback voltage is higher than the predetermined voltage, the current flowing from the gate wiring or the drive wiring through the adjustment transistor increases, and when the feedback voltage is lower than the predetermined voltage, the current flowing from the gate wiring or the drive wiring through the adjustment transistor decreases.

[0113] In the switch circuit according to the third or fourth configuration, the slew rate adjustment circuit may have a switch (205) inserted between the application terminal of the predetermined voltage and the third node, and may be configured to supply the predetermined voltage to the third node by keeping the switch in an on state before the target period, and to keep the switch in an off state during the target period (fifth configuration).

[0114] In the switch circuit according to the second configuration (see FIG. 17), the current sink circuit may have an adjustment transistor (201) inserted between the gate wiring or the drive wiring and a reference potential end, the gate of the adjustment transistor is connected to the third node, and the current sink circuit may be configured to sink a current from the gate wiring or the drive wiring through the adjustment transistor depending on the voltage of the third node (sixth configuration).

[0115] In the switch circuit according to the sixth configuration, a configuration (seventh configuration) may be adopted in which, during the target period, a current flowing from the gate wiring or the drive wiring through the adjustment transistor increases in response to an increase in the voltage of the third node, and a current flowing from the gate wiring or the drive wiring through the adjustment transistor decreases in response to a decrease in the voltage of the third node.

[0116] In the switch circuit according to the sixth or seventh configuration, the slew rate adjustment circuit may have a switch (205) inserted between an application terminal of a predetermined voltage and the third node, and may be configured to supply the predetermined voltage to the third node by keeping the switch in an on state before the target period, and to keep the switch in an off state during the target period (eighth configuration).

[0117] In the switch circuit according to any one of the above first to eighth configurations, the constant current circuit may have a switched capacitor circuit (203a to 203d), and may be configured (ninth configuration) in which the constant current is drawn from the third node by the switched capacitor circuit during the target period. [Explanation of symbols]

[0118] 1 Semiconductor device CS case 10, 10ref switch circuit 20 Protection circuit 30 Internal power circuit VS Voltage Source C OUT Output Capacitor IN Input terminal OUT Output terminal GND Ground terminal EN Enable terminal V IN Input voltage V OUT Output Voltage S EN Enable Signal VDIV Voltage CNT1 control signal CNT2 Shift control signal 110 Control circuit 120 Level Shifter 130 Driver 140 Charge pump circuit 141 Oscillator Circuit 142 Capacitor 143, 144 Diodes 150, 200, 300 Slew rate adjustment circuit M1 Output transistor C P parasitic capacitance WR1~WR3 wiring ND1~ND3 nodes V BST Driving voltage V G Gate Voltage VDD Internal power supply voltage ND1~ND3 nodes I1 charging current I2 discharge current 910 Slew rate adjustment circuit 911 Adjustment transistor 912 Resistance 913, 914 Voltage divider resistor 915 Lamp Circuit 916 Differential Amplifier SS Lamp Signal 201 Adjustment transistor 202 Feedback capacitor 203 Constant current circuit 203a capacitor 203b, 203c Switch 203d Switching circuit 204 Differential Amplifier 205 Switch 206 Resistance

Claims

1. an output switching element provided between the first node and the second node; a drive circuit connected to a gate wiring to which the gate of the output switching element is connected and to a drive wiring to which a drive voltage is applied, and configured to drive the gate of the output switching element in response to a control signal; a slew rate adjustment circuit configured to adjust a slew rate of a gate voltage of the output switching element during a target period in which the drive circuit increases a gate voltage of the output switching element based on the drive voltage in order to switch the output switching element from OFF to ON; The slew rate adjustment circuit includes a feedback capacitor inserted between the gate wiring or the drive wiring and a third node, a constant current circuit configured to draw a constant current from the third node during the target period, and a current draw circuit configured to draw a current from the gate wiring or the drive wiring in response to a voltage of the third node. , switch circuit.

2. During the target period, the gate voltage of the output switching element increases based on a difference between a current supplied from the drive circuit to the gate wiring and a current drawn from the gate wiring to the slew rate adjustment circuit, or During the target period, the difference between the current output from the circuit generating the drive voltage to the drive wiring and the current drawn from the drive wiring to the slew rate adjustment circuit is supplied to the gate wiring, thereby increasing the gate voltage of the output switching element.

2. The switch circuit according to claim 1.

3. The current sink circuit comprises: an adjustment transistor inserted between the gate wiring or the drive wiring and a reference potential terminal; a differential amplifier configured to receive the voltage at the third node as a feedback voltage and to control a gate potential of the adjustment transistor in response to a comparison result between the feedback voltage and a predetermined voltage; A current is drawn from the gate wiring or the drive wiring through the adjustment transistor in response to the voltage of the third node.

3. The switch circuit according to claim 2.

4. The differential amplifier controls a gate potential of the adjustment transistor so that, during the target period, when the feedback voltage is higher than the predetermined voltage, a current flowing from the gate wiring or the drive wiring through the adjustment transistor increases, and when the feedback voltage is lower than the predetermined voltage, a current flowing from the gate wiring or the drive wiring through the adjustment transistor decreases.

4. The switch circuit according to claim 3.

5. The slew rate adjustment circuit has a switch inserted between an application terminal of the predetermined voltage and the third node, and supplies the predetermined voltage to the third node by keeping the switch in an on state before the target period, and keeps the switch in an off state during the target period.

4. The switch circuit according to claim 3.

6. the current sink circuit has an adjustment transistor inserted between the gate wiring or the drive wiring and a reference potential end, the gate of the adjustment transistor being connected to the third node; The current sink circuit sinks a current from the gate wiring or the drive wiring through the adjustment transistor in response to a voltage of the third node.

3. The switch circuit according to claim 2.

7. During the target period, in response to an increase in the voltage of the third node, a current flowing from the gate wiring or the drive wiring through the adjustment transistor increases, and in response to a decrease in the voltage of the third node, a current flowing from the gate wiring or the drive wiring through the adjustment transistor decreases.

7. The switch circuit according to claim 6.

8. The slew rate adjustment circuit has a switch inserted between an application terminal of a predetermined voltage and the third node, and supplies the predetermined voltage to the third node by keeping the switch in an on state before the target period, and keeps the switch in an off state during the target period.

7. The switch circuit according to claim 6.

9. The constant current circuit has a switched capacitor circuit, and the constant current is drawn from the third node by the switched capacitor circuit during the target period.

9. A switch circuit according to claim 1.

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