Semiconductor element and manufacturing method of semiconductor element

Abstract

To solve a problem in which there is a need for a semiconductor element that can efficiently couple propagating light from one side to the other side between two opposing portions.SOLUTION: A semiconductor element includes a semiconductor layer, a first optical waveguide provided on the semiconductor layer, and a second optical waveguide provided on the semiconductor layer. The first optical waveguide includes a first portion, and a second portion including a bent region connected to the first portion. The second optical waveguide includes a third portion facing the first portion. The semiconductor layer includes a first region located between the first portion and the third portion, and a second region in which the second portion is provided. The top surface of the second region is located lower than the top surface of the first region. The first portion does not include a light extraction region that extracts light passing through a first waveguide to the outside.SELECTED DRAWING: Figure 1A

Description

[Technical field]

[0001] The present disclosure relates to semiconductor devices and methods for manufacturing semiconductor devices. [Background technology]

[0002] A semiconductor element having an optical waveguide can be used in various optical devices such as a semiconductor laser element or an optical circuit, etc. Patent Document 1 discloses an example of a ring resonator that utilizes a whispering gallery mode. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 8-125251 Summary of the Invention [Problem to be solved by the invention]

[0004] There is a need for a semiconductor device that can efficiently couple propagating light from one portion to the other between two opposing portions. [Means for solving the problem]

[0005] In one embodiment, a semiconductor element of the present disclosure is a semiconductor element comprising a semiconductor layer, a first ridge provided on the semiconductor layer, and a second ridge provided on the semiconductor layer, wherein the first ridge has a first portion and a second portion including a bending region connected to the first portion, the second ridge has a third portion opposite the first portion, the semiconductor layer has a first region located between the first portion and the third portion, and a second region in which the second portion is provided, and a height from a lower end to an upper end of the first ridge in the first region is lower than a height from a lower end to an upper end of the first ridge in the second region.

[0006] In one embodiment, a semiconductor element of the present disclosure is a semiconductor element comprising a semiconductor layer, a first ridge provided on the semiconductor layer, and a second ridge provided on the semiconductor layer, wherein the first ridge has a first portion and a second portion connected to the first portion, the second ridge has a third portion opposite the first portion, the second portion has a portion extending in a direction from the third portion side to the first portion side, the distance between the second portion and the third portion is greater than the distance between the first portion and the third portion, the semiconductor layer has a first region located between the first portion and the third portion and a second region in which the second portion is provided, and a height from a lower end to an upper end of the first ridge in the first region is lower than a height from a lower end to an upper end of the first ridge in the second region.

[0007] In one embodiment, a manufacturing method for a semiconductor element disclosed herein includes the steps of: preparing a semiconductor stack; etching the semiconductor stack to form a semiconductor layer, a first ridge provided on the semiconductor layer, the first ridge having a first portion and a second portion including a bending region connected to the first portion; and a second ridge provided on the semiconductor layer, the second ridge having a third portion opposed to the first portion; and further etching the semiconductor stack to make a lower end of the first ridge in a portion forming the bending region lower than a lower end of the first ridge in a portion forming the first portion. Effect of the Invention

[0008] According to the present disclosure, it is possible to realize a semiconductor element capable of efficiently coupling propagating light from one portion to the other portion between two portions facing each other. [Brief description of the drawings]

[0009] [Figure 1A] FIG. 1A is a perspective view illustrating a schematic configuration of a semiconductor device according to Embodiment 1. FIG. [Figure 1B] FIG. 1B is a top view of the semiconductor device shown in FIG. 1A. [Figure 2A]FIG. 2A is a cross-sectional view of the semiconductor element shown in FIG. 1B taken along line IIA-IIA. [Figure 2B] FIG. 2B is a cross-sectional view of the semiconductor element shown in FIG. 1B taken along line IIB-IIB. [Figure 2C] FIG. 2C is a cross-sectional view of the semiconductor element shown in FIG. 1B taken along line IIC-IIC. [Figure 3A] FIG. 3A is a diagram showing the electric field distribution of propagating light in an optical waveguide obtained by simulation for the first example. [Figure 3B] FIG. 3B is a diagram showing the electric field distribution of propagating light in the optical waveguide obtained by simulation for the second example. [Figure 3C] FIG. 3C is a diagram showing the electric field distribution of propagating light in the optical waveguide obtained by simulation for the third example. [Figure 4A] FIG. 4A is a top view diagrammatically illustrating the configuration of a semiconductor element according to Modification 1 of Embodiment 1. FIG. [Figure 4B] FIG. 4B is a top view diagrammatically illustrating the configuration of a semiconductor element according to Modification 2 of Embodiment 1. As shown in FIG. [Figure 4C] FIG. 4C is a top view diagrammatically illustrating the configuration of a semiconductor element according to Modification 3 of Embodiment 1. As shown in FIG. [Figure 4D] FIG. 4D is a top view diagrammatically illustrating the configuration of a semiconductor device according to Modification 4 of Embodiment 1. FIG. [Figure 5A] FIG. 5A is a perspective view illustrating a schematic configuration of a semiconductor device according to the second embodiment. [Figure 5B] FIG. 5B is a top view of the semiconductor device shown in FIG. 5A. [Figure 5C] FIG. 5C is a cross-sectional view of the semiconductor element shown in FIG. 5B taken along line VC-VC. [Figure 6A] FIG. 6A is a perspective view illustrating a schematic configuration of a semiconductor device according to a modified example of the second embodiment. [Figure 6B] FIG. 6B is a top view of the semiconductor device shown in FIG. 6A. [Figure 6C] FIG. 6C is a cross-sectional view of the semiconductor element shown in FIG. 6B taken along line VIC-VIC. [Figure 7A] FIG. 7A is a perspective view illustrating a schematic configuration of a semiconductor device according to Embodiment 3. FIG. [Figure 7B] FIG. 7B is a top view of the semiconductor device shown in FIG. 7A. [Figure 7C] FIG. 7C is a cross-sectional view of the semiconductor element shown in FIG. 7B taken along line VIIC-VIIC. [Figure 8A] FIG. 8A is a view for explaining an example of a step in the method for manufacturing a semiconductor device according to the first embodiment. [Figure 8B] FIG. 8B is a view for explaining an example of a step in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 8C] FIG. 8C is a view for explaining an example of a step in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 8D] FIG. 8D is a view for explaining an example of a step in the method for manufacturing a semiconductor device according to the first embodiment. [Figure 8E] FIG. 8E is a view for explaining an example of a step in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 8F] FIG. 8F is a view for explaining an example of a step in the method for manufacturing a semiconductor device according to the first embodiment. [Figure 8G] FIG. 8G is a view for explaining an example of a step in the method for manufacturing a semiconductor device according to the first embodiment. [Figure 8H] FIG. 8H is a view for explaining an example of a step in the method for manufacturing a semiconductor device according to the first embodiment. [Figure 8I] FIG. 8I is a view for explaining an example of a process in the method for manufacturing a semiconductor device according to the first embodiment. [Figure 8J] FIG. 8J is a view for explaining an example of a step in the method for manufacturing a semiconductor device according to the first embodiment. [Figure 9] FIG. 9 is a top view diagrammatically illustrating the configuration of a semiconductor element according to a comparative example. [Figure 10A] FIG. 10A is a graph showing an oscillation spectrum of laser light generated when the semiconductor element according to Example 1 is optically excited. [Figure 10B] FIG. 10B is a graph showing an oscillation spectrum of laser light generated when the semiconductor element according to the second embodiment is optically excited. [Figure 11] FIG. 11 is a diagram showing an oscillation spectrum of laser light generated when the semiconductor element according to the comparative example is optically excited. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, a semiconductor device and a manufacturing method thereof according to an embodiment of the present disclosure will be described in detail with reference to the drawings. Parts having the same reference numerals appearing in multiple drawings indicate the same or equivalent parts.

[0011] Furthermore, the following is an example to embody the technical idea of ​​the present invention, and the present invention is not limited to the description of the embodiment. Furthermore, the description of the dimensions, materials, shapes, relative positions, etc. of the components is intended to be illustrative, and not to limit the scope of the present invention thereto. The sizes and positional relationships of the components shown in each drawing may be exaggerated to make it easier to understand. In addition, in this specification or claims, when there are multiple corresponding components for a certain component and each of them needs to be expressed separately, the components may be distinguished by adding "first" or "second" to the beginning of the component. When the objects or viewpoints distinguished between this specification and the claims are different, the same addition may not refer to the same object between this specification and the claims. (Embodiment 1) A semiconductor element according to one embodiment of the present disclosure is a semiconductor element comprising a semiconductor layer, a first ridge provided on the semiconductor layer, and a second ridge provided on the semiconductor layer, wherein the first ridge has a first portion and a second portion including a bending region connected to the first portion, the second ridge has a third portion opposite the first portion, the semiconductor layer has a first region located between the first portion and the third portion, and a second region in which the second portion is provided, and a height from a lower end to an upper end of the first ridge in the first region is lower than a height from a lower end to an upper end of the first ridge in the second region.

[0012] Furthermore, a semiconductor element of one embodiment according to the present disclosure is a semiconductor element comprising a semiconductor layer, a first ridge provided on the semiconductor layer, and a second ridge provided on the semiconductor layer, wherein the first ridge has a first portion and a second portion connected to the first portion, the second ridge has a third portion facing the first portion, the second portion has a portion extending in a direction from the third portion side to the first portion side, the distance between the second portion and the third portion is greater than the distance between the first portion and the third portion, the semiconductor layer has a first region located between the first portion and the third portion and a second region in which the second portion is provided, and a height from a lower end to an upper end of the first ridge in the first region is lower than a height from a lower end to an upper end of the first ridge in the second region.

[0013] In the semiconductor element of the present disclosure configured as above, propagating light can be efficiently coupled from one of the two opposing portions to the other.

[0014] First, with reference to FIG. 1A and FIG. 1B, a configuration example of a semiconductor device according to the first embodiment of the present disclosure will be described. FIG. 1A is a perspective view that shows a schematic configuration of a semiconductor device 100 according to the first exemplary embodiment of the present disclosure. The semiconductor device 100 shown in FIG. 1A includes a semiconductor layer 10, and a first ridge 20a and a second ridge 20b provided on the semiconductor layer 10. FIG. 1B is a top view of the semiconductor device 100 shown in FIG. 1A. For reference, the drawings show an X-axis, a Y-axis, and a Z-axis that are perpendicular to each other. The direction of the X-axis arrow is the +X direction, and the opposite direction is the -X direction. When the ±X directions are not distinguished, they are simply referred to as the X direction. The same applies to the Y direction and the Z direction. The thickness direction of the semiconductor layer 10 is parallel to the Z direction. The direction in which the first ridge 20a and the second ridge 20b are arranged is parallel to the X direction. The direction perpendicular to the thickness direction of the semiconductor layer 10 and the direction in which the first ridge 20a and the second ridge 20b are arranged is parallel to the Y direction. This does not limit the orientation of the semiconductor element 100 during use, and the orientation of the semiconductor element 100 is arbitrary. In this specification, viewing the semiconductor element 100 from the +Z direction side is referred to as a "top view."

[0015] As shown in FIG. 1B, each of the first ridge 20a and the second ridge 20b has a generally rectangular ring shape in a top view. The semiconductor device 100 includes at least a first optical waveguide and a second optical waveguide. The first optical waveguide includes at least the first ridge 20a. The second optical waveguide includes at least the second ridge 20b. Each of the first optical waveguide and the second optical waveguide forms a ring resonator. The resonant wavelength λ of the propagating light in each optical waveguide and the optical distance L of one revolution of each optical waveguide satisfy the relationship mλ=L (m is a natural number). The optical distance means the product of the distance that the light actually travels in a medium and the refractive index of the medium. The resonant wavelength when the first optical waveguide and the second optical waveguide interact with each other may include a wavelength different from the wavelength when each optical waveguide oscillates independently.

[0016] The semiconductor layer 10 may be, for example, a layer grown on a substrate. The semiconductor layer 10 may be, for example, monocrystalline or polycrystalline, but may also be amorphous. The material of the semiconductor layer 10 will be described later.

[0017] Each of the first ridge 20a and the second ridge 20b has a laminated structure. The laminated structure includes, in the Z direction from the semiconductor layer 10 side, a semiconductor layer of the same conductivity type as the semiconductor layer 10, an active layer, and a semiconductor layer of a conductivity type different from that of the semiconductor layer 10, in this order. The conductivity type of the semiconductor layer 10 is defined as a first conductivity type, and the conductivity type different from the first conductivity type is defined as a second conductivity type. The first conductivity type is one of n-type and p-type, and the second conductivity type is the other of n-type and p-type. The materials and sizes of the first ridge 20a and the second ridge 20b will be described later.

[0018] By irradiating the first optical waveguide and the second optical waveguide with light, the active layers included in each of the first optical waveguide and the second optical waveguide are excited to generate laser oscillation. The wavelength of the laser light corresponds to a resonant wavelength when the first optical waveguide and the second optical waveguide interact with each other. This resonant wavelength may include a wavelength different from the wavelength when each optical waveguide oscillates independently.

[0019] Each of the components included in the semiconductor device 100 will be described below.

[0020] The first ridge 20a includes at least a first portion and a second portion including a curved region connected to the first portion. In this embodiment, the straight portion 22a on the +X direction side included in the first ridge 20a shown in FIG. 1B corresponds to the first portion. Also, at least one of the curved portion 23a on the +X direction side and the +Y direction side included in the first ridge 20a corresponds to the second portion. In this embodiment, the first optical waveguide in the portion forming the first portion is a straight waveguide, and the first optical waveguide in the portion forming the second portion is a curved waveguide.

[0021] 1B, the first ridge 20a includes two straight line portions 21a extending along the X direction, two straight line portions 22a extending along the Y direction, and four curved line portions 23a extending while changing direction from one of the X direction and the Y direction to the other. One straight line portion 21a and one straight line portion 22a adjacent to the straight line portion 21a are connected by one curved line portion 23a, respectively, to form the ring-shaped first ridge 20a.

[0022] The second ridge 20b includes at least a third portion facing the first portion. In this embodiment, the straight portion 22b on the -X direction side included in the second ridge 20b shown in FIG. 1B corresponds to the third portion. In this embodiment, the second optical waveguide in the portion forming the third portion is a straight waveguide. As shown in FIG. 1B, the second ridge 20b includes two straight portions 21b extending in the X direction, two straight portions 22b extending in the Y direction, and four curved portions 23b extending from one of the X direction and the Y direction to the other. One straight portion 21b and one straight portion 22b adjacent to the straight portion 21a are connected by one curved portion 23b, respectively, to form a ring-shaped second ridge 20b.

[0023] The straight line portion 22a on the +X direction side of the first ridge 20a and the straight line portion 22b on the -X direction side of the second ridge 20b face each other. In other words, at least one straight line portion 22a of the first ridge 20a faces the straight line portion 22b of the second ridge 20b that is adjacent to and closest to the straight line portion 22a.

[0024] In the following description, when there is no need to distinguish between the two straight line portions 21a included in the first ridge 20a, they will simply be referred to as the "straight line portions 21a," when there is no need to distinguish between the two straight line portions 22a, they will simply be referred to as the "straight line portions 22a," and when there is no need to distinguish between the four curved line portions 23a, they will simply be referred to as the "curved line portions 23a." The same applies to the two straight line portions 21b, the two straight line portions 22b, and the four curved line portions 23b included in the second ridge 20b.

[0025] In the first ridge 20a, the length of the straight line portion 21a and the length of the straight line portion 22a may be equal to each other, or the length of the straight line portion 21a may be greater or smaller than the length of the straight line portion 22a. The curved line portion 23a may be, for example, in the shape of a quarter circle arc. The curved line portion 23a may have any curved shape such as an elliptical arc. The same applies to the straight line portions 21b and 22b and the curved line portion 23b in the second ridge 20b. Each of the first ridge 20a and the second ridge 20b may have any ring shape such as a circular ring or an elliptical ring that does not include a straight line portion, instead of a roughly rectangular ring shape as shown in FIG. 1B in a top view. The mutually facing portions of the first ridge 20a and the second ridge 20b do not have to have a straight line shape, and may have curved shapes that are curved in the same direction or in opposite directions.

[0026] In this specification, among the above mutually opposing parts, the part included in the first ridge 20a is referred to as the "first part", the part connected to the first part is referred to as the "second part", and among the above mutually opposing parts, the part included in the second ridge 20b is referred to as the "third part". The second part includes a curved region connected to the first part. From another perspective, the second part has a part extending in a direction from the third part side to the first part side. The distance between the second part and the third part is greater than the distance between the first part and the third part. The distance between the first part and the third part refers to the shortest distance between the surfaces where the first part and the third part face each other. In addition, the distance between the second part and the third part refers to the shortest distance between the second part and the third part. The second part intersects with the direction in which the first part extends and extends in a direction away from the first part and the third part. Therefore, the distance between the second part and the third part is greater than the distance between the first part and the third part.

[0027] As shown in FIG. 1A, the semiconductor layer 10 includes a first region 11 and a second region 12. In the example shown in FIG. 1A, the second region is provided in two rows and three columns. As shown in FIG. 1B, the row direction is parallel to the X direction, and the column direction is parallel to the Y direction. As shown in FIG. 1B, the first region 11 is a surface of the semiconductor layer 10 located between a straight portion 22a on the +X direction side included in the first ridge 20a and a straight portion 22b on the -X direction side included in the second ridge 20b, and a region immediately below the surface. In other words, the first region 11 is a surface of the semiconductor layer 10 located between the straight portion 22a of the first ridge 20a and the straight portion 22b of the second ridge 20b facing the straight portion 22a, and a region immediately below the surface. As shown in FIG. 1A, the second region 12 is a bottom surface of a recess provided on the upper surface of the semiconductor layer 10 and a portion immediately below the bottom surface. The second region 12 is provided with a curved portion 23a and / or a curved portion 23b. 1B, the second region 12 has a generally rectangular shape in top view. The height from the bottom end to the top end of the first ridge 20a in the first region 11 is lower than the height from the bottom end to the top end of the first ridge 20b in the second region 12. This makes it possible to reduce leakage of light propagating through the first optical waveguide and the second optical waveguide to the outside at the curved portions 23a and 23b.

[0028] As shown in FIG. 1A, the upper surface of the first ridge 20a, i.e., the upper surfaces of the straight portions 21a and 22a and the curved portion 23a, are located on the same plane parallel to the XY plane. The distance from the lower end of the first ridge 20a to the upper ends of the straight portions 21a and 22a in the first region 11 is smaller than the distance from the lower end of the first ridge 20a to the upper end of the curved portion 23a in the second region 12. The upper surface of the second optical waveguide, i.e., the upper surface of the straight portions 21b and 22b and the curved portion 23b, are located on the same plane parallel to the XY plane. The distance from the lower end of the second ridge 20b to the upper ends of the straight portions 21b and 22b in the first region 11 is smaller than the distance from the lower end of the second ridge 20b to the upper end of the curved portion 23b in the second region 12.

[0029] The height from the bottom end to the top end of the ridge in the curved portions 23a and 23b is greater than the height from the bottom end to the top end of the ridge in the straight portions 21a, 21b, 22a, and 22b. This can reduce the leakage of light propagating through the first ridge 20a and the second ridge 20b to the outside at the curved portions 23a and 23b. Furthermore, the heights of the straight portion 22a on the +X direction side and the straight portion 22b on the -X direction side facing each other are lower than the heights of the curved portions 23a and 23b. This can efficiently couple the light propagating through one optical waveguide to the other optical waveguide via the first region 11. The suppression of light leakage and efficient optical coupling will be described later with reference to a simulation example.

[0030] In the first embodiment, light is efficiently coupled from one to the other via the first region 11, rather than via the air region between the adjacent first ridge 20a and second ridge 20b.

[0031] The first portion (i.e., straight portion 22a) included in the first ridge 20a does not include a light extraction region for extracting light passing through the first optical waveguide to the outside. Similarly, the third portion (i.e., straight portion 22b) included in the second ridge 20b does not include a light extraction region for extracting light passing through the second optical waveguide to the outside. "Not including a light extraction region" refers to the absence of a light extraction structure such as a grating, and does not include the output of spontaneous emission light or the like. The generated laser light can be extracted, for example, from a straight portion of a certain optical waveguide that is not adjacent to another optical waveguide, for example, by providing a light extraction region in the straight portion. The light extraction region can include, for example, a grating.

[0032] Next, with reference to Figures 2A to 2C, a description will be given of the laminated structure of the first optical waveguide and the second optical waveguide in the semiconductor element 100. Figures 2A to 2C are cross-sectional views taken along lines IIA-IIA, IIB-IIB, and IIC-IIC, respectively, of the semiconductor element 100 shown in Figure 1B.

[0033] As shown in FIG. 2A, the straight line portion 22a included in the first ridge 20a has a layered structure including, from the semiconductor layer 10 side, a first semiconductor layer 24a including a semiconductor layer of a first conductivity type, a first active layer 25a, and a second semiconductor layer 26a including a semiconductor layer of a second conductivity type, in this order. The first active layer 25a included in the straight line portion 22a is located higher than the lower end of the first ridge 20a in the first region 11. The straight line portion 21a connected by the curved line portion 23a of the first ridge 20a has a layered structure similar to that of the straight line portion 22a. As shown in FIG. 2A, the straight line portion 22b included in the second ridge 20b has a layered structure including, from the semiconductor layer 10 side, a first semiconductor layer 24b including a semiconductor layer of a first conductivity type, a second active layer 25b, and a third semiconductor layer 26b including a semiconductor layer of a second conductivity type, in this order. The second active layer 25b included in the straight line portion 22b is located higher than the lower end of the second ridge 20b in the first region 11. The straight line portion 21b included in the second ridge 20b and extending along the X direction has a layered structure similar to that of the straight line portion 22b.

[0034] As shown in FIG. 2B, the curved portion 23a included in the first ridge 20a has a laminated structure including, from the semiconductor layer 10 side, a first semiconductor layer 24a including a semiconductor layer of a first conductivity type, a first active layer 25a, and a second semiconductor layer 26a including a semiconductor layer of a second conductivity type, in this order. The first active layer 25a included in the curved portion 23a is located higher than the lower end of the first ridge 20a in the first region 11 shown in FIG. 2A and the lower end of the first ridge 20a in the second region 12 shown in FIG. 2B. The curved portion 23a and the first active layer 25a included in the straight portion 22a are formed on the same plane. As shown in FIG. 2B, the curved portion 23b included in the second ridge 20b has a laminated structure including, from the semiconductor layer 10 side, a first semiconductor layer 24b including a semiconductor layer of a first conductivity type, a second active layer 25b, and a third semiconductor layer 26b including a semiconductor layer of a second conductivity type, in this order. The second active layer 25b included in the curved portion 23b is located at a higher position than the lower end of the second ridge 20b in the first region 11 shown in Fig. 2A and the lower end of the second ridge 20b in the second region 12 shown in Fig. 2B. The second active layer 25b included in the curved portion 23b and the straight portion 22b are formed on the same plane.

[0035] As shown in FIG. 2C, the upper surface of the second region 12 is located lower than the upper surface of the first region 11.

[0036] 2A, 2B, and 2C, the height from the bottom end to the top end of the first ridge 20a in the first region 11 is lower than the height from the bottom end to the top end of the first ridge 20a in the second region 12, so the light confinement effect in the second region 12 is higher than that in the first region 11. In other words, the first region 11 has a larger amount of light seeping out than the second region 12. Therefore, the first region 11 facilitates optical coupling between the first optical waveguide and the second optical waveguide, and the second region 12 can reduce optical loss.

[0037] (Semiconductor layer 10) The semiconductor layer 10 is, for example, In x Al y Ga 1-x-y N (0≦x≦1, 0≦y≦1, x+y≦1). For example, when the material of the semiconductor layer 10 is GaN, the semiconductor layer 10 may contain impurities and include a semiconductor layer of a first conductivity type. Examples of impurities include silicon, germanium, and magnesium. When the semiconductor layer 10 includes n-type GaN as the semiconductor layer of the first conductivity type, the impurity concentration is, for example, 1×10 17 cm -3 More than 1×10 19 cm -3 Silicon or germanium can be doped so as to satisfy the following conditions. The impurity concentration can be analyzed by secondary ion mass spectroscopy (SIMS). The semiconductor layer 10 may also include an undoped semiconductor layer in part. An undoped semiconductor layer is a semiconductor layer into which no impurities have been intentionally introduced. However, the undoped semiconductor layer may unavoidably contain impurities during the manufacturing process. The concentrations of n-type impurities and p-type impurities contained in the undoped semiconductor layer are, for example, 1×10 17 cm ―3The concentration of n-type impurities and p-type impurities in the undoped semiconductor layer may be, for example, a concentration below the detection limit in the analysis result of SIMS or the like. The thickness of the semiconductor layer 10 may be, for example, 0.1 μm or more and 10 μm or less.

[0038] (First semiconductor layers 24a and 24b) The first semiconductor layers 24a and 24b include one or more semiconductor layers of a first conductivity type. The semiconductor layer of the first conductivity type is, for example, a nitride semiconductor layer, and the first conductivity type may be either n-type or p-type. The first conductivity type may be, for example, n-type. The n-type impurity is, for example, silicon (Si) or germanium (Ge). The semiconductor layer 10 and the first semiconductor layers 24a and 24b may be the same nitride semiconductor layer. In this case, the refractive indexes of these layers can be made equal to each other. As a result, there is no difference in the refractive index between the semiconductor layer 10 and the first semiconductor layers 24a and 24b, so that confinement of light emitted from the first active layer and the second active layer described later is unlikely to occur. Therefore, it is possible to easily generate light coupling through the first region 11.

[0039] (First active layer 25a and second active layer 25b) The first active layer 25a is provided between the first semiconductor layer 24a and the second semiconductor layer 26a. The second active layer 25b is provided between the first semiconductor layer 24b and the third semiconductor layer 26b. Each active layer is a light emitting layer. Each active layer may be, for example, a nitride semiconductor layer that emits light with an emission peak wavelength range of 200 nm to 760 nm. The emission peak wavelength is preferably 250 nm to 570 nm. Each active layer has, for example, a multiple quantum well structure having a plurality of well layers and a plurality of barrier layers. When each active layer is a quantum well structure that emits light in the above wavelength range, the well layer and the barrier layer are, for example, GaN, InGaN, AlGaN, or AlInGaN, and the well layer is, for example, AlGaN, GaN, or InGaN. Note that a superlattice layer in which undoped GaN layers and undoped InGaN layers are alternately stacked may be formed between the first semiconductor layer 24a and the first active layer 25a or between the first semiconductor layer 24b and the second active layer 25b.

[0040] (Second semiconductor layer 26a and third semiconductor layer 26b) The second semiconductor layer 26a and the third semiconductor layer 26b each include one or more semiconductor layers of a second conductivity type different from the first conductivity type. The second conductivity type semiconductor layer is, for example, a nitride semiconductor layer, and the second conductivity type can be p-type. The p-type impurity is, for example, magnesium (Mg). The second semiconductor layer 26a and the third semiconductor layer 26b may each include an undoped semiconductor layer. The p-type impurity is, for example, 1×10 17 cm -3 More than 1×10 21 cm -3 The following may be included:

[0041] The sizes of the first ridge 20a and the second ridge 20b are as follows. The widths of the straight portions 21a, 21b, 22a, and 22b and the curved portions 23a and 23b included in the first ridge 20a and the second ridge 20b may be, for example, 0.5 μm or more and 10 μm or less. The height from the lower end of the first ridge to the upper end of the straight portions 21a, 21b, 22a, and 22b in the first region 11 may be, for example, 400 nm or more and 1.0 μm or less. The height from the lower end of the first ridge to the upper end of the curved portions 23a and 23b in the second region 12 may be, for example, 1.1 μm or more and 2.0 μm or less. The shortest distance between one side of the first portion (i.e., the straight portion 22a) and one side of the third portion (i.e., the straight portion 22b) facing each other is, for example, 200 nm or more and 1 μm or less, preferably 250 nm or more and 1 μm or less, and more preferably 450 nm or more and 1 μm or less. The first ridge 20a and the second ridge 20b having such sizes can be manufactured by photolithography and etching. A manufacturing method for the semiconductor device 100 according to the first embodiment will be described later.

[0042] (Calculation of the electric field distribution of light propagating in an optical waveguide) Next, the electric field distribution of the propagating light in the optical waveguide will be described with reference to FIG. 3A to FIG. 3C. FIG. 3A to FIG. 3C are diagrams showing the electric field distribution of the propagating light in the optical waveguide obtained by simulation by the beam propagation method (BPM) for the first to third examples, respectively, and show the intensity distribution of the X component Ex of the electric field in the TE (Transverse Electric) mode. The shading of the scale bar of the X component Ex of the electric field shown in FIG. 3A to FIG. 3C corresponds to the shading of the curve representing the X component Ex of the electric field. The configuration shown in FIG. 3A to FIG. 3C has a semiconductor layer extending along the XY plane, and a convex portion protruding from the semiconductor layer in the Z direction and extending along the Y direction. The convex portion functions as an optical waveguide. The semiconductor layer or the convex portion includes an active layer represented by an arrow. Note that the area other than the semiconductor layer and the convex portion is air. In the configuration shown in FIG. 3A to FIG. 3C, the portion located lower than the active layer is a semiconductor layer of the first conductivity type, and the portion located higher than the active layer is a semiconductor layer of the second conductivity type. The materials of the semiconductor layers were assumed to be GaN / InGaN / AlGaN. The widths of the protrusions shown in Figures 3A to 3C are all 1 μm. The heights of the protrusions shown in Figures 3A to 3C, i.e., the distances from the bottom end of the protrusion to the top end of the protrusion, are 600 nm, 800 nm, and 1500 nm, respectively. The thicknesses of the active layers shown in Figures 3A to 3C are all 140 nm.

[0043] (1st calculation example) In the example shown in Fig. 3A, the height of the convex portion is set to 600 nm. The convex portion shown in Fig. 3A corresponds to, for example, the straight line portions 22a and 22b.

[0044] (2nd calculation example) In the example shown in Fig. 3B, the height of the convex portion is 800 nm. The convex portion shown in Fig. 3B corresponds to, for example, the straight line portions 22a and 22b shown in Fig. 2A. In the example shown in Fig. 2A, the light propagating through one of the straight line portion 22a on the +X direction side and the straight line portion 22b on the -X direction side facing each other has a portion distributed in the first region 11 of the semiconductor layer 10. Therefore, the light propagating through the one can be efficiently coupled to the other via the first region 11.

[0045] (3rd calculation example) In the example shown in Fig. 3C, the height of the convex portion is set to 1500 nm. The convex portion shown in Fig. 3C corresponds to, for example, the curved portions 23a and 23b shown in Fig. 2B.

[0046] (calculation result) From the calculation results of the first, second, and third calculation examples, it can be seen that the lower the height of the convex portion, the more light seeps out of the convex portion. It can also be seen that light propagates more through the semiconductor layer than through the air.

[0047] From the results of the first calculation example shown in FIG. 3A and the second calculation example shown in FIG. 3B, it can be seen that light seeps from one of the straight line portion 22a and the straight line portion 22b to the other through the first region 11. This can cause optical coupling. Also, from the results of the third calculation example, it can be seen that light leakage is unlikely to occur in the curved line portion 23a. Therefore, it is possible to reduce light loss in the curved line portion 23a where optical coupling is not intended.

[0048] From the above calculation results, it can be seen that in the semiconductor element 100 according to this embodiment 1, the curved portions 23a and 23b reduce leakage of light propagating through the first ridge 20a and the second ridge 20b, and the straight portions 22a and 22b enable light propagating through one of the first ridge 20a and the second ridge 20b to be efficiently coupled to the other.

[0049] Unlike the semiconductor device 100 according to the first embodiment, the first active layer 25a included in the straight line portions 21a and 22a and the second active layer 25b included in the straight line portions 21b and 22b may be located at a position lower than the upper surface of the first region 11. However, it is preferable that the first active layer 25a and the second active layer 25b are located at a position higher than the upper surface of the first region 11. This can reduce the reflection of the propagating light that occurs at the boundary between the straight line portions 21a, 21b, 22a, and 22b and the curved line portions 23a and 23b. The smaller the difference between the distribution of the propagating light in the straight line portions 21a, 21b, 22a, and 22b and the distribution of the propagating light in the curved line portions 23a and 23b, the smaller the reflection of the propagating light that occurs at the boundary between the two. The difference between the distribution of the propagating light shown in FIG. 3B and the distribution of the propagating light shown in FIG. 3C is smaller than the difference between the distribution of the propagating light shown in FIG. 3A and the distribution of the propagating light shown in FIG. 3C. Furthermore, the threshold value of laser oscillation can be lowered when the first active layer 25a and the second active layer 25b are located higher than the upper surface of the first region 11. This is because the greater the portion of the propagating light distributed in the straight line portions 21a, 21b, 22a, and 22b, the higher the electric field intensity of the propagating light in the first active layer 25a and the second active layer 25b. The propagating light shown in FIG. 3B is distributed more in the convex portion than the propagating light shown in FIG. 3A.

[0050] For these reasons, it is desirable that the first active layer 25a and the second active layer 25b included in the straight line portions 21a, 21b, 22a, and 22b are located higher than the upper surface of the first region 11 in the semiconductor device 100 according to the first embodiment.

[0051] (Modification) Next, first to fourth modifications of the semiconductor device 100 according to the first embodiment will be described with reference to FIGS. 4A to 4D, respectively.

[0052] (Variation 1) FIG. 4A is a top view that shows a schematic configuration of a semiconductor device 110 according to a first modification of the first embodiment. The semiconductor device 110 shown in FIG. 4A differs from the semiconductor device 100 shown in FIG. 1A in that the entire region of the first ridge 20a and the second ridge 20b other than the periphery of the linear portion 22a on the +X direction side and the linear portion 22b on the -X direction side that face each other is the second region 12. The upper surface of the second region 12 is located lower than the upper surface of the first region 11. In the semiconductor device 110 according to the first modification of the first embodiment, light is easily propagated through the semiconductor layer only in the first portion of the first ridge 20a and the third portion of the second ridge 20b that face each other. Therefore, in the other portions of the first ridge 20a and the second ridge 20b, leakage of light propagating through the optical waveguide can be reduced, and light propagating through one of the first optical waveguide and the second optical waveguide can be efficiently coupled to the other.

[0053] (Variation 2) FIG. 4B is a top view that typically illustrates a configuration of a semiconductor device 120 according to Modification 2 of the first embodiment. The semiconductor device 120 illustrated in FIG. 4B differs from the semiconductor device 100 illustrated in FIG. 1A in that a plurality of ridges 20 are arranged two-dimensionally. In each ridge 20, a portion that faces another ridge 20 corresponds to the first portion or the third portion in the first embodiment. In the plurality of ridges 20, the first region 11 is located between two straight portions that face each other among two ridges adjacent to each other in the X direction and the Y direction in a top view. The curved portion included in each ridge 20 is provided in the second region 12. The optical waveguides included in each ridge 20 interact with each other. Each ridge 20 has a generally rectangular ring shape in a top view. The plurality of ridges 20 may include a plurality of types of ridges that are different in size and / or shape. The semiconductor device 120 may be a topological insulator laser device.

[0054] (Variation 3) FIG. 4C is a top view that typically illustrates a configuration of a semiconductor device 130 according to Modification 3 of the first embodiment. The semiconductor device 130 illustrated in FIG. 4A differs from the semiconductor device 100 illustrated in FIG. 1A in that one of the two ridges does not have a closed ring shape. The semiconductor device 130 illustrated in FIG. 4C includes a third ridge 20c and a fourth ridge 20d. The third ridge 20c has a ring shape, and the fourth ridge 20d has a U-shape. The third ridge 20c has two straight line portions 22c that extend along the Y direction, and two curved line portions 23c that have a semicircular arc shape. Each curved line portion 23c is connected to the two straight line portions 22c. The third ridge 20c includes a third optical waveguide. The fourth ridge 20d includes a fourth optical waveguide. The fourth ridge 20d has two straight line portions 21d extending in the X direction, a straight line portion 22d extending in the Y direction, and two curved line portions 23d having a quarter-circular arc shape. Each curved line portion 23d is connected to the straight line portion 21d and the straight line portion 22d. In top view, the first region 11 is located between the straight line portion 22c (i.e., the first portion) and the straight line portion 22d (i.e., the third portion) of the third ridge 20c and the fourth ridge 20d that face each other on the +X direction side. The curved line portion 23c (i.e., the second portion) and the curved line portion 23d are provided in the second region 12. The upper surface of the second region 12 is located lower than the upper surface of the first region 11.

[0055] The semiconductor element 130 is capable of coupling laser light generated in the third ridge 20c to the fourth ridge 20d via the first region 11. The coupled laser light can be extracted from both ends or one end of the fourth ridge 20d.

[0056] (Variation 4) FIG. 4D is a top view that illustrates a configuration of a semiconductor device 140 according to Modification 4 of the first embodiment. The semiconductor device 140 illustrated in FIG. 4D differs from the semiconductor device 100 illustrated in FIG. 1A in that both of the two ridges are not in a closed ring shape. The semiconductor device 140 illustrated in FIG. 4D includes a fifth ridge 20e and a sixth ridge 20f. The fifth ridge 20e and the sixth ridge 20f each have a U-shape. The fifth ridge 20e has two straight line portions 21e extending in the X direction, a straight line portion 22e extending in the Y direction, and two curved line portions 23e having a quarter-circular arc shape. Each curved line portion 23e is connected to the straight line portion 21e and the straight line portion 22e. The sixth ridge 20f has two straight line portions 21f extending in the X direction, a straight line portion 22f extending in the Y direction, and two curved line portions 23f having a quarter-circular arc shape. Each curved portion 23f is connected to a straight portion 21f and a straight portion 22f. The fifth ridge 20e and the sixth ridge 20f are arranged such that the straight portion 22e and the straight portion 22f face each other. The first region 11 is located between the straight portion 22e and the straight portion 22f facing each other. The curved portions 23e and 23f are provided in the second region 12. The upper surface of the second region 12 is located lower than the upper surface of the first region 11.

[0057] The semiconductor element 140 functions as the following optical circuit. Light incident on one of the lower or upper ends of the fifth ridge 20e is efficiently coupled to the sixth ridge 20f via the first region 11. The coupled light is emitted from one of the upper or lower ends of the sixth ridge 20f.

[0058] (Embodiment 2) Next, with reference to FIG. 5A to FIG. 5C, a configuration example of a semiconductor device according to the second embodiment of the present disclosure will be described. FIG. 5A is a perspective view that shows a schematic configuration of a semiconductor device 200 according to the second exemplary embodiment of the present disclosure. The semiconductor device 200 shown in FIG. 5A includes an insulating layer 32, a first electrode 30a, and a second electrode 30b in addition to the components included in the semiconductor device 100 shown in FIG. 1A. According to the second embodiment, laser oscillation by current injection is possible. FIG. 5B is a top view of the semiconductor device 200 shown in FIG. 5A. The dashed line portion shown in FIG. 5B represents the first ridge 20a, the second ridge 20b, and the second region 12 located below the second electrode 30b. The same applies to the following FIGS. 6B and 7B. As shown in FIG. 5B, the top surface of the second electrode 30b reflects the shapes of the first ridge 20a, the second ridge 20b, and the second region 12. FIG. 5C is a VC-VC line cross-sectional view of the semiconductor device 200 shown in FIG. 5B. As shown in FIG. 5C, the insulating layer 32 is provided on the upper surface of the semiconductor layer 10, the side surface of the first ridge 20a, and the side surface of the second ridge 20b. The insulating layer 32 is not provided on the upper surface of the first ridge 20a and the upper surface of the second ridge 20b. In FIG. 5C, the upper surfaces of the curved portions 23a and 23b are shown as parts of the upper surfaces of the first ridge 20a and the second ridge 20b. The first electrode 30a is provided on the lower surface of the semiconductor layer 10. The first electrode 30a is electrically connected to the lower surface of the semiconductor layer 10. The second electrode 30b is provided on the upper surface of the insulating layer 32 and the upper surfaces of the first ridge 20a and the second ridge 20b. The second electrode 30b is electrically connected to the upper surfaces of the first ridge 20a and the second ridge 20b. That is, according to the second embodiment, the first ridge 20a and the second ridge 20b are electrically connected in parallel.

[0059] By applying a voltage to the first electrode 30a and the second electrode 30b, a current can be injected into the first ridge 20a and the second ridge 20b. For example, the first electrode 30a may be a negative electrode and the second electrode 30b may be a positive electrode.

[0060] The insulating layer 32 may be formed of at least one insulating material selected from the group consisting of, for example, SiO2, ZnO, Nb2O5, TiO2, and Al2O3.

[0061] The first electrode 30a and the second electrode 30b may be formed of at least one metal selected from the group consisting of, for example, Ag, Ti, Pt, and Au.

[0062] (Modification of the second embodiment) Next, with reference to FIG. 6A to FIG. 6C, a configuration example of a semiconductor device according to a modification of the embodiment 2 of the present disclosure will be described. FIG. 6A is a perspective view that shows a schematic configuration of a semiconductor device 210 according to a modification of the embodiment 2 of the present disclosure. The semiconductor device 210 according to the modification of the embodiment 2 is different from the semiconductor device 200 according to the embodiment 2 in that the semiconductor layer 10 has a bottom 10a extending in the XY plane and a protruding portion 10b protruding from the bottom 10a in the Z direction, and a first electrode 30a is provided on the upper surface of the bottom 10a. The first electrode 30a is electrically connected to the upper surface of the bottom 10a of the semiconductor layer 10. FIG. 6B is a top view of the semiconductor device 210 shown in FIG. 6A. As shown in FIG. 6B, the first electrode 30a is arranged so as to surround the second electrode 30b in a top view. FIG. 6C is a cross-sectional view of the semiconductor device 210 shown in FIG. 6B along the VIC-VIC line. As shown in FIG. 6C, the configuration in which the first active layer 25a and the second active layer 25b are located above the protruding portion 10b included in the semiconductor layer 10 is the same as the configuration in the second embodiment.

[0063] In the semiconductor element 200 according to the second embodiment, the first electrode 30a and the second electrode 30b are located on opposite sides of the semiconductor layer 10. In contrast, in the semiconductor element 210 according to the modified example of the second embodiment, the first electrode 30a and the second electrode 30b are located on the same side of the semiconductor layer 10.

[0064] (Embodiment 3) According to the third embodiment, the upper surface of the second electrode 30b shown in FIG. 5A can be flattened. Next, with reference to FIGS. 7A to 7C, a configuration example of a semiconductor device according to the third embodiment of the present disclosure will be described. FIG. 7A is a perspective view that shows a schematic configuration of a semiconductor device 300 according to the third exemplary embodiment of the present disclosure. The semiconductor device 300 shown in FIG. 7A is different from the semiconductor device 200 shown in FIG. 5A in that the upper surface of the second electrode 30b is flat. FIG. 7B is a top view of the semiconductor device 300 shown in FIG. 7A. As shown in FIG. 7B, the upper surface of the second electrode 30b does not reflect the shapes of the first ridge 20a, the second ridge 20b, and the second region 12 located thereunder. FIG. 7C is a cross-sectional view of the semiconductor device 300 shown in FIG. 7B along the line VIIC-VIIC. As shown in FIG. 7C, the upper surface of the insulating layer 32 and the upper surfaces of the first ridge 20a and the second ridge 20b are located on the same plane that is parallel to the XY plane. A second electrode 30b is provided on the upper surface of the insulating layer 32 and on the upper surfaces of the first ridge 20a and the second ridge 20b. The second electrode 30b is electrically connected to the upper surfaces of the first ridge 20a and the second ridge 20b. This makes it easy to form additional wiring from the outside of the semiconductor element 300 to the second electrode 30b.

[0065] (Method of manufacturing semiconductor device) A manufacturing method for a semiconductor element of one embodiment according to the present disclosure includes the steps of preparing a semiconductor laminate; etching the semiconductor laminate to form a semiconductor layer, a first ridge provided on the semiconductor layer, the first ridge having a first portion and a second portion including a bending region connected to the first portion, and a second ridge provided on the semiconductor layer, the second ridge having a third portion opposite the first portion; and further etching the semiconductor laminate to make a lower end of the first ridge in a portion forming the bending region lower than a lower end of the first ridge in a portion forming the first portion.

[0066] The method for manufacturing a semiconductor element according to the present disclosure makes it possible to manufacture a semiconductor element capable of efficiently coupling propagating light from one portion to the other portion between two portions facing each other.

[0067] An example of a method for manufacturing the semiconductor device 100 according to the embodiment 1 will be described below with reference to Figures 8A to 8J. Figures 8A to 8J are views for explaining an example of steps in the method for manufacturing the semiconductor device 100 according to the embodiment 1.

[0068] Fig. 8A is a top view showing a manufacturing process of a semiconductor device, and Fig. 8B is a cross-sectional view taken along line VIIIB-VIIIB in Fig. 8A. In the first step, a semiconductor laminate 10S is prepared as shown in Fig. 8A. As shown in Fig. 8B, the semiconductor laminate 10S has a laminate structure including a first conductive type semiconductor layer 24, an active layer 25, and a second conductive type semiconductor layer 26 in this order.

[0069] FIG. 8C is a top view showing a manufacturing process of a semiconductor device, and FIG. 8D is a cross-sectional view taken along line VIIID-VIIID in FIG. 8C. In the next step, as shown in FIG. 8C, a first photoresist 40a and a second photoresist 40b are provided on the second conductive type semiconductor layer 26. As shown in FIG. 8C, each of the first photoresist 40a and the second photoresist 40b has a generally rectangular ring shape in a top view. The first photoresist 40a includes two straight line portions 41a extending along the X direction, two straight line portions 42a extending along the Y direction, and four curved line portions 43a. Each curved line portion 43a is connected to the straight line portion 41a extending along the X direction and the straight line portion 42a extending along the Y direction. Similarly, the second photoresist 40b includes two straight line portions 41b extending along the X direction, two straight line portions 42b extending along the Y direction, and four curved line portions 43b. Each curved portion 43b is connected to a straight portion 41b extending along the X direction and a straight portion 42b extending along the Y direction.

[0070] The first photoresist 40a and the second photoresist 40b are formed by applying a layered photoresist to the upper surface of the second conductive type semiconductor layer 26 and patterning the photoresist by photolithography. The distance between one side of the linear portion 42a on the +X direction side and the side of the linear portion 42b on the -X direction side facing each other may be, for example, 200 nm or more and 1 μm or less. Considering the ease of processing by photolithography, the distance may be, for example, 500 nm or more and 1 μm or less. Note that electron beam lithography may be used instead of photolithography. Photolithography is preferable from the viewpoint of lead time. As shown in FIG. 8C and FIG. 8D, the second conductive type semiconductor layer 26 has an upper surface exposed from the first photoresist 40a and the second photoresist 40b.

[0071] FIG. 8E is a top view showing a manufacturing process of a semiconductor device, and FIG. 8F is a cross-sectional view taken along line VIIIF-VIIIF in FIG. 8E. In the next step, a part of the semiconductor laminate 10S shown in FIG. 8C is removed by etching from the exposed upper surface of the second conductive type semiconductor layer 26 to a predetermined depth as shown in FIG. 8E and FIG. 8F. The etching may be dry etching or wet etching. The etching depth is greater than the sum of the thickness of the active layer 25 and the thickness of the second conductive type semiconductor layer 26. The etching depth may be less than the sum. The etching forms a semiconductor layer extending along the XY plane and two convex portions each having a ring shape located on the semiconductor layer. Of the convex portions on the -X direction side, the portions located directly below the straight line portions 41a and 42a shown in FIG. 8E correspond to the straight line portions 21a and 22a included in the first ridge 20a shown in FIG. 1B. Of the convex portion on the +X direction side, the portion located directly below the straight line portions 41b and 42b shown in Fig. 8E corresponds to the straight line portions 21b and 22b included in the second ridge 20b shown in Fig. 1B. Of the first conductivity type semiconductor layer 24 shown in Fig. 8E, the portion located between the straight line portion 42a on the +X direction side and the straight line portion 42b on the -X direction side that face each other in top view corresponds to the first region 11 shown in Fig. 1B.

[0072] The above etching forms straight line portions 21a and 22a included in first ridge 20a, straight line portions 21b and 22b included in second ridge 20b, and first region 11. As shown in Figures 8E and 8F, first conductivity type semiconductor layer 24 has an upper surface exposed from first photoresist 40a and second photoresist 40b.

[0073] FIG. 8G is a top view showing a manufacturing process of a semiconductor device, and FIG. 8H is a cross-sectional view taken along line VIIIH-VIIIH in FIG. 8G. In the next step, a third photoresist 40c is provided on the upper surface of the first conductive type semiconductor layer 24 shown in FIG. 8E that is exposed from the first photoresist 40a and the second photoresist 40b, as shown in FIG. 8G and FIG. 8H. As shown in FIG. 8G, the third photoresist 40c is removed from the peripheral portions of the curved portions 43a and 43b in a top view. The removed portion would have a roughly rectangular shape in a top view if the first photoresist 40a and the second photoresist 40b were not present. The third photoresist 40c is formed by patterning using photolithography. Electron beam lithography may be used instead of photolithography. As shown in FIG. 8G and FIG. 8H, the first conductive type semiconductor layer 24 has an upper surface that is exposed from the first photoresist 40a, the second photoresist 40b, and the third photoresist 40c.

[0074] FIG. 8I is a top view showing a manufacturing process of a semiconductor device, and FIG. 8J is a cross-sectional view taken along line VIIIJ-VIIIJ in FIG. 8I. In the next step, a part of the first conductive type semiconductor layer 24 shown in FIG. 8G is removed by etching from the upper surface of the first conductive type semiconductor layer 24 exposed from the first photoresist 40a, the second photoresist 40b, and the third photoresist 40c to a predetermined depth, as shown in FIG. 8I and FIG. 8J. The dashed leader line shown in FIG. 8I represents the semiconductor layer 10 and the first region 11 located under the third photoresist 40c. As a result of the recess being formed by etching, the semiconductor layer 10 including the first region 11 and the second region 12 is formed, as shown in FIG. 8I. The part located directly below the curved portion 43a shown in FIG. 8I corresponds to the curved portion 23a included in the first ridge 20a shown in FIG. 1B. The part located directly below the curved portion 43b shown in FIG. 8I corresponds to the curved portion 23b included in the second ridge 20b shown in FIG. 1B. By the above etching, curved portion 23a included in first ridge 20a, curved portion 23b included in second ridge 20b, and semiconductor layer 10 including first region 11 and second region 12 are formed.

[0075] In the next step, the first to third photoresists 40a to 40c are removed from the structure shown in FIGS. 8I and 8J.

[0076] Through the above steps, the semiconductor device 100 according to embodiment 1 shown in Fig. 1A can be manufactured. The manufacturing process of the semiconductor device 100 according to embodiment 1 includes a step of preparing a semiconductor stack 10S and an etching step of etching the semiconductor stack 10S. The etching step includes forming the semiconductor layer 10, the first ridge 20a, the second ridge 20b, and the first region 11 and the second region included in the semiconductor layer 10 in the semiconductor device 100 shown in Fig. 1A.

[0077] The process of manufacturing the semiconductor device 200 according to the second embodiment shown in FIG. 5A includes the process of manufacturing the semiconductor device 100 according to the first embodiment, as well as the process of providing an insulating layer 32, a first electrode 30a, and a second electrode 30b. The process of providing the insulating layer 32 includes providing the insulating layer 32 on the upper surface of the semiconductor layer 10, the side surface of the first ridge 20a, and the side surface of the second ridge 20b, as shown in FIG. 5C. The process of providing the first electrode 30a includes providing the first electrode 30a on the lower surface of the semiconductor layer 10. The process of providing the second electrode 30b includes providing the second electrode 30b on the upper surface of the insulating layer 32 and the upper surfaces of the first ridge 20a and the second ridge 20b. The process of manufacturing the semiconductor device 300 according to the third embodiment is the same as the process of manufacturing the semiconductor device 200 according to the second embodiment, except that the shape of the insulating layer 32 shown in FIG. 7C is different from the shape of the insulating layer 32 shown in FIG. 5C.

[0078] (Example) Next, examples 1 and 2 of the semiconductor device 100 according to the first embodiment and a comparative example will be described with reference to Figures 9 to 11. The semiconductor devices according to examples 1 and 2 and the comparative example were manufactured by photolithography and etching. In the following, the semiconductor devices according to examples 1 and 2 will be described using the same reference symbols as those shown in Figure 1A.

[0079] Example 1 In Example 1, the semiconductor layer 10, the first ridge 20a, and the second ridge 20b were formed of GaN. The widths of the straight line portions 21a, 22a, 21b, and 22b and the curved line portions 23a and 23b were 1 μm, the lengths of the straight line portions 21a, 21b, 22a, and 22b were 10 μm, and the radii of curvature of the curved line portions 23a and 23b were 20 μm. The distance between one side of the straight line portion 22a and one side of the straight line portion 22b facing each other was 0.6 μm. The distance from the upper surface of the first region 11 to the upper surfaces of the straight line portions 21a, 21b, 22a, and 22b was 0.67 μm. The distance from the upper surface of the second region 12 to the upper surfaces of the curved line portions 23a and 23b was 1.5 μm. The distance between the upper surfaces of the straight line portions 21a, 21b, 22a, and 22b and the curved line portions 23a and 23b and the upper surfaces of the first active layer 25a and the second active layer 25b was 170 μm.

[0080] Example 2 The semiconductor device according to Example 2 differs from Example 1 in the following respects: In Example 2, the straight line portions 21a, 21b, 22a, and 22b each had a length of 15 μm.

[0081] (Comparative Example) FIG. 9 is a top view showing a schematic configuration of a semiconductor device according to a comparative example. As shown in FIG. 9, the semiconductor device according to the comparative example is different from the semiconductor devices according to the first and second examples in that the heights from the bottom to the top of the ridges of the straight line portions 21a, 21b, 22a, and 22b, and the heights from the bottom to the top of the ridges of the curved line portions 23a and 23b are all 2 μm. That is, the semiconductor device according to the comparative example does not distinguish between the first and second regions, and the heights from the bottom to the top of each ridge are the same in each straight line portion and curved line portion. Also, the semiconductor device according to the comparative example is different from the first and second examples in that the lengths of the straight line portions 21a, 21b, 22a, and 22b are 20 μm.

[0082] (Photoluminescence measurement) Photoluminescence measurements (PL measurements) were performed on the semiconductor elements according to Example 1, Example 2, and Comparative Example. Each semiconductor element was excited by laser light emitted from a solid-state laser device. The wavelength of the laser light was 355 nm. In the optical excitation, the first optical waveguide alone, the second optical waveguide alone, or both the first optical waveguide and the second optical waveguide were irradiated with the laser light. When either the first or second optical waveguide was irradiated alone, the other was covered with a light shielding plate.

[0083] 10A and 10B are graphs showing the oscillation spectrum of laser light generated when the semiconductor elements according to the first and second examples are optically excited, respectively. The oscillation spectrum shows multiple peaks at multiple resonance wavelengths. As shown in FIG. 10A and FIG. 10B, the resonance wavelength was different when only one of the first optical waveguide located on the left side and the second optical waveguide located on the right side was excited compared to when both were excited. When both were excited, laser light with a resonance wavelength that could not be obtained when only one was excited was generated. This is because when both were excited, light propagating through one of the first optical waveguide and the second optical waveguide is coupled to the other.

[0084] Fig. 11 is a graph showing the oscillation spectrum of laser light generated when the semiconductor element according to the comparative example is optically excited. As shown in Fig. 11, the resonance wavelength and oscillation intensity were almost the same when only one of the left and right optical waveguides was excited and when both were excited. Therefore, in the comparative example, no clear oscillation was observed, which is presumed to have occurred as a result of light propagating through one of the two optical waveguides being coupled to the other.

[0085] As shown by the dashed circle, when both are excited, there is a peak that does not appear when only one is excited. It is presumed that this is not the result of the coupling of propagating light in the first optical waveguide and the second optical waveguide. The height of the ridge of the semiconductor element according to the comparative example is higher than that in the simulation shown in FIG. 3C, and it is considered that the light is strongly confined within the optical waveguide. Therefore, it is predicted that it is difficult for light to couple from one optical waveguide to the other waveguide that is a distance longer than the resonant wavelength. The reason why there is a peak when both are excited and when only one is excited is thought to be that the place where the excitation light hits when only one is excited does not strictly match when both are excited.

[0086] Table 1 shows the difference in structure between Example 1, Example 2, and the Comparative Example, and the presence or absence of optical coupling. Example 1 and Example 2 are significantly different from the Comparative Example in the height of the straight line portion. It was presumed that no optical coupling occurred between the two optical waveguides in the Comparative Example, in which the height of the straight line portion is relatively large. In contrast, it was presumed that optical coupling occurred between the two optical waveguides in Examples 1 and 2, in which the height of the straight line portion is relatively small.

[0087] [Table 1]

[0088] The present disclosure includes semiconductor devices and methods for manufacturing semiconductor devices as described in the following sections. [Item 1] A semiconductor layer; a first ridge provided on the semiconductor layer; a second ridge provided on the semiconductor layer; A semiconductor device comprising: the first ridge has a first portion and a second portion including a bend region connected to the first portion; the second ridge has a third portion opposing the first portion; the semiconductor layer has a first region located between the first portion and the third portion, and a second region in which the second portion is provided, a height from a lower end to an upper end of the first ridge in the first region is lower than a height from a lower end to an upper end of the first ridge in the second region. [Item 2] A semiconductor layer; a first ridge provided on the semiconductor layer; a second ridge provided on the semiconductor layer; A semiconductor device comprising: the first ridge has a first portion and a second portion connected to the first portion; the second ridge has a third portion opposing the first portion; the second portion has a portion extending in a direction from the third portion toward the first portion, a distance between the second portion and the third portion is greater than a distance between the first portion and the third portion; the semiconductor layer has a first region located between the first portion and the third portion, and a second region in which the second portion is provided, a height from a lower end to an upper end of the first ridge in the first region is lower than a height from a lower end to an upper end of the first ridge in the second region. [Item 3] 3. The semiconductor element according to item 1 or 2, wherein the shortest distance between one side of the first portion and one side of the third portion is 200 nm or more and 1 μm or less. [Item 4] a height from the lower end to the upper end of the first ridge is not less than 400 nm and not more than 1.0 μm; 4. The semiconductor element according to claim 1, wherein the height from the lower end to the upper end of the first ridge is not less than 1.1 μm and not more than 2.0 μm. [Item 5] 5. The semiconductor element according to any one of claims 1 to 4, wherein the first ridge has a ring shape in a top view. [Item 6] 6. The semiconductor element of any one of claims 1 to 5, wherein the second ridge has a ring shape in a top view. [Item 7] the first ridge is included in a first optical waveguide; the second ridge is included in a second optical waveguide; 7. The semiconductor element according to any one of items 1 to 6, wherein a peak wavelength of light propagating through the first optical waveguide and the second optical waveguide is not less than 250 nm and not more than 570 nm. [Item 8] the first optical waveguide includes a first semiconductor layer of a first conductivity type, a first active layer, and a second semiconductor layer of a second conductivity type different from the first conductivity type, in this order from the semiconductor layer side; 8. The semiconductor element according to claim 7, wherein the second optical waveguide comprises the first semiconductor layer, a second active layer, and a third semiconductor layer of the second conductivity type, in this order from the semiconductor layer side. [Item 9] 9. The semiconductor device of claim 8, wherein the refractive index of the semiconductor layer and the refractive index of the first semiconductor layer are equal to each other. [Item 10] 10. The semiconductor element according to item 8 or 9, wherein the first active layer of the second portion is located at a position higher than the lower end of the first ridge in the second region. [Item 11] 11. The semiconductor element according to any one of claims 8 to 10, wherein the first active layer of the first portion is located at a position higher than the lower end of the first ridge in the first region. [Item 12] Item 12. The semiconductor device according to any one of items 8 to 11, wherein the semiconductor layer, the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, the first active layer, and the second active layer are nitride semiconductor layers. [Item 13] providing a semiconductor laminate; Etching the semiconductor laminate A semiconductor layer; a first ridge provided on the semiconductor layer, the first ridge having a first portion and a second portion including a bent region connected to the first portion; a second ridge provided on the semiconductor layer and having a third portion facing the first portion; and forming further etching the semiconductor laminate to make a lower end of the first ridge in a portion forming the bending region lower than a lower end of the first ridge in a portion forming the first portion; A method for manufacturing a semiconductor device comprising the steps of: [Item 14] Item 14. The method for manufacturing a semiconductor device according to item 13, wherein the etching is performed by photolithography. [Item 15] A semiconductor layer; a first optical waveguide including a first ridge disposed on the semiconductor layer; a second optical waveguide including a second ridge disposed on the semiconductor layer; having the first optical waveguide includes a first straight waveguide and a first bent waveguide connected to the first straight waveguide; the second optical waveguide includes a second linear waveguide facing the first linear waveguide, a height from a lower end to an upper end of the first ridge in the first straight waveguide is lower than a height from a lower end to an upper end of the first ridge in the first curved waveguide. [Industrial Applicability]

[0089] The semiconductor element of the present disclosure can be applied to various optical devices such as, for example, a semiconductor laser element or an optical integrated circuit. [Explanation of symbols]

[0090] 10: semiconductor layer 10a: bottom 10b: convex portion 10S: semiconductor laminate 11: first region 12: second region 20: ridge 20a: first ridge 20b: second ridge 20c: third ridge 20d: fourth ridge 20e: fifth ridge 20f: sixth ridge 21a, 21b, 21d, 21e, 21f: straight line portion 22a, 22b, 22c, 22d, 22e, 22f: straight line portion 23a, 23b, 23c, 23d, 23e, 23f: curved portion 24: first conductive type semiconductor layer 24a, 24b: first semiconductor layer 25: active layer 25a: first active layer 25b: second active layer 26: second conductive type semiconductor layer 26a: second semiconductor layer 26b: third semiconductor layer 30a: first electrode 30b: second electrode 32: insulating layer 40a: first photoresist 40b: second photoresist 40c: third photoresist 41a, 41b, 42a, 42b: straight line portion 43a, 43b: curved line portion 100, 110, 120, 130, 140: semiconductor element 200, 210: semiconductor element 300: semiconductor element

Claims

1. A semiconductor layer; a first ridge provided on the semiconductor layer; a second ridge provided on the semiconductor layer; A semiconductor device comprising: the first ridge has a first portion and a second portion including a bend region connected to the first portion; the second ridge has a third portion opposing the first portion; the semiconductor layer has a first region located between the first portion and the third portion, and a second region in which the second portion is provided, A semiconductor device, wherein a height from a lower end to an upper end of the first ridge in the first region is lower than a height from a lower end to an upper end of the first ridge in the second region.

2. A semiconductor layer; a first ridge provided on the semiconductor layer; a second ridge provided on the semiconductor layer; A semiconductor device comprising: the first ridge has a first portion and a second portion connected to the first portion; the second ridge has a third portion opposing the first portion; the second portion has a portion extending in a direction from the third portion toward the first portion, a distance between the second portion and the third portion is greater than a distance between the first portion and the third portion; the semiconductor layer has a first region located between the first portion and the third portion, and a second region in which the second portion is provided, A semiconductor device, wherein a height from a lower end to an upper end of the first ridge in the first region is lower than a height from a lower end to an upper end of the first ridge in the second region.

3. The semiconductor element according to claim 1 , wherein the shortest distance between one side surface of the first portion and one side surface of the third portion is not less than 200 nm and not more than 1 μm.

4. a height from the lower end to the upper end of the first ridge in the first region is not less than 400 nm and not more than 1.0 μm; The semiconductor device according to claim 1 , wherein a height from the lower end to the upper end of the first ridge in the second region is not less than 1.1 μm and not more than 2.0 μm.

5. The semiconductor device according to claim 1 , wherein the first ridge has a ring shape in a top view.

6. The semiconductor device according to claim 1 , wherein the second ridge has a ring shape in a top view.

7. the first ridge is included in a first optical waveguide; the second ridge is included in a second optical waveguide; 3. The semiconductor device according to claim 1, wherein a peak wavelength of light propagating through the first optical waveguide and the second optical waveguide is not less than 250 nm and not more than 570 nm.

8. the first optical waveguide includes a first semiconductor layer of a first conductivity type, a first active layer, and a second semiconductor layer of a second conductivity type different from the first conductivity type, in this order from the semiconductor layer side; the second optical waveguide includes the first semiconductor layer, a second active layer, and a third semiconductor layer of the second conductivity type, in this order from the semiconductor layer side; The semiconductor device according to claim 7.

9. The semiconductor device according to claim 8 , wherein the refractive index of the semiconductor layer and the refractive index of the first semiconductor layer are equal to each other.

10. The semiconductor device according to claim 8 , wherein the first active layer of the second portion is located higher than the lower end of the first ridge in the second region.

11. The semiconductor device according to claim 8 , wherein the first active layer of the first portion is located higher than the lower end of the first ridge in the first region.

12. The semiconductor device according to claim 8 , wherein the semiconductor layer, the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, the first active layer, and the second active layer are nitride semiconductor layers.

13. providing a semiconductor laminate; Etching the semiconductor laminate A semiconductor layer; a first ridge provided on the semiconductor layer, the first ridge having a first portion and a second portion including a bent region connected to the first portion; a second ridge provided on the semiconductor layer and having a third portion facing the first portion; and forming further etching the semiconductor laminate to make a lower end of the first ridge in a portion forming the bending region lower than a lower end of the first ridge in a portion forming the first portion; A method for manufacturing a semiconductor device comprising the steps of:

14. The method for manufacturing a semiconductor device according to claim 13, wherein the etching is performed by photolithography.

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