Voltage detection circuit

Abstract

To detect the voltage in the wide range accurately while suppressing the occurrence of leak current.SOLUTION: A capacitive coupling driving unit 14 generates driving signals for driving gates of MOS transistors 15 to 22 with a potential of a selection signal output from a selector 13 as a reference potential. The capacitive coupling driving unit 14 supplies the generated driving signals to the gates of the MOS transistors 15 to 22 included in switches S1 to S4. The selector 13 includes two PMOS 26 and 27 connected in series between a pair of input nodes Nip and Nim, and two NMOS 29 and 30 connected in series between the pair of input nodes Nip and Nim. One of the two PMOS and NMOS is a normal MOS transistor having a normal threshold and the other of the two PMOS and NMOS is a low-threshold MOS transistor having a lower threshold than the normal threshold.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a voltage detection circuit having a fully differential configuration. [Background technology]

[0002] Patent Document 1 discloses a voltage detection circuit with a fully differential configuration that employs a switch circuit called a CCSW circuit. CCSW is an abbreviation for Capacitively-Coupled Switch. Hereinafter, the voltage detection circuit disclosed in Patent Document 1 will be referred to as the prior art. The prior art is configured with a selector that provides the higher of the voltages at two input nodes as the substrate potential of a P-channel MOS transistor and provides the lower of the voltages at the two input nodes as the substrate potential of an N-channel MOS transistor. [Prior art documents] [Non-patent literature]

[0003] [Patent Document 1] Patent No. 6673150 Summary of the Invention [Problem to be solved by the invention]

[0004] The conventional technology is assumed to be used in a battery monitoring IC that monitors the voltage of a battery. Note that IC is an abbreviation for Integrated Circuit. In battery monitoring ICs, the voltage range that can be detected is expanding year by year as the number of types of batteries to be detected increases. Since changing the IC design for each type of battery leads to an increase in the number of product types, it is desirable for a battery monitoring IC to be able to detect a wide range of voltages, both positive and negative, with one chip, i.e., one AFE. Note that AFE is an abbreviation for Analog Front End.

[0005] The conventional technology is suitable for applications where the voltage of a fuel cell is to be detected because it can detect negative voltages, but is not suitable for applications where the voltage of a lithium-ion battery is to be detected, for example, 0 to 5 V, because the input range of positive voltages is relatively narrow. Furthermore, with the conventional technology, there was a risk that the selector would not operate when the input voltage was near 0 V, causing a leak current and reducing the detection accuracy.

[0006] The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a voltage detection circuit that can accurately detect a wide range of voltages while suppressing the occurrence of leakage current. [Means for solving the problem]

[0007] The voltage detection circuit according to claim 1 is a fully differential voltage detection circuit that receives the voltages of a pair of input nodes (Nip, Nim), detects the difference voltage between them, and outputs it from a pair of output nodes (Nop, Nom), and includes a plurality of switches (S1 to S4), a capacitive couple driving section (14), and a selector (13). The plurality of switches are composed of at least one MOS transistor (15 to 22, 52 to 55) that is provided so as to be capable of opening and closing between the pair of input nodes and the pair of output nodes. The capacitive couple driving section includes driving capacitances (Cdr1 to Cdr4) and driving sections (33, 34) that generate driving signals for driving the gates of the MOS transistors and supply the driving signals to the gates of the MOS transistors, and controls the on / off of each of the plurality of switches by driving the gates of the MOS transistors via the driving capacitances. The selector is connected between the pair of input nodes, selects one of the voltages of the pair of input nodes, and outputs a selection signal having a potential corresponding to the selected voltage.

[0008] The driving section generates the driving signal using the potential of the selection signal output from the selector as a reference potential. The selector includes two MOS transistors (26, 27, 29, 30) connected in series between the pair of input nodes. One of the two MOS transistors is a normal MOS transistor having a normal threshold, and the other of the two MOS transistors is a low-threshold MOS transistor having a threshold lower than the normal threshold. As will be described in detail later, this allows the operating range of the selector to be expanded.

[0009] According to the above configuration, when a positive voltage is input, the selector does not become unstable and no leak current occurs, so that the potential state of each of the multiple switches can be made equivalent to that of a configuration without a selector. Therefore, according to the above configuration, the input range and detection accuracy of the positive voltage can be made equivalent to that of a configuration without a selector. Furthermore, according to the above configuration, as in the conventional technology, a negative voltage can be detected by the operation of the selector. In this way, according to the above configuration, it is possible to detect a negative voltage while maintaining the input range and detection accuracy of the positive voltage at the same level as that of a configuration without a selector. Therefore, according to the above configuration, it is possible to obtain the excellent effect of being able to accurately detect a wide range of voltages while suppressing the occurrence of leak current. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram illustrating a configuration of a voltage detection circuit according to a first embodiment; [Diagram 2] FIG. 1 is a diagram showing a schematic configuration of a battery monitoring IC according to a first embodiment; [Diagram 3] FIG. 1 is a diagram showing a specific configuration example of a switch circuit according to a first embodiment; [Figure 4] FIG. 1 is a diagram for explaining the potential state of each part during a sample period when a positive voltage is input according to the first embodiment; [Diagram 5] FIG. 1 is a diagram for explaining the potential state of each part during a hold period when a positive voltage is input according to the first embodiment; [Figure 6]FIG. 1 is a diagram for explaining the potential state of each part during a sample period when a negative voltage is input according to the first embodiment; [Figure 7] FIG. 1 is a diagram showing an example of an operating range, an indeterminate range, a voltage range, and a transmission range of each unit according to the first embodiment; [Figure 8] FIG. 1 is a schematic diagram showing a configuration of a ΔΣ modulator according to a modified example; [Figure 9] FIG. 13 is a diagram showing a specific configuration example of a switch circuit according to a second embodiment; [Figure 10] FIG. 11 is a diagram illustrating a configuration of a voltage detection circuit according to a third embodiment. [Figure 11] FIG. 13 is a diagram showing a specific configuration example of a switch circuit according to a third embodiment; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, a number of embodiments will be described with reference to the drawings. Note that the same reference numerals are used to designate substantially the same components in the respective embodiments, and the description thereof will be omitted. (First embodiment) The first embodiment will be described below with reference to FIGS.

[0012] <Overall composition> As shown in Fig. 1, the voltage detection circuit 1 of this embodiment includes a fully differential switched capacitor amplifier 2 having a pair of input nodes Nip and Nim and a pair of output nodes Nop and Nom, and various circuits (not shown). In this specification, the switched capacitor amplifier may be abbreviated as SC amplifier. The voltage detection circuit 1 receives the voltage VINP of the input node Nip and the voltage VINM of the input node Nim, detects the difference voltage between them, and outputs it from the output nodes Nop and Nom. The voltage detection circuit 1 is configured as an IC mounted on a vehicle such as an automobile together with other circuit elements (not shown).

[0013] The SC amplifier 2 includes a differential output type operational amplifier 3, capacitors Cs1, Cs2, Cf1, Cf2, Cd1, and Cd2, and switches S1 to S16. The on / off of the switches S1 to S16 is controlled by a control circuit (not shown). Each of the capacitors including the capacitors Cs1, Cs2, Cf1, Cf2, Cd1, and Cd2 includes two terminals. In this specification, in order to distinguish between the two terminals of a capacitor, one of the two terminals may be referred to as a first terminal and the other of the two terminals may be referred to as a second terminal.

[0014] A first terminal of the capacitor Cs1 is connected to the inverting input terminal of the operational amplifier 3. A common potential VCM can be applied to the first terminal of the capacitor Cs1 via a switch S5. A second terminal of the capacitor Cs1 is connected to the input node Nip via a switch S1 and is connected to the input node Nim via a switch S2. A first terminal of the capacitor Cs2 is connected to the non-inverting input terminal of the operational amplifier 3. A common potential VCM can be applied to the first terminal of the capacitor Cs2 via a switch S6. A second terminal of the capacitor Cs2 is connected to the input node Nim via a switch S3 and is connected to the input node Nip via a switch S4.

[0015] In this way, the first terminals of the paired capacitors Cs1 and Cs2 in the differential configuration are connected to the input terminals of the operational amplifier 3, and function as a pair of sampling capacitors. The capacitors Cs1 and Cs2 have the same capacitance value. In this specification, the term "same capacitance value" does not only refer to capacitors whose capacitance values ​​are completely the same, but also includes capacitors whose capacitance values ​​are slightly different and not strictly the same, as long as the desired effect is achieved.

[0016] A first terminal of the capacitor Cf1 is connected to the inverting input terminal of the operational amplifier 3. A second terminal of the capacitor Cf1 is connected to the non-inverting output terminal of the operational amplifier 3 via the switch S7. That is, the capacitor Cf1 is connected between the inverting input terminal and the non-inverting output terminal of the operational amplifier 3 via the switch S7. A common potential VCM can be applied to the second terminal of the capacitor Cf1 via the switch S8.

[0017] A first terminal of the capacitor Cf2 is connected to the non-inverting input terminal of the operational amplifier 3. A second terminal of the capacitor Cf2 is connected to the inverting output terminal of the operational amplifier 3 via the switch S9. That is, the capacitor Cf2 is connected between the non-inverting input terminal and the inverting output terminal of the operational amplifier 3 via the switch S9. A common potential VCM can be applied to the second terminal of the capacitor Cf2 via the switch S10. In this way, the pair of capacitors Cf1 and Cf2 in the differential configuration are connected between the input terminal and the output terminal of the operational amplifier 3, and function as a pair of feedback capacitances. The capacitors Cf1 and Cf2 have the same capacitance value.

[0018] A first terminal of the capacitor Cd1 is connected to an inverting input terminal of the operational amplifier 3. A reference voltage VREFP can be applied to a second terminal of the capacitor Cd1 via a switch S11. A common potential VCM can be applied to a second terminal of the capacitor Cd1 via a switch S12. A reference voltage VREFM can be applied to a second terminal of the capacitor Cd1 via a switch S13. The reference voltages VREFP and VREFM are examples of DAC voltages output from a D / A converter (not shown). In this specification, the D / A converter may be abbreviated as DAC.

[0019] A first terminal of the capacitor Cd2 is connected to the non-inverting input terminal of the operational amplifier 3. A reference voltage VREFP can be applied to a second terminal of the capacitor Cd2 via a switch S14. A common potential VCM can be applied to a second terminal of the capacitor Cd2 via a switch S15. A reference voltage VREFM can be applied to a second terminal of the capacitor Cd2 via a switch S16. In this way, the capacitors Cd1 and Cd2 that form a pair in the differential configuration can store charge according to the DAC voltage, and have first terminals connected to the input terminals of the operational amplifier 3, functioning as a pair of DAC capacitances. The capacitors Cd1 and Cd2 have the same capacitance value.

[0020] Although not shown, the SC amplifier 2 includes a common mode feedback circuit that controls the common-mode level of the output voltage of the operational amplifier 3. In the above configuration, the common mode feedback circuit operates to feedback control the common-mode level of the output voltage of the operational amplifier 3 to the common potential VCM. Note that in the SC amplifier 2, the common potentials of all circuits are set to the common potential VCM.

[0021] The SC amplifier 2 samples the input voltages VINP and VINM, which are applied via a pair of input nodes Nip and Nim, using capacitors Cs1 and Cs2. The SC amplifier 2 transfers the charge sampled in this way via capacitors Cf1 and Cf2, and outputs output voltages VOUTP and VOUTM, which are the amplified input voltages VINP and VINM, from the output terminals of the operational amplifier 3. The non-inverting output terminal of the operational amplifier 3 is connected to the output node Nop. The inverting output terminal of the operational amplifier 3 is connected to the output node Nom. Therefore, the output voltages VOUTP and VOUTM are output to the subsequent circuit via the pair of output nodes Nop and Nom.

[0022] <Application example of voltage detection circuit> As shown in Fig. 2, the voltage detection circuit 1 of this embodiment can be applied to a battery monitoring IC 5 that monitors an assembled battery 4 mounted on a vehicle. The assembled battery 4 is a lithium ion battery, a fuel cell, or the like, and multiple battery cells 4a, 4b, etc. are connected in series in multiple stages. Therefore, a common mode voltage is superimposed on the multiple battery cells 4a, 4b, etc. This common mode voltage becomes higher as the battery cell is connected to the upper stage side of the assembled battery 4, i.e., the higher potential side, and the maximum value of the common mode voltage becomes a relatively high voltage of, for example, about several hundred volts. Note that Fig. 2 only illustrates two battery cells 4a, 4b, which are part of the battery cells, and the configuration corresponding to them.

[0023] The negative terminal P9 of the battery cell (not shown) located at the bottom of the battery pack 4, i.e., on the lowest potential side, is connected to the ground line Lg. The battery monitoring IC 5 has functions such as detecting the voltage between the terminals of the battery pack 4, i.e., the battery cells 4a and 4b, and amplifying the voltage. The battery monitoring IC 5 also has a function of detecting the current flowing through the battery cells 4a and 4b. The battery monitoring IC 5 has terminals P1 and P2 corresponding to the terminals of the battery cell 4a, terminals P3 and P4 corresponding to the terminals of the battery cell 4b, and a terminal P9 for supplying a ground potential of 0V.

[0024] Each terminal of the battery cell 4a is connected to terminals P1, P2 via a filter 6a. The filter 6a is an RC filter and includes resistors R1, R2 and a capacitor C1. Each terminal of the battery cell 4b is connected to terminals P3, P4 via a filter 6b. The filter 6b is an RC filter configured similarly to the filter 6a, and includes resistors R3, R4 and a capacitor C2. The terminal P9 is configured as the negative terminal of the battery cell with the lowest potential, and is connected to the ground line Lg.

[0025] The battery monitoring IC 5 includes a multiplexer 7 and a switch circuit 8 in addition to the voltage detection circuit 1. The voltage detection circuit 1 includes an SC amplifier 2, a control circuit 9, a leak cancellation circuit 10, an A / D converter 11, and various digital circuits (not shown). In this specification, the A / D converter may be abbreviated as ADC. The control circuit 9 controls the overall operation of the battery monitoring IC 5, and includes, as a part of its configuration, a capacitive couple driver that controls the on / off of the switches S1 to S4 included in the voltage detection circuit 1. The leak cancellation circuit 10 is a differential circuit that cancels the charge leaking from a pair of input nodes Nip and Nim due to the operation of the voltage detection circuit 1.

[0026] The multiplexer 7 selects one of the voltages at terminals P1 and P2, the voltages at terminals P3 and P4, etc., by switching on and off the switches Sm1, Sm2, Sm3, Sm4, etc., and outputs it to the subsequent stage. The differential analog signal selected by the multiplexer 7 is input to the voltage detection circuit 1 via a switch circuit 8 including a chop switch in which four switches Sh1, Sh2, Sh3, and Sh4 are cross-connected. In the voltage detection circuit 1, the SC amplifier 2 receives and integrates the differential analog signal, and outputs the integrated voltage to the subsequent ADC 11. When the ADC 11 receives the integrated voltage, it quantizes it into multiple levels and outputs it digitally. The digital output is output digitally after a predetermined digital processing.

[0027] According to the above configuration, a pair of input nodes Nip, Nim of the voltage detection circuit 1 can be connected to the terminals of each of the battery cells 4a, 4b, ... that make up the battery pack 4. The voltage detection circuit 1 constitutes a part of a differential sample-and-hold circuit that outputs a detection voltage corresponding to the input voltages VINP, VINM. The voltage detection circuit 1 also constitutes a part of a level shift circuit that reduces a relatively high common-mode voltage superimposed on each of the battery cells 4a, 4b, ... to a relatively low common-mode voltage.

[0028] The output voltages VOUTP and VOUTM output from the SC amplifier 2 of the voltage detection circuit 1 correspond to detection voltages corresponding to the input voltages VINP and VINM, and are converted to digital data by the ADC 11 of a differential input format. This digital data represents the detection values ​​of the input voltages VINP and VINM, and is acquired by a higher-level control device (not shown). The voltage detection circuit 1 is configured to be able to add an offset so that the output voltages VOUTP and VOUTM fall within the input voltage range of the ADC 11, for example, a voltage range of +2.5V to -2.5V.

[0029] <Specific configuration of switch circuit> In the above configuration, the multiple switches S1 to S4 connected between the pair of input nodes Nip, Nim and the pair of sampling capacitors Cs1, Cs2, together with the selector 13 and the capacitive couple driving unit 14, constitute a switch circuit 12, which is a CCSW circuit, as shown in Figures 1 and 2. Note that in Figures 1 and 2, the configurations of the selector 13 and the capacitive couple driving unit 14 are shown in a simplified manner, but their detailed configurations will be described later with reference to Figure 3. The switch circuit 12 including the switches S1 to S4 constitutes a part of the SC amplifier 2, and as a specific configuration thereof, for example, a configuration as shown in Figure 3 can be adopted.

[0030] In the following description, of the pair of input nodes Nip, Nim, the high-potential input node Nip may be referred to as the high-potential input node, and the low-potential input node Nim may be referred to as the low-potential input node. In the following description, of the multiple switches S1 to S4, the switches S1 and S4 connected to the high-potential input node may be referred to as the high-potential side switches, and the switches S2 and S3 connected to the low-potential side nodes may be referred to as the low-potential side switches.

[0031] 3, the switch circuit 12 includes switches S1 to S4, as well as a selector 13 and a capacitive couple driver 14. The switches S1 to S4 are provided so as to be capable of opening and closing between the input nodes Nip, Nim and the output nodes Nop, Nom, and each include at least one MOS transistor. In this case, the high-side switch includes two P-channel MOS transistors connected in series, and the low-side switch includes two N-channel MOS transistors connected in series.

[0032] The specific configuration of the switches S1 to S4 is as follows. The switch S1 is composed of two P-channel MOS transistors 15 and 16 connected in series. In this specification, the P-channel MOS transistor may be abbreviated as PMOS. The source of the PMOS 15 is connected to the input node Nip, and its drain is connected to the node N1. The drain of the PMOS 16 is connected to the node N1, and its source is connected to the node Np.

[0033] The node N1 is an example of an intermediate node which is an interconnection node between two PMOSs 15 and 16. The node Np is connected to the second terminal of the capacitor Cs1 and corresponds to the high potential output node of the pair of output nodes of the switch circuit 12. The back gate of the PMOS 15 is connected to its source. The back gate of the PMOS 16 is connected to its source. In other words, the back gates of the PMOSs 15 and 16 are connected to the terminal of their source or drain that is not connected to the intermediate node, the node N1.

[0034] In addition, since the back gate and the body are synonymous in a MOS transistor, in this specification, the back gate of each MOS transistor including PMOS 15 and 16 may be referred to as the body. Between the body and drain of PMOS 15, there is a body diode D15 with the drain side as the anode. Between the body and drain of PMOS 16, there is a body diode D16 with the drain side as the anode. That is, in the switch S1, the body diodes D15 and D16 face each other. The gates of PMOS 15 and 16 are connected to the capacitive couple driver 14, and the on / off of these diodes is controlled by the capacitive couple driver 14.

[0035] The switch S2 is composed of two N-channel MOS transistors 17 and 18 connected in series. In this specification, an N-channel MOS transistor may be abbreviated as NMOS. The source of the NMOS 17 is connected to the input node Nim, and its drain is connected to the node N2. The drain of the NMOS 18 is connected to the node N2, and its source is connected to the node Np.

[0036] Node N2 is an example of an intermediate node that is an interconnection node between two NMOSs 17 and 18. The backgate of NMOS 17 is connected to its source. The backgate of NMOS 18 is connected to its source. In other words, the backgates of NMOSs 17 and 18 are connected to the terminal of their source or drain that is not connected to node N2, which is the intermediate node.

[0037] Between the body and drain of NMOS17, there is a body diode D17 with the body side as the anode. Between the body and drain of NMOS18, there is a body diode D18 with the body side as the anode. That is, the body diodes D17 and D18 face each other in the switch S2. The gates of NMOS17 and NMOS18 are connected to the capacitive couple driver 14, and their on / off is controlled by the capacitive couple driver 14.

[0038] The switch S3 consists of two NMOS transistors 19 and 20 connected in series. The source of the NMOS transistor 19 is connected to the input node Nim, and its drain is connected to a node N3. The drain of the NMOS transistor 20 is connected to the node N3, and its source is connected to a node Nm. The node N3 is an example of an intermediate node that is an interconnection node between the two NMOS transistors 19 and 20.

[0039] The node Nm is connected to the second terminal of the capacitor Cs2 and corresponds to the lower potential output node of the pair of output nodes of the switch circuit 12. The back gate of the NMOS 19 is connected to its source. The back gate of the NMOS 20 is connected to its source. That is, the back gates of the NMOSs 19 and 20 are connected to the terminal of their source or drain that is not connected to the intermediate node, the node N3.

[0040] Between the body and drain of NMOS19, there is a body diode D19 with the body side as the anode. Between the body and drain of NMOS20, there is a body diode D20 with the body side as the anode. That is, the body diodes D19 and D20 face each other in the switch S3. The gates of NMOS19 and 20 are connected to the capacitive couple driver 14, and their on / off is controlled by the capacitive couple driver 14.

[0041] The switch S4 is composed of two PMOSs 21 and 22 connected in series. The source of the PMOS 21 is connected to the input node Nip, and its drain is connected to a node N4. The drain of the PMOS 22 is connected to the node N4, and its source is connected to a node Nm. The node N4 is an example of an intermediate node that is an interconnection node between the two PMOSs 21 and 22. The backgate of the PMOS 21 is connected to its source. The backgate of the PMOS 22 is connected to its source. In other words, the backgates of the PMOSs 21 and 22 are connected to the terminal of their source or drain that is not connected to the intermediate node, the node N4.

[0042] Between the body and drain of PMOS21, there is a body diode D21 with the drain side as the anode. Between the body and drain of PMOS22, there is a body diode D22 with the drain side as the anode. That is, in switch S1, the body diodes D21 and D22 face each other. The gates of PMOS21 and PMOS22 are connected to the capacitive couple driver 14, and their on / off is controlled by the capacitive couple driver 14.

[0043] The selector 13 is connected between a pair of input nodes Nip and Nim, selects one of the voltages VINP and VINM of the pair of input nodes Nip and Nim, and outputs a selection signal having a potential corresponding to the selected voltage, and includes a maximum selector 23, a minimum selector 24, and a Zener diode 25. The maximum selector 23 and the minimum selector 24 each include two MOS transistors connected in series between the pair of input nodes Nip and Nim. The two MOS transistors included in the maximum selector 23 are PMOSs 26 and 27.

[0044] The drain of PMOS 26 is connected to the input node Nip, and the drain of PMOS 27 is connected to the input node Nim. The gate of PMOS 26 is connected to the input node Nim, and the gate of PMOS 27 is connected to the input node Nip. The sources and back gates of PMOS 26 and 27 are all connected to a node N5. The node N5 is an output node for outputting a selection signal Vmax in the maximum selector 23, and is connected to a signal line 28. In other words, the maximum selector 23 is configured to output a signal of the node N5, which is an interconnection node between the two PMOSs 26 and 27, as the selection signal Vmax.

[0045] Between the body and drain of the PMOS26, there is a body diode D26 with the drain side as the anode. Between the body and drain of the PMOS27, there is a body diode D27 with the drain side as the anode. That is, in the maximum selector 23, the body diodes D26 and D27 face each other. With this configuration, the maximum selector 23 selects the higher of the voltages VINP and VINM, and outputs a selection signal Vmax having a potential corresponding to the selected voltage to other circuits via the node N5 and the signal line 28.

[0046] A normal MOS transistor having a normal threshold is used as the PMOS 27, which is one of the two PMOSs 26 and 27 included in the maximum selector 23. A low-threshold MOS transistor having a threshold lower than the normal threshold is used as the other PMOS 26, which is the PMOS 26, which is the other of the two PMOSs 26 and 27 included in the maximum selector 23. The low-threshold MOS transistor also includes a depletion MOS transistor having a threshold of 0V. In this embodiment, a depletion MOS transistor is used as the PMOS 26. In FIG. 2 and other figures, the symbols of MOS transistors using depletion MOS transistors are distinguished by adding an * mark near the gate.

[0047] The two MOS transistors included in the minimum selector 24 are NMOS 29 and 30. The drain of the NMOS 29 is connected to the input node Nip, and the drain of the NMOS 30 is connected to the input node Nim. The gate of the NMOS 29 is connected to the input node Nim, and the gate of the NMOS 30 is connected to the input node Nip. The sources and back gates of the NMOS 29 and 30 are both connected to a node N6. The node N6 is an output node for outputting a selection signal Vmin in the minimum selector 24, and is connected to a signal line 31. In other words, the minimum selector 24 is configured to output a signal of the node N6, which is an interconnection node between the two NMOSs 29 and 30, as the selection signal Vmin.

[0048] Between the body and drain of NMOS29, there is a body diode D29 with the body side as the anode. Between the body and drain of NMOS30, there is a body diode D30 with the body side as the anode. That is, in the minimum selector 24, the body diodes D29 and D30 face each other. With this configuration, the minimum selector 24 selects the lower voltage of the voltages VINP and VINM, and outputs a selection signal Vmin having a potential corresponding to the selected voltage to other circuits via the node N6 and the signal line 31.

[0049] A normal MOS transistor having a normal threshold is used as the NMOS 29, which is one of the two NMOSs 29 and 30 included in the minimum selector 24. A low-threshold MOS transistor having a threshold lower than the normal threshold is used as the other NMOS 30, which is the other of the two NMOSs 29 and 30 included in the minimum selector 24. In this embodiment, a depletion MOS transistor is used as the NMOS 30.

[0050] In the selector 13 having the above configuration, there exists an operation indeterminate region where the selector 13 cannot operate normally depending on the difference between the voltages VINP and VINM of the input nodes Nip and Nim. Therefore, in the above configuration, a Zener diode 25 with the node N6 side as the anode is connected between the nodes N5 and N6. As a result, in the above operation indeterminate region, the selection signals Vmax and Vmin are fixed to a predetermined potential relationship.

[0051] The capacitive couple driving unit 14 controls the operation of the switches S1 to S4 based on binary control signals SLSA0n, SLSB0n, SLSA0p, and SLSB0p provided from the outside. The high level of the control signals SLSA0n to SLSB0p is +5V, and the low level is 0V. The capacitive couple driving unit 14 is configured to control the on / off of the switches S1 to S4 by driving the gates of the MOS transistors 15 to 22 via the driving capacitances Cdr1 to Crd4.

[0052] The capacitive couple driving section 14 is configured as a part of the control circuit 9 described above, and its specific configuration is as follows. That is, the capacitive couple driving section 14 includes a plurality of driving capacitances Cdr1, Cdr2, Cdr3, and Cdr4 provided corresponding to the switches S1 to S4, respectively, a PMOS driving section 33, and an NMOS driving section 34. In the following description, the PMOS driving section 33 and the NMOS driving section 34 may be simply abbreviated as the driving sections 33 and 34. The driving capacitance Cdr1 is connected between a node N7 to which a control signal SLSA0n is applied and a node N8. The node N8 is connected to the gates of the PMOSs 15 and 16 of the switch S1. The driving capacitance Cdr2 is connected between a node N9 to which a control signal SLSB0p is applied and a node N10. The node N10 is connected to the gates of the NMOSs 17 and 18 of the switch S2.

[0053] The driving capacitance Cdr3 is connected between a node N11 to which a control signal SLSA0p is applied and a node N12. The node N12 is connected to the gates of the NMOSs 19 and 20 of the switch S3. The driving capacitance Crd4 is connected between a node N13 to which a control signal SLSB0n is applied and a node N14. The node N14 is connected to the gates of the PMOSs 21 and 22 of the switch S4. In this embodiment, the driving capacitances Cdr1 to Cdr4 are configured by comb capacitances.

[0054] The driving units 33 and 34 supply driving signals SLSAn, SLSBn, SLSAp, and SLSBp to the gates of the MOS transistors 15 to 22 constituting the switches S1 to S4, respectively. The driving signals SLSAn to SLSBp are binary signals that are either an off level that turns off the MOS transistors 15 to 22 or an on level that turns on the MOS transistors 15 to 22. Specifically, the on level and the off level are as follows.

[0055] That is, when the driving target is an NMOS, the on level is a level that satisfies the following formula (1), and when the driving target is a PMOS, the on level is a level that satisfies the following formula (2), and the off level is a level that satisfies the following formula (3), where VGS is the gate-source voltage of the MOS transistor, and Vt is the threshold voltage of the MOS transistor. VGS>Vt …(1) VGS<-Vt …(2) VGS ≒ 0 … (3)

[0056] The PMOS driver 33 includes two PMOSs 35 and 36. The drain of the PMOS 35 is connected to a node N8, and its source is connected to a node N15. The node N15 is connected to a signal line 28. The back gate of the PMOS 35 is connected to its source. The gate of the PMOS 35 is connected to a node N14. Between the body and drain of the PMOS 35, there is a body diode D35 with the drain side as the anode.

[0057] The drain of PMOS36 is connected to node N14, and its source is connected to node N15. The back gate of PMOS36 is connected to its source. The gate of PMOS36 is connected to node N8. Between the body and drain of PMOS36, there is a body diode D36 with the drain side as the anode.

[0058] The PMOS driver 33 configured as described above generates a drive signal SLSAn for driving the gates of PMOS 15, 16 and a drive signal SLSBn for driving the gates of PMOS 21, 22, using the potential of the selection signal Vmax output from the selector 13 as a reference potential. The drive signal SLSAn has the same logic as the control signal SLSA0n, and is supplied from node N8 to the gates of PMOS 15, 16 of switch S1. The drive signal SLSBn has the same logic as the control signal SLSB0n, and is supplied from node N14 to the gates of PMOS 21, 22 of switch S4.

[0059] The NMOS driver 34 includes two NMOSs 37 and 38. The drain of the NMOS 37 is connected to a node N10, and its source is connected to a node N16. The node N16 is connected to a signal line 31. The back gate of the NMOS 37 is connected to its source. The gate of the NMOS 37 is connected to a node N12. Between the body and drain of the NMOS 37, there is a body diode D37 with the body side serving as the anode.

[0060] The drain of the NMOS 38 is connected to the node N12, and the source is connected to the node N16. The back gate of the NMOS 38 is connected to the source. The gate of the NMOS 38 is connected to the node N10. Between the body and drain of the NMOS 38, there is a body diode D38 with the body side as the anode.

[0061] The NMOS driver 34 configured as described above generates a drive signal SLSBp for driving the gates of NMOS 17, 18 and a drive signal SLSAp for driving the gates of NMOS 19, 20, using the potential of the selection signal Vmin output from the selector 13 as a reference potential. The drive signal SLSBp has the same logic as the control signal SLSB0p, and is supplied from node N10 to the gates of NMOS 17, 18 of switch S2. The drive signal SLSAp has the same logic as the control signal SLSA0p, and is supplied from node N12 to the gates of NMOS 19, 20 of switch S3.

[0062] Next, the operation of the above configuration will be described with reference to FIGS. The capacitive couple driver 14 controls the switches S1, S3 and the switches S2, S4 to be turned on and off complementarily. In this specification, "turning on and off complementarily" does not exclude the case where a period during which both switches are off, that is, a so-called dead time, is provided. Hereinafter, the period during which the switches S1, S3 are turned on and the switches S2, S4 are turned off may be referred to as a sample period, and the period during which the switches S1, S3 are turned off and the switches S2, S4 are turned on may be referred to as a hold period.

[0063] In the SC amplifier 2 having the above configuration, during the sample period, the capacitors Cs1 and Cs2 are charged by the voltages VINP and VINM of the input nodes Nip and Nim, that is, the voltages VINP and VINM of the input nodes Nip and Nim are sampled by the capacitors Cs1 and Cs2. Also, in the SC amplifier 2 having the above configuration, during the hold period, the charges stored in the capacitors Cs1 and Cs2 are transferred to the subsequent circuit.

[0064] In the following, assuming such an operation, the potential state of each part at the time of positive voltage input where a positive voltage is input via the input nodes Nip and Nim and at the time of negative voltage input where a negative voltage is input via the input nodes Nip and Nim will be described. Note that here, it is assumed that the voltage VINP is +5V and the voltage VINM is 0V at the time of positive voltage input, and that the voltage VINP is -2V and the voltage VINM is 0V at the time of negative voltage input. In Figs. 4 to 6, the on / off state of each MOS transistor is indicated by the presence or absence of hatching. Specifically, in Figs. 4 to 6, only the MOS transistors that are turned on are hatched.

[0065] [1] Potential state of each part when positive voltage is input 4 and 5, when a positive voltage is input, in the selector 13, PMOS 26 and NMOS 30 are turned on, and PMOS 27 and NMOS 29 are turned off. As a result, when a positive voltage is input, the potential of the selection signal Vmax becomes 5 V, and the potential of the selection signal Vmin becomes 0 V. As shown in Fig. 4 and 6, during the sample period, the control signals SLSA0n and SLSB0p become 0 V, and the control signals SLSB0n and SLSA0p become 5 V.

[0066] 4, in the sample period when a positive voltage is input, in the drivers 33 and 34, PMOS 36 and NMOS 37 are turned on, and PMOS 35 and NMOS 38 are turned off. As a result, in the sample period when a positive voltage is input, the drive signal SLSAn becomes 1 V, the drive signal SLSBn becomes 5 V, the drive signal SLSAp becomes 4 V, and the drive signal SLSBp becomes 0 V. Therefore, in the sample period when a positive voltage is input, the PMOSs 15 and 16 of the switch S1 and the NMOSs 19 and 20 of the switch S3 are turned on, and the NMOSs 17 and 18 of the switch S2 and the PMOSs 21 and 22 of the switch S4 are turned off.

[0067] As shown in FIG. 5, during the hold period, the control signals SLSA0n and SLSB0p are 5V, and the control signals SLSB0n and SLSA0p are 0V. Therefore, as shown in FIG. 5, during the hold period when a positive voltage is input, in the drivers 33 and 34, the PMOS 35 and NMOS 38 are turned on, and the PMOS 36 and NMOS 37 are turned off. As a result, during the hold period when a positive voltage is input, the drive signal SLSAn is 5V, the drive signal SLSBn is 1V, the drive signal SLSAp is 0V, and the drive signal SLSBp is 4V. Therefore, during the hold period when a positive voltage is input, the PMOSs 15 and 16 of the switch S1 and the NMOSs 19 and 20 of the switch S3 are turned off, and the NMOSs 17 and 18 of the switch S2 and the PMOSs 21 and 22 of the switch S4 are turned on.

[0068] As described above, according to the configuration of this embodiment, when a positive voltage is input, the potential states of the switches S1 to S4 can be set to the same potential state as in the configuration in which the selector 13 is not provided. Furthermore, according to the configuration of this embodiment, since depletion MOS transistors are used as the PMOS 26 and NMOS 30 that should be turned on when a positive voltage is input in the selector 13, these PMOS 26 and NMOS 30 can be reliably turned on even when the input voltage VINP is near 0V, and as a result, the potential of the MOS transistors constituting the off switches does not become unstable, and high accuracy of the output can be achieved. Note that the case where the input voltage VINP is near 0V refers to the case where the input voltage VINP is equal to or lower than the threshold voltage Vt of the MOS transistor, for example, equal to or lower than 0.7V.

[0069] [2] Potential state of each part when negative voltage is input 6, when a negative voltage is input, in the selector 13, PMOS 27 and NMOS 29 are turned on, and PMOS 26 and NMOS 30 are turned off. As a result, when a negative voltage is input, the potential of the selection signal Vmax becomes 0 V, and the potential of the selection signal Vmin becomes -2 V. Therefore, in the sample period when a negative voltage is input, in the drivers 33 and 34, PMOS 36 and NMOS 37 are turned on, and PMOS 35 and NMOS 38 are turned off.

[0070] As a result, during the sample period when a negative voltage is input, the drive signal SLSAn becomes -4 V, the drive signal SLSBn becomes 0 V, the drive signal SLSAp becomes 2 V, and the drive signal SLSBp becomes -2 V. Therefore, during the sample period when a negative voltage is input, the PMOSs 15 and 16 of the switch S1 and the NMOSs 19 and 20 of the switch S3 are turned on, and the NMOSs 17 and 18 of the switch S2 and the PMOSs 21 and 22 of the switch S4 are turned off. The potential state during the hold period when a negative voltage is input is the differential target for the sample period when a negative voltage is input, so a description thereof will be omitted.

[0071] As described above, according to the configuration of this embodiment, when a negative voltage is input, the voltage VINP, which is the lower potential of the voltages VINP and VINM, is applied to the gate of the NMOS constituting the switch that should be turned off among the switches S1 to S4, and the voltage VINM, which is the higher potential of the voltages VINP and VINM, is applied to the gate of the PMOS constituting the switch that should be turned off, thereby reliably turning off those switches.

[0072] Furthermore, according to the configuration of this embodiment, when a negative voltage is input, a drive signal whose potential is changed to be higher by a level corresponding to the amplitude of the control signal relative to voltage VINP is applied to the gate of an NMOS constituting a switch that should be turned on among switches S1 to S4, and a drive signal whose potential is changed to be lower by a level corresponding to the amplitude of the control signal relative to voltage VINM is applied to the gate of a PMOS constituting a switch that should be turned on, thereby reliably turning on those switches.

[0073] According to the present embodiment described above, the following effects can be obtained. According to the configuration of this embodiment, when a positive voltage is input, the selector 13 does not become unstable and no leak current occurs, so that the potential states of the multiple switches S1 to S4 can be made equivalent to those in a configuration without the selector 13. Therefore, according to the configuration of this embodiment, the input range and detection accuracy of the positive voltage can be made equivalent to those in a configuration without the selector 13.

[0074] Furthermore, according to the configuration of this embodiment, as in the conventional technology, a negative voltage can be detected by the operation of the selector 13. In this way, according to the configuration of this embodiment, it is possible to detect a negative voltage while maintaining the input range and detection accuracy of a positive voltage at the same level as in a configuration without the selector 13. Therefore, according to this embodiment, it is possible to obtain the excellent effect of being able to accurately detect a wide range of voltages while suppressing the occurrence of leakage current.

[0075] The effect obtained by this embodiment becomes clearer when compared with the conventional technology. Therefore, the effect obtained by this embodiment will be described in detail below with reference to FIG. 7, comparing this embodiment with a comparative example corresponding to the conventional technology. In FIG. 7, the arrows indicating the range corresponding to the comparative example are indicated by dotted lines, and the arrows indicating the range corresponding to this embodiment are indicated by solid lines. In FIG. 7, Vf is the forward voltage of the diode, and Vcc is the drive voltage in the drive units 33 and 34.

[0076] 7, assuming a sample period when a negative voltage is input, the gate voltage range of the NMOSs 19 and 20 of the switch S3 that are turned on at that time, i.e., the voltage range of the drive signal SLSAp, is shown as the ON SW gate voltage range, and the gate voltage range of the NMOSs 17 and 18 of the switch S2 that are turned off at that time, i.e., the voltage range of the drive signal SLSBp, is shown as the OFF SW gate voltage range. Note that the negative voltage input in this case is assumed to be when the voltage VINP is in the range of "-Vt to 0V" and the voltage VINM is 0V.

[0077] As shown in Fig. 7, the positive side operating range of the voltage detection circuit 1 of this embodiment is the same as that of the comparative example, and the differential voltage between the input nodes Nip and Nim is in the range of about +5.0V. In this specification, the differential voltage between the input nodes Nip and Nim may be simply referred to as the differential voltage. The negative side operating range of the voltage detection circuit 1 is the same as that of the comparative example, and the differential voltage is in the range of about -2.5V. In other words, the differential input operating range of the voltage detection circuit 1 of this embodiment is in the range of -2.5V to +5.0V.

[0078] However, in this embodiment, depletion MOS transistors are used for PMOS 26, one of two PMOSs 26 and 27 constituting maximum selector 23, and NMOS 30, one of two NMOSs 29 and 30 constituting minimum selector 24, so the operating range of selector 13 is wider than that of the comparative example. That is, in the comparative example, the operating range of the positive side of the selector is a range equal to or higher than +Vtn, which is, for example, about 0.7 V. However, Vtn is the threshold value of a normal MOS transistor.

[0079] Therefore, in the comparative example, the Vmin indefinite range in which the selection signal Vmin output from the minimum selector is indefinite is the range from -Vtn to +Vtn, that is, the range from -0.7V to +0.7V. As a result, in the comparative example, in the range from -0.7V to +0.7V, the gate voltage of the NMOS of the switch to be turned off becomes higher than the input voltage, causing leakage and reducing accuracy. In contrast, in this embodiment, the operating range on the positive side of the selector 13 is a range equal to or higher than +Vtd, which is, for example, 0V. Here, Vtd is the threshold value of the depletion MOS transistor.

[0080] Therefore, in this embodiment, the Vmin indefinite range is the range from -Vtn to +Vtd, that is, the range from -0.7 V to 0 V. As a result, in this embodiment, in the range from -0.7 V to 0 V, the gate voltage of the NMOS of the switch to be turned off becomes higher than the input voltage, so there is a risk of leakage occurring, but in the range of 0 V or higher, that is, when a positive voltage is input, it is possible to prevent leakage from occurring.

[0081] Thus, according to this embodiment, when the differential voltage is approximately 0V or more, the selector 13 always operates, and it is possible to reduce the deterioration in accuracy due to leakage of the MOS transistor constituting the selector 13, as compared to the comparative example. In addition, in both the comparative example and this embodiment, the signal transmission range of the NMOS is in the range of approximately 0V to +3.0V. In the comparative example, since the NMOS exists in the path through which the voltage VINP passes, although the voltage VINP is expected to be approximately +5.0V at most, it can only pass up to approximately +3.0V, narrowing the input range of positive voltages.

[0082] In contrast, in this embodiment, since only PMOS exists in the path through which the voltage VINP passes, the input range of positive voltages can be expanded compared to the comparative example. Also, in this embodiment, since the NMOS only exists in the path through which the voltage VINM passes and it is sufficient to pass 0V, there is no risk of the input range being narrowed due to the signal transmission range of the NMOS. Although a detailed explanation is omitted, according to this embodiment, the input range is also expanded on the PMOS side compared to the comparative example by the opposite operation to that on the NMOS side.

[0083] Each of the switches S1 to S4 has a configuration in which two MOS transistors are connected in series, and the back gates of the MOS transistors are connected to the source or drain terminal that is not connected to the intermediate node that is the interconnection node of the two MOS transistors. In this way, the body diodes of the two MOS transistors in the switches S1 to S4 face each other.

[0084] Therefore, with this configuration, no current flows through the body diode, and no error occurs. In particular, when the negative voltage is large, no backflow occurs through the body diode, and the occurrence of errors associated with this can be suppressed. In addition, with the above configuration, the body potential of each MOS transistor constituting the signal transmission switches S1 to S4 for transmitting the input signal voltages VINP and VINM to the subsequent stage can be fixed to the input signal voltages VINP and VINM, which is an advantage in that the EMC tolerance is increased.

[0085] In this embodiment, the capacitive couple driving section 14 drives the gates of the MOS transistors 15-22 via the driving capacitances Cdr1-Cdr4, which are comb-tooth capacitances, to control the on / off of the switches S1-S4. That is, in this embodiment, the switches S1-S4 are configured to be capacitively coupled driven. In addition, in this embodiment, the driving capacitances Cdr1-Cdr4 are configured as comb-tooth capacitances.

[0086] This configuration provides the following effects. That is, the above configuration allows the circuit to be made smaller than when the drive capacitances Cdr1 to Cdr4 are configured with parallel plate capacitances, and also allows the parasitic capacitance with other circuits inside the chip to be reduced, thereby reducing interference. Furthermore, in a capacitive coupled drive configuration, noise is emitted in the sample / hold cycle, but by configuring the drive capacitances Cdr1 to Cdr4 with comb capacitances, the drive speed can be increased.

[0087] Normally, in a capacitively coupled drive configuration, in order to avoid noise interference, it is necessary to secure space between the other circuits inside the chip or to place a guard ring, which inevitably results in a large chip area. In contrast, with the above configuration, when high-speed drive is not desired, other circuits can be placed adjacent to the chip, which results in a reduction in the overall chip area while achieving the desired drive speed.

[0088] The voltage detection circuit 1 including the SC amplifier 2 of this embodiment constitutes a part of the battery monitoring IC 5, and more specifically, can be used as a level shift circuit in the battery monitoring IC 5. With this configuration, it is possible to transmit only the differential voltage through the capacitors Cs1 and Cs2, which are sampling capacitances, and therefore it is possible to shift the level of the common mode potential. Furthermore, with the above configuration, it is possible to detect signals in a wider range than the power supply voltage or ground potential, both positive and negative.

[0089] Furthermore, by applying the voltage detection circuit 1 to a battery monitoring IC 5, not only can a single IC detect the voltages of multiple battery cells, but it can also detect the voltage of a fuel cell in which the battery cell voltage is negative. As described above, the configuration of this embodiment makes it possible to make the input range and detection accuracy of positive voltages comparable to those of a configuration that does not include the selector 13, so that the same battery monitoring IC 5 can be used both as a normal battery monitoring IC that monitors lithium-ion batteries and as a battery monitoring IC for FCs that monitors fuel cells.

[0090] <Modifications regarding selectors> Regarding the configuration of this embodiment, it can be modified to use low-threshold MOS transistors other than depletion MOS transistors as the PMOS 26 included in the maximum selector 23 and the NMOS 30 included in the minimum selector 24. According to such a modification example, when the differential voltage is equal to or higher than a voltage corresponding to a threshold lower than the normal threshold, the selector 13 always operates. Compared with the comparative example, it is possible to reduce the accuracy degradation due to the leakage of the MOS transistors constituting the selector 13.

[0091] Regarding the configuration of this embodiment, it can be modified to use low-threshold MOS transistors including depletion MOS transistors as the PMOS 27 included in the maximum selector 23 and the NMOS 29 included in the minimum selector 24, and to use normal MOS transistors as the PMOS 26 included in the maximum selector 23 and the NMOS 30 included in the minimum selector 24.

[0092] According to such a modification example, although the positive operating range of the selector 13 becomes the same as that of the comparative example, the negative operating range of the selector 13 becomes a range of +Vtd or less, for example, 0V. Therefore, in the modification example, the Vmin indeterminate range becomes a range from +Vtd to +Vtn, that is, a range from 0V to +0.7V. As a result, in the modification example, in the range from 0V to +0.7V, although there is a possibility of leakage because the gate voltage of the NMOS of the switched-off switch becomes higher than the input voltage, it is possible to prevent the occurrence of leakage in the range of 0V or less, that is, when a negative voltage is input. Thus, according to the modification example, when the differential voltage is approximately 0V or less, the selector 13 always operates. Compared with the comparative example, it is possible to reduce the accuracy degradation due to the leakage of the MOS transistors constituting the selector 13.

[0093] <Another application example of the SC amplifier> The SC amplifier 2 configured as above can be used as an integrator in a ΔΣ ADC. The ΔΣ ADC is an ADC that has a ΔΣ modulator 41 as shown in Fig. 8 and obtains a high-resolution digital output by passing the output of the ΔΣ modulator 41 through a digital filter (not shown). The ΔΣ modulator 41 employs a type of pulse modulation method and includes an adder 42, an integrator 43, a comparator 44, and a DAC 45.

[0094] The adder 42 outputs a signal obtained by subtracting the output signal of the DAC 45 from the input signal Input. The integrator 43 integrates the output signal of the adder 42, and can be constituted by the SC amplifier 2. The comparator 44 binarizes the output signal of the integrator 43. The DAC 45 receives the output signal of the comparator 44 and outputs a signal according to the input. The ΔΣ modulator 41 thus configured integrates the input signal Input using the integrator 43, digitally converts the output using the comparator 44, and adds or subtracts from the input signal Input using the DAC 45 according to the output, thereby enabling the output of the comparator 44 to be extracted as the ΔΣ modulated output Output.

[0095] According to the above configuration, the above-mentioned operation shapes the power spectrum density distribution of the quantization error output by the comparator 44, that is, performs noise shaping, and improves the dynamic range of the passband. This configuration enables the ADC to shift the level of the common mode potential by itself, and makes it possible to detect signals in a wider range than the power supply voltage or ground potential, both positive and negative. Furthermore, according to the above configuration, it is possible to achieve a smaller size than a configuration in which a separate level shifter is provided in front of the ADC.

[0096] Second embodiment The second embodiment will be described below with reference to FIG. 9, a switch circuit 51 of the present embodiment differs from the switch circuit 12 of the first embodiment in the configuration of switches S1 to S4, etc. In this case, the high potential side switch is made up of one P-channel MOS transistor, and the low potential side switch is made up of one N-channel MOS transistor.

[0097] The specific configuration of the switches S1 to S4 is as follows. The switch S1 is composed of one PMOS 52. The source of the PMOS 52 is connected to the input node Nip, and the drain of the PMOS 52 is connected to the node Np. The back gate of the PMOS 52 is connected to the signal line 28. As a result, the selection signal Vmax is provided as the substrate potential of the PMOS 52. Although not shown in the figure, a body diode with the drain side as the anode exists between the body and drain of the PMOS 52. The gate of the PMOS 52 is connected to the capacitive couple driving unit 14, and the on / off of the PMOS 52 is controlled by the capacitive couple driving unit 14.

[0098] The switch S2 is composed of one NMOS 53. The source of the NMOS 53 is connected to the input node Nim, and the drain is connected to the node Np. The back gate of the NMOS 53 is connected to the signal line 31. As a result, the selection signal Vmin is provided as the substrate potential of the NMOS 53. Although not shown, a body diode with the body side serving as the anode exists between the body and drain of the NMOS 53. The gate of the NMOS 53 is connected to the capacitive couple driver 14, and its on / off is controlled by the capacitive couple driver 14.

[0099] The switch S3 is composed of one NMOS 54. The source of the NMOS 54 is connected to the input node Nim, and the drain of the NMOS 54 is connected to the node Nm. The back gate of the NMOS 54 is connected to the signal line 31. As a result, the selection signal Vmin is provided as the substrate potential of the NMOS 54. Although not shown, a body diode with the body side serving as the anode exists between the body and drain of the NMOS 54. The gate of the NMOS 54 is connected to the capacitive couple driver 14, and its on / off is controlled by the capacitive couple driver 14.

[0100] The switch S4 is composed of one PMOS 55. The source of the PMOS 55 is connected to the input node Nip, and the drain of the PMOS 55 is connected to the node Nm. The back gate of the PMOS 55 is connected to the signal line 28. This allows the selection signal Vmax to be applied as the substrate potential of the PMOS 55. Although not shown, a body diode with the drain side serving as the anode exists between the body and drain of the PMOS 55. The gate of the PMOS 55 is connected to the capacitive couple driver 14, and its on / off is controlled by the capacitive couple driver 14.

[0101] The present embodiment described above also provides the same effects as the first embodiment. Furthermore, according to the present embodiment, since the switches S1 to S4 are each composed of a single MOS transistor, the circuit can be made smaller than in the first embodiment. However, in the present embodiment in which the switches S1 to S4 are each composed of a single MOS transistor, there is a risk of a voltage detection error occurring due to a leak current caused by the body diode of the MOS transistor.

[0102] However, in this embodiment, the selection signal Vmax output from the selector 13 is provided as a substrate potential of the PMOSs 52 and 55 included in the switches S1 and S4, and the selection signal Vmin output from the selector 13 is provided as a substrate potential of the NMOSs 53 and 54 included in the switches S2 and S3. In this way, it is possible to prevent the occurrence of leakage current due to the body diodes of the MOS transistors that constitute the switches S1 to S4.

[0103] Third embodiment The third embodiment will be described below with reference to FIGS. <Overall composition> 10, an SC amplifier 62 included in a voltage detection circuit 61 of this embodiment differs from the SC amplifier 2 of the first embodiment in that it includes a switch S61 instead of the switches S2 and S4. The switch S61 is connected between the second terminal of the capacitor Cs1 and the second terminal of the capacitor Cs2. <Specific configuration of switch circuit>

[0104] In the above configuration, the switches S1, S3, and S61 connected between the pair of input nodes Nip and Nim and the capacitors Cs1 and Cs2, as well as the selector 13 and the capacitive couple driving unit 14, constitute a switch circuit 63, which is a CCSW circuit, as shown in Fig. 10. Note that Fig. 10 shows a simplified configuration of the selector 13 and the capacitive couple driving unit 14. The switch circuit 63 including the switches S1, S3, and S61 constitutes a part of the SC amplifier 62, and a specific configuration thereof may be, for example, as shown in Fig. 11. The switch S61 is configured by connecting in parallel a series circuit 66 in which two PMOSs 64 and 65 are connected in series, and a series circuit 69 in which two NMOSs 67 and 68 are connected in series.

[0105] The source of PMOS 64 is connected to node Np, and its drain is connected to node N61. The drain of PMOS 65 is connected to node N61, and its source is connected to node Nm. Node N61 is an example of an intermediate node that is an interconnection node between two PMOSs 64 and 65. The backgate of PMOS 64 is connected to its source. The backgate of PMOS 65 is connected to its source. In other words, the backgates of PMOSs 64 and 65 are connected to the terminal of their source or drain that is not connected to node N61, which is the intermediate node.

[0106] Between the body and drain of PMOS 64, there is a body diode D64 with the drain side as the anode. Between the body and drain of PMOS 65, there is a body diode D65 with the drain side as the anode. That is, in switch S61, the body diodes D64 and D65 face each other. The gates of PMOS 64 and 65 are connected to the capacitive couple driver 14, and the on / off of these is controlled by the capacitive couple driver 14. Specifically, the on / off of PMOS 64 and 65 is controlled by a drive signal SLSBn.

[0107] The source of NMOS 67 is connected to node Np, and its drain is connected to node N62. The drain of NMOS 68 is connected to node N62, and its source is connected to node Nm. Node N62 is an example of an intermediate node that is an interconnection node between two NMOSs 67 and 68. The backgate of NMOS 67 is connected to its source. The backgate of NMOS 68 is connected to its source. In other words, the backgates of NMOSs 67 and 68 are connected to the terminal of their source or drain that is not connected to node N62, which is the intermediate node.

[0108] Between the body and drain of the NMOS 67, there is a body diode D67 with the body side as the anode. Between the body and drain of the NMOS 68, there is a body diode D68 with the body side as the anode. That is, in the switch S61, the body diodes D67 and D68 face each other. The gates of the NMOSs 67 and 68 are connected to the capacitive couple driver 14, and the on / off of these diodes is controlled by the capacitive couple driver 14. Specifically, the on / off of the NMOSs 67 and 68 is controlled by the drive signal SLSBp.

[0109] The present embodiment described above also provides the same effects as the first embodiment. The switch S61 is configured by connecting in parallel a series circuit 66 of two PMOS transistors 64 and 65 and a series circuit 69 of two NMOS transistors 67 and 68, and the back gates of these MOS transistors are connected to the terminal of the source or drain that is not connected to the intermediate node that is the interconnection node of the two MOS transistors. In this way, the body diodes of the two MOS transistors in the switch S61 face each other, as in the switches S1 and S3. Therefore, with the configuration of this embodiment, as in the first embodiment, no current flows through the body diodes, and no errors occur.

[0110] Furthermore, according to this embodiment, the following effects can be obtained. In the configuration of this embodiment, the number of switches is one less than in the configuration of the first embodiment, and therefore, a corresponding reduction in size can be achieved. Also, according to the configuration of this embodiment, the operational amplifier 3 and the like are not connected to the input during hold but are in a disconnected state, and therefore, the CMRR can be improved. Note that CMRR is an abbreviation for Common Mode Rejection Ratio.

[0111] Furthermore, according to the configuration of this embodiment, the operational amplifier 3 and other components are not connected to the input during hold and are therefore in a disconnected state, so that the signal in the previous stage can be switched immediately after sampling is completed. Therefore, according to this embodiment, in a configuration in which a multiplexer is provided in the previous stage, the speed of the entire system can be increased.

[0112] (Other embodiments) The present invention is not limited to the embodiments described above and shown in the drawings, and can be modified, combined, or expanded as desired without departing from the spirit and scope of the present invention. The numerical values ​​and the like shown in the above embodiments are merely examples and are not intended to be limiting.

[0113] The selector 13 need only select one of the voltages VINP, VINM of a pair of input nodes Nip, Nim and output a selection signal having a potential corresponding to the selected voltage, and may be configured to include, for example, only one of the maximum selector 23 and the minimum selector 24.

[0114] The driving units 33 and 34 need only generate driving signals for driving the gates of the MOS transistors 15 to 22, etc. using the potential of the selection signal output from the selector 13 as a reference potential, and supply the generated driving signals to the gates of the MOS transistors 15 to 22, etc., and the specific configuration thereof can be modified as appropriate.

[0115] Although the present disclosure has been described based on the embodiment, it is understood that the present disclosure is not limited to the embodiment or structure. The present disclosure also includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, and other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure.

[0116] In addition to the inventions described in the claims, the present disclosure includes the following inventions. [1] A fully differential voltage detection circuit that receives voltages at a pair of input nodes (Nip, Nim), detects a differential voltage between the input nodes, and outputs the differential voltage from a pair of output nodes (Nop, Nom), a plurality of switches (S1 to S4) each including at least one MOS transistor (15 to 22, 52 to 55) provided so as to be capable of switching between the pair of input nodes and the pair of output nodes; a capacitive couple driver (14) including drive capacitances (Cdr1 to Cdr4) and a driver (33, 34) that generates drive signals for driving gates of the MOS transistors and supplies the drive signals to the gates of the MOS transistors, and controls the on / off of each of the plurality of switches by driving the gates of the MOS transistors via the drive capacitances; a selector (13) connected between the pair of input nodes, for selecting one of the voltages of the pair of input nodes and outputting a selection signal having a potential corresponding to the selected voltage; Equipped with the drive unit generates the drive signal using a potential of the selection signal output from the selector as a reference potential; The selector: two MOS transistors (26, 27, 29, 30) connected in series between the pair of input nodes; one of the two MOS transistors is a normal MOS transistor having a normal threshold; The other of the two MOS transistors is a low-threshold MOS transistor having a threshold lower than the normal threshold. [2] The selector: a maximum selector (23) that selects the higher of the voltages of the pair of input nodes and outputs the selection signal having a potential corresponding to the selected voltage; a minimum selector (24) that selects the lower of the voltages of the pair of input nodes and outputs the selection signal having a potential corresponding to the selected voltage; Equipped with The two MOS transistors included in the maximum selector are P-channel MOS transistors (26, 27), the two MOS transistors included in the minimum selector are N-channel MOS transistors (29, 30); The voltage detection circuit according to [1], wherein the maximum selector and the minimum selector are both configured to output a signal of an intermediate node (N5, N6) between the two MOS transistors as the selection signal. [3] The voltage detection circuit according to any one of claims 1 to 2, wherein the low-threshold MOS transistor is a depletion MOS transistor. [4] The high potential side of the pair of input nodes is a high potential side input node, the low potential side of the pair of input nodes is a low potential side input node, a switch of the plurality of switches connected to the high potential side input node is a high potential side switch, and a switch of the plurality of switches connected to the low potential side input node is a low potential side switch, The high-side switch is composed of one P-channel MOS transistor (52, 55), The voltage detection circuit according to any one of [1] to [3], wherein the low-side switch is formed of one N-channel MOS transistor (53, 54). [5] The high potential side of the pair of input nodes is a high potential side input node, the low potential side of the pair of input nodes is a low potential side input node, a switch of the plurality of switches connected to the high potential side input node is a high potential side switch, and a switch of the plurality of switches connected to the low potential side input node is a low potential side switch, The high-side switch is composed of two P-channel MOS transistors (15, 16, 21, 22) connected in series, The voltage detection circuit according to any one of [1] to [3], wherein the low-side switch is composed of two N-channel MOS transistors (17, 18, 19, 20) connected in series. [6] 13. The voltage detection circuit according to claim 12, wherein the selection signal output from the selector is provided as a substrate potential of the MOS transistors included in the plurality of switches. [7] A switched capacitor amplifier (2) is provided; The voltage detection circuit according to any one of [1] to [6], wherein the plurality of switches constitute a part of the switched capacitor amplifier. [8] The pair of input nodes are connectable to terminals of each battery cell constituting the battery pack (4), The voltage detection circuit according to any one of [1] to [7], wherein the plurality of switches form part of a level shift circuit that reduces a relatively high common-mode voltage superimposed on each of the battery cells (4a, 4b) to a relatively low common-mode voltage. [9] The voltage detection circuit according to any one of [1] to [8], wherein the driving capacitance is a comb capacitance. [Explanation of symbols]

[0117] 1, 61...voltage detection circuit, 2...switched capacitor amplifier, 4...battery pack, 4a, 4b...battery cell, 5...battery monitoring IC, 13...selector, 14...capacitive couple driver, 17, 18, 19, 20...NMOS, 15, 16, 21, 22...PMOS, 23...maximum selector, 24...minimum selector, 26, 27...PMOS, 29, 30...NMOS, 33...PMOS driver, 34...NMOS driver, 52, 55...PMOS, 53, 54...NMOS, Cdr1 to Cdr4...drive capacitance, Nip, Nim...input node, Nop, Nom...output node, S1 to S4...switch.

Claims

1. A fully differential voltage detection circuit that receives voltages at a pair of input nodes (Nip, Nim), detects a difference voltage between the input voltages, and outputs the difference voltage from a pair of output nodes (Nop, Nom), a plurality of switches (S1 to S4) each including at least one MOS transistor (15 to 22, 52 to 55) provided so as to be capable of opening and closing between the pair of input nodes and the pair of output nodes; a capacitance-coupled driving unit (14) including driving capacitances (Cdr1 to Cdr4) and a driving unit (33, 34) that generates a driving signal for driving the gate of the MOS transistor and supplies the driving signal to the gate of the MOS transistor, and controls the on / off of each of the plurality of switches by driving the gate of the MOS transistor via the driving capacitance; a selector (13) connected between the pair of input nodes, for selecting one of the voltages of the pair of input nodes and outputting a selection signal having a potential corresponding to the selected voltage; Equipped with the drive unit generates the drive signal using a potential of the selection signal output from the selector as a reference potential; The selector: two MOS transistors (26, 27, 29, 30) connected in series between the pair of input nodes; one of the two MOS transistors is a normal MOS transistor having a normal threshold voltage; The other of the two MOS transistors is a low-threshold MOS transistor having a threshold lower than the normal threshold.

2. The selector: a maximum selector (23) that selects the higher of the voltages of the pair of input nodes and outputs the selection signal having a potential corresponding to the selected voltage; a minimum selector (24) that selects the lower of the voltages of the pair of input nodes and outputs the selection signal having a potential corresponding to the selected voltage; Equipped with The two MOS transistors included in the maximum selector are P-channel MOS transistors (26, 27), the two MOS transistors included in the minimum selector are N-channel MOS transistors (29, 30); 2. The voltage detection circuit according to claim 1, wherein each of the maximum selector and the minimum selector is configured to output a signal at an intermediate node (N5, N6) between the two MOS transistors as the selection signal.

3. 2. The voltage detection circuit of claim 1, wherein the low-threshold MOS transistor is a depletion MOS transistor.

4. The high potential side of the pair of input nodes is a high potential side input node, the low potential side of the pair of input nodes is a low potential side input node, a switch of the plurality of switches connected to the high potential side input node is a high potential side switch, and a switch of the plurality of switches connected to the low potential side input node is a low potential side switch, The high-side switch is composed of one P-channel MOS transistor (52, 55), 4. The voltage detection circuit according to claim 1, wherein the low-side switch is formed of one N-channel MOS transistor (53, 54).

5. The high potential side of the pair of input nodes is a high potential side input node, the low potential side of the pair of input nodes is a low potential side input node, a switch of the plurality of switches connected to the high potential side input node is a high potential side switch, and a switch of the plurality of switches connected to the low potential side input node is a low potential side switch, The high-side switch is composed of two P-channel MOS transistors (15, 16, 21, 22) connected in series, 4. The voltage detection circuit according to claim 1, wherein the low-side switch is made up of two N-channel MOS transistors (17, 18, 19, 20) connected in series.

6. 4. The voltage detection circuit according to claim 1, wherein the selection signal output from the selector is provided as a substrate potential of the MOS transistors included in the plurality of switches.

7. A switched capacitor amplifier (2), 6. The voltage detection circuit according to claim 5, wherein the plurality of switches form a part of the switched capacitor amplifier.

8. The pair of input nodes are connectable to terminals of each battery cell constituting the battery pack (4), 8. The voltage detection circuit according to claim 7, wherein the plurality of switches form part of a level shift circuit that reduces a relatively high common mode voltage superimposed on each of the battery cells (4a, 4b) to a relatively low common mode voltage.

9. 9. The voltage detection circuit according to claim 8, wherein the driving capacitance is a comb capacitance.

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