Voltage detection circuit

Abstract

To detect the voltage in the wide range accurately while suppressing the occurrence of leak current.SOLUTION: A voltage detection circuit with a fully differential structure is provided between a pair of input nodes Nip and Nim, and a pair of output nodes Nop and Nom and includes a plurality of switches S1 to S4 including serial circuits SC1 to SC4 with a structure in which two MOS transistors are connected in series, and a capacitive coupling driving unit 14. The capacitive coupling driving unit 14 includes driving capacitors Cdr1 to Cdr4 and controls on and off of each of the switches S1 to S4 by driving the gates of the MOS transistors included in the switches S1 to S4 through the driving capacitors Cdr1 to Cdr4. A back gate of the MOS transistor is connected to a terminal, among its source and drain terminals, that is not connected to intermediate nodes N1 to N4 corresponding to mutual connection nodes of the two MOS transistors.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a voltage detection circuit having a fully differential configuration. [Background technology]

[0002] Patent Document 1 discloses a voltage detection circuit with a fully differential configuration that employs a switch circuit called a CCSW circuit. CCSW is an abbreviation for Capacitively-Coupled Switch. Hereinafter, the voltage detection circuit disclosed in Patent Document 1 will be referred to as the prior art. The prior art is configured with a selector that provides the higher of the voltages at two input nodes as the substrate potential of a P-channel MOS transistor and provides the lower of the voltages at the two input nodes as the substrate potential of an N-channel MOS transistor. [Prior art documents] [Non-patent literature]

[0003] [Patent Document 1] Patent No. 6673150 Summary of the Invention [Problem to be solved by the invention]

[0004] The conventional technology is assumed to be used in a battery monitoring IC that monitors the voltage of a battery. Note that IC is an abbreviation for Integrated Circuit. In battery monitoring ICs, the voltage range that can be detected is expanding year by year as the number of types of batteries to be detected increases. Since changing the IC design for each type of battery leads to an increase in the number of product types, it is desirable for a battery monitoring IC to be able to detect a wide range of voltages, both positive and negative, with one chip, i.e., one AFE. Note that AFE is an abbreviation for Analog Front End.

[0005] The conventional technology is suitable for applications where the voltage of a fuel cell is to be detected because it can detect negative voltages, but is not suitable for applications where the voltage of a lithium-ion battery is to be detected, for example, 0 to 5 V, because the input range of positive voltages is relatively narrow. Furthermore, with the conventional technology, there was a risk that the selector would not operate when the input voltage was near 0 V, causing a leak current and reducing the detection accuracy.

[0006] The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a voltage detection circuit that can accurately detect a wide range of voltages while suppressing the occurrence of leakage current. [Means for solving the problem]

[0007] The voltage detection circuit according to claim 1 is a fully differential voltage detection circuit that receives the voltages of a pair of input nodes (Nip, Nim), detects the difference between the voltages, and outputs the difference from a pair of output nodes (Nop, Nom), and includes a plurality of switches (S1 to S4, S71) and a capacitive couple driver (14). The plurality of switches are provided between the pair of input nodes and the pair of output nodes, and include series circuits (SC1 to SC4, 76, 79) in which two MOS transistors (15 to 22, 74 to 78) are connected in series. The capacitive couple driver includes driving capacitances (Cdr1 to Cdr4), and controls the on / off of each of the plurality of switches by driving the gates of the MOS transistors included in the plurality of switches via the driving capacitances. In this case, the back gates of the MOS transistors are connected to the terminals of the source or drain that are not connected to the intermediate node (N1 to N4, N71, N72) that is the interconnection node of the two MOS transistors.

[0008] In this way, in each of the multiple switches, the body diodes of the two MOS transistors face each other. Therefore, with the above configuration, no current flows through the body diode, and no errors occur. In particular, since no backflow occurs through the body diode when a negative voltage is input, the occurrence of errors associated with this can be suppressed. Therefore, with the above configuration, it is possible to obtain the excellent effect of being able to accurately detect a wide range of voltages while suppressing the occurrence of leakage current. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram illustrating a configuration of a voltage detection circuit according to a first embodiment; [Diagram 2] FIG. 1 is a diagram showing a schematic configuration of a battery monitoring IC according to a first embodiment; [Diagram 3] FIG. 1 is a diagram showing a specific example of the configuration of a switch circuit and a leak cancel circuit according to a first embodiment; [Figure 4] FIG. 1 is a diagram for explaining the potential state of each part during a sample period when a positive voltage is input according to the first embodiment; [Diagram 5] FIG. 1 is a diagram for explaining the potential state of each part during a hold period when a positive voltage is input according to the first embodiment; [Figure 6] FIG. 1 is a diagram for explaining the potential state of each part during a sample period when a negative voltage is input according to the first embodiment; [Figure 7] FIG. 1 is a diagram showing an example of an operating range, an indeterminate range, a voltage range, and a transmission range of each unit according to the first embodiment; [Figure 8] FIG. 1 is a schematic diagram showing a configuration of a ΔΣ modulator according to a modified example; [Figure 9] FIG. 11 is a diagram illustrating a configuration of a voltage detection circuit according to a second embodiment. [Figure 10] FIG. 13 is a diagram showing a specific configuration example of a switch circuit according to a second embodiment; [Figure 11] FIG. 13 is a diagram showing a specific configuration example of a switch circuit according to a third embodiment; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, a number of embodiments will be described with reference to the drawings. Note that the same reference numerals are used to designate substantially the same components in the respective embodiments, and the description thereof will be omitted. (First embodiment) The first embodiment will be described below with reference to FIGS.

[0011] <Overall composition> As shown in Fig. 1, the voltage detection circuit 1 of this embodiment includes a fully differential switched capacitor amplifier 2 having a pair of input nodes Nip and Nim and a pair of output nodes Nop and Nom, and various circuits (not shown). In this specification, the switched capacitor amplifier may be abbreviated as SC amplifier. The voltage detection circuit 1 receives the voltage VINP of the input node Nip and the voltage VINM of the input node Nim, detects the difference voltage between them, and outputs it from the output nodes Nop and Nom. The voltage detection circuit 1 is configured as an IC mounted on a vehicle such as an automobile together with other circuit elements (not shown).

[0012] The SC amplifier 2 includes a differential output type operational amplifier 3, capacitors Cs1, Cs2, Cf1, Cf2, Cd1, and Cd2, and switches S1 to S16. The on / off of the switches S1 to S16 is controlled by a control circuit (not shown). Each of the capacitors including the capacitors Cs1, Cs2, Cf1, Cf2, Cd1, and Cd2 includes two terminals. In this specification, in order to distinguish between the two terminals of a capacitor, one of the two terminals may be referred to as a first terminal and the other of the two terminals may be referred to as a second terminal.

[0013] A first terminal of the capacitor Cs1 is connected to the inverting input terminal of the operational amplifier 3. A common potential VCM can be applied to the first terminal of the capacitor Cs1 via a switch S5. A second terminal of the capacitor Cs1 is connected to the input node Nip via a switch S1 and is connected to the input node Nim via a switch S2. A first terminal of the capacitor Cs2 is connected to the non-inverting input terminal of the operational amplifier 3. A common potential VCM can be applied to the first terminal of the capacitor Cs2 via a switch S6. A second terminal of the capacitor Cs2 is connected to the input node Nim via a switch S3 and is connected to the input node Nip via a switch S4.

[0014] In this way, the first terminals of the paired capacitors Cs1 and Cs2 in the differential configuration are connected to the input terminals of the operational amplifier 3, and function as a pair of sampling capacitors. The capacitors Cs1 and Cs2 have the same capacitance value. In this specification, the term "same capacitance value" does not only refer to capacitors whose capacitance values ​​are completely the same, but also includes capacitors whose capacitance values ​​are slightly different and not strictly the same, as long as the desired effect is achieved.

[0015] A first terminal of the capacitor Cf1 is connected to the inverting input terminal of the operational amplifier 3. A second terminal of the capacitor Cf1 is connected to the non-inverting output terminal of the operational amplifier 3 via the switch S7. That is, the capacitor Cf1 is connected between the inverting input terminal and the non-inverting output terminal of the operational amplifier 3 via the switch S7. A common potential VCM can be applied to the second terminal of the capacitor Cf1 via the switch S8.

[0016] A first terminal of the capacitor Cf2 is connected to the non-inverting input terminal of the operational amplifier 3. A second terminal of the capacitor Cf2 is connected to the inverting output terminal of the operational amplifier 3 via the switch S9. That is, the capacitor Cf2 is connected between the non-inverting input terminal and the inverting output terminal of the operational amplifier 3 via the switch S9. A common potential VCM can be applied to the second terminal of the capacitor Cf2 via the switch S10. In this way, the pair of capacitors Cf1 and Cf2 in the differential configuration are connected between the input terminal and the output terminal of the operational amplifier 3, and function as a pair of feedback capacitances. The capacitors Cf1 and Cf2 have the same capacitance value.

[0017] A first terminal of the capacitor Cd1 is connected to an inverting input terminal of the operational amplifier 3. A reference voltage VREFP can be applied to a second terminal of the capacitor Cd1 via a switch S11. A common potential VCM can be applied to a second terminal of the capacitor Cd1 via a switch S12. A reference voltage VREFM can be applied to a second terminal of the capacitor Cd1 via a switch S13. The reference voltages VREFP and VREFM are examples of DAC voltages output from a D / A converter (not shown). In this specification, the D / A converter may be abbreviated as DAC.

[0018] A first terminal of the capacitor Cd2 is connected to the non-inverting input terminal of the operational amplifier 3. A reference voltage VREFP can be applied to a second terminal of the capacitor Cd2 via a switch S14. A common potential VCM can be applied to a second terminal of the capacitor Cd2 via a switch S15. A reference voltage VREFM can be applied to a second terminal of the capacitor Cd2 via a switch S16. In this way, the capacitors Cd1 and Cd2 that form a pair in the differential configuration can store charge according to the DAC voltage, and have first terminals connected to the input terminals of the operational amplifier 3, functioning as a pair of DAC capacitances. The capacitors Cd1 and Cd2 have the same capacitance value.

[0019] Although not shown, the SC amplifier 2 includes a common mode feedback circuit that controls the common-mode level of the output voltage of the operational amplifier 3. In the above configuration, the common mode feedback circuit operates to feedback control the common-mode level of the output voltage of the operational amplifier 3 to the common potential VCM. Note that in the SC amplifier 2, the common potentials of all circuits are set to the common potential VCM.

[0020] The SC amplifier 2 samples the input voltages VINP and VINM, which are applied via a pair of input nodes Nip and Nim, using capacitors Cs1 and Cs2. The SC amplifier 2 transfers the charge sampled in this way via capacitors Cf1 and Cf2, and outputs output voltages VOUTP and VOUTM, which are the amplified input voltages VINP and VINM, from the output terminals of the operational amplifier 3. The non-inverting output terminal of the operational amplifier 3 is connected to the output node Nop. The inverting output terminal of the operational amplifier 3 is connected to the output node Nom. Therefore, the output voltages VOUTP and VOUTM are output to the subsequent circuit via the pair of output nodes Nop and Nom.

[0021] <Application example of voltage detection circuit> As shown in Fig. 2, the voltage detection circuit 1 of this embodiment can be applied to a battery monitoring IC 5 that monitors an assembled battery 4 mounted on a vehicle. The assembled battery 4 is a lithium ion battery, a fuel cell, or the like, and multiple battery cells 4a, 4b, etc. are connected in series in multiple stages. Therefore, a common mode voltage is superimposed on the multiple battery cells 4a, 4b, etc. This common mode voltage becomes higher as the battery cell is connected to the upper stage side of the assembled battery 4, i.e., the higher potential side, and the maximum value of the common mode voltage becomes a relatively high voltage of, for example, about several hundred volts. Note that Fig. 2 only illustrates two battery cells 4a, 4b, which are part of the battery cells, and the configuration corresponding to them.

[0022] The negative terminal P9 of the battery cell (not shown) located at the bottom of the battery pack 4, i.e., on the lowest potential side, is connected to the ground line Lg. The battery monitoring IC 5 has functions such as detecting the voltage between the terminals of the battery pack 4, i.e., the battery cells 4a and 4b, and amplifying the voltage. The battery monitoring IC 5 also has a function of detecting the current flowing through the battery cells 4a and 4b. The battery monitoring IC 5 has terminals P1 and P2 corresponding to the terminals of the battery cell 4a, terminals P3 and P4 corresponding to the terminals of the battery cell 4b, and a terminal P9 for supplying a ground potential of 0V.

[0023] Each terminal of the battery cell 4a is connected to terminals P1, P2 via a filter 6a. The filter 6a is an RC filter and includes resistors R1, R2 and a capacitor C1. Each terminal of the battery cell 4b is connected to terminals P3, P4 via a filter 6b. The filter 6b is an RC filter configured similarly to the filter 6a, and includes resistors R3, R4 and a capacitor C2. The terminal P9 is configured as the negative terminal of the battery cell with the lowest potential, and is connected to the ground line Lg.

[0024] The battery monitoring IC 5 includes a multiplexer 7 and a switch circuit 8 in addition to the voltage detection circuit 1. The voltage detection circuit 1 includes an SC amplifier 2, a control circuit 9, a leak cancellation circuit 10, an A / D converter 11, and various digital circuits (not shown). In this specification, the A / D converter may be abbreviated as ADC. The control circuit 9 controls the overall operation of the battery monitoring IC 5, and includes as part of its configuration a capacitive couple driver that controls the on / off of the switches S1 to S4 included in the voltage detection circuit 1.

[0025] The leak cancel circuit 10 includes a DAC 10a, an amplifier 10b, and two switched capacitor blocks 10c and 10d connected in parallel. The leak cancel circuit 10 is a differential circuit that cancels the charge leaked from a pair of input nodes Nip and Nim due to the operation of the voltage detection circuit 1, more specifically, the operation of the switches S1 to S4, that is, the leak current. In FIG. 2, the leak cancel circuit is abbreviated as LC circuit, and the switched capacitor block is abbreviated as SCB.

[0026] The multiplexer 7 selects one of the voltages at terminals P1 and P2, the voltages at terminals P3 and P4, etc., by switching on and off the switches Sm1, Sm2, Sm3, Sm4, etc., and outputs it to the subsequent stage. The differential analog signal selected by the multiplexer 7 is input to the voltage detection circuit 1 via a switch circuit 8 including a chop switch in which four switches Sh1, Sh2, Sh3, and Sh4 are cross-connected. In the voltage detection circuit 1, the SC amplifier 2 receives and integrates the differential analog signal, and outputs the integrated voltage to the subsequent ADC 11. When the ADC 11 receives the integrated voltage, it quantizes it into multiple levels and outputs it digitally. The digital output is output digitally after a predetermined digital processing.

[0027] According to the above configuration, a pair of input nodes Nip, Nim of the voltage detection circuit 1 can be connected to the terminals of each of the battery cells 4a, 4b, ... that make up the battery pack 4. The voltage detection circuit 1 constitutes a part of a differential sample-and-hold circuit that outputs a detection voltage corresponding to the input voltages VINP, VINM. The voltage detection circuit 1 also constitutes a part of a level shift circuit that reduces a relatively high common-mode voltage superimposed on each of the battery cells 4a, 4b, ... to a relatively low common-mode voltage.

[0028] The output voltages VOUTP and VOUTM output from the SC amplifier 2 of the voltage detection circuit 1 correspond to detection voltages corresponding to the input voltages VINP and VINM, and are converted to digital data by the ADC 11 of a differential input format. This digital data represents the detection values ​​of the input voltages VINP and VINM, and is acquired by a higher-level control device (not shown). The voltage detection circuit 1 is configured to be able to add an offset so that the output voltages VOUTP and VOUTM fall within the input voltage range of the ADC 11, for example, a voltage range of +2.5V to -2.5V.

[0029] <Specific configurations of the switch circuit and the leak cancellation circuit> In the above configuration, the multiple switches S1 to S4 connected between the pair of input nodes Nip, Nim and the pair of sampling capacitors Cs1, Cs2, together with the selector 13 and the capacitive couple driving unit 14, constitute a switch circuit 12, which is a CCSW circuit, as shown in Figures 1 and 2. Note that in Figures 1 and 2, the configurations of the selector 13 and the capacitive couple driving unit 14 are shown in a simplified manner, but their detailed configurations will be described later with reference to Figure 3. The switch circuit 12 including the switches S1 to S4 constitutes a part of the SC amplifier 2, and as a specific configuration thereof, for example, a configuration as shown in Figure 3 can be adopted.

[0030] In the following description, of the pair of input nodes Nip, Nim, the input node Nip on the high potential side may be referred to as the first input node, and the input node Nim on the low potential side may be referred to as the second input node. In the following description, of the multiple switches S1 to S4, the switches S1 and S4 connected to the first input node may be referred to as the first switch, and the switches S2 and S3 connected to the second node may be referred to as the second switch.

[0031] 3, in addition to switches S1 to S4, the switch circuit 12 includes a selector 13 and a capacitive couple driver 14. The switches S1 to S4 are provided between input nodes Nip, Nim and output nodes Nop, Nom so as to be capable of opening and closing the nodes, and include a series circuit in which two MOS transistors are connected in series. In this case, the MOS transistor of the first switch is a P-channel type MOS transistor, and the MOS transistor of the second switch is an N-channel type MOS transistor.

[0032] The specific configuration of the switches S1 to S4 is as follows. The two MOS transistors 15 and 16 included in the switch S1 are both P-channel type MOS transistors. In this specification, the P-channel type MOS transistor may be abbreviated as PMOS. In other words, the switch S1 includes a series circuit SC1 in which two PMOSs 15 and 16 are connected in series. The source of the PMOS 15 is connected to the input node Nip, and its drain is connected to the node N1. The drain of the PMOS 16 is connected to the node N1, and its source is connected to the node Np.

[0033] The node N1 is an example of an intermediate node which is an interconnection node between two PMOSs 15 and 16. The node Np is connected to the second terminal of the capacitor Cs1 and corresponds to the high potential output node of the pair of output nodes of the switch circuit 12. The back gate of the PMOS 15 is connected to its source. The back gate of the PMOS 16 is connected to its source. In other words, the back gates of the PMOSs 15 and 16 are connected to the terminal of their source or drain that is not connected to the intermediate node, the node N1.

[0034] In addition, since the back gate and the body are synonymous in a MOS transistor, in this specification, the back gate of each MOS transistor including PMOS 15 and 16 may be referred to as the body. Between the body and drain of PMOS 15, there is a body diode D15 with the drain side as the anode. Between the body and drain of PMOS 16, there is a body diode D16 with the drain side as the anode. That is, in the switch S1, the body diodes D15 and D16 face each other. The gates of PMOS 15 and 16 are connected to the capacitive couple driver 14, and the on / off of these diodes is controlled by the capacitive couple driver 14.

[0035] The two MOS transistors 17 and 18 included in the switch S2 are both N-channel type MOS transistors. In this specification, an N-channel type MOS transistor may be abbreviated as NMOS. That is, the switch S2 includes a series circuit SC2 in which two NMOS transistors 17 and 18 are connected in series. The source of the NMOS 17 is connected to the input node Nim, and its drain is connected to the node N2. The drain of the NMOS 18 is connected to the node N2, and its source is connected to the node Np.

[0036] Node N2 is an example of an intermediate node that is an interconnection node between two NMOSs 17 and 18. The backgate of NMOS 17 is connected to its source. The backgate of NMOS 18 is connected to its source. In other words, the backgates of NMOSs 17 and 18 are connected to the terminal of their source or drain that is not connected to node N2, which is the intermediate node.

[0037] Between the body and drain of NMOS17, there is a body diode D17 with the body side as the anode. Between the body and drain of NMOS18, there is a body diode D18 with the body side as the anode. That is, the body diodes D17 and D18 face each other in the switch S2. The gates of NMOS17 and NMOS18 are connected to the capacitive couple driver 14, and their on / off is controlled by the capacitive couple driver 14.

[0038] The two MOS transistors 19 and 20 of the switch S3 are both NMOS. That is, the switch S3 includes a series circuit SC3 in which two NMOS transistors 19 and 20 are connected in series. The source of the NMOS 19 is connected to the input node Nim, and its drain is connected to a node N3. The drain of the NMOS 20 is connected to the node N3, and its source is connected to a node Nm. The node N3 is an example of an intermediate node that is an interconnection node between the two NMOS transistors 19 and 20.

[0039] The node Nm is connected to the second terminal of the capacitor Cs2 and corresponds to the lower potential output node of the pair of output nodes of the switch circuit 12. The back gate of the NMOS 19 is connected to its source. The back gate of the NMOS 20 is connected to its source. That is, the back gates of the NMOSs 19 and 20 are connected to the terminal of their source or drain that is not connected to the intermediate node, the node N3.

[0040] Between the body and drain of NMOS19, there is a body diode D19 with the body side as the anode. Between the body and drain of NMOS20, there is a body diode D20 with the body side as the anode. That is, the body diodes D19 and D20 face each other in the switch S3. The gates of NMOS19 and 20 are connected to the capacitive couple driver 14, and their on / off is controlled by the capacitive couple driver 14.

[0041] The two MOS transistors 21 and 22 of the switch S4 are both PMOS. That is, the switch S4 includes a series circuit SC4 in which two PMOS transistors 21 and 22 are connected in series. The source of the PMOS 21 is connected to the input node Nip, and its drain is connected to a node N4. The drain of the PMOS 22 is connected to the node N4, and its source is connected to a node Nm. The node N4 is an example of an intermediate node that is an interconnection node between the two PMOS transistors 21 and 22.

[0042] The back gate of PMOS 21 is connected to its source. The back gate of PMOS 22 is connected to its source. In other words, the back gates of PMOS 21 and 22 are connected to the terminal of their source or drain that is not connected to node N4, which is the intermediate node.

[0043] Between the body and drain of PMOS21, there is a body diode D21 with the drain side as the anode. Between the body and drain of PMOS22, there is a body diode D22 with the drain side as the anode. That is, the body diodes D21 and D22 face each other in the switch S4. The gates of PMOS21 and PMOS22 are connected to the capacitive couple driver 14, and their on / off is controlled by the capacitive couple driver 14.

[0044] The selector 13 is connected between a pair of input nodes Nip and Nim, selects one of the voltages VINP and VINM of the pair of input nodes Nip and Nim, and outputs a selection signal having a potential corresponding to the selected voltage, and includes a maximum selector 23, a minimum selector 24, and a Zener diode 25. The maximum selector 23 and the minimum selector 24 each include two MOS transistors connected in series between the pair of input nodes Nip and Nim. The two MOS transistors included in the maximum selector 23 are PMOSs 26 and 27.

[0045] The drain of PMOS 26 is connected to the input node Nip, and the drain of PMOS 27 is connected to the input node Nim. The gate of PMOS 26 is connected to the input node Nim, and the gate of PMOS 27 is connected to the input node Nip. The sources and back gates of PMOS 26 and 27 are all connected to a node N5. The node N5 is an output node for outputting a selection signal Vmax in the maximum selector 23, and is connected to a signal line 28. In other words, the maximum selector 23 is configured to output a signal of the node N5, which is an interconnection node between the two PMOSs 26 and 27, as the selection signal Vmax.

[0046] Between the body and drain of the PMOS26, there is a body diode D26 with the drain side as the anode. Between the body and drain of the PMOS27, there is a body diode D27 with the drain side as the anode. That is, in the maximum selector 23, the body diodes D26 and D27 face each other. With this configuration, the maximum selector 23 selects the higher of the voltages VINP and VINM, and outputs a selection signal Vmax having a potential corresponding to the selected voltage to other circuits via the node N5 and the signal line 28.

[0047] A normal MOS transistor having a normal threshold is used as the PMOS 27, which is one of the two PMOSs 26 and 27 included in the maximum selector 23. A low-threshold MOS transistor having a threshold lower than the normal threshold is used as the other PMOS 26, which is the PMOS 26, which is the other of the two PMOSs 26 and 27 included in the maximum selector 23. The low-threshold MOS transistor also includes a depletion MOS transistor having a threshold of 0V. In this embodiment, a depletion MOS transistor is used as the PMOS 26. In FIG. 2 and other figures, the symbols of MOS transistors using depletion MOS transistors are distinguished by adding an * mark near the gate.

[0048] The two MOS transistors included in the minimum selector 24 are NMOS 29 and 30. The drain of the NMOS 29 is connected to the input node Nip, and the drain of the NMOS 30 is connected to the input node Nim. The gate of the NMOS 29 is connected to the input node Nim, and the gate of the NMOS 30 is connected to the input node Nip. The sources and back gates of the NMOS 29 and 30 are both connected to a node N6. The node N6 is an output node for outputting a selection signal Vmin in the minimum selector 24, and is connected to a signal line 31. In other words, the minimum selector 24 is configured to output a signal of the node N6, which is an interconnection node between the two NMOSs 29 and 30, as the selection signal Vmin.

[0049] Between the body and drain of NMOS29, there is a body diode D29 with the body side as the anode. Between the body and drain of NMOS30, there is a body diode D30 with the body side as the anode. That is, in the minimum selector 24, the body diodes D29 and D30 face each other. With this configuration, the minimum selector 24 selects the lower voltage of the voltages VINP and VINM, and outputs a selection signal Vmin having a potential corresponding to the selected voltage to other circuits via the node N6 and the signal line 31.

[0050] A normal MOS transistor having a normal threshold is used as the NMOS 29, which is one of the two NMOSs 29 and 30 included in the minimum selector 24. A low-threshold MOS transistor having a threshold lower than the normal threshold is used as the other NMOS 30, which is the other of the two NMOSs 29 and 30 included in the minimum selector 24. In this embodiment, a depletion MOS transistor is used as the NMOS 30.

[0051] In the selector 13 having the above configuration, there exists an operation indeterminate region where the selector 13 cannot operate normally depending on the difference between the voltages VINP and VINM of the input nodes Nip and Nim. Therefore, in the above configuration, a Zener diode 25 with the node N6 side as the anode is connected between the nodes N5 and N6. As a result, in the above operation indeterminate region, the selection signals Vmax and Vmin are fixed to a predetermined potential relationship.

[0052] In the above configuration, switches S1 to S4 are provided on the input side of the operational amplifier 3. These switches S1 to S4, together with the capacitors Cs1 and Cs2, form an RC filter, thereby increasing the input impedance of the operational amplifier 3. Therefore, in the above configuration, the operational amplifier 3 is easily affected by the leakage current flowing in from the multiplexer 7 side, and a leakage cancellation circuit 10 is provided to eliminate this effect. As shown in FIG. 2, the leakage cancellation circuit 10 is connected to the input nodes Nip and Nim.

[0053] The leak cancellation circuit 10 has a configuration as shown in FIG. 2. The DAC 10a is configured to receive a digital command value for creating a compensation current, convert it into analog, output two command voltages, and input them to the amplifier 10b. The DAC 10a is configured as a fully differential DAC. The fully differential DAC outputs two command voltages, a first voltage that is directly proportional to the digital command value with a positive gradient, and a second voltage that is directly proportional to the digital command value with a negative gradient. The DAC 10a may be configured as a pseudo-differential DAC. The pseudo-differential DAC outputs two command voltages, a first voltage that is constant regardless of the digital command value, and a second voltage that is directly proportional to the digital command value.

[0054] The amplifier 10b is composed of two single-ended buffers configured as voltage followers. The amplifier 10b receives the two command voltages output by the DAC 10a, performs impedance conversion by the voltage followers, and outputs voltages Vdp and Vdm. The two switched capacitor blocks 10c and 10d are configured to switch the outputs of the two buffers to charge and discharge a pair of capacitors and output the same voltages.

[0055] The switched capacitor blocks 10c and 10d include four switches connected to the front stages of the two capacitors, that is, between the two buffers and the first terminals of the two capacitors, and three switches connected to the rear stages of the two capacitors, that is, between the second terminals of the two capacitors and the input nodes Nip and Nim. Figure 3 shows three switches connected to the rear stages of the two capacitors among the switches included in the leak cancellation circuit 10.

[0056] Specifically, three switches SL1, SL2, and SL3 connected to the rear stages of two capacitors in the switched capacitor block 10c and three switches SL4, SL5, and SL6 connected to the rear stages of two capacitors in the switched capacitor block 10d are shown in Fig. 3. Also shown in Fig. 3 are a pair of input nodes NLi1 and NLi2 connected to the second terminals of the two capacitors in the switched capacitor block 10c, and a pair of input nodes NLi3 and NLi4 connected to the second terminals of the two capacitors in the switched capacitor block 10d.

[0057] The input nodes NLi1, NLi2 and the input nodes NLi3, NLi4 all function as a pair of cancellation input nodes for inputting cancellation charges for canceling leaking charges. In the above configuration, in accordance with the operation of the leakage cancellation circuit 10, signals CLDAP, CLDAM, CLDBP, and CLDBM corresponding to the cancellation charges are provided to the input nodes NLi1, NLi2, NLi3, and NLi4, respectively.

[0058] The switches SL1 to SL3 are provided so as to be capable of opening and closing between a pair of input nodes Nip, Nim and a pair of input nodes NLi1, NLi2, and function as a plurality of cancel switches. The switches SL1 to SL3 include a series circuit configured by connecting two MOS transistors in series. However, the switch SL3 includes two of the above-mentioned series circuits, and these two series circuits are connected in parallel. The switches SL4 to SL6 are provided so as to be capable of opening and closing between a pair of input nodes Nip, Nim and a pair of input nodes NLi3, NLi4, and function as a plurality of cancel switches. The switches SL4 to SL6 include a series circuit configured by connecting two MOS transistors in series. However, the switch SL6 includes two of the above-mentioned series circuits, and these two series circuits are connected in parallel.

[0059] In the following description, of the pair of input nodes NLi1, NLi2 and the pair of input nodes NLi3, NLi4, the high potential input nodes NLi1, NLi3 may be referred to as the first cancel input node, and the low potential input nodes NLi2, NLi4 may be referred to as the second cancel input node. Also, in the following description, of the multiple switches SL1 to SL6, the switches SL1, SL4 connected between the first input node and the first cancel input node may be referred to as the first cancel switch, the switches SL2, SL5 connected between the second input node and the second cancel input node may be referred to as the second cancel switch, and the switches SL3, SL6 connected between the first cancel input node and the second cancel input node may be referred to as the third cancel switch.

[0060] In this case, the two MOS transistors of the first cancel switch are both PMOS, and the two MOS transistors of the second cancel switch are both NMOS. In this case, the two MOS transistors of one of the two series circuits of the third cancel switch are both PMOS, and the two MOS transistors of the other of the two series circuits of the third cancel switch are both NMOS transistors.

[0061] The specific configuration of the switches SL1 to SL6 is as follows. The two MOS transistors 41 and 42 of the switch SL1 are both PMOS. That is, the switch SL1 includes a series circuit SCL1 in which two PMOS transistors 41 and 42 are connected in series. The source of the PMOS 41 is connected to the input node Nip, and its drain is connected to the node NL1. The drain of the PMOS 42 is connected to the node NL1, and its source is connected to the input node NLi1.

[0062] The node NL1 is an example of an intermediate node that is an interconnection node between two PMOS 41 and 42. The backgate of the PMOS 41 is connected to its source. The backgate of the PMOS 42 is connected to its source. In other words, the backgates of the PMOS 41 and 42 are connected to the terminal of their source or drain that is not connected to the intermediate node, the node NL1.

[0063] Between the body and drain of the PMOS 41, there is a body diode D41 with the drain side as the anode. Between the body and drain of the PMOS 42, there is a body diode D42 with the drain side as the anode. That is, the body diodes D41 and D42 face each other in the switch SL1. The gates of the PMOSs 41 and 42 are connected to the capacitive couple driver 14, and the on / off of these diodes is controlled by the capacitive couple driver 14.

[0064] The two MOS transistors 43 and 44 of the switch SL2 are both NMOS. That is, the switch SL2 includes a series circuit SCL2 in which two NMOS transistors 43 and 44 are connected in series. The source of the NMOS 43 is connected to the input node Nim, and its drain is connected to the node NL2. The drain of the NMOS 44 is connected to the node NL2, and its source is connected to the node NLi2.

[0065] The node NL2 is an example of an intermediate node that is an interconnection node between two NMOSs 43 and 44. The backgate of the NMOS 43 is connected to its source. The backgate of the NMOS 44 is connected to its source. In other words, the backgates of the NMOSs 43 and 44 are connected to the terminals of their sources or drains that are not connected to the intermediate node, the node NL2.

[0066] Between the body and drain of NMOS 43, there is a body diode D43 with the body side as the anode. Between the body and drain of NMOS 44, there is a body diode D44 with the body side as the anode. That is, the body diodes D43 and D44 face each other in the switch SL2. The gates of NMOS 43 and 44 are connected to the capacitive couple driver 14, and the on / off of these diodes is controlled by the capacitive couple driver 14.

[0067] The switch SL3 includes two PMOS transistors 45 and 46 and two NMOS transistors 47 and 48. The switch SL3 includes a series circuit SCL3a in which the two PMOS transistors 45 and 46 are connected in series, and a series circuit SCL3b in which the two NMOS transistors 47 and 48 are connected in series. The switch SL3 is configured by connecting the two series circuits SCL3a and SCL3b in parallel. The source of the PMOS transistor 45 is connected to the input node NLi1, and its drain is connected to the node NL3a. The drain of the PMOS transistor 46 is connected to the node NL3a, and its source is connected to the input node NLi2.

[0068] The node NL3a is an example of an intermediate node that is an interconnection node between two PMOSs 45 and 46. The backgate of the PMOS 45 is connected to its source. The backgate of the PMOS 46 is connected to its source. In other words, the backgates of the PMOSs 45 and 46 are connected to the terminals of their sources or drains that are not connected to the intermediate node, the node NL3a.

[0069] Between the body and drain of the PMOS 45, there is a body diode D45 with the drain side as the anode. Between the body and drain of the PMOS 46, there is a body diode D46 with the drain side as the anode. That is, in the series circuit SCL3a of the switch SL3, the body diodes D45 and D46 face each other. The gates of the PMOSs 45 and 46 are connected to the capacitive couple driver 14, and the on / off of these diodes is controlled by the capacitive couple driver 14.

[0070] The source of the NMOS 47 is connected to the input node NLi1, and its drain is connected to the node NL3b. The drain of the NMOS 48 is connected to the node NL3b, and its source is connected to the input node NLi2. The node NL3b is an example of an intermediate node that is an interconnection node between the two NMOSs 47 and 48. The backgate of the NMOS 47 is connected to its source. The backgate of the NMOS 48 is connected to its source. In other words, the backgates of the NMOSs 47 and 48 are connected to the terminal of their source or drain that is not connected to the intermediate node, the node NL3b.

[0071] Between the body and drain of the NMOS 47, there is a body diode D47 with the body side as the anode. Between the body and drain of the NMOS 48, there is a body diode D48 with the body side as the anode. That is, in the series circuit SCL3b of the switch SL3, the body diodes D47 and D48 face each other. The gates of the NMOSs 47 and 48 are connected to the capacitive couple driver 14, and their on / off is controlled by the capacitive couple driver 14.

[0072] The two MOS transistors 49 and 50 of the switch SL4 are both PMOS. That is, the switch SL4 includes a series circuit SCL4 in which two PMOS transistors 49 and 50 are connected in series. The source of the PMOS 49 is connected to the input node Nip, and its drain is connected to the node NL4. The drain of the PMOS 50 is connected to the node NL4, and its source is connected to the input node NLi3.

[0073] Node NL4 is an example of an intermediate node that is an interconnection node between two PMOS 49 and 50. The backgate of PMOS 49 is connected to its source. The backgate of PMOS 50 is connected to its source. In other words, the backgates of PMOS 49 and 50 are connected to the terminals of their sources or drains that are not connected to node NL4, which is the intermediate node.

[0074] Between the body and drain of PMOS49, there is a body diode D49 with the drain side as the anode. Between the body and drain of PMOS50, there is a body diode D50 with the drain side as the anode. That is, the body diodes D49 and D50 face each other in the switch SL4. The gates of PMOS49 and 50 are connected to the capacitive couple driver 14, and their on / off is controlled by the capacitive couple driver 14.

[0075] The two MOS transistors 51 and 52 of the switch SL5 are both NMOS. That is, the switch SL5 includes a series circuit SCL5 in which two NMOS transistors 51 and 52 are connected in series. The source of the NMOS 51 is connected to the input node Nim, and its drain is connected to the node NL5. The drain of the NMOS 52 is connected to the node NL5, and its source is connected to the node NLi4.

[0076] The node NL5 is an example of an intermediate node that is an interconnection node between two NMOSs 51 and 52. The backgate of the NMOS 51 is connected to its source. The backgate of the NMOS 52 is connected to its source. In other words, the backgates of the NMOSs 51 and 52 are connected to the terminal of their source or drain that is not connected to the intermediate node, the node NL5.

[0077] Between the body and drain of NMOS 51, there is a body diode D51 with the body side as the anode. Between the body and drain of NMOS 52, there is a body diode D52 with the body side as the anode. That is, the body diodes D51 and D52 face each other in the switch SL5. The gates of NMOS 51 and 52 are connected to the capacitive couple driver 14, and the on / off of these diodes is controlled by the capacitive couple driver 14.

[0078] The switch SL6 includes two PMOS transistors 53 and 54 and two NMOS transistors 55 and 56. The switch SL6 includes a series circuit SCL6a in which the two PMOS transistors 53 and 54 are connected in series, and a series circuit SCL6b in which the two NMOS transistors 55 and 56 are connected in series. The switch SL6 is configured by connecting the two series circuits SCL6a and SCL6b in parallel. The source of the PMOS transistor 53 is connected to the input node NLi3, and its drain is connected to the node NL6a. The drain of the PMOS transistor 54 is connected to the node NL6a, and its source is connected to the input node NLi4.

[0079] The node NL6a is an example of an intermediate node that is an interconnection node between two PMOSs 53 and 54. The backgate of the PMOS 53 is connected to its source. The backgate of the PMOS 54 is connected to its source. In other words, the backgates of the PMOSs 53 and 54 are connected to the terminal of their source or drain that is not connected to the intermediate node, the node NL6a.

[0080] Between the body and drain of PMOS53, there is a body diode D53 with the drain side as the anode. Between the body and drain of PMOS54, there is a body diode D54 with the drain side as the anode. That is, in the series circuit SCL6a of switch SL6, the body diodes D53 and D54 face each other. The gates of PMOS53 and PMOS54 are connected to the capacitive couple driver 14, and the on / off of these diodes is controlled by the capacitive couple driver 14.

[0081] The source of NMOS 55 is connected to the input node NLi3, and its drain is connected to node NL6b. The drain of NMOS 56 is connected to node NL6b, and its source is connected to input node NLi4. Node NL6b is an example of an intermediate node that is an interconnection node between two NMOSs 55 and 56. The backgate of NMOS 55 is connected to its source. The backgate of NMOS 56 is connected to its source. In other words, the backgates of NMOSs 55 and 56 are connected to the terminal of their source or drain that is not connected to node NL6b, which is the intermediate node.

[0082] Between the body and drain of NMOS 55, there is a body diode D55 with the body side as the anode. Between the body and drain of NMOS 56, there is a body diode D56 with the body side as the anode. That is, in the series circuit SCL6b of switch SL6, the body diodes D55 and D56 face each other. The gates of NMOS 55 and 56 are connected to the capacitive couple driver 14, and their on / off is controlled by the capacitive couple driver 14.

[0083] The capacitive couple driving unit 14 controls the operations of the switches S1 to S4 and SL1 to SL6 based on binary control signals SLSA0n, SLSB0n, SLSA0p, and SLSB0p provided from the outside. The high level of the control signals SLSA0n to SLSB0p is +5V, and the low level is 0V. The capacitive couple driving unit 14 is configured to control the on / off of the switches S1 to S4 and SL1 to SL6 by driving the gates of the MOS transistors 15 to 22 and 41 to 56 via the driving capacitances Cdr1 to Cdr4.

[0084] The capacitive couple driver 14 is configured as a part of the control circuit 9 described above, and is specifically configured as follows. That is, the capacitive couple driver 14 includes a plurality of driving capacitances Cdr1, Cdr2, Cdr3, and Cdr4 provided corresponding to the switches S1 to S4, respectively, a PMOS driver 33, and an NMOS driver 34. In the following description, the PMOS driver 33 and the NMOS driver 34 may be simply referred to as the drivers 33 and 34. The driving capacitance Cdr1 is connected between a node N7 to which a control signal SLSA0n is applied and a node N8. The node N8 is connected to the gates of the PMOSs 15, 16, 41, 42, 53, and 54 of the switches S1, SL1, and SL6. The driving capacitance Cdr2 is connected between a node N9 to which a control signal SLSB0p is applied and a node N10. The node N10 is connected to the gates of the NMOSs 17, 18, 47, 48, 51 and 52 of the switches S2, SL3 and SL5.

[0085] The driving capacitance Cdr3 is connected between a node N11 to which a control signal SLSA0p is applied and a node N12. The node N12 is connected to the gates of NMOSs 19, 20, 43, 44, 55, and 56 of the switches S3, SL2, and SL6. The driving capacitance Cdr4 is connected between a node N13 to which a control signal SLSB0n is applied and a node N14. The node N14 is connected to the gates of PMOSs 21, 22, 45, 46, 49, and 50 of the switches S4, SL3, and SL4. In this embodiment, the driving capacitances Cdr1 to Cdr4 are configured by comb capacitances.

[0086] The driving units 33 and 34 supply driving signals SLSAn, SLSBn, SLSAp, and SLSBp to the gates of the MOS transistors 15-22 and 41-56 constituting the switches S1-S4 and SL1-SL6, respectively. The driving signals SLSAn to SLSBp are binary signals that are either an off level that turns off the MOS transistors 15-22 and 41-56, or an on level that turns on the MOS transistors 15-22 and 41-56. The on and off levels are specifically as follows:

[0087] That is, when the driving target is an NMOS, the on level is a level that satisfies the following formula (1), and when the driving target is a PMOS, the on level is a level that satisfies the following formula (2), and the off level is a level that satisfies the following formula (3), where VGS is the gate-source voltage of the MOS transistor, and Vt is the threshold voltage of the MOS transistor. VGS>Vt …(1) VGS<-Vt …(2) VGS ≒ 0 … (3)

[0088] The PMOS driver 33 includes two PMOSs 35 and 36. The drain of the PMOS 35 is connected to a node N8, and its source is connected to a node N15. The node N15 is connected to a signal line 28. The back gate of the PMOS 35 is connected to its source. The gate of the PMOS 35 is connected to a node N14. Between the body and drain of the PMOS 35, there is a body diode D35 with the drain side as the anode.

[0089] The drain of PMOS36 is connected to node N14, and its source is connected to node N15. The back gate of PMOS36 is connected to its source. The gate of PMOS36 is connected to node N8. Between the body and drain of PMOS36, there is a body diode D36 with the drain side as the anode.

[0090] The PMOS driver 33 configured as described above generates a drive signal SLSAn for driving the gates of PMOS 15, 16, 41, 42, 53, 54 and a drive signal SLSBn for driving the gates of PMOS 21, 22, 45, 46, 49, 50, using the potential of the selection signal Vmax output from the selector 13 as a reference potential. The drive signal SLSAn has the same logic as the control signal SLSA0n, and is supplied from a node N8 to the gates of PMOS 15, 16, 41, 42, 53, 54 of the switches S1, SL1, SL6. The drive signal SLSBn has the same logic as the control signal SLSB0n, and is supplied from a node N14 to the gates of PMOS 21, 22, 45, 46, 49, 50 of the switches S4, SL3, SL4.

[0091] The NMOS driver 34 includes two NMOSs 37 and 38. The drain of the NMOS 37 is connected to a node N10, and its source is connected to a node N16. The node N16 is connected to a signal line 31. The back gate of the NMOS 37 is connected to its source. The gate of the NMOS 37 is connected to a node N12. Between the body and drain of the NMOS 37, there is a body diode D37 with the body side serving as the anode.

[0092] The drain of the NMOS 38 is connected to the node N12, and the source is connected to the node N16. The back gate of the NMOS 38 is connected to the source. The gate of the NMOS 38 is connected to the node N10. Between the body and drain of the NMOS 38, there is a body diode D38 with the body side as the anode.

[0093] The NMOS driver 34 configured as described above generates a drive signal SLSBp for driving the gates of NMOSs 17, 18, 47, 48, 51, and 52 and a drive signal SLSAp for driving the gates of NMOSs 19, 20, 43, 44, 55, and 56, using the potential of the selection signal Vmin output from the selector 13 as a reference potential. The drive signal SLSBp has the same logic as the control signal SLSB0p, and is supplied from a node N10 to the gates of NMOSs 17, 18, 47, 48, 51, and 52 of the switches S2, SL3, and SL5. The drive signal SLSAp has the same logic as the control signal SLSA0p, and is supplied from a node N12 to the gates of NMOSs 19, 20, 43, 44, 55, and 56 of the switches S3, SL2, and SL6.

[0094] Next, the operation of the above configuration will be described with reference to FIGS. The capacitive couple driver 14 controls the switches S1, S3, SL1, SL2, SL6 and the switches S2, S4, SL3, SL4, SL5 to be turned on and off complementarily. In this specification, "turning on and off complementarily" does not exclude a case where a period during which both switches are off, that is, a so-called dead time, is provided. Hereinafter, a period during which the switches S1, S3, SL1, SL2, SL6 are turned on and the switches S2, S4, SL3, SL4, SL5 are turned off may be referred to as a sample period, and a period during which the switches S1, S3, SL1, SL2, SL6 are turned off and the switches S2, S4, SL3, SL4, SL5 are turned on may be referred to as a hold period.

[0095] In the SC amplifier 2 configured as above, during the sample period, the capacitors Cs1 and Cs2 are charged by the voltages VINP and VINM of the input nodes Nip and Nim, that is, the voltages VINP and VINM of the input nodes Nip and Nim are sampled by the capacitors Cs1 and Cs2. Also, in the SC amplifier 2 configured as above, during the hold period, the charges stored in the capacitors Cs1 and Cs2 are transferred to the subsequent circuit. Also, in the SC amplifier 2 configured as above, the leakage current is cancelled by passing a compensation current during both the hold period and the sample period due to the operation of the leakage cancellation circuit 10.

[0096] In the following, assuming such an operation, the potential state of each part at the time of positive voltage input where a positive voltage is input via the input nodes Nip and Nim and at the time of negative voltage input where a negative voltage is input via the input nodes Nip and Nim will be described. Note that here, it is assumed that the voltage VINP is +5V and the voltage VINM is 0V at the time of positive voltage input, and that the voltage VINP is -3V and the voltage VINM is 0V at the time of negative voltage input. In Figs. 4 to 6, the on / off state of each MOS transistor is indicated by the presence or absence of hatching. Specifically, in Figs. 4 to 6, only the MOS transistors that are turned on are hatched.

[0097] [1] Potential state of each part when positive voltage is input 4 and 5, when a positive voltage is input, in the selector 13, PMOS 26 and NMOS 30 are turned on, and PMOS 27 and NMOS 29 are turned off. As a result, when a positive voltage is input, the potential of the selection signal Vmax becomes 5 V, and the potential of the selection signal Vmin becomes 0 V. As shown in Fig. 4 and 6, during the sample period, the control signals SLSA0n and SLSB0p become 0 V, and the control signals SLSB0n and SLSA0p become 5 V.

[0098] 4, during the sample period when a positive voltage is input, PMOS 36 and NMOS 37 are turned on and PMOS 35 and NMOS 38 are turned off in the drivers 33 and 34. As a result, during the sample period when a positive voltage is input, the drive signal SLSAn becomes 1V, the drive signal SLSBn becomes 5V, the drive signal SLSAp becomes 4V, and the drive signal SLSBp becomes 0V.

[0099] Therefore, during the sample period when a positive voltage is input, PMOSs 15 and 16 of switch S1, NMOSs 19 and 20 of switch S3, PMOSs 41 and 42 of switch SL1, NMOSs 43 and 44 of switch SL2, and MOS transistors 53 to 56 of switch SL6 are turned on, while NMOSs 17 and 18 of switch S2, PMOSs 21 and 22 of switch S4, MOS transistors 45 to 48 of switch SL3, PMOSs 49 and 50 of switch SL4, and NMOSs 51 and 52 of switch SL5 are turned off.

[0100] 5, during the hold period, the control signals SLSA0n and SLSB0p are 5V, and the control signals SLSB0n and SLSA0p are 0V. Therefore, as shown in FIG 5, during the hold period when a positive voltage is input, in the drivers 33 and 34, PMOS 35 and NMOS 38 are turned on, and PMOS 36 and NMOS 37 are turned off. As a result, during the hold period when a positive voltage is input, the drive signal SLSAn is 5V, the drive signal SLSBn is 1V, the drive signal SLSAp is 0V, and the drive signal SLSBp is 4V.

[0101] Therefore, during the hold period when a positive voltage is input, PMOSs 15 and 16 of switch S1, NMOSs 19 and 20 of switch S3, PMOSs 41 and 42 of switch SL1, NMOSs 43 and 44 of switch SL2, and MOS transistors 53 to 56 of switch SL6 are turned off, while NMOSs 17 and 18 of switch S2, PMOSs 21 and 22 of switch S4, MOS transistors 45 to 48 of switch SL3, PMOSs 49 and 50 of switch SL4, and NMOSs 51 and 52 of switch SL5 are turned on.

[0102] As described above, according to the configuration of this embodiment, when a positive voltage is input, the potential states of the switches S1 to S4 and the switches SL1 to SL6 can be set to the same potential state as in the configuration without the selector 13. Furthermore, according to the configuration of this embodiment, since depletion MOS transistors are used as the PMOS 26 and NMOS 30 that should be turned on when a positive voltage is input in the selector 13, these PMOS 26 and NMOS 30 can be reliably turned on even when the input voltage VINP is near 0V, and as a result, the potential of the MOS transistors constituting the off switches does not become unstable, and high accuracy of the output can be achieved. Note that when the input voltage VINP is near 0V, it refers to a case where the input voltage VINP is equal to or lower than the threshold voltage Vt of the MOS transistor, for example, 0.7V or less.

[0103] [2] Potential state of each part when negative voltage is input 6, when a negative voltage is input, in the selector 13, PMOS 27 and NMOS 29 are turned on, and PMOS 26 and NMOS 30 are turned off. As a result, when a negative voltage is input, the potential of the selection signal Vmax becomes 0V, and the potential of the selection signal Vmin becomes -3V. Therefore, in the sample period when a negative voltage is input, in the drivers 33 and 34, PMOS 36 and NMOS 37 are turned on, and PMOS 35 and NMOS 38 are turned off. As a result, during the sample period when a negative voltage is input, the drive signal SLSAn becomes -4V, the drive signal SLSBn becomes 0V, the drive signal SLSAp becomes 1V, and the drive signal SLSBp becomes -3V.

[0104] Therefore, during the sample period when a negative voltage is input, PMOS 15, 16 of switch S1, NMOS 19, 20 of switch S3, PMOS 41, 42 of switch SL1, NMOS 43, 44 of switch SL2, and MOS transistors 53-56 of switch SL6 are turned on, while NMOS 17, 18 of switch S2, PMOS 21, 22 of switch S4, MOS transistors 45-48 of switch SL3, PMOS 49, 50 of switch SL4, and NMOS 51, 52 of switch SL5 are turned off. The potential state during the hold period when a negative voltage is input is a differential target with respect to the sample period when a negative voltage is input, so a description thereof will be omitted.

[0105] As described above, according to the configuration of this embodiment, when a negative voltage is input, the voltage VINP, which is the lower potential of the voltages VINP and VINM, is applied to the gate of the NMOS that constitutes the switch that should be turned off among the switches S1 to S4 and SL1 to SL6, and the voltage VINM, which is the higher potential of the voltages VINP and VINM, is applied to the gate of the PMOS that constitutes the switch that should be turned off, thereby reliably turning off those switches.

[0106] Furthermore, according to the configuration of this embodiment, when a negative voltage is input, a drive signal whose potential is changed to be higher by a level equivalent to the amplitude of the control signal relative to voltage VINP is applied to the gate of an NMOS constituting a switch that should be turned on among switches S1 to S4 and SL1 to SL6, and a drive signal whose potential is changed to be lower by a level equivalent to the amplitude of the control signal is applied to the gate of a PMOS constituting a switch that should be turned on, thereby reliably turning on those switches.

[0107] According to the present embodiment described above, the following effects can be obtained. According to the configuration of this embodiment, in each of the switches S1 to S4 for transmitting the input signals, voltages VINP and VINM, to the subsequent stage and the switches SL1 to SL6 of the leakage cancellation circuit 10, the body diodes of the two MOS transistors face each other. Therefore, according to the above configuration, no current flows through the body diode, and no error occurs. In particular, since no backflow occurs through the body diode when a negative voltage is input, the occurrence of an error associated with this can be suppressed.

[0108] Furthermore, according to the configuration of this embodiment, when a positive voltage is input, the selector 13 does not become unstable and no leak current occurs, so that the potential states of the multiple switches S1 to S4 and SL1 to SL6 can be made equivalent to those in a configuration without the selector 13. Therefore, according to the configuration of this embodiment, the input range and detection accuracy of the positive voltage can be made equivalent to those in a configuration without the selector 13.

[0109] Furthermore, according to the configuration of this embodiment, similarly to the conventional technology, a negative voltage can be detected by the operation of the selector 13. Thus, according to the configuration of this embodiment, it is possible to detect a negative voltage while maintaining the input range and detection accuracy of a positive voltage at the same level as in a configuration without the selector 13. Therefore, according to this embodiment, it is possible to obtain the excellent effect of being able to accurately detect a wide range of voltages while suppressing the occurrence of leakage current.

[0110] The effect obtained by this embodiment becomes clearer when compared with the conventional technology. Therefore, the effect obtained by this embodiment will be described in detail below with reference to FIG. 7, comparing this embodiment with a comparative example corresponding to the conventional technology. In FIG. 7, the arrows indicating the range corresponding to the comparative example are indicated by dotted lines, and the arrows indicating the range corresponding to this embodiment are indicated by solid lines. In FIG. 7, Vf is the forward voltage of the diode, and Vcc is the drive voltage in the drive units 33 and 34.

[0111] 7, assuming a sample period when a negative voltage is input, the gate voltage range of the NMOSs 19, 20, etc. of the switch S3 that are turned on at that time, i.e., the voltage range of the drive signal SLSAp, is shown as the ON SW gate voltage range, and the gate voltage range of the NMOSs 17, 18, etc. of the switch S2 that are turned off at that time, i.e., the voltage range of the drive signal SLSBp, is shown as the OFF SW gate voltage range. Note that the negative voltage input in this case is assumed to be when the voltage VINP is in the range of "-Vt to 0V" and the voltage VINM is 0V.

[0112] As shown in Fig. 7, the positive side operating range of the voltage detection circuit 1 of this embodiment is the same as that of the comparative example, and the differential voltage between the input nodes Nip and Nim is in the range of about +5.0V. In this specification, the differential voltage between the input nodes Nip and Nim may be simply referred to as the differential voltage. The negative side operating range of the voltage detection circuit 1 is the same as that of the comparative example, and the differential voltage is in the range of about -3.0V. In other words, the differential input operating range of the voltage detection circuit 1 of this embodiment is in the range of -3.0V to +5.0V.

[0113] However, in this embodiment, depletion MOS transistors are used for PMOS 26, one of two PMOSs 26 and 27 constituting maximum selector 23, and NMOS 30, one of two NMOSs 29 and 30 constituting minimum selector 24, so the operating range of selector 13 is wider than that of the comparative example. That is, in the comparative example, the operating range of the positive side of the selector is a range equal to or higher than +Vtn, which is, for example, about 0.7 V. However, Vtn is the threshold value of a normal MOS transistor.

[0114] Therefore, in the comparative example, the Vmin indefinite range in which the selection signal Vmin output from the minimum selector is indefinite is the range from -Vtn to +Vtn, that is, the range from -0.7V to +0.7V. As a result, in the comparative example, in the range from -0.7V to +0.7V, the gate voltage of the NMOS of the switch to be turned off becomes higher than the input voltage, causing leakage and reducing accuracy. In contrast, in this embodiment, the operating range on the positive side of the selector 13 is a range equal to or higher than +Vtd, which is, for example, 0V. Here, Vtd is the threshold value of the depletion MOS transistor.

[0115] Therefore, in this embodiment, the Vmin indefinite range is the range from -Vtn to +Vtd, that is, the range from -0.7 V to 0 V. As a result, in this embodiment, in the range from -0.7 V to 0 V, the gate voltage of the NMOS of the switch to be turned off becomes higher than the input voltage, so there is a risk of leakage occurring, but in the range of 0 V or higher, that is, when a positive voltage is input, it is possible to prevent leakage from occurring.

[0116] Thus, according to this embodiment, when the differential voltage is approximately 0V or more, the selector 13 always operates, and it is possible to reduce the deterioration in accuracy due to leakage of the MOS transistor constituting the selector 13, as compared to the comparative example. In addition, in both the comparative example and this embodiment, the signal transmission range of the NMOS is in the range of approximately 0V to +3.0V. In the comparative example, since the NMOS exists in the path through which the voltage VINP passes, although the voltage VINP is expected to be approximately +5.0V at most, it can only pass up to approximately +3.0V, narrowing the input range of positive voltages.

[0117] In contrast, in this embodiment, since only PMOS exists in the path through which the voltage VINP passes, the input range of positive voltages can be expanded compared to the comparative example. Also, in this embodiment, since the NMOS only exists in the path through which the voltage VINM passes and it is sufficient to pass 0V, there is no risk of the input range being narrowed due to the signal transmission range of the NMOS. Although a detailed explanation is omitted, according to this embodiment, the input range is also expanded on the PMOS side compared to the comparative example by the opposite operation to that on the NMOS side.

[0118] Each of the switches S1 to S4 and SL1 to SL6 includes a series circuit in which two MOS transistors are connected in series, and the back gates of the MOS transistors are connected to the source or drain terminal that is not connected to the intermediate node that is the interconnection node of the two MOS transistors. In this way, the body diodes of the two MOS transistors in the switches S1 to S4 and SL1 to SL6 face each other.

[0119] Therefore, with this configuration, no current flows through the body diode, and no error occurs. In particular, when the negative voltage is large, no backflow occurs through the body diode, and the associated error can be suppressed. Specifically, the configuration of this embodiment has the following advantage over the comparative example. That is, in the comparative example, when a negative voltage exceeding twice the Vf of the body diode is input, that is, when the differential voltage exceeds "-Vf x 2", the body diode of the switch that should be turned off turns on, causing a current to flow and resulting in a large error.

[0120] That is, in the comparative example, the body diode operating range, which is the range in which the body diode of the switch that should be turned off turns on, is a range below "-Vf x 2." In contrast, in the configuration in which the body diodes are opposed to each other as in this embodiment, the body diode of the switch that should be turned off does not turn on until a negative voltage exceeding the voltage obtained by adding the breakdown voltage BV to the Vf of the body diode is input, that is, until the differential voltage exceeds "-(Vf + BV)."

[0121] That is, in the configuration of this embodiment, the body diode operating range is a range below "-(Vf+BV)", specifically, a range below "-8.7 V (=0.7 V+8.0 V)". Therefore, according to the configuration of this embodiment, in the differential input operating range, that is, in the range where the differential voltage is from -3.0 V to +5.0 V, the problem of errors occurring due to backflow through the body diode does not occur.

[0122] Also, according to the above configuration, the body potential of each MOS transistor constituting the switches S1 to S4 for transmitting the input signals, voltages VINP and VINM, to the subsequent stage can be fixed by the input signal voltages VINP and VINM, which is an advantage in that the EMC tolerance is increased. Furthermore, according to the configuration of this embodiment, the body potential of each MOS transistor constituting the switches S1 to S4 can be fixed, which provides the following advantages.

[0123] That is, when the body potential of each MOS transistor constituting the switches S1 to S4 becomes unstable, the input terminal, the body potential, and the output terminal of the switch that is off may be coupled, and the CMRR may deteriorate. However, according to the configuration of this embodiment, such a problem does not occur, and the CMRR can be maintained at a good level. Note that CMRR is an abbreviation for Common Mode Rejection Ratio. Also, when the body potential of each MOS transistor constituting the switches S1 to S4 becomes unstable, the body potential is made the same potential as the signal after the switch is turned on, and therefore it is necessary to wait for settling for that time, and there is a risk of slowing down. However, according to the configuration of this embodiment, such a problem does not occur, and high speed can be achieved.

[0124] In this embodiment, the capacitive couple driving section 14 drives the gates of the MOS transistors 15-22 and 41-56 via the driving capacitances Cdr1-Cdr4, which are comb-tooth capacitances, to control the on / off of the switches S1-S4 and SL1-SL6. That is, in this embodiment, the switches S1-S4 and SL1-SL6 are driven by capacitive coupling. In addition, in this embodiment, the driving capacitances Cdr1-Cdr4 are configured by comb-tooth capacitances.

[0125] This configuration provides the following effects. That is, the above configuration allows the circuit to be made smaller than when the drive capacitances Cdr1 to Cdr4 are configured with parallel plate capacitances, and also allows the parasitic capacitance with other circuits inside the chip to be reduced, thereby reducing interference. Furthermore, in a capacitive coupled drive configuration, noise is emitted in the sample / hold cycle, but by configuring the drive capacitances Cdr1 to Cdr4 with comb capacitances, the drive speed can be increased.

[0126] Normally, in a capacitively coupled drive configuration, in order to avoid noise interference, it is necessary to secure space between the other circuits inside the chip or to place a guard ring, which inevitably results in a large chip area. In contrast, with the above configuration, when high-speed drive is not desired, other circuits can be placed adjacent to the chip, which results in a reduction in the overall chip area while achieving the desired drive speed.

[0127] The voltage detection circuit 1 including the SC amplifier 2 of this embodiment constitutes a part of the battery monitoring IC 5, and more specifically, can be used as a level shift circuit in the battery monitoring IC 5. With this configuration, it is possible to transmit only the differential voltage through the capacitors Cs1 and Cs2, which are sampling capacitances, and therefore it is possible to shift the level of the common mode potential. Furthermore, with the above configuration, it is possible to detect signals in a wider range than the power supply voltage or ground potential, both positive and negative.

[0128] Furthermore, by applying the voltage detection circuit 1 to the battery monitoring IC 5, not only can one IC detect the voltages of multiple battery cells, but also the voltage of a fuel cell in which the voltage of the battery cell is a negative voltage. According to the configuration of this embodiment, as described above, the input range and detection accuracy of the positive voltage can be made the same as in the configuration without the selector 13, so that the same battery monitoring IC 5 can be used as both a normal battery monitoring IC that monitors lithium-ion batteries and a battery monitoring IC for FCs that monitors fuel cells. In addition, in products such as the battery monitoring IC 5, a negative voltage may be applied to the IC when the IC fails. However, by applying the voltage detection circuit 1 of this embodiment, a signal can be transmitted without error even when a negative voltage is applied, so that the failure can be detected.

[0129] In this case, since the voltage detection circuit 1 includes the leak cancellation circuit 10, the following effect can be obtained. That is, the battery monitoring IC 5 has anti-aliasing filters 6a, 6b disposed between the battery cells 4a, 4b to be detected and the AFE included in the battery monitoring IC 5, resulting in a high output impedance. According to the voltage detection circuit 1 of this embodiment, even when applied to such a configuration with high output impedance, the action of the leak cancellation circuit 10 makes it possible to increase the input impedance of the AFE, and the voltage of the battery cells 4a, 4b can be detected with high accuracy.

[0130] The switches SL3 and SL6 of the leak cancel circuit 10 are configured by connecting in parallel series circuits SCL3a and SCL6a, each of which is configured with two PMOS transistors connected in series, and series circuits SCL3b and SCL6b, each of which is configured with two NMOS transistors connected in series. With this configuration, the switches SL3 and SL6 can transmit an intermediate potential, and the operation of leak cancel can be made faster than when the switches are configured with a single series circuit.

[0131] <Modifications regarding selectors> The configuration of this embodiment can be modified so that low-threshold MOS transistors other than depletion MOS transistors are used as the PMOS 26 of the maximum selector 23 and the NMOS 30 of the minimum selector 24. According to such a modification, the selector 13 always operates when the differential voltage is equal to or higher than a voltage corresponding to a threshold lower than a normal threshold, and the decrease in accuracy due to leakage of the MOS transistors constituting the selector 13 can be reduced compared to the comparative example.

[0132] Regarding the configuration of this embodiment, a low-threshold MOS transistor including a depletion MOS transistor is used as the PMOS 27 included in the maximum selector 23 and the NMOS 29 included in the minimum selector 24, and it can be modified to use a normal MOS transistor as the PMOS 26 included in the maximum selector 23 and the NMOS 30 included in the minimum selector 24.

[0133] According to such a modification example, although the positive operating range of the selector 13 becomes equivalent to that of the comparative example, the negative operating range of the selector 13 becomes a range of +Vtd or less, for example, 0V. Therefore, in the modification example, the Vmin indeterminate range becomes a range from +Vtd to +Vtn, that is, a range from 0V to +0.7V. As a result, in the modification example, although there is a possibility of leakage because the gate voltage of the NMOS of the switch to be turned off becomes higher than the input voltage in the range from 0V to +0.7V, it is possible to prevent the occurrence of leakage in the range of 0V or less, that is, when a negative voltage is input. Thus, according to the modification example, the selector 13 always operates when the differential voltage is approximately 0V or less, and it is possible to reduce the accuracy degradation due to the leakage of the MOS transistors constituting the selector 13 compared to the comparative example.

[0134] <Another application example of the SC amplifier> The SC amplifier 2 having the above configuration can be used as an integrator in a ΔΣ type ADC. The ΔΣ type ADC includes a ΔΣ modulator 61 as shown in FIG. 8, and is an ADC that obtains a high-resolution digital output by passing the output of the ΔΣ modulator 61 through a digital filter (not shown). The ΔΣ modulator 61 employs a type of pulse modulation method and includes an adder 62, an integrator 63, a comparator 64, and a DAC 65.

[0135] The adder 62 outputs a signal obtained by subtracting the output signal of the DAC 65 ​​from the input signal Input. The integrator 63 integrates the output signal of the adder 62, and can be constituted by the SC amplifier 2. The comparator 64 binarizes the output signal of the integrator 63. The DAC 65 ​​receives the output signal of the comparator 64 and outputs a signal according to the input. The ΔΣ modulator 61 thus configured integrates the input signal Input by the integrator 63, digitally converts the output by the comparator 64, and adds or subtracts from the input signal Input using the DAC 65 ​​according to the output, thereby making it possible to extract the output of the comparator 64 as the ΔΣ modulated output Output.

[0136] According to the above configuration, the above-mentioned operation shapes the power spectrum density distribution of the quantization error output by the comparator 64, that is, performs noise shaping, and improves the dynamic range of the passband. This configuration enables the ADC to shift the level of the common mode potential by itself, and makes it possible to detect signals in a wider range than the power supply voltage or ground potential, both positive and negative. Furthermore, according to the above configuration, the size can be reduced compared to a configuration in which a separate level shifter is provided in front of the ADC.

[0137] Second embodiment The second embodiment will be described below with reference to FIGS. <Overall composition> 9, an SC amplifier 72 included in a voltage detection circuit 71 of this embodiment differs from the SC amplifier 2 of the first embodiment in that it includes a switch S71 instead of the switches S2 and S4. The switch S71 is connected between the second terminal of the capacitor Cs1 and the second terminal of the capacitor Cs2.

[0138] <Specific configuration of switch circuit> In the above configuration, a plurality of switches S1, S3, and S71 connected between a pair of input nodes Nip, Nim and capacitors Cs1, Cs2 constitute a switch circuit 73, which is a CCSW circuit, together with a selector 13 and a capacitive couple driving unit 14, as shown in Fig. 9. Note that Fig. 9 shows a simplified configuration of the selector 13 and the capacitive couple driving unit 14. The switch circuit 73 including the switches S1, S3, and S71 constitutes a part of the SC amplifier 72, and a specific configuration thereof may be, for example, as shown in Fig. 10. Note that the leak cancel circuit is not shown in Fig. 10.

[0139] The switch S71 is configured by connecting in parallel a series circuit 76 in which two PMOSs 74 and 75 are connected in series, and a series circuit 79 in which two NMOSs 77 and 78 are connected in series. The source of the PMOS 74 is connected to the node Np, and its drain is connected to the node N71. The drain of the PMOS 75 is connected to the node N71, and its source is connected to the node Nm. The node N71 is an example of an intermediate node that is an interconnection node between the two PMOSs 74 and 75.

[0140] The back gate of PMOS74 is connected to its source. The back gate of PMOS75 is connected to its source. That is, the back gates of PMOS74 and 75 are connected to the terminal of their source or drain that is not connected to the intermediate node, node N71. Between the body and drain of PMOS74, there is a body diode D74 with the drain side as the anode. Between the body and drain of PMOS75, there is a body diode D75 with the drain side as the anode.

[0141] That is, in the switch S71, the body diodes D74 and D75 face each other. The gates of the PMOSs 74 and 75 are connected to the capacitive couple driver 14, and are turned on and off by the capacitive couple driver 14. Specifically, the PMOSs 74 and 75 are turned on and off by a drive signal SLSBn.

[0142] The source of NMOS 77 is connected to node Np, and its drain is connected to node N72. The drain of NMOS 78 is connected to node N72, and its source is connected to node Nm. Node N72 is an example of an intermediate node that is an interconnection node between two NMOSs 77 and 78. The backgate of NMOS 77 is connected to its source. The backgate of NMOS 78 is connected to its source. That is, the backgates of NMOSs 77 and 78 are connected to the terminal of their source or drain that is not connected to node N72, which is the intermediate node.

[0143] Between the body and drain of NMOS77, there is a body diode D77 with the body side as the anode. Between the body and drain of NMOS78, there is a body diode D78 with the body side as the anode. That is, in the switch S71, the body diodes D77 and D78 face each other. The gates of NMOS77 and 78 are connected to the capacitive couple driver 14, and the on / off of these diodes is controlled by the capacitive couple driver 14. Specifically, the on / off of NMOS77 and 78 is controlled by the drive signal SLSBp.

[0144] The present embodiment described above also provides the same effects as the first embodiment. The switch S71 is configured by connecting in parallel a series circuit 76 of two PMOS transistors 74 and 75 and a series circuit 79 of two NMOS transistors 77 and 78, and the back gates of these MOS transistors are connected to the terminal of the source or drain that is not connected to the intermediate node that is the interconnection node of the two MOS transistors. In this way, the body diodes of the two MOS transistors in the switch S71 face each other, as in the switches S1 and S3. Therefore, as in the first embodiment, the configuration of this embodiment also prevents current from flowing through the body diodes, and no errors occur.

[0145] Furthermore, according to this embodiment, the following effects can be obtained. In the configuration of this embodiment, the number of switches is one less than in the configuration of the first embodiment, so that a correspondingly smaller size can be achieved. Also, according to the configuration of this embodiment, the operational amplifier 3 and the like are not connected to the input during hold but are in a disconnected state, so that the CMRR can be improved.

[0146] Furthermore, according to the configuration of this embodiment, the operational amplifier 3 and other components are not connected to the input during hold and are therefore in a disconnected state, so that the signal in the previous stage can be switched immediately after sampling is completed. Therefore, according to this embodiment, in a configuration in which a multiplexer is provided in the previous stage, such as the battery monitoring IC 5 shown in FIG. 2, the speed of the entire system can be increased.

[0147] Third embodiment The third embodiment will be described below with reference to FIG. As shown in Fig. 11, the switch circuit 81 of this embodiment differs from the switch circuit 12 of the first embodiment in the configuration of the switches S1 to S4. Note that the leak cancellation circuit is not shown in Fig. 11. In this case, like the switch circuit 12 of the first embodiment, the switches S1 to S4 include a series circuit in which two MOS transistors are connected in series, but the connection forms of the MOS transistors included in these series circuits are different.

[0148] That is, the switch S1 includes a series circuit SC81 in which two PMOSs 15 and 16 are connected in series. The drain of the PMOS 15 is connected to the input node Nip, and its source is connected to the node N1. The source of the PMOS 16 is connected to the node N1, and its drain is connected to the node Np. In this case, the back gates of the PMOSs 15 and 16 are connected to the terminal of the source or drain that is connected to the node N1, which is the intermediate node. According to the above configuration, the body diodes D15 and D16 face each other in the switch S1, as in the first embodiment, although the opposing directions are reversed.

[0149] The switch S2 includes a series circuit SC82 in which two NMOSs 17 and 18 are connected in series. The drain of the NMOS 17 is connected to the input node Nim, and its source is connected to the node N2. The source of the NMOS 18 is connected to the node N2, and its drain is connected to the node Np. In this case, the back gates of the NMOSs 17 and 18 are connected to the terminal of the source or drain that is connected to the node N2, which is the intermediate node. According to the above configuration, the body diodes D17 and D18 face each other in the switch S2, as in the first embodiment, although the opposing directions are reversed.

[0150] The switch S3 includes a series circuit SC83 in which two NMOSs 19 and 20 are connected in series. The drain of the NMOS 19 is connected to the input node Nim, and its source is connected to the node N3. The source of the NMOS 20 is connected to the node N3, and its drain is connected to the node Nm. In this case, the back gates of the NMOSs 19 and 20 are connected to the terminal of the source or drain that is connected to the node N3, which is the intermediate node. According to the above configuration, the body diodes D19 and D20 face each other in the switch S3, as in the first embodiment, although the opposing directions are reversed.

[0151] The switch S4 includes a series circuit SC84 in which two PMOSs 21 and 22 are connected in series. The drain of the PMOS 21 is connected to the input node Nip, and its source is connected to the node N4. The source of the PMOS 22 is connected to the node N4, and its drain is connected to the node Nm. In this case, the back gates of the PMOSs 21 and 22 are connected to the terminal connected to the node N4, which is the intermediate node, among the terminals of the source or drain. According to the above configuration, the body diodes D21 and D22 face each other in the switch S4, as in the first embodiment, although the opposing directions are reversed.

[0152] The present embodiment described above also provides the same effects as those of the first embodiment. Furthermore, the present embodiment also provides the following effects. That is, the body potentials of the two MOS transistors constituting each of the series circuits SC81 to SC84 are the same, so that they can be arranged in the same trench, and as a result, the circuit can be made smaller.

[0153] (Other embodiments) The present invention is not limited to the embodiments described above and shown in the drawings, and can be modified, combined, or expanded as desired without departing from the spirit and scope of the present invention. The numerical values ​​and the like shown in the above embodiments are merely examples and are not intended to be limiting.

[0154] The selector 13 need only select one of the voltages VINP, VINM of a pair of input nodes Nip, Nim and output a selection signal having a potential corresponding to the selected voltage, and may be configured to include, for example, only one of the maximum selector 23 and the minimum selector 24.

[0155] The driving units 33 and 34 need only generate driving signals for driving the gates of the MOS transistors 15 to 22, etc. using the potential of the selection signal output from the selector 13 as a reference potential, and supply the generated driving signals to the gates of the MOS transistors 15 to 22, etc., and the specific configuration thereof can be modified as appropriate.

[0156] The leak cancel circuit 10 may be provided as necessary. For example, if the input impedance is low, it is possible to omit the leak cancel circuit 10, which allows the voltage detection circuit 1 and other circuits to be implemented in a smaller size.

[0157] Although the present disclosure has been described based on the embodiment, it is understood that the present disclosure is not limited to the embodiment or structure. The present disclosure also includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, and other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure.

[0158] In addition to the inventions described in the claims, the present disclosure includes the following inventions. [1] A fully differential voltage detection circuit that receives voltages at a pair of input nodes (Nip, Nim), detects a differential voltage between the input nodes, and outputs the differential voltage from a pair of output nodes (Nop, Nom), a plurality of switches (S1 to S4, S71) provided between the pair of input nodes and the pair of output nodes, each including a series circuit (SC1 to SC4, 76, 79) in which two MOS transistors (15 to 22, 74 to 78) are connected in series; a capacitance couple driver (14) including driving capacitances (Cdr1 to Cdr4) and controlling on / off of each of the plurality of switches by driving gates of the MOS transistors included in the plurality of switches via the driving capacitances; Equipped with A voltage detection circuit connects the back gate of the MOS transistor to the source or drain terminal that is not connected to the intermediate node (N1 to N4, N71, N72) which is the interconnection node between the two MOS transistors. [2] The high potential side of the pair of input nodes is defined as a first input node, the low potential side of the pair of input nodes is defined as a second input node, a switch of the plurality of switches connected to the first input node is defined as a first switch, and a switch of the plurality of switches connected to the second input node is defined as a second switch. The two MOS transistors included in the first switch are both P-channel MOS transistors (15, 16, 21, 22), The voltage detection circuit according to [1], wherein the two MOS transistors included in the second switch are both N-channel MOS transistors (17, 18, 19, 20). [3] The input terminal further includes a differential leakage cancel circuit (10) for canceling charges leaking from the pair of input nodes due to the operation of the plurality of switches, The leak cancel circuit includes: a pair of cancellation input nodes (NLi1 to NLi4) for inputting cancellation charges for canceling the leaking charges; a plurality of cancel switches (SL1 to SL6) provided to be capable of opening and closing between the pair of input nodes and the pair of cancel input nodes; Equipped with The plurality of cancel switches include series circuits (SCL1 to SCL6b) each having two MOS transistors (41 to 56) connected in series, The voltage detection circuit according to [1] or [2], wherein the back gate of the MOS transistor is connected to one of its source or drain terminals that is not connected to an intermediate node (NL1 to NL6) that is an interconnection node between the two MOS transistors. [4] The high potential side of the pair of input nodes is defined as a first input node, the low potential side of the pair of input nodes is defined as a second input node, the high potential side of the pair of cancel input nodes is defined as a first cancel input node, the low potential side of the pair of cancel input nodes is defined as a second cancel input node, a cancel switch connected between the first input node and the first cancel input node among the multiple cancel switches is defined as a first cancel switch, and a cancel switch connected between the second input node and the second cancel input node among the multiple cancel switches is defined as a second cancel switch, The two MOS transistors included in the first cancellation switch are both P-channel MOS transistors (41, 42, 49, 50), The voltage detection circuit according to [3], wherein the two MOS transistors included in the second cancellation switch are both N-channel MOS transistors (43, 44, 51, 52). [5] When the cancel switch connected between the first cancel input node and the second cancel input node among the plurality of cancel switches is defined as a third cancel switch, The third cancellation switch is configured by connecting two of the series circuits (SCL3a, SCL3b, SCL6a, SCL6b) in parallel, The two MOS transistors in one of the two series circuits are P-channel MOS transistors (45, 46, 53, 54), The voltage detection circuit according to [4], wherein the two MOS transistors included in the other of the two series circuits are all N-channel MOS transistors (47, 48, 55, 56). [6] a selector (13) connected between the pair of input nodes, for selecting one of the voltages of the pair of input nodes and outputting a selection signal having a potential corresponding to the selected voltage; The voltage detection circuit according to [1] or [2], further comprising a drive unit (33, 34) that generates drive signals for driving the gates of the MOS transistors of the plurality of switches using the potential of the selection signal output from the selector as a reference potential, and supplies the generated drive signals to the gates of the MOS transistors of the plurality of switches. [7] a selector (13) connected between the pair of input nodes, for selecting one of the voltages of the pair of input nodes, and for outputting a selection signal having a potential corresponding to the selected voltage; The capacitive couple driver includes: driving gates of the MOS transistors provided in the plurality of cancel switches via the driving capacitance to control on / off of the plurality of cancel switches; The voltage detection circuit according to any one of [3] to [5], further comprising a drive unit (33, 34) that generates drive signals for driving gates of the MOS transistors provided in the plurality of cancellation switches using a potential of the selection signal output from the selector as a reference potential, and supplies the generated drive signals to the gates of the MOS transistors provided in the plurality of cancellation switches. [8] Further, a switched capacitor amplifier (2) is provided, The voltage detection circuit according to any one of [1] to [7], wherein the plurality of switches constitute a part of the switched capacitor amplifier. [9] The pair of input nodes are connectable to terminals of each battery cell constituting the battery pack (4), The voltage detection circuit according to any one of [1] to [8], wherein the plurality of switches form part of a level shift circuit that reduces a relatively high common-mode voltage superimposed on each of the battery cells (4a, 4b) to a relatively low common-mode voltage.

[10] The voltage detection circuit according to any one of [1] to [9], wherein the driving capacitance is a comb capacitance. [Explanation of symbols]

[0159] 1, 71...voltage detection circuit, 2...switched capacitor amplifier, 4...battery pack, 4a, 4b...battery cell, 5...battery monitoring IC, 10...leak cancellation circuit, 13...selector, 14...capacitive couple driver, 15-22, 41-56, 74-78...MOS transistor, 33...PMOS driver, 34...NMOS driver, 74, 75...PMOS, 77, 78...NMOS, Cdr1-Cdr4...drive capacitance, N1-N4, N71, N72, NL1-NL6...node, Nip, Nim...input node, NLi1-NLi4...input node, Nop, Nom...output node, S1-S4, S71...switch, SC1-SC4, SCL1-SCL6b, 76, 79...series circuit, SL1-SL6...switch.

Claims

1. A fully differential voltage detection circuit that receives voltages at a pair of input nodes (Nip, Nim), detects a difference voltage between the input voltages, and outputs the difference voltage from a pair of output nodes (Nop, Nom), a plurality of switches (S1 to S4, S71) provided between the pair of input nodes and the pair of output nodes, the plurality of switches including a series circuit (SC1 to SC4, 76, 79) in which two MOS transistors (15 to 22, 74 to 78) are connected in series; a capacitance couple driver (14) including driving capacitances (Cdr1 to Cdr4) and controlling the on / off of each of the plurality of switches by driving gates of the MOS transistors included in the plurality of switches via the driving capacitances; Equipped with A voltage detection circuit in which the back gate of the MOS transistor is connected to one of its source or drain terminals that is not connected to the intermediate node (N1 to N4, N71, N72), which is the interconnection node of two of the MOS transistors.

2. The high potential side of the pair of input nodes is defined as a first input node, the low potential side of the pair of input nodes is defined as a second input node, a switch of the plurality of switches connected to the first input node is defined as a first switch, and a switch of the plurality of switches connected to the second input node is defined as a second switch, The two MOS transistors included in the first switch are both P-channel MOS transistors (15, 16, 21, 22), 2. The voltage detection circuit according to claim 1, wherein the two MOS transistors included in the second switch are both N-channel MOS transistors (17, 18, 19, 20).

3. Further, a differential leakage cancel circuit (10) is provided for canceling charges leaking from the pair of input nodes due to the operation of the plurality of switches, The leak cancel circuit includes: a pair of cancellation input nodes (NLi1 to NLi4) for inputting cancellation charges for canceling the leaking charges; a plurality of cancel switches (SL1 to SL6) provided to be capable of opening and closing between the pair of input nodes and the pair of cancel input nodes; Equipped with The plurality of cancellation switches include series circuits (SCL1 to SCL6b) each having two MOS transistors (41 to 56) connected in series, 2. The voltage detection circuit according to claim 1, wherein the back gate of the MOS transistor is connected to one of its source or drain terminals that is not connected to an intermediate node (NL1 to NL6) that is an interconnection node between the two MOS transistors.

4. The high potential side of the pair of input nodes is defined as a first input node, the low potential side of the pair of input nodes is defined as a second input node, the high potential side of the pair of cancel input nodes is defined as a first cancel input node, the low potential side of the pair of cancel input nodes is defined as a second cancel input node, a cancel switch connected between the first input node and the first cancel input node among the plurality of cancel switches is defined as a first cancel switch, and a cancel switch connected between the second input node and the second cancel input node among the plurality of cancel switches is defined as a second cancel switch, The two MOS transistors included in the first cancellation switch are both P-channel MOS transistors (41, 42, 49, 50), 4. The voltage detection circuit according to claim 3, wherein the two MOS transistors included in the second cancellation switch are both N-channel MOS transistors (43, 44, 51, 52).

5. When the cancel switch connected between the first cancel input node and the second cancel input node among the plurality of cancel switches is designated as a third cancel switch, The third cancellation switch is configured by connecting two of the series circuits (SCL3a, SCL3b, SCL6a, SCL6b) in parallel, The two MOS transistors included in one of the two series circuits are both P-channel MOS transistors (45, 46, 53, 54), 5. The voltage detection circuit according to claim 4, wherein the two MOS transistors included in the other of the two series circuits are both N-channel MOS transistors (47, 48, 55, 56).

6. a selector (13) connected between the pair of input nodes, for selecting one of the voltages of the pair of input nodes and outputting a selection signal having a potential corresponding to the selected voltage; 3. The voltage detection circuit according to claim 1, wherein the capacitive couple driving unit generates a driving signal for driving the gates of the MOS transistors provided in the plurality of switches using the potential of the selection signal output from the selector as a reference potential, and includes a driving unit (33, 34) that supplies the generated driving signal to the gates of the MOS transistors provided in the plurality of switches.

7. a selector (13) connected between the pair of input nodes, selecting one of the voltages of the pair of input nodes, and outputting a selection signal having a potential corresponding to the selected voltage; The capacitive couple driver includes: driving gates of the MOS transistors provided in the plurality of cancel switches via the driving capacitance to control on / off of the plurality of cancel switches; 6. The voltage detection circuit according to claim 3, further comprising a drive unit (33, 34) that generates drive signals for driving gates of the MOS transistors provided in the plurality of cancellation switches using a potential of the selection signal output from the selector as a reference potential, and supplies the generated drive signals to the gates of the MOS transistors provided in the plurality of cancellation switches.

8. Further, a switched capacitor amplifier (2) is provided, 8. The voltage detection circuit according to claim 7, wherein the plurality of switches form a part of the switched capacitor amplifier.

9. The pair of input nodes are connectable to terminals of each battery cell constituting the battery pack (4), 9. The voltage detection circuit according to claim 8, wherein the plurality of switches form part of a level shift circuit that reduces a relatively high common mode voltage superimposed on each of the battery cells (4a, 4b) to a relatively low common mode voltage.

10. 10. The voltage detection circuit according to claim 9, wherein the driving capacitance is a comb capacitance.

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