Semiconductor device

Abstract

To provide a semiconductor device having reduced on-resistance and improved withstand voltage.SOLUTION: A semiconductor device includes a semiconductor layer and trench structure parts. The trench structure parts are located at a gate electrode, a conductive member, and between the gate electrode and the semiconductor layer, between the conductive layer and the semiconductor layer, and between the gate electrode and the conductive member, and each have an insulation member including fixed charge. The insulation member has a first insulation part located between the gate electrode and a second face of the semiconductor layer in a first direction and located between the conductive member and the semiconductor layer in a second direction crossing the first direction. The first insulation part has a first region, a second region, and a third region. In the first direction, the first region is located between the gate electrode and the second region, the second region is located between the first region and the third region, and the third region is located between the second region and the second face. A first total amount of fixed charge in the first region is greater than a second total amount of fixed charge in the second region.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] There has been proposed a semiconductor device that includes a gate electrode and a field plate electrode to which a source potential is applied, both of which are provided within a trench formed in a semiconductor layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2022-185245 [Patent Document 2] International Publication No. 2018 / 078775 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the embodiments of the present invention is to provide a semiconductor device capable of reducing the on-resistance and improving the breakdown voltage. [Means for solving the problem]

[0005] According to an embodiment of the present invention, a semiconductor device includes a semiconductor layer having a first surface and a second surface located opposite to the first surface in a first direction, and a trench structure extending from the first surface in the first direction and located within the semiconductor layer, the trench structure including a gate electrode, a conductive member having a lower end located closer to the second surface in the first direction than the gate electrode, and insulating members including fixed charges located between the gate electrode and the semiconductor layer, between the conductive member and the semiconductor layer, and between the gate electrode and the conductive member, The semiconductor device has a first insulating portion located between the gate electrode and the second surface in one direction and between the conductive member and the semiconductor layer in a second direction intersecting the first direction, the first insulating portion having a first region, a second region, and a third region, in the first direction, the first region is located between the gate electrode and the second region, the second region is located between the first region and the third region, and the third region is located between the second region and the second surface, and a first total amount of the fixed charges in the first region is greater than a second total amount of the fixed charges in the second region. [Brief description of the drawings]

[0006] [Figure 1] FIG. 2A is a schematic cross-sectional view of the semiconductor device of the embodiment, and FIG. 2B is a graph showing the distribution of fixed charge density in a first direction of an insulating member of the semiconductor device of the embodiment. [Diagram 2] 1A is a graph showing Ron-Vdss characteristics, and FIG. 1B is a graph showing the charge density dependency of the withstand voltage. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Each embodiment will be described below with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios of each part may be different depending on the drawing. Identical or similar elements are labeled with the same reference numbers.

[0008] As shown in FIG. 1( a ), the semiconductor device of the embodiment includes a semiconductor layer 10 and a trench structure 50 .

[0009] The semiconductor layer 10 has a first surface 10A and a second surface 10B located on the opposite side of the first surface 10A in a first direction Z. The first direction Z is a direction from the first surface 10A toward the second surface 10B. In FIG. 1(a), a direction intersecting the first direction Z is defined as a second direction X. For example, the second direction X is perpendicular to the first direction Z. Furthermore, a direction intersecting the first direction Z and the second direction X is defined as a third direction Y. For example, the third direction Y is perpendicular to the first direction Z and the second direction X. The first surface 10A and the second surface 10B extend along the second direction X and the third direction Y.

[0010] The semiconductor layer 10 may be made of, for example, silicon. Alternatively, the semiconductor layer 10 may be made of, for example, silicon carbide, gallium nitride, or the like.

[0011] The trench structure 50 extends in a first direction Z from the first surface 10A and is located in the semiconductor layer 10. The trench structure 50 also extends in a third direction Y. For example, a plurality of trench structures 50 are arranged in the semiconductor layer 10 apart from each other in the second direction X. Alternatively, a plurality of columnar trench structures 50 may be arranged in the second direction X and the third direction Y.

[0012] The trench structure 50 includes a gate electrode 30 , a conductive member 60 , and an insulating member 40 .

[0013] The gate electrode 30 has an upper end 30b and a lower end 30a. The position of the upper end 30b in the first direction Z is between the position of the first surface 10A in the first direction Z and the position of the lower end 30a in the first direction Z. The gate electrode 30 can be made of, for example, conductive polycrystalline silicon.

[0014] The conductive member 60 has a lower end 60a at a position closer to the second surface 10B than the gate electrode 30 in the first direction Z. One trench structure 50 has, for example, two gate electrodes 30 located apart from each other in the second direction X. For example, the conductive member 60 is located between the two gate electrodes 30. The conductive member 60 extends in the first direction Z from a portion located between the two gate electrodes 30 toward the second surface 10B side. An example of a material that can be used for the conductive member 60 is polycrystalline silicon having electrical conductivity.

[0015] The conductive member 60 is electrically connected to a first electrode 21, which will be described later. Alternatively, a potential lower than that of a second electrode 22, which will be described later and to which a higher potential than that of the first electrode 21 is applied, may be applied to the conductive member 60. The conductive member 60 can reduce the electric field applied in the first direction Z (hereinafter, may be referred to as a vertical electric field), and can improve the withstand voltage.

[0016] The insulating member 40 is located between the gate electrode 30 and the semiconductor layer 10, between the conductive member 60 and the semiconductor layer 10, and between the gate electrode 30 and the conductive member 60. As a material for the insulating member 40, for example, silicon oxide, BPSG (boro-phospho silicate glass), or the like can be used.

[0017] The insulating member 40 has a first insulating portion 41 located between the lower end 30a of the gate electrode 30 and the second surface 10B in the first direction Z, and located between the conductive member 60 and the semiconductor layer 10 in the second direction X.

[0018] The insulating member 40 further includes a second insulating portion 42, a third insulating portion 43, a fourth insulating portion 44, and a fifth insulating portion 45.

[0019] The second insulating portion 42 is located between the side surface of the gate electrode 30 and the semiconductor layer 10 in the second direction X. The second insulating portion 42 and the first insulating portion 41 are distinguished from each other by the position of the lower end portion 30a of the gate electrode 30 in the first direction Z.

[0020] The third insulating portion 43 is located between a side surface of the gate electrode 30 and a side surface of the conductive member 60 in the second direction X.

[0021] The fourth insulating portion 44 is located between the upper end portion 30b of the gate electrode 30 and the first electrode 21 in the first direction X.

[0022] The fifth insulating portion 45 is located in the first direction X between the lower end portion 60a of the conductive member 60 and the semiconductor layer 10, and between the first insulating portion 41 and the semiconductor layer 10. The fifth insulating portion 45 and the first insulating portion 41 are distinguished from each other by the position of the lower end portion 60a of the conductive member 60 in the first direction Z.

[0023] At least the first insulating portion 41 of the insulating member 40 includes a first element. The first element includes at least one selected from the group consisting of hydrogen, helium, and argon. At least the first insulating portion 41 of the insulating member 40 includes a fixed charge. The first element functions as a fixed charge. In this specification, the first element and the defects occurring in the passing region when the first element is injected are treated as synonymous with the fixed charge. The amount of fixed charge can be interpreted as the sum of the amount of the first element and the amount of defects occurring in the passing region when the first element is injected. An expression relating to the magnitude relationship of the amount of fixed charge can be interpreted as the magnitude relationship of the amount of the first element and the sum of the amount of defects occurring in the passing region when the first element is injected. The fixed charge density can be interpreted as the sum of the concentration of the first element and the density of defects occurring in the passing region when the first element is injected. An expression relating to the magnitude relationship of the fixed charge density can be interpreted as the magnitude relationship of the concentration of the first element and the sum of the density of defects occurring in the passing region when the first element is injected. The first element is accelerated in the first direction Z with energy of, for example, 100 keV or more and is implanted into the insulating member 40 from the first surface 10A side.

[0024] The first insulating portion 41 has a first region 41A, a second region 41B, and a third region 41C. In the first direction Z, the first region 41A is located between the lower end portion 30a of the gate electrode 30 and the second region 41B. In the first direction Z, the second region 41B is located between the first region 41A and the third region 41C. In the first direction Z, the third region 41C is located between the second region 41B and the second surface 10B. The first region 41A and the second region 41B are in contact with each other. The second region 41B and the third region 41C are in contact with each other. The first insulating portion 41 includes a first position P1 that divides a portion between the position of the lower end 30a of the gate electrode 30 in the first direction Z and the position of the lower end 60a of the conductive member 60 in the first direction Z at a ratio of 1:9, a second position P2 that divides the portion at a ratio of 1:1, and a third position P3 that divides the portion at a ratio of 9:1. The first position P1 is included in the first region 41A. The third position P3 is included in the third region 41C.

[0025] The position of the first region 41A on the opposite side to the second region 41B in the first direction Z coincides with the position of the bottom end 30a of the gate electrode 30 in the first direction Z.

[0026] The boundary between the first region 41A and the second region 41B is, for example, located closer to the first surface 10A than the bisector C in the first direction Z of the trench structure 50. The bisector C divides a portion of the trench structure 50 between the position of the lower end 30a of the gate electrode 30 in the first direction Z and the position of the lower end 60a of the conductive member 60 in the first direction Z into two equal parts in the first direction Z.

[0027] The boundary between the second region 41B and the third region 41C is, for example, located closer to the second surface 10B than the bisector C. Alternatively, the boundary between the second region 41B and the third region 41C may coincide with the bisector C.

[0028] The position of the third region 41C on the opposite side in the first direction Z to the second region 41B coincides with the position of the lower end 60a of the conductive member 60 in the first direction Z.

[0029] The position of the lower end 30a of the gate electrode 30 in the first direction Z is, for example, in the range of 0.5 μm or more and 2.0 μm or less away from the first surface 10A.

[0030] The boundary between the first region 41A and the second region 41B is located, for example, at a distance from the first surface 10A in the range of 1.0 μm to 3.0 μm.

[0031] The position of the lower end 60a of the conductive member 60 in the first direction Z is, for example, within a range of 4.5 μm or more and 10.0 μm or less away from the first surface 10A.

[0032] FIG. 1(b) is a graph showing the distribution of fixed charge density in the first direction Z of the insulating member 40 calculated by simulation.

[0033] According to this embodiment, a first total amount of fixed charges in the first region 41A is greater than a second total amount of fixed charges in the second region 41B. A first maximum value of the density distribution of fixed charges along the first direction Z in the first region 41A is greater than a second maximum value of the density distribution of fixed charges along the first direction Z in the second region 41B. The density of fixed charges in the first region 41A is greater than the density of fixed charges in the second region 41B. The density of fixed charges in the first region 41A is, for example, 1×10 15 cm 3 The first region 41A has a fixed charge density of 2×10 15 cm 3 The second region 41B includes a portion having a fixed charge density of 1×10 15 cm 3 The density of the fixed charges (first element concentration) at the first position P1 is greater than the density of the fixed charges (first element concentration) at the second position P2. The density of the fixed charges at the first position P1 is 2×10 15 cm 3 Greater than.

[0034] Due to such fixed charges in the first region 41A, carriers can be accumulated in a region in the semiconductor layer 10 where carriers (electrons in the case of an n-type MOSFET, as described later) are injected from a channel, which will be described later, in the potential distribution of the semiconductor layer 10 when the first electrode 21, the second electrode 22, the gate electrode 30, and the conductive member 60 are at 0 V. This makes it possible to suppress the spread of current in the carrier injection region of the semiconductor layer 10 and reduce the on-resistance.

[0035] Furthermore, the third total amount of fixed charges in the third region 41C is greater than the second total amount of fixed charges in the second region 41B. The third maximum value of the density distribution of fixed charges along the first direction Z in the third region 41C is greater than the second maximum value of the density distribution of fixed charges along the first direction Z in the second region 41B. The third maximum value of the density distribution of fixed charges along the first direction Z in the third region 41C is greater than the first maximum value of the density distribution of fixed charges along the first direction Z in the first region 41A. The density of fixed charges in the third region 41C is greater than the density of fixed charges in the second region 41B. The density of fixed charges in the third region 41C is greater than the density of fixed charges in the fifth insulating portion 45. The density of fixed charges in the third region 41C is, for example, 1×10 15 cm 3 The third region 41A has a fixed charge density of 1×10 15 cm 3 The density of the fixed charges (first element concentration) at the third position P3 is greater than the density of the fixed charges (first element concentration) at the second position P2. The density of the fixed charges at the third position P3 is greater than 1×10 16 cm 3 Greater than.

[0036] Such fixed charges in the third region 41C can reduce the vertical electric field that tends to concentrate at the corners of the bottom end 60a of the conductive member 60, thereby improving the breakdown voltage.

[0037] The semiconductor device of the embodiment further includes a first electrode 21 provided on the first surface 10A and a second electrode 22 provided on the second surface 10B. The semiconductor layer 10 has an n-type first semiconductor portion 11, a p-type second semiconductor portion 12, and an n-type third semiconductor portion 13. The n-type impurity concentration of the third semiconductor portion 13 is higher than the n-type impurity concentration of the first semiconductor portion 11.

[0038] The first semiconductor portion 11 is provided on the second electrode 22 , the second semiconductor portion 12 is provided on the first semiconductor portion 11 , and the third semiconductor portion 13 is provided on the second semiconductor portion 12 .

[0039] The first electrode 21 is in contact with the third semiconductor portion 13 and is electrically connected to the third semiconductor portion 13. The first semiconductor portion 11 is adjacent to the first insulating portion 41 in the second direction X. The second semiconductor portion 12 faces a side surface of the gate electrode 30 in the second direction X via the second insulating portion 42. The second semiconductor portion 12 is in contact with the first electrode 21 and is electrically connected to the first electrode 21.

[0040] The semiconductor layer 10 may further include an n-type fourth semiconductor portion 14 provided between the second electrode 22 and the first semiconductor portion 11. The n-type impurity concentration of the fourth semiconductor portion 14 is higher than the n-type impurity concentration of the first semiconductor portion 11. The fourth semiconductor portion 14 is electrically connected to the second electrode 22.

[0041] The semiconductor device according to the embodiment has, for example, a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure. For example, the first electrode 21 functions as a source electrode, the second electrode 22 functions as a drain electrode, the first semiconductor portion 11 functions as a drift layer, the second semiconductor portion 12 functions as a base layer, the third semiconductor portion 13 functions as a source layer, and the fourth semiconductor portion 14 functions as a drain layer.

[0042] When a first potential (e.g., ground potential) is applied to the first electrode 21, a second potential (e.g., positive potential) higher than the first potential is applied to the second electrode 22, and a gate voltage equal to or greater than a threshold value is applied to the gate electrode 30, an n-type inversion layer (channel) is formed in a portion of the second semiconductor portion 12 facing the gate electrode 30. Then, a current flows between the second electrode 22 (drain electrode) and the first electrode 21 (source electrode) via the fourth semiconductor portion 14 (drain layer), the channel, and the third semiconductor portion 13 (source layer).

[0043] By introducing a positive fixed charge into the first region 41A described above, electrons can be accumulated in a region adjacent to the first region 41A in the first semiconductor portion 11, thereby suppressing the spreading of the electron current and reducing the on-resistance.

[0044] 2(a) is a graph showing the relationship between on-resistance Ron (horizontal axis) and breakdown voltage Vdss (vertical axis) calculated by simulation. Characteristic a1 shows the Ron-Vdss characteristic of the semiconductor device of the above-mentioned embodiment. Characteristic a2 shows the Ron-Vdss characteristic of the semiconductor device of the comparative example. The semiconductor device of the comparative example has a similar structure to the semiconductor device of the embodiment, but does not include fixed charges in the insulating member.

[0045] As shown in the results of FIG. 2(a), the semiconductor device of the embodiment has a fixed charge density distribution in the insulating member 40 as shown in FIG. 1(b) described above, and thus has a lower on-resistance Ron and a higher breakdown voltage Vdss than the comparative example.

[0046] 2(b) is a graph showing the relationship between charge density (horizontal axis) and breakdown voltage Vdss (vertical axis) calculated by simulation. Characteristic b1 shows the characteristic when a fixed charge is introduced only in the first region 41A of the first insulating portion 41. Characteristic b2 shows the characteristic when a fixed charge is introduced only in the third region 41C of the first insulating portion 41.

[0047] In the characteristic b1 in which fixed charges are introduced into the first region 41A, the breakdown voltage decreases as the fixed charge density increases from the fixed charge density at the breakdown voltage Vdss similar to that of the characteristic b2. In contrast, in the characteristic b2 in which fixed charges are introduced into the third region 41C, the breakdown voltage increases as the fixed charge density increases from the fixed charge density at the breakdown voltage Vdss similar to that of the characteristic b1 to a certain value. Therefore, it is preferable that the third total amount of fixed charges in the third region 41C is greater than the first total amount of fixed charges in the first region 41A. It is preferable that the third maximum value of the density distribution of fixed charges along the first direction Z in the third region 41C is greater than the first maximum value of the density distribution of fixed charges along the first direction Z in the first region 41A.

[0048] In addition, when a fixed charge is introduced into the third region 41C (characteristic b2) and when a fixed charge is introduced into the first region 41A (characteristic b1), if the fixed charge density becomes too large, the breakdown voltage is significantly reduced. Therefore, for example, the first maximum value is converted into a surface charge density at the interface between the first insulating portion 41 and the semiconductor layer 10, and is 1.0×10 13 cm -2 For example, the third maximum value is preferably 1.0×10 or less when converted into a surface charge density at the interface between the first insulating portion 41 and the semiconductor layer 10. 14 cm -2 The following is preferred:

[0049] The density of fixed charges can be measured by, for example, ESR (Electron Spin Resonance), SIMS (Secondary Ion Mass Spectrometry), etc. In addition, the presence of fixed charges in an oxide film can be indirectly estimated by measuring defects in a semiconductor layer by DLTS (Deep Level Transient Spectroscopy), SR (Spreading Resistance), etc.

[0050] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0051] DESCRIPTION OF SYMBOLS 10...Semiconductor layer, 10A...First surface, 10B...Second surface, 11...First semiconductor portion, 12...Second semiconductor portion, 13...Third semiconductor portion, 14...Fourth semiconductor portion, 21...First electrode, 22...Second electrode, 30...Gate electrode, 40...Insulating member, 41...First insulating portion, 41A...First region, 41B...Second region, 41C...Third region, 42...Second insulating portion, 43...Third insulating portion, 44...Fourth insulating portion, 45...Fifth insulating portion, 50...Trench structure portion, 60...Conductive member

Claims

1. a semiconductor layer having a first surface and a second surface located on the opposite side of the first surface in a first direction; a trench structure extending in the first direction from the first surface and located within the semiconductor layer; Equipped with The trench structure is A gate electrode; a conductive member having a lower end located closer to the second surface than the gate electrode in the first direction; an insulating member including a fixed charge, the insulating member being located between the gate electrode and the semiconductor layer, between the conductive member and the semiconductor layer, and between the gate electrode and the conductive member; having the insulating member has a first insulating portion located between the gate electrode and the second surface in the first direction and located between the conductive member and the semiconductor layer in a second direction intersecting the first direction, the first insulating portion has a first region, a second region, and a third region; In the first direction, the first region is located between the gate electrode and the second region, the second region is located between the first region and the third region, and the third region is located between the second region and the second surface, A semiconductor device, wherein a first total amount of the fixed charges in the first region is greater than a second total amount of the fixed charges in the second region.

2. The semiconductor device according to claim 1 , wherein a third total amount of said fixed charges in said third region is greater than said second total amount.

3. The semiconductor device according to claim 1 , wherein the third total amount is greater than the first total amount.

4. a semiconductor layer having a first surface and a second surface located on the opposite side of the first surface in a first direction; a trench structure extending in the first direction from the first surface and located within the semiconductor layer; Equipped with The trench structure is A gate electrode; a conductive member having a lower end located closer to the second surface than the gate electrode in the first direction; an insulating member including a fixed charge, the insulating member being located between the gate electrode and the semiconductor layer, between the conductive member and the semiconductor layer, and between the gate electrode and the conductive member; having the insulating member has a first insulating portion located between the gate electrode and the second surface in the first direction and located between the conductive member and the semiconductor layer in a second direction intersecting the first direction, the first insulating portion has a first region, a second region, and a third region; In the first direction, the first region is located between the gate electrode and the second region, the second region is located between the first region and the third region, and the third region is located between the second region and the second surface, A semiconductor device, wherein a density of the fixed charges in the first region is greater than a density of the fixed charges in the second region.

5. The semiconductor device according to claim 4 , wherein a density of said fixed charges in said third region is greater than a density of said fixed charges in said second region.

6. The maximum value of the density distribution of the fixed charges along the first direction in the first region is 1.0×10 when converted into a surface charge density at the interface between the first insulating portion and the semiconductor layer. １３ cm －２ 6. The semiconductor device according to claim 5, wherein:

7. The maximum value of the density distribution of the fixed charges along the first direction in the third region is 1.0×10 when converted into a surface charge density at the interface between the first insulating portion and the semiconductor layer. １４ cm －２ cm －２ 6. The semiconductor device according to claim 5, wherein:

8. 5. The semiconductor device according to claim 1, wherein the fixed charges include at least one selected from the group consisting of hydrogen, helium, and argon.

9. A first electrode provided on the first surface; a second electrode provided on the second surface; Further equipped with The semiconductor layer is a first semiconductor portion of a first conductivity type provided on the second electrode; a second semiconductor portion of a second conductivity type provided on the first semiconductor portion; a third semiconductor portion of a first conductivity type provided on the second semiconductor portion and electrically connected to the first electrode; The semiconductor device according to claim 1 , further comprising:

10. The semiconductor device according to claim 9 , wherein the conductive member is electrically connected to the first electrode.

11. The first region has a fixed charge density of 2×10 １５ cm ３ Including the larger part, The second region has a fixed charge density of 1×10 １５ cm ３ Includes smaller parts, The third region has a fixed charge density of 5×10 １５ cm ３ The semiconductor device of claim 1 including a larger portion.

12. a semiconductor layer having a first surface and a second surface located on the opposite side of the first surface in a first direction; a trench structure extending in the first direction from the first surface and located within the semiconductor layer; Equipped with The trench structure is A gate electrode; a conductive member having a lower end located closer to the second surface than the gate electrode in the first direction; an insulating member located between the gate electrode and the semiconductor layer, between the conductive member and the semiconductor layer, and between the gate electrode and the conductive member, the insulating member containing a first element, the first element containing at least one selected from the group consisting of hydrogen, helium, and argon; having the insulating member has a first insulating portion located between the gate electrode and the second surface in the first direction and located between the conductive member and the semiconductor layer in a second direction intersecting the first direction, the first insulating portion includes a first position that divides a portion between a position in the first direction of an end portion of the gate electrode on the second surface side and a position in the first direction of an end portion of the conductive member on the second surface side at a ratio of 1:9, a second position that divides the portion in the first direction at a ratio of 1:1, and a third position that divides the portion in the first direction at a ratio of 9:1; a concentration of the first element at the first location is greater than a concentration of the first element at the second location, and a concentration of the first element at the third location is greater than a concentration of the first element at the second location.

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