Calculation device

Abstract

To provide a calculation device that can obtain stable characteristics.SOLUTION: A calculation device according to an embodiment includes an element portion. The element portion includes a first structure and a second structure. The first structure includes a first substrate and a first quantum bit fixed to the first substrate. The second structure includes a second substrate, a second quantum bit fixed to the second substrate, and a first variable coupler fixed to the second substrate. The first variable coupler includes a first portion and a second portion. The first portion is capacitively couplable to the first quantum bit, and the second portion is capacitively couplable to the second quantum bit.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present invention relate to a computing device. [Background technology]

[0002] For example, electronic circuits including a plurality of nonlinear elements are used in computing devices, and it is desirable to stabilize the characteristics of the electronic circuits and computing devices. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2023-20041 A Summary of the Invention [Problem to be solved by the invention]

[0004] SUMMARY OF THE PRESENTLY PREFERRED EMBODIMENTS An embodiment of the present invention provides a computing device that provides stable performance. [Means for solving the problem]

[0005] According to an embodiment of the present invention, a computing device includes an element unit. The element unit includes a first structure and a second structure. The first structure includes a first substrate and a first quantum bit fixed to the first substrate. The second structure includes a second substrate, a second quantum bit fixed to the second substrate, and a first variable coupler fixed to the second substrate. The first variable coupler includes a first portion and a second portion. The first portion is capacitively coupleable to the first quantum bit, and the second portion is capacitively coupleable to the second quantum bit. [Brief description of the drawings]

[0006] [Figure 1] 1(a) and 1(b) are schematic diagrams illustrating a computing device according to the first embodiment. [Diagram 2]2A and 2B are schematic cross-sectional views illustrating a computing device according to the first embodiment. [Diagram 3] FIG. 3 is a schematic diagram illustrating a computing device according to the first embodiment. [Figure 4] FIG. 4 is a schematic perspective view illustrating the computing device according to the first embodiment. [Diagram 5] FIG. 5 is a schematic perspective view illustrating the computing device according to the first embodiment. [Figure 6] 6A and 6B are schematic cross-sectional views illustrating a computing device according to the first embodiment. [Figure 7] 7(a) and 7(b) are schematic diagrams illustrating a computing device according to the second embodiment. [Figure 8] FIG. 8 is a schematic plan view illustrating a computing device according to the second embodiment. [Figure 9] FIG. 9 is a schematic cross-sectional view illustrating a computing device according to the second embodiment. [Figure 10] FIG. 10 is a schematic cross-sectional view illustrating a computing device according to the second embodiment. [Figure 11] FIG. 11 is a schematic cross-sectional view illustrating a computing device according to the second embodiment. [Figure 12] FIG. 12 is a schematic cross-sectional view illustrating a computing device according to the embodiment. [Figure 13] FIG. 13 is a schematic cross-sectional view illustrating a computing device according to the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios of each part may be different depending on the drawing. In this specification and each drawing, elements similar to those described above with reference to the previous drawings are given the same reference numerals and detailed descriptions thereof will be omitted as appropriate.

[0008] (First embodiment) 1(a) and 1(b) are schematic diagrams illustrating a calculation device according to a first embodiment, in which (a) is a plan view, and (b) is a cross-sectional view taken along line A1-A2 in (a) of FIG. 2A and 2B are schematic cross-sectional views illustrating a computing device according to the first embodiment. Fig. 2(a) is a cross-sectional view taken along line B1-B2 in Fig. 1(a), and Fig. 2(b) is a cross-sectional view taken along line B3-B4 in Fig. 1(a). As shown in FIG. 1(a), a computing device 110 according to the embodiment includes an element unit 10E.

[0009] The element portion 10E includes a first structure 11 and a second structure 12. The first structure 11 includes a first substrate 11s and a first quantum bit 11b. The first quantum bit 11b is fixed to the first substrate 11s. In one example, the first quantum bit 11b includes a first quantum bit Josephson junction 11bJ. For example, the first quantum bit 11b includes a first quantum bit Josephson junction 11bJ and a first quantum bit capacitor 11bC. The first quantum bit Josephson junction 11bJ and the first quantum bit capacitor 11bC are connected in parallel.

[0010] The second structure 12 includes a second substrate 12s, a second quantum bit 12b, and a first variable coupler 50A. The second quantum bit 12b is fixed to the second substrate 12s. In one example, the second quantum bit 12b includes a second quantum bit Josephson junction 12bJ. For example, the second quantum bit 12b includes a second quantum bit Josephson junction 12bJ and a second quantum bit capacitor 12bC. The second quantum bit Josephson junction 12bJ and the second quantum bit capacitor 12bC are connected in parallel.

[0011] The first variable coupler 50A is fixed to the second base 12s. The first variable coupler 50A includes a first portion 41 and a second portion 42. The first portion 41 is capacitively coupleable to the first quantum bit 11b. The second portion 42 is capacitively coupleable to the second quantum bit 12b.

[0012] In the computing device 110, the first substrate 11s on which the first quantum bit 11b is provided is separated from the second substrate 12s on which the second quantum bit 12b is provided. For example, a plurality of first structures 11 are manufactured, and a plurality of second structures 12 are manufactured. The plurality of first structures 11 are inspected, and a plurality of first structures 11 having good characteristics are extracted. The plurality of second structures 12 are inspected, and a plurality of second structures 12 having good characteristics are extracted. The first structures 11 having good characteristics and the second structures 12 having good characteristics are combined. This allows good characteristics to be stably obtained. For example, in the case where a plurality of element units 10E are provided, it is easy to increase the scale. A computing device that can obtain large-scale and stable characteristics can be efficiently obtained. According to the embodiment, a computing device that can obtain stable characteristics can be provided.

[0013] In the computing device 110, the first quantum bit 11b is coupled to the second quantum bit 12b via the first variable coupler 50A. The coupling strength is variable. For example, a stable bit operation can be performed. For example, a stable two-qubit operation can be performed.

[0014] As shown in FIG. 1(a), in this example, the element unit 10E further includes a first connection unit 31C. The first structure 11 further includes a first conductive unit 11c fixed to a first base 11s. The first conductive unit 11c can be capacitively coupled to the first quantum bit 11b. The first connection unit 31C electrically connects the first conductive unit 11c to the first portion 41. The first connection unit 31C is, for example, a superconductor.

[0015] As shown in FIG. 1(a), in this example, the second structure 12 further includes a second conductive portion 12c. The second conductive portion 12c is electrically connected to the second portion 42. The second conductive portion 12c can be capacitively coupled to the second quantum bit 12b. The second conductive portion 12c may be continuous with the second portion 42. The boundary between the second conductive portion 12c and the second portion 42 may be clear or unclear.

[0016] The first direction D1 from the first base 11s to the first quantum bit 11b is defined as the Z-axis direction. A direction perpendicular to the Z-axis direction is defined as the X-axis direction. A direction perpendicular to the Z-axis direction and the X-axis direction is defined as the Y-axis direction. The first base 11s is aligned along the XY plane. In this example, the second base 12s is aligned along the XY plane. In an embodiment, a plane parallel to the second base 12s may intersect with the XY plane.

[0017] As shown in FIG. 1(a), the first variable coupler 50A includes a first Josephson junction 51, a second Josephson junction 52, and a third Josephson junction 53. The first Josephson junction 51 includes a first end 51e and a first other end 51f. The second Josephson junction 52 includes a second end 52e and a second other end 52f. The third Josephson junction 53 includes a third end 53e and a third other end 53f. The first end 51e is connected to the third end 53e. The first other end 51f is connected to the second other end 52f. In this example, the first other end 51f is connected to the second other end 52f via a first conductive member 58a. The second end 52e is connected to the third other end 53f. The first portion 41 is connected to the first end 51e and the third end 53e. The second portion 42 is connected to the second end 52e and the third other end 53f. The first variable coupler 50A is, for example, a double transmon coupler.

[0018] 1(b), a third insulating member 53i is provided between the conductive member including the third end portion 53e and the conductive member including the third other end portion 53f. A region including the third insulating member 53i becomes a third Josephson junction 53.

[0019] 2(a), a first insulating member 51i is provided between a conductive member including a first end portion 51e and a conductive member including a first other end portion 51f. A region including the first insulating member 51i becomes a first Josephson junction 51.

[0020] 2(b), a second insulating member 52i is provided between the conductive member including the second end portion 52e and the conductive member including the second other end portion 52f. The region including the second insulating member 52i becomes the second Josephson junction 52.

[0021] FIG. 3 is a schematic diagram illustrating a computing device according to the first embodiment. 3, the device 110 according to the embodiment may further include a first control conductive member 61 and a controller 70. The controller 70 can supply a signal S1 to the first control conductive member 61. The signal S1 supplied to the first control conductive member 61 changes the magnetic flux in the space 51SP in the loop 51L including the first Josephson junction 51, the second Josephson junction 52, and the third Josephson junction 53. The change in the magnetic flux in the space 51SP in the loop 51L changes the coupling strength.

[0022] The control unit 70 can perform, for example, a two-qubit gate operation by supplying the signal S1 to the first control conductive member 61. The signal S1 is, for example, a pulse including an AC component. The frequency of the AC component included in the signal S1 is set, for example, to the difference or sum of the frequency of the first quantum bit and the frequency of the second quantum bit. In one example of the case where the frequency is set to the difference, the frequency of the AC component included in the signal S1 is, for example, 100 MHz or more and 1 GHz or less. In one example of the case where the frequency is set to the sum, the frequency of the AC component included in the signal S1 is, for example, 8 GHz or more and 10 GHz or less. In another example, the signal S1 is, for example, a pulse including a DC component.

[0023] The first control conductive member 61 may be in contact with, for example, a substrate (in this example, the second substrate 12s) on which the first variable coupler 50A is provided. The first control conductive member 61 may be separated from, for example, the substrate on which the first variable coupler 50A is provided.

[0024] FIG. 4 is a schematic perspective view illustrating the computing device according to the first embodiment. 4, the computing device 111 according to the embodiment includes a plurality of element units 10E. In this example, the plurality of element units 10E are arranged along the XY plane. In the embodiment, the direction in which the plurality of element units 10E are arranged is arbitrary. In the computing device 111, the configuration of each of the plurality of element units 10E may be similar to the configuration of the element unit 10E in the computing device 110.

[0025] FIG. 5 is a schematic perspective view illustrating the computing device according to the first embodiment. 6A and 6B are schematic cross-sectional views illustrating a computing device according to the first embodiment. 5, in a computing device 112 according to the embodiment, the element unit 10E further includes a third structure 13 and a first connection structure 11CB. Except for this, the configuration of the computing device 112 may be similar to the configuration of the computing device 110.

[0026] Second structure 12 further includes second other quantum bit 12bA fixed to second substrate 12s. Third structure 13 includes third substrate 13s and third quantum bit 13b fixed to third substrate 13s.

[0027] 6(a) illustrates a first connection structure 11CB. The first connection structure 11CB includes a first connection base 11Cs and a second variable coupler 50B fixed to the first connection base 11Cs. The second variable coupler 50B includes a third portion 43 and a fourth portion 44. The third portion 43 can be capacitively coupled to the third quantum bit 13b. The fourth portion 44 can be capacitively coupled to the second other quantum bit 12bA.

[0028] In this example, the element portion 10E further includes a second opposing connection portion 32CA. The second structure 12 further includes a second opposing conductive portion 12cA fixed to the second base 12s. The second opposing conductive portion 12cA can be capacitively coupled to the second other quantum bit 12bA. The second opposing connection portion 32CA electrically connects the second opposing conductive portion 12cA to the fourth portion 44 (see FIG. 6(a)).

[0029] In this example, element unit 10E further includes a second connection unit 32C. Third structure 13 further includes a third conductive unit 13c. Third conductive unit 13c can be capacitively coupled to third quantum bit 13b. Second connection unit 32C electrically connects third conductive unit 13c to third portion 43 (see FIG. 6(a)).

[0030] As shown in FIG. 6(a), the second variable coupler 50B includes a fourth Josephson junction 54, a fifth Josephson junction 55, and a sixth Josephson junction 56. The fourth Josephson junction 54 includes a fourth end 54e and a fourth other end 54f. The fifth Josephson junction 55 includes a fifth end 55e and a fifth other end 55f. The sixth Josephson junction 56 includes a sixth end 56e and a sixth other end 56f. The fourth end 54e is connected to the sixth end 56e. The fourth other end 54f is connected to the fifth other end 55f. In this example, the fourth other end 54f is connected to the fifth other end 55f via the second conductive member 58b. The fifth end 55e is connected to the sixth other end 56f. The third portion 43 is connected to the fourth end 54e and the sixth end 56e. The fourth portion 44 is connected to the fifth end 55e and the sixth other end 56f. The second variable coupler 50B is, for example, a double transmon coupler.

[0031] The configurations of the fourth Josephson junction 54, the fifth Josephson junction 55, and the sixth Josephson junction 56 may be similar to the configurations of the first Josephson junction 51, the second Josephson junction 52, and the third Josephson junction 53. In the second variable coupler 50B, a configuration similar to that of the first control conductive member 61 may be applied.

[0032] As shown in FIG. 5, in the computing device 112, the element unit 10E may further include a fourth structure 14. The third structure 13 further includes a third other quantum bit 13bA fixed to a third base 13s. The fourth structure 14 includes a fourth base 14s, a fourth quantum bit 14b fixed to the fourth base 14s, and a third variable coupler 50C fixed to the fourth base 14s. The third variable coupler 50C includes a fifth portion 45 and a sixth portion 46. The fifth portion 45 can be capacitively coupled to the third other quantum bit 13bA. The sixth portion 46 can be capacitively coupled to the fourth quantum bit 14b.

[0033] In this example, the element portion 10E further includes a third connection portion 33C. As shown in FIG. 6(b), the third structure 13 further includes a third other conductive portion 13cA. The third other conductive portion 13cA can be capacitively coupled to the third other quantum bit 13bA. The third connection portion 33C electrically connects the third other conductive portion 13cA to the fifth portion 45.

[0034] As shown in FIG. 6(b), in this example, the fourth structure 14 further includes a fourth conductive portion 14c. The fourth conductive portion 14c is electrically connected to the sixth portion 46. The fourth conductive portion 14c can be capacitively coupled to the fourth quantum bit 14b. The fourth conductive portion 14c may be continuous with the sixth portion 46. The boundary between the fourth conductive portion 14c and the sixth portion 46 may be clear or unclear.

[0035] As shown in FIG. 6(b), the third variable coupler 50C includes a seventh Josephson junction 57, an eighth Josephson junction 58, and a ninth Josephson junction 59. The seventh Josephson junction 57 includes a seventh end 57e and a seventh other end 57f. The eighth Josephson junction 58 includes an eighth end 58e and an eighth other end 58f. The ninth Josephson junction 59 includes a ninth end 59e and a ninth other end 59f. The seventh end 57e is connected to the ninth end 59e. The seventh other end 57f is connected to the eighth other end 58f. In this example, the seventh other end 57f is connected to the eighth other end 58f via the third connection member 58c. The eighth end 58e is connected to the ninth other end 59f. The fifth portion 45 is connected to the seventh end 57e and the ninth end 59e. The sixth portion 46 is connected to the eighth end 58e and the ninth other end 59f. The third variable coupler 50C is, for example, a double transmon coupler.

[0036] The seventh Josephson junction 57, the eighth Josephson junction 58, and the ninth Josephson junction 59 may have the same configuration as the first Josephson junction 51, the second Josephson junction 52, and the third Josephson junction 53. In the third variable coupler 50C, a configuration similar to that of the first control conductive member 61 may be applied.

[0037] Second embodiment 7(a) and 7(b) are schematic diagrams illustrating a calculation device according to the second embodiment, where Fig. 7(a) is a plan view, and Fig. 7(b) is a cross-sectional view taken along line A3-A4 in Fig. 7(a). As shown in FIGS. 7(a) and 7(b), a computing device 120 according to the embodiment includes an element unit 10E.

[0038] The element section 10E includes a first structure 11, a second structure 12, and a first variable coupler 50A. The first structure 11 includes a first base 11s and a first quantum bit 11b fixed to the first base 11s. The second structure 12 includes a second base 12s and a second quantum bit 12b fixed to the second base 12s.

[0039] The first variable coupler 50A includes a third substrate 13s, a first portion 41 fixed to the third substrate 13s, and a second portion 42 fixed to the third substrate 13s. The first portion 41 is capacitively coupleable to the first quantum bit 11b. The second portion 42 is capacitively coupleable to the second quantum bit 12b.

[0040] In the computing device 120, for example, a plurality of first structures 11, a plurality of second structures 12, and a plurality of first variable couplers 50A are manufactured. The plurality of first structures 11 are inspected, and a plurality of first structures 11 having good characteristics are extracted. The plurality of second structures 12 are inspected, and a plurality of second structures 12 having good characteristics are extracted. The plurality of first variable couplers 50A are inspected, and a plurality of first variable couplers 50A having good characteristics are extracted. The first structure 11 having good characteristics, the second structure 12 having good characteristics, and the first variable coupler 50A having good characteristics are combined. This allows good characteristics to be stably obtained. For example, in the case where a plurality of element sections 10E are provided, it is easy to increase the scale. A computing device that can obtain large-scale and stable characteristics can be efficiently obtained. According to the embodiment, a computing device that can obtain stable characteristics can be provided.

[0041] In this example, the element unit 10E further includes a first connection unit 31C. The first structure 11 further includes a first conductive unit 11c fixed to the first base 11s. The first conductive unit 11c can be capacitively coupled to the first quantum bit 11b. The first connection unit 31C electrically connects the first conductive unit 11c to the first portion 41.

[0042] In this example, the element portion 10E further includes a second connection portion 32C. The second structure 12 further includes a second conductive portion 12c fixed to a second base 12s. The second conductive portion 12c can be capacitively coupled to the second quantum bit 12b. The second connection portion 32C electrically connects the second conductive portion 12c to the second portion 42.

[0043] In the computing device 120, the configuration of the first variable coupler 50A may be similar to that of the first variable coupler 50A in the computing device 110. For example, the first variable coupler 50A includes a first Josephson junction 51, a second Josephson junction 52, and a third Josephson junction 53 (see FIG. 7(a)). The first Josephson junction 51 includes a first end 51e and a first other end 51f. The second Josephson junction 52 includes a second end 52e and a second other end 52f. The third Josephson junction 53 includes a third end 53e and a third other end 53f. The first end 51e is connected to the third end 53e. The first other end 51f is connected to the second other end 52f. In this example, the first other end 51f is connected to the second other end 52f via a first conductive member 58a. The second end 52e is connected to the third other end 53f. The first portion 41 is connected to the first end 51e and the third end 53e. The second portion 42 is connected to the second end 52e and the third other end 53f. The first variable coupler 50A is, for example, a double transmon coupler.

[0044] In the computing device 120 , the configurations of the first Josephson junction 51 and the second Josephson junction 52 may be similar to those in the computing device 110 .

[0045] FIG. 8 is a schematic plan view illustrating a computing device according to the second embodiment. 8, the device 121 according to the embodiment may further include a first control conductive member 61 and a controller 70. The controller 70 can supply a signal S1 to the first control conductive member 61. The signal S1 supplied to the first control conductive member 61 changes the magnetic flux in the space 51SP in the loop 51L including the first Josephson junction 51, the second Josephson junction 52, and the third Josephson junction 53. The change in the magnetic flux in the space 51SP in the loop 51L changes the coupling strength.

[0046] The control unit 70 can perform, for example, a two-qubit gate operation by supplying a signal S1 to the first control conductive member 61. The signal S1 is, for example, a pulse including an AC component. The frequency of the AC component included in the signal S1 is set to, for example, the difference or sum of the frequency of the first quantum bit and the frequency of the second quantum bit. In another example, the signal S1 is, for example, a pulse including a DC component.

[0047] FIG. 9 is a schematic cross-sectional view illustrating a computing device according to the second embodiment. As shown in FIG. 9, in a computing device 121 according to the embodiment, the first structure 11 further includes a first conductive portion 11c fixed to a first base 11s. The first conductive portion 11c can be capacitively coupled to the first quantum bit 11b. The first conductive portion 11c is electrically connected to the first portion 41. The second structure 12 further includes a second conductive portion 12c fixed to a second base 12s. The second conductive portion 12c can be capacitively coupled to the second quantum bit 12b. The second conductive portion 12c is electrically connected to the second portion 42. The configuration of the computing device 121 other than the above may be the same as the configuration of the computing device 120. In the computing device 121, the first conductive portion 11c faces the first portion 41. The second conductive portion 12c faces the second portion 42.

[0048] FIG. 10 is a schematic cross-sectional view illustrating a computing device according to the second embodiment. As shown in FIG. 10, in a computing device 122 according to the embodiment, the first structure 11 further includes a first conductive portion 11c fixed to a first base 11s. The first conductive portion 11c can be capacitively coupled to the first quantum bit 11b. The first conductive portion 11c can be capacitively coupled to the first portion 41. The second structure 12 further includes a second conductive portion 12c fixed to a second base 12s. The second conductive portion 12c can be capacitively coupled to the second quantum bit 12b. The second conductive portion 12c can be capacitively coupled to the second portion 42. The configuration of the computing device 122 other than the above may be the same as the configuration of the computing device 120.

[0049] In the computing device 122, the first conductive portion 11c faces the first portion 41. The second conductive portion 12c faces the second portion 42. The first conductive portion 11c is spaced apart from the first portion 41. The second conductive portion 12c is spaced apart from the second portion 42.

[0050] FIG. 11 is a schematic cross-sectional view illustrating a computing device according to the second embodiment. 11 , in a computing device 123 according to the embodiment, a first quantum bit 11b faces a first portion 41. The first quantum bit 11b can be capacitively coupled to the first portion 41. The second quantum bit 12b faces a second portion 42. The second quantum bit 12b can be capacitively coupled to the second portion 42. The configuration of the computing device 123 other than the above may be similar to the configuration of the computing device 120.

[0051] In the calculation device 121, the calculation device 122, and the calculation device 123, good characteristics can be stably obtained. For example, it is easy to increase the scale. A calculation device that can obtain large-scale and stable characteristics can be efficiently obtained. According to the embodiment, a calculation device that can obtain stable characteristics can be provided.

[0052] In the configurations of the computing device 120, the computing device 121, the computing device 122, and the computing device 123, a plurality of element units 10E may be provided.

[0053] FIG. 12 is a schematic cross-sectional view illustrating a computing device according to the embodiment. 12, in a computing device 110a according to the embodiment, a first structure 11 includes a first conductive layer 11G. A second structure 12 includes a second conductive layer 12G. The configuration of the computing device 110a other than the above may be similar to the configuration of the computing device 110.

[0054] The first conductive layer 11G is provided on the first base 11s. The first conductive layer 11G functions, for example, as a ground layer. The first conductive layer 11G may function, for example, as a part of the first quantum bit 11b. The second conductive layer 12G is provided on the second base 12s. The second conductive layer 12G functions, for example, as a ground layer. The second conductive layer 12G may function, for example, as a part of the second quantum bit 12b. The first conductive layer 11G is electrically connected to the first conductive member 58a.

[0055] FIG. 13 is a schematic cross-sectional view illustrating a computing device according to the embodiment. 13, in a computing device 110b according to the embodiment, the first structure 11 includes a first intermediate conductive layer 11M. The second structure 12 includes a second intermediate conductive layer 12M. The configuration of the computing device 110b other than the above may be similar to the configuration of the computing device 110a.

[0056] The first intermediate conductive layer 11M is provided on the first substrate 11s. The first intermediate conductive layer 11M functions as, for example, a ground layer. The first intermediate conductive layer 11M may function as, for example, a part of the first quantum bit 11b. The first intermediate conductive layer 11M is capacitively coupled to the first conductive layer 11G. The first conductive layer 11G is electrically connected to the first conductive member 58a.

[0057] The second intermediate conductive layer 12M is provided on the second substrate 12s. The second intermediate conductive layer 12M functions, for example, as a ground layer. The second intermediate conductive layer 12M may function, for example, as a part of the second quantum bit 12b. The second intermediate conductive layer 12M is capacitively coupled to the second conductive layer 12G. The second conductive layer 12G is continuous with the first conductive member 58a.

[0058] The above-mentioned first conductive layer 11G and second conductive layer 12G may be applied to the second embodiment. The above-mentioned first intermediate conductive layer 11M and second intermediate conductive layer 12M may be applied to the second embodiment.

[0059] The embodiments may include the following technical solutions. (Technical proposal 1) An element portion is provided, The element portion is a first structure including a first substrate and a first quantum bit fixed to the first substrate; a second structure including a second substrate, a second quantum bit fixed to the second substrate, and a first variable coupler fixed to the second substrate, the first variable coupler including a first portion and a second portion, the first portion being capacitively coupleable to the first quantum bit, and the second portion being capacitively coupleable to the second quantum bit; 13. A computing device comprising:

[0060] (Technical proposal 2) The first variable coupler is a first Josephson junction, a second Josephson junction, and a third Josephson junction; the first Josephson junction includes a first end and a first other end; the second Josephson junction includes a second end and a second other end; the third Josephson junction includes a third end and a third other end; the first end is connected to the third end, the first other end is connected to the second other end, The second end is connected to the third other end, the first portion is connected to the first end and the third end, The computing device described in technical solution 1, wherein the second part is connected to the second end and the third other end.

[0061] (Technical proposal 3) The element portion further includes a first connection portion, the first structure further includes a first conductive portion fixed to the first base, the first conductive portion is capable of being capacitively coupled to the first quantum bit; The computing device described in Technical Solution 1 or 2, wherein the first connection portion electrically connects the first conductive portion to the first portion.

[0062] (Technical proposal 4) The second structure further includes a second conductive portion, the second conductive portion is electrically connected to the second portion, The computing device described in Technical Proposal 3, wherein the second conductive portion is capable of being capacitively coupled to the second quantum bit.

[0063] (Technical proposal 5) the element portion further includes a third structure and a first connection structure, the second structure further includes a second other quantum bit fixed to the second substrate; the third structure includes a third substrate and a third quantum bit fixed to the third substrate; the first connection structure includes a first connection base and a second variable coupler fixed to the first connection base, the second variable coupler includes a third section and a fourth section; the third portion is capacitively coupleable to the third qubit; The computing device according to any one of Technical Schemes 1 to 3, wherein the fourth portion is capable of being capacitively coupled to the second other quantum bit.

[0064] (Technical proposal 6) The second variable coupler is a fourth Josephson junction, a fifth Josephson junction, and a sixth Josephson junction; the fourth Josephson junction includes a fourth end and a fourth other end, the fifth Josephson junction includes a fifth end and a fifth other end; the sixth Josephson junction includes a sixth end and a sixth other end, the fourth end is connected to the sixth end, the fourth other end is connected to the fifth other end, the fifth end is connected to the sixth other end, the third portion is connected to the fourth end and the sixth end, The computing device described in technical solution 5, wherein the fourth part is connected to the fifth end and the sixth other end.

[0065] (Technical proposal 7) The element portion further includes a second opposing connection portion, the second structure further includes a second opposing conductive portion fixed to the second base, the second opposing conductive portion is capable of being capacitively coupled to the second other quantum bit; The computing device according to Technical Solution 5 or 6, wherein the second opposing connection portion electrically connects the second opposing conductive portion to the fourth portion.

[0066] (Technical proposal 8) The element portion further includes a second connection portion, the third structure further includes a third conductive portion, the third conductive portion is capable of being capacitively coupled to the third quantum bit; The computing device according to any one of Technical Solutions 5 to 7, wherein the second connection portion electrically connects the third conductive portion to the third portion.

[0067] (Technical proposal 9) The element portion further includes a fourth structure, the third structure further includes a third other quantum bit fixed to the third substrate; the fourth structure includes a fourth substrate, a fourth quantum bit fixed to the fourth substrate, and a third variable coupler fixed to the fourth substrate; the third variable coupler includes a fifth section and a sixth section; the fifth portion is capable of being capacitively coupled to the third other quantum bit; The computing device according to any one of Technical Solutions 5 to 8, wherein the sixth portion is capable of being capacitively coupled to the fourth quantum bit.

[0068] (Technical proposal 10) The third variable coupler is a seventh Josephson junction, an eighth Josephson junction, and a ninth Josephson junction; the seventh Josephson junction includes a seventh end and a seventh other end; the eighth Josephson junction includes an eighth end and an eighth other end; the ninth Josephson junction includes a ninth end and a ninth other end, the seventh end is connected to the ninth end, the seventh other end is connected to the eighth other end, The eighth end is connected to the ninth other end, the fifth portion is connected to the seventh end and the ninth end, The computing device according to technical solution 9, wherein the sixth part is connected to the eighth end and the ninth other end.

[0069] (Technical proposal 11) The element portion includes: a first structure including a first substrate and a first quantum bit fixed to the first substrate; a second structure including a second substrate and a second quantum bit fixed to the second substrate; a first variable coupler including a third substrate, a first portion fixed to the third substrate, and a second portion fixed to the third substrate, the first portion being capacitively coupleable to the first quantum bit, and the second portion being capacitively coupleable to the second quantum bit; 13. A computing device comprising:

[0070] (Technical proposal 12) The first variable coupler is a first Josephson junction, a second Josephson junction, and a third Josephson junction; the first Josephson junction includes a first end and a first other end; the second Josephson junction includes a second end and a second other end; the third Josephson junction includes a third end and a third other end; the first end is connected to the third end, the first other end is connected to the second other end, The second end is connected to the third other end, the first portion is connected to the first end and the third end, The computing device described in technical solution 11, wherein the second part is connected to the second end and the third other end.

[0071] (Technical proposal 13) The element portion further includes a first connection portion, the first structure further includes a first conductive portion fixed to the first base, the first conductive portion is capable of being capacitively coupled to the first quantum bit; The computing device according to technical proposal 11 or 12, wherein the first connection portion electrically connects the first conductive portion to the first portion.

[0072] (Technical proposal 14) The element portion further includes a second connection portion, the second structure further includes a second conductive portion fixed to the second base, the second conductive portion is capable of being capacitively coupled to the second quantum bit; The computing device described in technical proposal 13, wherein the second connection portion electrically connects the second conductive portion to the second portion.

[0073] (Technical proposal 15) the first structure further includes a first conductive portion fixed to the first base, the first conductive portion is capable of being capacitively coupled to the first quantum bit; the first conductive portion is electrically connected to the first portion, the second structure further includes a second conductive portion fixed to the second base, the second conductive portion is capable of being capacitively coupled to the second quantum bit; The computing device according to technical proposal 11 or 12, wherein the second conductive part is electrically connected to the second part.

[0074] (Technical proposal 16) the first structure further includes a first conductive portion fixed to the first base, the first conductive portion is capable of being capacitively coupled to the first quantum bit; the first conductive portion is capable of being capacitively coupled to the first portion; the second structure further includes a second conductive portion fixed to the second base, the second conductive portion is capable of being capacitively coupled to the second quantum bit; The computing device according to technical proposal 11 or 12, wherein the second conductive portion is capacitively coupled to the second portion.

[0075] (Technical proposal 17) the first conductive portion faces the first portion, The computing device according to technical proposal 15 or 16, wherein the second conductive portion faces the second portion.

[0076] (Technical proposal 18) A first control conductive member; A control unit; Further equipped with The control unit is capable of supplying a signal to the first control conductive member; The computing device according to Technical Solution 2, wherein the signal supplied to the first control conductive member changes the magnetic flux in the space within a loop including the first Josephson junction, the second Josephson junction, and the third Josephson junction.

[0077] (Technical proposal 19) The computing device according to technical proposal 18, wherein the signal includes an AC component.

[0078] (Technical proposal 20) The computing device described in Technical Proposal 18 or 19, wherein the control unit is capable of performing a two-qubit operation by supplying the signal to the first control conductive member.

[0079] According to the embodiment, it is possible to provide an electronic circuit and a computing device that can improve the performance.

[0080] The above describes the embodiment of the present invention with reference to examples. However, the present invention is not limited to these examples. For example, the specific configuration of each element such as the substrate, quantum bit, variable coupler and control unit included in the computing device is included in the scope of the present invention as long as a person skilled in the art can implement the present invention in the same way by appropriately selecting from the known range and obtain the same effect.

[0081] Any combination of two or more elements of each example, within the scope of technical feasibility, is also included within the scope of the present invention as long as it includes the gist of the present invention.

[0082] All computing devices that can be implemented by a person skilled in the art by appropriately modifying the design of the computing device described above as an embodiment of the present invention are within the scope of the present invention as long as they include the gist of the present invention.

[0083] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications and alterations, and it is understood that these modifications and alterations also fall within the scope of the present invention.

[0084] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0085] 10E: element portion, 11-14: first to fourth structures, 11CB: first connection structure, 11Cs: first connection base, 11G, 12G: first and second conductive layers, 11M, 12M: first and second intermediate conductive layers, 11b-14b: first to fourth quantum bits, 11bC, 12bC: first and second quantum bit capacitors, 11bJ, 12bJ: first and second quantum bit Josephson junctions, 11c-14c: first to fourth conductive portions, 11s-14s: first to fourth bases, 12bA: second other quantum bit, 12cA: second opposing conductive portion, 13bA: third other quantum bit, 13cA: third other conductive portion, 31C-33C: first to third connection portions, 32CA: second opposing connection portion, 41-46: first to sixth portions, 50A-50C: first to third variable couplers, 51-59: first to ninth Josephson junctions, 51L: loop, 51SP: space, 51e-59e: first to ninth ends, 51f-59f: first to ninth other ends, 51i-53i: first to third insulating members, 61: first control conductive member, 70: control unit, 110-112, 110a, 110b, 120-123: computing devices, D1: first direction, S1: signal

Claims

1. An element portion is provided, The element portion is a first structure including a first substrate and a first quantum bit fixed to the first substrate; a second structure including a second substrate, a second quantum bit fixed to the second substrate, and a first variable coupler fixed to the second substrate, the first variable coupler including a first portion and a second portion, the first portion being capacitively coupleable to the first quantum bit, and the second portion being capacitively coupleable to the second quantum bit; 13. A computing device comprising:

2. The first variable coupler comprises: a first Josephson junction, a second Josephson junction, and a third Josephson junction; the first Josephson junction includes a first end and a first other end; the second Josephson junction includes a second end and a second other end; the third Josephson junction includes a third end and a third other end, the first end is connected to the third end, The first other end is connected to the second other end, The second end is connected to the third other end, the first portion is connected to the first end and the third end; The computing device of claim 1 , wherein the second portion is connected to the second end and to the third other end.

3. the element portion further includes a third structure and a first connection structure, the second structure further includes a second other quantum bit fixed to the second substrate; the third structure includes a third substrate and a third quantum bit fixed to the third substrate; the first connection structure includes a first connection base and a second variable coupler fixed to the first connection base; the second variable coupler includes a third section and a fourth section; the third portion is capacitively coupleable to the third qubit; The computing device of claim 1 , wherein the fourth portion is capable of being capacitively coupled to the second other quantum bit.

4. The second variable coupler is a fourth Josephson junction, a fifth Josephson junction, and a sixth Josephson junction; the fourth Josephson junction includes a fourth end and a fourth other end, the fifth Josephson junction includes a fifth end and a fifth other end, the sixth Josephson junction includes a sixth end and a sixth other end, the fourth end is connected to the sixth end, the fourth other end is connected to the fifth other end, The fifth end is connected to the sixth other end, the third portion is connected to the fourth end and the sixth end, The computing device of claim 3 , wherein the fourth portion is connected to the fifth end and the sixth other end.

5. The element portion further includes a fourth structure, the third structure further includes a third other quantum bit fixed to the third substrate; the fourth structure includes a fourth substrate, a fourth quantum bit fixed to the fourth substrate, and a third variable coupler fixed to the fourth substrate; the third variable coupler includes a fifth section and a sixth section; the fifth portion is capable of being capacitively coupled to the third other quantum bit; The computing device of claim 3 , wherein the sixth portion is capacitively coupleable to the fourth qubit.

6. The third variable coupler is a seventh Josephson junction, an eighth Josephson junction, and a ninth Josephson junction; the seventh Josephson junction includes a seventh end and a seventh other end; the eighth Josephson junction includes an eighth end and an eighth other end, the ninth Josephson junction includes a ninth end and a ninth other end, the seventh end is connected to the ninth end, The seventh other end is connected to the eighth other end, The eighth end is connected to the ninth other end, the fifth portion is connected to the seventh end and the ninth end, The computing device of claim 5 , wherein the sixth portion is connected to the eighth end and the ninth other end.

7. The element portion includes: a first structure including a first substrate and a first quantum bit fixed to the first substrate; a second structure including a second substrate and a second quantum bit fixed to the second substrate; a first variable coupler including a third substrate, a first portion fixed to the third substrate, and a second portion fixed to the third substrate, the first portion being capacitively coupleable to the first quantum bit, and the second portion being capacitively coupleable to the second quantum bit; 13. A computing device comprising:

8. The first variable coupler comprises: a first Josephson junction, a second Josephson junction, and a third Josephson junction; the first Josephson junction includes a first end and a first other end; the second Josephson junction includes a second end and a second other end; the third Josephson junction includes a third end and a third other end, the first end is connected to the third end, The first other end is connected to the second other end, The second end is connected to the third other end, the first portion is connected to the first end and the third end; The computing device of claim 7 , wherein the second portion is connected to the second end and the third other end.

9. the first structure further includes a first conductive portion fixed to the first base, the first conductive portion is capable of being capacitively coupled to the first quantum bit; the first conductive portion is electrically connected to the first portion, the second structure further includes a second conductive portion fixed to the second base, the second conductive portion is capable of being capacitively coupled to the second quantum bit; The computing device of claim 7 or 8, wherein the second conductive portion is electrically connected to the second portion.

10. the first structure further includes a first conductive portion fixed to the first base, the first conductive portion is capable of being capacitively coupled to the first quantum bit; the first conductive portion is capable of being capacitively coupled to the first portion; the second structure further includes a second conductive portion fixed to the second base, the second conductive portion is capable of being capacitively coupled to the second quantum bit; The computing device of claim 7 or 8, wherein the second conductive portion is capacitively coupleable to the second portion.

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