Semiconductor device

Abstract

To provide a semiconductor device with reduced power consumption that can perform a product-sum operation.SOLUTION: A semiconductor device includes first and second circuits, and the second circuit includes first and second switches, a current / voltage conversion circuit, and a first transistor. The first circuit is electrically connected to a first terminal of the second circuit. A first terminal of the first switch is electrically connected to the first terminal of the second circuit. A second terminal of the first switch is electrically connected to an input terminal of the current / voltage conversion circuit. An output terminal of the current / voltage conversion circuit is electrically connected to a first terminal of the first transistor. A second terminal of the first transistor is electrically connected to a first terminal of the second switch. A second terminal of the second switch is electrically connected to a second terminal of the second circuit. The first circuit has a function of retaining a plurality of pieces of first data and a function of making a current in an amount responsive to the sum of products of the plurality of pieces of first data and a plurality of pieces of second data flow to the first terminal of the second circuit when the plurality of pieces of second data are input to the first circuit.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification relates to an object, an operation method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, examples of the technical field of one embodiment of the present invention disclosed in this specification more specifically include a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a power storage device, an imaging device, a memory device, a signal processing device, a sensor, a processor, an electronic device, a system, a driving method thereof, a manufacturing method thereof, or an inspection method thereof. [Background technology]

[0003] Currently, the development of integrated circuits that mimic the mechanisms of the human brain is actively progressing. Such integrated circuits incorporate the mechanisms of the brain as electronic circuits, and have circuits that correspond to the "neurons" and "synapses" of the human brain. For this reason, such integrated circuits are sometimes called "neuromorphic," "brain-morphic," "brain-inspired," etc. Such integrated circuits have a non-von Neumann architecture, and are expected to perform parallel processing with extremely low power consumption compared to the von Neumann architecture, which consumes more power as the processing speed increases.

[0004] An information processing model that mimics a neural network with "neurons" and "synapses" is called an artificial neural network (ANN). By using an artificial neural network, it is possible to make inferences with an accuracy comparable to or even exceeding that of humans. In an artificial neural network, the main operation is the weighted sum of neuron outputs, i.e., the product-sum operation.

[0005] An invention using a memory cell using an OS transistor as a circuit for performing product-sum operations is disclosed in, for example, Patent Document 1. An OS transistor (sometimes referred to as an oxide semiconductor transistor) is a transistor having a metal oxide semiconductor in a channel formation region, and has been reported to have an extremely small off-state current (for example, Non-Patent Documents 1 and 2). In addition, various semiconductor devices using OS transistors have been manufactured (for example, Non-Patent Documents 3 and 4). A manufacturing process for an OS transistor can be incorporated into a conventional CMOS process for Si transistors, and the OS transistor can be stacked on the Si transistor (for example, Non-Patent Document 4). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2017-168099 A [Non-patent literature]

[0007] [Non-Patent Document 1] S. Yamazaki et al., “Properties of crystalline In-Ga-Zn-oxide semiconductor and its transistor characteristics,” Jpn.J.Appl.Phys.,vol.53,04ED18(2014). [Non-Patent Document 2] K. Kato et al., “Evaluation of Off-State Current Characteristics of Transistor Using Oxide Semiconductor Material, Indium-Gallium-Zinc Oxide,” Jpn.J.Appl.Phys., vol. 51, 021201 (2012). [Non-Patent Document 3] S. Amano et al., “Low Power LC Display Using In-Ga-Zn-Oxide TFTs Based on Variable Frame Frequency,” SID Symp. Dig. Papers, vol. 41, pp. 626-629 (2010). [Non-Patent Document 4] T. Ishizu et al., “Embedded Oxide Semiconductor Memories: A Key Enabler for Low-Power ULSI,” ECS Tran., vol. 79, pp. 149-156 (2017). Summary of the Invention [Problem to be solved by the invention]

[0008] When a multiply-and-accumulate operation is performed in a digital circuit, a digital multiplier circuit multiplies the digital data (multiplier data) that is the multiplier by the digital data (multiplicand data) that is the multiplicand. Then, a digital adder circuit adds the digital data (product data) obtained by the multiplication, and obtains digital data (product-and-accumulate data) as the result of the multiply-and-accumulate operation. It is preferable that the digital multiplier circuit and the digital adder circuit have specifications that can handle multi-bit operations. However, in this case, the circuit scale of each of the digital multiplier circuit and the digital adder circuit may become large, which may lead to an increase in the circuit area of ​​the entire operation circuit and an increase in power consumption.

[0009] In addition, in the artificial neural network, in addition to the sum-of-products operation, the activation function is operated. If the activation function is operated by a digital circuit, as described above, the circuit area of ​​the entire operation circuit may increase and the power consumption may increase. In addition, if the sum-of-products operation is performed by an analog circuit, instead of a digital multiplication circuit and a digital addition circuit, the operation result output by the analog circuit becomes an analog signal, so that the operation result needs to be converted from an analog signal to a digital signal in order to input it to a digital circuit that operates the activation function. Furthermore, since the digital circuit outputs the operation result of the activation function as a digital signal, in order to perform the sum-of-products operation again using the operation result, the digital signal of the operation result needs to be converted to an analog signal in order to input it to the analog circuit. In particular, in the artificial neural network, the sum-of-products operation and the activation function are repeatedly performed, so that in a circuit that combines analog and digital circuits, the conversion between digital and analog signals is also frequently performed. As a result, the power consumption of the circuit that converts between digital and analog signals may also increase.

[0010] An object of one embodiment of the present invention is to provide a semiconductor device capable of calculating an activation function. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.

[0011] Another object of one embodiment of the present invention is to provide a novel semiconductor device or the like. Another object of one embodiment of the present invention is to provide an electronic device including the semiconductor device.

[0012] The problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. The other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. One embodiment of the present invention solves at least one of the problems listed above and other problems. One embodiment of the present invention does not need to solve all of the problems listed above and other problems. [Means for solving the problem]

[0013] (1) One embodiment of the present invention is a semiconductor device including a first circuit and a second circuit, in which the second circuit includes a first switch, a second switch, a current-voltage conversion circuit, and a first transistor. The first circuit is electrically connected to a first terminal of the second circuit, and the first terminal of the second circuit is electrically connected to the first terminal of the first switch, so that the first circuit is electrically connected to the first terminal of the first switch. The second terminal of the first switch is electrically connected to an input terminal of the current-voltage conversion circuit. The output terminal of the current-voltage conversion circuit is electrically connected to the first terminal of the first transistor, and the second terminal of the first transistor is electrically connected to the first terminal of the second switch. The first circuit outputs a plurality of first data W1 to W2. m (m is an integer of 1 or more) and a function of storing a plurality of second data X1 to X m is input, a current according to the value of formula (A1) flows to the first terminal of the second circuit. The current-voltage conversion circuit has a function of outputting a first potential according to the current input to the input terminal of the current-voltage conversion circuit to the output terminal of the current-voltage conversion circuit. The first transistor has a function of outputting the first potential from the second terminal of the first transistor when the first potential is equal to or greater than the sum of the potential of the gate of the first transistor and a threshold voltage of the first transistor, and a function of outputting the potential of the sum from the second terminal of the first transistor when the first potential is smaller than the sum.

[0014]

number

[0015] (2) Alternatively, in the above-mentioned (1), according to one aspect of the present invention, the current-voltage conversion circuit may include an operational amplifier and a load. In particular, it is preferable that an inverting input terminal of the operational amplifier is electrically connected to a first terminal of the current-voltage conversion circuit and a first terminal of the load, and an output terminal of the operational amplifier is electrically connected to a second terminal of the load.

[0016] (3) Alternatively, in one embodiment of the present invention, in the above-mentioned configuration (2), the load may include any one of a resistor, a diode, and a transistor.

[0017] (4) Alternatively, one aspect of the present invention may be configured such that the semiconductor device according to any one of (1) to (3) above includes a third circuit including a current mirror circuit, and the first circuit includes a first cell, a second cell, a first wiring, a second wiring, and a third wiring, the first cell includes a first capacitance, and the second cell includes a second capacitance. Specifically, the first wiring is electrically connected to the first cell, a first terminal of the second circuit, and the third circuit, the second wiring is electrically connected to the second cell and the third circuit, and the third wiring is electrically connected to the first terminal of the first capacitance and the first terminal of the second capacitance. The first cell has a function of holding a first potential at the second terminal of the first capacitance and a function of flowing a current amount according to the first potential to the first wiring. The second cell has a function of holding a second potential at the second terminal of the second capacitance and a function of flowing a current amount according to the second potential to the second wiring. The current mirror circuit also has a function of causing the amount of current flowing through the second wiring to flow through the first wiring. One of the plurality of first data is data corresponding to a potential difference between the first potential and the second potential. A potential corresponding to one of the plurality of second data is input to the third wiring.

[0018] (5) Alternatively, in one aspect of the present invention, in any one of the above (1) to (4), the first cell may have a second transistor and a third transistor, and the second cell may have a fourth transistor and a fifth transistor. Specifically, a first terminal of the second transistor is electrically connected to a second terminal of the first capacitance and a gate of the third transistor, a first terminal of the third transistor is electrically connected to a first wiring, a first terminal of the fourth transistor is electrically connected to a second terminal of the second capacitance and a gate of the fifth transistor, and a first terminal of the fifth transistor is electrically connected to a second wiring.

[0019] (6) Another embodiment of the present invention is an electronic device including the semiconductor device according to any one of (1) to (5) above and a housing. The semiconductor device performs a multiply-and-accumulate operation and a ReLU function operation.

[0020] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package or the like are examples of semiconductor devices. Also, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. are themselves semiconductor devices and may have semiconductor devices.

[0021] In addition, when it is stated in this specification that X and Y are connected, the following cases are also disclosed in this specification: when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. Therefore, it is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, and it is also disclosed in a figure or text other than the connection relationship shown in the figure or text. X and Y are objects (for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc.).

[0022] As an example of a case where X and Y are electrically connected, one or more elements (e.g., a switch, a transistor, a capacitive element, an inductor, a resistive element, a diode, a display device, a light-emitting device, a load, etc.) that enable the electrical connection between X and Y can be connected between X and Y. The switch has a function of controlling on / off. In other words, the switch has a function of being in a conductive state (on state) or a non-conductive state (off state) and controls whether or not a current flows.

[0023] As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (digital-analog conversion circuits, analog-digital conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boosting circuits, step-down circuits, etc.), level shifter circuits that change the potential level of a signal, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that can increase the signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, if a signal output from X is transmitted to Y, X and Y are considered to be functionally connected.

[0024] In addition, when it is explicitly stated that X and Y are electrically connected, this includes the case where X and Y are electrically connected (i.e., the case where X and Y are connected with another element or circuit between them) and the case where X and Y are directly connected (i.e., the case where X and Y are connected without having another element or circuit between them).

[0025] Also, for example, it can be expressed as "X, Y, and the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y." Or, it can be expressed as "The source (or first terminal, etc.) of the transistor is electrically connected to X, the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as "X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are provided in this connection order." By using expressions similar to these examples to specify the order of connections in a circuit configuration, the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor can be distinguished and the technical scope can be determined. Note that these expressions are merely examples and are not limited to these expressions. Here, X and Y are objects (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc.).

[0026] In addition, even when components that are independent on a circuit diagram are shown as being electrically connected to each other, one component may have the functions of multiple components. For example, when a part of a wiring also functions as an electrode, one conductive film has both the functions of a wiring and an electrode. Therefore, the term "electrical connection" in this specification also includes such a case where one conductive film has the functions of multiple components.

[0027] In addition, in this specification, the term "resistance element" may be, for example, a circuit element or wiring having a resistance value higher than 0Ω. Therefore, in this specification, the term "resistance element" includes wiring having a resistance value, a transistor in which a current flows between the source and drain, a diode, a coil, and the like. Therefore, the term "resistance element" can be rephrased as "resistance", "load", "region having a resistance value", and the like, and conversely, the terms "resistance", "load", and "region having a resistance value" can be rephrased as "resistance element". The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. In addition, for example, 1 Ω or more and 1×10 9 It may be set to Ω or less.

[0028] In addition, in this specification, the term "capacitive element" may refer to, for example, a circuit element having a capacitance value higher than 0F, a region of a wiring having a capacitance value, a parasitic capacitance, a gate capacitance of a transistor, and the like. Therefore, in this specification, the term includes a parasitic capacitance that appears between wirings, a gate capacitance that appears between one of the source or drain of a transistor and the gate, and the like. In addition, the terms "capacitive element", "parasitic capacitance", "gate capacitance", and the like can be rephrased as "capacitance", and conversely, the term "capacitance" can be rephrased as "capacitive element", "parasitic capacitance", "gate capacitance", and the like. In addition, the term "pair of electrodes" in "capacitance" can be rephrased as "pair of conductors", "pair of conductive regions", "pair of regions", and the like. The value of the electrostatic capacitance can be, for example, 0.05 fF or more and 10 pF or less. In addition, it may be, for example, 1 pF or more and 10 μF or less.

[0029] In addition, in this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conductive state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals becomes a source and the other becomes a drain depending on the conductivity type (n-channel type, p-channel type) of the transistor and the level of the potential applied to the three terminals of the transistor. For this reason, in this specification, the terms source and drain can be replaced. In addition, in this specification, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or the first electrode or the first terminal) and "the other of the source or drain" (or the second electrode or the second terminal) are used. Note that, depending on the structure of the transistor, a backgate may be included in addition to the above-mentioned three terminals. In this case, in this specification, one of the gate or the backgate of the transistor may be referred to as the first gate, and the other of the gate or the backgate of the transistor may be referred to as the second gate. Furthermore, in the same transistor, the terms "gate" and "backgate" may be interchangeable. Furthermore, when a transistor has three or more gates, in this specification and the like, the respective gates may be referred to as a first gate, a second gate, a third gate, and so on.

[0030] In this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on a circuit configuration, a device structure, etc. Also, a terminal, a wiring, etc. can be referred to as a node.

[0031] In addition, in this specification and the like, "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to a potential difference from a reference potential, and if the reference potential is the ground potential (earth potential), for example, "voltage" can be interchanged as "potential." Note that ground potential does not necessarily mean 0V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also change.

[0032] In addition, in this specification and the like, the terms "high-level potential" and "low-level potential" do not mean specific potentials. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials provided by both wirings do not have to be equal to each other.

[0033] "Current" refers to the phenomenon of charge transfer (electrical conduction). For example, the statement "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) accompanying the movement of carriers. The carriers referred to here include electrons, holes, anions, cations, complex ions, etc., and the carriers differ depending on the system through which the current flows (for example, semiconductors, metals, electrolytes, vacuum, etc.). In addition, the "direction of current" in wiring, etc. is the direction in which positive carriers move, and is described as a positive current amount. In other words, the direction in which negative carriers move is the opposite direction to the direction of current, and is expressed as a negative current amount. Therefore, in this specification, etc., unless otherwise specified regarding the positive and negative (or current direction) of the current, a statement such as "current flows from element A to element B" can be rephrased as "current flows from element B to element A" etc. Furthermore, statements such as "current is input to element A" can be rephrased as "current is output from element A" or the like.

[0034] In addition, in this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion of components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. Also, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0035] In addition, in this specification, the terms indicating the arrangement, such as "above" and "below", may be used for convenience in order to explain the positional relationship between the components with reference to the drawings. Furthermore, the positional relationship between the components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing shown by 180 degrees.

[0036] In addition, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0037] In addition, in this specification and the like, the terms "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be changed to the term "conductive film". Or, for example, the term "insulating film" may be changed to the term "insulating layer". Or, depending on the situation, it is possible to replace the terms "film" and "layer" with other terms without using them. For example, the terms "conductive layer" or "conductive film" may be changed to the term "conductor". Or, for example, the terms "insulating layer" and "insulating film" may be changed to the term "insulating body".

[0038] In addition, the terms "electrode", "wiring", "terminal" and the like in this specification do not limit the functions of these components. For example, "electrode" may be used as a part of "wiring", and vice versa. Furthermore, the terms "electrode" or "wiring" include cases where a plurality of "electrodes" or "wirings" are formed integrally. Furthermore, for example, "terminal" may be used as a part of "wiring" or "electrode", and vice versa. Furthermore, the term "terminal" includes cases where a plurality of "electrodes", "wiring", "terminals", and the like are formed integrally. Therefore, for example, an "electrode" can be a part of a "wiring" or "terminal", and for example, a "terminal" can be a part of a "wiring" or "electrode". Furthermore, the terms "electrode", "wiring", "terminal" and the like may be replaced with terms such as "region" depending on the circumstances.

[0039] In addition, in this specification and the like, terms such as "wiring", "signal line", and "power line" can be interchanged with each other depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line". For example, the term "wiring" may be changed to the term "power line". The opposite is also true, and terms such as "signal line" and "power line" may be changed to the term "wiring". The term "power line" may be changed to the term "signal line". The opposite is also true, and terms such as "signal line" may be changed to the term "power line". The term "potential" applied to the wiring may be changed to the term "signal" depending on the circumstances. The opposite is also true, and terms such as "signal" may be changed to the term "potential".

[0040] In this specification and the like, the impurity of a semiconductor refers to, for example, other than the main component constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The inclusion of an impurity may cause, for example, an increase in the defect level density of the semiconductor, a decrease in carrier mobility, a decrease in crystallinity, and the like. When the semiconductor is an oxide semiconductor, the impurity that changes the characteristics of the semiconductor may be, for example, a Group 1 element, a Group 2 element, a Group 13 element, a Group 14 element, a Group 15 element, transition metals other than the main component, and in particular, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, and the like. Specifically, when the semiconductor is a silicon layer, the impurity that changes the characteristics of the semiconductor may be, for example, a Group 1 element, a Group 2 element, a Group 13 element, a Group 15 element, oxygen, and the like, except for hydrogen.

[0041] In this specification and the like, a switch refers to a device that has a function of being in a conductive state (on state) or a non-conductive state (off state) and controlling whether or not a current flows. Alternatively, a switch refers to a device that has a function of selecting and switching a path through which a current flows. As an example, an electrical switch, a mechanical switch, or the like can be used. In other words, the switch is not limited to a specific one as long as it can control a current.

[0042] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), and logic circuits combining these. When a transistor is used as a switch, the "conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically short-circuited. Also, the "non-conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically cut off. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0043] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical system) technology. The switch has an electrode that can be moved mechanically, and the movement of the electrode controls whether the switch is conductive or non-conductive.

[0044] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes the case of -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case of 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less. Effect of the Invention

[0045] According to one embodiment of the present invention, a semiconductor device capable of calculating an activation function can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low power consumption can be provided.

[0046] According to one embodiment of the present invention, a novel semiconductor device or the like can be provided. According to one embodiment of the present invention, an electronic device including the semiconductor device can be provided.

[0047] The effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are effects not mentioned in this section, which will be described below. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. One embodiment of the present invention has at least one of the effects listed above and other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases. [Brief description of the drawings]

[0048] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a semiconductor device. [Diagram 2] FIG. 2 is a circuit diagram showing a configuration example of a circuit included in the semiconductor device. [Diagram 3] 3A and 3B are circuit diagrams showing configuration examples of circuits included in a semiconductor device. [Figure 4] FIG. 4 is a circuit diagram showing a configuration example of a circuit included in the semiconductor device. [Diagram 5] FIG. 5 is a circuit diagram showing a configuration example of a circuit included in the semiconductor device. [Figure 6] FIG. 6 is a timing chart showing an example of the operation of the semiconductor device. [Figure 7] FIG. 7 is a block diagram showing a configuration example of a semiconductor device. [Figure 8] FIG. 8 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 9] FIG. 9 is a block diagram showing a configuration example of a semiconductor device. [Figure 10]FIG. 10 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. [Figure 11] FIG. 11 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. [Figure 12] 12A and 12B are diagrams illustrating a hierarchical neural network. [Figure 13] FIG. 13 is a block diagram showing a configuration example of a semiconductor device. [Figure 14] FIG. 14 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 15] FIG. 15 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 16] 16A to 16C are schematic cross-sectional views illustrating configuration examples of transistors. [Figure 17] FIG. 17 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 18] FIG. 18 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 19] 19A and 19B are schematic cross-sectional views showing configuration examples of a transistor. [Figure 20] 20A and 20B are schematic cross-sectional views showing configuration examples of a transistor. [Figure 21] FIG. 21A is a top view showing a configuration example of a capacitive element, and FIGS. 21B and 21C are cross-sectional perspective views showing the configuration example of a capacitive element. [Figure 22] 22A is a top view showing a configuration example of a capacitive element, FIG. 22B is a cross-sectional view showing the configuration example of a capacitor, and FIG. 22C is a cross-sectional perspective view showing the configuration example of a capacitive element. [Figure 23] FIG. 23 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 24] FIG. 24 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Diagram 25] FIG. 25A is a diagram for explaining the classification of IGZO crystal structures, FIG. 25B is a diagram for explaining the XRD spectrum of crystalline IGZO, and FIG. 25C is a diagram for explaining the ultrafine electron beam diffraction pattern of crystalline IGZO. [Figure 26] FIG. 26A is a perspective view showing an example of a semiconductor wafer, FIG. 26B is a perspective view showing an example of a chip, and FIGS. 26C and 26D are perspective views showing examples of an electronic component. [Figure 27] 27A to 27F are perspective views of a package and a module that house an imaging device. [Figure 28] FIG. 28 is a perspective view illustrating an example of an electronic device. [Figure 29] 29A to 29C are perspective views showing an example of an electronic device. [Diagram 30] FIG. 30 is a circuit diagram showing the circuit configuration input to the circuit simulator. [Diagram 31] FIG. 31 is a graph showing the relationship between the output voltage and the input current, obtained by a circuit simulator. [Diagram 32] FIG. 32A is a graph showing the relationship between time and the amount of current, and FIG. 32B is a graph showing the change in output voltage over time obtained by a circuit simulator. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0049] In an artificial neural network (hereafter referred to as a neural network), the strength of synapses can be changed by providing existing information to the neural network. This process of providing existing information to a neural network and determining the strength of connections is sometimes called "learning."

[0050] In addition, by providing some information to a neural network that has undergone "learning" (with connection strengths determined), it is possible for the network to output new information based on the connection strengths. In this way, the process of outputting new information based on given information and connection strengths in a neural network is sometimes called "inference" or "cognition."

[0051] Examples of neural network models include the Hopfield type and hierarchical type. In particular, a neural network with a multi-layer structure is sometimes called a "deep neural network" (DNN), and machine learning using a deep neural network is sometimes called "deep learning."

[0052] In this specification and the like, a metal oxide is an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OSs), and the like. For example, when a metal oxide is used in an active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide can constitute a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. In addition, when an OS transistor is described, it can be rephrased as a transistor having a metal oxide or an oxide semiconductor.

[0053] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0054] In this specification and the like, the configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be appropriately combined with each other.

[0055] In addition, the content (or a part of the content) described in one embodiment may be applied, combined, or replaced with at least one of another content (or a part of the content) described in that embodiment and the content (or a part of the content) described in one or more other embodiments.

[0056] The contents described in the embodiments refer to contents described in each embodiment using various figures or contents described using text in the specification.

[0057] Furthermore, a figure (or a part thereof) described in one embodiment can be combined with another part of that figure, with another figure (or a part thereof) described in that embodiment, and / or with at least one figure (or a part thereof) described in one or more other embodiments to form even more figures.

[0058] The embodiments described in this specification will be described with reference to the drawings. However, it is possible to implement the embodiments in many different ways, and it is easily understood by those skilled in the art that the form and details can be changed in various ways without departing from the spirit and scope of the invention. Therefore, the present invention is not interpreted as being limited to the description of the embodiments. In the configuration of the invention of the embodiments, the same reference numerals are used in common between different drawings for the same parts or parts having similar functions, and repeated explanations may be omitted. In addition, in perspective views and the like, the description of some components may be omitted in order to ensure the clarity of the drawings.

[0059] In this specification, when the same symbol is used for multiple elements, particularly when it is necessary to distinguish between them, an identification symbol such as “_1”, "[n]”, "[m,n]”, etc. may be added to the symbol.

[0060] In addition, in the drawings of this specification, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing deviations.

[0061] (Embodiment 1) In this embodiment, an example of an arithmetic circuit which is a semiconductor device of one embodiment of the present invention will be described.

[0062] <Arithmetic circuit configuration example 1> The arithmetic circuit MAC1 shown in Fig. 1 shows an example of the configuration of an arithmetic circuit capable of performing a multiply-and-accumulate operation and a function operation. The arithmetic circuit MAC1 is a circuit that performs a multiply-and-accumulate operation of a plurality of first data stored in a plurality of memory cells described later and a plurality of second data inputted, and performs an activation function operation using the result of the multiply-and-accumulate operation. Note that the plurality of first data and the plurality of second data can be, for example, analog data or multi-valued data (discrete data).

[0063] The arithmetic circuit MAC1 includes, for example, a memory cell array CA, a circuit CMS, a circuit WDD, a circuit XLD, a circuit WLD, and a circuit ACTV.

[0064] The memory cell array CA includes memory cells AM[1,1] to AM[m,n] and memory cells AMr[1] to AMr[m]. In the memory cell array CA, the memory cells AM[1,1] to AM[m,n] are arranged in a matrix of m rows and n columns (m is an integer equal to or greater than 1, and n is an integer equal to or greater than 1). The memory cells AMr[1] to AMr[m] are arranged in the n+1th column of the memory cell array CA.

[0065] The memory cells AM[1,1] to AM[m,n] have a function of storing first data, and the memory cells AMr[1] to AMr[m] have a function of storing reference data required for performing a multiply-and-accumulate operation. Note that the reference data can be analog data or multi-valued data (discrete data) like the first data and the second data.

[0066] The memory cell AM[1,1] is electrically connected to the wiring WD[1], the wiring BL[1], the wiring WL[1], and the wiring XL[1]. The memory cell AM[m,1] is electrically connected to the wiring WD[1], the wiring BL[1], the wiring WL[m], and the wiring XL[m]. The memory cell AM[1,n] is electrically connected to the wiring WD[n], the wiring BL[n], the wiring WL[1], and the wiring XL[1]. The memory cell AM[m,n] is electrically connected to the wiring WD[n], the wiring BL[n], the wiring WL[m], and the wiring XL[m]. The memory cell AMr[1] is electrically connected to the wiring WDr, the wiring BLr, the wiring WL[1], and the wiring XL[1]. In addition, the memory cell AMr[m] is electrically connected to the wiring WDr, the wiring BLr, the wiring WL[m], and the wiring XL[m].

[0067] An example of a detailed circuit configuration of each of the memory cells AM[1,1] to AM[m,n] and the memory cells AMr[1] to AMr[m] will be described later.

[0068] For example, the circuit CMS is electrically connected to wirings BL[1] to BL[n] and a wiring BLr. The circuit CMS has a function of supplying a current from the wiring BL[1] to each of the memory cells AM[1,1] to AM[m,1] and a function of setting the current to a constant current. The circuit CMS also has a function of supplying a current from the wiring BL[n] to each of the memory cells AM[1,n] to AM[m,n] and a function of setting the current to a constant current. The circuit CMS also has a function of supplying a current from the wiring BLr to each of the memory cells AMr[1] to AMr[m], a function of supplying a current to the wirings BL[1] to BL[n] in an amount substantially equal to the current, and a function of setting the current to a constant current.

[0069] As an example, the circuit WDD is electrically connected to the wirings WD[1] to WD[n] and the wiring WDr. The circuit WDD has a function of transmitting data to be stored in each memory cell of the memory cell array CA. For example, the circuit WDD can transmit first data as the data to the wirings WD[1] to WD[n] and also transmit reference data as the data to the wiring WDr.

[0070] As an example, the circuit WLD is electrically connected to the wirings WL[1] to WL[m]. When writing data to a memory cell in the memory cell array CA, the circuit WLD has a function of selecting a memory cell to which data is to be written. As a specific example, when writing data to a memory cell in the i-th row (i is an integer between 1 and m) of the memory cell array CA, the circuit WLD applies a high-level potential to the wiring WL[i] and applies a low-level potential to the wirings WL[1] to WL[m] other than the wiring WL[i], thereby selecting the memory cells AM[i,1] to AM[i,n] and the memory cell AMr[i] to which data is to be written.

[0071] For example, the circuit XLD is electrically connected to the wirings XL[1] to XL[m]. The circuit XLD has a function of transmitting second data for multiplication with the first data to each memory cell in the memory cell array CA. Specifically, for example, the circuit XLD can apply a potential according to the second data to the wirings XL[1] to XL[m].

[0072] For example, the circuit ACTV is electrically connected to the wirings BL[1] to BL[n], the wiring BLr, and the wirings NIL[1] to NIL[n]. The circuit ACTV has a function of inputting a predetermined voltage to the wirings BL[1] to BL[n] and the wiring BLr. The circuit ACTV also has a function of outputting a voltage according to the amount of current flowing from the wiring BL[1] to the circuit ACTV, a function of performing a calculation according to a predefined function system using the voltage, and a function of outputting the result of the calculation of the function to the wiring NIL[1]. The circuit ACTV also has a function of converting the amount of current flowing from the wiring BL[n] to the circuit ACTV into a voltage or the like, a function of performing a calculation according to a predefined function system using the voltage, and a function of outputting the result of the calculation of the function to the wiring NIL[n].

[0073] In particular, the predefined function system in the circuit ACTV can be, for example, a sigmoid function, a tanh function, a softmax function, a ReLU function (ramp function), a threshold function, etc. Furthermore, these functions can be applied, for example, as activation functions in a neural network.

[0074] <<Example of ACTV circuit configuration>> Next, a configuration example of a circuit ACTV that can be applied to the arithmetic circuit MAC1 will be described.

[0075] 2 is a circuit diagram showing a configuration example of the circuit ACTV. The circuit ACTV includes, as an example, transistors Tr51[1] to Tr51[n], circuits IVC[1] to IVC[n], switches SW4A[1] to SW4A[n], switches SW4B[1] to SW4B[n], switches SW5[1] to SW5[n], and a switch SW5r.

[0076] For example, a p-channel transistor can be used as each of the transistors Tr51[1] to Tr51[n].

[0077] In addition, it is preferable that the transistors Tr51[1] to Tr51[n] have the same electrical characteristics. To achieve this, it is preferable that the transistors Tr51[1] to Tr51[n] have the same size (e.g., channel length, channel width, transistor configuration, etc.). By making the sizes of the transistors Tr51[1] to Tr51[n] equal to each other, the transistors Tr51[1] to Tr51[n] can perform approximately the same operation under the same conditions. The same conditions here refer to, for example, the potentials of the sources, drains, gates, etc. of the transistors Tr51[1] to Tr51[n].

[0078] In addition, unless otherwise specified, the transistors Tr51[1] to Tr51[n] are assumed to operate in the saturation region when on, i.e., when a voltage within a range in which the transistors operate in the saturation region is appropriately input to the gate, source, and drain of each of the above-described transistors.

[0079] It is preferable that each of the transistors Tr51[1] to Tr51[n] is a transistor including silicon in a channel formation region (hereinafter, referred to as a Si transistor). Silicon can be, for example, amorphous silicon (sometimes referred to as hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, or single crystal silicon.

[0080] Note that, instead of p-channel transistors, n-channel transistors may be used as each of the transistors Tr51[1] to Tr51[n]. Furthermore, OS transistors may be used as each of the transistors Tr51[1] to Tr51[n].

[0081] In addition, for example, electrical switches such as analog switches and transistors can be applied to each of the switches SW4A[1] to SW4A[n], the switches SW4B[1] to SW4B[n], the switches SW5[1] to SW5[n], and the switch SW5r. Alternatively, for example, mechanical switches can be applied to each of the switches SW4A[1] to SW4A[n], the switches SW4B[1] to SW4B[n], the switches SW5[1] to SW5[n], and the switch SW5r. In addition, when transistors are applied to the switches SW4A[1] to SW4A[n], the switches SW4B[1] to SW4B[n], the switches SW5[1] to SW5[n], and the switch SW5r, the transistors can be OS transistors or Si transistors.

[0082] In this embodiment, each of switches SW4A[1] to SW4A[n], switches SW4B[1] to SW4B[n], switches SW5[1] to SW5[n], and switch SW5r is turned on when a high-level potential is input to the control terminal, and turned off when a low-level potential is input to the control terminal.

[0083] The first terminal of the switch SW4A[1] is electrically connected to the first terminal of the switch SW5[1] and the wiring BL[1], and the second terminal of the switch SW4A[1] is electrically connected to the first terminal of the circuit IVC[1]. In addition, the wiring BL[1] is electrically connected to one of the first terminals of the circuit ACTV, for example, so that the above "The first terminal of the switch SW4A[1] is electrically connected to the first terminal of the switch SW5[1] and the wiring BL[1]" can be rephrased as "The first terminal of the switch SW4A[1] is electrically connected to the first terminal of the switch SW5[1] and one of the first terminals of the circuit ACTV". The second terminal of the circuit IVC[1] is electrically connected to the first terminal of the transistor Tr51[1], and the second terminal of the transistor Tr51[1] is electrically connected to the first terminal of the switch SW4B[1]. The second terminal of the switch SW4B[1] is electrically connected to the wiring NIL[1]. In addition, as an example, the wiring NIL[1] is electrically connected to one of the multiple second terminals of the circuit ACTV, so the above statement "The second terminal of the switch SW4B[1] is electrically connected to the wiring NIL[1]" can be rephrased as "The second terminal of the switch SW4B[1] is electrically connected to one of the multiple second terminals of the circuit ACTV."

[0084] Similarly, the first terminal of the switch SW4A[n] is electrically connected to the first terminal of the switch SW5[n] and the wiring BL[n], and the second terminal of the switch SW4A[n] is electrically connected to the first terminal of the circuit IVC[n]. In addition, the wiring BL[n] is electrically connected to one of the first terminals of the circuit ACTV, for example, so that the above "the first terminal of the switch SW4A[n] is electrically connected to the first terminal of the switch SW5[n] and the wiring BL[n]" can be rephrased as "the first terminal of the switch SW4A[n] is electrically connected to the first terminal of the switch SW5[n] and one of the first terminals of the circuit ACTV". The second terminal of the circuit IVC[n] is electrically connected to the first terminal of the transistor Tr51[n], and the second terminal of the transistor Tr51[n] is electrically connected to the first terminal of the switch SW4B[n]. The second terminal of the switch SW4B[n] is electrically connected to the wiring NIL[n]. Furthermore, as an example, the wiring NIL[n] is electrically connected to one of the multiple second terminals of the circuit ACTV, so the above statement "The second terminal of the switch SW4B[n] is electrically connected to the wiring NIL[n]" can be rephrased as "The second terminal of the switch SW4B[n] is electrically connected to one of the multiple second terminals of the circuit ACTV."

[0085] In addition, second terminals of the switches SW5[1] to SW5[n] are electrically connected to the wiring VSL, and control terminals of the switches SW5[1] to SW5[n] are electrically connected to the wiring WE. Gates of the transistors Tr51[1] to Tr51[n] are electrically connected to the wiring VBA. Control terminals of the switches SW4A[1] to SW4A[n] and the switches SW4B[1] to SW4B[n] are electrically connected to the wiring SL4.

[0086] Moreover, a first terminal of the switch SW5r is electrically connected to the line BLr, a second terminal of the switch SW5r is electrically connected to the line VSL, and a control terminal of the switch SW5r is electrically connected to the line WE.

[0087] Each of the circuits IVC[1] to IVC[n] has a function of outputting a voltage corresponding to the amount of current input to the first terminal to the second terminal. That is, the circuits IVC[1] to IVC[n] have a function as a current-voltage conversion circuit.

[0088] The line VSL functions as, for example, a line that applies a constant voltage, which may be, for example, a low-level potential or a ground potential.

[0089] For example, the wiring WE functions as a wiring that supplies a voltage for switching the switches SW5[1] to SW5[n] and the switch SW5r between a conductive state and a non-conductive state.

[0090] For example, the wiring SL4 functions as a wiring that supplies a voltage for switching the switches SW4[1] to SW4[n] between a conductive state and a non-conductive state.

[0091] The wiring VBA functions, for example, as a wiring that applies a constant voltage.

[0092] Each of the transistors Tr51[1] to Tr51[n] has a function of controlling the voltage between the first terminal and the second terminal of each of the transistors Tr51[1] to Tr51[n]. Specifically, each of the transistors Tr51[1] to Tr51[n] has a function of limiting the potential transferred from the second terminal of each of the circuits IVC[1] to IVC[n] to the second terminal of each of the transistors Tr51[1] to Tr51[n]. At this time, the voltage between the first terminal and the second terminal of each of the transistors Tr51[1] to Tr51[n] is determined by a constant voltage provided by the wiring VBA and the potential of each of the first terminals of the transistors Tr51[1] to Tr51[n].

[0093] Next, a description will be given of an example of a circuit configuration that can be applied to the circuits IVC[1] to IVC[n]. A circuit ACTV in FIG. 3A shows a specific circuit configuration of the circuits IVC[1] to IVC[n].

[0094] 3A, the circuit IVC[1] includes a resistor RE[1] and an operational amplifier OP[1], and the circuit IVC[n] includes a resistor RE[n] and an operational amplifier OP[n].

[0095] In the circuit IVC[1], the inverting input terminal of the operational amplifier OP[1] is electrically connected to the first terminal of the circuit IVC[1] and the first terminal of the resistor RE[1]. The non-inverting input terminal of the operational amplifier OP[1] is electrically connected to the wiring VdL. The output terminal of the operational amplifier OP[1] is electrically connected to the second terminal of the resistor RE[1] and the second terminal of the circuit IVC[1].

[0096] In the circuit IVC[n], the inverting input terminal of the operational amplifier OP[n] is electrically connected to the first terminal of the circuit IVC[n] and the first terminal of the resistor RE[n]. The non-inverting input terminal of the operational amplifier OP[n] is electrically connected to the wiring VdL. The output terminal of the operational amplifier OP[n] is electrically connected to the second terminal of the resistor RE[n] and the second terminal of the circuit IVC[n].

[0097] The line VdL functions as, for example, a line that applies a constant voltage, which may be, for example, a ground potential or a low-level potential.

[0098] That is, in the circuit ACTV of FIG. 3A, n current-voltage conversion circuits are configured by the resistors RE[1] through RE[n], the operational amplifiers OP[1] through OP[n], and the wiring VdL.

[0099] In addition, examples of circuit configurations that can be applied to the circuits IVC[1] to IVC[n] are not limited to the circuits IVC[1] to IVC[n] shown in Fig. 3A. For example, as shown in the circuit ACTV shown in Fig. 3B, the resistors RE[1] to RE[n] provided in the circuits IVC[1] to IVC[n] of Fig. 3A may be changed to loads LE[1] to LE[n], respectively. For example, diodes, transistors, etc. may be used as the loads LE[1] to LE[n]. Even when these circuit elements are used, n current-voltage conversion circuits can be configured by the loads LE[1] to LE[n] and the operational amplifiers OP[1] to OP[n].

[0100] Next, a specific example of the operation of the circuit ACTV will be described. Note that, as an example, the operation of the circuit ACTV shown in FIG. 3A will be described.

[0101] In the circuit ACTV, a high-level potential is input to the wiring WE and a high-level potential is input to the wiring SL4, so that the switches SW5[1] to SW5[n], SW4A[1] to SW4A[n], and SW4B[1] to SW4B[n] are turned on. Therefore, the potential provided by the wiring VSL is applied to the first terminals of the circuits IVC[1] to IVC[n].

[0102] The potential applied by the wiring VSL can be, for example, an initialization potential in each of the circuits IVC[1] to IVC[n]. Therefore, a potential corresponding to the initialization potential is output from the second terminal of each of the circuits IVC[1] to IVC[n]. At this time, when a current flows from the wiring BL[j] (j is an integer between 1 and n) to the circuit ACTV, the current flows to the wiring VSL side.

[0103] In the circuit ACTV, a high-level potential is input to the wiring WE and a low-level potential is input to the wiring SL4, so that the switches SW5[1] to SW5[n] and SW5r are turned on and the switches SW4A[1] to SW4A[n] and SW4B[1] to SW4B[n] are turned off. At this time, the potential provided by the wiring VSL is applied to the wirings BL[1] to BL[n] and BLr.

[0104] In the circuit ACTV, a low-level potential is input to the wiring WE and a high-level potential is input to the wiring SL4, so that the switches SW5[1] to SW5[n] are turned off and the switches SW4A[1] to SW4A[n] and the switches SW4B[1] to SW4B[n] are turned on. As a result, the first terminals of the circuits IVC[1] to IVC[n] are electrically connected to the wirings BL[1] to BL[n].

[0105] At this time, a current I S The operational amplifier OP[j] included in the circuit IVC[j] is configured as a negative feedback via the resistor RE[j], so the resistance value of the resistor RE[j] is R, and the potential provided by the wiring VdL is V ref The potential of the second terminal of the circuit IVC[j] is V A [j], the potential V A [j] can be expressed by the following formula.

[0106]

number

[0107] In addition, the potential V A[j] is input to the first terminal of the transistor Tr51[j]. At this time, the potential output from the second terminal of the transistor Tr51[j] is the potential given by the wiring VBA, which is input to the gate of the transistor Tr51[j], and the potential V A [j] and V BIAS The threshold voltage of transistor Tr51[j] is V th The potential output from the second terminal of transistor Tr51[j] is V OUT [j], the potential V OUT [j] can be expressed by the following approximation:

[0108]

number

[0109] In addition, equation (1.2) is V A [j] is V BIAS +V th This holds true when V A [j] is V BIAS +V th This holds true when less than

[0110] From equations (1.2) and (1.3), the relationship between the potential input to the first terminal of transistor Tr51[i] and the potential output from the second terminal of transistor Tr51[i] can be regarded as the calculation of a ReLU function (ramp function).

[0111] The ReLU function can be treated as an activation function of a neuron included in a hierarchical neural network described in the embodiment 3. In other words, by using the circuit ACTV, it is possible to perform the calculation of the activation function in the hierarchical neural network.

[0112] <<Memory cell configuration example>> Next, a configuration example of the memory cells AM[1,1] to AM[m,n] and the memory cells AMr[1] to AMr[m] included in the memory cell array CA will be described.

[0113] 4 is a circuit diagram showing a configuration example of the memory cell array CA and the circuit CMS. The memory cell array CA and the circuit CMS have a function of calculating the sum of products of a plurality of first data and a plurality of second data.

[0114] In the memory cell array CA shown in FIG. 4, each of the memory cells AM[1,1] to AM[m,n] and the memory cells AMr[1] to AMr[m] includes a transistor Tr11, a transistor Tr12, and a capacitor C1.

[0115] The sizes of the transistors Tr11 included in the memory cells AM[1,1] to AM[m,n] and the memory cells AMr[1] to AMr[m] are preferably equal to each other. The sizes of the transistors Tr12 included in the memory cells AM[1,1] to AM[m,n] and the memory cells AMr[1] to AMr[m] are preferably equal to each other.

[0116] By making the sizes of the transistors equal to each other, the electrical characteristics of each transistor can be made almost equal. Therefore, by making the sizes of the transistors Tr11 included in each of the memory cells AM[1,1] to AM[m,n] and the memory cells AMr[1] to AMr[m] equal and making the sizes of the transistors Tr12 included in each of the memory cells AM[1,1] to AM[m,n] and the memory cells AMr[1] to AMr[m] equal, each of the memory cells AM[1,1] to AM[m,n] and the memory cells AMr[1] to AMr[m] can perform almost the same operation under the same conditions. The same conditions here refer to, for example, the potentials of the source, drain, gate, etc. of the transistor Tr11, the potentials of the source, drain, gate, etc. of the transistor Tr12, and the voltages input to each of the memory cells AM[1,1] to AM[m,n] and the memory cells AMr[1] to AMr[m].

[0117] Unless otherwise specified, the transistor Tr11 may function as a switching element. In other words, the transistor Tr11 may have a gate, source, and drain that are appropriately supplied with voltages within a range in which the transistor Tr11 operates as a switching element. The transistor Tr11 may operate in a saturation region when on, or may operate in both a linear region and a saturation region.

[0118] In addition, unless otherwise specified, the transistor Tr12 is assumed to operate in the saturation region when on, i.e., when a voltage within the range in which the transistors operate in the saturation region is appropriately input to the gate, source, and drain of each of the above-mentioned transistors.

[0119] Note that the transistor Tr11 is preferably an OS transistor. In addition, it is more preferable that the channel formation region of the transistor Tr11 contains an oxide containing at least one of indium, gallium, and zinc. Alternatively, the channel formation region of the transistor Tr11 may be an oxide containing at least one of indium, an element M (for example, the element M may be one or more elements selected from aluminum, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.), and zinc. It is more preferable that the transistor Tr11 has the structure of the transistor described in the fourth embodiment.

[0120] By using an OS transistor as the transistor Tr11, the leakage current of the transistor Tr11 can be suppressed, and therefore a multiply-and-accumulate circuit with high calculation accuracy can be realized. In addition, by using an OS transistor as the transistor Tr11, the leakage current from the retention node (for example, node N[1,1], node N[m,1], node N[1,n], node N[m,n], node Nr[1], node Nr[m], etc. described later) to the write word line (for example, wiring WD[1] to wiring WD[n], wiring WDr, etc.) when the transistor Tr11 is in a non-conductive state can be made very small. In other words, the number of refresh operations of the potential of the retention node can be reduced, and therefore the power consumption of the multiply-and-accumulate circuit can be reduced.

[0121] In addition, by using an OS transistor for the transistor Tr12, it can be manufactured simultaneously with the transistor Tr11, which may shorten the manufacturing process of the product-sum operation circuit. The transistor Tr12 may be a Si transistor instead of an OS transistor. Silicon may be, for example, amorphous silicon (sometimes called hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, single crystal silicon, or the like.

[0122] In FIG. 4, the back gates of the transistors Tr11 and Tr12 are illustrated, and the connection configuration of the back gates is not illustrated, but the electrical connection destination of the back gates can be determined at the design stage. For example, in a transistor having a back gate, the gate and the back gate may be electrically connected to increase the on-current of the transistor. That is, for example, the gate and the back gate of the transistor Tr11 may be electrically connected, or the gate and the back gate of the transistor Tr12 may be electrically connected. Also, for example, in a transistor having a back gate, in order to change the threshold voltage of the transistor or to reduce the off-current of the transistor, a wiring for electrically connecting the back gate of the transistor to an external circuit or the like may be provided, and a potential may be applied to the back gate of the transistor by the external circuit or the like.

[0123] 4 has a backgate, the semiconductor device of one embodiment of the present invention is not limited thereto. For example, the transistors Tr11 and Tr12 shown in FIG. 4 may have a structure without a backgate, that is, a single-gate transistor. Some of the transistors may have a backgate, and other transistors may have a structure without a backgate.

[0124] 4, the transistors Tr11 and Tr12 are n-channel transistors, but the semiconductor device of one embodiment of the present invention is not limited to this. For example, the transistors Tr11 and Tr12 may be partially or entirely replaced with p-channel transistors.

[0125] The above-described modifications of the transistor structures and polarities are not limited to the transistors Tr11 and Tr12, but also apply to, for example, transistors Tr33 and Tr34 described later, as well as transistors described elsewhere in the specification or shown in other drawings.

[0126] In each of the memory cells AM[1,1] to [m,n] and the memory cells AMr[1] to AMr[m], a first terminal of the transistor Tr11 is electrically connected to a gate of the transistor Tr12. A first terminal of the transistor Tr12 is electrically connected to a wiring VR. A first terminal of the capacitor C1 is electrically connected to the gate of the transistor Tr12.

[0127] In the memory cell AM[1,1], the second terminal of the transistor Tr11 is electrically connected to the wiring WD[1], and the gate of the transistor Tr11 is electrically connected to the wiring WL[1]. The second terminal of the transistor Tr12 is electrically connected to the wiring BL[1], and the second terminal of the capacitor C1 is electrically connected to the wiring XL[1]. In the memory cell AM[1,1], the electrical connection point between the first terminal of the transistor Tr11, the gate of the transistor Tr12, and the first terminal of the capacitor C1 is the node N[1,1].

[0128] In the memory cell AM[m,1], the second terminal of the transistor Tr11 is electrically connected to the wiring WD[1], and the gate of the transistor Tr11 is electrically connected to the wiring WL[m]. The second terminal of the transistor Tr12 is electrically connected to the wiring BL[1], and the second terminal of the capacitor C1 is electrically connected to the wiring XL[m]. In the memory cell AM[m,1], the electrical connection point between the first terminal of the transistor Tr11, the gate of the transistor Tr12, and the first terminal of the capacitor C1 is defined as a node N[m,1].

[0129] In the memory cell AM[1,n], the second terminal of the transistor Tr11 is electrically connected to the wiring WD[n], and the gate of the transistor Tr11 is electrically connected to the wiring WL[1]. The second terminal of the transistor Tr12 is electrically connected to the wiring BL[n], and the second terminal of the capacitor C1 is electrically connected to the wiring XL[1]. In the memory cell AM[1,n], the electrical connection point between the first terminal of the transistor Tr11, the gate of the transistor Tr12, and the first terminal of the capacitor C1 is the node N[1,n].

[0130] In the memory cell AM[m,n], the second terminal of the transistor Tr11 is electrically connected to the wiring WD[n], and the gate of the transistor Tr11 is electrically connected to the wiring WL[m]. The second terminal of the transistor Tr12 is electrically connected to the wiring BL[n], and the second terminal of the capacitor C1 is electrically connected to the wiring XL[m]. In the memory cell AM[m,n], the electrical connection point between the first terminal of the transistor Tr11, the gate of the transistor Tr12, and the first terminal of the capacitor C1 is defined as a node N[m,n].

[0131] In the memory cell AMr[1], the second terminal of the transistor Tr11 is electrically connected to the wiring WDr, and the gate of the transistor Tr11 is electrically connected to the wiring WL[1]. The second terminal of the transistor Tr12 is electrically connected to the wiring BLr, and the second terminal of the capacitor C1 is electrically connected to the wiring XL[1]. Note that in the memory cell AMr[1], the electrical connection point between the first terminal of the transistor Tr11, the gate of the transistor Tr12, and the first terminal of the capacitor C1 is defined as a node Nr[1]. In addition, the current flowing from the wiring BLr to the second terminal of the transistor Tr12 is defined as I AMr[1] Let us assume that.

[0132] In the memory cell AMr[m], the second terminal of the transistor Tr11 is electrically connected to the wiring WDr, and the gate of the transistor Tr11 is electrically connected to the wiring WL[m]. The second terminal of the transistor Tr12 is electrically connected to the wiring BLr, and the second terminal of the capacitor C1 is electrically connected to the wiring XL[m]. Note that in the memory cell AMr[m], the electrical connection point between the first terminal of the transistor Tr11, the gate of the transistor Tr12, and the first terminal of the capacitor C1 is defined as a node Nr[m]. In addition, the current flowing from the wiring BLr to the second terminal of the transistor Tr12 is defined as I AMr[2] Let us assume that.

[0133] The above-mentioned nodes N[1], N[m], Nr[1], and Nr[m] function as retention nodes for the respective memory cells.

[0134] The wiring VR is a wiring for passing a current between the first terminal and the second terminal of the transistor Tr12 of each of the memory cells AM[1,1] to AM[m,n] and the memory cells AMr[1] to AMr[m]. Therefore, the wiring VR functions as a wiring for applying a predetermined potential. Note that in this embodiment, the potential applied by the wiring VR can be, for example, a low-level potential, a ground potential, or a potential lower than the ground potential.

[0135] <<Example of Circuit CMS configuration>> Next, a configuration example of the circuit CMS will be described.

[0136] In FIG. 4, the circuit CMS includes circuits CS1[1] to CS1[n], circuits CS2[1] to CS2[n], a circuit CM, switches SW3[1] to SW3[n], switches SW7[1] to SW7[n], and a switch SW7r.

[0137] The control terminals of the switches SW3[1] to SW3[n] are electrically connected to a wiring SL3. The control terminals of the switches SW7[1] to SW7[n] and SW7r are electrically connected to a wiring SL7.

[0138] A first terminal of the switches SW7[1] to SW7[n] is electrically connected to the wirings BL[1] to BL[n], respectively. A first terminal of the switch SW7r is electrically connected to the wiring BLr.

[0139] The wiring SL3 functions as a wiring that supplies a voltage for switching the switches SW3[1] to SW3[n] between a conductive state and a non-conductive state, respectively. The wiring SL7 functions as a wiring that supplies a voltage for switching the switches SW7[1] to SW7[n] and SW7r between a conductive state and a non-conductive state, respectively.

[0140] Each of the circuits CS1[1] to CS1[n] functions as, for example, a current source circuit that supplies a constant current. In addition, each of the circuits CS1[1] to CS1[n] has a function of setting the amount of the constant current, which will be described in detail later.

[0141] Each of the circuits CS1[1] to CS1[n] includes a p-channel transistor Tr33, a capacitor C6, and a switch SW1.

[0142] The transistor Tr33 is preferably a Si transistor. The silicon contained in the channel formation region of the transistor Tr33 may be, for example, amorphous silicon (sometimes called hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, or single crystal silicon.

[0143] In addition, it is preferable that the transistors Tr33 included in each of the circuits CS1[1] to CS1[n] have the same electrical characteristics as each other. To achieve this, for example, it is preferable that the transistors Tr33 included in each of the circuits CS1[1] to CS1[n] have the same size as each other.

[0144] In addition, unless otherwise specified, the transistor Tr33 of each of the circuits CS1[1] to CS1[n] includes a case where the transistor Tr33 operates in the saturation region when on, i.e., a case where a voltage within a range where the transistor operates in the saturation region is appropriately input to the gate, source, and drain of each of the above-mentioned transistors.

[0145] In each of the circuits CS1[1] to CS1[n], a first terminal of the transistor Tr33 is electrically connected to the wiring VHE, a gate of the transistor Tr33 is electrically connected to a first terminal of the capacitor C6 and a first terminal of the switch SW1, and a second terminal of the transistor Tr33 is electrically connected to a second terminal of the switch SW1. The second terminal of the capacitor C6 is electrically connected to the wiring VHE. The control terminal of the switch SW1 is electrically connected to the wiring SL1.

[0146] In the circuit CS1[1], the second terminal of the transistor Tr33 and the second terminal of the switch SW1 are electrically connected to a first terminal of the switch SW3[1] and a second terminal of the switch SW7[1].

[0147] In the circuit CS1[n], the second terminal of the transistor Tr33 and the second terminal of the switch SW1 are electrically connected to a first terminal of the switch SW3[n] and a second terminal of the switch SW7[n].

[0148] The wiring VHE functions as a wiring for applying a constant voltage, which is preferably, for example, a high-level potential.

[0149] The wiring SL1 functions as a wiring for supplying a voltage for switching the conductive state and non-conductive state of the switches SW1 in each of the circuits CS1[1] to CS1[n].

[0150] Each of the circuits CS1[1] to CS1[n] has a function of keeping the amount of current flowing between the source and drain of the transistor Tr33 constant, even if the source-drain voltage of the transistor Tr33 changes. Specifically, in each of the circuits CS1[1] to CS1[n], the switch SW1 is turned on to configure the transistor Tr33 as a diode connection. At this time, a current flows between the source and drain of the transistor Tr33 according to the source-drain (gate) voltage of the transistor Tr33. In addition, the potential of the gate of the transistor Tr33 is almost equal to the potential of the drain. Here, by turning off the switch SW1 and holding the potential of the gate of the transistor Tr33 by the first terminal of the capacitance C6, the gate-source voltage of the transistor Tr33 can be kept constant. Therefore, when the transistor Tr33 operates in the saturation region, even if the potential of the drain changes, the amount of current flowing between the source and drain can be kept constant as the amount of current flowing when the switch SW1 is turned on.

[0151] In this specification, temporarily connecting a transistor in a diode configuration, making the potential of the gate of the transistor approximately equal to the potential of the drain, and then making the gate and drain of the transistor non-conductive and keeping the amount of source-drain current of the transistor constant is described as "setting (programming) the amount of current flowing between the source and drain of the transistor in the transistor," etc. Also, when the transistor is included in a circuit such as each of circuits CS1[1] to CS1[n], it is described as "setting (programming) the amount of current flowing into the circuit in the circuit," "setting (programming) the amount of current flowing out of the circuit (current flowing into the circuit) in the circuit," etc.

[0152] Each of the circuits CS2[1] to CS2[n] functions as a current source circuit that supplies a constant current, for example. Similarly to the circuits CS1[1] to CS1[n], each of the circuits CS2[1] to CS2[n] also has a function of setting the amount of the constant current.

[0153] Each of the circuits CS2[1] to CS2[n] includes a transistor Tr34 which is an n-channel transistor, a capacitor C7, and a switch SW2.

[0154] Note that the transistor Tr34 can be, for example, an OS transistor or a Si transistor that can be used for the transistor Tr11. When a Si transistor is used for the transistor Tr34, silicon contained in the channel formation region of the transistor Tr34 can be, for example, amorphous silicon (sometimes called hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, single crystal silicon, or the like.

[0155] In addition, it is preferable that the transistors Tr34 included in each of the circuits CS2[1] to CS2[n] have the same electrical characteristics as each other. To achieve this, for example, it is preferable that the transistors Tr34 included in each of the circuits CS2[1] to CS2[n] have the same size as each other.

[0156] In addition, unless otherwise specified, the transistor Tr34 of each of the circuits CS2[1] to CS2[n] includes a case where the transistor Tr34 operates in the saturation region when it is on. In other words, the gate, source, and drain of each of the above-mentioned transistors include a case where a voltage within a range where the transistor operates in the saturation region is appropriately input.

[0157] In each of the circuits CS2[1] to CS2[n], a first terminal of the transistor Tr34 is electrically connected to the wiring VLE, ​​a gate of the transistor Tr34 is electrically connected to a first terminal of the capacitor C7 and a first terminal of the switch SW2, and a second terminal of the transistor Tr34 is electrically connected to a second terminal of the switch SW2. The second terminal of the capacitor C7 is electrically connected to the wiring VLE. The control terminal of the switch SW2 is electrically connected to the wiring SL2.

[0158] In the circuit CS2[1], the second terminal of the transistor Tr34 and the second terminal of the switch SW2 are electrically connected to the second terminal of the switch SW3[1].

[0159] In the circuit CS2[n], the second terminal of the transistor Tr34 and the second terminal of the switch SW2 are electrically connected to the second terminal of the switch SW3[n].

[0160] The line VLE functions as a line that applies a constant voltage. The constant voltage is preferably, for example, a low-level potential.

[0161] The wiring SL2 functions as a wiring for supplying a voltage for switching the conductive state and non-conductive state of the switches SW2 in each of the circuits CS2[1] to CS2[n].

[0162] Each of the circuits CS2[1] to CS2[n] has a function of keeping the amount of current flowing between the source and drain of the transistor Tr34 constant, similar to each of the circuits CS1[1] to CS1[n], even if the source-drain voltage of the transistor Tr34 changes. Specifically, in each of the circuits CS2[1] to CS2[n], the switch SW2 is turned on to configure the transistor Tr34 as a diode connection. At this time, a current flows between the source and drain of the transistor Tr34 according to the source-drain (gate) voltage of the transistor Tr34. In addition, the potential of the gate of the transistor Tr34 becomes almost equal to the potential of the drain. Here, by turning off the switch SW2 and holding the potential of the gate of the transistor Tr34 by the first terminal of the capacitance C7, the gate-source voltage of the transistor Tr34 can be kept constant. Therefore, when the transistor Tr34 operates in the saturation region, even if the drain potential changes, the amount of current flowing between the source and drain can be kept constant as the amount of current flowing when the switch SW2 is turned on.

[0163] The circuit CM functions as, for example, a current mirror circuit, and includes, for example, a transistor Tr31 and transistors Tr32[1] to Tr32[n].

[0164] In order for the circuit CM to function as a current mirror circuit, it is preferable that the transistor Tr31 and the transistors Tr32[1] to Tr32[n] have the same electrical characteristics. To achieve this, for example, it is preferable that the transistors Tr31 and the transistors Tr32[1] to Tr32[n] have the same sizes.

[0165] In addition, unless otherwise specified, each of the transistors Tr31 and Tr32[1] to Tr32[n] includes a case where the transistors Tr31 and Tr32[1] to Tr32[n] operate in a saturation region when on, i.e., a case where a voltage within a range where the transistors operate in a saturation region is appropriately input to the gate, source, and drain of each of the above-mentioned transistors.

[0166] A first terminal of the transistor Tr31 and each of the transistors Tr32[1] to Tr32[n] is electrically connected to the wiring VHE. A second terminal of the transistor Tr31 is electrically connected to a gate of the transistor Tr31, each of the gates of the transistors Tr31[1] to Tr31[n], and a second terminal of the switch SW7r.

[0167] The second terminal of the transistor Tr32[1] is electrically connected to the second terminal of the switch SW3[1], the second terminal of the transistor Tr34 of the circuit CS2[1], and the second terminal of the switch SW2 of the circuit CS2[1]. The second terminal of the transistor Tr32[n] is electrically connected to the second terminal of the switch SW3[n], the second terminal of the transistor Tr34 of the circuit CS2[n], and the second terminal of the switch SW2 of the circuit CS2[n].

[0168] By configuring the circuit CM as shown in FIG. 4, an amount of current approximately equal to the current flowing between the first terminal and the second terminal of transistor Tr31 can be caused to flow between the first terminal and the second terminal of each of transistors Tr32[1] to Tr32[n].

[0169] For example, electrical switches such as analog switches and transistors can be used as the switches SW1, SW2, SW3[1] to SW3[n], SW7[1] to SW7[n], and SW7r. For example, mechanical switches can be used as the switches SW1, SW2, SW3[1] to SW3[n], SW7[1] to SW7[n], and SW7r. When transistors are used as the switches SW1, SW2, SW3[1] to SW3[n], SW7[1] to SW7[n], and SW7r, the transistors can be OS transistors or Si transistors.

[0170] The configuration of the circuit CM is not limited to the configuration shown in Fig. 4. For example, the circuit CM may be configured as shown in Fig. 5, in which the transistors Tr31 and Tr35 are cascode-connected, and the transistors Tr32[1] to Tr32[n] are cascode-connected, respectively, to the transistors Tr36[1] to Tr36[n]. By cascode-connecting the transistors included in the current mirror circuit as in the circuit CM shown in Fig. 5, the operation of the current mirror circuit can be made more stable.

[0171] In this embodiment, each of switches SW1, SW2, SW3[1] to SW3[n], SW7[1] to SW7[n], and SW7r is turned on when a high-level potential is input to the control terminal, and turned off when a low-level potential is input to the control terminal.

[0172] <Example of operation of the calculation circuit> Next, an example of the operation of the arithmetic circuit MAC1 will be described.

[0173] Fig. 6 shows a timing chart of an operation example of the arithmetic circuit MAC1. The timing chart of Fig. 6 shows the fluctuation of the potentials of the wiring WL[1], wiring WL[2], wiring WL[m] (in this operation example, m is an integer of 4 or more), wiring SL1, wiring SL2, wiring SL3, wiring SL4, wiring SL7, wiring WE, wiring WD[1], wiring WDr, node N[1,1], node N[2,1], node N[m,1], node Nr[1], node Nr[2], node Nr[m], wiring XL[1], wiring XL[2], and wiring XL[m] at times T01 to T14 and in the vicinity thereof. Note that in Fig. 6, a high-level potential is represented as High, and a low-level potential is represented as Low.

[0174] In this operation example, the voltage applied by the line VR is set to the ground potential.

[0175] <<From time T01 to time T02>> Between time T01 and time T02, a high-level potential is input to the wiring WE, which turns on the switches SW5[1] to SW5[n] and the switch SW5r included in the circuit ACTV.

[0176] When the switches SW5[1] to SW5[n] and SW5r are turned on, the wirings BL[1] to BL[n] and BLr are electrically connected to the wiring VSL, and an initialization potential is applied from the wiring VSL to the wirings BL[1] to BL[n] and BLr. Note that in this operation example, the initialization potential applied by the wiring VSL is the ground potential.

[0177] In addition, a high-level potential is input to the wiring SL4 between time T01 and time T02, which causes the switches SW4A[1] to SW4A[n] and the switches SW4B[1] to SW4B[n] included in the circuit ACTV to be turned on.

[0178] When the switches SW4A[1] to SW4A[n] are turned on, the first terminals of the circuits IVC[1] to IVC[n] are supplied with a ground potential from the wiring VSL. In this operation example, the potential supplied from the wiring VdL is set to the ground potential, so that a potential of 0 V is output from the second terminals of the circuits IVC[1] to IVC[n].

[0179] In addition, a low-level potential is input to the wirings WL[1] to WL[m] between time T01 and time T02.

[0180] In addition, a low-level potential is input to the wirings SL1 to SL3 and the wiring SL7 between time T01 and time T02. Therefore, in the circuit CMS, the switch SW1 included in the circuits CS1[1] to CS1[n], the switch SW2 included in the circuits CS2[1] to CS2[n], the switches SW3[1] to SW3[n], the switches SW7[1] to SW7[n], and the switch SW7r are turned off.

[0181] Between time T01 and time T02, a ground potential (denoted as GND in FIG. 6) is input to the wiring WD[1] and the wiring WDr.

[0182] In addition, between time T01 and time T02, a voltage is supplied from the circuit XLD to each of the wirings XL[1] to XL[m]. Here, for example, the voltage supplied from the circuit XLD to each of the wirings XL[1] to XL[m] is set to a reference potential (V RFP It is written as follows.)

[0183] Between time T01 and time T02, the potentials of the nodes N[1,1] to N[m,n] and the potentials of the nodes Nr[1] to Nr[m] are set to the ground potential (denoted as GND in FIG. 6).

[0184] <<From time T02 to time T03>> Between time T02 and time T03, a low-level potential is input to the wiring SL4, which turns off the switches SW4A[1] to SW4A[n] and the switches SW4B[1] to SW4B[n] included in the circuit ACTV.

[0185] As a result, no current flows from each of the wirings BL[1] to BL[n] to the first terminals of the circuits IVC[1] to IVC[n]. This makes it possible to suppress changes in the potentials of the first terminals of the circuits IVC[1] to IVC[n] caused by changes in the potentials of the wirings BL[1] to BL[n]. This completes the initialization of the circuits IVC[1] to IVC[n].

[0186] Note that, from time T02 to time T03, the high-level potential continues to be input to the wiring WE from before time T02. Also, from time T02 to time T03, the low-level potential continues to be input to the wirings SL1, SL2, SL3, SL4, and SL7 from before time T02.

[0187] <<From time T03 to time T04>> Between time T03 and time T04, a high-level potential is input to the wiring WL[1], so that a high-level potential is applied to the gates of the transistors Tr11 included in each of the memory cells AM[1,1] to AM[1,n] and the memory cell AMr[1] in the memory cell array CA, turning on each of the transistors Tr11.

[0188] In addition, between time T03 and time T04, the line WD[1] is at a potential higher than the ground potential V PR -V W[1,1]At this time, since the transistor Tr11 of the memory cell AM[1,1] is in an on state, the line WD[1] and the node N[1,1] are in a conductive state, and the first terminal (node ​​N[1,1]) of the capacitor C1 of the memory cell AM[1,1] is supplied with a potential higher than the ground potential V PR -V W[1,1] A large potential is input.

[0189] In this operation example, V PR is the potential corresponding to the reference data, and V W[1,1] is a potential corresponding to the first data stored in the memory cell AM[1,1].

[0190] In addition, between time T03 and time T04, the line WDr is charged with a potential higher than the ground potential V PR At this time, since the transistor Tr11 of the memory cell AMr[1] is in an on state, the line WDr and the node Nr[1] are in a conductive state, and the first terminal (node ​​Nr[1]) of the capacitor C1 of the memory cell AMr[1] is supplied with a potential higher than the ground potential V PR A large potential is input.

[0191] In addition, since the switches SW5[1] to SW5[n] are in an on state, the ground potential is input to each of the wirings BL[1] to BL[n]. In addition, since the ground potential from the wiring VR is input to the first terminal of the transistor Tr12 in each of the memory cells AM[1,1] to AM[m,n], the voltage between the first terminal and the second terminal of the transistor Tr12 is approximately 0 V. Therefore, no current flows between the first terminal and the second terminal of the transistor Tr12 in each of the memory cells AM[1,1] to AM[m,n].

[0192] In addition, since the switch SW5r is also in an on state, the ground potential is also input to the wiring BLr. In addition, since the ground potential from the wiring VR is input to the first terminal of the transistor Tr12 in the memory cells AMr[1] to AMr[m], the voltage between the first terminal and the second terminal of the transistor Tr12 is approximately 0 V. Therefore, no current flows between the first terminal and the second terminal of the transistor Tr12 in each of the memory cells AMr[1] to AMr[m].

[0193] In addition, between time T03 and time T04, the transistors Tr11 of the memory cells AM[1,2] to AM[1,n] are also in an on state, so that at this timing, the first data can be input from the wirings WD[2] to WD[n] to the memory cells AM[1,2] to AM[1,n], respectively, to write potentials corresponding to the first data to the nodes N[1,2] to N[1,n]. Note that in this operation example, the description focuses on the memory cells AM[1,1] to AM[m,1] electrically connected to the wiring WD[1] and the memory cells AMr[1] to AMr[m] electrically connected to the wiring WDr, and therefore the description of the operations of the other memory cells is omitted.

[0194] In addition, between time T03 and time T04, the wirings WL[2] to WL[m] continue to receive a low-level potential from before time T03. Therefore, in the memory cell array CA, a low-level potential is applied to the gates of the transistors Tr11 included in the memory cells AM[2,1] to AM[m,1] and the memory cells AMr[2] to AMr[m] arranged in the second to m-th rows, and the transistors Tr11 are in an off state. As a result, the data input to the wirings WD[1] and WDr are not written to the nodes N[2,1] to N[m,1] and the nodes Nr[2] to Nr[m].

[0195] <<From time T04 to time T05>> Between time T04 and time T05, a low-level potential is input to the wiring WL[1], so that a low-level potential is applied to the gates of the transistors Tr11 included in each of the memory cells AM[1,1] to AM[1,n] and the memory cell AMr[1] in the memory cell array CA, turning off each of the transistors Tr11.

[0196] In the memory cell AM[1,1], the transistor Tr11 is turned off, so that the first terminal (node ​​N[1,1]) of the capacitor C1 of the memory cell AM[1,1] is charged with a potential higher than the ground potential V PR -V W[1,1] In addition, in the memory cell AMr[1], the transistor Tr11 is turned off, so that a potential higher than the ground potential is applied to the first terminal (node ​​Nr[1]) of the capacitor C1 of the memory cell AMr[1]. PR A large potential is maintained.

[0197] <<From time T05 to time T06>> Between time T05 and time T06, a high-level potential is input to the wiring WL[2], so that a high-level potential is applied to the gates of the transistors Tr11 included in each of the memory cells AM[2,1] to AM[2,n] and AMr[2] in the memory cell array CA, turning on each of the transistors Tr11.

[0198] In addition, between time T05 and time T06, the line WD[1] is at a potential higher than the ground potential V PR -V W[2,1] At this time, the transistor Tr11 of the memory cell AM[2,1] is in an on state, so that the line WD[1] and the node N[2,1] are in a conductive state, and the first terminal (node ​​N[2,1]) of the capacitor C1 of the memory cell AM[2,1] is supplied with a potential higher than the ground potential V PR -V W[2,1] A large potential is input.

[0199] In this operation example, V W[2,1] is a potential corresponding to the first data stored in the memory cell AM[2,1].

[0200] In addition, between time T05 and time T06, the line WDr is charged with a potential higher than the ground potential V PR At this time, since the transistor Tr11 of the memory cell AMr[2] is in an on state, the line WDr and the node Nr[2] are in a conductive state, and the first terminal (node ​​Nr[2]) of the capacitor C1 of the memory cell AMr[2] is supplied with a potential higher than the ground potential V PR A large potential is input.

[0201] In addition, between time T05 and time T06, the wiring WL[1] and the wirings WL[3] to WL[m] are continuously supplied with a low-level potential from before time T05. Therefore, in the memory cell array CA, a low-level potential is applied to the gates of the transistors Tr11 included in the memory cells AM[1,1], AM[3,1] to AM[m,1], AMr[1], and AMr[3] to AMr[m] arranged in the first row and the third row to the mth row, and each transistor Tr11 is in an off state. As a result, the data input to each of the wirings WD[1] and WDr is not written to the nodes N[1,1], N[3,1] to N[m,1], Nr[1], and Nr[3] to Nr[m].

[0202] <<From time T06 to time T07>> Between time T06 and time T07, a low-level potential is input to the wiring WL[2], so that a low-level potential is applied to the gates of the transistors Tr11 included in each of the memory cells AM[2,1] to AM[2,n] and AMr[2] in the memory cell array CA, turning off each of the transistors Tr11.

[0203] In the memory cell AM[2,1], when the transistor Tr11 is turned off, a potential V ... PR -V W[2,1] In addition, in the memory cell AMr[2], the transistor Tr11 is turned off, so that a potential higher than the ground potential is applied to the first terminal (node ​​Nr[2]) of the capacitor C1 of the memory cell AMr[2]. PR A large potential is maintained.

[0204] <<From time T07 to time T08>> Between time T07 and time T08, similar to the above-mentioned operations between time T03 and time T04 and between time T05 and time T06, a potential corresponding to the first data is held at the first terminal of the capacitance C1 of each of the memory cells AM[3,1] to AM[m-1,n]. Specifically, for example, the first terminal (node ​​N[3,1]) of the capacitance C1 of the memory cell AM[3,1] is held at a potential V PR -V W[3,1] A higher potential is held, and the first terminal (node ​​N[m-1,1]) of the capacitor C1 of the memory cell AM[m-1,1] is supplied with a potential higher than the ground potential V PR -V W[m-1,1] A high potential is maintained.

[0205] In this operation example, V W[3,1] is the potential corresponding to the first data stored in the memory cell AM[3,1], and V W[m-1,1] is a potential corresponding to the first data stored in the memory cell AM[m-1,1].

[0206] <<From time T08 to time T09>> Between time T08 and time T09, a high-level potential is input to the wiring WL[m], so that a high-level potential is applied to the gates of the transistors Tr11 included in each of the memory cells AM[m,1] to AM[m,n] and AMr[m] in the memory cell array CA, turning on each of the transistors Tr11.

[0207] In addition, between time T08 and time T09, the line WD[1] is at a potential higher than the ground potential V PR -V W[m,1] At this time, since the transistor Tr11 of the memory cell AM[m,1] is in an on state, the line WD[1] and the node N[m,1] are in a conductive state, and the first terminal (node ​​N[m,1]) of the capacitor C1 of the memory cell AM[m,1] is supplied with a potential higher than the ground potential V PR -V W[m,1] A large potential is input.

[0208] In this operation example, V W[m,1] is a potential corresponding to the first data stored in the memory cell AM[m,1].

[0209] In addition, between time T08 and time T09, the line WDr is charged with a potential higher than the ground potential V PR At this time, since the transistor Tr11 of the memory cell AMr[m] is in an on state, the line WDr and the node Nr[m] are in a conductive state, and the first terminal (node ​​Nr[m]) of the capacitor C1 of the memory cell AMr[m] is supplied with a potential higher than the ground potential V PR A large potential is input.

[0210] In addition, between time T08 and time T09, the low-level potential is continuously input to the wirings WL[1] to WL[m-1] from before time T08. Therefore, in the memory cell array CA, a low-level potential is applied to the gates of the transistors Tr11 included in the memory cells AM[1,1] to AM[m-1,1] and the memory cells AMr[1] to AMr[m-1] arranged in the 1st row to the m-1th row, and each of the transistors Tr11 is in an off state. As a result, the data input to the wirings WD[1] and WDr is not written to the nodes N[1,1] to N[m-1,1] and the nodes Nr[1] to Nr[m-1].

[0211] <<From time T09 to time T10>> Between time T09 and time T10, a low-level potential is input to the wiring WL[m], so that a low-level potential is applied to the gates of the transistors Tr11 included in each of the memory cells AM[m,1] to AM[m,n] and the memory cell AMr[m] in the memory cell array CA, turning off each of the transistors Tr11.

[0212] In the memory cell AM[m,1], when the transistor Tr11 is turned off, a potential V 1 is applied to the first terminal (node ​​N[m,1]) of the capacitor C1 of the memory cell AM[m,1], which is higher than the ground potential. PR -V W[m,1] In addition, in the memory cell AMr[m], the transistor Tr11 is turned off, so that a potential higher than the ground potential V PR A large potential is maintained.

[0213] <<From time T10 to time T11>> Between time T10 and time T11, a low-level potential is input to the wiring WE, which causes the switches SW5[1] to SW5[n] and the switch SW5r in the circuit ACTV to be turned off.

[0214] <<From time T11 to time T12>> Between time T11 and time T12, a high-level potential is input to the wirings SL1, SL2, and SL7. As a result, in the circuit CMS, the switch SW1 included in each of the circuits CS1[1] to CS1[n], the switch SW2 included in each of the circuits CS2[1] to CS2[n], the switches SW7[1] to SW7[n], and the switch SW7r are turned on.

[0215] At this time, each of the memory cells AM[1,1] to AM[m,1] is in electrical contact with the circuit CS1[1] included in the circuit CMS through the wiring BL[1]. Also, each of the memory cells AMr[1] to AMr[m] is in electrical contact with the circuit CM included in the circuit CMS through the wiring BLr.

[0216] Here, consider the current flowing from the second terminal to the first terminal of the transistor Tr12 in each of the memory cells AM[1,1] to AM[m,1].

[0217] For example, the current flowing from the wiring BL to the first terminal via the second terminal of the transistor Tr12 of the memory cell AM[1,1] is I AM[1,1],1 Then, I AM[1,1],1 can be expressed by the following formula:

[0218]

number

[0219] k is a constant determined by the channel length, channel width, mobility, and capacitance of the gate insulating film of the transistor Tr12. this the threshold voltage of the transistor Tr12. Note that the constant k can be applied not only to the memory cell AM[1,1] but also to the other memory cells AM and AMr. In addition, the threshold voltages of the transistors Tr12 of not only the memory cell AM[1,1] but also the other memory cells AM and AMr are V th Let us assume that.

[0220] For example, the current flowing from the wiring BL to the first terminal of the transistor Tr12 of the memory cell AM[2,1] via the second terminal is I AM[2,1],1 Then, I AM[2,1],1 can be expressed by the following formula:

[0221]

number

[0222] For example, the current flowing from the wiring BL to the first terminal of the transistor Tr12 of the memory cell AM[m,1] via the second terminal is I AM[m,1],1 Then, I AM[m,1],1 can be expressed by the following formula:

[0223]

number

[0224] Here, consider the current flowing between the first terminal and the second terminal of the transistor Tr33 of the circuit CS1[1] included in the circuit CMS. In this operation example, the amount of this current is represented as I1.

[0225] Between time T11 and time T12, switch SW1 in circuit CS1[1] is on, switch SW3[1] is off, switch SW7[1] is on, and switch SW4A[1] in circuit AVTC is off. Therefore, the amount of current I1 flowing between the first terminal and the second terminal of transistor Tr33 in circuit CS1[1] can be expressed by the following equation using Kirchhoff's law.

[0226]

number

[0227] In addition, the transistor Tr33 of the circuit CS1[1] is configured as a diode connection, and a wiring VHE that provides a high-level potential as a constant voltage is electrically connected to the first terminal of the transistor Tr33 of the circuit CS1[1]. Therefore, the potential of the gate (second terminal) of the transistor Tr33 of the circuit CS1[1] is determined by the amount of current I1 flowing between the first terminal and the second terminal of the transistor Tr33.

[0228] Next, consider the current flowing from the second terminal to the first terminal of the transistor Tr12 in each of the memory cells AMr[1] to AMr[m].

[0229] For example, the current flowing from the wiring BLr to the first terminal via the second terminal of the transistor Tr12 of the memory cell AMr[1] is I AMr[1],2 Similarly, when AMr[1],2 can be expressed by the following formula:

[0230]

number

[0231] For example, the current flowing from the wiring BLr to the first terminal of the transistor Tr12 of the memory cell AMr[2] via the second terminal is I AMr[2],2 Similarly, when AMr[2],2 can be expressed by the following formula:

[0232]

number

[0233] For example, the current flowing from the wiring BLr to the first terminal via the second terminal of the transistor Tr12 of the memory cell AMr[m] is I AMr[m],2 Similarly, whenAMr[m],2 can be expressed by the following formula:

[0234]

number

[0235] Here, consider the current flowing between the first terminal and the second terminal of the transistor Tr34 of the circuit CS2[1] included in the circuit CMS. In this operation example, the amount of this current is represented as I2.

[0236] Between time T11 and time T12, switch SW2 of circuit CS2[1] is on, switch SW3[1] is off, and switch SW7r is on, so the amount of current flowing between the first terminal and the second terminal of transistor Tr34 of circuit CS2[1] is approximately equal to the amount of current flowing between the first terminal and the second terminal of transistor Tr32[1].

[0237] In addition, since the circuit CM is configured as a current mirror circuit, the amount of current flowing between the first terminal and the second terminal of the transistor Tr32[1] is approximately equal to the amount of current flowing between the first terminal and the second terminal of the transistor Tr31.

[0238] Since the amount of current flowing between the first terminal and the second terminal of transistor Tr31 is the sum of the currents flowing from wiring BLr to memory cells AMr[1] to AMr[m], the amount of current I2 flowing between the first terminal and the second terminal of transistor Tr34 in circuit CS2[1] can be expressed as follows:

[0239]

number

[0240] In addition, the transistor Tr34 of the circuit CS2[1] is configured as a diode connection, and the first terminal of the transistor Tr34 of the circuit CS2[1] is electrically connected to a wiring VLE that provides a high-level potential as a constant voltage. Therefore, the potential of the gate (second terminal) of the transistor Tr34 of the circuit CS2[1] is determined by the amount of current I2 flowing between the first terminal and the second terminal of the transistor Tr34.

[0241] <<From time T12 to time T13>> Between time T12 and time T13, a low-level potential is input to the wiring SL1, and a low-level potential is input to the wiring SL2. As a result, in the circuit CMS, the switches SW1 included in each of the circuits CS1[1] to CS1[n] are turned off, and the switches SW2 included in each of the circuits CS2[1] to CS2[n] are turned off.

[0242] Therefore, the potential of the gate of the transistor Tr33 of the circuit CS1[1] is held by the first terminal of the capacitor C6, and the potential of the gate of the transistor Tr34 of the circuit CS2[1] is held by the first terminal of the capacitor C7 during the period from time T12 to time T13. As a result, the gate-source voltage of the transistor Tr33 of the circuit CS1[1] is held, so that the amount of current I1 always flows between the first terminal and the second terminal of the transistor Tr33. Similarly, the gate-source voltage of the transistor Tr34 of the circuit CS2[1] is held, so that the amount of current I2 always flows between the first terminal and the second terminal of the transistor Tr34. That is, the amount of current I1 flowing out of the circuit CS[1] is set to the circuit CS[1], and the amount of current I2 flowing into the circuit CS2[1] is set to the circuit CS2[1].

[0243] <<From time T13 to time T14>> Between time T13 and time T14, a high-level potential is input to the wiring SL3, and a high-level potential is input to the wiring SL4. As a result, in the circuit CMS, the switches SW3[1] to SW3[n] are turned on. In the circuit ACTV, the switches SW4A[1] to SW4A[n] and SW4B[1] to SW4B[n] are turned on.

[0244] In addition, between time T13 and time T14, a potential corresponding to the second data is input to each of the wirings XL[1] to XL[m]. Here, for example, the potential input from the circuit RPC[1] to the wiring XL[1] is set to V RFP +V X[1] The potential input from the circuit RPC[2] to the wiring XL[2] is V higher than the ground potential. RFP +V X[2] The potential input from the circuit RPC[m] to the wiring XL[m] is V higher than the ground potential. RFP +V X[m] The potential is set to high.

[0245] In this operation example, the potential V X[1] ~V X[m] is a potential corresponding to the second data.

[0246] Between time T13 and time T14, the potential of the wiring XL[1] is the reference potential V RFP From V RFP +V X[1] , the second terminal of the capacitance C1 of each of the memory cell AM[1] and the memory cell AMr[1] is V RFP +V X[1] At this time, since the nodes N[1,1] and Nr[1] are in an electrically floating state, the potentials of the nodes N[1,1] and Nr[1] change due to the capacitive coupling of the capacitor C1.

[0247] In each of the memory cell AM[1] and the memory cell AMr[1], the increment of the potential of the gate of the transistor Tr12 is the potential obtained by multiplying the potential change of the wiring XL[1] by a capacitance coupling coefficient determined by the configuration of the memory cell. The capacitance coupling coefficient is calculated based on the capacitance of the capacitor C1, the gate capacitance of the transistor Tr12, the parasitic capacitance, and the like. In this operation example, in order to avoid complexity of the explanation, the increment of the potential of the wiring XL[1] and the increment of the potential of the gate of the transistor Tr12 are described as having the same value. This corresponds to the capacitance coupling coefficient of each of the memory cell AM[1,1] and the memory cell AMr[1] being 1. In this operation example, the capacitance coupling coefficient of each of the memory cells other than the memory cell AM[1,1] and the memory cell AMr[1] included in the memory cell array CA is also described as being 1.

[0248] Since the capacitive coupling coefficient is set to 1, the potential of the second terminal of the capacitance C1 of each memory cell AM[1,1] and memory cell AMr[1] is V RFP From V RFP +V X[1] As a result, the potentials of the nodes N[1,1] and Nr[1] change to V X[1] to rise.

[0249] Here, the current flowing from the wiring BL to the first terminal via the second terminal of the transistor Tr12 of the memory cell AM[1,1] is I AM[1,1],3 Then, I AM[1.1],3 can be expressed by the following formula:

[0250]

number

[0251] Similarly, the current flowing from the wiring BLr to the first terminal via the second terminal of the transistor Tr12 of the memory cell AMr[1] is I AMr[1],4 Then, I AMr[1],4 can be expressed by the following formula:

[0252]

number

[0253] In addition, the capacitive coupling coefficient of the memory cell AM[2,1] and the memory cell AMr[2] is set to 1, so the potential of the second terminal of the capacitance C1 included in each of them is V RFP From V RFP +V X[2] As a result, the potentials of the nodes N[2,1] and Nr[2] change to V X[2] to rise.

[0254] Here, for example, the current flowing from the wiring BL to the first terminal via the second terminal of the transistor Tr12 of the memory cell AM[2,1] is I AM[2,1],3 Then, I AM[2.1],3 can be expressed by the following formula:

[0255]

number

[0256] Similarly, for example, the current flowing from the wiring BLr to the first terminal via the second terminal of the transistor Tr12 of the memory cell AMr[2] is I AMr[2],4 Then, I AMr[2],4 can be expressed by the following formula:

[0257]

number

[0258] In addition, the capacitive coupling coefficient of the memory cell AM[m,1] and the memory cell AMr[m] is set to 1, so that the potential of the second terminal of the capacitance C1 included in each of them is V RFP From V RFP +V X[m] By changing the potential of the node N[m,1] and the node Nr[m] to V X[m] to rise.

[0259] Here, for example, the current flowing from the wiring BL to the first terminal via the second terminal of the transistor Tr12 of the memory cell AM[m,1] is I AM[m,1],3 Then, I AM[m.1],3 can be expressed by the following formula:

[0260]

number

[0261] Similarly, for example, the current flowing from the wiring BLr to the first terminal via the second terminal of the transistor Tr12 of the memory cell AMr[2] is I AMr[m],4 Then, I AMr[m],4 can be expressed by the following formula:

[0262]

number

[0263] When the total amount of current flowing from wiring BL[1] to memory cells AM[1,1] to AM[m,1] between time T13 and time T14 is I3, the amount of current I3 can be expressed as follows:

[0264]

number

[0265] In addition, since the circuit CM is configured as a current mirror circuit, the amount of current flowing between the first terminal and the second terminal of the transistor Tr32[1] included in the circuit CM is approximately equal to the amount of current flowing between the first terminal and the second terminal of the transistor Tr31. In addition, the amount of current flowing between the first terminal and the second terminal of the transistor Tr31 is the sum of the currents flowing from the wiring BLr to the memory cells AMr[1] to AMr[m]. When the amount of current flowing between the first terminal and the second terminal of the transistor Tr32[1] included in the circuit CM between time T13 and time T14 is I4, the amount of current I4 can be expressed as follows:

[0266]

number

[0267] Also, between time T13 and time T14, switches SW3[1] through SW3[n], switches SW4A[1] through SW4A[n], and switches SW4B[1] through SW4B[n] are in the on state, so that current flows from the circuit CMS and the memory cell array CA through the wiring BL to the circuit ACTV. Specifically, for example, a current I1 flows out of the circuit CS1[1], a current I2 flows into the circuit CS2[1], a current I3 flows in the memory cells AM[1,1] through AM[m,1], and a current I4 flows between the source and drain of the transistor Tr32[1] of the circuit CM. Here, the amount of current flowing from the wiring BL[1] to the wiring NIL[1] is I S [1], the amount of current I S [1] can be written as follows using Kirchhoff's law:

[0268]

number

[0269] From equation (1.20), the amount of current I input from wiring BL[1] to circuit ACTV S [1] is the potential V according to the first data W[1,1] ~V W[m,1] and a potential V according to the second data X[1] ~V X[m] In other words, the sum of the products of the first data and the second data is proportional to the amount of current I S [1]

[0270] In this embodiment, the transistor included in the arithmetic circuit MAC1 is an OS transistor or a Si transistor, but one embodiment of the present invention is not limited thereto. The transistor included in the arithmetic circuit MAC1 may be, for example, a transistor including Ge or the like in a channel formation region, a transistor including a compound semiconductor such as ZnSe, CdS, GaAs, InP, GaN, or SiGe in a channel formation region, a transistor including a carbon nanotube in a channel formation region, or a transistor including an organic semiconductor in a channel formation region.

[0271] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0272] (Embodiment 2) In this embodiment, an arithmetic circuit having a different configuration from the arithmetic circuit MAC1 described in the first embodiment will be described.

[0273] <Arithmetic circuit configuration example 2> The arithmetic circuit MAC2 shown in FIG. 7 differs from the arithmetic circuit MAC1 in that it has memory cells AMb[1] to AMb[n] in a memory cell array CA.

[0274] The memory cell AMb[1] is electrically connected to the wiring BL[1], the wiring WD[1], the wiring XLb, and the wiring WLb. The memory cell AMb[n] is electrically connected to the wiring BL[n], the wiring WD[n], the wiring XLb, and the wiring WLb.

[0275] A specific configuration example of the memory cells AMb[1] to AMb[n] is shown in Fig. 8. Note that Fig. 8 also illustrates memory cells AM[1,1] to AM[m,n], memory cells AMr[1] to AMr[m], a circuit WDD, a circuit CMS, and a circuit ACTV in order to show electrical connections with the memory cells AMb[1] to AMb[n], respectively.

[0276] 8, the memory cells AMb[1] to AMb[n] can be configured in a similar manner to the memory cells AM[1,1] to AM[m,n] and the memory cells AMr[1] to AMr[m]. Therefore, in the arithmetic circuit MAC2 in FIG. 8, each of the memory cells AMb[1] to AMb[n] includes a transistor Tr11, a transistor Tr12, and a capacitance C1.

[0277] In each of the memory cells AMb[1] to AMb[n], a first terminal of the transistor Tr12 is electrically connected to the wiring VRA.

[0278] In the memory cell AMb[1], the electrical connection point between the first terminal of the transistor Tr11, the gate of the transistor Tr12, and the first terminal of the capacitor C1 is defined as a node Nb[1]. In the memory cell AMb[n], the electrical connection point between the first terminal of the transistor Tr11, the gate of the transistor Tr12, and the first terminal of the capacitor C1 is defined as a node Nb[n].

[0279] The wiring WLb functions as a wiring that supplies a selection signal from the circuit WLD to the memory cells AMb[1] to AMb[n] when writing data to the memory cells AMb[1] to AMb[n]. The wiring XLb functions as a wiring that applies a constant potential to the second terminals of the capacitors C1 of the memory cells AMb[1] to AMb[n], for example. The constant potential is preferably a ground potential, a low-level potential, a high-level potential, or the like. Alternatively, the wiring XLb may function as a wiring that supplies an arbitrary potential from the circuit XLD.

[0280] The wiring VRA of each of the memory cells AMb[1] to AMb[n] can be a low-level potential, a ground potential, or a potential lower than the ground potential, similar to the wirings VR of each of the memory cells AM[1,1] to AM[m,n] and the memory cells AMr[1] to AMr[m]. Alternatively, the wirings VRA of each of the memory cells AMb[1] to AMb[n] may be wirings that apply a high-level potential in some cases. For example, if a positive current is to flow from the memory cell AMb[1] to the wiring BL[1], the wiring VRA of the memory cell AMb[1] may be a wiring that applies a high-level potential.

[0281] As an example of the operation of the arithmetic circuit MAC2 in Fig. 8, for example, in the timing chart of Fig. 6, between time T02 and time T11, the nodes Nb[1] to Nb[n] are held at the ground potential, low-level potential, or potential applied by the wiring VR so that the transistors Tr12 of the memory cells AMb[1] to AMb[n] are turned off. Then, in the timing chart of Fig. 6, between time T14 and time T15, an arbitrary amount of current I BIAS [1]~I BIAS A potential V BIAS [1]~V BIAS [n] is held. For example, in this case, I BIAS [1] is expressed by the following formula.

[0282]

number

[0283] Therefore, between time T14 and time T15, for example, the amount of current I S [1] is expressed as follows:

[0284]

number

[0285] Equation (2.2) corresponds to an operation that further gives an arbitrary bias to the result of the product-sum operation. As will be described in detail in the third embodiment, the operation that further gives an arbitrary bias to the result of the product-sum operation is used in the operation of a hierarchical neural network. For this reason, it can be said that the arithmetic circuit MAC2 is suitable for performing the operation of a hierarchical neural network.

[0286] <Arithmetic circuit configuration example 3> Next, a configuration example of an arithmetic circuit which is a semiconductor device of one embodiment of the present invention, different from the arithmetic circuit MAC1 in FIG. 1 and the arithmetic circuit MAC2 in FIG. 7, will be described.

[0287] The arithmetic circuit MAC3 shown in FIG. 9 differs from the arithmetic circuits MAC1 and MAC2 in that a current related to the result of a product-sum operation flows from the circuit CMS to the circuit ACTV.

[0288] 9, the circuit CMS is electrically connected to the circuit ACTV through wirings BLO[1] to BLO[n]. Note that for other circuit configurations, the description of the arithmetic circuit MAC1 in FIG. 1 should be referred to.

[0289] FIG. 10 shows a specific example of the configuration of the circuit ACTV and the circuit CMS.

[0290] The circuit CMS shown in Figure 10 is configured such that, in the circuit CMS of Figure 4 described in embodiment 1, a wiring BLO[1] is electrically connected to the second terminal of the switch SW3[1], the second terminal of the transistor Tr32[1], and the second terminal of the transistor Tr34 in the circuit CS2[1], and a wiring BLO[n] is electrically connected to the second terminal of the switch SW3[n], the second terminal of the transistor Tr32[n], and the second terminal of the transistor Tr34 in the circuit CS2[n].

[0291] 10 includes switches SW8[1] to SW8[n] and a switch SW8r, and the first terminals of the switches SW8[1] to SW8[n] are electrically connected to the wirings BL[1] to BL[n] and the first terminals of the switches SW7[1] to SW7[n]. The first terminal of the switch SW8r is electrically connected to the wiring BLr. The second terminals of the switches SW8[1] to SW8[n] and SW8r are electrically connected to the wiring VLL, and the control terminals of the switches SW8[1] to SW8[n] and SW8r are electrically connected to the wiring SL8.

[0292] Note that, as the switches SW8[1] to SW8[n] and the switch SW8r, for example, switches applicable to the switches SW1, SW2, SW3[1] to SW3[n], etc. can be used. In this specification and the like, like the switches SW1, SW2, and SW3[1] to SW3[n], each of the switches SW8[1] to SW8[n] and the switch SW8r is turned on when a high-level potential is input to the control terminal, and turned off when a low-level potential is input to the control terminal.

[0293] The wiring VLL functions as a wiring that applies a constant voltage, for example. The constant voltage can be, for example, a low-level potential, a ground potential, or the like. In particular, the constant voltage applied by the wiring VLL may be equal to the constant voltage applied by the wiring VSL. In other words, the wiring VLL and the wiring VSL may be integrated into a single wiring.

[0294] For example, the wiring SL8 functions as a wiring that supplies a voltage for switching the switches SW8[1] to SW8[n] and the switch SW8r between a conductive state and a non-conductive state.

[0295] 10 has almost the same configuration as the circuit ACTV in FIG.

[0296] 10, wirings that electrically connect the circuit ACTV and the circuit CMS are designated as wirings BLO[1] to BLO[n]. The wirings BLO[1] to BLO[n] are electrically connected to the first terminals of the switches SW4[1] to SW4 included in the circuit ACTV in FIG.

[0297] By applying the circuit CMS and the circuit ACTV having the configuration shown in FIG. 10 to the arithmetic circuit MAC3 in FIG. 9, it is possible to perform the same operation as the arithmetic circuit MAC1 described in the first embodiment.

[0298] In the timing chart of FIG. 6, when potentials corresponding to the first data are written to each of the memory cells AM[1,1] to AM[m,n] and the memory cells AMr[1] to AMr[m], that is, between time T03 and time T09, a high-level potential is applied to the wiring WE to turn on the switches SW5[1] to SW5[n] and SW5r, and the potentials of the wirings BL[1] to BL[n] and BLr are set to ground potential. However, in the arithmetic circuit MAC3 to which the circuit CMS and circuit ACTV of FIG. 10 are applied, a high-level potential is applied to the wiring SL8 to turn on the switches SW8[1] to SW8[n] and SW8r, and the potentials of the wirings BL[1] to BL[n] and BLr are set to ground potential. Furthermore, when current is to flow from each of the wirings BL[1] to BL[n] and the wiring BLr to the corresponding memory cells AM and memory cells AMr, for example, after time T11 in the timing chart of FIG. 6, a low-level potential can be applied to the wiring SL8 to turn off the switches SW8[1] to SW8[n] and the switch SW8r.

[0299] Furthermore, the configurations of the circuit CMS and the circuit ACTV included in the arithmetic circuit MAC3 in Fig. 9 are not limited to the configuration shown in Fig. 10. For example, the circuit CMS and the circuit ACTV included in the arithmetic circuit MAC3 in Fig. 9 may have the configuration example shown in Fig. 11.

[0300] The circuit CMS shown in Fig. 11 is configured by adding switches SW6[1] to SW6[n] to the circuit CMS in Fig. 10. Specifically, a first terminal of the switch SW6[1] is electrically connected to a second terminal of the switch SW3[1], a second terminal of the transistor Tr32[1], and a second terminal of the transistor Tr34. The second terminal of the switch SW6[1] is electrically connected to a wiring BLO[1]. The control terminals of the switches SW6[1] to SW6[n] are electrically connected to a wiring SL6.

[0301] Note that the switches SW6[1] to SW6[n] may be, for example, switches that can be applied to the switches SW1, SW2, SW3[1] to SW3[n], etc. In this specification and the like, like the switches SW1, SW2, and SW3[1] to SW3[n], each of the switches SW6[1] to SW6[n] is turned on when a high-level potential is input to a control terminal, and turned off when a low-level potential is input to the control terminal.

[0302] 11 does not include the switches SW4A[1] to SW4A[n] in the circuit ACTV of Fig. 2. Therefore, wirings BLO[1] to BLO[n] are electrically connected to the first terminals of the circuits IVC[1] to IVC[n] included in the circuit ACTV of Fig. 11, respectively.

[0303] That is, the circuit CMS in FIG. 11 is configured such that switches SW6[1] through SW6[n] are provided in place of the switches SW4A[1] through SW4A[n] included in the circuit ACTV in FIG.

[0304] Furthermore, when the operation of the timing chart of FIG. 6 described in embodiment 1 is performed using the circuit CMS of FIG. 11 and the arithmetic circuit MAC3 to which the circuit ACTV is applied, the timing at which the switches SW3[1] to SW3[n], the switches SW4B[1] to SW4B[n], and the switches SW6[1] to SW6[n] are each turned on or off is the same, so the wiring SL3, the wiring SL4, and the wiring SL6 may be combined into a single wiring.

[0305] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0306] (Embodiment 3) In this embodiment, a structure of a hierarchical neural network that can perform an operation using a semiconductor device of one embodiment of the present invention will be described.

[0307] As an example, a hierarchical neural network has one input layer, one or more intermediate layers (hidden layers), and one output layer, and is composed of a total of three or more layers. FIG. 12A shows an example of a hierarchical neural network 100, which has a first layer to an Rth layer (where R can be an integer of 4 or more). In particular, the first layer corresponds to the input layer, the Rth layer corresponds to the output layer, and the other layers correspond to intermediate layers. FIG. 12A shows an excerpt of the (k-1)th layer and the kth layer (where k is an integer of 3 or more and R-1 or less) as intermediate layers.

[0308] Each layer of the neural network 100 has one or more neurons. In FIG. 12A, the first layer is made up of neurons N1 (1) Neuron N p (1) (where p is an integer equal to or greater than 1), and the (k-1)th layer has neurons N1 (k-1) Neuron N m (k-1) (where m is an integer equal to or greater than 1), and the kth layer has neurons N1 (k)Neuron N n (k) (where n is an integer equal to or greater than 1), and the Rth layer has neurons N1 (R) Neuron N q (R) (where q is an integer equal to or greater than 1).

[0309] In addition, in FIG. 12A, neuron N1 (1) , neuron N p (1) , neuron N1 (k-1) , neuron N m (k-1) , neuron N1 (k) , neuron N n (k) , neuron N1 (R) , neuron N q (R) In addition, the (k-1)th layer neuron N i (k-1) (where i is an integer between 1 and m), and the kth layer neuron N j (k) (Here j is an integer between 1 and n.)

[0310] Next, we will explain the transmission of signals from neurons in the previous layer to neurons in the next layer, and the signals input and output to and from each neuron. j (k) We are focusing on:

[0311] FIG. 12B shows the kth layer of neurons N j (k) and neuron N j (k) The input signal to neuron N j (k) 4 shows a signal output from the

[0312] Specifically, the (k-1)th layer neuron N1 (k-1) Neuron N m (k-1) The output signals of each (k-1)~z m (k-1) But neuron N j (k) The output is directed to neuron N j (k) is z1 (k-1) ~z m (k-1) Depending on z j (k) Generate z j (k) is output as an output signal to each neuron in the (k+1)th layer (not shown).

[0313] The degree of signal transmission of a signal input from a neuron in the previous layer to a neuron in the next layer is determined by the connection strength (hereinafter referred to as a weighting coefficient) of the synapse that connects those neurons. In the neural network 100, the product of the signal output from a neuron in the previous layer and the corresponding weighting coefficient is input to a neuron in the next layer. i (k-1) and the kth layer neuron N j (k) The weight coefficient of the synapse between i (k-1) j (k) Then, the kth layer neuron N j (k) The signal input to can be expressed by equation (3.1).

[0314]

number

[0315] That is, the (k-1)th layer neuron N1 (k-1) Neuron N m (k-1) From each of these, the k-th layer neuron N j (k) When a signal is transmitted to the (k-1) ~z m (k-1) The weighting coefficients (w1 (k-1)j (k) Or even w m (k-1) j (k) ) is multiplied by the k-th layer neuron N j (k) For w1 (k-1) j (k) z1 (k-1) Or even w m (k-1) j (k) z m (k-1) At this time, the kth layer neuron N j (k) The sum of the signals input to j (k) becomes equation (3.2).

[0316]

number

[0317] In addition, the weighting factor w1 (k-1) j (k) Or even w m (k-1) j (k) and the neuron's signal z1 (k-1) ~z m (k-1) The result of the multiplication and accumulation of and can be biased. When the bias is b, equation (3.2) can be rewritten as the following equation.

[0318]

number

[0319] Neuron N j (k) u j (k) Depending on j (k) Here, neuron N j (k) Output signal z fromj (k) is defined as follows:

[0320]

number

[0321] The function f(u j (k) ) is an activation function in a hierarchical neural network, and may be a step function, a ReLU function (ramp function), a sigmoid function, or the like. The activation function may be the same for all neurons, or may be different. In addition, the activation functions of neurons may be the same or different for each layer.

[0322] Meanwhile, the signal, weighting coefficient w, or bias b output by the neuron of each layer may be an analog value, a digital value, or a multi-value. The digital value may be, for example, a binary value, and the multi-value may be, for example, a ternary value or more. A value with a larger number of bits may be used. As an example, in the case of an analog value, for example, a ReLU function, a sigmoid function, or the like may be used as an activation function. In the case of a binary digital value, for example, a step function whose output is -1 or 1, or 0 or 1 may be used. In addition, the signal output by the neuron of each layer may be ternary or more. For example, as an activation function that outputs three values, a step function whose output is -1, 0, or 1, or a step function whose output is 0, 1, or 2 may be used. In addition, for example, as an activation function that outputs five values, a step function whose output is -2, -1, 0, 1, or 2 may be used. By using digital values ​​for at least one of the signals, weighting coefficients w, or biases b output by the neurons in each layer, it is possible to reduce the circuit size, reduce power consumption, increase the calculation speed, etc. Also, by using analog values ​​for at least one of the signals, weighting coefficients w, or biases b output by the neurons in each layer, it is possible to improve the accuracy of calculations.

[0323] In neural network 100, when an input signal is input to the first layer (input layer), each layer from the first layer (input layer) to the last layer (output layer) generates an output signal based on the signal input from the previous layer using formula (3.1), formula (3.2) (or formula (3.3)), and formula (3.4), and outputs the output signal to the next layer. The signal output from the last layer (output layer) corresponds to the result of calculation by neural network 100.

[0324] The calculations performed in the first layer (input layer), hidden layer, and last layer (output layer) of the neural network 100 can be performed using the calculation circuits MAC1 to MAC3 described in the first and second embodiments.

[0325] In particular, when it is desired to add a bias to the result of the sum of products as in equation (3.3), the arithmetic circuit MAC2 described in the second embodiment may be used. In this case, the bias b in equation (3.3) is calculated by subtracting I BIAS Equivalent to [1].

[0326] The circuit XLD of the arithmetic circuits MAC1 to MAC3 described in the first and second embodiments can be applied as an example to the input layer described in the present embodiment. Here, the second layer includes a neuron N1 (2) Neuron N r (2) (r is an integer equal to or greater than 1), and consider a case in which a signal is sent from a neuron included in the first layer to a neuron included in the second layer. In this case, the memory cell array CA of the arithmetic circuits MAC1 to MAC3 has memory cells AM arranged in a matrix of p rows and r columns.

[0327] Neuron N in the first layer (input layer) s[1] (1) (s[1] is an integer between 1 and p) is the received signal z s[1](1) is output to all neurons in the second layer (hidden layer). s[1] (1) By setting the potential (second data) output from the circuit XLD, the signal z s[1] (1) can be input to the memory cells AM[s[1],1] to AM[s[1],r] and the memory cell AMr[s[1]] included in the memory cell array CA via the wiring XL[s[1]].

[0328] At this time, a weight coefficient w s[1] (1) s[2] (2) is stored as the first data, so that the second layer (hidden layer) neuron N s[2] (2) At, the signal z s[1] (1) and the weighting factor w s[1] (1) s[2] (2) Specifically, the current I flowing from the wiring BL[s[2]] to the circuit ACTV can be calculated by multiplying and adding it to the sum of the product. S From [s[2]], the signal z s[1] (1) and the weighting factor w s[1] (1) s[2] (2) In addition, the activation function value is calculated from the result of the product sum by the circuit ACTV, and the activation function value is input to the neuron N s[2] (2) Output signal z s[2] (2) and output it from wiring NIL[s[2]].

[0329] Moreover, the arithmetic circuits MAC1 to MAC3 described in the first and second embodiments can be applied as the hidden layer. Here, a case is considered in which a signal is sent from a neuron included in the (k-1)th layer to a neuron included in the kth layer. In this case, the memory cell array CA of the arithmetic circuits MAC1 to MAC3 has memory cells AM arranged in a matrix of m rows and n columns.

[0330] Neuron N in the (k-1)th layer i (k-1) is the signal z i (k-1) The kth layer neuron N1 (k) Neuron N n (k) The signal z i (k-1) By setting the potential (second data) output from the circuit XLD, the signal z i (k-1) can be input to the memory cells AM[i,1] to AM[i,n] and the memory cell AMr[i] included in the memory cell array CA via the wiring XL[i].

[0331] At this time, a weighting coefficient w i (k-1) j (k) is stored as the first data, so that the kth layer neuron N j (k) At, the signal z i (k-1) and the weighting factor w i (k-1) j (k) Specifically, the current I S From [j], signal z i (k-1) and the weighting factor w i (k-1) j (k)In addition, the activation function value is calculated from the result of the product sum by the circuit ACTV, and the activation function value is input to the neuron N j (k) Output signal z j (k) and can be output from the wiring NIL[j].

[0332] Moreover, the arithmetic circuits MAC1 to MAC3 described in the first and second embodiments can be applied to the output layer. Here, the (R-1)th layer includes a neuron N1 (R-1) Neuron N v (R-1) (v is an integer equal to or greater than 1), and consider a case in which a signal is sent from a neuron included in the (R-1)th layer to a neuron included in the Rth layer. In this case, the memory cell array CA of the arithmetic circuits MAC1 to MAC3 has memory cells AM arranged in a matrix of v rows and q columns.

[0333] Neuron N in layer (R-1) s[R-1] (R-1) (s[R-1] is an integer between 1 and v.) s[R-1] (R-1) The Rth layer neuron N1 (R) Neuron N q (R) The signal z s[R-1] (R-1) By setting the potential (second data) output from the circuit XLD, the signal z output from the (R-1)th layer is s[R-1] (R-1) can be input to the memory cells AM[s[R-1],1] to AM[s[R-1],n] and the memory cell AMr[s[R-1]] included in the memory cell array CA via the wiring XL[s[R-1]].

[0334] At this time, a weight coefficient w s[R-1](R-1) s[R] (R) is stored as the first data, so that the Rth layer neuron N s[R] (R) At, the signal z s[R-1] (R-1) and the weighting factor w s[R-1] (R-1) s[R] (R) Specifically, the current I flowing from the wiring BL[s[R]] to the circuit ACTV can be calculated by multiplying and adding it to the sum of the product. S [s[R]] to signal z s[R-1] (R-1) and the weighting factor w s[R-1] (R-1) s[R] (R) In addition, the activation function value is calculated from the result of the product sum by the circuit ACTV, and the activation function value is input to the neuron N in the Rth layer. s[R] (R) Output signal z s[R] (R) and it can be output from the wiring NIL[s[R]].

[0335] Incidentally, in the arithmetic circuit described in this embodiment, the number of rows of the memory cells AM is the number of neurons in the previous layer. In other words, the number of rows of the memory cells AM corresponds to the number of output signals of the neurons in the previous layer that are input to one neuron in the next layer. Also, in the arithmetic circuit described in this embodiment, the number of columns of the memory cells AM is the number of neurons in the next layer. In other words, the number of columns of the memory cells AM corresponds to the number of output signals output from the neurons in the next layer. In other words, the number of rows and columns of the memory cell array of the arithmetic circuit are determined by the number of neurons in the previous layer and the next layer, so the number of rows and columns of the memory cell array may be determined and designed according to the neural network to be configured.

[0336] For example, when the arithmetic circuit MAC1 described in the first embodiment is applied as the hidden layer, the weight coefficient w i (k-1) j (k)is used as the first data, and potentials corresponding to the first data are stored in the memory cells AM of the same column, so that the (k-1)th layer neuron N i (k-1) Output signal z from i (k-1) is used as the second data, and a potential corresponding to the second data is supplied from the circuit XLD to the wiring XL of each row, so that the amount of current I S From signal z i (k-1) and the weighting factor w i (k-1) j (k) The sum of products of the two is calculated, and the ACTV circuit calculates the value of the activation function according to the calculated value. In other words, the activation function is used as a signal to activate the k-th layer neuron N j (k) Output signal z j (k) In addition, the circuit ACTV is configured to output a potential according to the value of the activation function, and the k-th layer neuron N j (k) Output signal z j (k) is input to another arithmetic circuit MAC1, the neuron N output from the (k+1)th layer in the other arithmetic circuit MAC1 is s[k+1] (k+1) (s[k+1] is an integer greater than or equal to 1 and less than or equal to the total number of neurons in the k+1th layer.) s[k+1] (k+1) can be calculated.

[0337] Specifically, the above-mentioned calculation can be performed by using an arithmetic circuit MAC4 shown in Fig. 13. As an example, the arithmetic circuit MAC4 in Fig. 13 has an arithmetic circuit MAC1-1 having a configuration in which the circuit WDD is not provided in the arithmetic circuit MAC1 in Fig. 1, an arithmetic circuit MAC1-2 having a configuration in which the circuit WDD and the circuit XLD are not provided in the arithmetic circuit MAC1 in Fig. 1, and a circuit WDD.

[0338] In the arithmetic circuit MAC1-1, the memory cell array CA1 corresponds to the memory cell array CA of the arithmetic circuit MAC1 in Fig. 1, the circuit CMS1 corresponds to the circuit CMS of the arithmetic circuit MAC1 in Fig. 1, the circuit XLD1 corresponds to the circuit XLD of the arithmetic circuit MAC1 in Fig. 1, the circuit WLD1 corresponds to the circuit WLD of the arithmetic circuit MAC1 in Fig. 1, and the circuit ACTV1 corresponds to the circuit ACTV of the arithmetic circuit MAC1 in Fig. 1. In the arithmetic circuit MAC1-2, the memory cell array CA2 corresponds to the memory cell array CA of the arithmetic circuit MAC1 in Fig. 1, the circuit CMS2 corresponds to the circuit CMS of the arithmetic circuit MAC1 in Fig. 1, the circuit WLD2 corresponds to the circuit WLD of the arithmetic circuit MAC1 in Fig. 1, and the circuit ACTV2 corresponds to the circuit ACTV of the arithmetic circuit MAC1 in Fig. 1.

[0339] In addition, the memory cell array CA1 of the arithmetic circuit MAC1-1 has m×n memory cells AM and m memory cells AMr arranged in a matrix, and the memory cell array CA2 of the arithmetic circuit MAC1-2 has n×t (t is an integer greater than or equal to 1 and is the total number of neurons in the (k+1)th layer) memory cells AM and n memory cells AMr arranged in a matrix.

[0340] 1, wiring BLr1 corresponds to wiring BLr of the arithmetic circuit MAC1 of FIG. 1, wiring XL1[1] to wiring XL1[m] corresponds to wiring XL[1] to wiring XL[m] of the arithmetic circuit MAC1 of FIG. 1, wiring WL1[1] to wiring WL1[m] corresponds to wiring WL[1] to wiring WL[n] of the arithmetic circuit MAC1 of FIG. 1, wiring WD1[1] to wiring WD1[n] corresponds to wiring WD[1] to wiring WD[n] of the arithmetic circuit MAC1 of FIG. 1, wiring WDr1 corresponds to wiring WDr of the arithmetic circuit MAC1 of FIG. 1, and wiring NIL1[1] to wiring NIL1[n] corresponds to wiring NIL to wiring NIL[n] of the arithmetic circuit MAC1 of FIG. 1. In addition, in the arithmetic circuit MAC1-2, wiring BL2[1] to wiring BL2[n] correspond to wiring BL[1] to wiring BL[n] of the arithmetic circuit MAC1 in Figure 1, wiring BLr2 corresponds to wiring BLr of the arithmetic circuit MAC1 in Figure 1, wiring XL2[1] to wiring XL2[n] correspond to wiring XL[1] to wiring XL[m] of the arithmetic circuit MAC1 in Figure 1, wiring WL2[1] to wiring WL2[n] correspond to wiring WL[1] to wiring WL[n] of the arithmetic circuit MAC1 in Figure 1, wiring WD2[1] to wiring WD2[t] correspond to wiring WD[1] to wiring WD[n] of the arithmetic circuit MAC1 in Figure 1, and wiring WDr2 corresponds to wiring WDr of the arithmetic circuit MAC1 in Figure 1.

[0341] Furthermore, the wirings NIL[1] to NIL[n] of the arithmetic circuit MAC1-1 are electrically connected to the wirings XL[1] to XL[n] of the arithmetic circuit MAC1-2, respectively.

[0342] For example, in the arithmetic circuit MAC1-1 of FIG. 13, the weight coefficient between the neuron in the (k-1)th layer and the neuron in the kth layer is stored as the first data in the memory cells AM[1,1] to AM[m,n] of the memory cell array CA1, and the neuron N s[k-1] (k-1) Output signal z from s[k-1] (k-1)The second data is used to supply a potential corresponding to the second data from the circuit XLD1 to the wiring XL1 of each row, so that the k-th layer neuron N1 (k) Neuron N n (k) Output signal z1 (k) ~z n (k) The output signal z1 (k) ~z n (k) Each value can be expressed as a potential output from the circuit ACTV1 to the wirings NIL1[1] to NIL1[n], respectively.

[0343] Here, in the arithmetic circuit MAC1-2 of FIG. 13, the weight coefficient between the neuron in the kth layer and the neuron in the (k+1)th layer is stored as the first data in the memory cells AM[1,1] to AM[n,t] of the memory cell array CA2, and the potential supplied to the wiring XL2 of each row, that is, the neuron N1 in the kth layer, is stored as the first data. (k) Neuron N n (k) Output signal z1 (k) ~z n (k) By using the second data, the (k+1)th layer neuron N1 (k+1) Neuron N t (k+1) Each output signal z1 (k+1) ~z t (k+1) The output signal z1 (k+1) ~z n (k+1) Each value can be expressed as a potential output from the circuit ACTV2 to each of the wirings NIL2[1] to NIL2[n].

[0344] In the arithmetic circuit MAC4 in FIG. 13, the wirings WD1[1] to WD1[n] and the wirings WD2[1] to WD2[t] are illustrated, but the wirings arranged in the same column may be combined into one wiring. For example, the wirings WD1[1] and WD2[1] may be combined into one wiring, or, for example, when n is smaller than t, the wirings WD1[n] and WD2[n] may be combined into one wiring, or, for example, when n is larger than t, the wirings WD1[t] and WD2[t] may be combined into one wiring. Similarly, the wirings WDr1 and WDr2 may be combined into one wiring. As described above, by combining the wirings WD1 and WD2 into one wiring, the number of wirings that transmit the first data can be reduced, and therefore the number of driving circuits required for each wiring included in the circuit WDD can be reduced. In other words, the circuit area of ​​the circuit WDD can be reduced.

[0345] As described above, the arithmetic circuits MAC1 to MAC3 can determine the number of rows and columns of the memory cell array CA according to the scale of the hierarchical neural network. Also, by using at least one of the arithmetic circuits MAC1 to MAC3 and connecting them as shown in Fig. 13, it is possible to perform an operation according to the number of layers of the hierarchical neural network.

[0346] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0347] (Embodiment 4) In this embodiment, a structural example of the semiconductor device described in the above embodiment and a structural example of a transistor that can be applied to the semiconductor device will be described.

[0348] <Example of semiconductor device configuration> The semiconductor device shown in Fig. 14 includes a transistor 300, a transistor 500, and a capacitor 600. Fig. 16A is a cross-sectional view of the transistor 500 in the channel length direction, Fig. 16B is a cross-sectional view of the transistor 500 in the channel width direction, and Fig. 16C is a cross-sectional view of the transistor 300 in the channel width direction.

[0349] The transistor 500 is a transistor having a metal oxide in a channel formation region (OS transistor). The transistor 500 has a characteristic of having a small off-state current and a field-effect mobility that does not change even at high temperatures. By applying the transistor 500 to a semiconductor device, such as a transistor included in the arithmetic circuit MAC1, the arithmetic circuit MAC2, the arithmetic circuit MAC3, or the arithmetic circuit MAC4 described in the above embodiment, a semiconductor device whose operation performance is not degraded even at high temperatures can be realized. In particular, by utilizing the characteristic of having a small off-state current and applying the transistor 500 to, for example, the transistor Tr11 of the arithmetic circuit MAC1, a potential written to the first terminal of the capacitor C1 of the memory cell can be held for a long time.

[0350] 14, the transistor 500 is provided above the transistor 300, for example, and the capacitor 600 is provided above the transistor 300 and the transistor 500, for example. The capacitor 600 can be a capacitor included in the arithmetic circuit MAC1, the arithmetic circuit MAC2, the arithmetic circuit MAC3, the arithmetic circuit MAC4, or the like described in the above embodiment. Depending on the circuit configuration, the capacitor 600 shown in FIG. 14 is not necessarily provided.

[0351] The transistor 300 is provided over a substrate 311 and includes a conductor 316, an insulator 315, a semiconductor region 313 formed of a part of the substrate 311, and a low-resistance region 314a and a low-resistance region 314b functioning as a source region or a drain region. Note that the transistor 300 can be applied to, for example, a transistor included in the arithmetic circuit MAC1, the arithmetic circuit MAC2, the arithmetic circuit MAC3, the arithmetic circuit MAC4, and the like described in the above embodiment. Specifically, the transistor 300 can be, for example, a transistor Tr12 included in the arithmetic circuit MAC1. The transistor 300 can also be, for example, a transistor included in the circuit ACTV. Note that Figure 14 shows a configuration in which the gate of the transistor 300 is electrically connected to one of the source or drain of the transistor 500 via one of a pair of electrodes of the capacitor 600; however, depending on the configuration of the arithmetic circuit MAC1, arithmetic circuit MAC2, arithmetic circuit MAC3, arithmetic circuit MAC4, etc., one of the source or drain of the transistor 300 may be electrically connected to one of the source or drain of the transistor 500 via one of a pair of electrodes of the capacitor 600, or one of the source or drain of the transistor 300 may be electrically connected to the gate of the transistor 500 via one of a pair of electrodes of the capacitor 600, or each terminal of the transistor 300 may not be electrically connected to each terminal of the transistor 500 or each terminal of the capacitor 600.

[0352] Moreover, as the substrate 311, it is preferable to use a semiconductor substrate (for example, a single crystal substrate or a silicon substrate).

[0353] 16C, the upper surface and the side surface in the channel width direction of the semiconductor region 313 of the transistor 300 are covered with a conductor 316 via an insulator 315. By forming the transistor 300 as a fin type in this manner, the effective channel width is increased, thereby improving the on-characteristics of the transistor 300. In addition, the contribution of the electric field of the gate electrode can be increased, thereby improving the off-characteristics of the transistor 300.

[0354] The transistor 300 may be either a p-channel type or an n-channel type.

[0355] The region where the channel of the semiconductor region 313 is formed, the region nearby, the low resistance region 314a which becomes the source region or the drain region, and the low resistance region 314b preferably contain a semiconductor such as a silicon-based semiconductor, and preferably contain single crystal silicon. Alternatively, they may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), GaN (gallium nitride), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be used. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs and GaAlAs, or the like.

[0356] The low resistance region 314a and the low resistance region 314b contain, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0357] The conductor 316 functioning as the gate electrode can be made of a conductive material such as a semiconductor material, such as silicon, containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron, a metal material, an alloy material, or a metal oxide material.

[0358] Since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use materials such as titanium nitride and tantalum nitride for the conductor. Furthermore, in order to achieve both electrical conductivity and embeddability, it is preferable to use metal materials such as tungsten and aluminum as the conductor in a laminated state, and in particular, it is preferable to use tungsten in terms of heat resistance.

[0359] 14 is just an example and is not limited to the structure, and an appropriate transistor may be used depending on the circuit configuration, driving method, and the like. For example, when the semiconductor device is a unipolar circuit including only OS transistors, the structure of the transistor 300 may be similar to that of a transistor 500 including an oxide semiconductor, as shown in FIG 15. Details of the transistor 500 will be described later.

[0360] In FIG. 15, the transistor 300 is provided on a substrate 312. In this case, the substrate 312 may be a semiconductor substrate similar to the substrate 311 of the semiconductor device in FIG. 14. The substrate 312 may be, for example, an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate having stainless steel foil, a tungsten substrate, a substrate having tungsten foil, a flexible substrate, a laminated film, paper containing a fibrous material, or a base film. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, and soda lime glass. Examples of flexible substrates, laminated films, and base films include the following. For example, there are plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Alternatively, there is, for example, a synthetic resin such as acrylic. Alternatively, examples include polypropylene, polyester, polyvinyl fluoride, polyvinyl chloride, etc. Alternatively, examples include polyamide, polyimide, aramid, epoxy resin, inorganic vapor deposition film, paper, etc.

[0361] An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order over the transistor 300.

[0362] As the insulators 320, 322, 324, and 326, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like can be used.

[0363] In this specification, silicon oxynitride refers to a material having a higher oxygen content than nitrogen, silicon nitride oxide refers to a material having a higher nitrogen content than oxygen, aluminum oxynitride refers to a material having a higher oxygen content than nitrogen, and aluminum nitride oxide refers to a material having a higher nitrogen content than oxygen.

[0364] The insulator 322 may function as a planarizing film that planarizes steps caused by the transistor 300 provided thereunder. For example, the top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve the planarity.

[0365] The insulator 324 is preferably a film having a barrier property that prevents diffusion of hydrogen, impurities, and the like from the substrate 311 or the transistor 300 to a region where the transistor 500 is provided.

[0366] As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element having an oxide semiconductor such as the transistor 500, the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 500 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film that releases a small amount of hydrogen.

[0367] The amount of desorption of hydrogen can be analyzed, for example, by using thermal desorption spectrometry (TDS). For example, the amount of desorption of hydrogen from the insulator 324 is calculated as 10×10 per area of ​​the insulator 324 when the surface temperature of the film is in the range of 50° C. to 500° C. in the TDS analysis. 15 atoms / cm 2 Less than or equal to 5×10 15 atoms / cm 2 The following is acceptable.

[0368] The insulator 326 preferably has a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. For example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced.

[0369] A conductor 328, a conductor 330, and the like that connect to the capacitor 600 or the transistor 500 are embedded in the insulator 320, the insulator 322, the insulator 324, and the insulator 326. The conductor 328 and the conductor 330 function as a plug or a wiring. In addition, a plurality of conductors that function as a plug or a wiring may be collectively given the same reference symbol. In this specification and the like, a wiring and a plug connected to the wiring may be integrated. That is, there are cases where a part of a conductor functions as a wiring and a case where a part of a conductor functions as a plug.

[0370] As the material for each plug and wiring (conductor 328, conductor 330, etc.), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used in a single layer or a laminated layer. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferable to form the wiring from a low resistance conductive material such as aluminum or copper. By using a low resistance conductive material, it is possible to reduce the wiring resistance.

[0371] A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 14 , an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. A conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring connected to the transistor 300. Note that the conductor 356 can be provided using a material similar to that of the conductor 328 and the conductor 330.

[0372] Note that, for example, the insulator 350 is preferably an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 356 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 350 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0373] Note that, for example, tantalum nitride or the like may be used as the conductor having a barrier property against hydrogen. By stacking tantalum nitride and tungsten having high conductivity, it is possible to suppress diffusion of hydrogen from the transistor 300 while maintaining the conductivity of the wiring. In this case, a structure in which the tantalum nitride layer having a barrier property against hydrogen is in contact with the insulator 350 having a barrier property against hydrogen is preferable.

[0374] A wiring layer may be provided over the insulator 354 and the conductor 356. For example, in FIG. 14, an insulator 360, an insulator 362, and an insulator 364 are stacked in this order. A conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364. The conductor 366 functions as a plug or a wiring. The conductor 366 can be provided using a material similar to that of the conductor 328 and the conductor 330.

[0375] Note that, for example, the insulator 360 is preferably an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 366 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 360 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0376] A wiring layer may be provided over the insulator 364 and the conductor 366. For example, in FIG. 14, an insulator 370, an insulator 372, and an insulator 374 are stacked in this order. A conductor 376 is formed in the insulator 370, the insulator 372, and the insulator 374. The conductor 376 functions as a plug or a wiring. Note that the conductor 376 can be provided using a material similar to that of the conductor 328 and the conductor 330.

[0377] Note that, for example, the insulator 370 is preferably an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 376 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 370 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0378] A wiring layer may be provided over the insulator 374 and the conductor 376. For example, in FIG. 14, an insulator 380, an insulator 382, ​​and an insulator 384 are stacked in this order. A conductor 386 is formed in the insulator 380, the insulator 382, ​​and the insulator 384. The conductor 386 functions as a plug or a wiring. Note that the conductor 386 can be provided using a material similar to that of the conductor 328 and the conductor 330.

[0379] Note that, for example, the insulator 380 is preferably an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 386 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 380 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0380] In the above, a wiring layer including the conductor 356, a wiring layer including the conductor 366, a wiring layer including the conductor 376, and a wiring layer including the conductor 386 have been described, but the semiconductor device of this embodiment is not limited to this. There may be three or fewer wiring layers similar to the wiring layer including the conductor 356, or there may be five or more wiring layers similar to the wiring layer including the conductor 356.

[0381] An insulator 510, an insulator 512, an insulator 514, and an insulator 516 are stacked in this order on the insulator 384. Any of the insulator 510, the insulator 512, the insulator 514, and the insulator 516 is preferably made of a substance that has a barrier property against oxygen, hydrogen, and the like.

[0382] For example, the insulator 510 and the insulator 514 are preferably formed using a film having a barrier property that prevents hydrogen, impurities, and the like from diffusing from the substrate 311 or a region where the transistor 300 is provided to a region where the transistor 500 is provided. Therefore, a material similar to that of the insulator 324 can be used.

[0383] As an example of a film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element having an oxide semiconductor such as the transistor 500, the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 500 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film that releases a small amount of hydrogen.

[0384] As a film having a barrier property against hydrogen, for example, the insulator 510 and the insulator 514 are preferably made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0385] In particular, aluminum oxide has a high blocking effect of preventing the film from permeating both oxygen and impurities such as hydrogen and moisture, which are factors that cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. In addition, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0386] For example, the insulator 512 and the insulator 516 can be formed using a material similar to that of the insulator 320. By using a material with a relatively low dielectric constant for these insulators, parasitic capacitance between wirings can be reduced. For example, the insulator 512 and the insulator 516 can be formed using a silicon oxide film, a silicon oxynitride film, or the like.

[0387] A conductor 518, a conductor constituting the transistor 500 (for example, the conductor 503), and the like are embedded in the insulator 510, the insulator 512, the insulator 514, and the insulator 516. Note that the conductor 518 functions as a plug or a wiring connected to the capacitor 600 or the transistor 300. The conductor 518 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0388] In particular, the insulator 510 and the conductor 518 in the region in contact with the insulator 514 are preferably conductors having barrier properties against oxygen, hydrogen, and water. With this structure, the transistors 300 and 500 can be separated by a layer having barrier properties against oxygen, hydrogen, and water, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0389] Above the insulator 516 is a transistor 500 .

[0390] As shown in Figures 16A and 16B, the transistor 500 has a conductor 503 arranged so as to be embedded in the insulator 514 and the insulator 516, an insulator 520 arranged on the insulator 516 and the conductor 503, an insulator 522 arranged on the insulator 520, an insulator 524 arranged on the insulator 522, an oxide 530a arranged on the insulator 524, an oxide 530b arranged on the oxide 530a, a conductor 542a and a conductor 542b arranged apart from each other on the oxide 530b, an insulator 580 arranged on the conductor 542a and the conductor 542b and having an opening formed therein overlapping between the conductor 542a and the conductor 542b, an oxide 530c arranged on the bottom and side surfaces of the opening, an insulator 550 arranged on the formation surface of the oxide 530c, and a conductor 560 arranged on the formation surface of the insulator 550. In this specification, conductor 542a and conductor 542b are collectively referred to as conductor 542.

[0391] 16A and 16B, it is preferable that an insulator 544 is disposed between the oxide 530a, the oxide 530b, the conductor 542a, and the conductor 542b and the insulator 580. It is preferable that the conductor 560 has a conductor 560a provided inside the insulator 550 and a conductor 560b provided so as to be embedded inside the conductor 560a, as shown in FIGS. 16A and 16B. It is preferable that an insulator 574 is disposed on the insulator 580, the conductor 560, and the insulator 550, as shown in FIGS. 16A and 16B.

[0392] In the following, oxide 530a, oxide 530b, and oxide 530c may be collectively referred to as oxide 530.

[0393] Note that in the transistor 500, a three-layer structure of the oxide 530a, the oxide 530b, and the oxide 530c is illustrated in a region where a channel is formed and in the vicinity thereof; however, one embodiment of the present invention is not limited thereto. For example, a single layer of the oxide 530b, a two-layer structure of the oxide 530b and the oxide 530a, a two-layer structure of the oxide 530b and the oxide 530c, or a stacked structure of four or more layers may be provided. In addition, in the transistor 500, the conductor 560 is illustrated as having a two-layer structure; however, one embodiment of the present invention is not limited thereto. For example, the conductor 560 may have a single-layer structure or a stacked structure of three or more layers. The transistor 500 illustrated in FIGS. 14, 16A, and 16B is merely an example, and the present invention is not limited to the structure. An appropriate transistor may be used depending on the circuit configuration, the driving method, and the like.

[0394] Here, the conductor 560 functions as a gate electrode of the transistor, and the conductors 542a and 542b function as a source electrode and a drain electrode, respectively. As described above, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and in the region sandwiched between the conductors 542a and 542b. The arrangement of the conductors 560, 542a, and 542b is selected in a self-aligned manner with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be arranged in a self-aligned manner between the source electrode and the drain electrode. Therefore, the conductor 560 can be formed without providing a margin for alignment, so that the area occupied by the transistor 500 can be reduced. This allows the semiconductor device to be miniaturized and highly integrated.

[0395] Furthermore, since the conductor 560 is formed in a self-aligned manner in the region between the conductor 542a and the conductor 542b, the conductor 560 does not have a region overlapping with the conductor 542a or the conductor 542b. This makes it possible to reduce the parasitic capacitance formed between the conductor 560 and the conductor 542a and between the conductor 560 and the conductor 542b. As a result, the switching speed of the transistor 500 can be improved, and high frequency characteristics can be achieved.

[0396] The conductor 560 may function as a first gate (also referred to as a top gate) electrode. The conductor 503 may function as a second gate (also referred to as a bottom gate) electrode. In this case, the threshold voltage of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560. In particular, by applying a negative potential to the conductor 503, the threshold voltage of the transistor 500 can be made higher than 0 V, and the off-current can be reduced. Therefore, applying a negative potential to the conductor 503 can reduce the drain current when the potential applied to the conductor 560 is 0 V, compared to when a negative potential is not applied.

[0397] The conductor 503 is disposed so as to overlap the oxide 530 and the conductor 560. In this manner, when a potential is applied to the conductor 560 and the conductor 503, an electric field generated from the conductor 560 and an electric field generated from the conductor 503 are connected, and a channel formation region formed in the oxide 530 can be covered. In this specification and the like, a transistor structure in which a channel formation region is electrically surrounded by the electric fields of the first gate electrode and the second gate electrode is referred to as a surrounded channel (S-channel) structure.

[0398] The conductor 503 has a structure similar to that of the conductor 518, and the conductor 503a is formed in contact with the inner walls of the openings of the insulator 514 and the insulator 516, and the conductor 503b is formed further inward. Note that although the transistor 500 has a structure in which the conductor 503a and the conductor 503b are stacked, one embodiment of the present invention is not limited to this. For example, the conductor 503 may have a single layer structure or a stacked structure of three or more layers.

[0399] Here, the conductor 503a is preferably made of a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the impurities are less likely to permeate through). Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (the oxygen is less likely to permeate through). Note that in this specification, the function of suppressing the diffusion of impurities or oxygen refers to the function of suppressing the diffusion of any one or all of the impurities or the oxygen.

[0400] For example, the conductor 503a has a function of suppressing the diffusion of oxygen, so that the conductor 503b can be prevented from being oxidized and the conductivity from decreasing.

[0401] In addition, when the conductor 503 also functions as a wiring, it is preferable that the conductor 503b is made of a highly conductive material mainly composed of tungsten, copper, or aluminum. In addition, when the conductivity of the wiring can be maintained high, the conductor 503a is not necessarily provided. Although the conductor 503b is illustrated as a single layer, it may have a laminated structure, for example, a laminate of titanium or titanium nitride and the above-mentioned conductive material.

[0402] The insulators 520, 522, and 524 function as a second gate insulating film.

[0403] Here, the insulator 524 in contact with the oxide 530 is preferably an insulator containing more oxygen than the oxygen required for the stoichiometric composition. That is, an excess oxygen region is preferably formed in the insulator 524. By providing such an insulator containing excess oxygen in contact with the oxide 530, oxygen vacancies in the oxide 530 can be reduced and the reliability of the transistor 500 can be improved.

[0404] Specifically, it is preferable to use an oxide material from which some oxygen is released by heating as an insulator having an excess oxygen region. An oxide material from which oxygen is released by heating is an oxide material from which the amount of released oxygen converted into oxygen atoms is 1.0×10 18 atoms / cm 3 More than 1.0×10 19 atoms / cm 3 More preferably, 2.0×10 19 atoms / cm 3 or more than 3.0 x 10 20 atoms / cm 3 The oxide film is one having the above-mentioned properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100° C. or higher and 700° C. or lower, or 100° C. or higher and 400° C. or lower.

[0405] In addition, the oxide 530 may be brought into contact with the insulator having the excess oxygen region and subjected to one or more of heat treatment, microwave treatment, and RF treatment. By carrying out such treatment, water or hydrogen in the oxide 530 can be removed. For example, a reaction occurs in the oxide 530 that breaks the bond of VoH, in other words, "V O H→V O A reaction of "H + H" occurs, resulting in dehydrogenation. Some of the hydrogen generated at this time may combine with oxygen to form HO and be removed from the oxide 530 or the insulator near the oxide 530. Some of the hydrogen may also be diffused or captured (also referred to as gettering) in the conductor 542a and the conductor 542b.

[0406] In addition, the microwave treatment is preferably performed using, for example, a device having a power source that generates high-density plasma or a device having a power source that applies RF to the substrate side. For example, high-density oxygen radicals can be generated by using a gas containing oxygen and high-density plasma, and the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 530 or an insulator near the oxide 530 by applying RF to the substrate side. In addition, the pressure of the microwave treatment may be set to 133 Pa or more, preferably 200 Pa or more, and more preferably 400 Pa or more. In addition, for example, oxygen and argon are used as gases to be introduced into the microwave treatment device, and the oxygen flow rate ratio (O2 / (O2+Ar)) is 50% or less, preferably 10% or more and 30% or less.

[0407] In addition, in a manufacturing process of the transistor 500, it is preferable to perform heat treatment while the surface of the oxide 530 is exposed. The heat treatment may be performed, for example, at a temperature of 100° C. or higher and 450° C. or lower, more preferably 350° C. or higher and 400° C. or lower. Note that the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher. For example, the heat treatment is preferably performed in an oxygen atmosphere. In this way, oxygen is supplied to the oxide 530 to reduce oxygen deficiencies (V O) can be reduced. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to compensate for the desorbed oxygen after the heat treatment in a nitrogen gas or inert gas atmosphere. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to compensate for the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in succession to a heat treatment in a nitrogen gas or inert gas atmosphere.

[0408] In addition, by subjecting the oxide 530 to an oxygen supplying treatment, the oxygen vacancies in the oxide 530 are repaired by the supplied oxygen. In other words, O In addition, the reaction of the hydrogen remaining in the oxide 530 with the supplied oxygen can be removed as H2O (dehydration). As a result, the hydrogen remaining in the oxide 530 recombines with the oxygen vacancies to form V O The formation of H can be suppressed.

[0409] When the insulator 524 has an excess oxygen region, it is preferable that the insulator 522 has a function of suppressing the diffusion of oxygen (eg, oxygen atoms, oxygen molecules, etc.) (the oxygen is less likely to permeate).

[0410] The insulator 522 preferably has a function of suppressing diffusion of oxygen, impurities, and the like, so that oxygen contained in the oxide 530 does not diffuse toward the insulator 520. Furthermore, reaction of the conductor 503 with oxygen contained in the insulator 524 and the oxide 530 can be suppressed.

[0411] The insulator 522 is preferably a single layer or a multilayer insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more highly integrated, problems such as leakage current may occur due to the thinning of the gate insulating film. By using a high-k material for the insulator that functions as the gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0412] In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials having a function of suppressing diffusion of impurities and oxygen (the oxygen is unlikely to permeate through them). As an insulator containing an oxide of one or both of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like. When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses release of oxygen from the oxide 530 and the intrusion of impurities such as hydrogen into the oxide 530 from the periphery of the transistor 500.

[0413] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulators.

[0414] In addition, it is preferable that the insulator 520 is thermally stable. For example, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In addition, by combining a high-k insulator with silicon oxide or silicon oxynitride, it is possible to obtain the insulator 520 having a thermally stable laminated structure with a high relative dielectric constant.

[0415] 16A and 16B, the insulator 520, the insulator 522, and the insulator 524 are illustrated as the second gate insulating film having a stacked structure of three layers, but the second gate insulating film may have a single layer, a two-layer, or a stacked structure of four or more layers. In this case, the second gate insulating film is not limited to a stacked structure made of the same material, and may be a stacked structure made of different materials.

[0416] In the transistor 500, it is preferable to use a metal oxide functioning as an oxide semiconductor for the oxide 530 including the channel formation region. For example, a metal oxide such as In-M-Zn oxide (wherein the element M is one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used as the oxide 530. In particular, it is preferable that the In-M-Zn oxide applicable to the oxide 530 is CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) or CAC-OS (Cloud-Aligned Composite Oxide Semiconductor). In addition, In-Ga oxide, In-Zn oxide, In oxide, etc. may be used as the oxide 530.

[0417] In addition, it is preferable to use a metal oxide with a low carrier concentration for the transistor 500. In order to reduce the carrier concentration of the metal oxide, the impurity concentration in the metal oxide may be reduced to reduce the defect state density. In this specification and the like, a low impurity concentration and a low defect state density are referred to as high purity intrinsic or substantially high purity intrinsic. Note that examples of impurities in the metal oxide include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0418] In particular, hydrogen contained in the metal oxide reacts with oxygen that bonds with the metal atom to form water, which may cause oxygen vacancies in the metal oxide. In addition, when hydrogen enters an oxygen vacancy in the oxide 530, the oxygen vacancy and hydrogen combine to form V O May form H. V O H functions as a donor and may generate electrons as carriers. In addition, some of the hydrogen may bond with oxygen that bonds with metal atoms to generate electrons as carriers. Therefore, a transistor using a metal oxide containing a large amount of hydrogen is likely to have normally-on characteristics. In addition, hydrogen in a metal oxide is easily mobile due to stress such as heat or an electric field, so if a metal oxide contains a large amount of hydrogen, the reliability of the transistor may be deteriorated. In one embodiment of the present invention, V in the oxide 530 O It is preferable to reduce H as much as possible and make it high-purity intrinsic or substantially high-purity intrinsic. O In order to obtain a metal oxide with a sufficiently reduced amount of H, it is important to remove impurities such as water and hydrogen from the metal oxide (sometimes referred to as dehydration or dehydrogenation treatment) and to supply oxygen to the metal oxide to compensate for the oxygen deficiency (sometimes referred to as oxygen addition treatment). O By using a metal oxide in which impurities such as H are sufficiently reduced for the channel formation region of a transistor, stable electrical characteristics can be obtained.

[0419] A defect in which hydrogen has entered an oxygen vacancy can function as a donor for a metal oxide. However, it is difficult to quantitatively evaluate the defect. Therefore, in a metal oxide, the carrier concentration may be used instead of the donor concentration. Therefore, in this specification, the carrier concentration assuming a state in which no electric field is applied may be used as a parameter of the metal oxide, instead of the donor concentration. In other words, the "carrier concentration" described in this specification may be rephrased as the "donor concentration".

[0420] Therefore, when a metal oxide is used for the oxide 530, it is preferable that hydrogen in the metal oxide is reduced as much as possible. Specifically, in the metal oxide, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5×10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 By using a metal oxide in which impurities such as hydrogen are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0421] In addition, when a metal oxide is used for the oxide 530, the metal oxide is a semiconductor that has a wide band gap and is intrinsic (also called I-type) or substantially intrinsic, and the carrier concentration of the metal oxide in the channel formation region is 1×10 18 cm -3 Preferably less than 1×10 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 The lower limit of the carrier concentration of the metal oxide in the channel formation region is not particularly limited, but is preferably, for example, 1×10 -9 cm -3 It can be said that:

[0422] Furthermore, when a metal oxide is used for the oxide 530, when the conductors 542a and 542b come into contact with the oxide 530, oxygen in the oxide 530 may diffuse to the conductors 542a and 542b, and the conductors 542a and 542b may be oxidized. When the conductors 542a and 542b are oxidized, the conductivity of the conductors 542a and 542b is likely to decrease. The diffusion of oxygen in the oxide 530 to the conductors 542a and 542b can be expressed in other words as the conductors 542a and 542b absorbing the oxygen in the oxide 530.

[0423] Furthermore, oxygen in the oxide 530 may diffuse into the conductor 542a and the conductor 542b, forming a heterogeneous layer between the conductor 542a and the oxide 530b and between the conductor 542b and the oxide 530b. Since the heterogeneous layer contains more oxygen than the conductor 542a and the conductor 542b, it is presumed that the heterogeneous layer has insulating properties. In this case, the three-layer structure of the conductor 542a or the conductor 542b, the heterogeneous layer, and the oxide 530b can be regarded as a three-layer structure made of a metal-insulator-semiconductor, and may be referred to as a metal-insulator-semiconductor (MIS) structure or a diode junction structure mainly based on the MIS structure.

[0424] Note that the above-mentioned different layer is not limited to being formed between conductor 542a and conductor 542b and oxide 530b. For example, the different layer may be formed between conductor 542a and conductor 542b and oxide 530c, between conductor 542a and conductor 542b and oxide 530b, or between conductor 542a and conductor 542b and oxide 530c.

[0425] The metal oxide that functions as a channel formation region in the oxide 530 preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. In this manner, by using a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0426] The oxide 530 has the oxide 530a below the oxide 530b, so that the diffusion of impurities from structures formed below the oxide 530a to the oxide 530b can be suppressed. Also, the oxide 530 has the oxide 530c on the oxide 530b, so that the diffusion of impurities from structures formed above the oxide 530c to the oxide 530b can be suppressed.

[0427] The oxide 530 preferably has a laminated structure of a plurality of oxide layers having different atomic ratios of metal atoms. Specifically, in the metal oxide used for the oxide 530a, the atomic ratio of element M among the constituent elements is preferably larger than the atomic ratio of element M among the constituent elements in the metal oxide used for the oxide 530b. In addition, in the metal oxide used for the oxide 530a, the atomic ratio of element M to In is preferably larger than the atomic ratio of element M to In in the metal oxide used for the oxide 530b. In addition, in the metal oxide used for the oxide 530b, the atomic ratio of In to element M is preferably larger than the atomic ratio of In to element M in the metal oxide used for the oxide 530a. In addition, the oxide 530c can use a metal oxide that can be used for the oxide 530a or the oxide 530b.

[0428] Specifically, the oxide 530a may be a metal oxide having an atomic ratio of In, Ga, and Zn of In:Ga:Zn=1:3:4 or 1:1:0.5. The oxide 530b may be a metal oxide having an atomic ratio of In, Ga, and Zn of In:Ga:Zn=4:2:3 or 1:1:1. The oxide 530c may be a metal oxide having an atomic ratio of In, Ga, and Zn of In:Ga:Zn=1:3:4 and an atomic ratio of Ga and Zn of Ga:Zn=2:1 or Ga:Zn=2:5. Specific examples of the oxide 530c having a layered structure include layered structures in which the atomic ratios of In, Ga, and Zn are In:Ga:Zn=4:2:3 and In:Ga:Zn=1:3:4, layered structures in which the atomic ratios of Ga and Zn are Ga:Zn=2:1 and In:Ga:Zn=4:2:3, layered structures in which the atomic ratios of Ga and Zn are Ga:Zn=2:5 and In:Ga:Zn=4:2:3, and layered structures in which gallium oxide and the atomic ratio of In, Ga, and Zn are In:Ga:Zn=4:2:3.

[0429] Furthermore, for example, when the atomic ratio of In to element M in the metal oxide used for oxide 530a is smaller than the atomic ratio of In to element M in the metal oxide used for oxide 530b, an In-Ga-Zn oxide having an atomic ratio of In, Ga, and Zn of In:Ga:Zn=5:1:6 or thereabouts, In:Ga:Zn=5:1:3 or thereabouts, In:Ga:Zn=10:1:3 or thereabouts, or the like, can be used as oxide 530b.

[0430] In addition to the compositions described above, the oxide 530b may be a metal oxide having a composition of In:Zn=2:1, a composition of In:Zn=5:1, a composition of In:Zn=10:1, or a composition close to any one of these.

[0431] It is preferable to combine these oxides 530a, 530b, and 530c while satisfying the above-mentioned atomic ratio relationship. For example, it is preferable to use metal oxides having a composition of In:Ga:Zn=1:3:4 for the oxides 530a and 530c, and metal oxides having a composition of In:Ga:Zn=4:2:3 to 4.1 for the oxides 530b. The above composition indicates the atomic ratio in the oxide formed on the substrate, or the atomic ratio in the sputtering target. In addition, it is preferable to increase the ratio of In in the composition of the oxide 530b, since this can increase the on-current or field effect mobility of the transistor.

[0432] In addition, the energy of the conduction band minimum of the oxide 530a and the oxide 530c is preferably higher than that of the oxide 530b. In other words, the electron affinity of the oxide 530a and the oxide 530c is preferably smaller than that of the oxide 530b.

[0433] Here, the energy level of the conduction band minimum changes gradually at the junction of the oxide 530a, the oxide 530b, and the oxide 530c. In other words, it can be said that the energy level of the conduction band minimum at the junction of the oxide 530a, the oxide 530b, and the oxide 530c changes continuously or is a continuous junction. To achieve this, it is preferable to reduce the defect level density of the mixed layer formed at the interface between the oxide 530a and the oxide 530b and the interface between the oxide 530b and the oxide 530c.

[0434] Specifically, the oxides 530a and 530b, and the oxides 530b and 530c have a common element other than oxygen (as a main component), so that a mixed layer with a low density of defect states can be formed. For example, when the oxide 530b is an In-Ga-Zn oxide, the oxides 530a and 530c may be made of an In-Ga-Zn oxide, a Ga-Zn oxide, or a gallium oxide.

[0435] At this time, the main carrier path is the oxide 530b. By configuring the oxide 530a and the oxide 530c as described above, the defect state density at the interface between the oxide 530a and the oxide 530b and at the interface between the oxide 530b and the oxide 530c can be reduced. Therefore, the effect of interface scattering on carrier conduction is reduced, and the transistor 500 can obtain a high on-state current.

[0436] Conductors 542a and 542b functioning as a source electrode and a drain electrode are provided on the oxide 530b. As the conductors 542a and 542b, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are conductive materials that are difficult to oxidize, or materials that maintain conductivity even when oxygen is absorbed, and are therefore preferable.Furthermore, metal nitride films such as tantalum nitride are preferable because they have barrier properties against hydrogen or oxygen.

[0437] 16A and 16B, the conductor 542a and the conductor 542b are shown as a single-layer structure, but may be a laminated structure of two or more layers. For example, a tantalum nitride film and a tungsten film may be laminated. A titanium film and an aluminum film may be laminated. A two-layer structure in which an aluminum film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, or a two-layer structure in which a copper film is laminated on a tungsten film may be used.

[0438] In addition, there are three-layer structures in which a titanium film or titanium nitride film is laminated on the titanium film or titanium nitride film, an aluminum film or copper film is laminated on the titanium film or titanium nitride film, and a titanium film or titanium nitride film is further formed thereon, and a three-layer structure in which a molybdenum film or molybdenum nitride film is laminated on the molybdenum film or molybdenum nitride film, an aluminum film or copper film is laminated on the molybdenum film or molybdenum nitride film, and a molybdenum film or molybdenum nitride film is further formed thereon, etc. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

[0439] 16A, regions 543a and 543b may be formed as low-resistance regions at and near the interface of the oxide 530 with the conductor 542a (conductor 542b). In this case, the region 543a functions as one of the source region and the drain region, and the region 543b functions as the other of the source region and the drain region. A channel formation region is formed in a region sandwiched between the regions 543a and 543b.

[0440] By providing the conductor 542a (conductor 542b) so as to be in contact with the oxide 530, the oxygen concentration in the region 543a (region 543b) may be reduced. Also, a metal compound layer containing a metal contained in the conductor 542a (conductor 542b) and a component of the oxide 530 may be formed in the region 543a (region 543b). In such a case, the carrier concentration in the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low-resistance region.

[0441] The insulator 544 is provided to cover the conductor 542a and the conductor 542b and suppresses oxidation of the conductor 542a and the conductor 542b. In this case, the insulator 544 may be provided to cover the side surfaces of the oxide 530 and the insulator 524 and to be in contact with the insulator 522.

[0442] The insulator 544 can be a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium, etc. Alternatively, the insulator 544 can be silicon nitride oxide, silicon nitride, or the like.

[0443] In particular, it is preferable to use, as the insulator 544, an insulator containing an oxide of either or both of aluminum and hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). In particular, hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, it is preferable because it is less likely to crystallize in a heat treatment in a later step. Note that the insulator 544 is not an essential component when the conductor 542a and the conductor 542b are made of a material having oxidation resistance or when the conductivity does not decrease significantly even when oxygen is absorbed. It may be designed appropriately depending on the desired transistor characteristics.

[0444] The insulator 544 can prevent impurities such as water and hydrogen contained in the insulator 580 from diffusing to the oxide 530b through the oxide 530c and the insulator 550. The insulator 580 can also prevent the conductor 560 from being oxidized by excess oxygen contained in the insulator 580.

[0445] The insulator 550 functions as a first gate insulating film. The insulator 550 is preferably disposed in contact with the inside (top and side surfaces) of the oxide 530c. The insulator 550 is preferably formed using an insulator that contains excess oxygen and releases oxygen by heating, similar to the insulator 524 described above.

[0446] Specifically, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having vacancies can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0447] By providing an insulator that releases oxygen when heated as the insulator 550 in contact with the top surface of the oxide 530c, oxygen can be effectively supplied from the insulator 550 to the channel formation region of the oxide 530b through the oxide 530c. Similarly to the insulator 524, the concentration of impurities such as water or hydrogen in the insulator 550 is preferably reduced. The thickness of the insulator 550 is preferably 1 nm or more and 20 nm or less.

[0448] Furthermore, in order to efficiently supply excess oxygen contained in the insulator 550 to the oxide 530, a metal oxide may be provided between the insulator 550 and the conductor 560. The metal oxide preferably suppresses oxygen diffusion from the insulator 550 to the conductor 560. By providing a metal oxide that suppresses oxygen diffusion, the diffusion of excess oxygen from the insulator 550 to the conductor 560 is suppressed. That is, a decrease in the amount of excess oxygen supplied to the oxide 530 can be suppressed. Furthermore, oxidation of the conductor 560 due to the excess oxygen can be suppressed. As the metal oxide, a material that can be used for the insulator 544 may be used.

[0449] The insulator 550 may have a laminated structure, similar to the second gate insulating film. As transistors become smaller and more highly integrated, problems such as leakage current may occur due to the thinning of the gate insulating film. Therefore, by making the insulator that functions as the gate insulating film a laminated structure of a high-k material and a thermally stable material, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. In addition, a laminated structure that is thermally stable and has a high relative dielectric constant can be obtained.

[0450] Although the conductor 560 functioning as the first gate electrode is shown as having a two-layer structure in FIGS. 16A and 16B, it may have a single-layer structure or a laminated structure of three or more layers.

[0451] The conductor 560a is preferably made of a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Alternatively, it is preferably made of a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.). The conductor 560a has a function of suppressing the diffusion of oxygen, so that it is possible to suppress the conductor 560b from being oxidized by the oxygen contained in the insulator 550 and its conductivity from decreasing. As a conductive material having a function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used. In addition, an oxide semiconductor applicable to the oxide 530 can be used as the conductor 560a. In that case, the conductor 560b can be formed by a sputtering method to reduce the electrical resistance value of the conductor 560a and make it a conductor. This can be called an OC (Oxide Conductor) electrode.

[0452] The conductor 560b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Since the conductor 560b also functions as wiring, it is preferable to use a conductor having high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. The conductor 560b may have a layered structure, for example, a layered structure of titanium or titanium nitride and the above conductive material.

[0453] The insulator 580 is provided on the conductor 542a and the conductor 542b via the insulator 544. The insulator 580 preferably has an excess oxygen region. For example, the insulator 580 preferably has silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having voids, or a resin. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, silicon oxide and silicon oxide having voids are preferable because they allow for easy formation of an excess oxygen region in a later step.

[0454] The insulator 580 preferably has an excess oxygen region. By providing the insulator 580, which releases oxygen when heated, in contact with the oxide 530c, oxygen in the insulator 580 can be efficiently supplied to the oxide 530 through the oxide 530c. Note that the concentration of impurities such as water or hydrogen in the insulator 580 is preferably reduced.

[0455] The opening of the insulator 580 is formed to overlap the region between the conductor 542a and the conductor 542b. As a result, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and the region sandwiched between the conductor 542a and the conductor 542b.

[0456] In miniaturizing a semiconductor device, it is necessary to shorten the gate length, but it is also necessary to prevent the conductivity of the conductor 560 from decreasing. If the film thickness of the conductor 560 is increased for that purpose, the conductor 560 may have a shape with a high aspect ratio. In this embodiment, the conductor 560 is provided so as to be embedded in the opening of the insulator 580, so that even if the conductor 560 has a shape with a high aspect ratio, the conductor 560 can be formed without collapsing during the process.

[0457] The insulator 574 is preferably provided in contact with a top surface of the insulator 580, a top surface of the conductor 560, and a top surface of the insulator 550. By forming the insulator 574 by a sputtering method, excess oxygen regions can be provided in the insulator 550 and the insulator 580. This allows oxygen to be supplied from the excess oxygen regions into the oxide 530.

[0458] For example, the insulator 574 can be a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like.

[0459] In particular, aluminum oxide has high barrier properties and can suppress the diffusion of hydrogen and nitrogen even in a thin film of 0.5 nm to 3.0 nm. Therefore, aluminum oxide formed by sputtering can function as a barrier film against impurities such as hydrogen as well as an oxygen source.

[0460] An insulator 581 functioning as an interlayer film is preferably provided over the insulator 574. Like the insulator 524, the insulator 581 preferably has a reduced concentration of impurities such as water or hydrogen.

[0461] Furthermore, conductor 540a and conductor 540b are arranged in openings formed in insulator 581, insulator 574, insulator 580, and insulator 544. Conductor 540a and conductor 540b are provided facing each other with conductor 560 interposed therebetween. Conductor 540a and conductor 540b have the same structure as conductor 546 and conductor 548, which will be described later.

[0462] An insulator 582 is provided over the insulator 581. The insulator 582 is preferably made of a substance that has a barrier property against oxygen, hydrogen, and the like. Therefore, the insulator 582 can be made of a material similar to that of the insulator 514. For example, the insulator 582 is preferably made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0463] In particular, aluminum oxide has a high blocking effect of preventing the film from permeating both oxygen and impurities such as hydrogen and moisture, which are factors that cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. In addition, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0464] An insulator 586 is provided over the insulator 582. The insulator 586 can be formed using a material similar to that of the insulator 320. By using a material with a relatively low dielectric constant for these insulators, parasitic capacitance between wirings can be reduced. For example, the insulator 586 can be formed using a silicon oxide film, a silicon oxynitride film, or the like.

[0465] Furthermore, conductors 546, conductors 548, etc. are embedded in insulators 520, 522, 524, 544, 580, 574, 581, 582, and 586.

[0466] The conductor 546 and the conductor 548 function as a plug or a wiring connected to the capacitor 600, the transistor 500, or the transistor 300. The conductor 546 and the conductor 548 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0467] After the transistor 500 is formed, an opening may be formed to surround the transistor 500, and an insulator having a high barrier property against hydrogen or water may be formed to cover the opening. By surrounding the transistor 500 with the insulator having a high barrier property, it is possible to prevent moisture and hydrogen from entering from the outside. Alternatively, a plurality of transistors 500 may be collectively surrounded by an insulator having a high barrier property against hydrogen or water. When an opening is formed to surround the transistor 500, for example, it is preferable to form an opening that reaches the insulator 514 or the insulator 522 and form the insulator having a high barrier property in contact with the insulator 514 or the insulator 522, since this can serve as part of the manufacturing process of the transistor 500. As the insulator having a high barrier property against hydrogen or water, for example, a material similar to that of the insulator 522 may be used.

[0468] Next, a capacitor 600 is provided above the transistor 500. The capacitor 600 includes a conductor 610, a conductor 620, and an insulator 630.

[0469] A conductor 612 may be provided over the conductor 546 and the conductor 548. The conductor 612 functions as a plug or a wiring connected to the transistor 500. The conductor 610 functions as an electrode of the capacitor 600. Note that the conductor 612 and the conductor 610 can be formed at the same time.

[0470] A metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing the above-mentioned element (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film), or the like can be used for the conductor 612 and the conductor 610. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added can also be used.

[0471] 14, the conductor 612 and the conductor 610 have a single-layer structure, but are not limited to this structure and may have a stacked structure of two or more layers. For example, a conductor having barrier properties and a conductor having high adhesion to the conductor having high conductivity may be formed between a conductor having barrier properties and a conductor having high conductivity.

[0472] A conductor 620 is provided to cover a region overlapping with the conductor 610 with an insulator 630 interposed therebetween. The conductor 620 can be made of a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high-melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten. When the conductor 620 is formed simultaneously with other structures such as a conductor, a low-resistance metal material such as Cu (copper) or Al (aluminum) may be used.

[0473] An insulator 650 is provided over the conductor 620 and the insulator 630. The insulator 650 can be provided using a material similar to that of the insulator 320. The insulator 650 may also function as a planarizing film that covers the uneven shape underneath.

[0474] By using this structure, in a semiconductor device including a transistor having an oxide semiconductor, a change in electrical characteristics can be suppressed and reliability can be improved, or miniaturization or high integration can be achieved in a semiconductor device including a transistor having an oxide semiconductor.

[0475] Note that the semiconductor device of one embodiment of the present invention may have a structure in which, for example, another semiconductor substrate on which a circuit is configured is attached below the substrate 311 on which the transistor 300 is formed. Fig. 17 illustrates a structure in which a layer SA which is a part of the semiconductor device in Fig. 14 is attached to a layer SB on which a circuit is configured on another semiconductor substrate. Specifically, the semiconductor device illustrated in Fig. 17 has a structure in which a substrate 211 on which the circuits and the like included in the layer SB are configured is attached below the substrate 311 included in the layer SA. Note that conductors, insulators, and the like above the insulator 360 in the layer SA are omitted in Fig. 17.

[0476] As an example, like the transistor 300 on the substrate 311, an insulator 220, an insulator 222, an insulator 224, an insulator 226, and an insulator 230 are provided in this order on the substrate 211 so as to cover the transistor 200.

[0477] Furthermore, the insulator 220, the insulator 222, the insulator 224, the insulator 226, the insulator 230, and the insulator 231 can be made of, for example, a material that can be used for the insulator 320, the insulator 322, the insulator 324, the insulator 326, the insulator 230, and the like. The insulator 220, the insulator 222, the insulator 224, the insulator 226, the insulator 230, and the insulator 231 can be formed by, for example, a process similar to that for the insulator 320, the insulator 322, the insulator 324, the insulator 326, the insulator 350, and the like.

[0478] Furthermore, conductors 228 and 229 and the like are embedded in the insulators 220, 222, 224, and 226. The conductors 228 and 229 function as plugs or wirings, similar to the conductors 328 and 330. The conductors 228 and 229 can be made of a material that can be used for the conductors 328 and 330.

[0479] The insulator 232 functions as a bonding layer for an insulator 341 provided below the substrate 311, which will be described later. Furthermore, a conductor 233 is embedded in the insulators 231 and 232 so as to be electrically connected to a part of the conductor 229, and the conductor 233 also functions as a part of the bonding layer.

[0480] The insulator 232 may be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or titanium nitride.

[0481] For example, copper, aluminum, tin, zinc, tungsten, silver, platinum, or gold can be used as the conductor 233. In view of ease of bonding with the conductor 342 described below, it is preferable to use copper, aluminum, tungsten, or gold.

[0482] The conductor 233 may have a multi-layer structure including multiple layers. For example, a first conductor may be formed on the side surfaces of the insulator 231 and the insulator 232, and then a second conductor may be formed so as to fill the openings of the insulator 231 and the insulator 232. As the first conductor, for example, a conductor having a barrier property against hydrogen, such as tantalum nitride, may be used, and as the second conductor, for example, tungsten having high conductivity may be used.

[0483] Further, an insulator 341 is formed below the substrate 311 included in the layer SA. The insulator 341 functions as a bonding layer for the insulator 232 on the substrate 211.

[0484] The insulator 341 can be, for example, a material that can be used for the insulator 232. In particular, in order to join the insulator 232 and the insulator 341, it is preferable that the insulator 232 and the insulator 341 are made of the same component.

[0485] In the layer SA, a conductor 342 is embedded in the insulator 341, the substrate 311, the insulator 320, and the insulator 322 so as to be electrically connected to a part of the conductor 330, and the conductor 342 also functions as a part of the bonding layer.

[0486] For example, a material that can be used for the conductor 233 can be used as the conductor 342. In particular, in order to join the conductor 342 and the conductor 233, it is preferable that the conductor 342 and the conductor 233 are made of the same metal material.

[0487] The conductor 342 may have a multi-layer structure including a plurality of layers. For example, a first conductor may be formed on the side surfaces of the insulator 341, the substrate 311, the insulator 320, and the insulator 322, and then a second conductor may be formed so as to fill the openings of the insulator 341, the substrate 311, the insulator 320, and the insulator 322. As the first conductor, for example, a conductor having a barrier property against hydrogen, such as tantalum nitride, may be used, and as the second conductor, for example, tungsten having high conductivity may be used.

[0488] Next, the bonding of the layer SA and the layer SB will be described.

[0489] In a pre-process for bonding the layer SA and the layer SB, the surfaces of the insulator 226 and the conductor 229 in the layer SB are planarized so that they are at the same height. Similarly, the surfaces of the insulator 341 and the conductor 342 in the layer SA are planarized so that they are at the same height.

[0490] In the lamination process, when bonding insulator 232 and insulator 341, that is, bonding between insulating layers, a hydrophilic bonding method can be used in which the surfaces are polished to a high degree of flatness, then the surfaces are brought into contact with each other after being hydrophilically treated with oxygen plasma or the like to form a temporary bond, and then the final bond is performed by dehydrating the surfaces with a heat treatment. Hydrophilic bonding also produces bonds at the atomic level, so mechanically excellent bonds can be obtained.

[0491] Furthermore, for example, when bonding conductor 233 and conductor 342, that is, bonding conductors together, a surface activation bonding method can be used in which oxide films and adsorption layers of impurities on the surfaces are removed by sputtering or the like, and cleaned and activated surfaces are brought into contact with each other to bond them. Alternatively, a diffusion bonding method can be used in which surfaces are bonded together using a combination of temperature and pressure. In either case, bonding occurs at the atomic level, so a bond that is excellent not only electrically but also mechanically can be obtained.

[0492] By carrying out the above-mentioned bonding process, the conductor 342 included in the layer SA can be electrically connected to the conductor 233 included in the layer SB. Furthermore, a connection having sufficient mechanical strength can be obtained between the insulator 341 included in the layer SA and the insulator 232 included in the layer SB.

[0493] When the layers SA and SB are bonded to each other, since an insulating layer and a metal layer are mixed on each bonding surface, for example, a surface activated bonding method and a hydrophilic bonding method may be combined.

[0494] For example, a method can be used in which the surface is cleaned after polishing, the surface of the metal layer is subjected to an anti-oxidation treatment, and then a hydrophilic treatment is performed before bonding. The surface of the metal layer may be made of a resistant metal such as gold and then subjected to a hydrophilic treatment. Note that bonding methods other than the above-mentioned methods may also be used.

[0495] By using the bonding process described above, further circuits can be added to the semiconductor device. Therefore, an increase in the circuit area of ​​the semiconductor device can be suppressed. Furthermore, the bonding process allows another semiconductor device (e.g., a logic circuit, a signal conversion circuit, a potential level conversion circuit, a current source, a voltage source, a switching circuit, an amplifier circuit, a photoelectric conversion circuit, an arithmetic circuit, etc.) to be electrically connected to the semiconductor device. Therefore, a novel semiconductor device can be configured.

[0496] As an example, a transistor 200 is formed on a substrate 211 included in the layer SB. Although the transistor 200 is shown as having the same structure as the transistor 300 in FIG. 17 as an example, the transistor 200 may have a structure different from that of the transistor 300. For example, as shown in FIG. 18, the transistor 200 may have the structure of the transistor 500 shown in FIG. 16 as an OS transistor. As the substrate 212 shown in FIG. 18, for example, a substrate that can be used for the substrate 312 of the semiconductor device shown in FIG. 15 can be used.

[0497] Next, another example of the structure of an OS transistor illustrated in FIGS. 14 and 15 will be described.

[0498] 19A and 19B are modifications of the transistor 500 shown in Figures 16A and 16B, in which Figure 19A is a cross-sectional view of the transistor 500 in the channel length direction and Figure 19B is a cross-sectional view of the transistor 500 in the channel width direction. Note that the structures shown in Figures 19A and 19B can also be applied to other transistors included in the semiconductor device of one embodiment of the present invention, such as the transistor 300.

[0499] 19A and 19B differs from the transistor 500 shown in Figures 16A and 16B in that the transistor 500 includes an insulator 402 and an insulator 404. The transistor 500 also differs from the transistor 500 shown in Figures 16A and 16B in that an insulator 552 is provided in contact with a side surface of the conductor 540a and an insulator 552 is provided in contact with a side surface of the conductor 540b. The transistor 500 also differs from the transistor 500 shown in Figures 16A and 16B in that the transistor 500 does not include an insulator 520.

[0500] 19A and 19B, the insulator 402 is provided over the insulator 512. Furthermore, the insulator 404 is provided over the insulator 574 and the insulator 402.

[0501] 19A and 19B, the insulator 514, the insulator 516, the insulator 522, the insulator 524, the insulator 544, the insulator 580, and the insulator 574 are provided, and the insulator 404 covers them. That is, the insulator 404 is in contact with the top surface of the insulator 574, the side surface of the insulator 574, the side surface of the insulator 580, the side surface of the insulator 544, the side surface of the insulator 524, the side surface of the insulator 522, the side surface of the insulator 516, the side surface of the insulator 514, and the top surface of the insulator 402. As a result, the oxide 530 and the like are isolated from the outside by the insulator 404 and the insulator 402.

[0502] The insulators 402 and 404 preferably have a high function of suppressing diffusion of hydrogen (for example, at least one of hydrogen atoms, hydrogen molecules, and the like) or water molecules. For example, the insulators 402 and 404 are preferably made of silicon nitride or silicon nitride oxide, which are materials with high hydrogen barrier properties. This can suppress diffusion of hydrogen and the like into the oxide 530, thereby suppressing deterioration of the characteristics of the transistor 500. Therefore, the reliability of the semiconductor device of one embodiment of the present invention can be improved.

[0503] The insulator 552 is provided in contact with the insulator 581, the insulator 404, the insulator 574, the insulator 580, and the insulator 544. The insulator 552 preferably has a function of suppressing diffusion of hydrogen or water molecules. For example, the insulator 552 is preferably made of an insulator having a high hydrogen barrier property, such as silicon nitride, aluminum oxide, or silicon nitride oxide. In particular, silicon nitride is preferably used as the insulator 552 because it has a high hydrogen barrier property. By using a material having a high hydrogen barrier property as the insulator 552, impurities such as water or hydrogen can be suppressed from diffusing from the insulator 580 or the like to the oxide 530 through the conductor 540a and the conductor 540b. Furthermore, oxygen contained in the insulator 580 can be suppressed from being absorbed by the conductor 540a and the conductor 540b. As described above, the reliability of the semiconductor device of one embodiment of the present invention can be improved.

[0504] The transistor 500 shown in FIG. 19A and FIG. 19B may have a different configuration depending on the situation. For example, the transistor 500 shown in FIG. 19A and FIG. 19B may be modified to the transistor shown in FIG. 20A and FIG. 20B as a modified example. FIG. 20A is a cross-sectional view of the transistor in the channel length direction, and FIG. 20B is a cross-sectional view of the transistor in the channel width direction. The transistor shown in FIG. 20A and FIG. 20B is different from the transistor shown in FIG. 19A and FIG. 19B in that the oxide 530c has a two-layer structure of an oxide 530c1 and an oxide 530c2.

[0505] The oxide 530c1 is in contact with the top surface of the insulator 524, the side surface of the oxide 530a, the top surface and side surface of the oxide 530b, the side surfaces of the conductors 542a and 542b, the side surface of the insulator 544, and the side surface of the insulator 580. The oxide 530c2 is in contact with the insulator 550.

[0506] The oxide 530c1 may be, for example, an In-Zn oxide. The oxide 530c2 may be the same material as that used for the oxide 530c when the oxide 530c has a single-layer structure. For example, the oxide 530c2 may be a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4, Ga:Zn=2:1, or Ga:Zn=2:5.

[0507] By forming the oxide 530c in a two-layer structure of the oxide 530c1 and the oxide 530c2, the on-current of the transistor can be increased compared to when the oxide 530c has a single-layer structure. Therefore, the transistor can be applied as, for example, a power MOS transistor. The oxide 530c of the transistor having the configuration shown in FIG. 16A and FIG. 16B can also have a two-layer structure of the oxide 530c1 and the oxide 530c2.

[0508] 20A and 20B can be used, for example, as the transistor 300 shown in Figures 14 and 15. As described above, the transistor 300 can be used, for example, as a transistor included in the semiconductor device described in the above embodiment, such as the arithmetic circuit MAC1, the arithmetic circuit MAC2, the arithmetic circuit MAC3, and the arithmetic circuit MAC4. Note that the transistors shown in Figures 20A and 20B can also be used as transistors other than the transistor 300 and the transistor 500 included in the semiconductor device of one embodiment of the present invention.

[0509] Next, a capacitive element that can be applied to the semiconductor device of FIGS. 14 and 15 will be described.

[0510] Fig. 21 shows a capacitive element 600A as an example of the capacitive element 600 applicable to the semiconductor device shown in Fig. 14 and Fig. 15. Fig. 21A is a top view of the capacitive element 600A, Fig. 21B is a perspective view showing a cross section of the capacitive element 600A taken along dashed line L3-L4, and Fig. 21C is a perspective view showing a cross section of the capacitive element 600A taken along dashed line W3-L4.

[0511] The conductor 610 functions as one of a pair of electrodes of the capacitor 600A, and the conductor 620 functions as the other of the pair of electrodes of the capacitor 600A. The insulator 630 functions as a dielectric material sandwiched between the pair of electrodes.

[0512] As the insulator 630, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, zirconium oxide, etc. can be used, and can be provided as a stacked layer or a single layer.

[0513] In this specification, hafnium oxynitride refers to a material whose composition contains more oxygen than nitrogen, and hafnium nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0514] Also, for example, a laminated structure of a material with high dielectric strength, such as silicon oxynitride, and a high dielectric constant (high-k) material may be used for the insulator 630. With this configuration, the capacitive element 600A can ensure sufficient capacitance by having an insulator with high dielectric constant (high-k), and the capacitive element 600A can improve its dielectric strength by having an insulator with high dielectric strength, thereby suppressing electrostatic breakdown of the capacitive element 600A.

[0515] Examples of high dielectric constant (high-k) material insulators (materials with a high relative dielectric constant) include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0516] Alternatively, the insulator 630 may be a single layer or a multilayer insulator containing a high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba, Sr)TiO3 (BST). For example, when the insulator 630 is a multilayer, a three-layer stack in which zirconium oxide, aluminum oxide, and zirconium oxide are formed in this order, or a four-layer stack in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are formed in this order may be used. Alternatively, the insulator 630 may be a compound containing hafnium and zirconium. As semiconductor devices become finer and more highly integrated, problems such as leakage current in transistors and capacitors may occur due to the thinning of the dielectric material used in the gate insulator and capacitor. By using a high-k material for the gate insulator and the insulator that functions as the dielectric used in the capacitor, it is possible to reduce the gate potential during transistor operation and ensure the capacitance of the capacitor while maintaining the physical film thickness.

[0517] The capacitor 600 is electrically connected to the conductor 546 and the conductor 548 at the bottom of the conductor 610. The conductor 546 and the conductor 548 function as plugs or wiring for connecting to other circuit elements. In addition, in Figures 21A to 21C, the conductor 546 and the conductor 548 are collectively referred to as the conductor 540.

[0518] Also, in order to clarify the figure, FIG. 21 omits the insulator 586 in which the conductor 546 and the conductor 548 are embedded, and the insulator 650 covering the conductor 620 and the insulator 630.

[0519] 14, 15, and 21A to 21C is a planar type capacitive element, but the shape of the capacitive element is not limited to this. For example, the capacitive element 600 may be a cylindrical capacitive element 600B shown in FIGS. 22A to 22C.

[0520] 22A is a top view of the capacitive element 600B, FIG. 22B is a cross-sectional view of the capacitive element 600B taken along dashed line L3-L4, and FIG. 22C is a perspective view showing the cross-section of the capacitive element 600B taken along dashed line W3-L4.

[0521] In FIG. 22B, the capacitor 600B has an insulator 631 on an insulator 586 in which a conductor 540 is embedded, an insulator 651 having an opening, a conductor 610 that functions as one of a pair of electrodes, and a conductor 620 that functions as the other of the pair of electrodes.

[0522] Also, in FIG. 22C, insulator 586, insulator 650, and insulator 651 are omitted for clarity.

[0523] The insulator 631 can be, for example, a material similar to that of the insulator 586.

[0524] Furthermore, a conductor 611 is embedded in the insulator 631 so as to be electrically connected to the conductor 540. The conductor 611 can be made of, for example, the same material as the conductors 330 and 518.

[0525] The insulator 651 can be, for example, a material similar to that of the insulator 586.

[0526] As described above, the insulator 651 has an opening that overlaps with the conductor 611.

[0527] The conductor 610 is formed on the bottom and side surfaces of the opening. That is, the conductor 610 overlaps with the conductor 611 and is electrically connected to the conductor 611.

[0528] The conductor 610 is formed by forming an opening in the insulator 651 by etching or the like, and then depositing the conductor 610 by sputtering, ALD, or the like. Thereafter, the conductor 610 deposited on the insulator 651 may be removed by chemical mechanical polishing (CMP) or the like, leaving the conductor 610 deposited in the opening.

[0529] The insulator 630 is located on the insulator 651 and on the surface on which the conductor 610 is formed. The insulator 630 functions as a dielectric material sandwiched between a pair of electrodes in the capacitor.

[0530] Conductor 620 is formed on insulator 630 so that the opening of insulator 651 is filled.

[0531] The insulator 650 is formed to cover the insulator 630 and the conductor 620 .

[0532] The cylindrical capacitive element 600B shown in FIG. 22 can have a higher capacitance value than the planar capacitive element 600A.

[0533] 14 and 15. In other words, one embodiment of the present invention may be a semiconductor device including an arithmetic circuit MAC1 or the like described in the above embodiment and a photoelectric conversion element.

[0534] A photoelectric conversion element has a function of inducing a current in response to incident light. By utilizing this function, an imaging device can be obtained by arranging a plurality of photoelectric conversion elements, for example, in a matrix.

[0535] By combining the arithmetic circuits MAC1, MAC2, MAC3, and MAC4 described in the above embodiments with an imaging device, for example, image information captured by the imaging device can be input to the arithmetic circuit as second data. That is, a product-sum operation between the image information and the first data can be executed. In particular, by using the first data as a filter value, a convolution process of the image information can be executed. Furthermore, by combining the imaging device with the arithmetic circuit MAC4, etc., a configuration can be created in which the convolution process is repeatedly executed. By utilizing this configuration, it is possible to execute the calculation of a convolutional neural network (CNN).

[0536] 23 illustrates a configuration example of a semiconductor device in which a photoelectric conversion element 700 is provided above the capacitor 600 in FIG. 14. Note that the photoelectric conversion element 700 may be provided below the transistor 300 instead of above the capacitor 600.

[0537] The photoelectric conversion element 700 includes, for example, a layer 767a, a layer 767b, a layer 767c, a layer 767d, and a layer 767e.

[0538] 23 is an example of an organic photoconductive film, with layer 767a being a lower electrode, layer 767e being a light-transmitting upper electrode, and layers 767b, 767c, and 767d being equivalent to a photoelectric conversion section. Note that, instead of photoelectric conversion element 700 shown in FIG. 23, for example, a pn junction photodiode, an avalanche photodiode, or the like may be used.

[0539] The layer 767a serving as the lower electrode can be either an anode or a cathode, and the layer 767b serving as the upper electrode can be the other of the anode or the cathode. Note that in this embodiment, the layer 767a serves as the cathode, and the layer 767b serves as the anode.

[0540] The layer 767a is preferably, for example, a low-resistance metal layer, etc. Specifically, the layer 767a may be, for example, aluminum, titanium, tungsten, tantalum, silver, or a laminate of these.

[0541] The layer 767e is preferably a conductive layer having a high light-transmitting property to visible light. Specifically, the layer 767e can be, for example, indium oxide, tin oxide, zinc oxide, indium-tin oxide, gallium-zinc oxide, indium-gallium-zinc oxide, graphene, or the like. Note that the layer 767e may be omitted.

[0542] In the photoelectric conversion portion, one of the layer 767b and the layer 767d can be a hole transport layer, and the other can be an electron transport layer. In addition, the layer 767c can be a photoelectric conversion layer.

[0543] For the hole transport layer, for example, molybdenum oxide can be used. For the electron transport layer, for example, C 60 , C 70 or derivatives thereof can be used.

[0544] As the photoelectric conversion layer, a mixed layer (bulk heterojunction structure) of an n-type organic semiconductor and a p-type organic semiconductor can be used.

[0545] 23, the insulator 751 is provided over the insulator 650, and the layer 767a is provided over the insulator 751. The insulator 752 is provided over the insulator 751 and the layer 767a. The layer 767b is provided over the insulator 752 and the layer 767a.

[0546] In addition, a layer 767c, a layer 767d, a layer 767e, and an insulator 753 are stacked in this order on the layer 767b.

[0547] For example, the insulator 751 functions as an interlayer insulating film. For example, like the insulator 324, the insulator 751 is preferably an insulator having a barrier property against hydrogen. By using an insulator having a barrier property against hydrogen for the insulator 751, diffusion of hydrogen to the transistor 500 can be suppressed. For this reason, for example, a material that can be used for the insulator 324 can be used for the insulator 751.

[0548] The insulator 752 functions as an element isolation layer, for example. Although not shown, the insulator 752 is provided to prevent a short circuit with another photoelectric conversion element located adjacent to the insulator 752. As the insulator 752, for example, an organic insulator or the like is preferably used.

[0549] For example, the insulator 753 functions as a light-transmitting planarization film. For example, a material such as silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride can be used for the insulator 753.

[0550] Above the insulator 753, for example, a light blocking layer 771, an optical conversion layer 772, and a microlens array 773 are provided.

[0551] The light-shielding layer 771 provided on the insulator 753 can suppress the inflow of light into adjacent pixels. A metal layer such as aluminum or tungsten can be used for the light-shielding layer 771. In addition, the metal layer and a dielectric film having a function as an anti-reflection film may be laminated.

[0552] A color filter can be used for the optical conversion layer 772 provided on the insulator 753 and the light-shielding layer 771. A color image can be obtained by assigning colors such as red (red), green (G), blue (B), yellow (Y), cyan (C), and magenta (M) to the color filters for each pixel.

[0553] Furthermore, if a wavelength cut filter is used for the optical conversion layer 772, a semiconductor device capable of obtaining images in various wavelength regions can be obtained.

[0554] For example, the semiconductor device in Fig. 23 can function as an infrared imaging device by using a filter that blocks light with wavelengths equal to or shorter than visible light in the optical conversion layer 772. Also, the semiconductor device in Fig. 23 can function as a far-infrared imaging device by using a filter that blocks light with wavelengths equal to or shorter than near-infrared light in the optical conversion layer 772. Also, the semiconductor device in Fig. 23 can function as an ultraviolet imaging device by using a filter that blocks light with wavelengths equal to or longer than visible light in the optical conversion layer 772.

[0555] 23 can function as an imaging device for obtaining an image that visualizes the intensity of radiation used in an X-ray imaging device or the like by using a scintillator in the optical conversion layer 772. When radiation such as X-rays that has passed through a subject is incident on the scintillator, it is converted into light (fluorescence) such as visible light or ultraviolet light by the photoluminescence phenomenon. Then, image data is obtained by detecting the light with the photoelectric conversion element 700. Also, a semiconductor device having such a configuration may be used in a radiation detector or the like.

[0556] Scintillators contain a substance that absorbs the energy of radiation such as X-rays and gamma rays and emits visible or ultraviolet light when irradiated with such radiation. For example, Gd2O2S:Tb, Gd2O2S:Pr, Gd2O2S:Eu, BaFCl:Eu, NaI, CsI, CaF2, BaF2, CeF3, LiF, LiI, ZnO, etc. dispersed in resin, ceramics, etc. can be used.

[0557] A microlens array 773 is provided on the light-shielding layer 771 and the optical conversion layer 772. Light passing through each lens of the microlens array 773 passes through the optical conversion layer 772 directly below, and is irradiated onto the photoelectric conversion element 700. By providing the microlens array 773, concentrated light can be incident on the photoelectric conversion element 700, so that photoelectric conversion can be performed efficiently. The microlens array 773 is preferably formed of a resin or glass that is highly translucent to visible light.

[0558] 23 shows a structure of a semiconductor device in which the transistor 300 and the photoelectric conversion element 700 using an organic photoconductive film are provided above the transistor 500; however, the semiconductor device of one embodiment of the present invention is not limited to this structure. For example, the semiconductor device of one embodiment of the present invention may have a back-illuminated pn junction photoelectric conversion element instead of the photoelectric conversion element 700.

[0559] Fig. 24 shows a configuration example of a semiconductor device in which a back-illuminated pn junction photoelectric conversion element 700A is provided above the transistor 300 and the transistor 500 in Fig. 14. The semiconductor device shown in Fig. 24 has a configuration in which a structure SC having a photoelectric conversion element 700A is attached above a substrate 311 on which the transistor 300, the transistor 500, and the capacitor element 600 are provided.

[0560] The structure SC includes a light-shielding layer 771, an optical conversion layer 772, and a microlens array 773, and the above description should be referred to for the description of these.

[0561] The photoelectric conversion element 700A is a pn junction type photodiode formed on a silicon substrate, and has a layer 765b corresponding to a p-type region and a layer 765a corresponding to an n-type region. The photoelectric conversion element 700A is a buried type photodiode, and a thin p-type region (part of the layer 765b) provided on the surface side (current extraction side) of the layer 765a can suppress dark current and reduce noise.

[0562] The insulator 701, the conductor 741, and the conductor 742 function as bonding layers. The insulator 754 functions as an interlayer insulating film and a planarizing film. The insulator 755 functions as an element isolation layer. The insulator 756 functions to suppress the outflow of carriers.

[0563] The silicon substrate is provided with grooves for separating pixels, and the insulator 756 is provided on the upper surface of the silicon substrate and in the grooves. By providing the insulator 756, it is possible to prevent carriers generated in the photoelectric conversion element 700A from flowing out to adjacent pixels. The insulator 756 also has a function of suppressing the intrusion of stray light. Therefore, the insulator 756 can suppress color mixing. An anti-reflection film may be provided between the upper surface of the silicon substrate and the insulator 756.

[0564] The element isolation layer can be formed by using a LOCOS (LOCal Oxidation of Silicon) method. Alternatively, it may be formed by using a STI (Shallow Trench Isolation) method or the like. For example, an inorganic insulating film such as silicon oxide or silicon nitride, or an organic insulating film such as polyimide or acrylic can be used as the insulator 756. Note that the insulator 756 may have a multi-layer structure.

[0565] A layer 765a (n-type region, corresponding to a cathode) of the photoelectric conversion element 700A is electrically connected to the conductor 741. A layer 765b (p-type region, corresponding to an anode) is electrically connected to the conductor 742. The conductors 741 and 742 have regions embedded in the insulator 701. The surfaces of the insulator 701, the conductor 741, and the conductor 742 are flattened so that they are all at the same height.

[0566] An insulator 691 and an insulator 692 are stacked in this order above the insulator 650. Openings are provided in the insulator 691 and the insulator 692, and a conductor 743 is formed to fill the openings.

[0567] As the insulator 691, for example, a material that can be used for the insulator 751 can be used.

[0568] As the insulator 692, for example, a material that can be used for the insulator 650 can be used.

[0569] Each of the insulators 693 and 701 functions as a part of the bonding layer. Each of the conductors 741, 742, and 743 also functions as a part of the bonding layer.

[0570] For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, titanium nitride, etc. can be used for the insulator 693 and the insulator 701. In particular, in order to bond the insulator 693 and the insulator 701 to each other, it is preferable that the insulator 693 and the insulator 701 be made of the same component.

[0571] For example, copper, aluminum, tin, zinc, tungsten, silver, platinum, or gold can be used as the conductor 741, the conductor 742, and the conductor 743. In particular, in order to easily bond the conductor 741 and the conductor 743, and the conductor 742 and the conductor 743, it is preferable to use copper, aluminum, tungsten, or gold.

[0572] Note that the conductor 741, the conductor 742, and the conductor 743 may each have a multilayer structure including a plurality of layers. For example, a first conductor may be formed on a side surface of an opening in which the conductor 741, the conductor 742, or the conductor 743 is provided, and then a second conductor may be formed to fill the opening. As the first conductor, for example, a conductor having a barrier property against hydrogen, such as tantalum nitride, can be used, and as the second conductor, for example, tungsten having high conductivity can be used.

[0573] In a pre-process for bonding the bonding layer on the substrate 311 side to the bonding layer on the structure SC side, the surfaces of the insulator 693 and the conductor 743 on the substrate 311 side are planarized so that they are equal in height. Similarly, the surfaces of the insulator 701, the conductor 741, and the conductor 742 on the structure SC side are planarized so that they are equal in height.

[0574] In the bonding process, when bonding the insulator 693 and the insulator 701, that is, bonding between insulating layers, a hydrophilic bonding method can be used in which the surfaces are polished to a high degree of flatness, then the surfaces are brought into contact with each other after being hydrophilically treated with oxygen plasma or the like to form a temporary bond, and then the final bond is performed by dehydrating the surfaces with a heat treatment. The hydrophilic bonding method also produces bonds at the atomic level, and therefore provides mechanically excellent bonds.

[0575] Furthermore, for example, when bonding conductor 741 and conductor 743, and conductor 742 and conductor 743, that is, bonding between conductors, a surface activation bonding method can be used in which oxide films and adsorption layers of impurities on the surfaces are removed by sputtering or the like, and cleaned and activated surfaces are brought into contact with each other to bond them. Alternatively, a diffusion bonding method can be used in which surfaces are bonded using a combination of temperature and pressure. In both cases, bonding occurs at the atomic level, so excellent bonding can be obtained not only electrically but also mechanically.

[0576] By carrying out the bonding process described above, the conductor 743 on the substrate 311 side can be electrically connected to the conductor 741 and the conductor 742 on the structure SC side. Also, a connection having sufficient mechanical strength can be obtained between the insulator 693 on the substrate 311 side and the insulator 701 on the structure SC side.

[0577] When bonding the substrate 311 and the structure SC, since an insulating layer and a metal layer are mixed on each bonding surface, for example, a surface activated bonding method and a hydrophilic bonding method may be combined.

[0578] For example, a method can be used in which the surface is cleaned after polishing, the surface of the metal layer is subjected to an anti-oxidation treatment, and then a hydrophilic treatment is performed before bonding. The surface of the metal layer may be made of a resistant metal such as gold and then subjected to a hydrophilic treatment. Note that bonding methods other than the above-mentioned methods may also be used.

[0579] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0580] (Embodiment 5) In this embodiment, a metal oxide (hereinafter also referred to as an oxide semiconductor) which can be used for the OS transistor described in the above embodiment will be described.

[0581] The metal oxide preferably contains at least indium or zinc. In particular, it is preferable that the metal oxide contains indium and zinc. In addition to these, it is preferable that the metal oxide contains aluminum, gallium, yttrium, tin, etc. In addition, it may contain one or more elements selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc.

[0582] <Classification of crystal structures> First, classification of crystal structures in oxide semiconductors will be described with reference to Fig. 25A. Fig. 25A is a diagram for explaining classification of crystal structures of oxide semiconductors, typically IGZO (metal oxide containing In, Ga, and Zn).

[0583] As shown in FIG. 25A, oxide semiconductors are broadly classified into "Amorphous", "Crystalline", and "Crystal". "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC). "Crystalline" excludes single crystal, poly crystal, and completely amorphous. "Crystal" includes single crystal and poly crystal.

[0584] The structure in the bold frame shown in Fig. 25A is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). In other words, this structure is completely different from the energetically unstable "Amorphous" and "Crystal".

[0585] The crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD) spectrum. FIG. 25B shows an XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of the CAAC-IGZO film classified as "Crystalline". The GIXD method is also called the thin film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by the GIXD measurement shown in FIG. 25B will be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in FIG. 25B is in the vicinity of In:Ga:Zn=4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in FIG. 25B is 500 nm.

[0586] As shown in Figure 25B, a clear peak indicating crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ=31° in the XRD spectrum of the CAAC-IGZO film. Note that, as shown in Figure 25B, the peak near 2θ=31° is asymmetric with respect to the angle at which the peak intensity is detected.

[0587] The crystal structure of the film or substrate can be evaluated by a diffraction pattern (also called a nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). The diffraction pattern of the CAAC-IGZO film is shown in FIG. 25C. FIG. 25C is a diffraction pattern observed by NBED, which causes an electron beam to be incident parallel to the substrate. The composition of the CAAC-IGZO film shown in FIG. 25C is approximately In:Ga:Zn=4:2:3 [atomic ratio]. In the nanobeam electron diffraction method, electron diffraction is performed with a probe diameter of 1 nm.

[0588] As shown in FIG. 25C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0589] <<Structure of oxide semiconductor>> In addition, when focusing on the crystal structure, oxide semiconductors may be classified differently from that shown in FIG. 25A. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. In addition, non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OS), amorphous oxide semiconductors, and the like.

[0590] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0591] [CAAC-OS] CAAC-OS is an oxide semiconductor having a plurality of crystalline regions, each of which has a c-axis aligned in a specific direction. The specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. The crystalline region is a region having periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, the crystalline region is also a region with a uniform lattice arrangement. CAAC-OS has a region in which a plurality of crystalline regions are connected in the ab-plane direction, and the region may have distortion. The distortion refers to a portion in which the direction of the lattice arrangement changes between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement in the region in which the plurality of crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor having a c-axis aligned and no clear orientation in the ab-plane direction.

[0592] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be about several tens of nm.

[0593] In addition, in an In-M-Zn oxide (wherein element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter, In layer) and a layer containing element M, zinc (Zn), and oxygen (hereinafter, (M, Zn) layer) are stacked. Note that indium and element M are mutually substituted. Thus, the (M, Zn) layer may contain indium. Also, the In layer may contain element M. Note that the In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0594] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD device, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0595] For example, a plurality of bright points (spots) are observed in the electron diffraction pattern of the CAAC-OS film, and the two spots are observed at positions symmetrical to each other with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0596] When the crystal region is observed from the specific direction, the lattice arrangement in the crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. The above distortion may have a lattice arrangement such as a pentagon or heptagon. In addition, in the CAAC-OS, no clear grain boundary can be confirmed even in the vicinity of the distortion. That is, it is found that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is considered to be because the CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms in the ab-plane direction is not dense and the bond distance between atoms changes due to the substitution of metal atoms.

[0597] A crystal structure in which clear grain boundaries are observed is called a polycrystal. The grain boundaries are likely to become recombination centers and capture carriers, causing a decrease in the on-current of a transistor and a decrease in field effect mobility. Therefore, CAAC-OS in which clear grain boundaries are not observed is one of the crystalline oxides having a crystal structure suitable for a semiconductor layer of a transistor. In order to form a CAAC-OS, a structure containing Zn is preferable. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the occurrence of grain boundaries more than In oxide.

[0598] The CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to crystal grain boundaries. In addition, since the crystallinity of an oxide semiconductor can be decreased by the inclusion of impurities, the generation of defects, and the like, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of an oxide semiconductor having the CAAC-OS are stable. Therefore, an oxide semiconductor having the CAAC-OS is resistant to heat and has high reliability. In addition, the CAAC-OS is stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, the use of the CAAC-OS in an OS transistor can increase the degree of freedom in the manufacturing process.

[0599] [nc-OS] The nc-OS has periodic atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has minute crystals. Note that the size of the minute crystals is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore the minute crystals are also called nanocrystals. In addition, the nc-OS does not show regularity in crystal orientation between different nanocrystals. Therefore, no orientation is seen in the entire film. Therefore, depending on the analysis method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structure analysis is performed on an nc-OS film using an XRD device, no peak indicating crystallinity is detected in out-of-plane XRD measurement using θ / 2θ scan. In addition, when an nc-OS film is subjected to electron diffraction (also called selected area electron diffraction) using an electron beam with a probe diameter larger than that of nanocrystals (for example, 50 nm or more), a diffraction pattern like a halo pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter (e.g., 1 nm to 30 nm) that is close to the size of a nanocrystal or smaller than the nanocrystal, an electron diffraction pattern in which multiple spots are observed within a ring-shaped region centered on the direct spot may be obtained.

[0600] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor. The a-like OS has a void or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Moreover, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0601] <<Oxide semiconductor structure>> Next, the above-mentioned CAC-OS will be described in detail, with reference to its material composition.

[0602] [CAC-OS] CAC-OS is, for example, a material configuration in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof. In the following, a state in which one or more metal elements are unevenly distributed in a metal oxide and the regions having the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof, is also referred to as a mosaic or patch state.

[0603] Furthermore, CAC-OS is a composite metal oxide in which the material is separated into a first region and a second region, forming a mosaic structure, and the first region is distributed throughout the film (hereinafter, also referred to as a cloud structure). In other words, CAC-OS is a composite metal oxide in which the first region and the second region are mixed together.

[0604] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are represented as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. Also, the second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. Also, the second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0605] Specifically, the first region is a region mainly composed of indium oxide, indium zinc oxide, etc., and the second region is a region mainly composed of gallium oxide, gallium zinc oxide, etc. In other words, the first region can be rephrased as a region mainly composed of In, and the second region can be rephrased as a region mainly composed of Ga.

[0606] In addition, there are cases where a clear boundary between the first region and the second region cannot be observed.

[0607] For example, in the case of a CAC-OS of an In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) has confirmed that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0608] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act in a complementary manner, giving the CAC-OS a switching function (On / Off function). In other words, CAC-OS has a conductive function in part of the material and an insulating function in other parts of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, it is possible to maximize both functions. Therefore, by using CAC-OS in a transistor, it is possible to achieve a high on-current (I on ), high field effect mobility (μ), and good switching behavior can be achieved.

[0609] Oxide semiconductors have a variety of structures and have different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0610] <Transistor Having Oxide Semiconductor> Next, the case where the oxide semiconductor is used for a transistor will be described.

[0611] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0612] For the transistor, an oxide semiconductor having a low carrier concentration is preferably used. For example, the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 Less than or equal to 1×10 15 cm -3 Less than 1×10, more preferably 13 cm -3 Less than or equal to 1×10 11 cm -3 Less than 1×10, more preferably 10 cm -3 Less than 1 x 10 -9 cm -3 The above is the case. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, an oxide semiconductor having a low impurity concentration and a low density of defect states is referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0613] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states might also be low.

[0614] In addition, charges trapped in the trap states of an oxide semiconductor take a long time to disappear and may behave as if they are fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0615] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in a nearby film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0616] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0617] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. For this reason, the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon near the interface with the oxide semiconductor (concentration obtained by secondary ion mass spectrometry (SIMS)) are set to 2×10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0618] In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect states may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of an alkali metal or an alkaline earth metal in an oxide semiconductor obtained by SIMS is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 To the following:

[0619] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor is likely to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in an oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 To the following:

[0620] Furthermore, hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. In addition, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce hydrogen in the oxide semiconductor as much as possible. Specifically, when the hydrogen concentration in an oxide semiconductor measured by SIMS is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5×10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0621] When an oxide semiconductor in which impurities are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0622] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0623] (Embodiment 6) This embodiment mode describes an example of a semiconductor wafer on which the semiconductor device or the like described in the above embodiment mode is formed, and an electronic component in which the semiconductor device is incorporated.

[0624] <Semiconductor wafer> First, an example of a semiconductor wafer on which semiconductor devices and the like are formed will be described with reference to FIG. 26A.

[0625] 26A includes a wafer 4801 and a plurality of circuit portions 4802 provided on the upper surface of the wafer 4801. Note that on the upper surface of the wafer 4801, a portion where the circuit portions 4802 are not present is a spacing 4803, which is a region for dicing.

[0626] The semiconductor wafer 4800 can be manufactured by forming a plurality of circuit portions 4802 on the surface of the wafer 4801 in a previous process. After that, the surface of the wafer 4801 opposite to the surface on which the plurality of circuit portions 4802 are formed may be ground to thin the wafer 4801. This process reduces warping of the wafer 4801 and allows for miniaturization of the component.

[0627] The next step is a dicing step. Dicing is performed along scribe lines SCL1 and SCL2 (sometimes called dicing lines or cutting lines) shown by dashed lines. In order to facilitate the dicing step, it is preferable that the spacing 4803 is arranged so that the multiple scribe lines SCL1 are parallel to each other, the multiple scribe lines SCL2 are parallel to each other, and the scribe lines SCL1 and SCL2 are perpendicular to each other.

[0628] By performing a dicing process, a chip 4800a as shown in FIG. 26B can be cut out from the semiconductor wafer 4800. The chip 4800a has a wafer 4801a, a circuit portion 4802, and a spacing 4803a. It is preferable that the spacing 4803a is as small as possible. In this case, it is sufficient that the width of the spacing 4803 between adjacent circuit portions 4802 is approximately equal to the cutting allowance of the scribe line SCL1 or the cutting allowance of the scribe line SCL2.

[0629] Note that the shape of the element substrate of one embodiment of the present invention is not limited to the shape of the semiconductor wafer 4800 shown in Fig. 26A. For example, the semiconductor wafer may have a rectangular shape. The shape of the element substrate can be changed as appropriate depending on the manufacturing process of the element and the device for manufacturing the element.

[0630] <Electronic components> FIG. 26C shows a perspective view of electronic component 4700 and a substrate (mounting substrate 4704) on which electronic component 4700 is mounted. Electronic component 4700 shown in FIG. 26C has chip 4800a in mold 4711. As shown in FIG. 26C, chip 4800a may have a configuration in which circuit section 4802 is laminated. FIG. 26C omits a part of electronic component 4700 in order to show the inside of electronic component 4700. Electronic component 4700 has land 4712 on the outside of mold 4711. Land 4712 is electrically connected to electrode pad 4713, and electrode pad 4713 is electrically connected to chip 4800a by wire 4714. Electronic component 4700 is mounted on, for example, printed circuit board 4702. A plurality of such electronic components are combined and electrically connected on printed circuit board 4702 to complete mounting substrate 4704.

[0631] 26D shows a perspective view of electronic component 4730. Electronic component 4730 is an example of a SiP (System in package) or MCM (Multi Chip Module). Electronic component 4730 has interposer 4731 provided on package substrate 4732 (printed circuit board), and semiconductor device 4735 and multiple semiconductor devices 4710 provided on interposer 4731.

[0632] The electronic component 4730 has a semiconductor device 4710. The semiconductor device 4710 can be, for example, the semiconductor device described in the above embodiment, a high bandwidth memory (HBM), or the like. The semiconductor device 4735 can be an integrated circuit (semiconductor device) such as a CPU, a GPU, an FPGA, or a memory device.

[0633] A ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used for the package substrate 4732. A silicon interposer, a resin interposer, or the like can be used for the interposer 4731.

[0634] The interposer 4731 has a plurality of wirings and functions to electrically connect a plurality of integrated circuits having different terminal pitches. The plurality of wirings are provided in a single layer or multiple layers. The interposer 4731 also functions to electrically connect the integrated circuits provided on the interposer 4731 to electrodes provided on the package substrate 4732. For these reasons, the interposer may be called a "rewiring substrate" or an "intermediate substrate." In addition, a through electrode may be provided in the interposer 4731, and the integrated circuits and the package substrate 4732 may be electrically connected using the through electrode. In addition, in a silicon interposer, a TSV (Through Silicon Via) may be used as the through electrode.

[0635] It is preferable to use a silicon interposer as the interposer 4731. Since a silicon interposer does not require an active element, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring of the silicon interposer can be formed by a semiconductor process, it is easy to form fine wiring, which is difficult to form with a resin interposer.

[0636] In HBM, many wirings need to be connected to realize a wide memory bandwidth. For this reason, the interposer that mounts HBM requires fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer that mounts HBM.

[0637] In addition, in SiP, MCM, etc. that use silicon interposers, deterioration in reliability due to differences in the expansion coefficient between the integrated circuit and the interposer is unlikely to occur. In addition, since the surface of the silicon interposer is highly flat, connection failures between the integrated circuit mounted on the silicon interposer and the silicon interposer are unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional mounting) in which multiple integrated circuits are arranged side by side on the interposer.

[0638] A heat sink (heat dissipation plate) may be provided overlapping the electronic component 4730. When providing a heat sink, it is preferable to make the height of an integrated circuit provided on the interposer 4731 uniform. For example, in the electronic component 4730 shown in this embodiment, it is preferable to make the height of the semiconductor device 4710 and the height of the semiconductor device 4735 uniform.

[0639] In order to mount electronic component 4730 on another substrate, electrodes 4733 may be provided on the bottom of package substrate 4732. Fig. 26D shows an example in which electrodes 4733 are formed of solder balls. By providing solder balls in a matrix on the bottom of package substrate 4732, BGA (Ball Grid Array) mounting can be realized. Electrodes 4733 may also be formed of conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 4732, PGA (Pin Grid Array) mounting can be realized.

[0640] The electronic component 4730 can be mounted on other substrates using various mounting methods, including but not limited to BGA and PGA. For example, a mounting method such as a Staggered Pin Grid Array (SPGA), a Land Grid Array (LGA), a Quad Flat Package (QFP), a Quad Flat J-leaded package (QFJ), or a Quad Flat Non-leaded package (QFN) can be used.

[0641] Next, an electronic component having an image sensor chip (imaging device) including a photoelectric conversion element will be described.

[0642] 27A is a perspective view showing the appearance of the upper surface of a package containing an image sensor chip. The package includes a package substrate 4510 for fixing an image sensor chip 4550 (see FIG. 27C), a cover glass 4520, and an adhesive 4530 for bonding the two together.

[0643] 27B is a perspective view of the bottom surface of the package. The bottom surface of the package has a BGA (Ball Grid Array) with solder balls as bumps 4540. Note that the package is not limited to a BGA, and may have an LGA (Land Grid Array), PGA (Pin Grid Array), or the like.

[0644] 27C is a perspective view of the package with a portion of the cover glass 4520 and the adhesive 4530 omitted. An electrode pad 4560 is formed on the package substrate 4510, and the electrode pad 4560 and the bump 4540 are electrically connected via a through hole. The electrode pad 4560 is electrically connected to the image sensor chip 4550 by a wire 4570.

[0645] 27D is a perspective view showing the appearance of the upper surface of a camera module in which an image sensor chip is housed in a lens-integrated package. The camera module has a package substrate 4511 for fixing an image sensor chip 4551 (FIG. 27F), a lens cover 4521, a lens 4535, and the like. Also, an IC chip 4590 (FIG. 27F) having functions such as a drive circuit for an imaging device and a signal conversion circuit is provided between the package substrate 4511 and the image sensor chip 4551, and has a configuration as a SiP (System in Package).

[0646] 27E is a perspective view of the appearance of the bottom surface side of the camera module. The bottom surface and side surfaces of the package substrate 4511 have a QFN (Quad Flat No-lead package) configuration with lands 4541 for mounting. Note that this configuration is one example, and a QFP (Quad Flat Package), the above-mentioned BGA, or the like may also be provided.

[0647] 27F is a perspective view of the module without a portion of lens cover 4521 and lens 4535. Land 4541 is electrically connected to electrode pad 4561, and electrode pad 4561 is electrically connected to image sensor chip 4551 or IC chip 4590 by wire 4571.

[0648] By housing the image sensor chip in a package of the above-described form, it becomes easy to mount the image sensor chip on a printed circuit board, etc., and the image sensor chip can be incorporated into various semiconductor devices and electronic devices. For example, by incorporating the image sensor chip into the arithmetic circuit described in the above embodiment, information captured by the image sensor chip can be input to the arithmetic circuit as input data.

[0649] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0650] (Embodiment 7) In this embodiment, an example of an electronic device having the semiconductor device described in the above embodiment will be described. Note that Fig. 28 illustrates a state in which an electronic device includes an electronic component 4700 having the semiconductor device. Although Fig. 28 illustrates the electronic component 4700, the imaging device shown in Fig. 27 may be applied instead.

[0651] [mobile phone] 28 is a mobile phone (smartphone), which is one type of information terminal. The information terminal 5500 has a housing 5510 and a display unit 5511. As an input interface, a touch panel is provided on the display unit 5511, and buttons are provided on the housing 5510.

[0652] The information terminal 5500 can execute applications using artificial intelligence by applying the semiconductor device described in the above embodiment. Examples of applications using artificial intelligence include an application that recognizes a conversation and displays the conversation content on the display unit 5511, an application that recognizes characters, figures, and the like input by a user to a touch panel provided in the display unit 5511 and displays them on the display unit 5511, and an application that performs biometric authentication such as fingerprints and voiceprints.

[0653] [Wearable devices] 28 illustrates a wristwatch-type information terminal 5900 as an example of a wearable terminal. The information terminal 5900 includes a housing 5901, a display portion 5902, operation buttons 5903, an operator 5904, a band 5905, and the like.

[0654] The wearable terminal can execute applications using artificial intelligence by applying the semiconductor device described in the above embodiment, similarly to the above-described information terminal 5500. Examples of applications using artificial intelligence include an application that manages the health condition of a person wearing a wearable terminal, and a navigation system that selects and guides the user along the optimal route by inputting a destination.

[0655] [Information terminal] 28 also shows a desktop information terminal 5300. The desktop information terminal 5300 has a main body 5301 of the information terminal, a display 5302, and a keyboard 5303.

[0656] The desktop information terminal 5300 can execute applications using artificial intelligence by applying the semiconductor device described in the above embodiment, similarly to the information terminal 5500 described above. Examples of applications using artificial intelligence include design support software, text correction software, and automatic menu generation software. In addition, new artificial intelligence can be developed by using the desktop information terminal 5300.

[0657] In the above description, a smartphone, a desktop information terminal, and a wearable terminal are illustrated as examples of electronic devices in Fig. 28, but information terminals other than smartphones, desktop information terminals, and wearable terminals can also be applied. Examples of information terminals other than smartphones, desktop information terminals, and wearable terminals include PDAs (Personal Digital Assistants), notebook information terminals, and workstations.

[0658] [electric appliances] 28 also illustrates an electric refrigerator-freezer 5800 as an example of an electric appliance. The electric refrigerator-freezer 5800 includes a housing 5801, a door for a refrigerator compartment 5802, a door for a freezer compartment 5803, and the like.

[0659] The electric refrigerator-freezer 5800 having artificial intelligence can be realized by applying the semiconductor device described in the above embodiment to the electric refrigerator-freezer 5800. By using artificial intelligence, the electric refrigerator-freezer 5800 can have a function of automatically generating a menu based on ingredients stored in the electric refrigerator-freezer 5800 and the expiration dates of the ingredients, a function of automatically adjusting the temperature to suit the ingredients stored in the electric refrigerator-freezer 5800, and the like.

[0660] In this example, an electric refrigerator-freezer has been described as an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, IH (Induction Heating) cookers, water servers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0661] [Game consoles] 28 also illustrates a portable game machine 5200, which is an example of a game machine. The portable game machine 5200 includes a housing 5201, a display portion 5202, buttons 5203, and the like.

[0662] Furthermore, FIG. 28 illustrates a stationary game machine 7500, which is an example of a game machine. The stationary game machine 7500 has a main body 7520 and a controller 7522. The controller 7522 can be connected to the main body 7520 wirelessly or by wire. Although not illustrated in FIG. 28, the controller 7522 can include a display unit for displaying game images, a touch panel as an input interface other than buttons, a stick, a rotary knob, a sliding knob, and the like. The shape of the controller 7522 is not limited to that shown in FIG. 28, and the shape of the controller 7522 may be changed in various ways depending on the genre of the game. For example, in a shooting game such as an FPS (First Person Shooter), a controller with a trigger as a button and a shape imitating a gun can be used. For example, in a music game, a controller with a shape imitating a musical instrument, a musical device, or the like can be used. Furthermore, the stationary game machine may not use a controller, but may instead be equipped with a camera, depth sensor, microphone, etc., and be operated by the game player's gestures and / or voice.

[0663] Furthermore, the images of the above-mentioned game machines can be output by display devices such as television sets, personal computer displays, game displays, and head-mounted displays.

[0664] A low-power portable game machine 5200 can be realized by applying the semiconductor device described in the above embodiment to the portable game machine 5200. In addition, the low power consumption can reduce heat generation from a circuit, and therefore the influence of heat generation on the circuit itself, peripheral circuits, and modules can be reduced.

[0665] Furthermore, by applying the semiconductor device described in the above embodiment modes to the portable game machine 5200, the portable game machine 5200 can have artificial intelligence.

[0666] Originally, the expression of the progress of a game, the behavior of creatures appearing in the game, and phenomena occurring in the game are determined by the program of the game, but by applying artificial intelligence to the portable game device 5200, it becomes possible to express things that are not limited to the game program. For example, it becomes possible to express things such as changes in the questions asked by the player, the progress of the game, the time, and the behavior of people appearing in the game.

[0667] In addition, when playing a game on the portable game console 5200 that requires multiple players, the game players can be personified using artificial intelligence, so that the game can be played by one person by making the opponent a game player based on artificial intelligence.

[0668] 28 illustrates a portable game machine as an example of a game machine, but the electronic device of one embodiment of the present invention is not limited to this. Examples of the electronic device of one embodiment of the present invention include a home-use stationary game machine, an arcade game machine installed in an entertainment facility (game center, amusement park, etc.), and a pitching machine for batting practice installed in a sports facility.

[0669] [Mobile object] The semiconductor device described in the above embodiment can be applied to automobiles, which are moving objects, and to the vicinity of a driver's seat of an automobile.

[0670] FIG. 28 shows an automobile 5700 as an example of a moving object.

[0671] An instrument panel capable of displaying a speedometer, a tachometer, a mileage, a fuel gauge, a gear status, an air conditioner setting, etc. may be provided around the driver's seat of the automobile 5700. A display device showing such information may also be provided around the driver's seat.

[0672] In particular, the display device can display an image from an imaging device (not shown) provided on the automobile 5700, thereby compensating for visibility blocked by pillars and blind spots around the driver's seat, thereby improving safety. In other words, by displaying an image from an imaging device provided on the outside of the automobile 5700, blind spots can be compensated for and safety can be improved.

[0673] Since the semiconductor device described in the above embodiment can be applied as a component of artificial intelligence, the computer can be used, for example, in an automatic driving system of the automobile 5700. The computer can also be used in a system that performs road guidance, risk prediction, etc. The display device may be configured to display information such as road guidance and risk prediction.

[0674] In the above description, an automobile is described as an example of a moving body, but the moving body is not limited to an automobile. For example, a moving body may be a train, a monorail, a ship, an aircraft (helicopter, unmanned aerial vehicle (drone), airplane, rocket), etc., and a computer according to one embodiment of the present invention may be applied to these moving bodies to provide a system using artificial intelligence.

[0675] [camera] The semiconductor device described in the above embodiment can be applied to a camera.

[0676] 28 shows a digital camera 6240 as an example of an imaging device. The digital camera 6240 has a housing 6241, a display unit 6242, an operation button 6243, a shutter button 6244, and the like, and a detachable lens 6246 is attached to the digital camera 6240. Note that, although the digital camera 6240 is configured such that the lens 6246 can be detached from the housing 6241 and replaced, the lens 6246 and the housing 6241 may be integrated. The digital camera 6240 may also be configured such that a strobe device, a viewfinder, and the like can be separately attached.

[0677] A low power consumption digital camera 6240 can be realized by applying the semiconductor device described in the above embodiment to the digital camera 6240. In addition, low power consumption can reduce heat generation from a circuit, and therefore influence of heat generation on the circuit itself, peripheral circuits, and modules can be reduced.

[0678] Furthermore, a digital camera 6240 having artificial intelligence can be realized by applying the semiconductor device described in the above embodiment to the digital camera 6240. By using artificial intelligence, the digital camera 6240 can have a function of automatically recognizing a subject such as a face or an object, a function of adjusting focus according to the subject, a function of automatically turning on a flash according...

Claims

[Claim 1] A first circuit and a second circuit, the second circuit includes a first switch, a second switch, a current-voltage conversion circuit, and a first transistor; The first circuit is electrically connected to a first terminal of the first switch; a second terminal of the first switch is electrically connected to an input terminal of the current-voltage conversion circuit; an output terminal of the current-voltage conversion circuit is electrically connected to a first terminal of the first transistor; a second terminal of the first transistor electrically connected to a first terminal of the second switch; The first circuit is The first data W １ Or W ｍ (m is an integer equal to or greater than 1); The first circuit receives a plurality of second data X １ ~X ｍ and a function of causing a current according to the value of formula (A1) to flow to the first terminal of the second circuit when The current-voltage conversion circuit has a function of outputting a first potential corresponding to the current input to an input terminal of the current-voltage conversion circuit to an output terminal of the current-voltage conversion circuit. [0010]

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