Light emitting element

Abstract

To reduce light absorption by a semiconductor material while securing excellent conduction between an electrode and a semiconductor.SOLUTION: A light emitting element includes: a semiconductor structure (10) having an n-side semiconductor layer (12) having a first n-side semiconductor layer (12a) and a second n-side semiconductor layer (12b); an active layer (16) configured to emit red light, and a p-side semiconductive layer (14); an n-side electrode (20); and p-side electrode (30). The semiconductor structure has a first region (10a) in which a p-side semiconductor layer and an active layer are disposed and a second region (10b) other than the first region. The first n-side semiconductor layer is disposed in the first region and the second region. The second n-side semiconductor layer is disposed on a surface opposite to the p-side semiconductor layer side of the first n-side semiconductor layer so as to overlap with the first n-side semiconductor layer in at least part the second region in a plan view and has band gap energy smaller than the first n-side semiconductor layer. The n-side electrode is electrically connected to the second n-side semiconductor layer at an opening (hn) of the first n-side semiconductor layer.SELECTED DRAWING: Figure 1C

Description

[Technical field]

[0001] The present disclosure relates to a light-emitting device. [Background technology]

[0002] For example, Patent Document 1 has proposed a red-emitting light-emitting element made of an AlGaInP-based semiconductor material, which has an n-side electrode and a p-side electrode on one side and emits light from the side opposite to the side on which the electrodes are provided. Specifically, Patent Document 1 proposes a light-emitting element having a transparent substrate attached to the light-extraction side, in which a transparent film having a lower refractive index than the transparent substrate is provided on the surface of the transparent substrate on the light-extraction side, and the surface of the transparent film is roughened. In this light-emitting element, the transparent film has a roughened surface, which increases the light distribution angle and luminous efficiency regardless of the material of the transparent substrate, and is made of a low-refractive index material, which generates a total reflection angle and increases the luminous efficiency. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2018-064006 A Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present disclosure is to provide a light-emitting element that can reduce light absorption by a semiconductor material while ensuring good electrical continuity between an electrode and a semiconductor. [Means for solving the problem]

[0005] A light-emitting device according to the present disclosure includes a semiconductor structure including an n-side semiconductor layer having a first n-side semiconductor layer and a second n-side semiconductor layer, an active layer, and a p-side semiconductor layer, the active layer being disposed between the n-side semiconductor layer and the p-side semiconductor layer in a thickness direction; an n-side electrode electrically connected to the n-side semiconductor layer; a p-side electrode electrically connected to the p-side semiconductor layer, the active layer emits red light having a peak wavelength in the range of 620 nm to 700 nm, The semiconductor structure has a first region and a second region in a plan view, the first region is a region in which the p-side semiconductor layer and the active layer are disposed, and the second region is a region other than the first region, the first n-side semiconductor layer is disposed in the first region and the second region, the second n-side semiconductor layer is disposed on a surface of the first n-side semiconductor layer opposite to the p-side semiconductor layer side so as to overlap the first n-side semiconductor layer in at least a part of the second region in a plan view, the second n-side semiconductor layer has a smaller band gap energy than the first n-side semiconductor layer, the first n-side semiconductor layer disposed in the second region has an opening exposing the second n-side semiconductor layer, The n-side electrode is electrically connected to the second n-side semiconductor layer in the opening, which is a light-emitting element. Effect of the Invention

[0006] The light emitting element of the present disclosure can reduce light absorption by the semiconductor material while ensuring good electrical continuity between the electrode and the semiconductor. [Brief description of the drawings]

[0007] [Figure 1A] FIG. 1 is a plan view showing a light-emitting device according to a first embodiment of the present disclosure. [Figure 1B] 1B is a cross-sectional view taken along line IB-IB of FIG. 1A, illustrating the light-emitting device according to the first embodiment of the present disclosure. [Figure 1C] 1B is a cross-sectional view taken along line IC-IC in FIG. 1A, showing the light-emitting device according to the first embodiment of the present disclosure. [Diagram 2] 1 is a plan view showing a first region and a second region of a semiconductor structure constituting a light emitting device according to a first embodiment of the present disclosure. [Diagram 3] 1 is a plan view showing a p-side electrode of the light-emitting element according to the first embodiment of the present disclosure. [Figure 4] 1 is a plan view showing an opening in an insulating film constituting the light emitting element according to the first embodiment of the present disclosure. [Diagram 5] 4 is a plan view showing an opening in another insulating film constituting the light emitting device according to the first embodiment of the present disclosure. FIG. [Figure 6] 1 is a plan view showing a wiring layer constituting the light emitting device according to the first embodiment of the present disclosure. [Figure 7] 2 is a plan view showing an n-side pad electrode and a p-side pad electrode constituting the light-emitting element according to the first embodiment of the present disclosure. FIG. [Figure 8] FIG. 4 is a plan view showing a light-emitting device according to a second embodiment of the present disclosure. [Figure 9] FIG. 11 is a plan view showing a first region, a second region, and a p-side electrode in a light-emitting element according to a second embodiment of the present disclosure. [Figure 10] 11 is a plan view showing an opening in an insulating film constituting a light emitting element according to a second embodiment of the present disclosure. FIG. [Figure 11] 11 is a plan view showing a wiring layer, an n-side pad electrode, a p-side pad electrode, and an opening in another insulating film, which constitute a light-emitting element according to Embodiment 2 of the present disclosure. FIG. [Figure 12] FIG. 11 is a cross-sectional view showing a light-emitting device according to a third embodiment of the present disclosure. [Figure 13(a)] 1 is a cross-sectional view showing a step of a method for manufacturing the light-emitting device according to the first embodiment of the present disclosure. [Figure 13(b)] 1 is a cross-sectional view showing a step of a method for manufacturing the light-emitting device according to the first embodiment of the present disclosure. [Figure 13(c)] 1 is a cross-sectional view showing a step of a method for manufacturing the light-emitting device according to the first embodiment of the present disclosure. [Figure 13(d)] 1 is a cross-sectional view showing a step of a method for manufacturing the light-emitting device according to the first embodiment of the present disclosure. [Figure 13(e)] 1 is a cross-sectional view showing a step of a method for manufacturing the light-emitting device according to the first embodiment of the present disclosure. [Figure 13(f)] 1 is a cross-sectional view showing a step of a method for manufacturing the light-emitting device according to the first embodiment of the present disclosure. [Figure 13(g)] 1 is a cross-sectional view showing a step of a method for manufacturing the light-emitting device according to the first embodiment of the present disclosure. [Figure 13(h)] 1 is a cross-sectional view showing a step of a method for manufacturing the light-emitting device according to the first embodiment of the present disclosure. [Figure 13(i)] 1 is a cross-sectional view showing a step of a method for manufacturing the light-emitting device according to the first embodiment of the present disclosure. [Figure 13(j)] 1 is a cross-sectional view showing a step of a method for manufacturing the light-emitting device according to the first embodiment of the present disclosure. [Figure 13(k)] 1 is a cross-sectional view showing a step of a method for manufacturing the light-emitting device according to the first embodiment of the present disclosure. [Figure 13(l)] 1 is a cross-sectional view showing a step of a method for manufacturing the light-emitting device according to the first embodiment of the present disclosure. [Figure 13(m)] 1 is a cross-sectional view showing a step of a method for manufacturing the light-emitting device according to the first embodiment of the present disclosure. [Figure 13(n)] 1 is a cross-sectional view showing a step of a method for manufacturing the light-emitting device according to the first embodiment of the present disclosure. [Figure 13(o)] 1 is a cross-sectional view showing a step of a method for manufacturing the light-emitting device according to the first embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] (Embodiment 1) Each of Figs. 1A to 7 shows an embodiment of the light-emitting element of the present disclosure in a cross-sectional view or a plan view. Fig. 1A is a plan view of the light-emitting element of this embodiment. Fig. 1B is a cross-sectional view taken along line IB-IB in Fig. 1A. Fig. 1C is a cross-sectional view taken along line IC-IC in Fig. 1A. In addition, Fig. 2 shows only a first region and a second region described later, and clarifies their positional relationship in a plan view. As shown in these figures, the light-emitting element 1 of this embodiment has a semiconductor structure 10, an n-side electrode 20, and a p-side electrode 30. The semiconductor structure has an n-side semiconductor layer 12 having a first n-side semiconductor layer 12a and a second n-side semiconductor layer 12b, a p-side semiconductor layer 14, and an active layer 16 located between the n-side semiconductor layer 12 and the p-side semiconductor layer. Furthermore, the light-emitting element 1 has a dielectric multilayer film 40, insulating films 45a, 45b, an n-side pad electrode 50, a p-side pad electrode 60, and a wiring layer 70 for connecting the n-side electrode 20 and the p-side electrode 30 to the n-side pad electrode 50 and the p-side pad electrode 60, respectively. The light-emitting element 1 has a holder 80 for supporting the semiconductor structure 10 on the surface opposite to the surface on which the n-side pad electrode 50 and the p-side pad electrode 60 are arranged. Light emitted by the active layer 16 of the light-emitting element 1 is mainly extracted from the side on which the holder 80 is arranged.

[0009] The semiconductor structure 10 has a first region 10a and a second region 10b in a plan view. The first region 10a is a region in which the p-side semiconductor layer 14 and the active layer 16 are arranged. The second region 10b, which is a region other than the first region 10a, is a region in which only the n-side semiconductor layer 12 is arranged in the semiconductor structure 10. In this embodiment, the second region 10b has an outer peripheral portion 10b1 arranged at the outer edge of the light-emitting element 1 and a central portion 10b2 arranged approximately at the center of the light-emitting element 1 in a plan view. The light-emitting element 1 of this embodiment has a configuration in which the first n-side semiconductor layer 12a of the n-side semiconductor layer 12 is arranged in the first region 10a and the second region 10b, and at least a part of the second n-side semiconductor layer 12b is arranged in the second region 10b. As shown in FIG. 1A, in this embodiment, the second n-side semiconductor layer 12b is arranged in the central portion 10b2 of the second region 10b. The second n-side semiconductor layer 12b is disposed on the side opposite the p-side semiconductor layer 14, that is, on the holding portion 80 side, as viewed from the first n-side semiconductor layer 12a.

[0010] The first n-side semiconductor layer 12a has an opening hn at the center 10b2 of the second region 10b, and the second n-side semiconductor layer 12b is exposed at the opening hn. Here, the member x is exposed from the member y, or the member y exposes the member x, means that a part of the member x is covered with the member y, while another part of the member x is not covered with the member y, and allows the part not covered with the member y to be covered with another member. In this embodiment, the n-side electrode 20 is electrically connected to the second n-side semiconductor layer 12b at the opening hn, and the n-side electrode 20 is further electrically connected to the n-side pad electrode 50 via the wiring layer 70.

[0011] In this embodiment, the active layer 16 emits red light having a peak wavelength in the range of 620 nm to 700 nm. The smaller the band gap energy of the semiconductor material constituting the semiconductor structure capable of emitting such red light, the more light from the active layer 16 tends to be absorbed. On the other hand, from the viewpoint of reducing the contact resistance between the semiconductor material and the metal, i.e., the forward voltage Vf of the light-emitting device, it may be disadvantageous to form the n-side semiconductor layer 12 only with semiconductor materials having higher band gap energy. Therefore, in this embodiment, the second n-side semiconductor layer 12b has a smaller band gap energy than the first n-side semiconductor layer 12a, and the entire second n-side semiconductor layer 12b is disposed in the second region 10b that does not overlap with the active layer 16 in a plan view. Furthermore, the n-side electrode 20 is disposed so as to be in contact with the second n-side semiconductor layer 12b, and the n-side electrode 20 and the second n-side semiconductor layer 12b are electrically connected to each other. According to this configuration, it is possible to reduce the interference of the semiconductor material, which is favorable in terms of contact resistance with the n-side electrode 20, with the light from the active layer. As a result, it is possible to reduce the absorption of red light and improve the light emission efficiency of the light emitting element 1 without increasing the forward voltage Vf of the light emitting element 1. That is, in the light emitting element 1, it is possible to reduce the light absorption by the semiconductor material while ensuring good electrical conduction between the n-side electrode 20 and the semiconductor material. In addition, in this embodiment, the central portion 10b2 of the second region 10b in which the second n-side semiconductor layer 12b is arranged is surrounded by the first region 10a in a plan view. This arrangement can reduce the bias of the current density distribution in the light emitting element 1.

[0012] In this embodiment, the entire second n-side semiconductor layer 12b may not be located in the second region 10b in a plan view, and a part of the second n-side semiconductor layer 12b may be disposed in the first region 10a. Also, a plurality of second regions 10b each having a shape surrounded by the first region 10a in a plan view may be disposed. For example, the second region 10b may have a plurality of substantially rectangular second regions 10b as shown in FIG. 1A, or the second region 10b may have a central portion 10b2 and a plurality of regions extending radially from the central portion 10b2 in a plan view.

[0013] In a plan view, the outer edge of the second n-side semiconductor layer 12b has a shape corresponding to the outer edge of the second region 10b, and it is preferable that the entire outer edge of the second n-side semiconductor layer 12b is disposed within the second region 10b. By making the shape of the second n-side semiconductor layer 12b correspond to the shape of the second region 10b, it becomes easier to arrange the first region 10a and the second region 10b in consideration of the current density distribution, the position of the light emitting region, and the like.

[0014] The present embodiment will be described in more detail below. 1. Semiconductor structure The semiconductor structure 10 has an n-side semiconductor layer 12 having a first n-side semiconductor layer 12a and a second n-side semiconductor layer 12b, a p-side semiconductor layer 14, and an active layer 16 disposed between the n-side semiconductor layer 12 and the p-side semiconductor layer 14. In FIG. 1B and FIG. 1C, the semiconductor structure 10 is shown with the p-side semiconductor layer 14 on the lower side and the light extraction surface (the surface on the side of the holding unit 80) on the upper side. In this embodiment, the semiconductor structure 10 is rectangular in plan view, but may be other shapes, such as a square, a circle, a trapezoid, a triangle, a polygon having five or more sides, etc. In addition, when the shape of the semiconductor structure 10 in plan view is a polygon having multiple corners, the corners of the polygon may be rounded.

[0015] The semiconductor materials constituting the semiconductor structure 10 are selected so that the active layer 16 emits red light having a peak wavelength in the range of 620 nm to 700 nm. In this embodiment, the semiconductor materials constituting the p-side semiconductor layer 14, the active layer 16, and the first n-side semiconductor layer 12a may include, for example, AlGaInP-based materials. The AlGaInP-based materials include, for example, (Al x Ga 1-x ) y In 1-yP (0≦x≦1, 0≦y≦1). The peak wavelength of the red light is adjusted by changing the ratio of Al and Ga in the semiconductor material constituting the active layer 16. In this embodiment, for example, a material satisfying 0.1≦x≦0.5 and 0.1≦y≦0.5 in the above formula may be used as the material constituting the active layer 16 (or one layer of the active layer 16 when the active layer 16 has a multi-layer structure).

[0016] The p-side semiconductor layer 14 may be composed of a plurality of layers. The p-side semiconductor layer 14 may have, for example, a p-side contact layer, a p-side cladding layer, and a p-side intermediate layer, in this order from the bottom of FIG. 1B and FIG. 1C. The p-side contact layer is for ensuring electrical connection with the p-side electrode 30 and spreading the current. For example, a GaP-based semiconductor material (one of the AlGaInP-based materials, a material that does not contain Al and In) can be used for the p-side contact layer. The thickness of the p-side contact layer may be 0.1 μm or more and 1 μm or less. The cladding layer is for promoting the recombination of electrons and holes in the active layer 16. For example, an AlInP-based semiconductor material can be used for the cladding layer. The thickness of the p-side cladding layer can be 0.1 μm or more and 1 μm or less. The p-side intermediate layer is for reducing the diffusion of impurities in the p-side semiconductor layer 14 to the active layer. For example, an AlGaInP-based semiconductor material can be used for the p-side intermediate layer. The thickness of the p-side intermediate layer may be not less than 0.1 μm and not more than 0.5 μm.

[0017] The active layer 16 may have a multiple quantum well structure having a plurality of well layers and a plurality of barrier layers. In this case, a GaInP-based material may be used for the well layers, and an AlGaInP-based material may be used for the barrier layers. The thickness of one well layer may be 1 nm or more and 10 nm or less. The thickness of one barrier layer may be 10 nm or more and 50 nm or less. The well layers and the barrier layers may be alternately arranged so that the number of well layers is 5 to 20. The total thickness of the active layer 16 may be, for example, 5 μm to 10 μm.

[0018] The first n-side semiconductor layer 12a of the n-side semiconductor layer 12 may be composed of multiple layers. In that case, the material of each layer is selected according to the function it performs. The n-layer may have, for example, an n-side intermediate layer, an n-side cladding layer, and a current diffusion layer, in this order from the bottom of FIG. 1B and FIG. 1C. The n-side intermediate layer is for reducing the movement of impurities in the n-side semiconductor layer 12 to the active layer 16. For the n-side intermediate layer, for example, an AlGaInP-based semiconductor material can be used. The thickness of the n-side intermediate layer can be 0.1 μm or more and 0.5 μm or less. The n-side cladding layer is for promoting the recombination of electrons and holes in the active layer 16, similar to the above-mentioned p-side cladding layer. For the n-side cladding layer, for example, an AlInP-based semiconductor material can be used. The thickness of the n-side cladding layer can be 0.1 μm or more and 1 μm or less. The current diffusion layer is for diffusing current. For example, an AlGaInP-based semiconductor material can be used for the current diffusion layer. The current spreading layer may have a thickness of 1 μm or more and 3 μm or less.

[0019] The thickness of the first n-side semiconductor layer 12a in the second region 10b may be, for example, 1 μm or more and 2 μm or less. By making the thickness of the first n-side semiconductor layer 12a 1 μm or more, it is possible to reduce the occurrence of cracks in the semiconductor structure 10. By making the thickness of the first n-side semiconductor layer 12a 2 μm or less, it is possible to reduce light absorption by the first n-side semiconductor layer 12a.

[0020] The second n-side semiconductor layer 12b includes a semiconductor material having a smaller band gap energy than the first n-side semiconductor layer 12a. For example, when the first n-side semiconductor layer 12a is a layer including an AlGaInP-based material, the second n-side semiconductor layer 12b may be configured to include an AlGaAs-based material. The AlGaAs-based material is, for example, Al z Ga 1-z As (0≦z≦1). In this embodiment, GaAs (where Z=1) is particularly preferably used from the viewpoint of reducing the contact resistance.

[0021] The band gap energy of the AlGaInP-based material is about 1.91 eV or more and 2.23 eV or less, and the band gap energy of the AlGaAs-based material is about 1.42 eV or more and 2.16 eV or less. For example, the band gap energy of GaAs is about 1.4 eV. Since the contact resistance between an AlGaAs-based material and a metal is generally lower than the contact resistance between an AlGaInP-based material and a metal, the AlGaAs-based material is preferably used when the p-side semiconductor layer 14 to the first n-side semiconductor layer 12a are composed of an AlGaInP-based material.

[0022] The thickness of the second n-side semiconductor layer 12b may be, for example, 0.05 μm or more and 0.5 μm or less. By setting the thickness of the second n-side semiconductor layer 12b to 0.05 μm or more, the sheet resistance of the second n-side semiconductor layer 12b can be reduced. By setting the thickness of the second n-side semiconductor layer 12b to 0.5 μm or less, the light absorption by the second n-side semiconductor layer 12b can be reduced.

[0023] In a plan view, the area of ​​the second n-side semiconductor layer 12b may be, for example, 3% to 10% of the area of ​​the light-emitting element 1. By setting it in such a range, it is possible to reduce light absorption by the second n-side semiconductor layer 12b while ensuring the electrical connection between the second n-side semiconductor layer 12b and the n-side electrode 20.

[0024] The semiconductor structure 10 has a region in which the p-side semiconductor layer 14 and the active layer 16 are arranged. In the first n-side semiconductor layer 12a, a region in which the p-side semiconductor layer 14 and the active layer 16 are not arranged is a region in which the first n-side semiconductor layer 12a is exposed from the p-side semiconductor layer 14 and the active layer 16. In this embodiment, in a plan view, the region in which the p-side semiconductor layer 14 and the active layer 16 are arranged in the semiconductor structure 10 is the first region 10a, and the region other than the first region 10a is the second region 10b. As shown in FIG. 2, the second region 10b is surrounded by the first region 10a in a plan view. The second region 10b has an outer peripheral portion 10b1 located near the outer edge of the light-emitting element 1 and a central portion 10b2 located approximately in the center of the light-emitting element 1.

[0025] The first region 10a is a region where light is mainly emitted in the light emitting element 1, and it is preferable to make the first region 10a as large as possible to ensure the amount of light emitted. On the other hand, in the second region 10b, the central portion 10b2 where the second n-side semiconductor layer 12b is arranged is a portion where the n-side electrode 20 and the n-side semiconductor layer 12 are electrically connected. As shown in FIG. 1A, in the light emitting element 1 that is substantially rectangular in plan view, the first region 10a may be configured to occupy, for example, 70% or more of the area of ​​the light emitting element 1, and the second region 10b may be configured to occupy, for example, 10% to 30% of the area of ​​the light emitting element 1. In addition, in plan view, the area of ​​the second n-side semiconductor layer 12b may be configured to occupy, for example, 10% to 20% of the area of ​​the second region 10b.

[0026] When the light-emitting element 1 has a rectangular shape with short sides of 100 μm to 2000 μm and long sides of 100 μm to 2000 μm, the second region 10b may include a substantially rectangular central portion 10b2 with short sides of 1 μm to 10 μm and long sides of 50 μm to 1500 μm, and a peripheral portion 10b1 having a width of 1 μm to 15 μm from the outer edge of the light-emitting element 1. In this case, the shape of the second n-side semiconductor layer 12b may be a rectangle with short sides of 1 μm to 10 μm and long sides of 50 μm to 1500 μm.

[0027] 1B and 1C, the first n-side semiconductor layer 12a has an opening hn located in the central portion 10b2 of the second region 10b. In the opening hn, the second n-side semiconductor layer 12b is exposed from the first n-side semiconductor layer 12a. The opening hn may have a shape and area such that, for example, 60% to 90% of the surface of the second n-side semiconductor layer 12b is exposed in a plan view.

[0028] As shown in FIG. 1B and FIG. 1C, among the surfaces of the first n-side semiconductor layer 12a on the side opposite to the p-side semiconductor layer 14, the surface where the first n-side semiconductor layer 12a and the second n-side semiconductor layer 12b do not overlap in plan view is a rough surface. This is to reduce the total reflection of light from the active layer 16 and improve the light extraction efficiency. The Ra (arithmetic mean roughness) of the first n-side semiconductor layer 12a, which is a rough surface, may be, for example, 0.05 μm or more. The rough surface of the first n-side semiconductor layer 12a may be, for example, a surface that is made up of convex parts or concave parts having an irregular shape and arrangement, or a surface that is made up of convex parts or concave parts having a regular shape and arrangement. Alternatively, the rough surface may be a surface that has both convex parts or concave parts having an irregular shape and arrangement and convex parts or concave parts having a regular shape and arrangement.

[0029] 2.N side electrode The n-side electrode 20 is disposed in the opening hn, and is in contact with the second n-side semiconductor layer 12b exposed from the first n-side semiconductor layer 12a, and is electrically connected to the n-side semiconductor layer 12. As will be described later, the n-side electrode 20 is electrically connected to the wiring layer 70, and is electrically connected to the n-side pad electrode 50 via the wiring layer 70.

[0030] The n-side electrode 20 is located in an opening hn of the first n-side semiconductor layer 12a and an opening h1 of an insulating film 45a described later. A part of the n-side electrode 20 covers the lower surface of the insulating film 45a in Figures 1B and 1C. The n-side electrode 20 overlaps with the second n-side semiconductor layer 12b in a plan view.

[0031] The n-side electrode 20 may be made of a material containing at least one metal selected from, for example, Au, Ag, Al, Ni, Pd, Ge, Si, and Sn, and may be made of, for example, an alloy containing one or more of these metals. The n-side electrode 20 may have a multilayer structure. More specifically, the n-side electrode 20 may have a multilayer structure in which AuGe, Ni, Ti, Pt, and Ti are stacked in this order from the second n-side semiconductor layer 12b side. The thickness of the n-side electrode 20 may be, for example, 100 nm or more and 500 nm or less.

[0032] 3.p side electrode The p-side electrode 30 is located on the bottom surface of the p-side semiconductor layer 14 in FIG. 1B and FIG. 1C. As shown in FIG. 3, a plurality of p-side electrodes 30 are arranged on the semiconductor structure 10. The shape of the p-side electrodes 30 in plan view is, for example, circular. The p-side electrodes 30 are regularly arranged so that the distance between the p-side electrodes 30 is the same in plan view. This arrangement can reduce light absorption by the p-side electrodes 30 while reducing bias in the current density distribution of the light emitting element 1. When the shape of the p-side electrodes 30 in plan view is circular, for example, the p-side electrodes 30 having a diameter of 3 μm to 20 μm may be arranged at intervals (the distance between the centers of adjacent p-side electrodes 30) of 30 μm to 100 μm. Alternatively, the p-side electrodes 30 may be irregularly arranged.

[0033] 1B and 1C of the p-side semiconductor layer 14. In that case, the current can be diffused over a wider range via the p-side electrode 30, and the bias in the current density distribution can be further reduced.

[0034] The p-side electrode 30 may be made of a material containing at least one metal selected from, for example, Au, Ag, Al, Ni, Pd, Ge, Si, In, and Sn, and may be made of, for example, an alloy containing one or more of these metals. The p-side electrode 30 may be made of a material that contains In, Sn, and O and has electrical conductivity. The material containing In, Sn, and O may be so-called ITO. An electrode using a material containing In, Sn, and O has high translucency with respect to the peak wavelength of light from the active layer 16, and therefore can be suitably used for the p-side electrode 30. The p-side electrode 30 may have a laminated structure. The thickness of the p-side electrode 30 may be, for example, 10 nm or more and 100 nm or less.

[0035] 4. Dielectric multilayers and insulating films The light emitting element 1 of this embodiment has a configuration in which an n-side pad electrode 50 and a p-side pad electrode 60 are arranged on the same side of a semiconductor structure 10. In this embodiment, in order to arrange the n-side pad electrode 50 and the p-side pad electrode 60 in a desired position and shape regardless of the positions of the n-side electrode 20 and the p-side electrode 30, electrical insulation between the n-side electrode 20 and the p-side electrode 30 and electrical connection between these electrodes and the n-side pad electrode 50 and the p-side pad electrode 60 are ensured by using the dielectric multilayer film 40, insulating films 45a, 45b, and a wiring layer 70 described later.

[0036] A dielectric multilayer film 40 and insulating films 45a and 45b are disposed on the semiconductor structure 10. The dielectric multilayer film 40 is a DBR (Distributed Bragg Reflector) film in which dielectrics with high refractive index and dielectrics with low refractive index are alternately laminated. For example, the dielectric multilayer film 40 is a combination of a high refractive index dielectric and a low refractive index dielectric, such as a Nb2O5 layer and a SiO2 layer, and a TiO2 layer and a SiO2 layer, and this combination is repeatedly laminated in 10 to 30 pairs. In one combination of a high refractive index dielectric and a low refractive index dielectric, the thickness of each dielectric may be 100 nm to 200 nm. The dielectric multilayer film 40 is disposed so as to cover substantially the entire lower surface of the semiconductor structure 10 in FIG. 1B and FIG. 1C in a plan view, except for the region where the n-side electrode 20 and the p-side electrode 30 are electrically connected to the wiring layer 70. Note that the dielectric multilayer film 40 may not be disposed, and an insulating film may be disposed instead of the dielectric multilayer film 40.

[0037] The insulating film 45a is disposed on the lower surface of the dielectric multilayer film 40 in FIGS. 1B and 1C. The insulating film 45a has an opening h1 that overlaps with the opening hn of the first n-side semiconductor layer 12a in a plan view, and an opening h2 that overlaps with the p-side electrode 30 disposed in the p-side semiconductor layer 14. The n-side electrode 20 is disposed in the opening h1, and the p-side electrode 30 is electrically connected to the wiring layer 70 at the opening h2. As shown in FIGS. 2 and 4, the opening h1 is disposed so as to overlap with the center portion 10b2 of the second region 10b in a plan view. Also, as shown in FIG. 1A, the opening h2 is disposed at a position corresponding to the p-side electrode 30, as a circular shape similar to the p-side electrode 30.

[0038] The insulating film 45b electrically insulates the n-side wiring portion 70a connected to the n-side electrode 20 and the p-side wiring portion 70b connected to the p-side electrode 30 of the wiring layer 70. As shown in FIGS. 1A, 1B, and 5, the insulating film 45b has an opening h3 and an opening h4, the n-side pad electrode 50 and the wiring layer 70 are electrically connected to each other through the opening h3, and the p-side pad electrode 60 and the wiring layer 70 are electrically connected to each other through the opening h4. In the portions other than the openings h3 and h4, the insulating film 45b is located between the n-side pad electrode 50 and the p-side pad electrode 60 and the wiring layer 70, and electrically insulates the n-side pad electrode 50 and the p-side pad electrode 60 from each other. In a plan view, the area of ​​the opening h3 is, for example, 5000 μm 2 More than 10000μm 2 In plan view, the area of ​​the opening h4 is, for example, 1000 μm 2 More than 5000μm 2 The following is the result.

[0039] The insulating films 45a and 45b may be made of a material selected from SiO2, SiN, SiON, and the like. A film using SiO2 is preferably used for the insulating films 45a and 45b because it has high light transmittance for the peak wavelength of light emitted by the active layer 16. The thickness of the insulating films 45a and 45b may be 0.1 μm or more and 1 μm or less. The insulating films 45a and 45b may be made of different materials or the same material.

[0040] 5.Wiring layer The wiring layer 70 serves to electrically connect the n-side electrode 20 and the n-side pad electrode 50, and to electrically connect the p-side electrode 30 and the p-side pad electrode 60. As shown in Figures 1B, 1C, and 6, the wiring layer 70 has an n-side wiring portion 70a electrically connected to the n-side electrode 20 and a p-side wiring portion 70b electrically connected to the p-side electrode 30 in a plan view.

[0041] The wiring layer 70 may be made of a material containing at least one metal selected from, for example, Au, Cu, and Al, and may be made of, for example, an alloy containing one or more of these metals. As shown in Fig. 1A and Fig. 6, the wiring layer 70 is disposed in a relatively wide area of ​​the semiconductor structure 10 in a plan view, and therefore, it is preferable to use a material having a high reflectance, particularly for light emitted from the active layer 16, for the wiring layer 70. It is preferable to use, for example, Au for the wiring layer 70. The thickness of the wiring layer 70 may be 100 nm or more and 500 nm or less.

[0042] The positions of the dielectric multilayer film 40, the insulating films 45a, 45b, and the wiring layer 70 are not limited to those shown in the drawings. As long as the connection between the n-side electrode 20 and the p-side electrode 30 and the n-side pad electrode 50 and the p-side pad electrode 60 is ensured, three or more insulating films may be arranged in the thickness direction, and multiple wiring layers 70 may be arranged in the thickness direction. In addition, the positions and shapes of the openings in the insulating films 45a and 45b are not particularly limited.

[0043] 6. Pad electrodes The n-side pad electrode 50 and the p-side pad electrode 60 are portions electrically connected to an external power supply. The n-side pad electrode 50 is electrically connected to the n-side wiring portion 70a through an opening h3 of the insulating film 45b, and the p-side pad electrode 60 is electrically connected to the p-side wiring portion 70b through an opening h4 of the insulating film 45b.

[0044] 1A and 7, the n-side pad electrode 50 and the p-side pad electrode 60 have substantially the same rectangular shape in a plan view, and are disposed substantially symmetrically on the left and right of the light emitting element 1 in the drawings. In a plan view, the area of ​​the n-side pad electrode 50 and the area of ​​the p-side pad electrode 60 are each, for example, 20% or more and 40% or less of the area of ​​the light emitting element 1 in a plan view.

[0045] The n-side pad electrode 50 and the p-side pad electrode 60 may be made of a material containing at least one metal selected from Au, Ag, Pt, Ti, Ni, Ge, Rh, and Ru, and may be made of an alloy, particularly a eutectic, containing one or more of these metals as components. Examples of eutectic used for the n-side pad electrode 50 and the p-side pad electrode 60 are Au-Sn eutectic and Ag-Sn eutectic. The thickness of the n-side pad electrode 50 and the p-side pad electrode 60 may be 100 nm or more and 500 nm or less, respectively.

[0046] 7. Holding part The holding part 80 can protect the semiconductor structure 10 and improve the mechanical strength of the light-emitting element 1. After the semiconductor structure 10 is grown on a growth substrate, the growth substrate is removed and the holding part 80 is disposed on the surface of the light-emitting element 1 on the n-side semiconductor layer 12 side, i.e., so as to replace the growth substrate. When light is extracted from the n-side semiconductor layer 12 side, by disposing the holding part 80 having high light transmittance for the peak wavelength of light from the active layer 16, the amount of extracted light can be increased.

[0047] In this embodiment, the holding unit 80 includes a bonding member 80a and a support substrate 80b. The bonding member 80a is, for example, SiO2. The thickness of the bonding member 80a may be 0.5 μm or more and 2 μm or less.

[0048] In this embodiment, the support substrate 80b may be a sapphire substrate, a glass substrate, or the like. A sapphire substrate is preferably used for the support substrate 80b because of its high mechanical strength and high translucency to light from the active layer 16. The thickness of the support substrate 80b may be 500 μm or more and 1000 μm or less.

[0049] The configuration and material of the holding portion 80 are not limited to those described above, and may be, for example, a single-layer structure composed only of a layer made of SiO2. When the holding portion 80 has a single-layer structure composed only of a layer made of SiO2, the thickness of the holding portion 80 may be 0.5 μm or more and 2 μm or less.

[0050] (Embodiment 2) Next, a description will be given of embodiment 2. In the following description and in Figs. 8 to 11, members that are described using the same reference numerals as those in embodiment 1 are the same members as those described in embodiment 1, and the description of embodiment 1 applies except for the parts that differ from embodiment 1.

[0051] An example of the arrangement of the first region 10a, the second region 10b, and the second n-side semiconductor layer 12b will be described as embodiment 2 with reference to Figs. 8 to 11. In the light emitting device of embodiment 2, the first region 10a of the semiconductor structure 10 is a region including the center C of the light emitting device 1 in plan view as shown in Figs. 8 and 9, and the second n-side semiconductor layer 12b does not overlap with the center C of the light emitting device 1 in plan view. The second region 10b has a shape including an outer peripheral portion 10b1 and an extension portion 10b3 that is disposed continuously with the outer peripheral portion 10b1 and extends from the outer peripheral portion 10b1 toward the center C of the light emitting device. The second n-side semiconductor layer 12b (shown by a dashed line in Figs. 8 and 9) is disposed within the extension portion 10b3 in plan view. The light emitting device of the second embodiment corresponds to a configuration in which the central portion 10b2 of the second region 10b and the second n-side semiconductor layer 12b, which were disposed approximately in the center of the light emitting device 1 in the first embodiment, are disposed toward the long side of the lower semiconductor structure 10 in FIG. 8 and FIG. 9. With this configuration, the first region 10a including the active layer 16 is disposed in the central region of the light emitting device in a plan view, and light is easily emitted from the central region of the light emitting device. In a plan view, the area of ​​the second n-side semiconductor layer 12b may be 50% or more and 70% or less of the area of ​​the extension portion 10b3. By setting it in this range, it is possible to reduce light absorption by the second n-side semiconductor layer 12b while ensuring electrical connection between the second n-side semiconductor layer 12b and the n-side electrode 20.

[0052] The shape and dimensions of the extension portion 10b3 in a plan view may be the same as those of the central portion 10b2 of the second region 10b in the above-described embodiment 1. The shape and dimensions of the outer peripheral portion 10b1 in a plan view may be the same as those of the outer peripheral portion 10b1 of the second region 10b in the above-described embodiment 1.

[0053] As a result of the second region 10b and the second n-side semiconductor layer 12b being positioned toward one of the long sides of the semiconductor structure 10 in a planar view, the shapes and / or arrangements of the p-side electrode 30, the opening hn, the n-side electrode 20, the openings h1, h2, h3 and the wiring layer 70 are also different from those of embodiment 1, as shown in Figures 8 to 10. 9, in the second embodiment, the shape of the p-side electrode 30 in top view is circular, similar to that of the first embodiment. The p-side electrode 30 is disposed near the center C where the second region 10b does not exist, and is not disposed in the region surrounded by the dotted line as shown in FIG 9. This is because, as will be described later, the n-side wiring portion 70a is disposed in that portion for the convenience of disposing the n-side pad electrode 50.

[0054] 10, the insulating film 45a is disposed on the dielectric multilayer film 40 (not shown) so as to cover the entire surface of the light-emitting element, except for the openings h1 and h2 at which the wiring layer 70 is electrically connected to the n-side electrode 20 and the p-side electrode 30. In this embodiment, the opening h1 is disposed in a circular shape in accordance with the shape and arrangement of the p-side electrode 30, as in the first embodiment, and the opening h2 is disposed so as to overlap with the opening hn (not shown) disposed in the first n-side semiconductor layer 12a, as in the first embodiment.

[0055] 9 and 11, the n-side wiring portion 70a covers almost the entire extension portion 10b3 of the second region 10b in a plan view, and has an extension portion 70a1 toward the first region 10a. As will be described later, the extension portion 70a1 is used for electrical connection with the n-side pad electrode 50. The p-side wiring portion 70b is disposed so as to overlap the region of the first region 10a where the p-side electrode 30 shown in FIG. 9 is disposed.

[0056] The insulating film 45b has an opening h3 through which the extension 70a1 of the n-side wiring portion 70a is electrically connected to the n-side pad electrode 50, and an opening h4 through which the p-side electrode 30 is electrically connected to the p-side pad electrode 60. In Fig. 11, the shapes and arrangement of the openings h3 and h4 are indicated by dashed lines, and the n-side pad electrode 50 and the p-side pad electrode 60 are indicated by dashed lines. The opening h3 is arranged so as to overlap the extending portion 70a1 of the wiring layer 70 in order to offset the second n-side semiconductor layer 12b as shown in the figure, while allowing the n-side pad electrode 50 to have the same shape and arrangement as in embodiment 1. In embodiment 2, if it is attempted to arrange the opening h4 so as to overlap the second n-side semiconductor layer 12b as in embodiment 1, it is necessary to also offset the n-side pad electrode 50 or to increase its dimensions so as to overlap the second n-side semiconductor layer 12b.

[0057] The area of ​​the opening h4 in the second embodiment is larger than that of the opening h4 in the first embodiment in plan view. The opening h4 is located closer to the central region of the light emitting element than the light emitting element 1 in the first embodiment. This is because, in the present embodiment, the second region 10b is not located in the central region of the light emitting element, and the p-side electrode 30 is also located in the central region of the light emitting element. By increasing the area of ​​the opening h4 in plan view, the electrical connection between the wiring layer 70 and the p-side pad electrode 60, and further the electrical connection between the p-side electrode 30 and the p-side pad electrode 60, can be made more reliable. For example, the area of ​​the opening h4 may be 60% or more and 90% or less of the area of ​​the p-side pad electrode 60 in plan view.

[0058] According to this embodiment, as described above, the light emitting region can be the approximate center of the light emitting element 1 in plan view. In order to reduce bias in the current density distribution, in this embodiment, the second region 10b in which the second n-side semiconductor layer 12b is disposed may be arranged along two opposing sides of the semiconductor structure 10 in plan view, or along four sides of the semiconductor structure 10. Alternatively, the second region 10b may be arranged at two corners located diagonally across the semiconductor structure 10 in plan view. Alternatively, by combining the first embodiment and the second embodiment, the second region 10b in which the second n-side semiconductor layer 12b is located may be arranged in the approximate center of the semiconductor structure 10 and in a region close to the outer edge of the semiconductor structure 10. In this case, the area of ​​the second region 10b located in the approximate center of the semiconductor structure 10 in plan view may be smaller than the area of ​​the second region 10b located in a region close to the outer edge of the semiconductor structure 10.

[0059] (Embodiment 3) In another embodiment, in order to reduce cracks in the n-side semiconductor layer 12, a part of the second n-side semiconductor layer 12b may be disposed so as to overlap with the first region 10a in a plan view. An example of such a configuration will be described below as embodiment 3 with reference to Fig. 12. The light-emitting device of embodiment 3 differs from the light-emitting device of embodiment 1 mainly in the arrangement of the second n-side semiconductor layer 12b.

[0060] In the light-emitting element 1 of the third embodiment shown in Fig. 12, the second n-side semiconductor layer 12b is not only disposed over the entire second region 10b, but also disposed across the first region 10a. By disposing the second n-side semiconductor layer 12b continuously in the first region 10a and the second region 10b, the area of ​​the second n-side semiconductor layer 12b in a planar view is increased, and cracks are less likely to occur. In order to reduce light absorption by the second n-side semiconductor layer 12b, it is preferable that the area of ​​the portion of the second n-side semiconductor layer 12b disposed in the first region 10a in a planar view is 20% or less of the area of ​​the entire second n-side semiconductor layer 12b in a planar view.

[0061] In addition, the thickness of the portion of the second n-side semiconductor layer 12b arranged in the first region 10a is preferably smaller than the thickness of the portion of the second n-side semiconductor layer 12b arranged in the second region 10b. By reducing the thickness of the second n-side semiconductor layer 12b, it is possible to reduce the absorption of light. The thickness of the portion of the second n-side semiconductor layer 12b arranged in the first region 10a may be, for example, 10% to 50% of the thickness of the portion of the second n-side semiconductor layer 12b arranged in the second region 10b. A step may be formed between the portion of the second n-side semiconductor layer 12b arranged in the first region 10a and the portion of the second n-side semiconductor layer 12b arranged in the second region 10b. Alternatively, the thickness of the second n-side semiconductor layer 12b may decrease from the boundary between the second region 10b and the first region 10a toward the first region 10a, in which case the second n-side semiconductor layer 12b has a trapezoidal cross-sectional shape as shown in the figure.

[0062] Furthermore, as long as at least a part of the thickness of the second n-side semiconductor layer 12b located in the first region 10a is smaller than the thickness of the part located in the second region 10b, the other part may be the same as the thickness of the part located in the second region 10b. For example, in the illustrated embodiment, the position where the reduction in the thickness of the second n-side semiconductor layer 12b starts does not have to be strictly at the boundary between the first region 10a and the second region 10b, but may be shifted toward the first region 10a or the second region 10b.

[0063] (Embodiment 4) As the fourth embodiment, a method for manufacturing the light-emitting device of the first embodiment will be described with reference to FIGS. 13(a) to (o).

[0064] As shown in FIG. 13(a), a semiconductor structure 10 having an underlayer 102, a second n-side semiconductor layer 12b, a first n-side semiconductor layer 12a, an active layer 16, and a p-side semiconductor layer 14 is formed on a growth substrate 100 made of GaAs. The underlayer 102 is formed of, for example, a GaInP layer, and the second n-side semiconductor layer 12b is formed of a GaAs layer. The first n-side semiconductor layer 12a is formed to have, in order from the underlayer 102 side, a current spreading layer, an n-side cladding layer, and an n-side intermediate layer. The current spreading layer is formed of an AlGaInP layer, the n-side cladding layer is formed of an AlInP layer, and the n-side intermediate layer is formed of an AlGaInP layer. The active layer 16 is formed to have an MQW layer in which GaInP layers as barrier layers and GaInP layers as well layers are alternately formed. The p-side semiconductor layer 14 is formed to have, in order from the active layer 16 side, a p-side intermediate layer, a p-side cladding layer, and a p-side contact layer. The p-side intermediate layer is formed of an AlGaInP layer, the p-side cladding layer is formed of an AlInP layer, and the p-side contact layer is formed of a GaP layer. The layers constituting the semiconductor structure 10 of FIG. 13(a) may be formed by a conventional method, such as an MOCVD method or an MOVPE method.

[0065] 13(b), a p-side electrode 30 is formed on the p-side semiconductor layer 14. The p-side electrode 30 is formed, for example, by forming an ITO layer on the p-side semiconductor layer 14 and removing a part of the ITO layer by, for example, wet etching.

[0066] Next, as shown in FIG. 13(c), the p-side semiconductor layer 14, the active layer 16, and a portion of the first n-side semiconductor layer 12a are removed by reactive ion etching or the like to form a first region 10a having the p-side semiconductor layer 14 and the active layer 16, and a second region 10b not having the p-side semiconductor layer 14 or the active layer 16, in the semiconductor structure 10.

[0067] Next, as shown in FIG. 13(d), the dielectric multilayer film 40 is formed. The material and thickness of each film are selected so that the dielectric multilayer film 40 functions as a DBR film, and the dielectric multilayer film 40 is formed by a sputtering method, a CVD method, or the like. After the dielectric multilayer film 40 is formed to cover the semiconductor structure 10, a part of the dielectric multilayer film 40 is removed by wet etching, dry etching, or the like so that the region of the first n-side semiconductor layer 12a where the n-side electrode 20 is arranged and a part of the p-side electrode 30 are exposed from the dielectric multilayer film 40. As a result, the dielectric multilayer film 40 is formed having an opening h1 and an opening h2 through which the n-side electrode 20 and the p-side electrode 30 are electrically connected to the wiring layer 70.

[0068] 13(e), an insulating film 45a having openings h1 and h2 is formed on the dielectric multilayer film 40. The insulating film 45a having openings h1 and h2 is formed by forming the insulating film 45a to cover the dielectric multilayer film 40, and then removing a part of the insulating film 45a by wet etching or the like. The insulating film 45a is formed by a sputtering method or a CVD method.

[0069] 13(f) shows a step of forming the n-side electrode 20. The n-side electrode 20 is formed in the opening h1, and a part of the n-side electrode 20 extends onto the insulating film 45a. The n-side electrode 20 is formed by, for example, a sputtering method, a vapor deposition method, or the like.

[0070] 13(g) shows a step of forming a wiring layer 70 on the insulating film 45a. The wiring layer 70 is formed so as to be electrically connected to the n-side electrode 20 and the p-side electrode 30. The wiring layer 70 is formed in the opening h2 so as to be electrically connected to the p-side electrode 30 at the opening h2. The wiring layer 70 is formed so that the n-side wiring portion 70a and the p-side wiring portion 70b are electrically separated from each other in a plan view. The wiring layer 70 is formed by a sputtering method, a vapor deposition method, or the like.

[0071] 13(h) shows a step of forming an insulating film 45b. The insulating film 45b is formed on the wiring layer 70. In plan view, the insulating film 45b is formed so as to contact the dielectric multilayer film 40 exposed from the wiring layer 70 between the n-side wiring portion 70a and the p-side wiring portion 70b. Furthermore, a part of the insulating film 45b is removed by wet etching or the like so as to become a film having openings h3 and h4 that expose parts of the wiring layer 70. The insulating film 45b is formed by a sputtering method or a CVD method.

[0072] 13(i) shows a process of forming an n-side pad electrode 50 and a p-side pad electrode 60. The n-side pad electrode 50 is formed so as to be electrically connected to the n-side wiring portion 70a exposed from the insulating film 45b. The p-side pad electrode 60 is formed so as to be electrically connected to the p-side wiring portion 70b. The n-side pad electrode 50 and the p-side pad electrode 60 may be formed at the same time as long as they each have a desired shape and size. The n-side pad electrode 50 and the p-side pad electrode 60 are formed by, for example, a sputtering method, a vapor deposition method, or the like.

[0073] FIG. 13(j) shows a step of bonding a support plate 120 supporting the semiconductor structure 10 to the side of the n-side pad electrode 50 and the p-side pad electrode 60 during a step of removing the growth substrate 100, which will be described later. The bonding of the support plate may be performed by disposing a viscous resin 110 on the side of the semiconductor structure 10 on which the n-side pad electrode 50 and the p-side pad electrode 60 are formed, disposing the support plate 120 on the resin 110, and solidifying the resin 110. In this case, the resin 110 functions as an adhesive. The resin 110 may be, for example, a polyimide resin or an epoxy resin, and the support plate 120 may be, for example, a sapphire substrate.

[0074] FIG. 13(k) shows a step of removing the growth substrate 100 to expose the second n-side semiconductor layer 12b. Specifically, the growth substrate 100 and the underlayer 102 shown in FIG. 13(j) are removed to expose the second n-side semiconductor layer 12b. When the growth substrate 100 is a GaAs substrate, the growth substrate 100 may be removed by etching with ammonia hydrogen peroxide (a mixture of ammonia water, hydrogen peroxide water, and pure water). In this case, the underlayer 102 remains as an etch stop layer, and the remaining underlayer 102 is removed with hydrochloric acid. Alternatively, the underlayer 102 may be removed with hydrochloric acid, thereby removing the growth substrate 100.

[0075] 13(l) shows a process of removing the second n-side semiconductor layer 12b to leave at least a part of the second n-side semiconductor layer 12b in the central portion 10b2 of the second region 10b. For example, a mask is formed on the second n-side semiconductor layer 12b overlapping the central portion 10b2, and the second n-side semiconductor layer 12b exposed from the mask is removed to leave the second n-side semiconductor layer 12b in the central portion 10b2. In the case of the second n-side semiconductor layer 12b made of a GaAs layer, the second n-side semiconductor layer 12b may be removed using hydrochloric acid.

[0076] 13(m) shows a step of roughening the surface of the first n-side semiconductor layer 12a opposite to the p-side semiconductor layer 14 side. The first n-side semiconductor layer 12a may be roughened by wet etching using a mask. For example, a mask is formed on the second n-side semiconductor layer 12b, and the first n-side semiconductor layer 12a exposed from the mask is roughened by wet etching. Note that the mask used in the above-mentioned step of leaving the second n-side semiconductor layer 12b may be used in the roughening step.

[0077] 13(n) shows a step of forming the holding part 80. For example, a bonding member 80a is formed by spin coating so as to cover the first n-side semiconductor layer 12a and the second n-side semiconductor layer 12b, and the supporting substrate 80b is bonded to the bonding member 80a as an adhesive. Alternatively, the holding part 80 may be formed by forming the bonding member 80a on one surface of the supporting substrate 80b by spin coating, and bonding the supporting substrate 80b to the n-side semiconductor layer 12. When the bonding member 80a is made of SOG, the supporting substrate 80b is bonded to the n-side semiconductor layer 12, and then heated and solidified to form the holding part 80.

[0078] Fig. 13(o) shows a step of removing the support plate 120 bonded in the step shown in Fig. 13(j). The support plate 120 may be removed by dissolving the resin 110. Thereafter, the light-emitting element 1 can be manufactured by singulating into individual light-emitting elements.

[0079] The present invention includes the following aspects.

[0080] (Appendix 1) a semiconductor structure including an n-side semiconductor layer having a first n-side semiconductor layer and a second n-side semiconductor layer, an active layer, and a p-side semiconductor layer, the active layer being disposed between the n-side semiconductor layer and the p-side semiconductor layer in a thickness direction; an n-side electrode electrically connected to the n-side semiconductor layer; a p-side electrode electrically connected to the p-side semiconductor layer, the active layer emits red light having a peak wavelength in the range of 620 nm to 700 nm, The semiconductor structure has a first region and a second region in a plan view, the first region is a region in which the p-side semiconductor layer and the active layer are disposed, and the second region is a region other than the first region, the first n-side semiconductor layer is disposed in the first region and the second region, the second n-side semiconductor layer is disposed on a surface of the first n-side semiconductor layer opposite to the p-side semiconductor layer side so as to overlap the first n-side semiconductor layer in at least a part of the second region in a plan view, the second n-side semiconductor layer has a smaller band gap energy than the first n-side semiconductor layer, the first n-side semiconductor layer disposed in the second region has an opening exposing the second n-side semiconductor layer, the n-side electrode is electrically connected to the second n-side semiconductor layer in the opening,

[0081] (Appendix 2) 2. The light-emitting device according to claim 1, wherein the second n-side semiconductor layer is not disposed in the first region in a plan view.

[0082] (Appendix 3) 3. The light-emitting device according to claim 1, wherein a portion of the second n-side semiconductor layer is disposed in the first region in a plan view.

[0083] (Appendix 4) 4. The light-emitting device according to any one of claims 1 to 3, wherein in the second region, a thickness of the second n-side semiconductor layer is smaller than a thickness of the first n-side semiconductor layer.

[0084] (Appendix 5) 5. The light-emitting device according to any one of claims 1 to 4, wherein the second region in which the second n-side semiconductor layer is arranged is surrounded by the first region in a plan view.

[0085] (Appendix 6) 6. The light emitting device according to any one of claims 1 to 5, wherein the second n-side semiconductor layer is located in a central region of the light emitting device in a plan view.

[0086] (Appendix 7) the first region includes a center of the light emitting element in a plan view, 6. The light emitting device according to claim 1, wherein the second n-side semiconductor layer does not overlap with a center of the light emitting device in a plan view.

[0087] (Appendix 8) the second region has, in a plan view, an outer periphery and an extension portion disposed continuously with the outer periphery and extending from the outer periphery toward a center of the light emitting element; The light-emitting device according to claim 7, wherein the second n-side semiconductor layer is disposed within the extension portion in a plan view.

[0088] (Appendix 9) 9. The light-emitting device according to claim 8, wherein an area of ​​the second n-side semiconductor layer is 50% or more and 70% or less of an area of ​​the extension portion in a plan view.

[0089] (Appendix 10) The light-emitting device according to any one of Appendices 1 to 9, wherein in a plan view, in a portion of the first n-side semiconductor layer that does not overlap with the second n-side semiconductor layer, a surface of the first n-side semiconductor layer opposite to the p-side semiconductor layer side is a rough surface.

[0090] (Appendix 11) 11. The light emitting device according to any one of claims 1 to 10, wherein an area of ​​the second n-side semiconductor layer is 10% to 20% of an area of ​​the second region in a plan view.

[0091] (Appendix 12) The light-emitting device according to any one of claims 1 to 11, wherein the first n-side semiconductor layer includes an AlGaInP-based material or includes a layer including an AlGaInP-based material, and the second n-side semiconductor layer includes an AlGaAs-based material.

[0092] (Appendix 13) 13. The light emitting device according to any one of claims 1 to 12, wherein an area of ​​the second n-side semiconductor layer is 3% to 10% of an area of ​​the light emitting device in a plan view. [Industrial Applicability]

[0093] The light-emitting element of the present disclosure efficiently emits red light having a peak wavelength in the range of 620 nm or more and 700 nm or less, and is used, for example, as the light source of indicators and traffic lights, automotive lamps, light sources for LED displays, backlights, etc. [Explanation of symbols]

[0094] 1 Light emitting element 10. Semiconductor Structure 10a 1st area 10b 2nd area 12 n-side semiconductor layer 12a First n-side semiconductor layer 12b Second n-side semiconductor layer 14 p-side semiconductor layer 16 Active layer 20 n-side electrode 30 p side electrode 40 Dielectric multilayer film 45a, 45b Insulating film hn, h1, h2, h3, h4 opening 50 n-side pad electrode 60 p-side pad electrode 70 wiring layer 80 Holding part 100 Growth substrate 102 Base layer 110 Resin 120 Support plate

Claims

1. a semiconductor structure including an n-side semiconductor layer having a first n-side semiconductor layer and a second n-side semiconductor layer, an active layer, and a p-side semiconductor layer, the active layer being disposed between the n-side semiconductor layer and the p-side semiconductor layer in a thickness direction; an n-side electrode electrically connected to the n-side semiconductor layer; a p-side electrode electrically connected to the p-side semiconductor layer, the active layer emits red light having a peak wavelength in the range of 620 nm to 700 nm, The semiconductor structure has a first region and a second region in a plan view, the first region is a region in which the p-side semiconductor layer and the active layer are disposed, and the second region is a region other than the first region, the first n-side semiconductor layer is disposed in the first region and the second region, the second n-side semiconductor layer is disposed on a surface of the first n-side semiconductor layer opposite to the p-side semiconductor layer side so as to overlap the first n-side semiconductor layer in at least a part of the second region in a plan view, the second n-side semiconductor layer has a smaller band gap energy than the first n-side semiconductor layer, the first n-side semiconductor layer disposed in the second region has an opening exposing the second n-side semiconductor layer, the n-side electrode is electrically connected to the second n-side semiconductor layer in the opening.

2. The light-emitting element according to claim 1 , wherein the second n-side semiconductor layer is not disposed in the first region in a plan view.

3. The light-emitting element according to claim 1 , wherein a portion of the second n-side semiconductor layer is disposed in the first region in a plan view.

4. 4. The light-emitting element according to claim 1, wherein in the second region, a thickness of the second n-side semiconductor layer is smaller than a thickness of the first n-side semiconductor layer.

5. 4. The light-emitting element according to claim 1, wherein the second region in which the second n-side semiconductor layer is arranged is surrounded by the first region in a plan view.

6. 4. The light emitting element according to claim 1, wherein the second n-side semiconductor layer is located in a central region of the light emitting element in a plan view.

7. The first region includes a center of the light emitting element in a plan view, 4. The light emitting element according to claim 1, wherein the second n-side semiconductor layer does not overlap with a center of the light emitting element in a plan view.

8. the second region has, in a plan view, an outer periphery and an extension portion disposed continuously with the outer periphery and extending from the outer periphery toward a center of the light emitting element; The light-emitting element according to claim 7 , wherein the second n-side semiconductor layer is disposed within the extension portion in a plan view.

9. The light-emitting element according to claim 8 , wherein an area of ​​the second n-side semiconductor layer is equal to or greater than 50% and equal to or less than 70% of an area of ​​the extension portion in a plan view.

10. 4. The light-emitting device according to claim 1, wherein in a plan view, in a portion of the first n-side semiconductor layer that does not overlap with the second n-side semiconductor layer, a surface of the first n-side semiconductor layer opposite to the p-side semiconductor layer side is a rough surface.

11. 4. The light-emitting element according to claim 1, wherein an area of ​​the second n-side semiconductor layer is 10% to 20% of an area of ​​the second region in a plan view.

12. The light-emitting element according to any one of claims 1 to 3, wherein the first n-side semiconductor layer includes an AlGaInP-based material or includes a layer including an AlGaInP-based material, and the second n-side semiconductor layer includes an AlGaAs-based material.

13. 4. The light-emitting element according to claim 1, wherein an area of ​​the second n-side semiconductor layer is equal to or greater than 3% and equal to or less than 10% of an area of ​​the light-emitting element in a plan view.

Images