Drive signal supply device and drive signal calibrating method thereof

Abstract

To provide a drive signal supply device that supplies a drive signal that meets the performance conditions according to the hardware specification and a drive signal calibrating method thereof.SOLUTION: A drive signal supply device includes an oscillation circuit, a drive signal generation circuit, and a control circuit. The oscillation circuit includes a plurality of oscillators each including inverters and outputs a plurality of oscillation signals. A switching characteristic of each of the inverters included in one of the plurality of oscillators is different from a switching characteristic of each of the inverters included in another of the plurality of oscillators. The control circuit detects a process corner of a semiconductor device based on the plurality of oscillation signals. The drive signal generation circuit generates one or more drive signals of the semiconductor device based on the control signal.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, and more particularly to a drive signal supplying device and a drive signal calibration method for the drive signal supplying device. [Background technology]

[0002] The semiconductor device includes a drive signal supplying device and operates based on a drive signal generated by the drive signal supplying device. The drive signal includes an internal voltage or an internal clock, and the internal voltage or the internal clock is supplied to each component included in the semiconductor device.

[0003] A semiconductor device is manufactured according to a set hardware specification. However, in the manufacturing process of the semiconductor device or the operation process in which the semiconductor device actually operates, the semiconductor device may not be manufactured or operate as expected according to the hardware specification due to changes in PVT (process, voltage and temperature), etc., and the performance of the semiconductor device may deteriorate. For example, the voltage level of the internal voltage may be lower than or exceed the voltage level according to the hardware specification, and the duty ratio of the internal clock may not be maintained at 50%. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2003-115750 A [Patent Document 2] Japanese Patent Application Publication No. 11-163691 [Patent Document 3] U.S. Patent No. 10,972,080 [Patent Document 4] U.S. Pat. No. 10,659,014 [Patent Document 5] U.S. Pat. No. 10,943,053 [Patent Document 6] U.S. Pat. No. 10,361,692 [Patent Document 7] U.S. Pat. No. 8,008,967 [Patent Document 8] U.S. Patent No. 7,463,096 [Patent Document 9] U.S. Patent No. 7,859,421 [Patent Document 10] Korean Patent No. 10-1477052 [Patent Document 11] Korean Patent No. 10-2376653 Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention has been made in consideration of the above-mentioned problems in the conventional art, and an object of the present invention is to provide a drive signal supplying device that supplies a drive signal that satisfies performance conditions according to hardware specifications.

[0006] Another object of the present invention is to provide a method for calibrating the drive signal of the drive signal supplying device. [Means for solving the problem]

[0007] In order to achieve the above-mentioned object, one aspect of the present invention provides a drive signal supplying device comprising an oscillator circuit, a drive signal generating circuit, and a control circuit, wherein the oscillator circuit outputs a plurality of oscillation signals, the oscillator circuit includes a plurality of oscillators, each of the plurality of oscillators includes an inverter, switching characteristics of each of the inverters included in one of the plurality of oscillators differ from switching characteristics of each of the inverters included in another of the plurality of oscillators, the drive signal generating circuit generates one or more drive signals for a semiconductor device based on a control signal, and the control circuit detects a process corner of the semiconductor device based on the plurality of oscillation signals.

[0008] In order to achieve the above-mentioned object, one aspect of the present invention provides a drive signal calibration method, in which a plurality of oscillation signals are output by an oscillation circuit, the oscillation circuit includes a plurality of oscillators, each of the plurality of oscillators includes an inverter, switching characteristics of each of the inverters included in one of the plurality of oscillators differ from switching characteristics of each of the inverters included in another of the plurality of oscillators, a process corner of a semiconductor device is detected based on the plurality of oscillation signals, and one or more drive signals of the semiconductor device are calibrated based on the process corner.

[0009] In order to achieve the above-mentioned object, a drive signal supplying device according to another aspect of the present invention comprises an oscillation circuit, a drive signal generating circuit, and a control circuit, wherein the oscillation circuit outputs a plurality of oscillation signals, the oscillation circuit includes a plurality of oscillators, each of the plurality of oscillators includes an inverter, and switching characteristics of each of the inverters included in one of the plurality of oscillators are different from switching characteristics of each of the inverters included in another of the plurality of oscillators, the drive signal generating circuit generates one or more drive signals for a semiconductor device based on a control signal, and the control circuit performs one or more operations including a comparison operation based on the plurality of oscillation signals to generate a control signal. Effect of the Invention

[0010] According to the drive signal supply device of the present invention, a process corner can be detected as a process characteristic of a semiconductor device using a plurality of oscillators that output a plurality of oscillation signals having different oscillation periods or different oscillation frequencies, and one or more drive signals that are supplied to each component included in the semiconductor device can be generated and calibrated based on the process corner.

[0011] The drive signal supplying device can supply one or more drive signals that satisfy the performance conditions set by the hardware specifications to the semiconductor device despite changes in PVT (process, voltage and temperature), etc., thereby preventing deterioration of the performance of the semiconductor device. [Brief description of the drawings]

[0012] [Figure 1] 1 is a block diagram showing a drive signal supplying device according to an embodiment of the present invention; [Diagram 2] 2 is a diagram for explaining a process change in a manufacturing process of a semiconductor device including the drive signal supply device of FIG. [Diagram 3] 3 is a diagram for explaining a process distribution and a process corner showing the process deviation in FIG. 2. FIG. [Figure 4A] 2 is a block diagram showing an example of the oscillator circuit of FIG. 1. [Figure 4B] FIG. 4B is a diagram for explaining the switching characteristics of the oscillator in FIG. 4A. [Diagram 5] 2 is a block diagram showing an example of a control circuit in FIG. 1. [Figure 6] FIG. 6 is a block diagram illustrating an example of a process corner determiner of FIG. 5. [Figure 7] 7 is a flow chart illustrating an example of the operation of the control circuit of FIG. 5 including the process corner determiner of FIG. 6. [Figure 8] 8 is a diagram for explaining a process of determining the process corner of FIG. 7. FIG. [Figure 9] FIG. 8 is a diagram for explaining two or more reference values ​​in FIG. 7. [Figure 10] 2 is a block diagram showing an example of a drive signal generating circuit shown in FIG. 1. [Figure 11] FIG. 7 is a block diagram showing another example of the process corner determiner of FIG. 5. [Figure 12] 12 is a flow chart illustrating an example of the operation of the control circuit of FIG. 5 including the process corner determiner of FIG. 11. [Figure 13] 13 is a diagram for explaining a process of determining the process corner of FIG. 12. FIG. [Figure 14] 1. FIG. 4 is a block diagram showing another example of the drive signal generating circuit of FIG. [Figure 15] 4 is a flowchart illustrating a drive signal calibration method according to an embodiment of the present invention. [Figure 16] 16 is a flowchart showing an example of a process for detecting a process corner in FIG. 15. [Figure 17] 17 is a flow chart illustrating an example of a process for determining the process corner of FIG. 16. [Figure 18] 17 is a flowchart illustrating another example of the process for determining the process corner of FIG. 16. [Figure 19] 4 is a flowchart illustrating a drive signal calibration method according to an embodiment of the present invention. [Figure 20] 1 is a block diagram showing an electronic system including a drive signal supply device according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific examples of the embodiments of the present invention will be described in detail with reference to the drawings.

[0014] FIG. 1 is a block diagram showing a drive signal supplying device according to an embodiment of the present invention.

[0015] 1, the drive signal supplying device 100 is included in the semiconductor device 300. The drive signal supplying device 100 generates one or more drive signals DSs and supplies them to each component included in the semiconductor device 300. For example, the one or more drive signals DSs include an internal voltage or an internal clock, but the scope of the present invention is not limited thereto.

[0016] The drive signal supply device (DSSD) 100 includes an oscillator circuit (OSC) 110, a control circuit 130, and a drive signal generation circuit 150.

[0017] The oscillator circuit 110 outputs a plurality of oscillation signals OSs having different oscillation periods or different oscillation frequencies. For example, the oscillator circuit 110 includes a plurality of oscillators (111-1, 111-n) (n is 2 or more), and outputs a plurality of oscillation signals OSs using the plurality of oscillators (111-1, 111-n).

[0018] In one embodiment, each of the oscillators (111-1, 111-n) includes an inverter, and a switching characteristic of each of the inverters (e.g., 113-1) included in one of the oscillators (111-1, 111-n) is different from a switching characteristic of each of the inverters (e.g., 113-n) included in another of the oscillators (111-1, 111-n). For example, each of the oscillators (111-1, 111-n) is implemented as a "ring oscillator", and each of the inverters included in one ring oscillator has the same switching characteristic, and the inverters included in one ring oscillator have different switching characteristics from the inverters included in the other ring oscillator. For example, a first ring oscillator included in the oscillators (111-1, 111-n) includes only inverters having a first switching characteristic, and a second ring oscillator included in the oscillators (111-1, 111-n) includes only inverters having a second switching characteristic that is different from the first switching characteristic.

[0019] In one embodiment, the inverter included in each of the oscillators 111-1, 111-n includes a p-type metal oxide semiconductor (PMOS) transistor and an n-type metal oxide semiconductor (NMOS) transistor. The hardware specifications of the PMOS transistor and the NMOS transistor included in the inverter are determined so that the inverter has the above switching characteristics.

[0020] In one embodiment, the hardware specifications of the PMOS transistors and NMOS transistors included in the inverter are determined independently of the multiple PMOS transistors and multiple NMOS transistors included in the semiconductor device 300 but not included in the drive signal supplying device 100, so that the multiple oscillators (111-1, 111-n) output multiple oscillation signals OSs having different oscillation periods or different oscillation frequencies. The hardware specifications of the PMOS transistors and NMOS transistors included in the inverter are for calibration of one or more drive signals DSs in the process in which the drive signal supplying device 100 generates one or more drive signals DSs. The oscillator circuit 110 will be described later with reference to Figures 4A and 4B.

[0021] The control circuit 130 receives a plurality of oscillation signals OSs from the oscillation circuit 110. The control circuit 130 detects a process characteristic of the semiconductor device 300 due to a manufacturing process used to manufacture the semiconductor device 300 based on the plurality of oscillation signals OSs, and generates a control signal CTLD based on the detected process characteristic.

[0022] In one embodiment, the control circuit 130 detects a process corner of the semiconductor device 300 and generates a control signal CTLD based on the detected process corner. The process corner is an index for classifying a process distribution, which represents a process deviation of the semiconductor device 300 due to a manufacturing process, according to a certain criterion to identify a process characteristic. "Detecting" a process corner means detecting a type of a process corner, which means "estimating" a type of a process corner, and includes a process of "determining" or "identifying" a process corner. The control circuit 130 will be described later with reference to FIGS. 5, 6, and 11.

[0023] The drive signal generation circuit 150 generates one or more drive signals DSs for the semiconductor device 300 based on the control signal CTLD.

[0024] In one embodiment, the control circuit 130 controls the operation of the drive signal generation circuit 150 based on the control signal CTLD. For example, the control circuit 130 calibrates one or more drive signals DSs based on the control signal CTLD. For example, the drive signal generation circuit 150 adjusts the voltage level or duty ratio of one or more drive signals DSs of the semiconductor device 300 based on the control signal CTLD, and generates and outputs one or more drive signals DSs with the adjusted voltage level or duty ratio.

[0025] In one embodiment, the drive signal generation circuit 150 provides one or more drive signals DSs as a feedback signal FDS to the oscillator circuit 110, which re-outputs a plurality of oscillation signals OSs. For example, the oscillator circuit 110 modifies one of the oscillation signals OSs based on the feedback signal FDS. The drive signal generation circuit 150 will be described below with reference to FIGS. 10 and 14.

[0026] With the above-described configuration, the drive signal supplying device 100 according to one embodiment of the present invention detects a process corner as a process characteristic of a semiconductor device using a plurality of oscillators that output a plurality of oscillation signals having different oscillation periods or different oscillation frequencies, and generates and calibrates one or more drive signals to be supplied to each component included in the semiconductor device based on the process corner.

[0027] The drive signal supplying device of the present invention can supply one or more drive signals that satisfy the performance conditions set by the hardware specifications to a semiconductor device, regardless of changes in PVT (process, voltage and temperature), etc., and can prevent deterioration of the performance of the semiconductor device.

[0028] FIG. 2 is a diagram for explaining a process change in a manufacturing process of a semiconductor device including the drive signal supply device of FIG.

[0029] 2, in a manufacturing process of a semiconductor device, a plurality of chips (or dies) including a plurality of semiconductor devices are mounted on one wafer 10. In FIG. 2, a semiconductor device 300a is mounted on one chip (e.g., 30). The semiconductor device 300a includes a drive signal supplying device 100a. The semiconductor device 300a and the drive signal supplying device 100a correspond to the semiconductor device 300 and the drive signal supplying device 100 in FIG. 1, respectively.

[0030] The PMOS transistor 51 and the NMOS transistor 53 illustrated inside the drive signal supply device (DSSD) 100a represent transistors included in an inverter provided in each of a plurality of oscillators (e.g., 111-1, 111-n in FIG. 1). The PMOS transistor 55 and the NMOS transistor 57 illustrated inside the semiconductor device 300a but outside the drive signal supply device 100a represent a number of PMOS transistors and a number of NMOS transistors included in the semiconductor device 300a but not included in the drive signal supply device 100a.

[0031] In one embodiment, process deviations occur in the transistors (51, 53, 55, 57) of the semiconductor device 300a during the manufacturing process. Despite the process deviations, the transistors (51, 53) are manufactured such that the inverters included in each of the oscillators (111-1, 111-n) have specific switching characteristics, as described above with reference to FIG. 1, but because the transistors (51, 53, 55, 57) are manufactured through the same manufacturing process, the oscillators (111-1, 111-n) output a plurality of oscillation signals that reflect the process deviations.

[0032] 1 relates to transistors (55, 57) included in semiconductor device 300a. For example, the "detection" or "estimation" of the process corner is directed to transistors (55, 57), and the voltage levels or duty ratios of one or more drive signals provided to semiconductor device 300a are calibrated (or adjusted) based on the process corner.

[0033] 2, the semiconductor device 300a mounted on one chip and the driving signal supplying device 100a included in the semiconductor device 300a have been described, but other chips mounted on the wafer 10 are also configured in the same or similar manner. Thus, a driving signal supplying device for the semiconductor device included in each of the multiple chips mounted on the wafer 10 is realized in each of the multiple chips.

[0034] FIG. 3 is a diagram for explaining the process distribution and the process corners showing the process deviations of FIG.

[0035] 3, "71" shows a graph representing process dispersion. The horizontal axis shows the speed of an NMOS transistor (or the magnitude of the drain current in saturation mode of an NMOS transistor), and the vertical axis shows the speed of a PMOS transistor (or the magnitude of the drain current in saturation mode of a PMOS transistor).

[0036] Regarding performance conditions based on the hardware specifications of a semiconductor device, if the speed of an NMOS transistor is manufactured to be faster than a predetermined speed range, it is expressed as "Fast (F)", if it is manufactured to be slower than the predetermined speed range, it is expressed as "Slow (S)", and if it is manufactured to meet the predetermined speed range, it is expressed as "Typical (T)". The same applies to PMOS transistors.

[0037] Regarding performance conditions according to the hardware specifications of the semiconductor device, when the speed of the NMOS transistor is manufactured to be slower than a predetermined speed range and when the speed of the PMOS transistor is manufactured to be faster than a predetermined speed range, it is represented as a process corner ("Slow-Fast (SF)"). When the speed of the NMOS transistor is manufactured to be faster than a predetermined speed and when the speed of the PMOS transistor is manufactured to be slower than a predetermined speed range, it is represented as a process corner ("Fast-Slow (FS)"). Similarly, process corners ("FF", "TT", "SS") are determined. For example, the process corners are represented by a combination of two letters that sequentially represent the characteristics of the NMOS transistor and the characteristics of the PMOS transistor by the manufacturing process.

[0038] “75” in FIG. 3 shows the process corners (“SF”, “TF”, “FF”, “ST”, “TT”, “FT”, “SS”, “TS”, and “FS”) as a table.

[0039] Fig. 4A is a block diagram showing an example of the oscillator circuit of Fig. 1. Fig. 4B is a diagram for explaining the switching characteristics of the oscillator of Fig. 4A.

[0040] 4A, an oscillator circuit (OSC) 500 outputs a plurality of oscillation signals having different oscillation periods or different oscillation frequencies. For example, the oscillator circuit 500 includes a plurality of ring oscillators (RO1, ROn) (n is 2 or more) (510, 530), each of which outputs a plurality of oscillation signals (OS1, OSn) having a different oscillation frequency (e.g., f1, fn).

[0041] In one embodiment, each of the plurality of ring oscillators (510, 530) comprises an inverter, and the switching characteristics of each of the inverters included in one of the plurality of ring oscillators (510, 530) are different from the switching characteristics of each of the inverters included in the other one of the plurality of ring oscillators (510, 530).

[0042] In one embodiment, the inverters included in each of the ring oscillators 510 and 530 include a PMOS transistor and an NMOS transistor connected in series between a power supply voltage VDD and a ground voltage, and the hardware specifications of the PMOS transistor and the NMOS transistor included in the inverter are determined so that the inverter has switching characteristics. For example, the PMOS transistor and the NMOS transistor included in the ring oscillator 510 are determined to have channel widths (Wp1, Wn1), respectively, and the PMOS transistor and the NMOS transistor included in the ring oscillator 530 are determined to have channel widths (Wpn, Wnn), respectively.

[0043] Referring to Figures 4A and 4B, the switching characteristic of an inverter refers to a change in an output signal due to a change in an input signal taking into account the passage of time, and is distinguished from a direct current (DC) characteristic, which refers to a change in an output signal due to a change in an input signal without taking into account the passage of time.

[0044] The oscillation frequency of the ring oscillator is determined based on the logical effort, the electrical effort, the parasitic delay, and the number of inverters included in the ring oscillator, and the logical effort is defined as the ratio of the input capacitance of a given gate to the input capacitance of an inverter that transmits the same output current. For example, the channel widths (Wn1, Wnn) of the NMOS transistors included in the ring oscillators (510, 530) are configured to have the same value. The channel width Wpn of the PMOS transistor included in the ring oscillator 530 is configured to be larger than the channel width Wnn of the PMOS transistor included in the ring oscillator 510. By configuring the logical efforts of the ring oscillators (510, 530) to be different from each other in the above manner, the ring oscillators (510, 530) output a plurality of oscillation signals having different oscillation periods or different oscillation frequencies.

[0045] In one embodiment, a channel width ratio is defined for each of the inverters included in each ring oscillator. The channel width ratio is defined as the ratio of the channel width of the PMOS transistor to the channel width of the NMOS transistor included in each of the inverters included in each ring oscillator. For example, each of the inverters included in the ring oscillator RO1 has a channel width ratio (Wp1 / Wn1), and each of the inverters included in the ring oscillator ROOn has a channel width ratio (Wpn / Wnn). For example, the channel width ratio of each of the inverters included in the ring oscillator ROOn is greater than the channel width ratio of each of the inverters included in the ring oscillator RO1.

[0046] In one embodiment, the number of ring oscillators (510, 530) included in the oscillator circuit 500 is determined according to the type of driving signal. For example, if the driving signal is an internal voltage, the number of ring oscillators (510, 530) is two or more. If the driving signal is an internal clock signal, the number of ring oscillators (510, 530) is three or more, but the scope of the present invention is not limited thereto.

[0047] FIG. 5 is a block diagram illustrating an example of the control circuit of FIG.

[0048] 1 and 5, a control circuit 700 corresponds to the control circuit 130. The control circuit 700 receives a plurality of oscillation signals OSs (OS1, ..., OSn), detects a process corner of the semiconductor device based on the plurality of oscillation signals OSs, and generates a control signal CTLD.

[0049] The control circuit 700 includes a counter 710 , a process corner determiner 730 , and a control signal generator 750 .

[0050] The counter 710 counts the oscillation signals OSs to generate a plurality of count values ​​CNTVs (CNTV1, ..., CNTVn). For example, the counter 710 counts the rising edges or falling edges of the oscillation signals OSs. For example, the counter 710 counts the oscillation signal OS1 to generate the count value CNTV1, and counts the oscillation signal OSn to generate the count value CNTVn.

[0051] The process corner determiner 730 determines a process corner based on the plurality of count values ​​CNTV. In one embodiment, the process corner determiner 730 generates and outputs process corner information PRCI that includes information regarding the process corner.

[0052] The control signal generator 750 receives the process corner information PRCI and generates a control signal CTLD based on the process corner.

[0053] In one embodiment, the process corner determiner 730 stores reference value information (REFI) 731 including two or more reference values ​​for distinguishing between types of process corners. The reference value information 731 is pre-stored in the process corner determiner 730 before the operation of the drive signal generating apparatus according to an embodiment of the present invention.

[0054] In one embodiment, in the process of determining the process corner, two or more reference values ​​may or may not be used depending on the type of drive signal that the drive signal supplying device (e.g., 100 in FIG. 1) generates or calibrates. If the drive signal supplying device generates or calibrates an internal voltage, two or more reference values ​​are used. If the drive signal supplying device generates or calibrates an internal clock signal, two or more reference values ​​are not used.

[0055] In one embodiment, the process corner determiner 730 is configured differently and distinguishes between the types of process corners in different ways when generating or calibrating an internal voltage and when generating or calibrating an internal clock. The case of generating or calibrating an internal voltage will be described with reference to Figures 6 to 10, and the case of generating or calibrating an internal clock signal will be described below with reference to Figures 11 to 14.

[0056] FIG. 6 is a block diagram illustrating an example of the process corner determiner of FIG.

[0057] 5 and 6, a process corner determiner 730a corresponds to the process corner determiner 730. The process corner determiner 730a is used to generate or calibrate internal voltages as driving signals supplied to the semiconductor device.

[0058] The process corner determiner 730a determines the process corner based on two or more reference values ​​(REF1, REF2) for distinguishing the type of the process corner and a plurality of count values ​​(CNTV1, CNTV2). In this case, the oscillation circuit (e.g., 500 in FIG. 4A) includes two oscillators (or two ring oscillators), generates oscillation signals (OS1, OS2) (i.e., when n is 2 in FIG. 4A or FIG. 5), and counts the oscillation signals (OS1, OS2) to generate a plurality of count values ​​(CNTV1, CNTV2). In this case, the number of oscillators included in the oscillation circuit is merely an example. As described above with reference to FIGS. 4A and 4B, the ratio of the channel widths of the inverters provided in the ring oscillator that outputs the oscillation signal OS2 is greater than the ratio of the channel widths of the inverters provided in the ring oscillator that outputs the oscillation signal OS1.

[0059] The process corner determiner 730a includes an average value calculator 731a and comparators (733a, 735a).

[0060] The average value calculator 731a receives the multiple count values ​​(CNTV1, CNTV2) and calculates an average count value AVG_CNTV by averaging the multiple count values ​​(CNTV1, CNTV2).

[0061] The comparators (733a, 735a) compare the average count value AVG_CNTV to two or more reference values ​​(REF1, REF2) to determine the process corners. In one embodiment, the comparator 733a compares the average count value AVG_CNTV to the reference value REF1 to generate a comparison result CR1, and the comparator 735a compares the average count value AVG_CNTV to the reference value REF2 to generate a comparison result CR2.

[0062] The process corner determiner 730a determines the type of the process corner based on the comparison result (CR1, CR2). The process corner determiner 730a generates and outputs process corner information PRCI including information on the process corner. For example, the process corner determiner 730a generates the process corner information PRCI as the comparison result (CR1, CR2).

[0063] FIG. 7 is a flow chart illustrating an example of the operation of the control circuit of FIG. 5 including the process corner determiner of FIG.

[0064] 5 to 7, the control circuit 700 receives a plurality of oscillation signals (OS1, OS2) (step S100).

[0065] The counter 710 counts a plurality of oscillation signals (OS1, OS2) to generate a plurality of count values ​​(CNTV1, CNTV2) (step S200).

[0066] The process corner determiner 730a averages the multiple count values ​​(CNTV1, CNTV2) to generate an average count value AVG_CNTV (step S300).

[0067] The process corner determiner 730a determines whether the average count value AVG_CNTV is smaller than a reference value REF1 (step S510), and determines whether the average count value AVG_CNTV is smaller than a reference value REF2 (step S530). The process corner determiner 730a distinguishes the type of the process corner according to steps S510 and S530. As will be described later with reference to FIG. 12, the process corner determiner 730a distinguishes the type of the process corner in a different manner than the process corner determiner 730b. For example, the first to third types of process corners classified by the process corner determiner 730a are different from the fourth to sixth types of process corners classified by the process corner determiner 730b.

[0068] If the average count value AVG_CNTV is smaller than the reference value REF1 (step S510: YES), the process corner determiner 730a determines the process corner as a first type (step S710). The control signal generator 750 increases the voltage level IVL of the internal voltage based on the fact that the process corner is determined as the first type (step S910). The first type corresponds to a case where the speed of the transistors of the semiconductor device is manufactured to be slower than a predetermined speed range with respect to the performance condition according to the hardware specifications of the semiconductor device.

[0069] If the average count value AVG_CNTV is equal to or greater than the reference value REF1 (step S510: NO) and if the average count value AVG_CNTV is smaller than the reference value REF2 (step S530: YES), the process corner determiner 730a determines the process corner as a second type (step S730). The control signal generator 750 maintains the voltage level IVL of the internal voltage based on the determination of the process corner as the second type (step S930). The second type corresponds to a case where the speed of the transistors of the semiconductor device is manufactured to satisfy a predetermined speed range with respect to the performance condition according to the hardware specification of the semiconductor device.

[0070] If the average count value AVG_CNTV is equal to or greater than the reference value REF1 (step S510: NO) and equal to or greater than the reference value REF2 (step S530: NO), the process corner determiner 730a determines the process corner as a third type (step S750). The control signal generator 750 reduces the voltage level IVL of the internal voltage based on the determination of the process corner as the third type (step S950). The third type corresponds to a case where the speed of the transistor of the semiconductor device is manufactured to be faster than a predetermined speed range with respect to the performance condition according to the hardware specification of the semiconductor device. The first, second, and third types will be described with reference to FIG. 8. The reference values ​​(REF1, REF2) will be described later with reference to FIG. 9.

[0071] FIG. 8 is a diagram for explaining the process of determining the process corner of FIG.

[0072] 8 indicates the average count value AVG_CNTV associated with the process corners "SF", "TF", "FF", "ST", "TT", "FT", "SS", "TS", and "FS", and "93" in FIG. 8 indicates the first type, the second type, and the third type. The average count value AVG_CNTV in "91" in FIG. 8 is data collected by testing in advance before the operation of the driving signal generating device according to an embodiment of the present invention. For example, a large number of average count values ​​AVG_CNTV are collected from a large number of test semiconductor devices manufactured to represent various process corners "SF", "TF", "FF", "ST", "TT", "FT", "SS", "TS", and "FS", each of which includes a driving signal supplying device (e.g., 100 in FIG. 1).

[0073] In one embodiment, the average count value AVG_CNTV collected from test semiconductor devices representing process corners "SS", "TS", and "ST" represents AVG3. The average count value AVG_CNTV collected from test semiconductor devices representing process corners "TT", "SF", and "FS" represents AVG2. The average count value AVG_CNTV collected from test semiconductor devices representing process corners "FF", "TF", and "FT" represents AVG1. AVG1 is greater than AVG2, which is greater than AVG3.

[0074] In one embodiment, process corners corresponding to (or related to) the same or similar average count value AVG_CNTV are classified into one type of process corner. For example, in "93" in FIG. 8, the process corners "SS", "TS", and "ST" corresponding to the average count value AVG_CNTV of AVG3 are classified as a first type of process corner 93-1. The process corners "TT", "SF", and "FS" corresponding to the average count value AVG_CNTV of AVG2 are classified as a second type of process corner 93-2. The process corners "FF", "TF", and "FT" corresponding to the average count value AVG_CNTV of AVG1 are classified as a third type of process corner 93-3.

[0075] FIG. 9 is a diagram for explaining two or more reference values ​​in FIG.

[0076] 7 to 9, reference values ​​(REF1, REF2) are set to distinguish the first type 93-1, the second type 93-2, and the third type 93-3 of the process corners.

[0077] In one embodiment, the reference value REF1 is set to have a value smaller than AVG2 and larger than AVG3 in order to distinguish between the first type 93-1 and the second type 93-2, and the reference value REF2 is set to have a value smaller than AVG1 and larger than AVG2 in order to distinguish between the third type 93-3 and the second type 93-2.

[0078] As described above with reference to FIG. 7, the process corner determiner 730 determines whether the average count value AVG_CNTV is less than the reference value REF1 (step S510), and determines whether the average count value AVG_CNTV is less than the reference value REF2 (step S530).

[0079] The process corner determiner 730 determines the type of the process corner based on the determinations in steps S510 and S530, and the control signal generator 750 increases, maintains, or decreases the voltage level IVL of the internal voltage according to steps S910, S930, and S950.

[0080] FIG. 10 is a block diagram showing an example of the drive signal generating circuit of FIG.

[0081] 1 and 10, the drive signal generation circuit 900a corresponds to the drive signal generation circuit 150. The drive signal generation circuit 900a receives a control signal CTLD from a control circuit (e.g., 700 in FIG. 5) including a process corner determiner (e.g., 730a in FIG. 6), and generates or calibrates one or more drive signals DSs including an internal voltage IV based on the control signal CTLD.

[0082] The drive signal generating circuit 900a includes a controller 910a and an internal voltage generator 930a. The controller 900a controls the internal voltage generator 930a based on a control signal CTLD. The internal voltage generator 930a generates or calibrates one or more drive signals DSs including an internal voltage IV under the control of the controller 900a.

[0083] In one embodiment, the internal voltage generator 930a calibrates the voltage level of the internal voltage IV by increasing, maintaining, or decreasing the voltage level of the internal voltage IV according to steps S910, S930, and S950 of FIG. 7 under the control of the controller 900a.

[0084] FIG. 11 is a block diagram illustrating another example of the process corner determiner of FIG.

[0085] 5 and 11, a process corner determiner 730b corresponds to the process corner determiner 730. The process corner determiner 730b is used to generate or calibrate an internal clock as a driving signal supplied to a semiconductor device.

[0086] The process corner determiner 730b determines the process corner based on the multiple count values ​​(CNTV1, CNTV2, CNTV3). In this case, the oscillation circuit (e.g., 500 in FIG. 4A) includes three oscillators (or three ring oscillators), generates oscillation signals (OS1, OS2, OS3) (i.e., when n is 3 in FIG. 4A or FIG. 5), and counts the oscillation signals (OS1, OS2, OS3) to generate multiple count values ​​(CNTV1, CNTV2, CNTV3). In this case, the number of oscillators included in the oscillation circuit is merely an example. As described above with reference to FIG. 4A and FIG. 4B, the channel width ratio of each inverter provided in the ring oscillator that outputs the oscillation signal OS3 is greater than the channel width ratio of each inverter provided in the ring oscillator that outputs the oscillation signal OS2. The channel width ratio of each inverter provided in the ring oscillator that outputs the oscillation signal OS2 is greater than the channel width ratio of each inverter provided in the ring oscillator that outputs the oscillation signal OS1.

[0087] The process corner determiner 730b includes comparators (731b, 733b).

[0088] The comparators (731b, 733b) compare the multiple count values ​​(CNTV1, CNTV2, CNTV3) to each other to determine a process corner. In one embodiment, the comparator 731b compares the count values ​​(CNTV1, CNTV2) to each other to generate a comparison result CR3, and the comparator 733b compares the count values ​​(CNTV2, CNTV3) to each other to generate a comparison result CR4.

[0089] The process corner determiner 730b determines the type of the process corner based on the comparison result (CR3, CR4). The process of determining the type of the process corner will be described with reference to FIG. 12. The process corner determiner 730b generates and outputs process corner information PRCI including information about the process corner. For example, the process corner determiner 730b generates the process corner information PRCI based on the comparison result (CR3, CR4).

[0090] FIG. 12 is a flow chart illustrating an example of the operation of the control circuit of FIG. 5 including the process corner determiner of FIG.

[0091] 5, 11 and 12, the control circuit 700 receives a plurality of oscillation signals (OS1, OS2, OS3) (step S100-1).

[0092] The counter 710 counts a plurality of oscillation signals (OS1, OS2, OS3) to generate a plurality of count values ​​(CNTV1, CNTV2, CNTV3) (step S200-1).

[0093] The process corner determiner 730b determines whether the count value CNTV1 is greater than the count value CNTV2 (step S510-1), and if the count value CNTV1 is not greater than the count value CNTV2, determines whether the count value CNTV3 is greater than the count value CNTV2 (step S530-1). The process corner determiner 730b distinguishes the type of the process corner according to steps S510-1 and S530-1. As described above with reference to FIG. 7, the process corner determiner 730b classifies the type of the process corner in a different manner than the process corner determiner 730a. For example, the fourth to sixth types of the process corners classified by the process corner determiner 730b are different from the first to third types of the process corners classified by the process corner determiner 730a.

[0094] If the count value CNTV1 is greater than the count value CNTV2 (step S510-1: YES), the process corner determiner 730b determines the process corner as a fourth type (step S710-1). The control signal generator 750 reduces the duty ratio DTR of the internal clock signal based on the determination of the process corner as the fourth type (step S910-1). The fourth type is a case where the PMOS transistor and the NMOS transistor of the semiconductor device are manufactured unbalanced with respect to the performance condition according to the hardware specification of the semiconductor device. For example, the fourth type corresponds to a case where the speed of the PMOS transistor is manufactured relatively faster than the speed of the NMOS transistor.

[0095] If the count value CNTV1 is equal to or smaller than the count value CNTV2 (step S510-1: NO) and if the count value CNTV3 is greater than the count value CNTV2 (step S530-1: YES), the process corner determiner 730b determines the process corner as the fifth type (step S730-1). The control signal generator 750 increases the duty ratio DTR of the internal clock signal based on the determination of the process corner as the fifth type (step S930-1). The fifth type is a case where the PMOS transistor and the NMOS transistor of the semiconductor device are manufactured unbalanced with respect to the performance condition according to the hardware specification of the semiconductor device. For example, the fifth type corresponds to a case where the speed of the PMOS transistor of the semiconductor device is manufactured relatively slower than the speed of the NMOS transistor.

[0096] 12, the process corner determiner 730b may determine the process corner as the fifth type (step S730-1) by immediately performing step S530-1 without performing step S510-1 after step S200-1. For example, if the count value CNTV3 is greater than the count value CNTV2 (step S530-1: YES), the process corner determiner 730b determines the process corner as the fifth type (step S730-1).

[0097] If the count value CNTV1 is equal to or less than the count value CNTV2 (step S510-1: NO) and if the count value CNTV3 is equal to or less than the count value CNTV2 (step S530-1: NO), the process corner determiner 730b determines the process corner as the sixth type (step S750-1). The control signal generator 750 maintains the duty ratio DTR of the internal clock based on the determination of the process corner as the sixth type (step S950-1). The sixth type is a case where the PMOS transistor and the NMOS transistor of the semiconductor device are manufactured in a well-balanced manner with respect to the performance condition according to the hardware specification of the semiconductor device. For example, the sixth type corresponds to a case where the speed of the PMOS transistor of the semiconductor device is manufactured to be substantially equal to the speed of the NMOS transistor. The fourth type, the fifth type, and the sixth type will be described with reference to FIG. 13.

[0098] FIG. 13 is a diagram for explaining the process of determining the process corner of FIG.

[0099] 13 indicates count values ​​(CNTV1, CNTV2, CNTV3) related to the process corners "TT", "SS", "FF", "SF", and "FS", and "97" in FIG. 13 indicates the fourth, fifth, and sixth types. The count values ​​(CNTV1, CNTV2, CNTV3) of "95" in FIG. 13 are data collected by testing in advance before the operation of the driving signal generating device according to an embodiment of the present invention, and are collected as multiple count values ​​(CNTV1, CNTV2, CNTV3) from a number of test semiconductor devices manufactured to represent various process corners "TT", "SS", "FF", "SF", and "FS", each of which includes a driving signal supplying device (e.g., 100 in FIG. 1).

[0100] In one embodiment, the count values ​​(CNTV1, CNTV2, CNTV3) collected from the test semiconductor device representing the process corner "TT" represent values ​​near CV5. The count values ​​(CNTV1, CNTV2, CNTV3) collected from the test semiconductor device representing the process corners "SF" and "FS" represent values ​​near CV4, and the count values ​​(CNTV1, CNTV2, CNTV3) collected from the test semiconductor device representing the process corner "SS" represent values ​​near CV4. The count values ​​(CNTV1, CNTV2, CNTV3) collected from the test semiconductor device representing the process corner "FF" represent values ​​between CV7 and CV6. CV7 is greater than CV6, which is greater than CV5, which is greater than CV4.

[0101] In one embodiment, the process corners corresponding to count values ​​(CNTV1, CNTV2, CNTV3) having the same or similar pattern are classified into one type of process corner.

[0102] For example, in "95" in FIG. 13, when the count value CNTV1 is greater than the count value CNTV2, the corresponding process corner "SF" is classified as the fourth type 97-4 of the process corner.

[0103] For example, the process corner FS corresponding to the case where the count value CNTV1 is equal to or smaller than the count value CNTV2 and the count value CNTV3 is larger than the count value CNTV2 is classified as the fifth type 97-5 of the process corner.

[0104] For example, the process corners "FF", "TT", and "SS" corresponding to the cases where the count value CNTV1 is equal to or smaller than the count value CNTV2 and the count value CNTV3 is equal to or smaller than the count value CNTV2 are classified as the sixth type 97-6 of the process corners.

[0105] FIG. 14 is a block diagram showing another example of the drive signal generating circuit of FIG.

[0106] 1 and 14, the drive signal generation circuit 900b corresponds to the drive signal generation circuit 150. The drive signal generation circuit 900b receives a control signal CTLD from a control circuit (e.g., 700 in FIG. 5) including a process corner determiner (e.g., 730b in FIG. 11), and generates or calibrates one or more drive signals DSs including an internal clock IC based on the control signal CTLD.

[0107] The drive signal generating circuit 900b includes a controller 910b and an internal clock generator 930b. The controller 910b controls the internal clock generator 930b based on a control signal CTLD. The internal clock generator 930b generates or calibrates one or more drive signals DSs including an internal clock IC under the control of the controller 910b.

[0108] In one embodiment, the internal clock generator 930b calibrates the internal clock IC by decreasing, increasing, or maintaining the duty ratio of the internal clock IC according to steps S910-1, S930-1, and S950-1 of FIG. 12 under the control of the controller 910b.

[0109] As described above with reference to Figure 12, the process corner determiner 730b compares the multiple count values ​​with each other to determine the process corner. The oscillator circuit (e.g., 500 in Figure 4A) includes multiple oscillators, including a first oscillator that outputs a first oscillator signal, a second oscillator that outputs a second oscillator signal, and a third oscillator that outputs a third oscillator signal.

[0110] In one embodiment, each of the inverters in the first oscillator has a first ratio of channel widths, each of the inverters in the second oscillator has a second ratio of channel widths, and each of the inverters in the third oscillator has a third ratio of channel widths, the second ratio of channel widths being greater than the first ratio of channel widths, and the third ratio of channel widths being greater than the first ratio of channel widths.

[0111] The process corner determiner 730b compares the frequency of the first oscillating signal, the frequency of the second oscillating signal, and the frequency of the third oscillating signal to determine the process corner. In one embodiment, a counter (e.g., 710 in FIG. 5) counts the rising or falling edges of the first oscillating signal, the second oscillating signal, and the third oscillating signal. The higher the frequency of the oscillating signal, the higher the count value of the oscillating signal.

[0112] In one embodiment, the counter counts the first oscillating signal to generate a first count value, counts the second oscillating signal to generate a second count value, and counts the third oscillating signal to generate a third count value. The process corner determiner 730b compares the first count value, the second count value, and the third count value to compare the frequency of the first oscillating signal, the frequency of the second oscillating signal, and the frequency of the third oscillating signal.

[0113] In one embodiment, the process corner determiner 730b determines the process corner as a fourth type when the frequency of the first oscillation signal is greater than the frequency of the second oscillation signal (e.g., when the count value CNTV1 is greater than the count value CNTV2), and the control signal generator (e.g., 750 in FIG. 5 ) reduces the duty cycle of the internal clock based on the process corner being determined as the fourth type.

[0114] In one embodiment, the process corner determiner 730b determines the process corner as a fifth type when the frequency of the first oscillation signal is equal to or less than the frequency of the second oscillation signal and the frequency of the third oscillation signal is greater than the frequency of the second oscillation signal (e.g., when the count value CNTV1 is equal to or less than the count value CNTV2 and the count value CNTV3 is greater than the count value CNTV2), and the control signal generator increases the duty ratio of the internal clock based on the process corner being determined as the fifth type.

[0115] In one embodiment, the process corner determiner 730b determines the process corner as a sixth type when the frequency of the first oscillation signal is equal to or less than the frequency of the second oscillation signal and the frequency of the third oscillation signal is equal to or less than the frequency of the second oscillation signal (for example, when the count value CNTV1 is equal to or less than the count value CNTV2 and the count value CNTV3 is equal to or less than the count value CNTV2), and the control signal generator maintains the duty ratio of the internal clock based on the process corner being determined as the sixth type.

[0116] FIG. 15 is a flow chart illustrating a drive signal calibration method according to one embodiment of the present invention.

[0117] Referring to FIG. 15, in the driving signal calibration method, a plurality of oscillation signals are output (step S1000).

[0118] In one embodiment, step S1000 is performed by an oscillator circuit (e.g., 110 in FIG. 1, 500 in FIG. 4A). For example, the oscillator circuit includes a plurality of oscillators, each of which includes an inverter. The switching characteristics of each of the inverters included in one of the plurality of oscillators are different from the switching characteristics of each of the inverters included in another of the plurality of oscillators. For example, each of the plurality of oscillators is implemented as a "ring oscillator", where each of the inverters included in one ring oscillator has the same switching characteristics, and the inverters included in one ring oscillator and the inverters included in the other ring oscillator have different switching characteristics from each other.

[0119] A process corner of the semiconductor device is detected based on the plurality of oscillation signals (step S1300).

[0120] In one embodiment, step S1300 is performed by a control circuit (700 in FIG. 5) or a process corner detector (e.g., 730 in FIG. 5, 730a in FIG. 6, 730b in FIG. 11). The process corner is an index for classifying a process distribution, which indicates a process deviation of a semiconductor device due to a manufacturing process of the semiconductor device, according to a certain criterion to identify a process characteristic.

[0121] In one embodiment, the process corner is detected by performing one or more operations including a comparison operation based on the plurality of oscillation signals, for example, the comparison operation includes steps S510 and S530 of FIG. 7 and steps S510-1 and S530-1 of FIG.

[0122] One or more driving signals of the semiconductor device are calibrated based on the process corner (step S1500).

[0123] In one embodiment, the number of ring oscillators included in the oscillation circuit is determined according to the type of the driving signal, for example, if the driving signal is an internal voltage, the number of ring oscillators is two or more, and if the driving signal is an internal clock, the number of ring oscillators is three or more.

[0124] In one embodiment, in the process of detecting the process corner, more than one reference value may or may not be utilized depending on the type of the drive signal: if the drive signal is an internal voltage, more than one reference value is utilized, and if the drive signal is an internal clock, more than one reference value is not utilized.

[0125] FIG. 16 is a flowchart showing an example of the process of detecting the process corner of FIG.

[0126] 15 and 16, in the process of detecting a process corner, a plurality of oscillation signals are counted to generate a plurality of count values ​​(step S1310).

[0127] A process corner is determined based on the multiple count values ​​(step S1330).

[0128] FIG. 17 is a flowchart showing an example of a process for determining the process corner of FIG.

[0129] 16 and 17, in the process of determining the process corner, a plurality of count values ​​are averaged to calculate an average count value (step S1331-1).

[0130] A process corner is identified based on the average count value and two or more criteria for distinguishing types of process corners (step S1333-1).

[0131] In one embodiment, steps S1331-1 and S1333-1 correspond to the embodiment described above with reference to FIGS.

[0132] FIG. 18 is a flowchart showing another example of the process of determining the process corner of FIG.

[0133] 15, 16 and 18, in the step of outputting a plurality of oscillation signals, a first oscillation signal, a second oscillation signal and a third oscillation signal are output (step S1001-3).

[0134] In the process of determining the process corner, the first oscillation signal, the second oscillation signal, and the third oscillation signal are compared (step S1331-3).

[0135] In one embodiment, the frequency of the first oscillating signal, the frequency of the second oscillating signal, and the frequency of the third oscillating signal are compared.

[0136] In the process of determining the process corner, the frequency of the first oscillation signal, the frequency of the second oscillation signal, and the frequency of the third oscillation signal are compared to identify the process corner (step S1333-3).

[0137] In one embodiment, steps S1000-3, S1331-3 and S1333-3 correspond to the embodiment described above with reference to FIGS. 5 and 11 to 14.

[0138] FIG. 19 is a flow chart illustrating a drive signal calibration method according to one embodiment of the present invention.

[0139] 7 and 19, the control circuit receives a plurality of oscillation signals (OS1, OS2) (step S100).

[0140] The counter counts the oscillation signals (OS1, OS2) to generate a number of count values ​​(CNTV1, CNTV2) (step S200).

[0141] The process corner determiner averages the multiple count values ​​(CNTV1, CNTV2) to generate an average count value AVG_CNTV (step S300).

[0142] The process corner determiner compares the average count value AVG_CNTV with the reference values ​​(REF1, REF2) (step S500) and determines the type of the process corner PRC (step S700).

[0143] In one embodiment, the types of process corner PRC include the first type, the second type, and the third type described above with reference to FIG. 7 etc. The first type or the third type corresponds to a case where the speed of the transistor of the semiconductor device is manufactured to be slower or faster than a predetermined speed range with respect to the performance condition according to the hardware specification of the semiconductor device. The second type corresponds to a case where the speed of the transistor of the semiconductor device is manufactured to satisfy a predetermined speed range with respect to the performance condition according to the hardware specification of the semiconductor device.

[0144] The process corner determiner calibrates (or adjusts) the voltage level IVL of the internal voltage based on the process corner PRC (step S900).

[0145] In one embodiment, the process corner determiner increases or decreases a voltage level of the internal voltage IV when the process corner PRC corresponds to the first type or the third type, and maintains a voltage level of the internal voltage IV when the process corner PRC corresponds to the second type.

[0146] The process corner determiner determines whether the process corner PRC corresponds to a second type (step S910).

[0147] If the process corner PRC does not correspond to the second type (step S910: NO), the control signal generator provides the increased or decreased internal voltage IV as a feedback signal (e.g., FDS in FIG. 1) to the oscillation circuit (step S930). For example, the increased or decreased internal voltage IV is provided as a power supply voltage (e.g., VDD in FIG. 4A) of the oscillation circuit.

[0148] In one embodiment, the oscillator circuit re-outputs multiple oscillation signals (OS1, OS2), and the control circuit re-determines the process corner PRC of the semiconductor device based on the re-output multiple oscillation signals to generate a control signal (e.g., CTLD in Figures 1 and 5, etc.).

[0149] In one embodiment, step S930 is repeatedly performed until the process corner PRC falls into the second type.

[0150] If the process corner PRC corresponds to the second type (step S 910: YES), the control signal generator outputs the internal voltage IV to the semiconductor device.

[0151] FIG. 20 is a block diagram illustrating an electronic system including a drive signal supply device according to one embodiment of the present invention.

[0152] 20, the electronic system 1500 includes a processor 1510, a memory device 1520, a storage device 1530, an image sensor 1540, an input / output device 1550, and a drive signal supply device 1560. Although not shown in FIG. 20, the electronic system 1500 further includes a port capable of communicating with a video card, a sound card, a memory card, a USB device, or the like, or communicating with other electronic devices.

[0153] The processor 1510 performs specific calculations or tasks. In one embodiment, the processor 1510 is a micro-processor, a central processing unit (CPU).

[0154] The processor 1510 communicates with a memory device 1520, a storage device 1530, an image sensor 1540, and an input / output device 1550 via an address bus, a control bus, and a data bus.

[0155] In one embodiment, the processor 1510 is also connected to an expansion bus, such as a Peripheral Component Interconnect (PCI) bus.

[0156] Memory device 1520 stores data necessary for the operation of electronic system 1500. For example, memory device 1520 may be implemented as DRAM, Mobile DRAM, SRAM, PRAM, FeRAM, RRAM, and / or MRAM.

[0157] The storage device 1530 may include a solid state drive, a hard disk drive, a CD-ROM, or the like.

[0158] The input / output devices 1550 include input devices such as a keyboard, keypad, mouse, etc., and output devices such as a printer, display, etc.

[0159] The drive signal supplying device 1560 supplies drive signals necessary for the operation of the electronic system 1500. For example, the drive signal supplying device 1560 generates one or more drive signals and supplies them to the components (1510, 1520, 1530, 1540, 1550) of the electronic system 1500. For example, the one or more drive signals include an internal voltage or an internal clock, and the drive signal supplying device 1560 corresponds to a drive signal supplying device according to an embodiment of the present invention.

[0160] The image sensor 1540 is communicatively coupled to the processor 1510 via a bus or other communication link.

[0161] As described above, the driving signal supplying device according to the embodiment of the present invention can detect a process corner as a process characteristic of a semiconductor device by using a plurality of oscillators that output a plurality of oscillation signals having different oscillation periods or different oscillation frequencies. The driving signal supplying device can generate and calibrate one or more driving signals to be supplied to each component included in the semiconductor device based on the process corner.

[0162] The drive signal supplying device can supply one or more drive signals that satisfy the performance conditions set by the hardware specifications to the semiconductor device, regardless of changes in PVT (process, voltage and temperature), etc., and can prevent deterioration of the performance of the semiconductor device.

[0163] Although the embodiments of the present invention have been described in detail above with reference to the drawings, the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the technical spirit of the present invention. [Explanation of symbols]

[0164] 10 Wafers 30 Chip 31 51, 55 PMOS transistors 53, 57 NMOS transistors 100, 100a, 1560 Drive signal supply device (DSSD) 110, 500 Oscillator circuit (OSC) 111-1, 111-n oscillators 113-1, 113-n inverter 130, 700 Control circuit 150, 900a, 900b Drive signal generating circuit 300, 300a Semiconductor device 510 Ring Oscillator (RO1) 530 Ring Oscillator (ROn) 710 Counter 730, 730a, 730b Process corner determiner 731 Reference Value Information (REFI) 731a Average Value Calculator 731b, 733a, 733b, 735a comparator 750 Control Signal Generator 910a, 910b Controller 930a Internal Voltage Generator 930b Internal Clock Generator 1500 Electronic Systems 1510 Processor 1520 Memory Device 1530 Storage device 1540 Image Sensor 1550 I / O device AVG_CNTV Average count value CNTV1~CNTVn, CNTVs count value CR1, CR2, CR3, CR4 comparison results CTLD Control Signal DSs drive signal DTR Duty ratio f1~fn Oscillation frequency FDS Feedback Signal IC internal clock IV Internal voltage IVL Voltage Level OS1 to OSn, OSs oscillation signal PRC Process Corner PRCI Process Corner Information REF1, REF2 reference values FF, FS, FT, SF, SS, ST, TF, TS, TT process corner VDD Power supply voltage Wn1~Wnn, Wp1~Wpn channel width

Claims

1. An oscillation circuit including a plurality of oscillators each having an inverter and outputting a plurality of oscillation signals; a control circuit for detecting a process corner of the semiconductor device based on the plurality of oscillation signals and generating a control signal; a drive signal generating circuit that generates one or more drive signals for the semiconductor device based on the control signal; A drive signal supplying device, wherein the switching characteristics of each of the inverters included in one of the plurality of oscillators are different from the switching characteristics of each of the inverters included in the other of the plurality of oscillators.

2. The control circuit includes: a counter that counts the plurality of oscillation signals to generate a plurality of count values; a process corner determiner for determining the process corner based on the plurality of count values; 2. The drive signal supplying device according to claim 1, further comprising: a control signal generator that generates the control signal based on the process corner.

3. the one or more drive signals for the semiconductor device include an internal voltage provided to the semiconductor device; 3. The driving signal supplying device of claim 2, wherein the process corner determiner determines the process corner based on two or more reference values ​​for classifying the types of the process corner and the plurality of count values.

4. The process corner determiner comprises: averaging the plurality of count values ​​to calculate an average count value; 4. The drive signal supplying device according to claim 3, wherein the process corner is determined by comparing the average count value with the two or more reference values.

5. The two or more reference values ​​include a first reference value and a second reference value, the process corner determiner determines the process corner as a first type if the average count value is less than the first reference value; 5. The driving signal supplying device of claim 4, wherein the control signal generator increases a voltage level of the internal voltage based on the process corner being determined to be the first type.

6. the control signal generator increases a voltage level of the internal voltage and then supplies the increased internal voltage to the oscillation circuit; The oscillation circuit re-outputs the plurality of oscillation signals; 6. The drive signal supply device according to claim 5, wherein the control circuit re-determines the process corner of the semiconductor device based on the re-outputted oscillation signals, and generates the control signal.

7. the process corner determiner determines the process corner as a second type when the average count value is greater than or equal to the first reference value and less than the second reference value; 6. The driving signal supply device of claim 5, wherein the control signal generator maintains a voltage level of the internal voltage based on the process corner being determined to be the second type.

8. the one or more drive signals of the semiconductor device include an internal clock provided to the semiconductor device; 3. The drive signal supplying device of claim 2, wherein the process corner determiner compares the plurality of count values ​​with each other to determine the process corner.

9. The plurality of oscillators include a first oscillator that outputs a first oscillation signal; a second oscillator that outputs a second oscillation signal; a third oscillator that outputs a third oscillation signal; each of the inverters in the first oscillator has a first ratio of channel widths; each of the inverters in the second oscillator has a second ratio of channel widths; each of the inverters in the third oscillator has a third ratio of channel widths; the second ratio of channel widths is greater than the first ratio of channel widths; the third ratio of channel widths is greater than the first ratio of channel widths; 9. The drive signal supplying device of claim 8, wherein the process corner determiner determines the process corner by comparing a frequency of the first oscillator signal, a frequency of the second oscillator signal, and a frequency of the third oscillator signal.

10. the counter counts the first oscillation signal to generate a first count value, counts the second oscillation signal to generate a second count value, and counts the third oscillation signal to generate a third count value; 10. The driving signal supplying device of claim 9, wherein the process corner determiner compares the first count value with the second count value, and compares the frequency of the first oscillation signal with the frequency of the second oscillation signal.

11. the process corner determiner determines the process corner as a first type if a frequency of the first oscillating signal is greater than a frequency of the second oscillating signal; 11. The drive signal supply device of claim 10, wherein the control signal generator reduces a duty ratio of the internal clock based on the process corner being determined to be the first type.

12. 12. The driving signal supplying device of claim 11, wherein the process corner determiner determines the process corner as the first type when the first count value is greater than the second count value.

13. the process corner determiner determines the process corner as a second type if a frequency of the third oscillator signal is greater than a frequency of the second oscillator signal; 10. The drive signal supply device of claim 9, wherein the control signal generator increases a duty ratio of the internal clock based on the process corner being determined to be the second type.

14. the process corner determiner determines the process corner as a third type when a frequency of the first oscillator signal is equal to or less than a frequency of the second oscillator signal and when a frequency of the third oscillator signal is equal to or less than a frequency of the second oscillator signal; 10. The driving signal supply device of claim 9, wherein the control signal generator maintains a duty ratio of the internal clock based on the process corner being determined to be the third type.

15. each of the inverters included in each of the plurality of oscillators includes a PMOS transistor and an NMOS transistor; each of the inverters included in each of the plurality of oscillators has a channel width ratio that is a ratio of a channel width of the PMOS transistor to a channel width of the NMOS transistor; 2. The drive signal supply device according to claim 1 , wherein the channel width ratio of each of the inverters included in one of the plurality of oscillators is different from the channel width ratio of each of the inverters included in the other of the plurality of oscillators.

16. outputting a plurality of oscillation signals by an oscillation circuit including a plurality of oscillators, each of which includes an inverter; detecting a process corner of a semiconductor device based on the plurality of oscillation signals; calibrating one or more drive signals of the semiconductor device based on the process corner; A drive signal calibration method, characterized in that the switching characteristics of each of the inverters included in one of the plurality of oscillators are different from the switching characteristics of each of the inverters included in the other one of the plurality of oscillators.

17. The step of detecting a process corner comprises: counting the plurality of oscillation signals to generate a plurality of count values; 17. The method of claim 16, further comprising: determining the process corner based on the plurality of count values.

18. The step of determining a process corner comprises: averaging the plurality of count values ​​to calculate an average count value; and identifying the process corner based on the average count value and two or more reference values ​​for classifying the types of the process corners.

19. the step of outputting a plurality of oscillating signals includes the step of outputting a first oscillating signal, a second oscillating signal, and a third oscillating signal; 20. The method of claim 17, wherein determining the process corner comprises comparing a frequency of the first oscillator signal, a frequency of the second oscillator signal, and a frequency of the third oscillator signal to identify the process corner.

20. An oscillation circuit including a plurality of oscillators each having an inverter and outputting a plurality of oscillation signals; a control circuit that performs one or more operations, including a comparison operation, based on the plurality of oscillation signals to generate a control signal; a drive signal generating circuit that generates one or more drive signals for the semiconductor device based on the control signal; A drive signal supplying device, wherein the switching characteristics of each of the inverters included in one of the plurality of oscillators are different from the switching characteristics of each of the inverters included in the other of the plurality of oscillators.

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