Printed circuit board

Abstract

To provide a printed circuit board capable of improving matching when an interconnect bridge is built in.SOLUTION: A printed circuit board includes an interconnect bridge including an insulating material, a plurality of conductive pattern layers each disposed on or within the insulating material, and a conductive post disposed on the insulating material, a first insulating layer having a recessed portion in which the interconnect bridge is embedded and which exposes a portion of the conductive post, and a first wiring layer disposed on the first insulating layer and including a first pad pattern connected to the exposed portion of the conductive post on the recessed portion.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present invention relates to printed circuit boards. [Background technology]

[0002] As the number of cores in server products' CPUs and GPUs increases rapidly, die-splitting technology, which can effectively increase the number of cores, is becoming common. In addition, as the demand for packages including HBM (High Bandwidth Memory) increases, technology that connects die to die with fine circuit line width is required. To meet these technical demands, technologies using silicon interposers have been developed, but there are limitations to commercialization due to price issues and complex assembly processes. In addition, technologies that embed silicon bridges into substrates have been developed, but there are limitations to achieving high consistency when embedding the bridge due to bridge position deviation, via processing deviation, and pad exposure deviation. Summary of the Invention [Problem to be solved by the invention]

[0003] SUMMARY OF THE PRESENT EMBODIMENT One of the various objects of the present invention is to provide a printed circuit board that can improve matching when incorporating an interconnect bridge.

[0004] Another of the various objects of the present invention is to provide a printed circuit board that can be manufactured using a process that is less sensitive to thickness variations in the interconnect bridges. [Means for solving the problem]

[0005] One of several solutions proposed through the present invention is to erect a conductive post on an interconnect bridge, cover it with an insulating layer, and then form a recess by skiving or the like on the insulating layer so that a portion of the conductive post is exposed, and then form a conductive pad on the recess to be connected to the conductive post.

[0006] For example, one example of a printed circuit board may include an insulating material, a plurality of conductive pattern layers each disposed on or within the insulating material, an interconnect bridge including a conductive post disposed on the insulating material, a first insulating layer having a recessed portion that embeds the interconnect bridge and exposes a portion of the conductive post, and a first wiring layer disposed on the first insulating layer and including a first pad pattern connected to the exposed portion of the conductive post on the recessed portion.

[0007] For example, a printed circuit board according to one example includes a first substrate portion including a plurality of first insulating layers, a plurality of first wiring layers respectively disposed on or within the plurality of first insulating layers, and a plurality of first via layers each penetrating at least one of the plurality of first insulating layers; and a second substrate portion including a plurality of second insulating layers, a plurality of second wiring layers respectively disposed on or within the plurality of second insulating layers, a plurality of second via layers each penetrating at least one of the plurality of second insulating layers, and a plurality of conductive posts each disposed on a second insulating layer disposed on the uppermost side of the plurality of second insulating layers, wherein the second substrate portion is disposed within the first substrate portion, at least one of the plurality of second wiring layers has an average pitch smaller than that of at least one of the plurality of first wiring layers, and at least one of the plurality of first insulating layers has a step region exposing a portion of each of the plurality of conductive posts. Effect of the Invention

[0008] Among the various advantages of the present invention, one advantage is that it provides a printed circuit board that can improve the matching when incorporating an interconnect bridge.

[0009] Another advantage of the present invention is that it provides a printed circuit board that can be manufactured using a process that has little effect on thickness variations of the interconnect bridges. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a block diagram illustrating a schematic example of an electronic device system. [Diagram 2] FIG. 1 is a perspective view illustrating an example of an electronic device. [Diagram 3] 1 is a cross-sectional view showing a schematic diagram of a BGA package mounted on a main board of an electronic device. [Figure 4] 1 is a cross-sectional view illustrating a silicon interposer package mounted on a main board. [Diagram 5] 1 is a cross-sectional view illustrating a schematic configuration of an organic interposer package mounted on a main board. [Figure 6] FIG. 1 is a cross-sectional view illustrating an example of a printed circuit board. [Figure 7] FIG. 2 is a cross-sectional view illustrating an example of an interconnect bridge. [Figure 8a] FIG. 7 is an enlarged cross-sectional view illustrating an example of a region A in FIG. 6. [Figure 8b] 7 is an enlarged cross-sectional view illustrating another example of the region A in FIG. 6. [Figure 9a] 1A to 1C are process diagrams illustrating an example of a method for manufacturing a printed circuit board. [Figure 9b] 1A to 1C are process diagrams illustrating an example of a method for manufacturing a printed circuit board. [Figure 9c] 1A to 1C are process diagrams illustrating an example of a method for manufacturing a printed circuit board. [Figure 9d] 1A to 1C are process diagrams illustrating an example of a method for manufacturing a printed circuit board. [Figure 9e] 1A to 1C are process diagrams illustrating an example of a method for manufacturing a printed circuit board. [Figure 9f] 1A to 1C are process diagrams illustrating an example of a method for manufacturing a printed circuit board. [Figure 9g] 1A to 1C are process diagrams illustrating an example of a method for manufacturing a printed circuit board. [Figure 9h] 1A to 1C are process diagrams illustrating an example of a method for manufacturing a printed circuit board. [Figure 10]FIG. 11 is a cross-sectional view illustrating a modified example of a printed circuit board. [Figure 11] FIG. 11 is a cross-sectional view illustrating another example of a printed circuit board. [Figure 12] FIG. 13 is a cross-sectional view illustrating another example of an interconnect bridge. [Figure 13] FIG. 11 is a cross-sectional view illustrating another example of a printed circuit board. [Figure 14] FIG. 13 is a cross-sectional view illustrating another example of an interconnect bridge. [Figure 15] FIG. 11 is a cross-sectional view illustrating another example of a printed circuit board. [Figure 16] FIG. 13 is a cross-sectional view illustrating another example of an interconnect bridge. [Figure 17] FIG. 11 is a cross-sectional view illustrating another example of a printed circuit board. [Figure 18] FIG. 13 is a cross-sectional view illustrating another example of an interconnect bridge. [Figure 19] FIG. 11 is a cross-sectional view illustrating another example of a printed circuit board. [Figure 20] FIG. 13 is a cross-sectional view illustrating another example of an interconnect bridge. [Figure 21] FIG. 11 is a cross-sectional view illustrating another example of a printed circuit board. [Figure 22] FIG. 13 is a cross-sectional view illustrating another example of an interconnect bridge. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] The present invention will now be described with reference to the accompanying drawings, in which the shapes and sizes of elements may be exaggerated or reduced for clarity.

[0012] electronic equipment FIG. 1 is a block diagram illustrating an example of an electronic device system.

[0013] Referring to the drawing, an electronic device 1000 accommodates a main board 1010. Chip-related components 1020, network-related components 1030, and other components 1040 are physically and / or electrically connected to the main board 1010. These are also connected to other electronic components described below to form various signal lines 1090.

[0014] The chip-related components 1020 include, but are not limited to, memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as central processors (e.g., CPU), graphic processors (e.g., GPU), digital signal processors, encryption processors, microprocessors, and microcontrollers; and logic chips such as analog-to-digital converters and ASICs (application-specific ICs). Needless to say, the chip-related components 1020 may include other types of chip-related electronic components. Needless to say, these chip-related components 1020 may be combined with each other. The chip-related components 1020 may be in the form of a package including the above-mentioned chips and electronic components.

[0015] The network-related components 1030 may include, but are not limited to, any other wireless and wired protocols designated as Wi-Fi (e.g., IEEE 802.11 family), WiMAX (e.g., IEEE 802.16 family), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G, and beyond, as well as any of a number of other different wireless or wired standards and protocols. It should be understood that the network-related components 1030 may also be combined with the chip-related components 1020 and with each other.

[0016] The other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCC (low temperature co-firing ceramics), EMI (electromagnetic interference) filters, MLCC (multi-layer ceramic capacitors), etc. However, the other components 1040 are not limited to these, and may also include passive elements in the form of chip components used for various other different applications. It goes without saying that the other components 1040 may be combined with the chip-related components 1020 and / or the network-related components 1030.

[0017] Depending on the type of electronic device 1000, the electronic device 1000 may include other electronic components that may or may not be physically and / or electrically coupled to the main board 1010. Examples of other electronic components include, but are not limited to, a camera module 1050, an antenna module 1060, a display 1070, and a battery 1080. The other electronic components may include, but are not limited to, an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (e.g., a hard disk drive), a compact disk (CD), a digital versatile disk (DVD), and the like. Needless to say, other electronic components used for various purposes may be included depending on the type of electronic device 1000.

[0018] The electronic device 1000 may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, etc. However, the electronic device 1000 is not limited to these, and may be any other electronic device that processes data.

[0019] FIG. 2 is a perspective view that illustrates an example of an electronic device.

[0020] Referring to the drawings, the electronic device may be, for example, a smartphone 1100. A motherboard 1110 is housed inside the smartphone 1100, and various components 1120 are physically and / or electrically connected to the motherboard 1110. In addition, other components such as a camera module 1130 and / or a speaker 1140 that may or may not be physically and / or electrically connected to the motherboard 1110 are housed inside the smartphone 1100. Some of the components 1120 may be the above-mentioned chip-related components, for example, a component package 1121, but are not limited thereto. The component package 1121 may be in the form of a printed circuit board on which electronic components including active components and / or passive components are surface-mounted. Alternatively, the component package 1121 may be in the form of a printed circuit board in which active components and / or passive components are built-in. Meanwhile, it goes without saying that the electronic device is not necessarily limited to the smartphone 1100, and may be other electronic devices as described above.

[0021] Semiconductor package including interposer Generally, a semiconductor chip has many fine electric circuits integrated, but it cannot function as a finished semiconductor product by itself and can be damaged by external physical or chemical shocks. Therefore, the semiconductor chip is not used as it is, but is packaged and used in electronic devices in the packaged state.

[0022] The reason why semiconductor packaging is necessary is that there is a difference in the width of the circuit between a semiconductor chip and a main board of an electronic device from the viewpoint of electrical connection. Specifically, in the case of a semiconductor chip, the size of the connection pads and the interval between the connection pads are very fine, whereas in the case of a main board used in an electronic device, the size of the component mounting pads and the interval between the component mounting pads are much larger than the scale of the semiconductor chip. Therefore, it is difficult to directly mount a semiconductor chip on such a main board, and a packaging technology that can reduce the difference in circuit width between them is required.

[0023] A semiconductor package including an interposer manufactured by such packaging technology will be described in more detail below with reference to the drawings.

[0024] FIG. 3 is a cross-sectional view that illustrates a schematic diagram of a BGA package mounted on a main board of an electronic device.

[0025] Among semiconductor chips, application specific integrated circuits (ASICs) such as graphics processing units (GPUs) are very expensive, so it is very important to package them with a high yield. For this purpose, a ball grid array (BGA) substrate 2210 capable of rewiring thousands to hundreds of thousands of connection pads is first prepared before mounting a semiconductor chip, and then an expensive semiconductor chip such as a GPU 2220 is mounted and packaged on the BGA substrate 2210 using a surface mounting technology (SMT), and then finally mounted on the main board 2110. Meanwhile, the BGA substrate 2210 may include a flip chip BGA (FCBGA) substrate.

[0026] Meanwhile, in the case of the GPU2220, it is necessary to minimize the signal path with a memory such as a High Bandwidth Memory (HBM), and for this purpose, a method is used in which a semiconductor chip such as an HBM2240 is mounted on an interposer 2230, packaged, and stacked in a package on which the GPU2220 is mounted in a package on package (POP) form for use. However, in this case, there is a problem that the thickness of the device becomes excessively thick, and there is a limit to minimizing the signal path.

[0027] FIG. 4 is a cross-sectional view that illustrates a schematic diagram of a silicon interposer package mounted on a main board.

[0028] As a solution to the above-mentioned problems, a method of manufacturing a semiconductor package 2310 including a silicon interposer can be considered as an interposer technology in which a first semiconductor chip such as a GPU 2220 and a second semiconductor chip such as an HBM 2240 are surface-mounted side-by-side on a silicon interposer 2250 and then packaged. In this case, it is possible to rewire the GPU 2220 and the HBM 2240 having thousands to hundreds of thousands of connection pads through the silicon interposer 2250, and to electrically connect them with a minimum number of paths. In addition, the semiconductor package 2310 including such a silicon interposer can be mounted again on a BGA substrate 2210 and rewired, and finally mounted on a main board 2110.

[0029] However, in the case of the silicon interposer 2250, not only is it very difficult to form through silicon vias (TSVs) and the like, but the manufacturing costs are also considerable, making it disadvantageous in terms of increasing the area and reducing costs.

[0030] FIG. 5 is a cross-sectional view that illustrates a schematic diagram of an organic interposer package mounted on a main board.

[0031] As a solution to the above-mentioned problems, a method of using an organic interposer 2260 instead of the silicon interposer 2250 can be considered. For example, a method of manufacturing a semiconductor package 2320 including an organic interposer can be considered as an interposer technology in which a first semiconductor chip such as a GPU 2220 and a second semiconductor chip such as an HBM 2240 are arranged on the organic interposer 2260 and surface-mounted, and then packaged. In this case, it is possible to rewire the GPU 2220 and the HBM 2240 having thousands to hundreds of thousands of connection pads through the organic interposer 2260, and to electrically connect them with a minimum number of paths. In addition, by mounting the semiconductor package 2310 including such an organic interposer on a BGA substrate 2210 and rewiring it again, it can finally be mounted on the main board 2110. In addition, it is advantageous for increasing the area and reducing the cost.

[0032] However, even when using the organic interposer 2260, the semiconductor chips 2220, 2240 must be mounted on the organic interposer 2260 and then mounted again on the BGA substrate 2210, which may make the process somewhat more complicated and may result in a reduced packaging yield.

[0033] Printed circuit board with built-in bridge FIG. 6 is a cross-sectional view that shows a schematic example of a printed circuit board, and FIG. 7 is a cross-sectional view that shows a schematic example of an interconnect bridge.

[0034] Referring to the drawing, a printed circuit board 100A according to an example may include an insulating material 151, a plurality of conductive pattern layers 152 disposed in the insulating material 151, an interconnect bridge 150A including conductive posts 154 disposed on the insulating material 151, a first insulating layer 111 having a recessed portion R in which the interconnect bridge 150A is embedded and a portion of the conductive post 154 is exposed, and a first wiring layer 121 disposed on the first insulating layer 111 and including a first pad pattern P1 connected to an exposed portion of the conductive post 154 on the recessed portion R. Here, the exposure of the conductive post 154 may be determined based on the first insulating layer 111. For example, it may mean that the conductive post 154 is exposed from the first insulating layer 111. If necessary, the first wiring layer 121 may further include a second pad pattern P2 disposed in another region other than the recessed portion R and spaced apart from the conductive post.

[0035] In this manner, in the printed circuit board 100A according to an embodiment, the interconnect bridge 150A may include the conductive post 154, which is narrower and taller than a general pad, and the first pad pattern P1 connected thereto may be wider, so that sufficient exposure tolerance and / or alignment tolerance can be ensured. In addition, since the conductive post 154 can be directly connected to the first pad pattern P1 without via processing after the interconnect bridge 150A is embedded, it may be more advantageous in improving the degree of alignment. In addition, since a part of the conductive post 154 can be exposed through the recess portion R, the above-mentioned structure and the effects thereof can be more easily realized, and the thickness change of the first insulating layer 111 and / or the interconnect bridge 150A is less likely to be affected. As a result, the process window of the process may be wider, which may be advantageous for mass production. In addition, the difficulty of the manufacturing process may be reduced.

[0036] If necessary, the printed circuit board 100A according to an example may further include a second wiring layer 122 arranged in the first insulating layer 111, a first via layer 131 penetrating the first insulating layer 111 and connecting the first and second wiring layers 121, 122, a second insulating layer 112 arranged below the first insulating layer 111, a third wiring layer 123 arranged in the second insulating layer 112, a second via layer 132 penetrating the second insulating layer 112 and connecting the second and third wiring layers 122, 123, a third insulating layer 113 arranged on the first insulating layer 111 and covering the first wiring layer 121, a fourth wiring layer 124 arranged on the third insulating layer 113, and a third via layer 133 penetrating the third insulating layer 113 and connecting the first and fourth wiring layers 121, 124.

[0037] In this way, the printed circuit board 100A may have an ETS (Embedded Trace Substrate) structure. However, the present invention is not limited to this, and the printed circuit board 100A may be a core-type board including a core insulating layer. For example, the part shown in the figure may represent a part of the built-up upper side of a core-type board. The printed circuit board 100A may be a BGA board or an FCBGA board, but is not limited to this.

[0038] Meanwhile, the recessed portion R may have a tapered shape such that the width of the upper end is larger than the width of the lower end in a cross section. The upper surface of the first insulating layer 111 may have a step due to the recessed portion R. For example, the first insulating layer 111 may have a step region due to the recessed portion R. Since the first pad pattern P1 may be disposed in the step region and the second pad pattern P2 may be disposed outside the step region, the upper surface and the lower surface of each of the first and second pad patterns P1 and P2 may have a step from each other. Meanwhile, the step of the first insulating layer 111 due to the recessed portion R may be restored by the third insulating layer 113. For example, the upper surface of the third insulating layer 113 may be substantially flat.

[0039] The components of the example printed circuit board 100A are described in more detail below with reference to the drawings.

[0040] The first to third insulating layers 111, 112, and 113 may each include an insulating material. The insulating material may be, but is not limited to, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material in which these resins are mixed with an inorganic filler such as silica, or a resin impregnated in a core material such as glass fiber (glass fiber, glass cloth, glass fabric) together with an inorganic filler, for example, an organic insulating material such as ABF (Ajinomoto Build-up Film) or prepreg. As a non-limiting example, the first to third insulating layers 111, 112, and 113 may include substantially the same material as each other, but is not limited to this. Here, substantially the same material may be a case in which insulating materials with the same trade name are used. A solder resist may be used as the material of the third insulating layer 113. For example, the third insulating layer 113 may be a solder resist layer.

[0041] Each of the first to fourth wiring layers 121, 122, 123, and 124 can include a metal material. As the metal material, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof can be used. Each of the first to fourth wiring layers 121, 122, 123, and 124 can include an electroless plating layer (or chemical copper) and / or an electrolytic plating layer (or electrolytic copper). If necessary, a sputtering layer can be included. If necessary, a copper foil can be included. Each of the first to fourth wiring layers 121, 122, 123, and 124 can perform various functions according to the design of the layer. For example, a ground pattern, a power pattern, a signal pattern, etc. can be included. Here, the signal pattern can include various signals other than the ground pattern, the power pattern, etc., such as a data signal. These patterns may include a line pattern, a plane pattern, and / or a pad pattern. For example, the first wiring layer 121 may include first and second pad patterns P1 and P2.

[0042] Each of the first to third via layers 131, 132, and 133 may contain a metal material. The metal material may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. Each of the first to third via layers 131, 132, and 133 may contain an electroless plating layer (or chemical copper) and / or an electrolytic plating layer (or electrolytic copper). If necessary, a sputtering layer may be included. Each of the first to third via layers 131, 132, and 133 may be a filled type in which a via hole is filled with a metal material, but is not limited thereto, and may be a conformal type in which a metal material is disposed along the wall surface of the via hole. Each of the first to third via layers 131, 132, and 133 may have a tapered shape in which the width of the upper end is wider than the width of the lower end on the cross section. The first to third via layers 131, 132, and 133 can perform various functions according to the design of the respective layers. For example, they can include ground vias, power vias, and signal vias. Here, the signal vias can include vias for transmitting various signals, such as data signals, other than ground vias and power vias. The first to third via layers 131, 132, and 133 can include stacked vias and / or staggered vias according to the form of upper and lower connections.

[0043] The interconnect bridge 150A may be a silicon bridge manufactured by forming wiring by a deposition process or the like using silicon dioxide or the like as an insulating body, or an organic bridge manufactured by forming wiring by a plating process or the like using an organic insulating material as an insulating body. Preferably, the interconnect bridge 150A may be an organic bridge, in which case reliability problems due to CTE mismatch may hardly occur. Furthermore, the difficulty and cost of the process for manufacturing the interconnect bridge 150A may be reduced. In addition, the interconnect bridge 150A may have an ETS structure, for example, a coreless substrate structure. In this way, when the interconnect bridge 150A is formed in the form of a coreless substrate, wiring design with a finer pitch may be possible. In addition, it may be manufactured at a lower cost and the process may be simpler than a silicon bridge. The organic bridge may be a high-density circuit board.

[0044] The insulating material 151 may include an insulating material. The insulating material may be an organic insulating material such as a photosensitive insulating material (PID). When a photosensitive insulating material (PID) is used as the material of the insulating material 151, the thickness of the insulating material 151 can be minimized and photo via holes can be formed, so that the multiple conductive pattern layers 152 can be designed with high density. However, the material is not limited thereto, and other organic insulating materials such as ABF may be used. If necessary, an inorganic insulating material such as silicon may be included. The insulating material 151 may be composed of multiple insulating layers, and the number of layers is not particularly limited. The multiple insulating layers may have boundaries that are separated from each other or may be unclear.

[0045] The conductive pattern layers 152 can provide a die-to-die interconnection path. The conductive pattern layers 152 can be composed of multiple layers, and the number of layers is not particularly limited. The conductive pattern layers 152 can perform various functions depending on the design of the layers, and can include at least a signal pattern. The conductive pattern layers 152 can each include a line pattern, a plane pattern, and / or a pad pattern. The conductive pattern layers 152 can each include a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The conductive pattern layers 152 can each include an electroless plating layer (or chemical copper) and / or an electrolytic plating layer (or electrolytic copper). If necessary, a sputtering layer can be included.

[0046] The multiple conductive pattern layers 152 may have a higher circuit density than the first to fourth wiring layers 121, 122, 123, and 124. That is, the multiple conductive pattern layers 152 may include higher density circuits. For example, the average pitch of the wiring included in at least one of the multiple conductive pattern layers 152 may be smaller than the average pitch of the wiring included in at least one of the first to fourth wiring layers 121, 122, 123, and 124. In addition, the average interlayer insulation distance between the multiple conductive pattern layers 152 may be smaller than the average interlayer insulation distance between the first to fourth wiring layers 121, 122, 123, and 124.

[0047] The conductive pattern layers 152 may have two high-density wiring layers and one ground layer, and the ground layer may be omitted from the line pattern for signal transmission, but is not limited thereto. The high-density wiring layer may have only one design rule, such as line / space, e.g., L / S is 2 μm / 2 μm or 1 μm / 1 μm, but is not limited thereto.

[0048] The conductive pattern layers 152 may be electrically connected to each other through the conductive via layers 153. Each of the conductive via layers 153 may include a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. Each of the conductive via layers 153 may include an electroless plating layer (or chemical copper) and / or an electrolytic plating layer (or electrolytic copper). If necessary, a sputtering layer may be included. Each of the conductive via layers 153 may be of a filled type in which a via hole is filled with a metal material, but is not limited thereto, and may be of a conformal type in which a metal material is disposed along the wall surface of a via hole. Each of the conductive via layers 153 may have a tapered shape in which the width of an upper end is wider than the width of a lower end on a cross section. Each of the conductive via layers 153 may perform various functions according to the design of the corresponding layer. For example, a ground via, a power via, a signal via, etc. may be included. Here, the signal via may include vias for transmitting various signals, for example, data signals, excluding ground vias, power vias, etc. The plurality of conductive via layers 153 may include stacked vias and / or staggered vias depending on the form of upper and lower connections.

[0049] The conductive post 154 may have a high aspect ratio. For example, the aspect ratio may be greater than 1. The conductive post 154 may perform various functions such as a signal post, a ground post, a power post, etc., and may include at least a signal post. The conductive post 154 may include a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The conductive post 154 may be formed by a plating process, and may include, but is not limited to, an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). If necessary, a sputtering layer may be included. The conductive post 154 may be connected to the conductive pattern layer 152 disposed at the uppermost side of the plurality of conductive pattern layers 152 through the conductive via layer 153 disposed at the uppermost side of the plurality of conductive via layers 153. There may be a plurality of conductive posts 154.

[0050] The interconnect bridge 150A can be attached to the top surface of the second insulating layer 112 via an adhesive 155. The adhesive 155 can include any known adhesive material, such as an epoxy-based adhesive material, but the material is not limited thereto.

[0051] FIG. 8a is an enlarged cross-sectional view that illustrates an example of region A in FIG.

[0052] Referring to the drawing, the conductive post 154 may be partially embedded in the first insulating layer 111 and partially protrude above the first insulating layer 111. For example, the upper surface of the conductive post 154 may have a step with the upper surface of the first insulating layer 111. In this case, the contact area with the first pad pattern P1 is increased, and better adhesion may be obtained. The first pad pattern P1 may be disposed on the upper surface of the first insulating layer 111 on the recessed portion R and cover the other protruding part of the conductive post 154. The first pad pattern P1 may include a first metal layer M1 that covers the upper surface of the first insulating layer 111 and the upper surface and side surface of the other protruding part of the conductive post 154 with a substantially constant thickness, and a second metal layer M2 that is disposed on the first metal layer M1 and has an average thickness greater than that of the first metal layer M1. The first metal layer M1 may be a seed layer formed by electroless plating and / or sputtering. The second metal layer M2 may be a plating layer formed by electrolytic plating.

[0053] FIG. 8b is an enlarged cross-sectional view that illustrates another example of region A in FIG.

[0054] Referring to the drawings, the conductive post 154 may be embedded in the first insulating layer 111, and the upper surface may be exposed from the upper surface of the first insulating layer 111. For example, the upper surface of the conductive post 154 may be substantially coplanar with the upper surface of the first insulating layer 111. In this case, a more flat surface may be provided. The first pad pattern P1 may be disposed on the upper surface of the first insulating layer 111 above the recess R, and may cover the exposed upper surface of the conductive post 154. The first pad pattern P1 may include a first metal layer M1 that covers the upper surface of the first insulating layer 111 and the exposed upper surface of the conductive post 154 with a substantially constant thickness, and a second metal layer M2 that is disposed on the first metal layer M1 and has an average thickness greater than that of the first metal layer M1. The first metal layer M1 may be a seed layer formed by electroless plating and / or sputtering. The second metal layer M2 may be a plating layer formed by electrolytic plating.

[0055] 9a to 9h are process diagrams that outline an example of the manufacture of a printed circuit board.

[0056] 9a, the second insulating layer 112, the second and third wiring layers 122, 123, and the second via layer 132 are formed by a build-up process using a carrier substrate or the like. A via hole for forming the second via layer 132 can be formed by laser processing, a mechanical drill, or the like. The second and third wiring layers 122, 123, and the second via layer 132 can be formed by a circuit formation process such as AP (Additive Process), SAP (Semi AP), MSAP (Modified SAP), or TT (Tenting). The second insulating layer 112 can be formed by a lamination process such as ABF.

[0057] 9b, the interconnect bridge 150A is attached using an adhesive 155. The interconnect bridge 150A can be manufactured by a substrate process. For example, the interconnect bridge 150A can be manufactured by forming a plurality of conductive pattern layers 152 and a plurality of conductive via layers 153 on an insulating material 151 through a build-up process using a carrier substrate, and then forming a plurality of conductive posts 154 on the insulating material 151 through a plating process using a resist. The uppermost conductive via layer 153 among the plurality of conductive via layers 153 can be formed at the same time as forming the plurality of conductive posts 154.

[0058] 9c, a first insulating layer 111 is laminated on a second insulating layer 112 to incorporate an interconnect bridge 150A. The first insulating layer 111 can be formed, for example, by a process of laminating ABF or the like on the second insulating layer 112.

[0059] 9d, a recess R exposing a portion of the conductive post 154 is formed in the first insulating layer 111. The recess R may be formed by a partial skiving process or a partial thinning process. The skiving process or thinning process may use plasma etching, wet etching, dry etching, laser processing, blasting processing, etc. The recess R may form a step region on the upper side of the first insulating layer 111.

[0060] 9e, a via hole v is formed in the first insulating layer 111. The via hole v can be formed using laser processing, a mechanical drill, or the like.

[0061] 9f, a first wiring layer 121 including first and second pad patterns P1 and P2 is formed on a first insulating layer 111. Also, a first via layer 131 is formed in a via hole v. The first wiring layer 121 and the first via layer 131 may be formed using a circuit formation process such as AP, SAP, MSAP, or TT. The first pad pattern P1 may cover the exposed conductive post 154 and may be connected thereto.

[0062] 9g, a third insulating layer 113 is laminated on the first insulating layer 111. The step can be restored through the third insulating layer 113. The third insulating layer 113 can be formed, for example, by a process of laminating ABF or SR on the first insulating layer 111. Alternatively, it can be formed by a process of applying an SR material and then curing it.

[0063] 9h, a fourth wiring layer 124 and a third via layer 133 are formed on the third insulating layer 113. A via hole for forming the third via layer 133 may be formed using laser processing, a mechanical drill, or the like. The fourth wiring layer 124 and the third via layer 133 may be formed using a circuit formation process such as AP, SAP, MSAP, or TT. Through a series of processes, the printed circuit board 100A according to the above-mentioned example may be manufactured.

[0064] FIG. 10 is a cross-sectional view that illustrates a modified example of the printed circuit board.

[0065] Referring to the drawings, the printed circuit board 500A according to the modified example may include a first substrate unit 200, a second substrate unit 150A disposed within the first substrate unit 200, and first and second semiconductor chips 310, 320 disposed on the first substrate unit 200 and connected to each other via the second substrate unit 150A. The first substrate unit 200 may be a multi-layer core substrate and may include a plurality of first insulating layers 211, 212, 213, 214, 215, a plurality of first wiring layers 221, 222, 223, and a plurality of first via layers 231, 232, 233. The second substrate unit 150A may be the above-mentioned interconnect bridge 150A and may include a plurality of second insulating layers 151, a plurality of second wiring layers 152, a plurality of second via layers 153, and a plurality of conductive posts 154. The second substrate unit 150A may be attached within the first substrate unit 200 by an adhesive 155. The printed circuit board 100A according to the above-mentioned example may be partially applied to the printed circuit board 500A according to the modified example. For example, the printed circuit board 500A according to the modified example may include the printed circuit board 100A according to the above-mentioned example as a part of a package substrate, for example, as a part of an upper build-up region in a core-type substrate, and may be in the form of a semiconductor package on which the first and second semiconductor chips 310 and 320 are mounted.

[0066] Each of the first insulating layers 211, 212, 213, 214, and 215 may include an insulating material. The insulating material may be, but is not limited to, a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a material in which these resins are mixed with an inorganic filler such as silica, or a resin impregnated in a core material such as glass fiber (glass cloth, glass fabric) together with an inorganic filler, for example, an organic insulating material such as CCL (Copper Clad Laminate), ABF (Ajinomoto Build-up Film), or prepreg. As a non-limiting example, the 1-1 insulating layer 211 may include CCL as a core layer, and the 1-2 insulating layers 212 and the 1-3 insulating layers 213 may include ABF or prepreg as build-up layers. The 1-4 insulating layer 214 and the 1-5 insulating layer 215 may include, but are not limited to, ABF or solder resist as the outermost layer. The 1-1 insulating layer 211 may include, in addition to the organic insulating material, other insulating materials such as glass plate, if necessary.

[0067] Each of the first wiring layers 221, 222, and 223 may include a metal material. The metal material may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. Each of the first wiring layers 221, 222, and 223 may include, but is not limited to, an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). As the electroless plating layer, a sputtering layer may be formed instead of chemical copper, and both may be included. If necessary, a copper foil may be further included. Each of the first wiring layers 221, 222, and 223 may perform various functions according to the design of the corresponding layer. For example, a ground pattern, a power pattern, a signal pattern, etc. may be included. Each of these patterns may include a line pattern, a plane pattern, and / or a pad pattern.

[0068] Each of the first via layers 231, 232, and 233 may include a metal material. The metal material may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. Each of the first via layers 231, 232, and 233 may perform various functions according to the design. For example, they may include a ground via, a power via, a signal via, and the like. Each of the first via layers 231, 232, and 233 may include, but is not limited to, an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). As the electroless plating layer, a sputtering layer may be formed instead of chemical copper, and both may be included. The 1-1 via layer 231 may include a through via. The through via may include a metal layer formed on the wall surface of the through hole and a plug filling the metal layer. The through via may have a cylindrical shape, but is not limited to this, and may have an hourglass shape. Each of the plurality of 1-2 via layers 232 and the plurality of 1-3 via layers 233 may include a microvia. The microvia may be a filled via that fills a via hole, or may be a conformal via that is arranged along the wall surface of the via hole. The microvias may be arranged in a stacked and / or staggered manner. The microvias may have a tapered shape. Each of the plurality of 1-2 via layers 232 and the plurality of 1-3 via layers 233 may have a microvia that is tapered in opposite directions to each other.

[0069] Each of the first and second semiconductor chips 310 and 320 may include an integrated circuit (IC) die in which hundreds to millions of elements are integrated into one chip. In this case, the integrated circuit may be, for example, a logic chip such as a central processor (e.g., CPU), a graphic processor (e.g., GPU), a field programmable gate array (FPGA), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, an application processor (e.g., AP), an analog-to-digital converter, or an application-specific IC (ASIC), but is not limited thereto, and may be other types of memory chips such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), a flash memory, a memory chip such as a High Bandwidth Memory (HBM), or a Power Management IC (PMIC). For example, the first semiconductor chip 310 may include a logic chip such as a GPU, and the second semiconductor chip 320 may include a memory chip such as an HBM. Alternatively, the first and second semiconductor chips 310 and 320 may be divided logic chips having different cores by being divided by a die split. However, this is not limited to this.

[0070] The first and second semiconductor chips 310 and 320 may each be formed based on an active wafer, and in this case, silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. may be used as a base material forming the respective bodies. Various circuits may be formed on the bodies. Each body may have a connection pad formed thereon, and the connection pad may include a conductive material such as aluminum (Al) or copper (Cu). The first and second semiconductor chips 310 and 320 may be bare dies, and in this case, metal bumps may be disposed on the connection pads. The first and second semiconductor chips 310 and 320 may be packaged dies, and in this case, a redistribution layer may be further formed on the connection pads, and metal bumps may be disposed on the redistribution layer. However, the present invention is not limited thereto.

[0071] The first and second semiconductor chips 310 and 320 may be connected to the first wiring layer 223 via a plurality of bumps 330. The plurality of bumps 330 may be formed of a low melting point metal, for example, solder such as tin (Sn)-aluminum (Al)-copper (Cu), but this is merely an example and the material is not particularly limited thereto. The plurality of bumps 330 may be formed in a multi-layer or single layer. When formed in a multi-layer, it may include copper pillars and solder, and when formed in a single layer, it may include tin-silver solder or copper, but is also not limited thereto.

[0072] The other contents are substantially the same as those described above, and therefore a duplicated description thereof will be omitted.

[0073] FIG. 11 is a cross-sectional view that shows a schematic diagram of another example of a printed circuit board, and FIG. 12 is a cross-sectional view that shows a schematic diagram of another example of an interconnect bridge.

[0074] Referring to the drawings, the printed circuit board 100B according to another example and the interconnect bridge 150B according to another example included therein may further include a protective material 156 in the printed circuit board 100A according to the example described above and the interconnect bridge 150A according to the example included therein. For example, the interconnect bridge 150B may further include a protective material 156 disposed on the insulating material 151 and covering at least one of the plurality of conductive posts 154. The protective material 156 may be disposed in a partial region on the upper surface of the insulating material 151. The protective material 156 may surround a side surface of at least one of the plurality of conductive posts 154 and may expose a portion of an upper end of the conductive post 154. Before the interconnect bridge 150B is embedded, the protective material 156 may be formed in a form completely covering the conductive post 151, and a portion of the protective material 156 may be removed during a process of forming the recess portion R after the interconnect bridge 150B is embedded. The upper surface of the protective material 156 may be substantially coplanar with the upper surface of the first insulating layer 111 on the recessed portion R. For example, the protective material 156 may be planarized during the formation of the recessed portion R. The protective material 156 may include an insulating material. The insulating material may be, but is not limited to, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material in which these resins are mixed with an inorganic filler such as silica, for example, an organic insulating material such as ABF. The protective material 156 may include an organic insulating material having high transparency among organic insulating materials. For example, the protective material 156 may have a relatively high transparency compared to the insulating material 151 and the first and second insulating layers 111 and 112. In this manner, the printed circuit board 100B according to another example may cover the plurality of conductive posts 154 with the protective material 156. Therefore, the conductive posts 154 may be protected, and the effective thickness of the interconnect bridge 150B may be improved. In addition, a flatter surface can be provided when mounting the interconnect bridge 150B. In addition, if the transparency of the protective material 156 is high, it may be easier to recognize the alignment when mounting the interconnect bridge 150, and therefore the accuracy of the mounting position can be improved.Therefore, the degree of matching can be improved when interconnect bridge 150B is built in.

[0075] The other contents are substantially the same as those described above. Meanwhile, the structure of the printed circuit board 100B according to another example may also be applied to the printed circuit board 500A according to the modified example described above, and a detailed description thereof will be omitted.

[0076] FIG. 13 is a cross-sectional view that shows a schematic diagram of a further example of a printed circuit board, and FIG. 14 is a cross-sectional view that shows a schematic diagram of a further example of an interconnect bridge.

[0077] Referring to the drawings, the printed circuit board 100C according to another example and the interconnect bridge 150C according to another example included therein may further include an alignment mark 157 in the printed circuit board 100B according to another example described above and the interconnect bridge 150B according to another example included therein. For example, the interconnect bridge 150C may further include an alignment mark 157 disposed on the insulating material 151 and spaced apart from the protective material 156. The alignment mark 157 may be disposed at substantially the same level as the plurality of conductive posts 154. The alignment mark 157 may be formed of the same material as when the plurality of conductive posts 154 is formed. For example, the alignment mark 157 may include the above-mentioned metal material. The alignment mark 157 may be embedded in the first insulating layer 111, but may be partially exposed through the recess portion R as necessary. In this manner, the printed circuit board 100C according to another example may include the interconnect bridge 150C including the alignment mark 157. Therefore, since it may be easier to recognize the alignment when mounting the interconnect bridge 150C, the accuracy of the mounting position can be improved, and therefore the degree of matching can be improved when the interconnect bridge 150C is built in.

[0078] The other contents are substantially the same as those described above. Note that the structure of the printed circuit board 100C according to the further example can also be applied to the printed circuit board 500A according to the above-mentioned modified example, and a detailed description thereof will be omitted.

[0079] FIG. 15 is a cross-sectional view illustrating a schematic diagram of yet another example of a printed circuit board; FIG. 16 is a cross-sectional view that illustrates a schematic diagram of yet another example of an interconnect bridge.

[0080] Referring to the drawings, the printed circuit board 100D according to another example and the interconnect bridge 150D according to another example included therein may have a structure in which the uppermost conductive pattern layer 152 of the plurality of conductive pattern layers 152 in the printed circuit board 100A according to the above-mentioned example and the interconnect bridge 150A according to the example included therein is disposed on an upper surface of an insulating material 151, and the uppermost conductive pattern layer 152 may include a conductive pad P3 connected to the conductive post 154 and a first ground pattern G1 spaced apart from the conductive post 154. In this manner, if necessary, the conductive pad P3 for the conductive post 154 may be further formed on the insulating material 151, and the first ground pattern G1 may be further formed in the remaining space. Therefore, the conductive post 154 may be formed higher more easily, and more diverse designs may be possible.

[0081] The other contents are substantially the same as those described above. Meanwhile, the structure of the printed circuit board 100D according to the further example can also be applied to the printed circuit board 500A according to the above-mentioned modified example, and a detailed description thereof will be omitted.

[0082] FIG. 17 is a cross-sectional view that shows a schematic diagram of a further example of a printed circuit board, and FIG. 18 is a cross-sectional view that shows a schematic diagram of a further example of an interconnect bridge.

[0083] Referring to the drawings, the printed circuit board 100E according to a further example and the interconnect bridge 150E according to a further example included therein may further include a protective material 156 in the printed circuit board 100D according to the further example and the interconnect bridge 150D according to the further example included therein described above. For example, the interconnect bridge 150E may further include a protective material 156 disposed on the insulating material 151 and covering at least one of the conductive posts 154 and the conductive pad P3 connected thereto. In this manner, the printed circuit board 100E according to a further example may further include the protective material 156, and thus may have various effects, such as improving the degree of matching when the interconnect bridge 150E is built in as described above.

[0084] The other contents are substantially the same as those described above. Meanwhile, the structure of the printed circuit board 100E according to another example can also be applied to the printed circuit board 500A according to the above-mentioned modified example, and a detailed description thereof will be omitted.

[0085] FIG. 19 is a cross-sectional view that shows a schematic diagram of yet another example of a printed circuit board, and FIG. 20 is a cross-sectional view that shows a schematic diagram of yet another example of an interconnect bridge.

[0086] Referring to the drawings, in the printed circuit board 100F according to yet another example and the interconnect bridge 150F according to yet another example included therein, in the printed circuit board 100E according to yet another example and the interconnect bridge 150E according to yet another example included therein, a protective material 156 may be further selectively formed. For example, the protective material 156 may cover some of the conductive posts 154 and some of the conductive pads P connected thereto. In this way, in the printed circuit board 100F according to yet another example, the protective material 156 may be selectively formed, thereby further increasing the degree of freedom in design.

[0087] The other contents are substantially the same as those described above. Meanwhile, the structure of the printed circuit board 100F according to another example can also be applied to the printed circuit board 500A according to the above-mentioned modified example, and a detailed description thereof will be omitted.

[0088] FIG. 21 is a cross-sectional view that shows a schematic diagram of a further example of a printed circuit board, and FIG. 22 is a cross-sectional view that shows a schematic diagram of a further example of an interconnect bridge.

[0089] Referring to the drawings, the printed circuit board 100G according to another example and the interconnect bridge 150G according to another example included therein are similar to the printed circuit board 100A according to the above example and the interconnect bridge 150A according to the above example, in which the conductive pattern layer 152 arranged at the bottom of the plurality of conductive pattern layers 152 of the interconnect bridge 150G may contact the adhesive 155, and the conductive pattern layer 152 arranged at the bottom may include a second ground pattern G2. For example, from the bottom layer to the top, the first and third layers may be ground layers, the second and fourth layers may be signal layers, and the signal connection line may not be arranged on the ground layer. In this way, the printed circuit board 100G according to another example may be designed in a more diverse manner.

[0090] The other contents are substantially the same as those described above. Meanwhile, the structure of the printed circuit board 100G according to another example can also be applied to the printed circuit board 500A according to the above-mentioned modified example, and a detailed description thereof will be omitted.

[0091] In the present invention, the thickness, width, length, depth, etc. can be measured with a scanning microscope or optical microscope based on a cross section obtained by polishing or cutting the printed circuit board. The cut section can be a vertical section or a horizontal section, and each value can be measured based on the required cut section. If the value is not constant, the value can be determined by averaging the values ​​measured at any five points. The width of the upper end and / or lower end of the via or recess can be measured on a cross section cut along the central axis in the thickness direction of the board. The depth of the via or recess can be measured as the distance from the upper end to the lower end of each object on a cross section cut along the central axis of each object in the thickness direction of the board.

[0092] In the present invention, the pitch may be measured by photographing a cut cross section of a printed circuit board using a scanning microscope or optical microscope, and the average pitch may be the average value of the pitch between wirings measured at any five points. The interlayer insulation distance may also be measured by photographing a cut cross section of a printed circuit board using a scanning microscope or optical microscope, and the average interlayer insulation distance may be the average value of the insulation distance between adjacent wirings or rewirings measured at any five points.

[0093] In the present invention, the transparency can be measured by polishing or cutting the printed circuit board in the length or width direction to a depth where the bridge is exposed to obtain a cross section, and then using a scanning microscope or optical microscope, for example, an optical microscope (x1000) manufactured by Olympus. Alternatively, it can be determined by transmittance and haze values, and the transmittance and haze can be measured by a UV-Vis Spectrometer of PerkinElmer's Lambda 1050 model. The transmittance can also be determined by a method of clarifying the constituent components through component analysis and then recombining them to obtain the transmittance. In addition, the transparency can also be determined by reflectance.

[0094] In the present invention, the term "cover" can include not only the case of covering entirely, but also the case of covering at least a part, and can include not only the case of covering directly, but also the case of covering indirectly. Furthermore, the term "fill" can include not only the case of filling completely, but also the case of filling almost entirely, for example, the case where some gaps or voids are present.

[0095] In the present invention, "substantially" can be determined by taking into account process errors, positional deviations, measurement errors, and the like that occur in the manufacturing process. For example, "substantially coplanar" can include not only a completely coplanar case, but also a nearly coplanar case. Furthermore, "substantially flat" can include not only a completely flat case, but also a nearly flat case.

[0096] In the present invention, the meaning of "on a cross section" can mean the cross-sectional shape when an object is cut vertically, or the cross-sectional shape when an object is cut vertically, or the cross-sectional shape when an object is viewed in a side view, and the meaning of "on a plane" can mean the planar shape when an object is cut horizontally, or the planar shape when an object is viewed in a top view or a bottom view.

[0097] In the present invention, for convenience, terms such as "lower side, lower part, lower surface" are used to mean a downward direction based on a cross section of a drawing, and terms such as "upper side, upper part, upper surface" are used to mean the opposite direction. However, these are merely definitions of directions for convenience of explanation, and the scope of the claims is not particularly limited by such directional descriptions, and the concepts of up / down can be changed at any time.

[0098] In the present invention, "connected" is a concept including not only direct connection but also indirect connection via an adhesive layer or the like. Furthermore, "electrically connected" is a concept including both physical connection and no connection. Furthermore, expressions such as "first, second" are used to distinguish one component from another component, and do not limit the order and / or importance of the components. In some cases, the first component may be named the second component, and similarly, the second component may be named the first component, within the scope of the right.

[0099] The term "one example" used in the present invention does not mean the same embodiment, but is provided to emphasize and describe unique features that are different from each other. However, the above-mentioned one example does not exclude that it is realized in combination with the features of another example. For example, even if the matter described in a specific example is not described in another example, it can be understood as a description related to the other example, unless there is a description in the other example that is opposite or contradictory to the matter.

[0100] The terms used in the present invention are merely used to describe an example and are not intended to limit the present invention. In this case, a singular expression includes a plural expression unless the context clearly indicates otherwise. [Explanation of symbols]

[0101] 1000:Electronic equipment 1010: Main board 1020: Chip related parts 1030: Network related parts 1040:Other parts 1050: Camera 1060:Antenna 1070:Display 1080: Battery 1090: Signal line 1100: Smartphone 1110: Motherboard 1120: Parts 1121: Parts package 1130: Camera module 1140: Speaker 2110: Main board 2210: BGA board 2220, 2240: Semiconductor chips 2230: Interposer 2250: Silicon interposer 2260: Organic interposer 2310, 2320: Semiconductor packages including interposers 100A, 100B, 100C, 100D, 100E, 100F, 100G, 500A: Printed Circuit Boards 111, 112, 113: insulating layers 121, 122, 123, 124: Wiring layer 131, 132, 133: Via layers 150A, 150B, 150C, 150D, 150E, 150F, 150G: Interconnect Bridges 151: Insulation material (insulation layer) 152: Conductive pattern layer (wiring layer) 153: Conductive via layer (via layer) 154: Conductive post 155: Adhesive 156: Protective materials 157: Alignment mark 211, 212, 213, 214: insulating layers 221, 222, 223: Wiring layer 231, 232, 233: Via layers 310, 320: Semiconductor chips 330: Bump R: Recessed part P1, P2: Pad patterns P3: Conductive pad G1, G2: Ground pattern

Claims

1. an interconnect bridge including an insulating material, a plurality of conductive pattern layers disposed on or within the insulating material, and a conductive post disposed on the insulating material; a first insulating layer having a recess in which the interconnect bridge is embedded and a portion of the conductive post is exposed; a first wiring layer disposed on the first insulating layer and including a first pad pattern coupled to the exposed portion of the conductive post above the recess portion.

2. the first wiring layer further includes a second pad pattern disposed in a region other than the recess and spaced apart from the conductive post; The printed circuit board according to claim 1 , wherein the top surfaces of the first and second pad patterns have a step with respect to each other.

3. The printed circuit board of claim 1 , wherein a portion of the conductive post is embedded in the first insulating layer and another portion protrudes above the upper surface of the first insulating layer.

4. The printed circuit board according to claim 3 , wherein the first pad pattern is disposed on the upper surface of the first insulating layer above the recessed portion and covers another protruding portion of the conductive post.

5. The first pad pattern is a first metal layer covering an upper surface of the first insulating layer and an upper surface and a side surface of another protruding part of the conductive post with a substantially constant thickness; 5. The printed circuit board of claim 4, further comprising: a second metal layer disposed on said first metal layer, said second metal layer having an average thickness greater than that of said first metal layer.

6. 2. The printed circuit board of claim 1, wherein the conductive posts are embedded in the first insulating layer and exposed from a top surface of the first insulating layer such that a top surface of the conductive posts is substantially coplanar with a top surface of the first insulating layer.

7. The printed circuit board of claim 6 , wherein the first pad pattern is disposed on the upper surface of the first insulating layer above the recessed portion and covers the exposed upper surfaces of the conductive posts.

8. The first pad pattern is a first metal layer covering a top surface of the first insulating layer and the exposed top surfaces of the conductive posts with a substantially constant thickness; 8. The printed circuit board of claim 7, further comprising: a second metal layer disposed on the first metal layer, the second metal layer having an average thickness greater than that of the first metal layer.

9. The conductive posts are provided in a plurality, the interconnect bridge further includes a protective material disposed on the insulating material and covering at least one of the conductive posts; The printed circuit board according to claim 1 , wherein the protective material is disposed on a partial area of ​​the upper surface of the insulating material.

10. The printed circuit board of claim 9 , wherein the interconnect bridge further includes an alignment mark disposed on the insulating material and spaced apart from the protective material.

11. The uppermost conductive pattern layer of the plurality of conductive pattern layers is disposed on an upper surface of the insulating material, 2. The printed circuit board of claim 1, wherein the uppermost conductive pattern layer includes a conductive pad connected to the conductive post and a first ground pattern spaced apart from the conductive post.

12. a conductive pattern layer disposed at a lowermost position among the plurality of conductive pattern layers contacting an adhesive attached to an underside of the interconnect bridge; The printed circuit board according to claim 1 , wherein the lowermost conductive pattern layer includes a second ground pattern.

13. a second wiring layer disposed within the first insulating layer; a first via layer penetrating the first insulating layer and connecting the first wiring layer and the second wiring layer; A second insulating layer disposed below the first insulating layer; a third wiring layer disposed within the second insulating layer; a second via layer penetrating the second insulating layer and connecting the second wiring layer and the third wiring layer; a third insulating layer disposed on the first insulating layer and covering the first wiring layer; a fourth wiring layer disposed on the third insulating layer; a third via layer penetrating the third insulating layer and connecting the first wiring layer and the fourth wiring layer, The printed circuit board of claim 1 , wherein a top surface of the third insulating layer is substantially flat.

14. The printed circuit board according to claim 1 , wherein the recessed portion has a tapered shape such that a width at an upper end is greater than a width at a lower end in a cross section.

15. The printed circuit board of claim 1 , wherein the conductive posts have an aspect ratio of greater than one.

16. a first substrate portion including a plurality of first insulating layers, a plurality of first wiring layers disposed on or within the plurality of first insulating layers, and a plurality of first via layers each penetrating at least one of the plurality of first insulating layers; a second substrate portion including a plurality of second insulating layers, a plurality of second wiring layers respectively disposed on or within the plurality of second insulating layers, a plurality of second via layers each penetrating at least one of the plurality of second insulating layers, and a plurality of conductive posts respectively disposed on a second insulating layer disposed on the uppermost side of the plurality of second insulating layers, the second substrate portion is disposed within the first substrate portion, At least one of the second wiring layers has an average pitch of wiring smaller than that of at least one of the first wiring layers; At least one of the first insulating layers has a stepped region exposing a portion of each of the conductive posts.

17. 17. The printed circuit board of claim 16, wherein the first and second insulating layers each comprise an organic insulating material.

18. 17. The printed circuit board of claim 16, further comprising a first semiconductor chip and a second semiconductor chip, each disposed on the first substrate portion and connected to each other via at least one of a plurality of second wiring layers of the second substrate portion.

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