Gallium nitride epitaxial structure for power device

Abstract

To provide a method and epitaxial semiconductor structure for fabricating multi-layer devices on an engineered substrate having a substrate thermal expansion coefficient.SOLUTION: A method for fabricating a multi-layer device includes the steps of growing a buffer layer 130 on an engineered substrate 102 having a substrate thermal expansion coefficient, and growing a GaN epitaxial layer 140 on the buffer layer 130. The GaN epitaxial layer 140 is characterized by an epitaxial thermal expansion coefficient substantially equal to the substrate thermal expansion coefficient. The engineered substrate 102 includes a ceramic substrate 110 having a thin silicon (Si) layer 120 or a thin silicon germanium (SiGe) layer formed thereon. The GaN epitaxial layer 140 includes a doped GaN epitaxial layer 142 and an undoped GaN epitaxial layer 144 below a conduction channel 150.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Patent Application No. 62 / 447,857, filed January 18, 2017, U.S. Provisional Patent Application No. 62 / 591,016, filed November 27, 2017, and U.S. Nonprovisional Patent Application No. 15 / 864,977, filed January 8, 2018, the contents of which are incorporated herein by reference in their entireties. [Background technology]

[0002]

[0002] Gallium nitride based power devices are typically epitaxially grown on sapphire substrates. The growth of gallium nitride based power devices on sapphire substrates is a heteroepitaxial growth process because the substrate and epitaxial layers are composed of different materials. Due to the heteroepitaxial growth process, the epitaxially grown materials may exhibit various adverse effects, including reduced uniformity and reduced metrics related to the electronic / optical properties of the epitaxial layers. Thus, there is a technical need for improved methods and systems related to epitaxial growth processes and substrate structures. Summary of the Invention [Means for solving the problem]

[0003] According to some embodiments of the present invention, a method for fabricating a multi-layer device on an engineered substrate having a substrate thermal expansion coefficient includes growing a buffer layer on the engineered substrate and growing a first epitaxial layer on the buffer layer, the first epitaxial layer being characterized by an epitaxial thermal expansion coefficient substantially equal to the substrate thermal expansion coefficient.

[0004] According to some other embodiments of the present invention, a method for fabricating a multilayer device on an engineered substrate having a substrate thermal expansion coefficient includes growing a buffer layer on the engineered substrate and growing one or more epitaxial layers on the buffer layer. At least one of the one or more epitaxial layers is characterized by an epitaxial thermal expansion coefficient substantially equal to the substrate thermal expansion coefficient. In some embodiments, the one or more epitaxial layers can include a superlattice of alternating undoped and doped GaN layers. The doped GaN layers can include carbon doped GaN (C-GaN) or iron doped GaN (Fe-GaN). The method can further include growing an undoped GaN layer coupled to the superlattice and growing a first epitaxial layer coupled to the undoped GaN layer. The first epitaxial layer can include aluminum gallium nitride (AlGaN) or indium aluminum nitride (InAlN). The interface between the undoped GaN layer and the first epitaxial layer can form a conducting channel of a high electron mobility transistor (HEMT). The engineered substrate can include a polycrystalline ceramic core, a barrier layer encapsulating the polycrystalline ceramic core, a bonding layer bonded to the barrier layer, and a substantially single crystalline silicon layer bonded to the bonding layer. The buffer layer can include at least one of AlN, AlGaN, or AlN / AlGaN.

[0005] According to some other embodiments of the present invention, a method for fabricating a multilayer device on an engineered substrate having a substrate thermal expansion coefficient includes growing a buffer layer on the engineered substrate and growing a first epitaxial layer coupled to the buffer layer. The first epitaxial layer is characterized by an epitaxial thermal expansion coefficient substantially equal to the substrate thermal expansion coefficient. The method further includes growing an aluminum gallium nitride (AlGaN) back barrier layer coupled to the first epitaxial layer, growing an undoped gallium nitride (GaN) layer coupled to the AlGaN back barrier layer, and growing a barrier layer coupled to the undoped GaN layer.

[0006] According to some further embodiments, an epitaxial semiconductor structure includes an engineered substrate having a substrate thermal expansion coefficient, a buffer layer formed on the engineered substrate, and a first epitaxial layer formed on the buffer layer, the first epitaxial layer being characterized by an epitaxial thermal expansion coefficient substantially equal to the substrate thermal expansion coefficient. [Brief description of the drawings]

[0007] [Figure 1] 1 is a simplified schematic cross-sectional view illustrating a power device formed on an engineered substrate structure according to one embodiment of the present invention. [Diagram 2] 1 is a simplified schematic cross-sectional view illustrating a power device formed on an engineered substrate structure according to another embodiment of the present invention. [Diagram 3] 1 is a simplified schematic cross-sectional view illustrating a power device formed on an engineered substrate structure having a backside contact in accordance with an embodiment of the present invention. [Figure 4] 1 is a simplified schematic cross-sectional view illustrating a power device formed on an engineered substrate structure having a front contact according to an embodiment of the present invention. [Diagram 5] 1 is a simplified schematic cross-sectional view illustrating a power device formed on an engineered substrate structure according to one embodiment of the present invention. [Figure 6]1 is a simplified schematic cross-sectional view illustrating a power device formed on an engineered substrate structure according to another embodiment of the present invention. [Figure 7] 1 is a simplified schematic cross-sectional view illustrating a power device formed on an engineered substrate structure according to a further embodiment of the present invention. [Figure 8] 1A-1D are simplified schematic cross-sectional views illustrating power devices formed on engineered substrate structures according to some other embodiments of the present invention. [Figure 9A] FIG. 2 is an exemplary conduction band diagram for a HEMT without an AlGaN back barrier layer, according to some embodiments. [Figure 9B] FIG. 2 is an exemplary conduction band diagram for a HEMT having an AlGaN back barrier layer in accordance with some other embodiments. [Figure 10] 1 is a simplified schematic cross-sectional view illustrating a substrate structure suitable for use in fabricating a power device according to an embodiment of the present invention. [Figure 11] 1 is a simplified schematic cross-sectional view illustrating an engineered substrate structure according to one embodiment of the present invention. [Figure 12] 1A-1D are simplified schematic diagrams illustrating engineered substrate structures according to some embodiments of the present invention. [Figure 13] 1A-1C are simplified schematic diagrams illustrating engineered substrate structures according to some other embodiments of the present invention. [Figure 14] 1A-1C are simplified schematic diagrams illustrating engineered substrate structures according to some further embodiments of the present invention. [Figure 15] 1 is a simplified flow chart illustrating a method of manufacturing an engineered substrate according to some embodiments of the present invention. [Figure 16] 1 is a simplified flow chart illustrating a method for fabricating a multi-layer device on an engineered substrate according to some embodiments of the present invention. [Figure 17] 4 is a simplified flow chart illustrating a method for fabricating a multi-layer device on an engineered substrate according to some other embodiments of the present invention. [Figure 18]4 is a simplified flow chart illustrating a method for fabricating a multi-layer device on an engineered substrate according to some further embodiments of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008]

[0026] The present invention relates generally to power devices formed on engineered substrates. More specifically, the present invention relates to methods and systems suitable for fabricating power devices using epitaxial growth processes. By way of example only, the present invention applies to methods and systems for fabricating power devices on substrates by epitaxial growth, the substrate being characterized by a coefficient of thermal expansion (CTE) that substantially matches the epitaxial layers that form the power devices. The methods and techniques can be applied to a variety of semiconductor process steps.

[0009]

[0027] 1 is a simplified schematic cross-sectional view illustrating a power device formed on an engineered substrate structure 102 according to one embodiment of the present invention. The engineered substrate structure 102 may include a ceramic substrate 110 having a thin silicon (Si) layer 120 formed thereon. The silicon layer 120 may provide a surface for subsequent epitaxial growth. The ceramic substrate 110 may have a CTE that substantially matches the CTE of one or more subsequent epitaxial layers.

[0010]

[0028] The buffer layer 130 may be epitaxially formed on the Si layer 120. The buffer layer 130 may include one or more layers. In some embodiments, the buffer layer 130 may be relatively thin, e.g., less than 0.5 microns thick. The buffer layer 130 may be, for example, about 0.2 μm thick AlN, about 0.125 μm thick Al 0.25 Ga 0.75 A relatively thin aluminum-containing buffer layer (e.g., 0.2 μm AlN / 0.125 ... 0.25 Ga0.75 N) can support GaN epitaxy of greater than 8 microns on large diameter substrates that cannot be produced using silicon substrates.

[0011]

[0029] A GaN epitaxial layer 140 may be formed on the buffer layer 130. In some embodiments, the GaN epitaxial layer 140 may have a thickness of more than 8 μm for high breakdown voltage. For example, a breakdown voltage of more than 500 V or 600 V may be achieved in a power device subsequently formed on the GaN epitaxial layer 140. As shown in FIG. 1, the GaN epitaxial layer 140 may include a doped GaN epitaxial layer 142 and an undoped GaN epitaxial layer 144 below (e.g., directly below) the conductive channel 150. The doped GaN epitaxial layer 142 may have a thickness of 5 μm or more. The doped GaN epitaxial layer 142 may include GaN doped with C or Fe to provide high resistivity, in some embodiments. As described more fully herein, low conductivity layers such as C-GaN or Fe-GaN layers may be formed, which may have a conductivity of less than 1×10 because the carbon or iron compensates for background impurities or provides a deep center. 12 cm -3 It may have a background doping level (free carrier density) of about 100 nm.

[0012]

[0030] Although GaN layers are described herein, the invention is not limited to GaN and other III-V materials may be utilized, including AlGaN, InGaN, InAlGaN, combinations thereof, etc. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.

[0013]

[0031] An AlGaN or InAlN layer 160 can be formed as a barrier layer on the GaN epitaxial layer 140. The AlGaN / GaN interface can give rise to a two-dimensional electron gas (2DEG) due to polarization-induced charges at the heterointerface. The two-dimensional electron gas forms the conductive channel 150 of a high electron mobility transistor (HEMT) power device.

[0014]

[0032] In some embodiments, an optional undoped or p-type GaN cap layer 170 suitable for fabricating an enhancement mode device may be formed on the AlGaN or InAlN layer 160.

[0015]

[0033] The ceramic substrate 110 can have a CTE that substantially matches the CTE of the GaN epitaxial layer, such that a relatively thin (e.g., less than 0.5 μm) buffer layer 130 can support a relatively thick (e.g., greater than 5 μm) GaN epitaxial layer 140.

[0016]

[0034] 2 is a simplified schematic cross-sectional view illustrating a power device formed on an engineered substrate structure 202 according to an embodiment of the present invention. The engineered substrate structure 202 can include a ceramic substrate 110 having a thin silicon germanium (SiGe) layer 220 formed thereon. The silicon germanium layer 220 can provide a lattice-matched surface for subsequent epitaxial growth. The ceramic substrate 110 can have a CTE that substantially matches the CTE of the subsequent epitaxial layer. The SiGe layer 220 can be epitaxially grown on a Si layer (not shown) or transferred from a donor substrate (e.g., by bonding the donor substrate with a SiGe layer formed thereon and a ceramic substrate).

[0017]

[0035] The buffer layer 130 may be epitaxially formed on the SiGe layer 220. The buffer layer 130 may include one or more layers. In some embodiments, the buffer layer 130 may be relatively thin, e.g., less than 0.5 microns thick. The buffer layer 130 may be, for example, about 0.2 μm thick AlN, about 0.125 μm thick Al 0.25 Ga 0.75 A relatively thin aluminum-containing buffer layer 130 (e.g., 0.2 μm AlN / 0.125 μm AlN) may be used. 0.25 Ga 0.75 N) can support GaN epitaxy of greater than 8 microns on large diameter substrates that cannot be produced using silicon substrates.

[0018]

[0036] A GaN epitaxial layer 140 may be formed on the buffer layer 130. In some embodiments, the GaN epitaxial layer 140 may have a thickness of more than 8 μm for high breakdown voltage. For example, a breakdown voltage of more than 500 V or 600 V may be achieved in a power device subsequently formed on the GaN epitaxial layer. As shown in FIG. 2, the GaN epitaxial layer may include, for example, a 5 μm doped epitaxial layer 142 and an undoped GaN layer 144 below (e.g., beneath) the conduction channel 150. The doped epitaxial layer 142 may include GaN doped with C or Fe in some embodiments. Although a GaN layer is described herein, the invention is not limited to GaN and other III-V materials may be utilized, including AlGaN, InGaN, InAlGaN, combinations thereof, and the like. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.

[0019]

[0037] An AlGaN or InAlN layer 160 can be formed as a barrier layer on the GaN epitaxial layer 140. The AlGaN / GaN interface can give rise to a two-dimensional electron gas (2DEG) due to polarization-induced charges at the heterointerface. The two-dimensional electron gas forms the conductive channel 150 of a high electron mobility transistor (HEMT) power device.

[0020]

[0038] In some embodiments, an optional undoped or p-type GaN cap layer 170 suitable for fabricating an enhancement mode device may be formed on the AlGaN or InAlN layer 160.

[0021]

[0039] 3 is a simplified schematic cross-sectional view illustrating a power device formed on an engineered substrate structure 102 according to one embodiment of the present invention. The engineered substrate structure 102 can include a ceramic substrate 110 having a thin Si layer 120 formed thereon. The Si layer 120 can provide a surface for subsequent epitaxial growth. The ceramic substrate 110 can have a CTE that substantially matches the CTE of the subsequent epitaxial layer.

[0022]

[0040] The power device may further include a buffer layer 130 epitaxially formed on the Si layer 120, a GaN epitaxial layer 140 formed on the buffer layer 130, and an AlGaN or InAlN barrier layer 160 formed on the GaN epitaxial layer 140, substantially similar to the power device shown in Figure 1. The GaN epitaxial layer 140 may include a 5 μm doped epitaxial layer 142 and an undoped GaN layer 144 below (e.g., directly below) the conduction channel 150. The GaN epitaxial layer 140 may also include one or more conductive epitaxial layers below the doped epitaxial layer (e.g., as shown in Figure 4).

[0023]

[0041] The power device may further include an electrical contact 310 formed through the ceramic substrate 110 to the Si layer 120 or the GaN epitaxial layer 140. During operation of the power device, some parasitic charge may build up in the Si layer 120 and / or the buffer layer 130, resulting in parasitic capacitance. The electrical contact 310 may facilitate removal of the parasitic charge, thereby enabling faster switching of the power device.

[0024]

[0042] 4 is a simplified schematic cross-sectional view illustrating a power device formed on an engineered substrate structure 102 according to one embodiment of the present invention. The engineered substrate structure 102 may include a ceramic substrate 110 having a thin silicon (Si) layer 120 formed thereon. The silicon layer 120 may provide a surface for subsequent epitaxial growth. The ceramic substrate 110 may have a CTE that substantially matches the CTE of a subsequent epitaxial layer.

[0025]

[0043] A GaN epitaxial layer 140 may be formed on the buffer layer 130. In some embodiments, the GaN epitaxial layer 140 may have a thickness of more than 8 μm for high breakdown voltage. For example, a breakdown voltage of more than 500 V or 600 V may be achieved in a power device subsequently formed on the GaN epitaxial layer 140. As shown in FIG. 4, the GaN epitaxial layer 140 may include, for example, a conductive GaN epitaxial layer 420, a doped GaN epitaxial layer 142, and an undoped GaN layer 144 below (e.g., beneath) the conductive channel 150. The doped epitaxial layer 142 may include GaN doped with C or Fe in some embodiments. Although a GaN layer is described herein, the invention is not limited to GaN, and other III-V materials may be utilized, including AlGaN, InGaN, InAlGaN, combinations thereof, and the like. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.

[0026]

[0044] An AlGaN or InAlN layer 160 can be formed as a barrier layer on the GaN epitaxial layer 140. The AlGaN / GaN interface can give rise to a two-dimensional electron gas (2DEG) due to polarization-induced charges at the heterointerface. The two-dimensional electron gas forms the conductive channel 150 of a high electron mobility transistor (HEMT) power device.

[0027]

[0045] In some embodiments, an optional undoped or p-type GaN cap layer 170 suitable for fabricating an enhancement mode device may be formed on the AlGaN or InAlN layer 160.

[0028]

[0046] The power device may further include an electrical contact 410 to the Si layer 120 or the GaN epitaxial layer 140 formed through the front side of the power device. Although FIG. 4 shows the electrical contact extending through the GaN epitaxial layer 140 to the buffer layer 130, in some embodiments the electrical contact may extend to the Si layer 120. The electrical contact may be insulated on its sidewalls so as not to be electrically connected to the AlGaN or InAlN layer 160 and the GaN epitaxial layer 140. The electrical contact 410 may facilitate removal of parasitic charges, thereby enabling faster switching of the power device.

[0029]

[0047] 5 is a simplified schematic cross-sectional view illustrating a power device formed on an engineered substrate structure 102 according to another embodiment of the present invention. The engineered substrate 102 may include a ceramic substrate 110 having a thin silicon (Si) layer 120 formed thereon. The silicon layer 120 may be a single crystal layer and may provide a surface for subsequent epitaxial growth. The ceramic substrate 110 may have a CTE that substantially matches the CTE of one or more of the subsequent epitaxial layers.

[0030]

[0048] As shown in FIG. 5, a partial monolayer 510 of SiN can be inserted to aid in the reduction of dislocations associated with 3D growth. The use of an engineered substrate 102 can allow for the reduction of compressive stress in the epitaxial layers through the use of a polycrystalline ceramic core substrate 110. As shown in FIG. 5, the partial monolayer 510 of SiN can provide SiN islands that are utilized in the lateral overgrowth process to reduce dislocation density and improve crystal quality. Further description is provided in U.S. Patent No. 9,012,253, issued April 21, 2015, the disclosure of which is incorporated herein by reference in its entirety for all purposes.

[0031]

[0049] The partial monolayer 510 of SiN can cover a portion of the buffer layer 130 and can provide tensile stress for GaN epitaxial growth. Regrowth of GaN on the partial monolayer 510 of SiN can result in nucleation between the SiN islands and lateral overgrowth on the SiN islands, resulting in termination of dislocations and improved crystal quality. Although SiN islands are described herein, other partial layers can be utilized, including arrays of SiN stripes, and the like. Furthermore, the SiN need not be formed as a monolayer, but can have a predetermined thickness greater than a monolayer. In addition to SiN, SiO 2 Other materials may be utilized in the lateral overgrowth process, including, for example,

[0032]

[0050] In some embodiments, multiple partial monolayers are utilized. In these embodiments, a first partial monolayer is formed, a first lateral overgrowth is performed, a second partial monolayer is formed, a second lateral overgrowth is performed, and the monolayer / regrowth structure is repeated a predetermined number of times to obtain multiple intermediate layers. The thickness of the lateral overgrowth layer may vary, for example, from 0.5 μm to 2.5 μm in some embodiments. The partial monolayer 510 may improve the surface of the subsequent lateral overgrowth layer, as the lateral overgrowth layers are successively flatter and characterized by a lower number of defects and / or dislocations, which may allow the thickness to be increased or decreased depending on the particular application.

[0033]

[0051] In some embodiments, the conductive epitaxial layer 420 formed on the partial monolayer 510 of SiN is 1×10 in design to provide a high resistivity layer as part of the overall epitaxial structure. 16 cm -3 It may also be undoped GaN (u-GaN), which is characterized by a relatively low doping density.

[0034]

[0052] 6 is a simplified schematic cross-sectional view illustrating a power device formed on an engineered substrate structure 102 according to another embodiment of the present invention. The engineered substrate 102 may include a ceramic substrate 110 having a thin silicon (Si) layer 120 formed thereon. The silicon layer 120, which may be a single crystal layer, provides a surface for subsequent epitaxial growth. The ceramic substrate 110 may have a CTE that substantially matches the CTE of one or more of the subsequent epitaxial layers.

[0035]

[0053] As shown in FIG. 6, Al x Ga 1-x An AlN epitaxial layer 640 extends from the buffer layer 130 to the undoped GaN layer 144 below the channel 150. The aluminum mole fraction may be low, for example less than 10%, to provide the desired carrier confinement. In other embodiments, the aluminum mole fraction may be in the range of 10% to 30%. x Ga 1-x The N epitaxial layer 640 can be doped with iron or carbon to further increase the resistivity of this epitaxial layer, which can act as an insulating or blocking layer. The bandgap difference between AlGaN and GaN can provide an additional barrier to breakdown.

[0036]

[0054] 7 is a simplified schematic cross-sectional view illustrating a power device formed on an engineered substrate structure 102 according to another embodiment of the present invention. The engineered substrate 102 may include a ceramic substrate 110 having a thin silicon (Si) layer 120 formed thereon. The silicon layer 120 may be a single crystal layer and may provide a surface for subsequent epitaxial growth. The ceramic substrate 110 may have a CTE that substantially matches the CTE of one or more of the subsequent epitaxial layers.

[0037]

[0055] In FIG. 7, epitaxial structure 740 is formed by growing alternating layers of C-GaN (or Fe-GaN) and undoped GaN (u-GaN) layers to provide high resistance with improved crystal quality. Because u-GaN is typically grown at higher temperatures compared to C-GaN or Fe-GaN, and higher growth temperatures are typically associated with higher quality crystals, the presence of u-GaN in the superlattice allows for higher crystal quality. Thus, the structure maintains the insulating properties of the epitaxial layers providing high breakdown performance while improving crystal quality. In some embodiments, even without intentional doping, as a result of incorporation of dopants present in the growth chamber, u-GaN can grow to as low as 1×10 16 cm -3 These layers, which have low electrical conductivity, can be combined with C-GaN or Fe-GaN layers in a superlattice, where the C-GaN or Fe-GaN layers have background doping levels of around 1×10, as the carbon or iron compensates for the background impurities. 12 cm -3 The background doping level (free carrier density) is about 100 nm, so the superlattice can provide high resistance and high quality crystals.

[0038]

[0056] FIG. 8 is a simplified schematic cross-sectional view illustrating a power device formed on an engineered substrate structure 102 according to another embodiment of the present invention. The engineered substrate 102 may include a ceramic substrate 110 having a thin silicon (Si) layer 120 formed thereon. The silicon layer 120 may be a single crystal layer and may provide a surface for subsequent epitaxial growth. The ceramic substrate 110 may have a CTE that substantially matches the CTE of one or more of the subsequent epitaxial layers. A buffer layer 130 may be epitaxially formed on the Si layer 120. As described above with reference to FIGS. 1 and 7, an unintentionally doped GaN (UID-GaN) epitaxial layer 840 (or alternating layers of C-GaN (or Fe-GaN) and undoped GaN (uGaN) layers) may be formed on the buffer layer 130.

[0039]

[0057] Continuing with reference to FIG. 8, an undoped low-composition AlGaN layer 810 may be formed on the UID-GaN layer 840 (or alternating layers of C-GaN (or Fe-GaN) and uGaN). The undoped low-composition AlGaN layer 810 may be referred to as a back barrier layer. An undoped GaN layer 144 may be formed on the undoped low-composition AlGaN layer 810. An AlGaN (or InGaN) layer 160 may be formed on the undoped GaN layer 810. The AlGaN (or InGaN) layer 160 may be referred to as a barrier layer. The AlGaN / GaN interface may give rise to a two-dimensional electron gas (2DEG) due to polarization-induced charges at the heterointerface. The two-dimensional electron gas forms the conductive channel 150 of a high electron mobility transistor (HEMT) power device. The addition of a low-composition AlGaN layer 810 (i.e., a back barrier layer) can enhance the retention of electrons in the conduction channel 150 and prevent them from entering the UID-GaN layer 840 (or alternating layers of C-GaN (or Fe-GaN) and uGaN) as leakage current, as described below.

[0040]

[0058] 9A shows an exemplary conduction band (CB) diagram of a HEMT without a back barrier layer according to some embodiments. The AlGaN barrier layer 160 has an aluminum mole fraction ranging from about 10% to about 100% and a thickness d ranging from about 1 nm to about 100 nm. 1 The GaN layer 144 (i.e., the channel) may have a thickness d in the range of about 10 nm to about 100 nm. 2 The UID-GaN layer 840 may have a thickness d greater than about 8 μm for high voltage resistance as discussed above. 3 As shown in FIG. 9A, the conduction band of the AlGaN barrier layer 160 can be F ) with respect to the first barrier height E B1 , which may range from about 1 eV to about 4 eV. The conduction band of the UID-GaN layer 840 is at the Fermi level (E F ) with respect to the second barrier height E B2 can be formed, which is the first barrier height E B1 In some embodiments, E B2 may range from 0.2 eV to 1.5 eV. Therefore, electrons in the channel (2DEG) 150 can easily penetrate into the UID-GaN layer 840, thereby causing leakage current.

[0041]

[0059] 9B shows an exemplary conduction band (CB) diagram of a HEMT having a low-composition AlGaN back barrier layer 810 according to another embodiment. For clarity, elements shown with respect to FIG. 9A are not repeated here. The low-composition AlGaN back barrier layer 810 has an aluminum mole fraction in the range of about 1% to about 50%, e.g., about 3% to about 15%, and a thickness d in the range of about 0.1 μm to about 1 μm, e.g., about 0.2 μm to about 0.3 μm. 4 In some embodiments, the AlGaN back barrier layer 810 may be undoped. As shown, the low composition AlGaN back barrier layer 810 has a Fermi level (E F) the second barrier height E formed by the UID-GaN layer 840 without using the low-composition AlGaN back barrier layer 810 B2 The third barrier height E is relatively high compared to B3 In some embodiments, E B3 can be in the range of 1 to 3 eV. Therefore, by adding a low-composition AlGaN back barrier layer 810, electrons in the channel (2DEG) can be prevented from penetrating into the UID-GaN layer, thereby reducing the leakage current through the substrate.

[0042]

[0060] FIG. 10 is a simplified schematic cross-sectional view illustrating a substrate structure 102 suitable for use in fabricating a power device according to an embodiment of the present invention. With reference to FIG. 10, an engineered substrate 102 can be provided that can include the elements illustrated in FIG. 11, including a polycrystalline ceramic core 110. A single crystal layer 120 (e.g., single crystal silicon) is bonded to the polycrystalline ceramic core 110, for example, using a layer transfer process, to provide a single crystal growth surface. A buffer layer 130 can be grown on the single crystal layer 120, and a III-V epitaxial layer 1040 (e.g., GaN) is grown on the buffer layer 130. The CTE of the III-V epitaxial layer 1040 can be substantially matched to the CTE of the core of the polycrystalline ceramic core 110. The III-V epitaxial layer 1040 can be single crystal and of high quality, in part due to the matched CTE.

[0043]

[0061] 11 is a simplified schematic diagram illustrating an engineered substrate structure according to some embodiments of the present invention. As shown in FIG. 11, the engineered substrate structure may be suitable for a variety of electronic and optical applications. The engineered substrate structure includes a core 1110 (e.g., an AlN substrate) that may have a coefficient of thermal expansion (CTE) that substantially matches the CTE of an epitaxial material grown on the engineered substrate structure, e.g., an exfoliated silicon (111) layer 1125.

[0044]

[0062] For applications involving the growth of gallium nitride (GaN) based materials (epitaxial layers including GaN based layers), the core 1110 may be a polycrystalline ceramic material, for example polycrystalline aluminum nitride (AlN), which may include a binder material such as yttrium oxide. Polycrystalline gallium nitride (GaN), polycrystalline aluminum gallium nitride (AlGaN), polycrystalline silicon carbide (SiC), polycrystalline zinc oxide (ZnO), polycrystalline gallium trioxide (Ga 2 O 3 Other materials may be utilized for the core, including, for example, tungsten carbide ... and the like.

[0045]

[0063] The core 1110 may have a thickness on the order of 100-1,500 μm, for example 750 μm. The core 1110 is encapsulated in an adhesion layer 1112, which may be referred to as a shell or encapsulation shell. In one embodiment, the adhesion layer 1112 comprises a tetraethylorthosilicate (TEOS) oxide layer having a thickness on the order of 1,000 Å. In other embodiments, the thickness of the adhesion layer 1112 varies, for example, from 100 Å to 2,000 Å. Although TEOS oxide is utilized for the adhesion layer 1112 in some embodiments, other materials that provide adhesion between a subsequently deposited layer and an underlying layer or material (e.g., ceramics, particularly polycrystalline ceramics) may also be utilized in accordance with embodiments of the present invention. For example, SiO 2 or other silicon oxide (Si x O y ) adheres well to ceramic materials and provides a suitable surface for subsequent deposition of, for example, conductive materials. Adhesion layer 1112 completely surrounds core 1110 in some embodiments, forming a completely encapsulated core 1110, and may be formed using an LPCVD process or other suitable deposition process, which may be compatible with semiconductor processing, particularly polycrystalline or composite substrates and layers. Adhesion layer 1112 provides a surface onto which subsequent layers adhere to form elements of an engineered substrate structure.

[0046]

[0064] In addition to using LPCVD processes, spin-on-glass / dielectric, furnace-based processes, and the like to form the encapsulating adhesion layer, other semiconductor processes including CVD processes or similar deposition processes can be utilized in accordance with embodiments of the present invention. As an example, a deposition process can be utilized to coat a portion of the core 1110, the core 1110 can be turned over, and the deposition process can be repeated to coat an additional portion of the core 1110. Thus, while LPCVD techniques are utilized in some embodiments to provide a fully encapsulated structure, other film formation techniques can be utilized depending on the particular application.

[0047]

[0065] Referring to FIG. 11, a conductive layer 1114 is formed surrounding the adhesion layer 1112. In one embodiment, the conductive layer 1114 is a shell of polysilicon (i.e., polycrystalline silicon) that is formed surrounding the adhesion layer 1112 because polysilicon has poor adhesion to ceramic materials. In embodiments in which the conductive layer 1114 is polysilicon, the thickness of the polysilicon layer may be on the order of 500-5,000 Å, for example 2,500 Å. In some embodiments, the polysilicon layer may be formed as a shell to completely surround the adhesion layer 1112 (e.g., a TEOS oxide layer), thereby forming a fully encapsulated adhesion layer 1112, which may be formed using an LPCVD process. In other embodiments, as described below, the conductive material may be formed on a portion of the adhesion layer 1112, for example, on the bottom half of the substrate structure. In some embodiments, the conductive material may be formed as a completely encapsulating layer and subsequently removed on one side of the substrate structure.

[0048]

[0066] In one embodiment, the conductive layer 1114 may be a polysilicon layer doped to provide a highly conductive material, for example a polysilicon layer doped with boron to provide a p-type polysilicon layer. In some embodiments, the doping with boron is on the order of 1×10 to provide high conductivity. 19 cm -3 ~1×10 20 cm -3The level of other dopants with different dopant concentrations (e.g., 1×10 16 cm -3 ~5×10 18 cm -3 Dopant concentrations ranging from 0.1 to 1000 nm (e.g., phosphorous, arsenic, bismuth, etc.) can be utilized to provide either n-type or p-type semiconductor materials suitable for use in conductive layer 1114. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.

[0049]

[0067] The presence of the conductive layer 1114 is useful in electrostatically chucking a fabricated substrate to a semiconductor processing tool, such as a tool having an electrostatic chuck (ESC or e-chuck). The conductive layer allows for rapid dechucking after processing in the semiconductor processing tool. In an embodiment of the invention, the conductive layer 1114 allows for electrical contact with the chuck or capacitive coupling to the e-chuck during future processing, including bonding. Thus, an embodiment of the invention provides a substrate structure that can be processed in a manner utilized with conventional silicon wafers. Those skilled in the art will recognize many variations, modifications, and alternatives. Additionally, having a substrate structure with high thermal conductivity in combination with an electrostatic chuck can provide better deposition conditions for subsequent fabrication and epitaxial layer formation, as well as subsequent device fabrication steps. For example, it can provide a desirable thermal profile that can result in lower stress, more uniform deposition thickness, and better stoichiometry control throughout subsequent layer formation.

[0050]

[0068] A second adhesion layer 1116 (e.g., a TEOS oxide layer having a thickness on the order of 1,000 Å) is formed surrounding the conductive layer 1114. In some embodiments, the second adhesion layer 1116 completely surrounds the conductive layer 1114 to form a fully encapsulated structure and may be formed using an LPCVD process, a CVD process, or any other suitable deposition process including deposition of a spin-on dielectric.

[0051]

[0069] A barrier layer 1118, for example a silicon nitride layer, is formed surrounding the second adhesive layer 1116. In one embodiment, the barrier layer 1118 is a silicon nitride layer with a thickness on the order of 2,000 Å to 5,000 Å. In some embodiments, the barrier layer 1118 completely surrounds the second adhesive layer 1116, forming a fully encapsulated structure, and can be formed using an LPCVD process. In addition to silicon nitride layers, amorphous materials including SiCN, SiON, AlN, SiC, etc. can be utilized as the barrier layer 1118. In some implementations, the barrier layer 1118 is comprised of several auxiliary layers constructed to form the barrier layer 1118. Thus, the term barrier layer is not intended to mean a single layer or material, but rather to encompass one or more materials stacked together in a composite manner. One skilled in the art would recognize many variations, modifications, and alternatives.

[0052]

[0070] In some embodiments, the barrier layer 1118, e.g., a silicon nitride layer, prevents elements present in the core, such as yttrium (elemental), yttrium oxide (i.e., yttria), oxygen, metallic impurities, and other trace elements, from diffusing and / or outgassing into the environment of a semiconductor processing chamber in which the engineered substrate may reside, e.g., during high temperature (e.g., 1,000° C.) epitaxial growth processes. Utilizing the encapsulation layers described herein, ceramic materials including polycrystalline AlN designed for non-cleanroom environments can be utilized in semiconductor process flows and cleanroom environments.

[0053]

[0071] Typically, the ceramic material utilized to form the core is fired at a temperature in the range of 1,800°C. It is expected that this process will drive off a significant amount of impurities present in the ceramic material. These impurities may include yttrium, calcium, and other elements and compounds resulting from the use of yttria as a sintering agent. Subsequent diffusion of these impurities during the epitaxial growth process, which is carried out at much lower temperatures in the range of 800°C to 1,100°C, would be expected to be insignificant. However, contrary to conventional expectations, the present inventors have determined that there is significant diffusion of elements through the layers of the engineered substrate even during the epitaxial growth process at temperatures much lower than the firing temperature of the ceramic material. Accordingly, embodiments of the present invention integrate a barrier layer 1118 into the engineered substrate structure to prevent this undesired diffusion.

[0054]

[0072] Referring again to FIG. 11, a bonding layer 1120 (e.g., a silicon oxide layer) is deposited on a portion of the barrier layer 1118, e.g., on top of the barrier layer 1118, and subsequently used during bonding of the substantially single crystal layer 1125 (e.g., a single crystal silicon layer, such as the exfoliated silicon (111) layer shown in FIG. 11). The bonding layer 1120 may be about 1.5 μm thick in some embodiments. In some embodiments, the thickness of the bonding layer 1120 is 20 nm or more for bonding-induced void mitigation. In some embodiments, the thickness of the bonding layer 1120 is in the range of 0.75 to 1.5 μm.

[0055]

[0073] The substantially single crystalline layer 1125 (e.g., exfoliated Si(111)) is suitable for use as a growth layer during an epitaxial growth process to form an epitaxial material. In some embodiments, the epitaxial material may include a GaN layer having a thickness of 2 μm to 10 μm, which may be utilized as one of multiple layers utilized in optoelectronic, RF, and power devices. In one embodiment, the substantially single crystalline layer 1125 includes a single crystalline silicon layer attached to the bonding layer 1120 using a layer transfer process.

[0056]

[0074] Further description of engineered substrate structures is provided in U.S. patent application Ser. No. 15 / 621,335, filed Jun. 13, 2017, and U.S. patent application Ser. No. 15 / 621,235, filed Jun. 13, 2017, the disclosures of which are incorporated by reference in their entireties for all purposes.

[0057]

[0075] FIG. 12 is a simplified schematic cross-sectional view illustrating an engineered substrate 1200 according to one embodiment of the present invention. The engineered substrate 1200 shown in FIG. 12 is suitable for a variety of electronic and optical applications. The engineered substrate 1200 includes a core 1210 that can have a coefficient of thermal expansion (CTE) that substantially matches the CTE of an epitaxial material grown on the engineered substrate 1200. The epitaxial material 1230 is not required as an element of the engineered substrate 1200, but is shown as optional since it is typically grown on the engineered substrate 1200.

[0058]

[0076] For applications involving the growth of gallium nitride (GaN) based materials (epitaxial layers including GaN based layers), the core 1210 may be a polycrystalline ceramic material such as polycrystalline aluminum nitride (AlN) which may include a binder material such as yttrium oxide. Polycrystalline gallium nitride (GaN), polycrystalline aluminum gallium nitride (AlGaN), polycrystalline silicon carbide (SiC), polycrystalline zinc oxide (ZnO), polycrystalline gallium trioxide (Ga 2 O 3 Other materials may be utilized for the core 1210, including, for example, tungsten carbide ... and the like.

[0059]

[0077] The thickness of the core 1210 may be on the order of 100 μm to 1,500 μm, for example 725 μm. The core 1210 is encapsulated in an adhesion layer 1212, which may be referred to as a shell or encapsulation shell. In one embodiment, the adhesion layer 1212 comprises a tetraethylorthosilicate (TEOS) oxide layer having a thickness on the order of 1,000 Å. In other embodiments, the thickness of the adhesion layer varies, for example, from 100 Å to 2,000 Å. Although TEOS oxide is utilized for the adhesion layer in some embodiments, other materials that provide adhesion between a subsequently deposited layer and an underlying layer or material (e.g., ceramics, particularly polycrystalline ceramics) may also be utilized in accordance with embodiments of the present invention. For example, SiO 2 or other silicon oxide (Si x O y ) adheres well to ceramic materials and provides a suitable surface for subsequent deposition of, for example, conductive materials. In some embodiments, adhesion layer 1212 completely surrounds core 1210, forming a completely encapsulated core. Adhesion layer 1212 may be formed using a low pressure chemical vapor deposition (LPCVD) process. Adhesion layer 1212 provides a surface onto which subsequent layers adhere to form elements of the engineered substrate 1200 structure.

[0060]

[0078] In addition to using LPCVD processes, furnace-based processes, and the like, to form the encapsulating first adhesion layer 1212, other semiconductor processes including CVD processes or similar deposition processes can be utilized in accordance with embodiments of the present invention. As an example, a deposition process can be utilized to coat a portion of the core, the core 1210 can be turned over, and the deposition process can be repeated to coat an additional portion of the core. Thus, while LPCVD techniques are utilized in some embodiments to provide a fully encapsulated structure, other film formation techniques can be utilized depending on the particular application.

[0061]

[0079] A conductive layer 1214 is formed surrounding the adhesion layer 1212. In one embodiment, the conductive layer 1214 is a shell of polysilicon (i.e., polycrystalline silicon) that is formed surrounding the first adhesion layer 1212 because polysilicon has poor adhesion to ceramic materials. In embodiments in which the conductive layer 1214 is polysilicon, the thickness of the polysilicon layer can be on the order of 500-5,000 Å, for example 2,500 Å. In some embodiments, the polysilicon layer can be formed as a shell to completely surround the first adhesion layer 1212 (e.g., a TEOS oxide layer), thereby forming a completely encapsulated first adhesion layer 1212, which can be formed using an LPCVD process. In other embodiments, as described below, the conductive material can be formed on a portion of the adhesion layer, for example, on the bottom half of the substrate structure. In some embodiments, the conductive material can be formed as a completely encapsulating layer and subsequently removed on one side of the substrate structure.

[0062]

[0080] In one embodiment, the conductive layer 1214 may be a polysilicon layer doped to provide a highly conductive material, for example a polysilicon layer doped with boron to provide a P-type polysilicon layer. In some embodiments, the doping with boron is on the order of 1×10 to provide high conductivity. 19 cm -3 ~1×10 20 cm -3 The level of other dopants with different dopant concentrations (e.g., 1×10 16 cm -3 ~5×10 18 cm -3 Dopant concentrations ranging from 0.1 to 1000 nm (e.g., phosphorous, arsenic, bismuth, etc.) can be utilized to provide either N-type or P-type semiconductor materials suitable for use in conductive layer 1214. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.

[0063]

[0081] The presence of conductive layer 1214 is useful in electrostatically chucking processed substrate 1200 to a semiconductor processing tool, such as a tool having an electrostatic discharge chuck (ESC). Conductive layer 1214 allows for rapid dechucking after processing in the semiconductor processing tool. Thus, embodiments of the present invention provide a substrate structure that can be processed in a manner utilized with conventional silicon wafers. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.

[0064]

[0082] A second adhesion layer 1216 (e.g., a TEOS oxide layer having a thickness on the order of 1,000 Å) is formed surrounding the conductive layer 1214. In some embodiments, the second adhesion layer 1216 completely surrounds the conductive layer 1214, forming a completely encapsulated structure. The second adhesion layer 1216 can be formed using an LPCVD process, a CVD process, or any other suitable deposition process, including deposition of a spin-on dielectric.

[0065]

[0083] A barrier layer 1218, for example a silicon nitride layer, is formed surrounding the second adhesive layer 1216. In one embodiment, the barrier layer 1218 is a silicon nitride layer with a thickness on the order of 4,000 Å to 5,000 Å. In some embodiments, the barrier layer 1218 completely surrounds the second adhesive layer 1216, forming a fully encapsulated structure, and can be formed using an LPCVD process. In addition to silicon nitride layers, amorphous materials including SiCN, SiON, AlN, SiC, etc. can be utilized as the barrier layer. In some implementations, the barrier layer is comprised of several auxiliary layers constructed to form the barrier layer. Thus, the term barrier layer is not intended to mean a single layer or material, but rather to encompass one or more materials stacked in a composite manner. One skilled in the art would recognize many variations, modifications, and alternatives.

[0066]

[0084] In some embodiments, the barrier layer 1218, e.g., a silicon nitride layer, prevents diffusion and / or outgassing of elements present in the core 1210 into the environment of a semiconductor processing chamber in which the engineered substrate 1200 may reside, e.g., during a high temperature (e.g., 1,000° C.) epitaxial growth process. Elements present in the core 1210 may include, e.g., yttrium oxide (i.e., yttria), oxygen, metallic impurities, other trace elements, and the like. Elements that diffuse out of the core 1210 may cause unintended doping of the engineered layers 1220 / 1222. Elements that are out-emitted from the core 1210 may migrate through the chamber and adsorb elsewhere on the wafer, causing impurities in the engineered layers 1220 / 1222 and epitaxial material 1230. Utilizing the encapsulation layers described herein, ceramic materials including polycrystalline AlN designed for non-cleanroom environments may be utilized in semiconductor process flows and cleanroom environments.

[0067]

[0085] A bonding layer 1220 (e.g., a silicon oxide layer) is deposited on a portion of the barrier layer 1218, e.g., on top of the barrier layer, and is subsequently used during bonding of the single crystal layer 1222. The bonding layer 1220 may be about 1.5 μm thick in some embodiments. The single crystal layer 1222 may be made of, for example, Si, SiC, sapphire, GaN, AlN, SiGe, Ge, diamond, Ga 2 O 3, AlGaN, InGaN, InN, and / or ZnO. In some embodiments, the single crystalline layer 1222 can have a thickness between 0 and 0.5 μm. The single crystalline layer 1222 is suitable for use as a growth layer during an epitaxial growth process to form the epitaxial material 1230. The crystalline layer of the epitaxial material 1230 is an extension of the underlying semiconductor lattice associated with the single crystalline layer 1222. The unique CTE matching properties of the engineered substrate 1200 allow for the growth of a thicker epitaxial material 1230 than existing technologies. In some embodiments, the epitaxial material 1230 includes a gallium nitride layer having a thickness between 2 μm and 10 μm, which can be utilized as one of multiple layers utilized in optoelectronic devices, power devices, and the like. In other embodiments, the epitaxial material 1230 can be an epitaxial structure having a thickness greater than 10 μm and including multiple epitaxial layers. In one embodiment, the bonding layer 1220 comprises a single crystal silicon layer that is attached to a silicon oxide barrier layer 1218 using a layer transfer process.

[0068]

[0086] FIG. 13 is a simplified schematic diagram illustrating an engineered substrate structure according to one embodiment of the present invention. The engineered substrate 1300 shown in FIG. 13 is suitable for a variety of electronic and optical applications. The engineered substrate includes a core 1310 that can have a coefficient of thermal expansion (CTE) that substantially matches the CTE of an epitaxial material 1230 that is grown on the engineered substrate 1300. The epitaxial material 1230 is not required as an element of the engineered substrate structure, but is shown as optional since it is typically grown on the engineered substrate structure.

[0069]

[0087] For applications involving the growth of gallium nitride (GaN) based materials (epitaxial layers including GaN based layers), the core 1310 may be a polycrystalline ceramic material, for example polycrystalline aluminum nitride (AlN). The thickness of the core 1310 may be on the order of 100-1,500 μm, for example 725 μm. The core 1310 is encapsulated in a first adhesion layer 1312, which may be referred to as a shell or encapsulation shell. In this embodiment, the first adhesion layer 1312 completely encapsulates the core, although this is not required by the invention, as will be explained in more detail with respect to FIG. 14.

[0070]

[0088] In one embodiment, the first adhesion layer 1312 comprises a tetraethylorthosilicate (TEOS) layer having a thickness on the order of 1,000 Å. In other embodiments, the thickness of the first adhesion layer 1312 varies, for example, from 100 Å to 2,000 Å. Although TEOS is utilized for the adhesion layer in some embodiments, other materials that provide adhesion between a subsequently deposited layer and the layer or material below it may also be utilized in accordance with embodiments of the present invention. For example, SiO 2 , SiON, etc., adhere well to ceramic materials and provide a suitable surface for subsequent deposition of, for example, conductive materials. In some embodiments, the first adhesion layer 1312 completely surrounds the core 1310, forming a completely encapsulated core, and may be formed using an LPCVD process. The adhesion layer 1312 provides a surface onto which subsequent layers adhere to form elements of the engineered substrate structure.

[0071]

[0089] In addition to using an LPCVD process, furnace-based process, etc. to form the encapsulating adhesion layer 1312, other semiconductor processes can be utilized in accordance with embodiments of the present invention. As an example, a deposition process, e.g., CVD, PECVD, etc., can be utilized to coat a portion of the core 1310, the core 1310 can be turned over, and the deposition process can be repeated to coat an additional portion of the core.

[0072]

[0090] A conductive layer 1314 is formed on at least a portion of the first adhesion layer 1312. In one embodiment, the conductive layer 1314 comprises polysilicon (i.e., polycrystalline silicon) formed by a deposition process on the bottom (e.g., bottom half or back side) of the core / adhesion layer structure. In embodiments in which the conductive layer 1314 is polysilicon, the thickness of the polysilicon layer may be on the order of a few thousand angstroms, for example, 3,000 Å. In some embodiments, the polysilicon layer may be formed using an LPCVD process.

[0073]

[0091] In one embodiment, the conductive layer 1314 may be a polysilicon layer that is doped to provide a highly conductive material, for example, the conductive layer 1314 may be doped with boron to provide a p-type polysilicon layer. In some embodiments, the doping with boron is about 1×10 to provide high conductivity. 19 cm -3 ~1×10 20 cm -3 The conductive layer 1314 is preferably a conductive layer having a thickness in the range of 0.1 to 100 nm. The presence of the conductive layer 1314 is useful in electrostatically chucking a processed substrate to a semiconductor processing tool, such as a tool having an electrostatic chuck (ESC). The conductive layer 1314 allows for rapid dechucking after processing. Thus, embodiments of the present invention provide a substrate structure that can be processed in the manner utilized with conventional silicon wafers. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.

[0074]

[0092] A second adhesive layer 1316 (e.g., a second TEOS layer) is formed to surround the conductive layer 1314 (e.g., a polysilicon layer). The thickness of the second adhesive layer 1316 is on the order of 1,000 Å. In some embodiments, the second adhesive layer 1316 can completely surround the conductive layer 1314, similar to the first adhesive layer 1312, to form a fully encapsulated structure, and can be formed using an LPCVD process. In other embodiments, the second adhesive layer 1316 only partially surrounds the conductive layer 1314, for example, terminating at a location indicated by a plane 1317 that can be aligned with a top surface of the conductive layer 1314. In this example, the top surface of the conductive layer 1314 contacts a portion of the barrier layer 1318. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.

[0075]

[0093] A barrier layer 1318 (e.g., a silicon nitride layer) is formed surrounding the second adhesion layer 1316. In some embodiments, the barrier layer 1318 has a thickness on the order of 4,000 Å to 5,000 Å. In some embodiments, the barrier layer 1318 completely surrounds the second adhesion layer 1316, forming a completely encapsulated structure, and may be formed using an LPCVD process.

[0076]

[0094] In some embodiments, the use of a silicon nitride barrier layer prevents elements present in the core 1310, such as yttrium oxide (i.e., yttria), oxygen, metallic impurities, and other trace elements, from diffusing and / or outgassing into the environment of a semiconductor processing chamber in which a fabricated substrate may reside, for example, during a high temperature (e.g., 1,000° C.) epitaxial growth process. Utilizing the encapsulation layers described herein, ceramic materials including polycrystalline AlN designed for non-cleanroom environments can be utilized in semiconductor process flows and cleanroom environments.

[0077]

[0095] FIG. 14 is a simplified schematic diagram illustrating an engineered substrate structure according to another embodiment of the present invention. In the embodiment shown in FIG. 14, a first adhesive layer 1412 is formed over at least a portion of the core 1410, but does not encapsulate the core 1410. In this implementation, the first adhesive layer 1412 is formed on the underside of the core 1410 (the backside of the core 1410) to enhance adhesion of a subsequently formed conductive layer 1414, as described more fully below. Although the adhesive layer 1412 is only shown on the underside of the core 1410 in FIG. 14, it will be understood that deposition of adhesive layer material on other portions of the core 1410 will not adversely affect the performance of the engineered substrate structure, and such material may be present in various embodiments. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0078]

[0096] The conductive layer 1414 does not encapsulate the first adhesive layer 1412 and the core 1410, but is substantially aligned with the first adhesive layer 1412. The conductive layer 1414 is illustrated as extending along a portion of the bottom or back and sides of the first adhesive layer 1412, but extension along the vertical sides is not required by the present invention. Thus, embodiments may utilize deposition on one side of the substrate structure, masking of one side of the substrate structure, and the like. The conductive layer 1414 may be formed on one side of the first adhesive layer 1412, e.g., a portion of the bottom / back side. The conductive layer 1414 provides electrical conduction on one side of the engineered substrate structure, which may be advantageous in RF and high power applications. The conductive layer 1414 may include doped polysilicon as described with respect to the conductive layer 1314 of FIG. 13.

[0079]

[0097] A portion of the core 1410, a portion of the first adhesive layer 1412, and the conductive layer 1414 are covered with a second adhesive layer 1416 to enhance adhesion to the material underlying the barrier layer 1418. The barrier layer 1418 forms an encapsulation structure to prevent diffusion from the underlying layers, as described above.

[0080]

[0098] In addition to semiconductor-based conductive layers, in other embodiments, conductive layer 1414 is a metal layer, such as 500 Å of titanium.

[0081]

[0099] Referring again to FIG. 14, depending on the implementation, one or more layers may be removed. For example, layers 1412, 1414 may be removed leaving only a single adhesion shell 1416 and barrier layer 1418. In another embodiment, only layer 1414 may be removed. In this embodiment, layer 1412 may also balance the stress and wafer warpage caused by layer 1220, deposited on top of layer 1418. Building a substrate structure with an insulating layer on top of core 1410 (e.g., with only an insulating layer between core 1410 and layer 1220) would benefit power / RF applications where a highly insulating substrate is desired.

[0082]

[0100] In another embodiment, the barrier layer 1418 may directly encapsulate the core 1410, followed by the conductive layer 1414, followed by the adhesive layer 1416. In this embodiment, the layer 1220 may be deposited directly onto the adhesive layer 1416 from the top. In yet another embodiment, the adhesive layer 1416 may be deposited onto the core 1410, followed by the barrier layer 1418, then the conductive layer 1414, and then another adhesive layer 1412.

[0083]

[0101] FIG. 15 is a simplified flow chart illustrating a method 1500 of fabricating an engineered substrate according to an embodiment of the present invention. The method 1500 can be utilized to fabricate a substrate that is CTE-matched to one or more of the epitaxial layers grown on the substrate. The method 1500 includes forming a support structure by providing a polycrystalline ceramic core (1510), encapsulating the polycrystalline ceramic core in a first adhesion layer that forms a shell (e.g., a tetraethylorthosilicate (TEOS) oxide shell) (1512), and encapsulating the first adhesion layer in a conductive shell (e.g., a polysilicon shell) (1514). The first adhesion layer can be formed as a monolayer of TEOS oxide. The conductive shell can be formed as a monolayer of polysilicon.

[0084]

[0102] The method 1500 also includes encapsulating 1516 the conductive shell in a second adhesion layer (e.g., a second TEOS oxide shell) and encapsulating 1518 the second adhesion layer in a barrier layer shell. The second adhesion layer can be formed as a single layer of TEOS oxide. The barrier layer shell can be formed as a single layer of silicon nitride.

[0085]

[0103] Once the support structure is formed by processes 1510-1518, the method 1500 further includes bonding 1520 a bonding layer (e.g., a silicon oxide layer) to the support structure and bonding 1522 a substantially single crystalline layer, e.g., a single crystalline silicon layer, to the silicon oxide layer. According to an embodiment of the invention, SiC, sapphire, GaN, AlN, SiGe, Ge, diamond, Ga 2 O 3 Other substantially single crystalline layers can be used, including SiO, ZnO, etc. Bonding the bonding layer can include deposition of the bonding material followed by a planarization process as described herein. In embodiments described below, bonding the substantially single crystalline layer (e.g., a single crystalline silicon layer) to the bonding layer utilizes a layer transfer process, where the layer is a single crystalline silicon layer that is transferred from a silicon wafer.

[0086]

[0104] With reference to FIG. 12, the bonding layer 1220 can be formed by depositing a thick (e.g., 4 μm thick) oxide layer followed by a chemical mechanical polishing (CMP) process that thins the oxide to a thickness of about 1.5 μm. The thick initial oxide helps fill voids and surface features present on the support structure that may be present after fabrication of the polycrystalline core and may continue to be present when the encapsulation layer shown in FIG. 12 is formed. The oxide layer also serves as a dielectric layer for the device. The CMP process provides a substantially planar surface free of voids, particles, or other features that can be used during a wafer transfer process to bond a monocrystalline layer 1222 (e.g., a monocrystalline silicon layer) to the bonding layer 1220. It will be appreciated that the bonding layer need not be characterized by an atomically flat surface, but should provide a substantially planar surface that will support bonding of the monocrystalline layer (e.g., a monocrystalline silicon layer) with the desired reliability.

[0087]

[0105] A layer transfer process is used to bond the monocrystalline layer 1222 (e.g., a monocrystalline silicon layer) to the bonding layer 1220. In some embodiments, a silicon wafer including a substantially monocrystalline layer 1222 (e.g., a monocrystalline silicon layer) is implanted to form a cleavage plane. In this embodiment, after wafer bonding, the silicon substrate can be removed along with the portion of the monocrystalline silicon layer below the cleavage plane, resulting in a delaminated monocrystalline silicon layer. The thickness of the monocrystalline layer 1222 can be varied to meet various application specifications. Additionally, the crystal orientation of the monocrystalline layer 1222 can be varied to meet application specifications. Additionally, the doping level and profile in the monocrystalline layer can be varied to meet the specific application specifications. In some embodiments, the depth of the implant can be adjusted to be greater than the desired final thickness of the monocrystalline layer 1222. The additional thickness allows for removal of thin portions of the transferred substantially monocrystalline layer that are damaged, leaving undamaged portions of the desired final thickness. In some embodiments, the surface roughness can be modified for high quality epitaxial growth. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.

[0088]

[0106] In some embodiments, the monocrystalline layer 1222 can be thick enough to provide a high quality lattice template for the subsequent growth of one or more epitaxial layers, but thin enough to be highly compliant. The monocrystalline layer 1222 is said to be "compliant" when it is relatively thin so that its physical properties are less constrained and can mimic those properties of the material that surrounds it with less tendency to develop crystalline defects. The compliance of the monocrystalline layer 1222 can be inversely proportional to the thickness of the monocrystalline layer 1222. The higher the compliance, the lower the defect density of the epitaxial layer grown on the template, allowing for the growth of a thicker epitaxial layer. In some embodiments, the thickness of the monocrystalline layer 1222 can be increased by epitaxially growing silicon on an exfoliated silicon layer.

[0089]

[0107] In some embodiments, tailoring the final thickness of the single crystal layer 1222 can be achieved by thermal oxidation of the top of the exfoliated silicon layer, followed by stripping of the oxide layer with hydrofluoric (HF) acid. For example, an exfoliated silicon layer with an initial thickness of 0.5 μm can be thermally oxidized to form a silicon dioxide layer with a thickness of about 420 nm. After removing the grown thermal oxide, the remaining silicon thickness in the transfer layer can be about 53 nm. During thermal oxidation, the implanted hydrogen can migrate toward the surface. Thus, the subsequent stripping of the oxide layer can remove some damage. Also, thermal oxidation is usually performed at temperatures above 1000° C. Lattice damage can be repaired even at high temperatures.

[0090]

[0108] The silicon oxide layer formed on top of the single crystal layer during thermal oxidation can be stripped using HF acid etching. 2The etch selectivity between the SiO2:Si) can be adjusted by adjusting the temperature and concentration of the HF solution as well as the stoichiometry and density of the silicon oxide. Etch selectivity refers to the etch rate of one material relative to another. The selectivity of the HF solution can range from about 10:1 to about 100:1 relative to (SiO2:Si). High etch selectivity can reduce the surface roughness by a similar factor from the initial surface roughness. However, the surface roughness of the resulting single crystal layer 1222 can still be greater than desired. For example, a bulk Si(111) surface may have a root mean square (RMS) surface roughness of less than 0.1 nm as determined by a 2 μm×2 μm atomic force microscope (AFM) scan before additional processing. In some embodiments, the desired surface roughness for epitaxial growth of gallium nitride material on Si(111) can be, for example, less than 1 nm, less than 0.5 nm, or less than 0.2 nm over a 30 μm×30 μm AFM scan area.

[0091]

[0109] If the surface roughness of the single crystal layer 1222 after thermal oxidation and oxide layer stripping exceeds the desired surface roughness, additional surface smoothing can be performed. There are several methods for smoothing silicon surfaces. These methods can include hydrogen annealing, laser trimming, plasma smoothing, and touch polishing (e.g., CMP). These methods may include preferential attack of high aspect ratio surface peaks. Thus, high aspect ratio features on the surface can be removed more quickly than low aspect ratio features, thus resulting in a smoother surface.

[0092]

[0110] It should be understood that the specific steps illustrated in FIG. 15 provide a particular method of manufacturing an engineered substrate according to one embodiment of the present invention. Other sequences of steps may be performed according to alternative embodiments. For example, alternative embodiments of the present invention may perform the steps outlined above in a different order. Additionally, individual steps illustrated in FIG. 15 may include multiple sub-steps that may be performed in various orders as appropriate for the individual step. Additionally, additional steps may be added or removed depending on the particular application. Those skilled in the art will recognize numerous variations, modifications, and alternatives.

[0093]

[0111] 16 is a simplified flow chart illustrating a method 1600 for fabricating a multi-layer device on an engineered substrate according to some embodiments of the present invention. The engineered substrate has a substrate thermal expansion coefficient. With reference to FIGS. 1 and 2, the engineered substrate 102 can include a ceramic substrate 110 having a thin silicon (Si) layer 120 or a thin silicon germanium (SiGe) layer 220 formed thereon.

[0094]

[0112] 1, 2, and 16, a method 1600 can include growing (1602) a buffer layer 130 on an engineered substrate 102 and growing (1604) a first epitaxial layer 142 coupled to the buffer layer 130. The first epitaxial layer 142 can be characterized by an epitaxial thermal expansion coefficient substantially equal to a substrate thermal expansion coefficient. In some embodiments, the first epitaxial layer 142 can include doped gallium nitride (GaN). With reference to FIG. 6, in some other embodiments, the first epitaxial layer 142 can include aluminum gallium nitride (AlGaN).

[0095]

[0113] The method 1600 may further include growing a second epitaxial layer 144 including undoped GaN coupled to the first epitaxial layer 142, and growing a third epitaxial layer 160 coupled to the second epitaxial layer 144. The interface between the second epitaxial layer 144 and the third epitaxial layer 160 may form a conduction channel 150 of a high electron mobility transistor (HEMT). In some embodiments, the third epitaxial layer 160 may include aluminum gallium nitride (AlGaN) or indium aluminum nitride (InAlN).

[0096]

[0114] With reference to FIG. 3 , in some embodiments, the method 1600 may further include forming an electrical contact 310 electrically coupled to the substantially single crystalline layer 120 through the engineered substrate 102. With reference to FIG. 4 , in some other embodiments, the method 1600 may further include growing a conductive epitaxial layer 420 disposed between the buffer layer 130 and the first epitaxial layer 142, and forming an electrical contact 410 electrically coupled to the conductive epitaxial layer 420 through the first epitaxial layer 142. With reference to FIG. 5 , in some embodiments, the method 1600 may further include growing a silicon nitride (SiN) layer 420 disposed between the buffer layer 130 and the conductive epitaxial layer 420. 3 N 4 ) may further include forming a partial monolayer 510 of

[0097]

[0115] It should be understood that the specific steps illustrated in FIG. 16 provide a particular method of manufacturing an engineered substrate according to one embodiment of the present invention. Other sequences of steps may be performed according to alternative embodiments. For example, alternative embodiments of the present invention may perform the steps outlined above in a different order. Additionally, individual steps illustrated in FIG. 16 may include multiple sub-steps that may be performed in various orders as appropriate for the individual step. Additionally, additional steps may be added or removed depending on the particular application. Those skilled in the art will recognize numerous variations, modifications, and alternatives.

[0098]

[0116] 17 is a simplified flow chart illustrating a method 1700 for fabricating a multi-layer device on an engineered substrate according to some other embodiments of the present invention. The engineered substrate has a substrate thermal expansion coefficient. Referring to FIG. 7, the engineered substrate 102 can include a ceramic substrate 110 having a thin silicon (Si) layer 120 formed thereon.

[0099]

[0117] 7 and 17, the method 1700 can include forming a buffer layer 130 on a processed substrate 102 (1702) and growing one or more epitaxial layers 740 on the buffer layer 130 (1704). At least one of the one or more epitaxial layers 740 is characterized by an epitaxial thermal expansion coefficient substantially equal to a substrate thermal expansion coefficient. In some embodiments, the one or more epitaxial layers 740 can include a superlattice of alternating layers of undoped GaN and doped GaN. The doped GaN can include carbon doped GaN (C-GaN) or iron doped GaN (Fe-GaN). The buffer layer 130 can include at least one of AlN, AlGaN, or AlN / AlGaN.

[0100]

[0118] The method 1700 may further include growing an undoped GaN layer 144 bonded to the one or more epitaxial layers 740, and growing a first epitaxial layer 160 comprising aluminum gallium nitride (AlGaN) or indium aluminum nitride (InAlN) bonded to the undoped GaN layer 144. The interface between the undoped GaN layer 144 and the first epitaxial layer 160 may form a conduction channel 150 of a high electron mobility transistor (HEMT).

[0101]

[0119] It should be understood that the specific steps illustrated in FIG. 17 provide a particular method of manufacturing an engineered substrate according to one embodiment of the present invention. Other sequences of steps may be performed according to alternative embodiments. For example, alternative embodiments of the present invention may perform the steps outlined above in a different order. Additionally, individual steps illustrated in FIG. 17 may include multiple sub-steps that may be performed in various orders as appropriate for the individual step. Additionally, additional steps may be added or removed depending on the particular application. Those skilled in the art will recognize numerous variations, modifications, and alternatives.

[0102]

[0120] 18 is a simplified flow chart illustrating a method 1800 for fabricating a multi-layer device on an engineered substrate according to some further embodiments of the present invention. The engineered substrate has a substrate thermal expansion coefficient. Referring to FIG. 8, the engineered substrate 102 can include a ceramic substrate 110 having a thin silicon (Si) layer 120 formed thereon.

[0103]

[0121] 8 and 18, the method 1800 can include forming (1802) a buffer layer 130 on the engineered substrate 102 and growing (1804) a first epitaxial layer 840 coupled to the buffer layer 130. The first epitaxial layer 840 can be characterized by an epitaxial thermal expansion coefficient substantially equal to a substrate thermal expansion coefficient. In some embodiments, the first epitaxial layer 840 can include unintentionally doped GaN (UID-GaN). In some other embodiments, the first epitaxial layer 840 can include alternating layers of undoped GaN and doped GaN. In some embodiments, the doped GaN can include carbon doped GaN (C-GaN) or iron doped GaN (Fe-GaN).

[0104]

[0122] The method 1800 may further include growing (1806) an aluminum gallium nitride (AlGaN) back barrier layer 810 coupled to the first epitaxial layer 840, growing (1808) an undoped gallium nitride (GaN) layer 144 coupled to the AlGaN back barrier layer 810, and growing (1810) a barrier layer 160 coupled to the undoped GaN layer 144. In some embodiments, the AlGaN back barrier layer 810 has an aluminum mole fraction in the range of about 3% to about 15%. According to some embodiments, the barrier layer 160 may include AlGaN or InGaN.

[0105]

[0123] It should be understood that the specific steps illustrated in FIG. 18 provide a particular method of manufacturing an engineered substrate according to one embodiment of the present invention. Other sequences of steps may be performed according to alternative embodiments. For example, alternative embodiments of the present invention may perform the steps outlined above in a different order. Additionally, individual steps illustrated in FIG. 18 may include multiple sub-steps that may be performed in various orders as appropriate for the individual step. Additionally, additional steps may be added or removed depending on the particular application. Those skilled in the art will recognize numerous variations, modifications, and alternatives.

[0106]

[0124] Although some embodiments have been discussed in terms of layers, it should be understood that the term layer can include several sub-layers that are constructed to form the layer of interest. Thus, the term layer does not mean a single layer of a single material, but is intended to encompass one or more materials that are compositely layered to form a desired structure. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0107]

[0125] Additionally, the examples and embodiments described herein are for illustrative purposes only, and various modifications or changes will be suggested to those skilled in the art in light thereof, which should be included within the spirit and scope of this application and the scope of the appended claims.

Claims

1. A processed substrate having a substrate thermal expansion coefficient, the processed substrate comprising: A polycrystalline ceramic core; a barrier layer encapsulating the polycrystalline ceramic core; a bonding layer bonded to the barrier layer; a single crystal silicon carbide (SiC) layer bonded to the bonding layer; and an epitaxial layer bonded to the single crystal SiC layer, the epitaxial layer being characterized by an epitaxial thermal expansion coefficient substantially equal to the substrate thermal expansion coefficient; 1. An epitaxial semiconductor structure comprising:

2. 10. The epitaxial semiconductor structure of claim 1, wherein the epitaxial layer comprises gallium nitride (GaN).

3. 3. The epitaxial semiconductor structure of claim 2, wherein the GaN comprises unintentionally doped GaN.

4. The epitaxial semiconductor structure of claim 1 , wherein the epitaxial layer comprises one or more doped gallium nitride (GaN) layers.

5. The epitaxial semiconductor structure of claim 4 , wherein the one or more doped GaN layers comprises an n-type GaN layer.

6. The epitaxial semiconductor structure of claim 4 , wherein the one or more doped GaN layers comprises a p-type GaN layer.

7. 10. The epitaxial semiconductor structure of claim 1, wherein the epitaxial layer comprises one or more layers of undoped GaN and n-type GaN.

8. 10. The epitaxial semiconductor structure of claim 1, wherein the epitaxial layer comprises one or more layers of undoped GaN and p-type GaN.

9. 10. The epitaxial semiconductor structure of claim 1, wherein the epitaxial layer comprises one or more layers of undoped GaN, n-type GaN, and p-type GaN.

10. 2. The epitaxial semiconductor structure of claim 1, wherein said single crystal SiC layer and said epitaxial layer are substantially lattice matched.

11. 10. The epitaxial semiconductor structure of claim 1 further comprising a buffer layer disposed between said single crystal SiC layer and said epitaxial layer.

12. 12. The epitaxial semiconductor structure of claim 11 further comprising a silicon nitride layer disposed between said buffer layer and said epitaxial layer.

13. 10. The epitaxial semiconductor structure of claim 1, wherein the epitaxial layers comprise alternating layers of undoped gallium nitride (GaN) and doped GaN.

14. 14. The epitaxial semiconductor structure of claim 13, wherein the doped GaN comprises carbon-doped GaN (C-GaN) or iron-doped GaN (Fe-GaN).

15. 2. The epitaxial semiconductor structure of claim 1, wherein the epitaxial layer comprises: a doped gallium nitride (GaN) layer; and an undoped GaN layer; The epitaxial semiconductor structure comprises: a buffer layer disposed between the single crystal SiC layer and the epitaxial layer; an aluminum gallium nitride (AlGaN) layer coupled to the epitaxial layer; a cap layer.

16. 10. The epitaxial semiconductor structure of claim 1, wherein the epitaxial layer comprises an aluminum gallium nitride (AlGaN) layer.

17. 10. The epitaxial semiconductor structure of claim 1, wherein the AlGaN layer has an aluminum mole fraction of less than 10%.

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