Control device

Abstract

To provide a technique capable of generating sampling data corresponding to each IED in an MU connected to each IED which provides a different sampling synchronous signal.SOLUTION: A control device comprises a sampling signal generator, an analog / digital converter, and a memory. A sampling period of a sampling signal is shorter than a first allowable error time, which is allowed with respect to synchronism timing indicated by a first synchronous signal, and a second allowable error time which is allowed with respect to synchronism timing indicated by a second synchronous signal. The control device further comprises: a first extraction section for extracting digital data, which are sampled in the closest timing to the synchronism timing indicated by the first synchronous signal, from among digital data stored in the memory; and a second extraction section for extracting digital data which are sampled in the closest timing to the synchronism timing indicated by the second synchronous signal, from among the digital data.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present disclosure relates to a control device. [Background technology]

[0002] In recent years, protection and control systems that support process buses are becoming more common as a form of protective relay equipment. In this protection and control system, the functions of a conventional protective relay equipment are divided into two, each of which is configured as an individual unit.

[0003] Specifically, a data collection control device that acquires electrical quantities, called a Merging Unit (MU), and a protection control device called an IED (Intelligent Electronic Device), are provided. The MU receives detection signals of electrical quantities (i.e., current, voltage, etc.) in the power system and converts the received signals to analog to digital (AD). The MU transmits data obtained by AD conversion to the IED via a process bus. The IED performs relay calculations based on the data received from the MU. The MU and IED adopt a synchronization method such as the IEEE1588 standard so that sampling synchronization can be achieved on a per-electrical-station basis.

[0004] Patent Document 1 (JP Patent Publication 2000-59980A) discloses a digital protection control device. This digital protection control device samples an electric signal representing the state of a power system at a sampling period shorter than a protection calculation period, converts it into digital data, and stores it. For each protection calculation period, prior to the execution of a protection control calculation, it reads out a plurality of sampling data sampled during a period corresponding to the protection calculation period, and executes a filter processing calculation followed by a protection control calculation within the same calculation period. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2000-59980 A Summary of the Invention [Problem to be solved by the invention]

[0006] To ensure reliability in maintenance and operation, IEDs (for example, IEDs for busbar protection) are often duplicated. Since the sampling synchronization timing of redundant IEDs differs for each system, the MUs connected via the process bus are also duplicated.

[0007] For example, an MU for system a connected to an IED for system a via a process bus for system a performs sampling according to a sampling synchronization signal provided by the IED for system a. An MU for system b connected to an IED for system b via a process bus for system b performs sampling according to a sampling synchronization signal provided by the IED for system b. As a result, MUs cannot be shared between systems a and b, which makes it difficult to reduce hardware construction costs.

[0008] In Patent Document 1, the electrical signal is sampled at a sampling period shorter than the protection calculation period, but does not disclose or suggest any means for solving the above problems.

[0009] An object of one aspect of the present disclosure is to provide a technique that enables an MU connected to IEDs that provide different sampling synchronization signals to generate sampling data corresponding to each IED. [Means for solving the problem]

[0010] A control device according to an embodiment includes a sampling signal generator that generates a sampling signal, an analog-to-digital converter that samples an electrical quantity of a power system based on the sampling signal and performs analog-to-digital conversion, and a memory that sequentially stores digital data of the electrical quantity output from the analog-to-digital converter. A sampling period of the sampling signal is shorter than a first allowable error time allowed for a synchronization timing indicated by a first synchronization signal and a second allowable error time allowed for a synchronization timing indicated by a second synchronization signal. The control device further includes a first extraction unit that extracts digital data sampled at a timing closest to the synchronization timing indicated by the first synchronization signal from each digital data stored in the memory, and a second extraction unit that extracts digital data sampled at a timing closest to the synchronization timing indicated by the second synchronization signal from each digital data stored in the memory. Effect of the Invention

[0011] According to the present disclosure, in the MU connected to each IED that provides a different sampling synchronization signal, sampling data corresponding to each IED can be generated. [Brief description of the drawings]

[0012] [Figure 1] FIG. 2 is a diagram showing the overall configuration of a protection and control system according to a first comparative example. [Diagram 2] 11 is a diagram for explaining a method for generating data after AD conversion according to Comparative Example 1. FIG. [Diagram 3] 1 is a diagram showing an overall configuration of a protection and control system according to a first embodiment. [Figure 4] FIG. 2 is a diagram for explaining a method of generating AD converted data according to the first embodiment. [Diagram 5] 2 is a block diagram showing an example of a hardware configuration of an MU and an IED according to the first embodiment. FIG. [Figure 6] FIG. 2 is a diagram illustrating an example of the functional configuration of an MU. [Figure 7]FIG. 1 is a diagram for explaining a first embodiment. [Figure 8] FIG. 11 is a diagram for explaining a second embodiment. [Figure 9] FIG. 11 is a diagram for explaining a third embodiment. [Figure 10] FIG. 13 is a diagram for explaining the configuration of a fourth embodiment. [Figure 11] FIG. 11 is a diagram showing the overall configuration of a protection and control system according to Comparative Example 2. [Figure 12] FIG. 11 is a diagram for explaining a system switching method according to a second comparative example. [Figure 13] FIG. 11 is a diagram for explaining a system switching method according to a second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, the present embodiment will be described with reference to the drawings. In the following description, the same components are denoted by the same reference numerals. Their names and functions are also the same. Therefore, detailed description thereof will not be repeated.

[0014] <Overall configuration of Comparative Example 1> In order to facilitate understanding of the protection and control system according to the present embodiment, first, the configuration of a protection and control system according to a first comparative example will be described.

[0015] Fig. 1 is a diagram showing an overall configuration of a protection and control system 1100 according to Comparative Example 1. Referring to Fig. 1, the protection and control system 1100 includes IEDs 10a and 10b, process buses 100a and 100b, a plurality of MUs 200a, and a plurality of MUs 200b. For example, the protection and control system 1100 includes 30 MUs 200a and 30 MUs 200b.

[0016] For convenience, the 30 MUs 200a are assigned #a1 to #a30 to be distinguished from one another. The 30 MUs 200b are assigned #b1 to #b30 to be distinguished from one another. MU 200a includes an AD conversion circuit 390a. The AD conversion circuit 390a includes a sampling signal generator 310a and an AD converter 320a. MU 200b includes an AD conversion circuit 390b. The AD conversion circuit 390b includes a sampling signal generator 310b and an AD converter 320b.

[0017] The IED 10a is communicatively connected to MUs #a1 to #a30 via a process bus 100a. The IED 10b is communicatively connected to MUs #b1 to #b30 via a process bus 100b. The IED 10a functions as a master station of the a system (hereinafter also referred to as a "synchronization master station") that transmits a synchronization packet Ka of the a system conforming to the IEEE 1588 standard. Similarly, the IED 10b functions as a synchronization master station of the b system that transmits a synchronization packet Kb of the b system conforming to the IEEE 1588 standard. Note that the synchronization packet may be provided from a high-precision clock device instead of the IED. In this case, the high-precision clock device functions as the synchronization master station.

[0018] The MU 200a receives a synchronization packet Ka from the IED 10a via the process bus 100a, and the MU 200b receives a synchronization packet Kb from the IED 10b via the process bus 100b.

[0019] The MU 200a determines the synchronous timing Ta of sampling according to the synchronous signal included in the synchronous packet Ka. The sampling signal generator 310a of the MU 200a generates a sampling signal Sa according to the synchronous timing Ta. The AD converter 320a samples the electric quantity of the power system based on the sampling signal Sa and performs AD conversion. Data Da, which is digital data after AD conversion (i.e., sampling data), is stored sequentially in the internal memory. The MU 200a transmits an SV (Sampled Value) packet including the data Da to the IED 10a of the a system.

[0020] The MU 200b determines the synchronous timing Tb of sampling according to the synchronous signal included in the synchronous packet Kb. The sampling signal generator 310b of the MU 200b generates a sampling signal Sb according to the synchronous timing Tb. The AD converter 320b samples the amount of electricity in the power system based on the sampling signal Sb and performs AD conversion. The data Db after AD conversion is stored sequentially in the internal memory. The MU 200b transmits an SV packet including the data Db to the IED 10b of the b system.

[0021] Next, a method for generating data Da by MU 200a and a method for generating data Db by MU 200b will be specifically described.

[0022] FIG. 2 is a diagram for explaining a method of generating data after AD conversion according to Comparative Example 1. Here, the frequency of the a-system synchronization signal (hereinafter also referred to as "synchronization frequency") Fa and the b-system synchronization frequency Fb are assumed to be 4800 Hz, which is an example described in the IEC 61869 standard. ΔTab indicates a synchronization error (i.e., sampling timing error time) between the a-system synchronization timing Ta and the b-system synchronization timing Tb. ΔTa (for example, 10 μsec) indicates a time allowed as an error time of a process of performing AD conversion from the synchronization timing Ta (hereinafter also referred to as "allowable error time"). That is, a period of ±ΔTa with respect to the synchronization timing Ta is allowed as an AD conversion error time. Similarly, ΔTb indicates an allowable error time allowed with respect to the synchronization timing Tb.

[0023] 2, AD conversion circuit 390a of MU 200a sequentially stores in its internal memory data Da#1-#5 obtained by sampling the amount of electricity according to synchronization timing Ta. AD conversion circuit 390b of MU 200b sequentially stores in its internal memory data Db#1-#5 obtained by sampling the amount of electricity according to synchronization timing Tb.

[0024] As described above, there is a synchronization error ΔTab between the synchronization timing Ta of the a system and the synchronization timing Tb of the b system, and sampling must be performed to satisfy the allowable error times ΔTa, ΔTb. Therefore, in Comparative Example 1, the AD conversion circuit 390a dedicated to the a system in MU 200a generates data Da that conforms to the synchronization timing Ta (specifically, that satisfies the allowable error time ΔTa). The AD conversion circuit 390b dedicated to the b system in MU 200b generates data Db that conforms to the synchronization timing Tb (specifically, that satisfies the allowable error time ΔTb).

[0025] However, in Comparative Example 1, the a-system and the b-system cannot share the MU (specifically, the AD conversion circuit), making it difficult to reduce the hardware construction cost.

[0026] Embodiment 1 <Overall composition> Fig. 3 is a diagram showing an overall configuration of a protection and control system 1000 according to the first embodiment. With reference to Fig. 3, the protection and control system 1000 includes IEDs 10a and 10b, process buses 100a and 100b, and a plurality of MUs 20. For example, the protection and control system 1000 includes 30 MUs 20. For convenience, the 30 MUs 20 are numbered #1 to #30 to be distinguished from one another. The 30 MUs 20 are also referred to as MU #1 to #30, respectively. Each MU 20 includes a sampling signal generator 31 and an AD converter 32.

[0027] IED 10a is communicatively connected to MU #1 to #30 via a process bus 100a. IED 10b is communicatively connected to MU #1 to #30 via a process bus 100b. IED 10a functions as a synchronization master station of the a system that transmits synchronization packet Ka, and IED 10b functions as a synchronization master station of the b system that transmits synchronization packet Kb.

[0028] Each MU 20 receives a synchronization packet Ka from the IED 10a via the process bus 100a, and receives a synchronization packet Kb from the IED 10b via the process bus 100b. The MU 20 determines the synchronization timing Ta of sampling in accordance with the synchronization signal included in the synchronization packet Ka, and determines the synchronization timing Tb of sampling in accordance with the synchronization signal included in the synchronization packet Kb.

[0029] The sampling signal generator 31 of MU 20 does not generate a sampling signal according to the synchronization timings Ta and Tb, but generates a sampling signal Sx at a timing inside MU 20. The sampling period Tx of the sampling signal Sx is set to be shorter than the allowable error time ΔTa allowed for the synchronization timing Ta, and shorter than the allowable error time ΔTb allowed for the synchronization timing Tb. Therefore, compared with the synchronization frequency of IEDs 10a and 10b (e.g., 4800 Hz), the sampling frequency Fx (i.e., Fx=1 / Tx) of the sampling signal Sx is a very high frequency (e.g., 230.4 kHz).

[0030] The AD converter 32 of the MU 20 samples the electrical quantity of the power system based on the sampling signal Sx and performs AD conversion. Data Dx, which is digital data after AD conversion, is stored sequentially in the internal memory.

[0031] The MU 20 extracts data Dxa sampled at the timing closest to the synchronization timing Ta from each piece of data Dx stored in the internal memory. The MU 20 also extracts data Dxb sampled at the timing closest to the synchronization timing Tb from each piece of data Dx stored in the internal memory. The MU 20 then transmits an SV packet including the data Dxa to the IED 10a of the a system, and transmits an SV packet including the data Dxb to the IED 10b of the b system.

[0032] Next, a method for generating data Dxa and Dxb by MU 20 according to the present embodiment will be specifically described.

[0033] Fig. 4 is a diagram for explaining a method of generating AD converted data according to the first embodiment. In the example of Fig. 4, the a-system synchronous frequency Fa and the b-system synchronous frequency Fb are 4800 Hz. The definitions of ΔTab, ΔTa, and ΔTb are the same as those explained in Fig. 2. Tx indicates the sampling period of the sampling signal Sx.

[0034] 4, the AD conversion circuit 39 of the MU 20 sequentially stores in an internal memory AD-converted data Dx#0-#15 obtained by sampling an electrical quantity every sampling period Tx. As described above, the sampling period Tx is set to be shorter than the allowable error time ΔTa (i.e., Tx<ΔTa) and shorter than the allowable error time ΔTb (i.e., Tx<ΔTb). Therefore, among the data Dx, there is data Dx that satisfies the allowable error time ΔTa of the synchronization timing Ta, and there is also data Dx that satisfies the allowable error time ΔTb of the synchronization timing Tb.

[0035] Specifically, MU20 extracts, as data Dxa, each of data Dx#3 and #12 sampled at the timing closest to synchronization timing Ta from data Dx#0 to #15 stored in the internal memory of AD conversion circuit 39. MU20 extracts, as data Dxb, each of data Dx#1 and #9 sampled at the timing closest to synchronization timing Tb from data Dx#0 to #15.

[0036] The MU 20 transmits an SV packet including each piece of data Dxa (for example, data Dx#3, #12) to the IED 10a, and transmits an SV packet including each piece of data Dxb (for example, data Dx#1, #9) to the IED 10b.

[0037] Thus, unlike generating sampling data according to the synchronization timing provided from each IED10a, 10b, the MU20 according to Embodiment 1 generates sampling data (e.g., data Dx) by its own high-speed sampling. Then, the MU20 extracts sampling data that matches each synchronization timing from among the respective sampling data, and transmits the extracted sampling data to each of the IEDs10a, 10b.

[0038] Accordingly, in the MU20 according to Embodiment 1, unlike in Comparative Example 1, it is not necessary to provide a dedicated AD conversion circuit for each of the plurality of synchronization signals provided from the plurality of IEDs10a, 10b, and sampling data according to each synchronization timing can be generated in one AD conversion circuit. Therefore, as compared with Comparative Example 1, the number of MU20s (specifically, AD conversion circuits) can be reduced, and thus the hardware construction cost can be reduced. In particular, since the cost of the hardware portion of the AD conversion circuit in the MU is large as compared with other hardware portions, a significant cost reduction is possible.

[0039] <Hardware Configuration of MU and IED> FIG. 5 is a block diagram showing an example of the hardware configuration of the MU20 and the IED10 according to Embodiment 1. The IED10 corresponds to the IED10a or IED10b shown in FIG. 3.

[0040] (MU) Referring to FIG. 5, the MU20 includes an auxiliary transformer 151 for input conversion, an AD conversion circuit 39, a processing circuit 154, a communication circuit 155, and a digital output circuit 156.

[0041] A plurality of channels are provided in the MU20 to receive the current signals of each phase output from the corresponding current transformer and the voltage signals of each phase output from the corresponding voltage transformer. The current signal of each phase from the corresponding current transformer and the voltage signal of each phase from the corresponding voltage transformer are respectively input to each channel.

[0042] The auxiliary transformer 151 receives the current signal from the current transformer or the voltage signal from the voltage transformer, and converts the received voltage signal or current signal into a signal with a voltage level suitable for signal processing in the AD conversion circuit 39 and the processing circuit 154. The auxiliary transformer 151 may be an isolated voltage dividing resistor.

[0043] The AD conversion circuit 39 takes in the voltage output from the auxiliary transformer 151 and converts it into digital data. Specifically, the AD conversion circuit 39 mainly includes an analog filter, an AD converter, a sampling signal generator, and a ring memory. The specific configurations and functions of these will be described later.

[0044] In this embodiment, the processing circuit 154 is configured as a field programmable gate array (FPGA). The processing circuit 154 may be configured as a microcomputer including a central processing unit (CPU), a random access memory (RAM), and a read only memory (ROM). In this case, the CPU realizes the desired function by controlling the entire MU 20 according to a program stored in the ROM or the like. The processing circuit 154 may be configured as a dedicated circuit such as an application specific integrated circuit (ASIC). The processing circuit 154 may be configured by combining an electronic circuit such as an FPGA or ASIC with a microcomputer.

[0045] The communication circuit 155 transmits and receives data to and from the communication circuit 101 of the IED 10 via the process bus 100 (eg, the process buses 100a and 100b in FIG. 1).

[0046] The digital output circuit 156 is an interface circuit for outputting a digital signal to an external device. For example, the digital output circuit 156 outputs a trip signal to a corresponding breaker in accordance with a command from the processing circuit 154.

[0047] (Intelligent Electronic Device) Referring to FIG. 5, the IED 10 includes a communication circuit 101 and a processing circuit 103.

[0048] The communication circuit 101 transmits and receives data via the process bus 100 with the communication circuit 155 of the MU 20. For example, the communication circuit 101 receives the SV packet transmitted from the communication circuit 155 of the MU 20.

[0049] The processing circuit 103 executes a protection relay operation based on the SV packets received from each MU 20. When the processing circuit 103 determines that an accident has occurred in the power system as a result of the protection relay operation, it outputs a command signal for opening the circuit breaker to the MU 20 corresponding to the power system where the accident has occurred. The processing circuit 154 of the MU 20 instructs the digital output circuit 156 to output a trip signal.

[0050] The processing circuit 103 is configured as a microcomputer including a CPU, a RAM, and a ROM. In this case, the CPU realizes the above operations by controlling the entire IED 10 according to the program stored in the ROM or the like. Note that the processing circuit 103 may be configured as an FPGA, or may be configured as a dedicated circuit such as an ASIC. Further, the processing circuit 103 may be configured by combining an electronic circuit such as an FPGA or an ASIC with a microcomputer.

[0051] <Functional Configuration of MU> FIG. 6 is a diagram showing an example of the functional configuration of the MU. Referring to FIG. 6, the MU 20 includes, as functional components, communication units 50a, 50b, data generation units 52a, 52b, and SV packet generation units 54a, 54b. Typically, the communication units 50a, 50b are realized by the communication circuit 155 of FIG. 5. The data generation units 52a, 52b and the SV packet generation units 54a, 54b are realized by the processing circuit 154 of FIG. 5. The MU 20 further includes an AD conversion circuit 39 as a hardware configuration.

[0052] The data generation unit 52a includes a synchronization control unit 22a, an within error range checking unit 24a, and an extraction unit 25a. The data generation unit 52b includes a synchronization control unit 22b, an within error range checking unit 24b, and an extraction unit 25b. The SV packet generation unit 54a includes a timing management unit 26a and an SV creation unit 27a. The SV packet generation unit 54b includes a timing management unit 26b and an SV creation unit 27b.

[0053] First, a flow of operations from when an electrical quantity (analog data) taken in from the outside is AD-converted by the AD conversion circuit 39 will be described.

[0054] The AD conversion circuit 39 includes a sampling signal generator 31, an AD converter 32, a ring memory 33, and an analog filter .

[0055] As described above, the sampling signal generator 31 generates a sampling signal Sx of a high frequency (for example, 230 kHz) according to the timing inside the MU 20.

[0056] The analog filter 34 is, for example, a low-pass filter that removes high-frequency noise components from a current signal or a voltage signal. Fig. 6 shows an example in which four analog filters 34 receive four channel current signals (for example, a-phase current Ia, b-phase current Ib, c-phase current Ic, and zero-phase current I0) respectively. The AD conversion circuit 39 may be configured without including the analog filter 34.

[0057] The AD converter 32 samples the analog data (here, a current signal) output from the corresponding analog filter 34 based on the sampling signal Sx, and converts the sampled analog data into digital data. The AD converter 32 may include a sample-and-hold circuit and a multiplexer. In this case, the multiplexer sequentially selects the electrical quantity signals held in the sample-and-hold circuit, and the AD converter performs AD conversion on the signal selected by the multiplexer.

[0058] The ring memory 33 sequentially stores the digital data of the electrical quantity output from the AD converter 32 (that is, data after AD conversion).

[0059] Next, a flow from when the MU 20 receives a synchronization packet Ka from the IED 10a until when it transmits an SV packet Pa to the IED 10a will be described.

[0060] The communication unit 50a receives the synchronization packet Ka from the IED 10a. The communication unit 50a outputs the synchronization signal included in the synchronization packet Ka to the data generation unit 52a.

[0061] The synchronization control unit 22a of the data generating unit 52a determines the synchronization timing Ta based on the synchronization signal from the communication unit 50a. The within-error-range checking unit 24a checks whether the synchronization timing Ta is within the error range of the sampling synchronization frequency Fa (for example, 4800 Hz).

[0062] The extraction unit 25a performs digital filtering such as downsampling and removal of unnecessary harmonic noise on each digital data stored in the ring memory 33. Furthermore, the extraction unit 25a extracts digital data (i.e., data Dxa) sampled at the timing closest to the synchronization timing Ta from each digital data, and outputs it to the SV packet generation unit 54a. The data Dxa extracted here corresponds to, for example, data Dx#3 and #12 described in FIG. 4.

[0063] The timing management unit 26a of the SV packet generator 54a manages the time from AD conversion of the analog data to transmission of an SV packet Pa including the AD-converted digital data. The SV creation unit 27a converts the extracted data Dxa into the SV format defined by IEC61850, and creates an SV packet Pa including the converted data Dxa.

[0064] The communication unit 50a transmits the SV packet Pa to the IED 10a in accordance with the timing set by the timing management unit 26a. Depending on the timing setting, in one phase, an SV packet Pa including one piece of data Dxa is transmitted, and in another phase, an SV packet Pa including multiple pieces of data Dxa is transmitted.

[0065] The flow from when the MU 20 receives a synchronization packet Kb from the IED 10b until when it transmits an SV packet Pb to the IED 10b is basically the same as the above flow.

[0066] Specifically, the communication unit 50b receives a synchronization packet Kb from the IED 10b. The error range check unit 24b checks whether the synchronization timing Tb determined by the synchronization control unit 22b is within the error range of the synchronization frequency Fb (for example, 4800 Hz).

[0067] The extraction unit 25b extracts the digital data sampled at the timing closest to the synchronization timing Tb (i.e., data Dxb) from the digital data stored in the ring memory 33, and outputs it to the SV packet generation unit 54b. The data Dxb extracted here corresponds to, for example, the data Dx#1 and #9 described in FIG.

[0068] The SV creation unit 27b creates an SV packet Pa including the extracted data Dxb. The communication unit 50b transmits the SV packet Pb to the IED 10b in accordance with the timing set by the timing management unit 26b.

[0069] <Example> Example 1 Fig. 7 is a diagram for explaining the first embodiment. In a protection and control system 1000A shown in Fig. 7, IEDs 10a and 10b execute protective relay calculations for busbar protection. The IEDs are duplicated to ensure reliability of maintenance and operation. For example, the IED 10a is a busbar protective relay device of an operating system, and the IED 10b is a busbar protective relay device of a standby system.

[0070] The sampling synchronization timing of the redundant IEDs is different for each system. That is, the synchronization timing of the IED 10a of the active system is different from the synchronization timing of the IED 10b of the standby system.

[0071] The IED 10a transmits a synchronization packet Ka via the process bus 100a to each MU 20. The IED 10b transmits a synchronization packet Kb via the process bus 100b to each MU 20. The MU 20 uses the AD conversion circuit 39 to generate data Dxa in accordance with the synchronization timing Ta, and generates data Dxb in accordance with the synchronization timing Tb.

[0072] The MU 20 transmits the data Dxa to the IED 10a of the active system, and transmits the data Dxb to the IED 10b of the standby system. The IED 10a executes a protective relay calculation for protecting the busbar using the data Dxa. The IED 10b executes a protective relay calculation for protecting the busbar using the data Dxb.

[0073] In this way, the MU 20 can generate sampling data (e.g., data Dxa) used in the protective relay calculation of the active IED 10a and sampling data (e.g., data Dxb) used in the protective relay calculation of the standby IED 10b. Therefore, according to the first embodiment, the number of MUs can be halved compared to a configuration in which an active MU and a standby MU are provided separately, enabling cost reduction.

[0074] Example 2 Fig. 8 is a diagram for explaining Example 2. In a protection and control system 1000B shown in Fig. 8, the IED 10a performs protective relay calculations for protecting a busbar, and the IED 10b performs protective relay calculations for protecting a power transmission line.

[0075] The synchronization timing of the IED 10a for busbar protection and the synchronization timing of the IED 10a for transmission line protection are different because if they were the same, a failure in some equipment would cause system switching in each device in the power system pipe, making it difficult to operate the protection system.

[0076] The IED 10a transmits a synchronization packet Ka via the process bus 100a to each MU 20. The IED 10b transmits a synchronization packet Kb via the process bus 100b to each MU 20. The MU 20 uses the AD conversion circuit 39 to generate data Dxa in accordance with the synchronization timing Ta, and generates data Dxb in accordance with the synchronization timing Tb.

[0077] The MU 20 transmits the data Dxa to the IED 10a for busbar protection and transmits the data Dxb to the IED 10b for power transmission line protection. The IED 10a executes a protective relay calculation for protecting the busbar using the data Dxa. The IED 10b executes a protective relay calculation for protecting the power transmission line using the data Dxb.

[0078] In this way, the MU 20 can generate sampling data (e.g., data Dxa) used in the protective relay calculation of the IED 10a for busbar protection and sampling data (e.g., data Dxb) used in the protective relay calculation of the IED 10b for power transmission line protection. Therefore, according to the second embodiment, the number of MUs can be halved compared to a configuration in which an MU corresponding to an IED for busbar protection and an MU corresponding to an IED for power transmission line protection are separately installed, enabling cost reduction.

[0079] Example 3 In the third embodiment, a configuration will be described in which a device for performing protection relay calculations for busbar protection and an oscilloscope are synchronous master stations. The oscilloscope is a data recording device for recording electrical quantity data.

[0080] The synchronization timing of the oscilloscope device is different from that of the protection relay calculation device for busbar protection (or for power transmission line protection). The synchronization frequency (i.e., sampling frequency) of the protection relay calculation device for busbar protection is, for example, 4800 Hz (or 4000 Hz, 5760 Hz). On the other hand, the synchronization frequency of the oscilloscope device is a higher frequency than the synchronization frequency of the protection relay calculation device, for example, 14400 Hz.

[0081] FIG. 9 is a diagram for explaining the third embodiment. Referring to FIG. 9, Fa and Fc are the synchronization frequency of the IED 10a and the synchronization frequency of the oscilloscope device 10c, respectively. The oscilloscope device 10c functions as a synchronization master station that transmits a synchronization packet Kc to the MU 20. ΔTac indicates a synchronization error between the synchronization timing Ta and the synchronization timing Tc. ΔTc indicates an allowable error time that is allowed as an error time of the process of performing AD conversion from the synchronization timing Tc. The definitions of ΔTa and ΔTx are the same as those described in FIG. 2 or FIG. 4.

[0082] 9, the AD conversion circuit 39 of the MU 20 sequentially stores in an internal memory AD converted data Dx#0-#34 obtained by sampling an electrical quantity every sampling period Tx. The sampling period Tx is set to be shorter than the allowable error time ΔTa (i.e., Tx<ΔTa) and shorter than the allowable error time ΔTc (i.e., Tx<ΔTc). Therefore, among the data Dx, there is data Dx that satisfies the allowable error time ΔTa of the synchronization timing Ta, and there is also data Dx that satisfies the allowable error time ΔTc of the synchronization timing Tc.

[0083] Specifically, MU 20 extracts, as data Dxa, each of data Dx#3 and #33 sampled at the timing closest to synchronization timing Ta from data Dx#0 to #34 stored in the internal memory of AD conversion circuit 39. MU 20 extracts, as data Dxc, each of data Dx#1, #3, #5, #7, #9, . . . , #28, #30, and #32 sampled at the timing closest to synchronization timing Tb from data Dx#0 to #15.

[0084] The MU 20 transmits an SV packet Pa including each data Dxa (for example, data Dx#3, #33) to the IED 10a, and transmits an SV packet Pc including each data Dxc (for example, data Dx#1, #3, #5, etc.) to the oscilloscope device 10c.

[0085] The flow from when the MU 20 receives the synchronization packet Kc from the IED 10b until when it transmits the SV packet Pc to the oscilloscope device 10c is basically the same as the flow described with reference to FIG.

[0086] Specifically, MU 20 has a configuration in which communication unit 50b, data generator 52b, and SV packet generator 54b in Fig. 6 are replaced with communication unit 50c, data generator 52c, and SV packet generator 54c, respectively. Alternatively, MU 20 may further include communication unit 50c, data generator 52c, and SV packet generator 54c in addition to the functional configuration shown in Fig. 6. Note that the configurations of communication unit 50c, data generator 52c, and SV packet generator 54c are not shown.

[0087] The communication unit 50c receives the synchronization packet Kc from the oscilloscope device 10c. The error range check unit 24c checks whether the synchronization timing Tc determined by the synchronization control unit 22c is within the error range of the synchronization frequency Fc (for example, 14400 Hz).

[0088] The extractor 25c extracts the digital data sampled at the timing closest to the synchronization timing Tc (ie, data Dxc) from the digital data stored in the ring memory 33, and outputs it to the SV packet generator 54c.

[0089] The SV creation unit 27c creates an SV packet Pc including the extracted data Dxc. The communication unit 50c transmits the SV packet Pc to the oscilloscope device 10c in accordance with the timing set by the timing management unit 26c.

[0090] In this way, the MU 20 can generate data used in the protection relay calculation of the IED 10a and data recorded in the oscilloscope 10c. That is, even if the synchronization frequencies of the synchronization master stations are significantly different, data corresponding to each synchronization master station can be generated. Therefore, according to the third embodiment, the number of MUs can be reduced by half compared to a configuration in which an MU corresponding to an IED for busbar protection and an MU corresponding to an oscilloscope for data recording are separately installed, thereby enabling cost reduction.

[0091] Example 4 Fig. 10 is a diagram for explaining the configuration of the embodiment 4. Referring to Fig. 10, a protection and control system 1000D includes IEDs 10a and 10b, an oscilloscope device 10c, a power system stabilization device 10d, process buses 100a to 100d, and each MU20.

[0092] The IED 10a is a busbar protection relay device, and the IED 10b is a transmission line protection relay device. The power system stabilization device 10d is connected to the monitoring and control terminals of each renewable energy installed in the electric power station and general consumers via a wide area network. The power system stabilization device is also called WAMPAC (Wide Area Monitoring Protection and Control Solutions).

[0093] The IED 10a is communicatively connected to MU #1 to #30 via a process bus 100a. The IED 10b is communicatively connected to MU #1 to #30 via a process bus 100b. The oscilloscope device 10c is communicatively connected to MU #1 to #30 via a process bus 100c. The power system stabilization device 10d is communicatively connected to MU #1 to #30 via a process bus 100d. The power system stabilization device 10d functions as a synchronization master station that transmits a synchronization packet Kd.

[0094] The MU 20 receives, via the process buses 100a to 100d, a synchronization packet Ka from the IED 10a, a synchronization packet Kb from the IED 10b, a synchronization packet Kc from the oscilloscope device 10c, and a synchronization packet Kd from the power system stabilization device 10d.

[0095] The MU 20 determines the synchronization timings Ta to Td of sampling based on the synchronization packets Ka to Kd. The sampling period Tx is shorter than the allowable error time ΔTd allowed for the synchronization timing Td according to the synchronization packet Kd. The MU 20 extracts data Dxa to Dxd according to the synchronization timings Ta to Td from each data Dx stored in the internal memory. The MU 20 transmits the data Dxa, Dxb, Dxc, and Dxd to the IED 10a, IED 10b, oscilloscope device 10c, and power system stabilization device 10d, respectively.

[0096] In this way, even in a system configuration in which the four synchronous master stations are separate, the AD conversion circuit 39 in the MU 20 can be shared. Therefore, by providing the MU 20 with a communication unit, data generation unit, and SV packet generation unit corresponding to each synchronous master station, it is possible to generate data (for example, data Dxa to Dxd) corresponding to each synchronous master station.

[0097] Therefore, even if a system such as WAMPAC is constructed in the future, there is no need to modify the MU hardware configuration, and there is no impact on existing equipment. Therefore, even if a new WAMPAC is constructed after the construction of the power station protection and control system, the MU can be reused without adding additional equipment. This reduces the cost of constructing WAMPAC.

[0098] Embodiment 2 In the above-mentioned first embodiment, a configuration in which IEDs are duplicated to ensure reliability of maintenance and operation has been described. According to this embodiment, when an abnormality occurs in an IED of an active system, it is possible to reduce the switching time when switching the operation of the protection of the power system to an IED of a standby system. In the second embodiment, such a system switching method from an active system to a standby system will be described.

[0099] In order to facilitate understanding of the system fail-over method according to the second embodiment, a system fail-over method according to a second comparative example will be first described.

[0100] Fig. 11 is a diagram showing an overall configuration of a protection and control system 1200 according to Comparative Example 2. Referring to Fig. 11, the protection and control system 1200 includes IEDs 10a and 10b, process buses 100a and 100b, and MUs 205. It is assumed that the IED 10a is a busbar protection relay device of an active system, and the IED 10b is a busbar protection relay device of a standby system.

[0101] The IED 10a transmits a synchronization packet Ka to the MUs #c1 to #c30 via the process bus 100a. The IED 10b transmits a synchronization packet Kb to the MUs #c1 to #c30 via the process bus 100b.

[0102] Each MU 205 receives a synchronization packet Ka from the IED 10a via the process bus 100a, and receives a synchronization packet Kb from the IED 10b via the process bus 100b.

[0103] Here, the AD conversion circuit 395 of the MU205 includes a switching type sampling signal generator 315 and an AD converter 325. When the IED 10a of the active system is operating normally, the MU205 determines the synchronous timing Ta of sampling according to the synchronous signal included in the synchronous packet Ka. Then, the sampling signal generator 315 of the MU205 generates a sampling signal Sa according to the synchronous timing Ta. The AD converter 325 executes AD conversion based on the sampling signal Sa. The data Da after AD conversion is stored sequentially in the internal memory. The MU205 transmits an SV packet including the data Da to the IED 10a.

[0104] On the other hand, when an abnormality occurs in the active IED 10a and the standby IED 10b is operated as the active device, the MU 205 determines the synchronous timing Tb of sampling according to the synchronous signal included in the synchronous packet Kb. Then, the sampling signal generator 315 generates a sampling signal Sb according to the synchronous timing Tb. The AD converter 325 performs AD conversion based on the sampling signal Sb. The data Db after AD conversion is sequentially stored in the internal memory. The MU 205 transmits an SV packet including the data Db to the IED 10b.

[0105] As described above, MU205 according to Comparative Example 2 can simultaneously generate only one type of AD converted data (for example, data Da or data Db). In other words, MU205 cannot simultaneously generate data Da and Db based on sampling signals Sa and Sb corresponding to synchronization timings Ta and Tb, respectively.

[0106] Fig. 12 is a diagram for explaining a system switching method according to Comparative Example 2. With reference to Fig. 12, at an initial point in time, MU205 uses the AD conversion circuit 395 to perform AD conversion of an electric quantity based on a sampling signal Sa following a synchronization timing Ta, and generates data Da. In the example of Fig. 12, data Da#1 is generated. At this time, MU205 does not use the AD conversion circuit 395 to perform AD conversion of an electric quantity based on a sampling signal Sb following a synchronization timing Tb.

[0107] Next, assume that an abnormality occurs in the a-system including the IED 10a and the process bus 100a. A certain period of time (hereinafter also referred to as "system switching confirmation time Tkk") is required from the time the abnormality occurs in the a-system until it is determined that the IED 10b of the standby system operates as a device of the active system. The system switching confirmation time Tkk is, for example, about 10 seconds.

[0108] The MU 205 detects the occurrence of an abnormality in the a-system including the IED 10a and the process bus 100a based on the status information included in the synchronization packet Ka from the IED 10a. The MU 205 notifies the IED 10b of the occurrence of the abnormality via the process bus 100b. The IED 10b recognizes the occurrence of the abnormality and determines that it will operate as an active system device. The IED 10b transmits an operation notification to the MU 205 indicating that it will operate as an active system device. For example, the system switching confirmation time Tkk is the time from when the MU 205 detects the occurrence of an abnormality in the a-system to when it receives the operation notification.

[0109] Thereafter, MU205 switches the referenced synchronization timing from synchronization timing Ta to synchronization timing Tb, performs AD conversion based on the sampling signal Sb according to synchronization timing Tb, and sequentially generates data Db. MU205 transmits the data Db to IED 10b. However, a certain amount of data Db is required to start protection relay calculation in IED 10b. The time until this certain amount of data Db is accumulated is defined as time Tspr.

[0110] Therefore, the IED 10b starts protecting the busbar as a protection relay device of the active system after the total time Tlock of the system switching confirmation time Tkk and the time Tspr has elapsed since the occurrence of an abnormality in the a system. Therefore, the time from the occurrence of an abnormality in the a system until the total time Tlock has elapsed is the non-protection period of the busbar.

[0111] Next, a system switching method according to the embodiment 2 will be described. Fig. 13 is a diagram for explaining the system switching method according to the embodiment 2. Note that the protection and control system according to the embodiment 2 is assumed to be a protection and control system 1000A as shown in Fig. 7.

[0112] 13, the MU 20 uses the AD conversion circuit 39 to perform AD conversion of an electrical quantity based on the sampling signal Sx, and generates data Dx. In the example of Fig. 13, before the occurrence of an abnormality in the a-system including the IED 10a and the process bus 100a, Dx#1 is generated as data Dxa, and Dx#-21 to #-4 are generated as data Dxb.

[0113] Next, assume that an abnormality occurs in the a-system. A method of determining whether an abnormality occurs by the MU 20 will be described. Specifically, the synchronization packet Ka received by the communication unit 50a of the MU 20 includes status information indicating the path between the IED 10a and the MU 20 (i.e., the process bus 100a) and the status of the a-system including the previous IED 10a. An abnormality determination unit (not shown) of the MU 20 determines whether an abnormality occurs in the a-system based on the status information. In detail, when the status information includes a flag indicating an abnormality, the abnormality determination unit determines that an abnormality occurs in the a-system, and when the status information includes a flag indicating normality, the abnormality determination unit determines that an abnormality does not occur in the a-system.

[0114] Here, MU 20 according to the second embodiment continues to generate data Dxb for system b, regardless of the presence or absence of an abnormality in system a. Therefore, even before the occurrence of an abnormality in system a, an SV packet Pb including data Dxb is transmitted to IED 10b at the timing managed by timing manager 26b.

[0115] When the abnormality determination unit determines that an abnormality has occurred in system a, the communication unit 50b of the MU 20 transmits instruction information to the IED 10b to instruct the IED 10b to execute a protective relay calculation using the data Dxb as an operating system device. Specifically, the communication unit 50b transmits an SV packet Pb including the data Dxb and the instruction information to the IED 10b.

[0116] The IED 10b receives the data Dxb and the instruction information contained in the SV packet Pb. As described above, the data Dxb is transmitted to the IED 10b even before the occurrence of the abnormality in the a-system. Therefore, the IED 10b can start the protection relay calculation from the time when the instruction information is received.

[0117] Therefore, in the second embodiment, the system switching confirmation time Tkk and the time Tscp in the second comparative example do not occur, so that the IED 10b can immediately start the protective relay calculation when an abnormality occurs in the a system.

[0118] The abnormality determination unit may determine whether an abnormality occurs in a functional unit related to the a system shown in FIG. 6. The functional unit includes a communication unit 50a, a data generation unit 52a, and an SV packet generation unit 54a. The abnormality determination unit has a known self-diagnosis function. If an abnormality occurs in a functional unit related to the a system, the communication unit 50b transmits the above instruction information to the IED 10b. In this case, the IED 10b can immediately start a protective relay calculation when an abnormality occurs in the a system. This can reduce the unprotected period of the busbar to almost zero.

[0119] Furthermore, for example, in a configuration in which the IED 10b is connected to the process bus 100a of the a-system, the IED 10b may have a function of determining an abnormality in the process bus 100a.

[0120] Other embodiments. The configuration exemplified as the above-mentioned embodiment is one example of the configuration of this embodiment, and it is possible to combine it with other known technologies, and it is also possible to modify the configuration, such as omitting some parts, as long as it does not deviate from the gist of this disclosure.

[0121] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0122] 10c oscilloscope device, 10d power system stabilizer, 22a to 22c synchronization control unit, 24a to 24c error range confirmation unit, 25a to 25c extraction unit, 26a to 26c timing management unit, 27a to 27c SV creation unit, 31, 310a, 310b, 315 sampling signal generator, 32, 320a, 320b, 325 AD converter, 33 ring memory, 34 analog filter, 39, 390a, 390b, 395 AD conversion circuit, 50a, 50b communication unit, 52a, 52b data generation unit, 54a, 54b packet generation unit, 100, 100a to 100d process bus, 101, 155 communication circuit, 103, 154 processing circuit, 151 auxiliary transformer, 156 Digital output circuits, 1000, 1000A, 1000B, 1000D, 1100, 1200 protection and control systems.

Claims

1. a sampling signal generator for generating a sampling signal; an analog-to-digital converter that samples an electrical quantity of the power system based on the sampling signal and performs analog-to-digital conversion; a memory for sequentially storing the digital data of the electrical quantity output from the analog-to-digital converter; a sampling period of the sampling signal is shorter than a first allowable error time allowed for a synchronization timing indicated by a first synchronization signal and a second allowable error time allowed for a synchronization timing indicated by a second synchronization signal; a first extracting unit that extracts, from each digital data stored in the memory, digital data sampled at a timing closest to a synchronization timing indicated by the first synchronization signal; a second extraction unit that extracts, from each digital data stored in the memory, digital data sampled at a timing closest to a synchronization timing indicated by the second synchronization signal.

2. a first communication unit that receives the first synchronization signal from a first master station; a second communication unit that receives the second synchronization signal from a second master station; the first communication unit transmits the first digital data extracted by the first extraction unit to the first master station; The control device according to claim 1 , wherein the second communication section transmits the second digital data extracted by the second extraction section to the second master station.

3. the first master station is an operational device that executes a first relay calculation for protecting the power system using the first digital data; 3. The control device according to claim 2, wherein the second master station is a standby system device that uses the second digital data to execute a second relay calculation for protecting the power system.

4. The first communication unit further receives first status information indicating a path between the first master station and the control device and a status in a first system including the first master station; An abnormality determination unit that determines whether or not an abnormality has occurred in the first system based on the first state information, The control device according to claim 3, wherein when an abnormality occurs in the first system, the second communication unit transmits instruction information to the second parent station to instruct the second parent station to execute the second relay calculation using the second digital data as an operating system device.

5. The abnormality determination unit further determines whether or not an abnormality has occurred in a functional unit related to the first system, the functional unit including the first extraction unit and the first communication unit; The control device according to claim 4 , wherein, when an abnormality occurs in a functional unit related to the first system, the second communication unit transmits the instruction information to the second master station.

6. the first master station executes a relay operation for protecting a busbar included in the power system using the first digital data; The control device according to claim 2 , wherein the second master station uses the second digital data to execute a relay operation for protecting a power transmission line included in the power system.

7. a third communication unit that receives a third synchronization signal from a third master station; a third extraction unit that extracts, from each digital data stored in the memory, digital data sampled at a timing closest to a synchronization timing indicated by the third synchronization signal, the sampling period is shorter than a third allowable error time allowed for the synchronization timing indicated by the third synchronization signal; the third communication unit transmits the third digital data extracted by the third extraction unit to the third master station; 7. The control device according to claim 1, wherein the third master station is a data recording device that records the third digital data.

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