Device and method of manufacturing the same

Abstract

To mount a chip with an air bridge in a flip-chip manner.SOLUTION: A method includes the processes of: removing a sacrificial layer except below an air bridge after depositing a conductive layer serving as the air bridge on the sacrificial layer to complete pattern formation on a first surface of a chip; and removing the sacrificial layer left below the air bridge after mounting the chip, having the sacrificial layer still left below the air bridge, with the first surface opposed to a substrate.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a device and a method for manufacturing the same. [Background technology]

[0002] The basic element of a superconducting quantum circuit is a superconducting resonator composed of an inductor and a capacitor made of a superconducting metal, and a SQUID (Super Quantum Interference Device) having a loop including one or more Josephson junctions. A Josephson junction is a tunnel junction in which a thin insulating film is sandwiched between superconductors, and behaves as a nonlinear inductor. The resonance frequency of the superconducting resonator can be changed by passing a direct current or microwave current through a control line (pump line) to the SQUID and modulating the magnetic flux passing through the SQUID loop. In a superconducting quantum circuit, a coplanar waveguide is used, which is configured with a signal line sandwiched between a pair of juxtaposed ground planes. A configuration in which multiple SQUIDs are arranged in one superconducting quantum circuit chip is used. For example, a configuration in which quantum bits including a SQUID, such as a Josephson Parametric Oscillator (JPO), are arranged in the chip. In such a configuration, crosstalk becomes an issue, in that a magnetic field applied to one SQUID is applied not only to that SQUID but also to other SQUIDs.

[0003] For example, Patent Documents 1 and 2 disclose a structure in which an air bridge is arranged in a wiring layer (superconducting conductor layer) on a substrate, connecting the ground planes on both sides of a signal line of a coplanar waveguide with a superconductor. According to Patent Document 1, the superconducting air bridge reduces crosstalk believed to be caused by charge distribution along the edge of the ground plane. Patent Document 2 discloses a method for fabricating a suspended conductive structure such as a metallic (conductive) air bridge connecting two parts of a conductive layer patterned on a substrate, in which a metallic bridge is formed using an interlayer dielectric (ILD) such as silicon dioxide to support the structure, and then the interlayer dielectric is removed. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 6437607 [Patent Document 2] Special Publication No. 2020-532866 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present disclosure is to provide a device and a manufacturing method thereof that allows a chip with an air bridge to be flip-chip mounted. [Means for solving the problem]

[0006] A method for manufacturing a device according to one aspect of the present disclosure includes the steps of depositing and patterning a conductive layer that will become an air bridge on a sacrificial layer on a first surface of a chip, and then removing the sacrificial layer except for a portion of the air bridge; mounting the chip with the sacrificial layer remaining under the air bridge with the first surface facing a substrate, and then removing the sacrificial layer remaining under the air bridge.

[0007] A device according to one aspect of the present disclosure comprises a chip including at least one air bridge on a first surface thereof and a substrate on which the chip is mounted, the chip being mounted with the first surface facing the substrate. Effect of the Invention

[0008] According to the present disclosure, a chip with an air bridge can be flip-chip mounted to a substrate. [Brief description of the drawings]

[0009] [Figure 1] 1A to 1E are diagrams illustrating a manufacturing process of one embodiment. [Diagram 2] 1(F) to 1(H) are diagrams illustrating a manufacturing process of one embodiment. [Diagram 3] FIG. 1 is a diagram showing a schematic diagram of one embodiment of mounting. [Figure 4] FIG. 1 is a diagram showing a schematic diagram of one embodiment of a superconducting circuit device. [Diagram 5] FIG. 13 is a diagram showing a schematic diagram of another mounting form. [Figure 6] FIG. 2 is a diagram showing a schematic diagram of another embodiment of a superconducting circuit device. [Figure 7] 1A to 1C are diagrams illustrating a modified example of one embodiment. [Figure 8] FIG. 1 is a diagram showing a schematic example of a configuration of a superconducting circuit having an air bridge. [Figure 9] FIG. 13 is a diagram showing a schematic diagram of another example of the configuration of a superconducting circuit having an air bridge. [Figure 10] FIG. 2 is a diagram illustrating an example of an air bridge. [Figure 11] FIG. 1 is a diagram showing a schematic diagram of an example of surface activated bonding. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] An air bridge is generally used as a three-dimensional wiring structure on a substrate with air as an insulator. As shown in Fig. 10, an air bridge 30 that connects a first conductor 12A and a second conductor 12B across a conductor 12C on a substrate 11 is made up of contact parts (pedestals) 13A and 13B that extend over the first conductor 12A and the second conductor 12B, respectively, pier parts 13C and 13D that rise up from the contact parts 13A and 13B in directions approaching each other, and a bridge girder part 13E whose both ends are supported by the pier parts 13C and 13D. The contact parts 13A, 13B, pier parts 13C, 13D, and bridge girder part 13E of the air bridge 30 are integrally formed from, for example, one conductive layer (conductive film) (in FIG. 10, the contours of the pier parts 13C, 13D, bridge girder part 13E, etc. are linear for the purpose of explaining each part of the air bridge, but they may be smoothly curved arch shapes). After forming a pattern by forming a conductive layer to be the air bridge on a sacrificial layer (not shown) formed on the substrate 11, the sacrificial layer is removed to form the air bridge 30. The air bridge 30 has a hollow structure below it and is physically fragile. For example, it is easily broken by ultrasonic cleaning, which is one of the common cleaning methods. For this reason, it is difficult to carry out a process after removing the sacrificial layer of the air bridge 30, and it is difficult to flip-chip mount (mount the chip by flipping it over) a chip having the air bridge 30 on the substrate 11 to an interposer (also called an "interposer substrate") or the like.

[0011] Here, we consider using an oxide film (silicon oxide film) as a sacrificial layer for forming the air bridge, leaving the sacrificial layer directly below the air bridge, and flip-chip mounting the chip to the interposer while increasing the strength of the air bridge.

[0012] In a device in which a chip is flip-chip mounted on an interposer, for example, HF (hydrogen fluoride) is used to remove the silicon oxide film (sacrificial layer) remaining under the air bridge of the chip. When etching the silicon oxide film (sacrificial layer) using an aqueous solution of hydrofluoric acid, hydrofluoric acid damages metal layers (conductive layers). For example, Al (aluminum) films forming Josephson junctions arranged in the wiring layer of a quantum chip, superconducting wiring, electrodes, etc. are eroded. A particular problem is that Josephson junctions (Al / Al oxide film / Al) that are quantum circuit elements of a quantum chip are eroded and lost by HF. In addition, when Al, Cu (copper), Ti (titanium), etc. are used for wiring, electrodes, bumps, etc. in an interposer, these will be eroded (Al, Cu, and Ti are eroded by hydrofluoric acid. For example, Nb (niobium), which is a material for superconducting wiring, is hardly eroded. Au (gold) is not eroded). By using vapor HF (vapor phase hydrogen fluoride: evaporating HF aqueous solution), the erosion of the metal layer (conductive layer) can be relatively suppressed. However, when etching in the vapor phase using hydrofluoric acid vapor evaporated from a hydrofluoric acid aqueous solution, in order to not only prevent the adhesion of reaction products but also to completely remove the silicon oxide film (sacrificial layer) directly below the air bridge, even VHF should be set to a stronger etching condition, and it is predicted that it is difficult to obtain an optimal process condition range (process window) for the erosion of metal by HF and the removal of the sacrificial layer. Therefore, it is considered difficult to remove the silicon oxide film (sacrificial layer) remaining under the air bridge using HF or vapor HF in a state in which a quantum chip having an air bridge is flip-chip mounted on an interposer. The above problem is one example, but the present disclosure is not limited to the above, and makes it possible to flip-chip mount a chip equipped with an air bridge.

[0013] According to the present disclosure, a conductive layer that becomes an air bridge is formed on a sacrificial layer on a first surface of a chip, a pattern is formed, and then the sacrificial layer is removed except for the lower part of the air bridge. The chip with the sacrificial layer remaining under the air bridge is mounted (flip-chip mounted) with the first surface facing a substrate (the substrate may be an interposer substrate or a substrate of a second chip), and then the sacrificial layer remaining under the air bridge is removed. This makes it possible to realize a device in which a chip including at least one air bridge on a first surface is mounted (flip-chip mounted) with the first surface facing the substrate. Hereinafter, several embodiments of the present disclosure will be described.

[0014] 1 and 2 are cross-sectional views showing an example of a process related to the manufacture of an air bridge when a quantum chip is manufactured using a semiconductor process according to an embodiment of the present disclosure. Note that the diagram is divided simply for convenience of drawing.

[0015] FIG. 1(A) shows a schematic diagram of a state where a wiring pattern is formed on the first surface (front surface) of a substrate 11. A superconducting conductor film 12 such as niobium (Nb) is formed on the first surface of the substrate 11, and a desired wiring pattern is formed by exposure and development (photolithography) / etching. Nb wiring constituting superconducting signal wiring, Josephson junctions having a laminated structure of Al / Al oxide film / Al by oblique deposition, for example, are created. An air bridge is fabricated in the following process. In the following, the wiring layer on the first surface on the substrate 11 is referred to by the same reference numeral 12 as the superconducting conductor film. In the wiring layer 12 on the first surface of the substrate 11, a first conductor 12A and a second conductor 12B are provided at a predetermined interval on both sides of a conductor 12C (signal conductor). An air bridge (not shown) straddles above the conductor 12C (signal conductor) and electrically connects the first conductor 12A and the second conductor 12B. The conductor 12C (signal conductor), the first conductor 12A, and the second conductor 12B in FIG. 1A may correspond to the conductor 12C (signal conductor), and the first conductor 12A and the second conductor 12B (connected by an air bridge 30) in FIG. 10. The first conductor 12A and the second conductor 12B may be ground planes. A waveguide in which ground planes (the first conductor 12A and the second conductor 12B) are arranged on both sides of the conductor 12C (signal conductor) with a gap therebetween constitutes a coplanar waveguide (CPW). Connecting the ground planes electrically separated by the conductor 12C (signal conductor) with an air bridge is effective in reducing crosstalk.

[0016] The substrate 11 is made of silicon. However, other electronic materials such as germanium, sapphire, and compound semiconductor materials (Group IV (GeSn, etc.), Group III-V (GaAs, GaN, GaP, GaSb, InAs, InP, InS, etc.), and Group II-VI (ZnS, ZnSe)) may also be used. Although a single crystal is preferable, polycrystalline or amorphous materials are also acceptable.

[0017] The superconducting conductor is made of a superconducting material such as Nb. The superconducting material is not limited to niobium (Nb), but may be niobium nitride, aluminum (Al), indium (In), lead (Pb), tin (Sn), rhenium (Re), palladium (Pd), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or an alloy or laminate structure containing at least one of these and exhibiting superconducting properties.

[0018] 1(B), photoresist 14 (photosensitive polyimide or the like) for forming an air bridge is formed (applied) on the entire surface of the substrate 11 in FIG. 1(A). The photoresist 14 is applied uniformly on the entire surface of the substrate by spin coating or the like to a thickness of, for example, several μm (micrometers) to tens or tens of μm, depending on the height of the air bridge.

[0019] 1(C), in order to form the piers 13C and 13D of the air bridge and the contacts 13A and 13B (see FIG. 10), a desired photomask is used to expose and develop the photoresist 14, thereby forming vias 15A and 15B that reach the superconducting conductor film 12. The patterned photoresist 14 is called a "sacrificial layer."

[0020] 1(D), the substrate 11 is heat-treated to reflow the photoresist 14. The substrate 11 is uniformly heated by a reflow device (e.g., a hot plate) not shown, and the photoresist 14 (sacrificial layer) patterned in the exposure and development process of FIG. 1(C) is heated to soften and flow, and the cross-sectional contour shape of the photoresist 14 is rounded to form an arch shape.

[0021] 2(E), a superconducting member 13 that will become an air bridge is formed by sputtering or the like on the patterned photoresist 14 (sacrificial layer) on the substrate 11. As a non-limiting example, the superconducting member 13 is made of aluminum (Al). The thickness of the superconducting member 13 may be on the order of several hundred nanometers (1 μm or less), for example.

[0022] Next, referring to FIG. 2(F), photoresist 16 is applied, and the photoresist 16 is exposed and developed using a desired photomask, so that the photoresist 16 is patterned into the planar shape of the air bridge (a mask for forming the air bridge is fabricated).

[0023] Referring to FIG. 2(G), the superconducting member 13(Al) is etched using the photoresist 16 remaining on the superconducting member 13 as an etching mask, so that the superconducting member 13 is patterned into the wiring of the air bridge. That is, a bridge is formed consisting of the wiring of the superconducting member 13 that straddles the conductor 12C from above via the photoresist 14 (sacrificial layer) remaining at the bottom. As a non-limiting example of etching the superconducting member 13(Al), any of wet etching using an acid such as a mixed acid or an alkaline aqueous solution such as a developing solution, milling using Ar ions, or reactive ion etching (RIE) using a chlorine (Cl)-based gas may be used. FIG. 2(G) corresponds to the state after etching the superconducting member 13(Al), where the photoresist 16 remains on the superconducting member 13 that becomes the air bridge. In addition, the photoresist 14 (sacrificial layer) is entirely left.

[0024] From the state of Fig. 2(G), the photoresist 16 and the photoresist 14 (sacrificial layer) other than the lower part of the superconducting member 13 that becomes the air bridge are simultaneously removed to obtain the state of Fig. 2(H). For example, the hardened layers of the photoresists 14 and 16 exposed on the surface are removed by ashing. Next, the photoresist 16 and the photoresist 14 (sacrificial layer) other than the lower part of the air bridge 30A are removed by, for example, immersing them in an organic solvent for several minutes. That is, the removal of the photoresist 16 and the photoresist 14 (sacrificial layer) is performed in two stages.

[0025] First, the hardened layer of the photoresist 16 and the photoresist 14 (sacrificial layer) exposed on the surface other than the lower part of the air bridge 30A is removed by ashing or the like. When oxygen plasma reacts with the photoresist 14 (sacrificial layer) and the photoresist 16, CO2 , H 2 O, O 2 Dry ashing using oxygen plasma (high-energy oxygen plasma is irradiated onto the resin surface, bonding with the carbon that constitutes the resin, and CO 2 By using a solvent (which vaporizes and decomposes as SiO 2 ), the hardened layer (the portion exposed to light during exposure is hardened) formed on the surface of the photoresist 16 and the photoresist 14 during the formation of the Al film is removed. Following this, the photoresist 16 and the photoresist 14 (sacrificial layer) are removed using an organic solvent. If the time for permeating the organic solvent is within a predetermined time (for example, several minutes), the photoresist 14 under the air bridge 30A is not completely dissolved and remains, and the photoresist 14 (sacrificial layer) exposed on the surface other than the lower part of the air bridge 30 is removed. As a result, as shown in FIG. 2(H), a state is obtained in which the photoresist 14 (sacrificial layer) under the air bridge 30A remains.

[0026] The photoresist 14 (sacrificial layer) remaining at the bottom of the air bridge 30A acts as a reinforcing member supporting the air bridge from below, and the mechanical strength of the air bridge is increased compared to when the bottom of the air bridge is hollow. Therefore, even if other processes such as cleaning and assembly are performed thereafter, the photoresist 14 (sacrificial layer) at the bottom of the air bridge 30A prevents the air bridge from buckling or collapsing. This makes it possible to perform additional cleaning of the quantum chip 10 and processes such as flip-chip mounting to an interposer.

[0027] FIG. 3 is a schematic cross-sectional view for explaining an example of mounting the quantum chip 10, in which the air bridge 30A is formed on the wiring layer 12 on the first surface, on the interposer 20 by the manufacturing process of FIG. 1 and FIG. 2. At the mounting stage, the interposer 20 has a wiring pattern formed on the wiring layer 22 on the first surface of the substrate 21, a wiring pattern formed on the wiring layer 23 on the second surface of the substrate 21, and a through via 24 penetrating the substrate 21. Also, a bump (metal protrusion) 25 is formed on the wiring layer 22 on the first surface of the interposer 20 or the wiring layer 12 of the quantum chip 10. When the substrate 11 of the quantum chip 10 is silicon, the substrate 21 of the interposer 20 is made of silicon. The substrate 21 is not limited to one containing silicon, and may contain other electronic materials such as sapphire, compound semiconductor materials (IV group, III-V group, II-VI group), glass, ceramic, etc. The wiring layer 22 on the first surface and the wiring layer 23 on the second surface are preferably made of the same superconducting material. 3, for simplicity, one through via 24 is illustrated, but a plurality of through vias are provided, such as a through via connecting a signal line of the wiring layer 22 on the first surface of the interposer 20 and the wiring layer 23 on the second surface, and a through via connecting a ground surface of the wiring layer 22 on the first surface of the interposer 20 and a ground surface of the wiring layer 23 on the second surface. Note that the through via 24 is illustrated as a via in which the inside of the via hole is filled with a conductor (a filled via), but it may be a holed via in which a conductor layer is formed with a uniform thickness according to the shape of the via hole (a conformal via). The via may have a superconducting thin film such as a Ti or TiN film on the via sidewall and be filled with Cu.

[0028] As shown in FIG. 3, the quantum chip 10, with the photoresist 14 (sacrificial layer) remaining on the lower part of the air bridge 30A, is flip-chip bonded (FCB) with the first surface including the air bridge 30A facing the wiring layer 22 on the first surface of the interposer 20.

[0029] The superconducting circuit device 1, in which the quantum chip 10 has been flip-chip bonded to the interposer 20, is immersed in an organic solvent (stripping liquid) or the like to remove the photoresist 14 (sacrificial layer) under the air bridge 30A in FIG. 3. If necessary, a dry process such as ashing may also be performed to remove the photoresist 14 (sacrificial layer). As a result, as shown in FIG. 4, a superconducting circuit device 1 is obtained in which the quantum chip 10 having the air bridge 30 with a hollow structure is flip-chip mounted on the interposer 20. In FIG. 4, the wiring layer 23 on the second surface of the interposer 20 may be connected to a package substrate or the like (not shown).

[0030] 3 and 4, the bump 25 is a metal protrusion suitable for controlling the height of the gap between the substrates to be joined, and can have any shape such as a columnar shape (cylinder, polygonal column, etc.), a pyramid shape (cone truncation, pyramid, etc.), a spherical shape, a rectangular shape, etc. The bump 25 may be made of a normal conducting material and molded by laminating a superconducting material. The bump 25 may be formed on the wiring layer 22 side of the first surface of the quantum chip 10. The bump 25 may be formed on the wiring layer 22 of the first surface of the interposer 20. The bump 25 may contain the same superconducting material as the wiring layer 22 of the first surface of the interposer 20, or may contain a different superconducting material from the wiring layer 22 of the first surface.

[0031] Considering signal transmission by wireless transmission (e.g., capacitive coupling) between the interposer 20 and the quantum chip 10, the height of the bump 25 may be, for example, on the order of several μm to 10 μm. In this case, the width of the bump 25 may be on the order of several to tens of μm. The bump 25 is also called a microbump.

[0032] The bump 25 may be configured to include multiple metal layers, but at least one layer preferably includes a superconducting material. The bump 25 is made of a normal conductive material such as Cu or silicon dioxide (SiO 2 ) or the like, the surface of which may be covered with a film of a superconducting material.

[0033] 4, the height of the air bridge 30 is set lower than the distance (height hb of the bump 25) between the quantum chip 10 and the wiring layer 22 on the first surface of the interposer 20, and the bridge beam (13E in FIG. 10) of the air bridge 30 is separated from the wiring layer 22 on the first surface of the interposer 20 via an air gap. The length of the air bridge 30 is set to a value corresponding to the distance between the first conductor 12A and the second conductor 12B (W+2S, where W is the width of the conductor 12C, S is the gap between the first conductor 12A and the conductor 12C, and S is the gap between the second conductor 12B).

[0034] When the quantum chip 10 is flip-chip bonded to the interposer 20, for example, solid-state bonding may be used. Although not particularly limited, among solid-state bonding, surface activated bonding (SAB) may be used. In this case, as a non-limiting example, as shown in FIG. 11, for example, the bump 25 formed on the wiring layer 22 side of the first surface of the interposer 20 and the electrode pad (electrode pad bonded to the bump 25) of the wiring layer 12 of the quantum chip 10 are arranged in a vacuum chamber 5 in a facing orientation, and a vacuum is drawn from the vacuum exhaust port 9 by a vacuum pump (not shown). The quantum chip 10 is fixed by, for example, a first fixing jig (stage) 2. The fixing method may be a clamp method or an electrostatic chuck method. The quantum chip 10 fixed by the first fixing jig (stage) 2 may be in a wafer state, or may be individualized from the wafer into each chip. The interposer 20 (wafer, or chips separated from the wafer) is fixed by a second fixing jig (stage) 3 supported by a support 6. The fixing method may be a clamp method or an electrostatic chuck method. The quantum chip 10 and the interposer 20 separated from the wafer into chips may be ones that have been selected as non-defective products in tests such as connection tests before bonding. The degree of vacuum in the vacuum chamber 5 is, for example, 10 -6The pressure may be about Pa (Pascal). The first fixing jig (holding member) 2 can be translated in the X and Y directions by the XY translation mechanism 2A relative to the second fixing jig 3 below, and can be positioned by moving in the Z direction and rotating around the Z axis by the Z direction movement mechanism 7 and the Z axis rotation mechanism 8. The activation device 4a is used to remove adsorbed substances and oxides on the surface of the electrode pad of the quantum chip 10 to activate the joint, and the activation device 4b is used to remove adsorbed substances and oxides on the surface of the bump 25 of the interposer 20 to activate the joint with the quantum chip 10. The activation devices 4a and 4b may be devices that irradiate Ar (argon) ions or neutral atomic beams.

[0035] Next, the quantum chip 10 and the interposer 20 are aligned. The alignment is performed by translating the first fixing jig 2 in the X-direction and Y-direction relative to the second fixing jig 3 and rotating it around the Z-axis. While maintaining the vacuum, the electrode pads of the wiring layer 12 of the quantum chip 10 and the contact surfaces of the bumps 25 are brought into contact with each other and pressurized by the Z-direction moving mechanism 7 (100 to several hundred MPa as a non-limiting example). At this time, the pressure in the direction perpendicular to the contact surfaces in contact under pressure may be measured by a Z-axis pressure sensor (not shown) to control the pressure. The temperature may be room temperature or a low temperature of, for example, 100° C. or less. The malleable bumps 25 follow the surface roughness of the electrode pads of the quantum chip 10 and are firmly bonded to the bonding interface between the bumps 25 and the electrode pads of the quantum chip 10. For example, alignment marks (not shown) may be provided on the quantum chip 10 and the interposer 20, and the positions may be adjusted using a transmitted image by an infrared camera or the like to align the two. When the quantum chip 10 and the interposer 20 are bonded in a wafer state, the wafer is separated into individual pieces after the bonding is completed.

[0036] By using the above process, it is possible to flip-chip mount the quantum chip 10 with the air bridge 30 onto the interposer 20.

[0037] In order to intentionally leave the sacrificial layer photoresist 14, it is desirable that the width of the air bridge 30 is relatively wide, for example, 30 μm (micrometers) or more. When each ground plane facing the signal line of the coplanar waveguide structure is electrically connected by an air bridge, a wide air bridge is more effective in eliminating the bias in the charge distribution spreading on the ground plane during the operation of the quantum circuit, and the crosstalk reduction effect is improved.

[0038] However, if the width of the air bridge 30 is too large, it becomes difficult to remove the sacrificial layer under the air bridge 30. In the manufacturing process of the air bridge, if the width of the superconducting member 13 (patterned using the photoresist 16) that becomes the air bridge is increased, the photoresist 14 (sacrificial layer) under it will also be formed long along the width of the superconducting member 13. When removing the photoresist 14 (sacrificial layer) remaining under the air bridge 30A (FIG. 3) after flip-chip bonding of the quantum chip 10 and the interposer 20, for example, the photoresist 14 (sacrificial layer) at the base (corner) of the wide pier of the air bridge 30A (FIG. 3) becomes difficult to remove, and residues of the photoresist 14 tend to remain. The residues of the photoresist 14 (sacrificial layer) cause dielectric loss in the superconducting quantum circuit element, and affect the yield. Due to the restriction of the height of the air bridge 30 to be equal to or less than the height of the bump 25 and the set length, the area of ​​the hollow part of the air bridge 30 cannot be significantly enlarged. Therefore, the upper limit of the width of the air bridge 30 may be determined from the viewpoint of the area of ​​the hollow portion of the air bridge 30 and removal of the photoresist 14 (sacrificial layer) left under the air bridge 30. Note that a plurality of air bridges 30 connecting opposing ground surfaces to one coplanar waveguide may be arranged in parallel.

[0039] As another embodiment of the present disclosure, as shown in FIG. 5, at least the top of the air bridge 30A may be in contact with the interposer 20. The photoresist 14 at the bottom of the air bridge 30A is left, and the air bridge 30A is supported from below, so that such a mounting embodiment can be realized. In the example of FIG. 5, the wiring (superconducting conductor) 13 constituting the air bridge 30A is in contact with the first wiring layer 22 of the interposer 20 facing the bridge girder portion at a predetermined width at a portion corresponding to the bridge girder portion (13E in FIG. 10). However, it is of course possible to configure the air bridge 30A so that a part (or a point) of the wiring (such as the top of the bridge girder portion) is in contact with the first wiring layer 22 of the interposer 20. FIG. 6 shows a schematic diagram of the air bridge 30A in FIG. 5 after the photoresist 14 at the bottom has been removed (the air bridge 30 has a hollow structure). 6, the first conductor 12A and the second conductor 12B arranged to face the signal conductor 12C of the quantum chip 10 with a gap therebetween are ground planes and form a coplanar waveguide. The wiring (superconducting conductor) 13 constituting the air bridge 30 not only electrically connects the ground plane (first conductor 12A) and the ground plane (second conductor 12B) separated by the signal conductor 12C in the quantum chip 10, but also abuts and electrically connects with the wiring layer 22 (ground plane) on the first surface of the interposer 20. The air bridge 30 provides a connection path between the ground plane (first and second conductors 12A and 12B) of the quantum chip 10 and the ground plane of the wiring layer 22 on the first surface of the interposer 20.

[0040] Fig. 7 shows, as another embodiment of the present disclosure, a configuration for easily allowing an organic solvent or oxygen plasma gas to penetrate in order to remove the photoresist 14 (sacrificial layer) immediately below the air bridge 30A after flip-chip mounting. In Fig. 7(A), a through via (ground via) connecting the ground surface of the wiring layer 22 on the first surface of the interposer 20 and the ground surface of the wiring layer 23 on the second surface is formed as a via (conformal via) 24G having a through hole that reaches the wiring layer 22 on the first surface to the wiring layer 23 on the second surface while forming a conductor layer while keeping the thickness of the plating film of Al, Cu, etc. constant, and when removing the photoresist 14 (sacrificial layer) immediately below the air bridge 30A, the organic solvent or oxygen plasma is easily allowed to penetrate from the opening of the through via 24G. Although not particularly limited, the diameter of the through via 24 (ground via) G may be on the order of tens of micrometers.

[0041] 7(B) is a diagram showing a schematic arrangement example of the through vias (ground vias) 24G of FIG. 7(A) as viewed from the wiring layer 23 side of the second surface of the interposer 20. In the array of through vias (ground vias) 24G, the pitch may be about 1 / 20 of the signal wavelength λ or less (if the wavelength λ of a signal frequency of 1 GHz (giga-hertz) is 3 cm (centimeter), the pitch is about 750 μm or less at 20 GHz). At least one through via (ground via) 24G may be provided in the vicinity of a quantum bit arranged on the quantum chip 10. By arranging an array of through vias (ground vias) 24G as cavities penetrating the interposer 20, it is possible to allow organic solvents and oxygen plasma gas to pass not only laterally from the side (gap between the quantum chip 10 and the interposer 20) but also uniformly vertically from the second wiring layer 23 of the interposer 20, which contributes to speeding up the removal of the photoresist 14 (sacrificial layer). Note that the through vias (ground vias) 24G are not limited to a regular array arrangement, and may of course be arranged in any pattern.

[0042] FIG. 7C shows an example in which notches 26 are provided at the four corners of the interposer 20 to facilitate penetration of an organic solvent or oxygen plasma in order to remove the photoresist 14 (sacrificial layer) remaining under the air bridge 30A. The notches 26 are not limited to the four corners, and may be provided on the sides or the like adjacent to the unused areas of the interposer 20. In addition, when there is an unused area in the wiring layer 12 of the quantum chip 10, a cavity penetrating the substrate 21 may be provided in the area of ​​the interposer 20 corresponding to the unused area. Note that, for the sake of explanation, FIG. 7C shows an example in which the quantum chip 10 and the interposer 20 have the same planar shape dimensions, but it goes without saying that the present invention is not limited to such a configuration.

[0043] An air bridge can also be used as a multi-layer wiring that does not use an interlayer insulating film that can cause loss. An air bridge can be said to be an interlayer insulating film structure that uses air, and can form low-capacity wiring with a relative dielectric constant of 1. In the layout of the wiring layer 12 of the quantum chip 10, when signal wiring to a quantum bit or a coupler crosses other signal wiring, a three-dimensional wiring structure is usually used in which the wiring is connected to the wiring layer 22 on the first surface on the interposer 20 side by a bump, the wiring is routed on the interposer 20 side, and then returned to the wiring layer 12 side of the quantum chip 10 by a bump again.

[0044] FIG. 8 is a diagram for explaining an example of a wiring pattern of the wiring layer 12 of the quantum chip 10. As described above, the quantum chip 10 is flip-chip mounted on the interposer 20. In FIG. 8, for the sake of explanation, the quantum chip 10 is configured to have terminals on its periphery. FIG. 8 also shows an example in which a Josephson Parametric Oscillator (JPO) is used as a quantum bit included in the superconducting circuit of the quantum chip 10. The coupler CP1 realizes four-body interaction between the four nearest neighboring JPO1 to JPO4 (other JPOs and couplers are omitted). Although not particularly limited, each JPO has a cross-shaped electrode with four arms and is surrounded by the ground surface of the wiring layer 12 with a gap 17 therebetween. Each JPO has a SQUID including Josephson junctions JJ1 and JJ2 in a loop. An IO line 18 extending from an IO (Input-Output) terminal has a coplanar waveguide structure, and its end is a coupling port C that capacitively couples with an electrode of the JPO. A pump line 19 extending from a pump terminal has a coplanar waveguide structure, and its end is a coupling port L that inductively couples (applies a magnetic field) to the SQUID of the JPO. The IO line 18 is used to transmit a signal to the JPO and a signal (reflected signal) from the JPO. The pump line 19 is used to transmit a microwave signal for generating a magnetic field to be applied to the SQUID. The IO line 18 and the pump line 19 are provided with an air bridge 30 that straddles each line from above and electrically connects two ground (GND) surfaces arranged opposite each other on both sides of the longitudinal direction of each line. The coupler CP1 may be configured to include a Josephson junction. Alternatively, the coupler CP1 may be configured to include a SQUID. In this case, a control line for transmitting a DC bias signal for applying a bias magnetic field to the SQUID of the coupler CP1 may be provided. The IO line 18 and the pump line 19 of each JPO are extended to the IO terminal and the pump terminal at intervals so as not to cross each other.In Figure 6, when the wiring of the IO line 18 and the pump line 19 in the quantum chip 10 is crossed, a three-dimensional wiring structure may be used in which one of the wires is extended to the wiring layer 22 on the first surface on the interposer 20 side using a bump, the wiring is routed in the wiring layer 22 on the first surface on the interposer 20 side, and then returned to the wiring layer 12 of the quantum chip 10 via the bump.

[0045] Alternatively, an air bridge may be used to cross a signal wire over another signal wire in the air. For example, in FIG. 10, when the first conductor 12A and the second conductor 12B are the first signal conductors and the conductor 12C is the second signal conductor, the air bridge 30 crosses the second signal conductor 12C across the first signal conductor and the second signal conductor with an air gap therebetween.

[0046] 9, the quantum chip 10 uses an air bridge 30S in the configuration of FIG. 8 to realize crossing of signals on the wiring layer 12 of the quantum chip 10. The pump line 19 connecting the L port of JPO1 and the pump terminal crosses over the IO line 18 connecting the C port of JPO1 and the IO terminal from above at the air bridge 30S. The IO line 18 connecting the C port of JPO4 and the IO terminal crosses over the pump line 19 connecting the L port of JPO4 and the pump terminal from above at the air bridge 30S. The width of the air bridge 30S is the same as the width of the central conductor (conductor 12C in FIG. 10) of the coplanar waveguide structure (for example, when the line width of the central conductor is 10 μm, the width of the air bridge 30S is also 10 μm). Like the air bridge 30 that connects the ground surface across the signal wiring, the air bridge 30S that crosses the signal wiring is flip-chip mounted on the interposer 20 with a photoresist (sacrificial layer) left on the lower part of the air bridge 30S, and then the photoresist (sacrificial layer) is removed from the lower part of the air bridge 30S. According to this embodiment, in addition to the three-dimensional wiring structure of the stacked quantum chip 10 and interposer 20, a further three-dimensional wiring structure can be realized by the air bridge, improving the freedom of wiring and layout in the quantum chip 10, and making it possible to eliminate or reduce the need for detour wiring via the interposer 20 via bumps for signal crossing, thereby enabling effective use of the wiring area of ​​the interposer 20.

[0047] In the above embodiment, an example in which one chip with an air bridge is mounted on an interposer has been described, but a configuration in which multiple chips (at least one of which has an air bridge) are juxtaposed and mounted on one interposer may also be used. In addition, the present invention may be applied to a three-dimensional chip in which multiple chips (at least one of which has an air bridge) are vertically stacked on an interposer. Furthermore, the present invention may also be applied to a configuration in which another chip (daughter chip) is stacked face-to-face on a base chip (mother chip) using bumps (also called "chip-on-chip"). The above-mentioned flip-chip mounting configuration is achieved when the base chip of the chip-on-chip is used as an interposer. In addition, the above-mentioned configuration may also be applied to three-dimensional MMICs (Monolithically Integrated Microwave Integrated Circuits) and the like in addition to superconducting quantum circuits.

[0048] The above-mentioned embodiments are described as follows (but are not limited to the following):

[0049] (Supplementary Note 1) A device comprising: a chip including at least one air bridge on a first surface; and a substrate on which the chip is mounted, the chip being mounted with the first surface facing the substrate.

[0050] (Supplementary Note 2) In the device of Supplementary Note 1, the air bridge is spaced apart in a height direction from the first surface of the substrate by an air gap.

[0051] (Supplementary Note 3) In the device of Supplementary Note 1, the air bridge is at least partially in contact with the first surface of the substrate.

[0052] (Supplementary Note 4) In any one of the devices according to Supplementary Note 1 to 3, the chip includes an air bridge that electrically connects a first ground conductor and a second ground conductor that are disposed on both sides of a conductor extending in one direction on the first surface with a gap therebetween, across the conductor, and / or The air bridge spans a second conductor and crosses the first conductor across an air gap between the second conductor and the air bridge.

[0053] (Supplementary Note 5) In the device of any one of Supplementary Notes 1 to 4, the first surface of the chip and the substrate are joined by bumps.

[0054] (Supplementary Note 6) In the device of any one of Supplementary Notes 1 to 5, the chip comprises a superconducting quantum circuit on the first surface, and the air bridge is made of a superconducting material.

[0055] (Appendix 7) A method for manufacturing a device includes the steps of forming a conductive layer to be an air bridge on a sacrificial layer on a first surface of a chip, forming a pattern, and then removing the sacrificial layer except for a portion under the air bridge; The method includes a step of mounting the chip with the sacrificial layer remaining under the air bridge with the first surface facing a substrate, and then removing the sacrificial layer remaining under the air bridge.

[0056] (Appendix 8) In the method of manufacturing the device of Appendix 7, in addition to the gap between the chip and the substrate, at least one of a through via, a notch, and a cavity provided in the substrate is used as a path for gas and / or solvent for removing the sacrificial layer remaining under the air bridge.

[0057] (Appendix 9) In the method for manufacturing a device according to appendix 7 or 8, when the chip is mounted with the first surface facing a substrate, the air bridge is spaced apart from the substrate in the height direction via a gap, or at least a portion of the air bridge is in contact with the substrate.

[0058] (Supplementary Note 10) In the method for manufacturing a device according to any one of Supplementary Notes 7 to 9, the sacrificial layer is made of photoresist.

[0059] The disclosures of Patent Documents 1 and 2 are incorporated herein by reference. Modifications and adjustments of the embodiments and examples are possible within the scope of the entire disclosure of the present invention (including the scope of claims), and further based on the basic technical ideas. Furthermore, various combinations and selections of the various disclosed elements (including each element of each appendix, each element of each example, each element of each drawing, etc.) are possible within the scope of the claims of the present invention. In other words, the present invention naturally includes various modifications and alterations that a person skilled in the art would be able to make in accordance with the entire disclosure, including the scope of claims, and the technical ideas. [Explanation of symbols]

[0060] 1. Superconducting circuit devices 2 First Fixture (Stage) 2A XY translation mechanism 3 Second Fixture (Stage) 4a, 4b activation device 5. Vacuum Chamber 6 Support part 7 Z direction movement mechanism 8 Z-axis rotation mechanism 9 Vacuum exhaust port 10. Quantum Chip 11 Substrate 12 Superconducting conductor film (wiring layer) 12A First Conductor 12B Second Conductor 12C Signal Conductor 13 Superconducting materials (superconducting conductor films) 13A, 13B Contact part 13C, 13D Bridge pier 13E Bridge girder 14 Photoresist 15A 1st via 15B Second via 16 Photoresist 17 Gap 18 IO lines 19 Pump Line 20 Interposer 21 Substrate 22 First side wiring layer 23 Second side wiring layer 24, 24G Through Via 25 Bump 26 Cutout 30, 30A, 30S Air Bridge

Claims

1. a chip including at least one air bridge on a first surface; A substrate on which the chip is mounted; Equipped with The device, wherein the chip is mounted with the first surface facing the substrate.

2. The device of claim 1 , wherein the air bridge is vertically spaced apart from the substrate by an air gap.

3. The device of claim 1 , wherein the air bridge at least partially abuts the substrate.

4. The chip has, on the first surface, an air bridge that electrically connects a first ground conductor and a second ground conductor that are disposed on both longitudinal sides of a conductor extending in one direction with a gap therebetween, across the conductor; and / or the air bridge spanning a second conductor and crossing the first conductor across an air gap between the second conductor and the first conductor; The device of claim 1 , comprising:

5. The device of claim 1 , wherein the first surface of the chip and the substrate are joined by bumps.

6. the chip comprises a superconducting quantum circuit on the first surface; 6. The device of claim 1, wherein the air bridge is made of a superconducting material.

7. forming a pattern of a conductive layer that will become an air bridge on a sacrificial layer on a first surface of the chip, and then removing the sacrificial layer except for a portion of the sacrificial layer that is below the air bridge; mounting the chip with the sacrificial layer remaining under the air bridge with the first surface facing a substrate, and then removing the sacrificial layer remaining under the air bridge; A method for manufacturing a device comprising:

8. The method for manufacturing a device according to claim 7, further comprising using at least one of a through via, a notch, and a cavity in the substrate, in addition to the gap between the chip and the substrate, as a path for gas and / or solvent for removing the sacrificial layer remaining under the air bridge.

9. With the chip mounted with the first surface facing the substrate, The method for manufacturing a device according to claim 7 , wherein the air bridge is separated from the substrate in a height direction by a gap, or at least a portion of the air bridge abuts against the substrate.

10. The method for manufacturing a device according to claim 7 , wherein the sacrificial layer is made of photoresist.

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