Solar battery and manufacturing method thereof

Abstract

To provide a solar battery and a manufacturing method thereof.SOLUTION: In a manufacturing method of a solar battery (100), an amorphous silicon layer is formed on a tunnel oxide layer (120) on the first side, a doped polysilicon layer (130) is formed in a first step by a diffusion doping process, and a doped oxide layer is formed on the doped polysilicon layer in a second step. After the doped oxide layer is formed, selective re-doping is performed on the first side by a laser doping process to form a selective emitter electrode in a highly doped region.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present application relates to the technical field of photovoltaics, and in particular to solar cells and methods for manufacturing the same. [Background technology]

[0002] In the field of photovoltaic technology, the front side of the TOPCon cell (Tunnel Oxide Passivated Contact cell) is similar to a typical PERC cell (Passivated Emitter and Rear Cell). The feature of the TOPCon cell is that the rear side is provided with a layer of tunnel oxide, and the tunnel oxide layer is provided with a layer of doped polysilicon, both of which together form a passivated contact structure and provide excellent interface passivation to the rear side of the silicon wafer.

[0003] The SE (Selective Emitter) process is a selective emitter electrode technology that performs high-concentration doping (i.e., high-concentration doping) at the contact position between the grid and the silicon wafer, and low-concentration doping (i.e., low-concentration doping) in areas other than the electrode. On the one hand, the selective emitter electrode technology can reduce the contact resistance between the silicon wafer and the grid and reduce the series resistance of the battery, and on the other hand, the low-concentration doping area can reduce the surface complexation and extend the minority carrier lifetime, thus improving the short-circuit current and open-circuit voltage of the battery.

[0004] In the related art, a first silicon layer with low doping is deposited first, a second silicon layer with high doping is deposited on it, and then the second silicon layer in the non-metallization pattern area is removed according to the metallization pattern. Since the second silicon layer and the first silicon layer are essentially both silicon, but the only difference is the doping concentration, regardless of the method used to remove the second silicon layer, the process window is difficult to control and the first silicon layer is also easy to remove, exposing the silicon substrate and eliminating the backside passivation structure. Summary of the Invention

[0005] Therefore, there is a need to provide a solar cell and a method for manufacturing the same that solves the problem that the silicon layer is easily removed in the related process, exposing the silicon substrate and losing the back passivation structure.

[0006] A method for manufacturing a solar cell, comprising the steps of: forming a tunnel oxide layer on a first side of a silicon substrate; forming an amorphous silicon layer on the tunnel oxide layer; performing a diffusion doping process, the process including: a first step of injecting a doping source and an oxygen source into the diffusion chamber and heating the amorphous silicon layer so as to form a doped polysilicon layer in the amorphous silicon layer and a doped oxide layer on the doped polysilicon layer; and a second step of stopping the injection of the doping source and continuing to inject an oxygen source to increase the thickness of the doped oxide layer; forming a highly doped region in the doped polysilicon layer by a laser doping process.

[0007] In one embodiment, the method meets at least one of the following characteristics (1) to (2): (1) In the first step, the process temperature is 820 to 880° C.; (2) In the second step, the process temperature is 850 to 920°C.

[0008] In one embodiment, the method meets at least one of the following characteristics (1) to (2): (1) The doping concentration of the doped polysilicon layer is 1×10 20 atoms / cm 3 ~3×10 21 atoms / cm 3 and the doping concentration of the doped polysilicon layer is 1×10 20 atoms / cm 3 ~3×10 21 atoms / cm 3 and (2) The sheet resistance of the doped polysilicon layer is 25 to 45 ohms.

[0009] In one embodiment, in the second step, the thickness of the doped oxide layer is controlled to be 80 to 120 nm.

[0010] In one embodiment, the method meets at least one of the following characteristics (1) to (2): (1) the tunnel oxide layer has a thickness of 0.5 to 2 nm; (2) The amorphous silicon layer has a thickness of 15 to 40 nm.

[0011] In one embodiment, the method meets at least one of the following characteristics (1) to (3): (1) the wavelength of the light source used in the laser doping process is 350 to 700 nm; (2) the width of the light spot formed in the laser doping process is 60 to 120 nm; (3) The doping concentration of the highly doped region is 2×10 20 atoms / cm 3 ~2×10 21 atoms / cm 3 and (4) The sheet resistance of the heavily doped region is 10 to 25 ohms.

[0012] In one embodiment, after the laser doping process, the manufacturing method further comprises: Further comprising forming a thermal oxide layer on the back surface by a thermal oxidation process.

[0013] In one embodiment, the method meets at least one of the following characteristics (1) to (3): (1) the temperature of the thermal oxidation process is 1000 to 1200°C; (2) the duration of the thermal oxidation process is 4000 to 10000 seconds; (3) The thermally oxidized layer has a thickness of 60 to 200 nm.

[0014] In one embodiment, the method comprises the steps of: The method further includes forming an emitter electrode on a second side of the silicon substrate, the second side being opposite the first side.

[0015] In one embodiment, the method comprises the steps of: Producing a first electrode in contact with the highly doped region; and / or The method further includes the step of fabricating a second electrode in contact with the emitter electrode.

[0016] A solar cell manufactured by the manufacturing method described in any one of the above embodiments.

[0017] The details of one or more embodiments of the application are set forth in the drawings and description below. Other features, objects, and advantages of the application will become apparent from the description, drawings, and claims. [Brief description of the drawings]

[0018] In order to more clearly explain the technical solutions in the embodiments or related technologies of the present application, the following briefly introduces drawings necessary for describing the embodiments or related technologies. Obviously, the drawings described below are only embodiments of the present invention, and those skilled in the art can obtain other drawings based on the disclosed drawings without any creative work. [Figure 1] FIG. 1 is a schematic diagram showing the structure of a solar cell manufactured by a manufacturing method according to one embodiment. [Diagram 2] FIG. 2 is a schematic diagram of the structure of a solar cell manufactured by the manufacturing method of one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] In order to make the above objects, features and advantages of the present invention more clear, specific embodiments of the present invention will be described in detail below with reference to the drawings. In the following description, many specific details will be described in order to fully understand the present invention. However, the present invention can be embodied in many ways different from those described herein, and those skilled in the art can make similar improvements without departing from the scope of the present invention, so the present invention is not limited to the specific embodiments disclosed below.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art of the present application. The terms used in the specification of the present application herein are for the purpose of describing specific examples only and are not intended to be limiting of the present application. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0021] In describing the present invention, the orientations or positional relationships indicated by terms such as "center," "longitudinal," "lateral," "length," "width," "thickness," "up," "down," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like, are based on those shown in the accompanying drawings and are intended merely to facilitate and simplify the description of the present invention, and are not intended to indicate or suggest that the designated devices or elements must have a particular orientation or be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present invention.

[0022] Moreover, the terms "first" and "second" are used for descriptive purposes only and cannot be understood to indicate or imply the relative importance or number of the indicated technical features. Thus, the feature defined by "first" or "second" may be expressly or imply that the feature includes at least one of the feature. In the present description, "plurality" means at least two, e.g., two, three, etc., unless otherwise clearly and specifically limited.

[0023] In the present invention, unless otherwise clearly specified and limited, the terms "attached", "connected", "connected", "fixed" and the like should be broadly understood, and unless otherwise clearly limited, for example, they may be fixedly connected, detachably connected, or integral, may be mechanically connected, may be electrically connected, may be directly connected, may be indirectly connected via an intermediate medium, may be internal communication between two elements, or may be an interactive relationship between two elements. Those skilled in the art may understand the specific meaning of the above terms in the present utility model according to the specific situation.

[0024] In the present application, a method for manufacturing a solar cell is provided. Figures 1 and 2 show a solar cell 100 manufactured by the manufacturing method according to one embodiment.

[0025] A method for manufacturing the solar cell 100 according to an embodiment of the present application includes the following steps.

[0026] A tunnel oxide layer 120 is formed on a first side of a silicon substrate 110 .

[0027] An amorphous silicon layer is formed on the tunnel oxide layer 120 .

[0028] The process of performing the diffusion doping process includes a first process of injecting a doping source and an oxygen source into a diffusion chamber and heating the amorphous silicon layer so as to form a doped polysilicon layer 130 in the amorphous silicon layer and a doped oxide layer 131 on the doped polysilicon layer 130, and a second process of stopping the injection of the doping source and continuing to inject an oxygen source to increase the thickness of the doped oxide layer 131.

[0029] A laser doping process forms a highly doped region 140 in the doped polysilicon layer 130 .

[0030] In the manufacturing method of the solar cell 100, an amorphous silicon layer is formed on the back tunnel oxide layer 120, and a doped polysilicon layer 130 is formed in the first step by a diffusion doping process, and a doped oxide layer 131 is formed on the doped polysilicon layer 130 in the second step. After the doped oxide layer 131 is formed, selective re-doping of the back side is realized by a laser doping process, and the highly doped region 140 forms a selective emitter electrode. On the one hand, the doped oxide layer 131 can provide sufficient impurity ions for SE doping, and on the other hand, the doped oxide layer 131 can protect the tunnel oxide layer 120, reduce or avoid the destruction of the tunnel oxide layer 120 in the laser doping SE process, and have a good passivation effect.

[0031] In addition, due to the protective effect of the doped oxide layer 131, it is advantageous to make the doped polysilicon layer 130 thinner. Reducing the thickness of the doped polysilicon layer 130 can significantly reduce the parasitic absorption in the long wavelength band and increase the short circuit current of the solar cell 100.

[0032] In one example manufacturing method, an emitter electrode 150 is formed on a second side of the silicon substrate 110, the second side being opposite the first side.

[0033] The emitter electrode 150 can be formed by doping the second side with impurity ions, and a PN junction is formed between the emitter electrode 150 and the silicon substrate 110. For example, the silicon substrate 110 can be an N-type silicon, and the emitter electrode 150 can be a P+ doped layer formed by a boron diffusion process.

[0034] In one example, before forming the emitter electrode 150, the silicon substrate 110 can be texture-cleaned to form a suede structure on the second side to provide anti-reflection effect.

[0035] In one example manufacturing method, a first passivation layer 160 is formed on the emitter electrode 150. In one example, the first passivation layer 160 includes an aluminum oxide layer 161 and a first silicon nitride layer 162, where the aluminum oxide layer 161 is located between the emitter electrode 150 and the first silicon nitride layer 162.

[0036] Heavy doping of the amorphous silicon layer on the back side of the solar cell 100 will cause large parasitic absorption, so the doped polysilicon layer 130 needs to be thin, but at the same time, it needs to be thin enough to prevent the sintering window of the slurry from being burned out. Therefore, the related deposition process, diffusion process and laser parameters are the key to the back side SE technology of the solar cell 100.

[0037] In one example, the tunnel oxide layer 120 is deposited using a CVD process, and in one example, is deposited using an LPCVD (Low Pressure Chemical Vapor Deposition) process. As can be appreciated, O2 may be used as a precursor for the tunnel oxide layer 120.

[0038] In one embodiment, the deposition process parameters for the tunnel oxide layer 120 are: pressure is 740-780 torr, in one embodiment, 755-765 torr, and in one embodiment, more preferably 760 torr; temperature is 550-650° C., in one embodiment, 590-610° C., and in one embodiment, 600° C.; oxygen source flow is 20,000-40,000 sccm, in one embodiment, 25,000-35,000 sccm, and in one embodiment, 30,000 sccm; time is 500-1,500 seconds, in one embodiment, 900-1,100 seconds, and in one embodiment, 1,000 seconds.

[0039] In one example, the tunnel oxide layer 120 has a thickness of 0.5 to 2 nm, and in one example, the tunnel oxide layer 120 has a thickness of 1.5 nm.

[0040] In one example, the amorphous silicon layer is deposited using a CVD process, and in one example, is deposited using a LPCVD process. As can be appreciated, SiH4 may be used as a precursor for the amorphous silicon layer.

[0041] In one embodiment, the deposition process parameters for the amorphous silicon layer are: pressure is 0.1-1 torr, in one embodiment 0.2-0.4 torr, and in one embodiment 0.3 torr; temperature is 550-650°C, in one embodiment 590-610°C, and in one embodiment 600°C; SiH4 flow is 500-2000 sccm, in one embodiment 1300-1500 sccm, and in one embodiment 1400 sccm; time is 150-400 seconds, in one embodiment 180-220 seconds, and in one embodiment 200 seconds.

[0042] In one example, the thickness of the amorphous silicon layer is 15 nm or more, for example, 15-40 nm. Research has shown that an amorphous silicon layer with a thickness of about 15 nm can meet the passivation requirements of the battery, and increasing the thickness of the amorphous silicon layer can avoid burning out the amorphous silicon layer during the metallization process. In one example, the thickness of the amorphous silicon layer is 15-20 nm. In one example, the thickness of the amorphous silicon layer is 20 nm. In this example, the thickness of the amorphous silicon layer is set in the range of 15-40 nm, which can greatly reduce the parasitic absorption in the long wavelength band and increase the short circuit current of the solar cell 100.

[0043] In the first step of the diffusion doping process, a doping source and an oxygen source are injected and deposited, and thermal diffusion is performed to dope the amorphous silicon layer to form the doped polysilicon layer 130 .

[0044] In one example, the doping source is a phosphorus source, such as phosphorus oxychloride, to provide phosphorus doping to the amorphous silicon layer.

[0045] In the first step, the method of injecting the doping source is to inject nitrogen and allow the liquid doping source in the source bottle, such as phosphorus oxychloride, to be introduced into the furnace tube by nitrogen.

[0046] In one example, the process temperature in the first step is 820-880° C., in another example, 860-880° C., and in another example, 870° C. In this example, the diffusion temperature is lower than that in the conventional process, to prevent the internal expansion of the doping source from being too severe when the amorphous silicon layer becomes thin, thereby preventing the passivation structure from being destroyed.

[0047] In one example, the process parameters of the first step are: The nitrogen flow is 500-1500 sccm, and in one example, 800-1200 sccm, and in one example, 1000 sccm. The oxygen source flow is 500-1500 sccm, and in one example, 900-1100 sccm, and in one example, 1000 sccm. The pressure is 100-500 torr, and in one example, 150-250 torr, and in one example, 200 torr. The time is 400-2000 seconds, and in one example, 600-1000 seconds, and in one example, 800 seconds.

[0048] In the second step of the diffusion doping process, an oxygen source is injected to form a doped oxide layer 131 in the doped polysilicon layer 130. In the second step, the doping source is no longer injected, and the main purpose is to form a thick doped oxide layer 131.

[0049] For example, when the doping source is a phosphorus source, specifically phosphorus oxychloride, the formed doped oxide layer 131 is a phosphosilicate glass layer (PSG layer).

[0050] In one example, the process parameters of the second step are: temperature is 850-920°C, in one example, 865-875°C, and in one example, 870°C; oxygen source flow is 1000-4000sccm, in one example, 1500-2500sccm, and in one example, 2000sccm; pressure is 100-500torr, in one example, 350-450torr, and in one example, 400torr; time is 2000-5000 seconds, in one example, 2500-3500 seconds, and in one example, 3000 seconds.

[0051] In one example, the thickness of the doped oxide layer 131 is 80-120 nm. In one example, the thickness of the doped oxide layer 131 is 90-110 nm. In one example, the thickness of the doped oxide layer 131 is 100 nm. On the one hand, the thick doped oxide layer 131 can provide sufficient impurity ions for laser doping to form SE cell pieces, and on the other hand, the doped oxide layer 131 with this thickness can protect the tunnel oxide layer 120 from being destroyed during the laser doping process, and can have an excellent passivation effect.

[0052] In one example, the doping concentration of the doped polysilicon layer 130 is 1×10 20 atoms / cm 3 ~3×10 21 atoms / cm 3 In one example, 21 atoms / cm 3 ~2.5×10 21 atoms / cm 3 In one example, 21 atoms / cm 3 It is.

[0053] In one example, the sheet resistance of the doped polysilicon layer 130 is 25-45 ohms, in one example, 32-38 ohms, and in one example, 35 ohms.

[0054] After forming the doped oxide layer 131, selective re-doping of the rear surface of the silicon substrate is realized using a laser method, and the heavily doped region 140 forms a selective emitter electrode.

[0055] In one example, the light source wavelength used in the laser doping process is 350 to 700 nm. In one example, the light source wavelength used in the laser doping process is 532 nm (green light). In one example, the light source wavelength used in the laser doping process is 355 nm (violet light).

[0056] In one example, the width of the light spot formed in the laser doping process is 60 to 120 nm. In one example, the light spot formed in the laser doping process is a square spot with a width of 80 nm.

[0057] In one example, the doping concentration of the heavily doped region 140 is 2×10 20 atoms / cm 3 ~2×10 21 atoms / cm 3 In one example, 20 atoms / cm 3 ~1×10 21 atoms / cm 3 In one example, 20 atoms / cm 3 It is.

[0058] In one example, the sheet resistance of the heavily doped region 140 is between 10 and 25 ohms, in one example, between 13 and 17 ohms, and in one example, 15 ohms.

[0059] In one example of the manufacturing method, after the laser doping process, the method further includes forming a thermal oxide layer on the back surface of the silicon substrate by a thermal oxidation process.

[0060] In the above example, a single thermal oxide layer 170 is generated by thermal oxidation based on the rear surface SE, and the thermal oxide layer 170 can serve as a barrier layer for the metal slurry to avoid burning out the doped polysilicon layer 130. Meanwhile, the thermal oxide layer 170 grown by thermal oxygen is also an excellent passivation material and can play an auxiliary role in passivation.

[0061] In one example, the process parameters of the thermal oxidation process are a temperature of 1000 to 1200° C. and a time of 4000 to 10000 seconds.

[0062] The thermal oxide layer has a consistent thickness to ensure that the doped polysilicon layer 130 is not burned through. In one example, the thickness of the thermal oxide layer is between 60 and 200 nm, in one example, between 70 and 100 nm, and in one example, 80 nm.

[0063] In one example manufacturing method, an etching cleaning process is used to remove the doped oxide layer 131 and the doped polysilicon layer 130 on the second side and the side surfaces of the silicon substrate 110. The etching cleaning process may be performed after the laser doping process or after the thermal oxidation process.

[0064] In one example manufacturing method, a second passivation layer 180 is deposited on the backside. In one example, the second passivation layer 180 comprises a second silicon nitride layer. The step of depositing the second passivation layer 180 may be after the laser doping process, or after the thermal oxidation process, or after the etching cleaning process.

[0065] The solar cell 100 may be, but is not limited to, a TOPCon cell.

[0066] In the above-mentioned method for manufacturing the solar cell 100, an amorphous silicon layer is formed on the back tunnel oxide layer 120, and a doped polysilicon layer 130 is formed in a first step by a diffusion doping process, and a doped oxide layer 131 is formed on the doped polysilicon layer 130 in a second step. After the doped oxide layer 131 is formed, selective re-doping of the back side is realized by a laser doping process, and the highly doped region 140 forms a selective emitter electrode. On the one hand, the doped oxide layer 131 can provide sufficient impurity ions for laser doping, and on the other hand, the doped oxide layer 131 can protect the tunnel oxide layer 120, reduce or avoid the destruction of the tunnel oxide layer 120 in the laser doping process, and have a good passivation effect.

[0067] In addition, due to the protective effect of the doped oxide layer 131, it is advantageous to make the doped polysilicon layer 130 thinner. Reducing the thickness of the doped polysilicon layer 130 can significantly reduce the parasitic absorption in the long wavelength band and increase the short circuit current of the solar cell 100.

[0068] The present application has a simple process, is easy to control the process, and the above manufacturing process, regardless of complex mask or related graphical processes, can meet the mass production requirements, improve efficiency, and at the same time greatly reduce production costs.

[0069] Furthermore, the present application further provides a solar cell manufactured by any one of the above examples of the manufacturing method.

[0070] Hereinafter, specific examples are provided to further illustrate the present application. Example 1

[0071] In this embodiment, a method for manufacturing a solar cell is provided, which includes the following steps.

[0072] Texture cleaning S1: Provide an N-type silicon wafer, and form a pyramid texture on the front side of the N-type silicon wafer through an alkaline cleaning process.

[0073] Boron diffusion S2: A boron diffusion process is performed on the front side of the N-type silicon wafer to fabricate the emitter electrode and form a PN junction.

[0074] Back-etching S3: The PN junction plating on the back surface of the N-type silicon wafer is cleaned, and the back surface of the N-type silicon wafer is polished.

[0075] LPCVD S4: A tunnel silicon oxide layer and an amorphous silicon layer are sequentially deposited by LPCVD.

[0076] For depositing the tunnel silicon oxide layer, the process parameters are pressure 760 torr, temperature 600° C., oxygen flow 30000 sccm, and time 1000 seconds.

[0077] The thickness of the formed tunnel oxide layer is 1.5 nm.

[0078] For depositing the amorphous silicon layer, the process parameters were: pressure 0.3 torr, temperature 600° C., SiH 4 flow 1400 sccm, and time 200 seconds.

[0079] The thickness of the formed amorphous silicon layer is 20 nm. Phosphorus Diffusion S5: A phosphorus diffusion process is performed on the backside of the N-type silicon wafer to form an N-type doped polysilicon layer (n-poly).

[0080] Phosphorus diffusion is mainly divided into the first and second processes.

[0081] In the first step, phosphorus source and oxygen are injected to deposit and simultaneously promote phosphorus doping at high temperature. The injection of phosphorus source is performed by introducing liquid phosphorus oxychloride in a source bottle into a furnace tube by nitrogen.

[0082] The process parameters for the first step were deposition temperature 860° C., nitrogen flow 1000 sccm, oxygen flow 1000 sccm, pressure 200 torr, and time 800 seconds.

[0083] In the second process, oxygen is injected but no phosphorus source is injected, with the main objective of forming a thick PSG layer.

[0084] The process parameters for the second step were deposition temperature 870° C., oxygen flow 2000 sccm, pressure 400 torr, and time 3000 seconds.

[0085] The PSG layer formed by this phosphorus diffusion process has a thickness of 100 nm and a doping concentration of 2×10 20 atoms / cm 3 , and the sheet resistance is 35 ohms.

[0086] Back laser SE S6: The back grid is re-doped by a laser to form a selective emitter electrode.

[0087] The process uses a 532 nm green laser. The light spot is a square spot with a width of 80 nm. The doping concentration of the highly doped region is 8×10 20 atoms / cm 3 The sheet resistance of the highly doped region is 15 ohms.

[0088] Thermal Oxidation S7: Grow a layer of thermal oxide on the backside of the N-type silicon wafer in a tubular thermal oxidation furnace tube.

[0089] The process parameters are a temperature of 1100° C. and a time of 8000 seconds.

[0090] The thickness of the thermal oxide layer is 80 nm.

[0091] Etching cleaning S8: The PSG layer and the amorphous silicon layer on the front and side surfaces are cleaned and removed by the chain polishing method and the groove polishing method.

[0092] Paint S9: An aluminum oxide layer and a first silicon nitride layer are sequentially deposited on the front side of an N-type silicon wafer, and a second silicon nitride layer is deposited on the back side.

[0093] Metallization S10: Print silver-aluminum paste on the front side of an N-type silicon wafer, print silver paste on the back side, and obtain grid lines by metallization via high-temperature sintering. Example 2

[0094] In this embodiment, A texture cleaning S1 is performed by providing a monocrystalline silicon wafer and forming a pyramid texture on the front surface of the monocrystalline silicon wafer through an alkaline cleaning process; A boron diffusion process is carried out on the front side of the single crystal silicon wafer to manufacture the emitter electrode and form the PN junction; Back-etching S3, which cleans the PN junction plating on the back surface of the single crystal silicon wafer and polishes the back surface of the single crystal silicon wafer; and S4 depositing a tunnel silicon oxide layer and an amorphous silicon layer in sequence by LPCVD.

[0095] For depositing the tunnel silicon oxide layer, the process parameters are pressure 760 torr, temperature 600° C., oxygen flow 30000 sccm, and time 1000 seconds.

[0096] The thickness of the formed tunnel oxide layer is 1.5 nm.

[0097] For depositing the amorphous silicon layer, the process parameters were: pressure 0.3 torr, temperature 600° C., SiH 4 flow 1400 sccm, and time 200 seconds.

[0098] The thickness of the formed amorphous silicon layer is 20 nm.

[0099] Phosphorus Diffusion S5: A phosphorus diffusion process is performed on the back side of the single crystal silicon wafer to form an N-type doped polysilicon layer (n-poly).

[0100] Phosphorus diffusion is mainly divided into the first and second processes.

[0101] In the first step, phosphorus source and oxygen are injected to deposit and simultaneously promote phosphorus doping at high temperature. The injection of phosphorus source is performed by introducing liquid phosphorus oxychloride in a source bottle into a furnace tube by nitrogen.

[0102] The process parameters for the first step were deposition temperature 860° C., nitrogen flow 1000 sccm, oxygen flow 1000 sccm, pressure 200 torr, and time 800 seconds.

[0103] In the second process, oxygen is injected but no phosphorus source is injected, with the main objective of forming a thick PSG layer.

[0104] The process parameters for the second step were deposition temperature 870° C., oxygen flow 2000 sccm, pressure 400 torr, and time 1000 seconds.

[0105] The PSG layer formed by this phosphorus diffusion process has a thickness of 100 nm and a doping concentration of 2×10 20 atoms / cm 3 , and the sheet resistance is 35 ohms.

[0106] Back laser SE S6: The back grid is re-doped by a laser to form a selective emitter electrode.

[0107] The process uses a 532 nm green laser. The light spot is a square spot with a width of 80 nm. The doping concentration of the highly doped region is 8×10 20 atoms / cm 3 The sheet resistance of the highly doped region is 15 ohms.

[0108] Thermal Oxidation S7: A layer of thermal oxide is grown on the back side of the single crystal silicon wafer in a tubular thermal oxidation furnace tube.

[0109] The process parameters are a temperature of 1100° C. and a time of 8000 seconds.

[0110] The thickness of the thermal oxide layer is 80 nm.

[0111] Etching cleaning S8: The PSG layer and the amorphous silicon layer on the front and side surfaces are cleaned and removed by the chain polishing method and the groove polishing method.

[0112] Coating S9: An aluminum oxide layer and a first silicon nitride layer are deposited in sequence on the front side, and a second silicon nitride layer is deposited on the rear side.

[0113] Metallization S10: Print silver-aluminum paste on the front side, print silver paste on the back side, and metallize by high-temperature sintering to obtain a grid. Comparative Example 1

[0114] The method for manufacturing a solar cell of this comparative example includes the following steps.

[0115] Texture cleaning S1: Provide a monocrystalline silicon wafer, and form a pyramid texture on the front side of the monocrystalline silicon wafer through an alkaline cleaning process.

[0116] Boron diffusion S2: A boron diffusion process is performed on the front side of the single crystal silicon wafer to fabricate the emitter electrode and form the PN junction.

[0117] Back-etching S3: Clean the PN junction plating on the back surface of the single crystal silicon wafer, and polish the back surface of the single crystal silicon wafer.

[0118] LPCVD S4: A tunnel silicon oxide layer and an amorphous silicon layer are sequentially deposited by LPCVD.

[0119] For depositing the tunnel silicon oxide layer, the process parameters are pressure 760 torr, temperature 600° C., oxygen flow 30000 sccm, and time 1000 seconds.

[0120] The thickness of the formed tunnel oxide layer is 1.5 nm.

[0121] For depositing the amorphous silicon layer, the process parameters were: pressure 0.3 torr, temperature 600° C., SiH 4 flow 1400 sccm, and time 1200 seconds.

[0122] The thickness of the formed amorphous silicon layer is 120 nm.

[0123] Phosphorus Diffusion S5: A phosphorus diffusion process is performed on the backside of the N-type silicon wafer to form an N-type doped polysilicon layer (n-poly).

[0124] Phosphorus diffusion is mainly divided into the first and second processes.

[0125] In the first step, phosphorus source and oxygen are injected to deposit and simultaneously promote phosphorus doping at high temperature. The injection of phosphorus source is performed by introducing liquid phosphorus oxychloride in a source bottle into a furnace tube by nitrogen.

[0126] The process parameters for the first step were deposition temperature 860° C., nitrogen flow 1000 sccm, oxygen flow 1000 sccm, pressure 200 torr, and time 800 seconds.

[0127] In the second step, oxygen is injected and no phosphorus source is injected.

[0128] The process parameters for the second step were deposition temperature 870° C., oxygen flow 2000 sccm, pressure 400 torr, and time 1000 seconds.

[0129] The PSG layer formed by this phosphorus diffusion process has a thickness of 100 nm and a doping concentration of 2×10 20 atoms / cm 3 , and the sheet resistance is 35 ohms.

[0130] Etching cleaning S6: The PSG layer and the amorphous silicon layer on the front and side surfaces are cleaned and removed by the chain polishing method and the groove polishing method.

[0131] Coating S7: An aluminum oxide layer and a first silicon nitride layer are successively deposited on the front side, and a second silicon nitride layer is deposited on the rear side.

[0132] Metallization S8: Print silver-aluminum paste on the front side and silver paste on the back side, then metallize by high-temperature sintering to obtain a grid. Comparative Example 2

[0133] The method for manufacturing a solar cell of this comparative example includes the following steps.

[0134] Texture cleaning S1: Provide a monocrystalline silicon wafer, and form a pyramid texture on the front side of the monocrystalline silicon wafer through an alkaline cleaning process.

[0135] Boron diffusion S2: A boron diffusion process is performed on the front side of the single crystal silicon wafer to fabricate the emitter electrode and form the PN junction.

[0136] Back-etching S3: Clean the PN junction plating on the back surface of the single crystal silicon wafer, and polish the back surface of the single crystal silicon wafer.

[0137] LPCVD S4: A tunnel silicon oxide layer and an amorphous silicon layer are sequentially deposited by LPCVD.

[0138] For depositing the tunnel silicon oxide layer, the process parameters are pressure 760 torr, temperature 600° C., oxygen flow 30000 sccm, and time 1000 seconds.

[0139] The thickness of the formed tunnel oxide layer is 1.5 nm.

[0140] For depositing the amorphous silicon layer, the process parameters were: pressure 0.3 torr, temperature 600° C., SiH 4 flow 1400 sccm, and time 200 seconds.

[0141] The thickness of the formed amorphous silicon layer is 20 nm.

[0142] Phosphorus Diffusion S5: A phosphorus diffusion process is performed on the back side of the single crystal silicon wafer to form an N-type doped polysilicon layer (n-poly).

[0143] Phosphorus diffusion is mainly divided into the first and second processes.

[0144] In the first step, phosphorus source and oxygen are injected to deposit and simultaneously promote phosphorus doping at high temperature. The injection of phosphorus source is performed by introducing liquid phosphorus oxychloride in a source bottle into a furnace tube by nitrogen.

[0145] The process parameters for the first step were deposition temperature 860° C., nitrogen flow 1000 sccm, oxygen flow 1000 sccm, pressure 200 torr, and time 800 seconds.

[0146] In the second step, oxygen is injected and no phosphorus source is injected.

[0147] The process parameters for the second step were deposition temperature 870° C., oxygen flow 2000 sccm, pressure 400 torr, and time 1000 seconds.

[0148] The PSG layer formed by this phosphorus diffusion process has a thickness of 100 nm and a doping concentration of 2×10 20 atoms / cm 3 , and the sheet resistance is 35 ohms.

[0149] Etching cleaning S6: The PSG layer and the amorphous silicon layer on the front and side are removed by chain and tank cleaning.

[0150] Coating S7: An aluminum oxide layer and a first silicon nitride layer are successively deposited on the front side, and a second silicon nitride layer is deposited on the rear side.

[0151] Metallization S8: Print silver-aluminum paste on the front side and silver paste on the back side, then metallize by high-temperature sintering to obtain a grid. Comparative Example 3

[0152] The method for manufacturing a solar cell of this comparative example includes the following steps.

[0153] Texture cleaning S1: Provide a monocrystalline silicon wafer, and form a pyramid texture on the front side of the monocrystalline silicon wafer through an alkaline cleaning process.

[0154] Boron diffusion S2: A boron diffusion process is performed on the front side of the single crystal silicon wafer to fabricate the emitter electrode and form the PN junction.

[0155] Back-etching S3: Clean the PN junction plating on the back surface of the single crystal silicon wafer, and polish the back surface of the single crystal silicon wafer.

[0156] LPCVD S4: A tunnel silicon oxide layer and an amorphous silicon layer are sequentially deposited by LPCVD.

[0157] For depositing the tunnel silicon oxide layer, the process parameters are pressure 760 torr, temperature 600° C., oxygen flow 30000 sccm, and time 1000 seconds.

[0158] The thickness of the formed tunnel oxide layer is 1.5 nm.

[0159] For depositing the amorphous silicon layer, the process parameters were: pressure 0.3 torr, temperature 600° C., SiH 4 flow 1400 sccm, and time 200 seconds.

[0160] The thickness of the formed amorphous silicon layer is 20 nm.

[0161] Phosphorus Diffusion S5: A phosphorus diffusion process is performed on the back side of the single crystal silicon wafer to form an N-type doped polysilicon layer (n-poly).

[0162] Phosphorus diffusion is mainly divided into the first and second processes.

[0163] In the first step, phosphorus source and oxygen are injected to deposit and simultaneously promote phosphorus doping at high temperature. The injection of phosphorus source is performed by introducing liquid phosphorus oxychloride in a source bottle into a furnace tube by nitrogen.

[0164] The process parameters for the first step were deposition temperature 860° C., nitrogen flow 1000 sccm, oxygen flow 1000 sccm, pressure 200 torr, and time 800 seconds.

[0165] In the second step, oxygen is injected and no phosphorus source is injected.

[0166] The process parameters for the second step were deposition temperature 870° C., oxygen flow 2000 sccm, pressure 400 torr, and time 1000 seconds.

[0167] The PSG layer formed by this phosphorus diffusion process has a thickness of 100 nm and a doping concentration of 2×10 20 atoms / cm 3 , and the sheet resistance is 35 ohms.

[0168] Thermal Oxidation S6: A layer of thermal oxide is grown on the backside using a tubular thermal oxidation furnace tube.

[0169] The process parameters are a temperature of 1100° C. and a time of 8000 seconds.

[0170] The thickness of the thermal oxide layer is 80 nm.

[0171] Etching cleaning S8: The PSG layer and the amorphous silicon layer on the front and side are removed by chain and tank cleaning.

[0172] Coating S9: An aluminum oxide layer and a first silicon nitride layer are deposited in sequence on the front side, and a second silicon nitride layer is deposited on the rear side.

[0173] Metallization S10: Print silver-aluminum paste on the front side, print silver paste on the back side, and metallize by high-temperature sintering to obtain a grid.

[0174] The differences between the above-mentioned Examples 1 and 2 and Comparative Examples 1 to 3 are shown in Table 1. Table 1 Differences between Examples 1-2 and Comparative Examples 1-3 JPEG2025026350000002.jpg45170

[0175] Electrical performance tests were conducted on the solar cells manufactured in Examples 1-2 and Comparative Examples 1-3, and the results are shown in Table 2. The test method was performed with reference to IEC TS 63202-3 Photovoltaic cells-Part 3: Measurement of current-voltage characteristics of bicial photovoltaic cells established and published by the International Electrotechnical Commission.

[0176] Table 2 Electrical performance of the solar cells manufactured in Examples 1-2 and Comparative Examples 1-3 JPEG2025026350000003.jpg42170

[0177] As can be seen from the test results in Table 2, the thickness of the doped polysilicon layer in Comparative Example 1 is thicker than that in Comparative Example 2, so the parasitic absorption is severe and the short circuit current is low. In Comparative Example 2, the thickness of the doped polysilicon layer is thin, but the open circuit voltage is seriously reduced compared to Comparative Example 1. This is simply because the doped polysilicon layer is thin and the current gain is relatively large, but the silver paste on the back side burns through the doped polysilicon layer and directly contacts the silicon substrate, causing a large amount of compounding, which further reduces the open circuit voltage.

[0178] In Comparative Example 3, a thicker thermal oxide layer is grown on the doped polysilicon layer than in Comparative Example 2, and the high-density thermal oxide layer provides excellent barrier and passivation effects, so that a high current amplification can be obtained while maintaining a high open circuit voltage.

[0179] In both examples 1 and 2, a PSG layer is formed on the doped polysilicon layer, and a laser doping process is performed in parallel. From the electrical results, the open circuit voltage of examples 1 and 2 is obviously improved, at least by 7 mV, compared to comparative examples 1 to 3. Compared with example 1 and example 2, example 2 forms a PSG layer to provide a certain protection for the doped polysilicon layer, but because the thickness is thin, the laser still causes a certain damage to the tunnel silicon oxide layer during the laser doping process, which makes the open circuit voltage of example 2 relatively low.

[0180] The technical features of the above-mentioned embodiments may be combined in any desired manner. For the sake of brevity, not all possible combinations of the technical features in the above-mentioned embodiments have been described. However, as long as there is no contradiction in the combination of these technical features, any combination should be considered to be within the scope of the present specification.

[0181] The above examples only show some embodiments of the present invention, and the description is specific and detailed, but it should not be understood as limiting the patent scope of the present invention. It should be noted that those skilled in the art can make some modifications and improvements without departing from the idea of ​​the present application, all of which are within the scope of protection of the present application. Therefore, the scope of protection of the present invention patent should be based on the appended claims, and the specification is used to explain the content of the claims. [Explanation of symbols]

[0182] 100, solar cell 110, silicon substrate 120, tunnel oxide layer 130, doped polysilicon layer 131, doped oxide layer 140, Highly doped region 150, emitter electrode 160, first passivation layer 161. Aluminum oxide layer 162, first silicon nitride layer 170. Thermal oxidation layer 180. Second passivation layer 191. First electrode 192. Second electrode

Claims

1. A method for manufacturing a solar cell, comprising the steps of: forming a tunnel oxide layer on a first side of a silicon substrate; forming an amorphous silicon layer on the tunnel oxide layer; A process of performing a diffusion doping treatment on an amorphous silicon layer, the process comprising: a first step of injecting a doping source and an oxygen source into a diffusion chamber and heating the amorphous silicon layer so as to form a doped polysilicon layer in the amorphous silicon layer and a doped oxide layer on the doped polysilicon layer; and a second step of stopping the injection of the doping source and continuing to inject an oxygen source to increase a thickness of the doped oxide layer; forming a highly doped region in the doped polysilicon layer by a laser doping process. A method for producing a solar cell comprising the steps of:

2. The manufacturing method meets at least one of the following characteristics (1) to (2): (1) In the first step, the process temperature is 820 to 880° C.; (2) In the second step, the process temperature is 850 to 920° C. The method for producing a solar cell according to claim 1 .

3. In the second step, the thickness of the doped oxide layer is controlled to be 80 to 120 nm. The method for producing a solar cell according to claim 1 .

4. The manufacturing method meets at least one of the following characteristics (1) to (2): (1) the tunnel oxide layer has a thickness of 0.5 to 2 nm; (2) The thickness of the amorphous silicon layer is 15 to 40 nm. The method for producing a solar cell according to claim 1 .

5. The manufacturing method meets at least one of the following characteristics (1) to (3): (1) the wavelength of the light source used in the laser doping process is 350 to 700 nm; (2) the width of the light spot formed in the laser doping process is 60-120 nm; (3) The doping concentration of the highly doped region is 2×10 ２０ atoms / cm ３ ~2×10 ２１ atoms / cm ３ and (4) The sheet resistance of the highly doped region is 10 to 25 ohms. The method for producing a solar cell according to claim 1 .

6. After the laser doping process, the method further comprises: Further comprising forming a thermal oxide layer on the back surface by a thermal oxidation process. The method for producing a solar cell according to claim 1 .

7. The manufacturing method meets at least one of the following characteristics (1) to (3): (1) the temperature of the thermal oxidation process is 1000 to 1200° C.; (2) the duration of the thermal oxidation process is 4,000 to 10,000 seconds; (3) The thickness of the thermally oxidized layer is 60 to 200 nm. The method for producing a solar cell according to claim 6 .

8. The manufacturing method includes: forming an emitter electrode on a second side of the silicon substrate, the second side being disposed opposite the first side; The method for producing a solar cell according to claim 1 .

9. The manufacturing method includes: Producing a first electrode in contact with the highly doped region; and / or The method further includes the step of manufacturing a second electrode in contact with the emitter electrode. The method for producing a solar cell according to claim 8 .

10. A solar cell comprising: Produced by the method according to any one of claims 1 to 9. A solar cell characterized by:

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