Prediction of failure probabilities of chips of wafer

Abstract

To provide a method (100) for training a machine learning system to predict failure probabilities of chips on a wafer.SOLUTION: A method is based on prediction (103) of final test yields depending on wafer-level test measurements by a machine learning system. The machine learning system predicts failure probabilities of chips depending on the wafer-level test measurements, and the predicted failure probabilities are aggregated to the predicted final test yields. The method is also based on training (104) the machine learning system such that a math difference between the predicted final test yields and final test yields from a training data set is minimized.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a method for training a machine learning system to predict the probability of failure of chips on a wafer, and a method for predicting the probability of failure of the chips by a trained machine learning system. [Background technology]

[0002] Prior Art Basically, it is known that machine learning (abbreviated ML) and machine learning methods can be suitable for predicting defects in components during manufacture.

[0003] Currently, predicting the failure or defect probability of individual semiconductor chips during final inspection based on wafer level measurements is not possible due to the lack of traceability between processes. In particular, the association between the individual chips on which wafer level measurements are performed and the Final Test to which they belong after wafer cutting is lost, making supervised model training impossible. Summary of the Invention [Problem to be solved by the invention]

[0004] It is therefore an object of the present invention to predict the probability that an individual chip is defective based on wafer level test measurements.

[0005] Advantages of the invention By predicting the failure probability, chips with high failure probabilities can be removed early in the manufacturing process, or depending on the failure probabilities of all chips in a lot, an intelligent combination of chips in a final product can be identified that will result in a lower failure probability in the final product.

[0006] Therefore, in accordance with the present invention, it is possible to reduce waste disposal, post-processing, and additional costs associated with the manufacture and shipping of defective products. By identifying and eliminating defects early, manufacturers can improve product quality and reduce reject rates. [Means for solving the problem]

[0007] Disclosure of the Invention In a first aspect, the present invention relates to a method for training a machine learning system to predict the failure probability of chips on a wafer during final level test or, in particular, during subsequent operation of the chips.

[0008] The method begins by providing a training data set that includes wafer-level test measurements and respective assigned final test yields for a number of wafers, which may be understood to be the quotient of the number of chips on a wafer that pass the final test to the total number of chips on the wafer that are tested in the final test.

[0009] This is followed by multiple iterations of the following steps:

[0010] Specifically for a repeat / batch, a step of extracting preferably a complete wafer-level lot of wafer-level test measurements and the FT lot to which the final test yield belongs.

[0011] Predicting a final test yield dependent on the wafer-level test measurements by a machine learning system, where the machine learning system predicts failure probabilities of the chips dependent on the wafer-level test measurements, and these predicted failure probabilities are aggregated into a predicted final test yield.

[0012] Training the machine learning system to minimize the mathematical difference between the predicted final test yield and the assigned final test yield.

[0013] What is surprising here is that, through the actual simplified training task of yield prediction, it is also learned during training which chips have high or low failure probabilities and whether these chips substantially correspond to the actual failure probabilities on the validation data set.

[0014] The invention in its first aspect can be used to color code defective chips already at an early stage in the manufacturing process, so that they are not processed further or can be removed after the dicing process (=cutting the individual chips from the wafer). Another application is the use of failure probability to perform intelligent sorting where multiple chips with high failure probability are packaged together, thereby reducing the risk that multiple good chips are packaged with one bad chip and the whole package is removed.

[0015] Furthermore, it is envisaged within the framework of the present invention that the allocation of multiple components to functional units includes a classification into at least two or three different classes corresponding to the probability of occurrence of a failure or defect.

[0016] Furthermore, within the scope of the present invention, the allocation is preferably implemented so that the integration of components into functional units is dependent on their class, whereby each functional unit preferably only has components of the same class, whereby the probability that, at the time of removal, in particular disposal, of an entire functional unit, it contains more than one defective component is increased. Alternatively or additionally, the allocation is preferably implemented so that the integration of components into functional units is dependent on their probability of occurrence of a failure in the functional unit, whereby the probability that, in the event of a functional unit failure, more than one defective component in the functional unit is the cause of this failure is maximized.

[0017] The subject of the invention is likewise a computer program, in particular a computer program product, comprising instructions for causing a computer to carry out the method according to the invention when the computer program is executed by a computer, whereby the computer program according to the invention provides the same advantages as those detailed above in connection with the method according to the invention.

[0018] The subject of the invention is also an apparatus for data processing, which is adapted to carry out the method according to the invention. As an apparatus, for example, a computer for executing the computer program according to the invention may be provided. The computer may have at least one processor for executing the computer program. A non-volatile data storage may also be provided, in which the computer program is stored and from which it can be read by the processor for execution.

[0019] The subject of the invention may also be a computer-readable storage medium containing a computer program according to the invention. The storage medium may for example be configured as a data storage device such as a hard disk and / or a non-volatile storage device and / or a memory card. The storage medium may for example be integrated into the computer.

[0020] Additionally, the methods of the present invention may be practiced as computer-implemented methods.

[0021] Further advantages, features and details of the invention will become apparent from the following specification, in which an embodiment of the invention is described in detail with reference to the drawings, in which the features recited in the claims and in the specification can each individually or in any combination be essential to the invention. [Brief description of the drawings]

[0022] [Figure 1]1 shows a schematic visualization of a method, an apparatus, a storage medium and a computer program according to an embodiment of the invention; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] During the production of semiconductor wafers, the wafers are inspected after the various manufacturing steps. Before the wafer is disassembled into individual chips and the chips are packaged into the final product, the "finished" wafer is inspected in the so-called wafer level test or EWS (= electronic wafer sorting). At this step, the positions of the individual chips on the wafer are still known.

[0024] After dicing and packaging, the wafers are inspected again in a so-called Final Test. Since the wafer positions are lost after the dicing process, the chips can no longer trace their original coordinates, which makes the training of supervised machine learning models impossible. Although the individual chip positions of the individual chips are lost, the information of which wafers as a whole are part of this test lot is still present.

[0025] In the following, a method is proposed to enable prediction of the failure probability at final inspection of individual chips based on wafer level measurements.

[0026] For this purpose, a neural network architecture is used that takes as input a set of wafer-level measurements of a wafer and predicts the failure probability for each chip on the wafer (e.g., by using a sigmoid activation function in the last layer). The average over these chip predictions can be calculated for each appropriate set of wafers and the final inspection lot, thereby giving the yield of chips on the wafer.

[0027] For this purpose, a neural network is trained so that it is able to predict the yield of the chips after the final test. The training is carried out according to FIG.

[0028] 1 shows a method 100 for training a machine learning system, in particular a neural network, to predict the probability of failure of chips on a wafer according to an embodiment of the present invention. Also shown is a computer program 20, a storage medium 40 and a data processing device 10 according to an alternative embodiment of the present invention.

[0029] The method 100 begins by providing 101 a training data set that includes wafer-level test measurements at the chip level and the assigned final test yields for each of a number of wafers.

[0030] Following this, the following steps are executed multiple times until a predetermined abort criterion is met.

[0031] Step 102 involves extracting a number of wafer level test measurements and the respective final test yields assigned thereto.

[0032] Predicting 103 the final test yield dependent on the wafer-level test measurements by a machine learning system, where the machine learning system predicts chip failure probabilities dependent on the wafer-level test measurements, and these predicted failure probabilities are aggregated into a predicted final test yield.

[0033] The extracted wafer-level measurements are processed as input quantities by a machine learning system, in particular propagated by a neural network, to obtain failure probabilities for each chip.

[0034] All failure probabilities are then aggregated (eg, by using an average) into a single lot yield.

[0035] The machine learning system is trained to minimize the mathematical difference between the predicted final test yield and the assigned final test yield, step 104. This training can be done using known training techniques based on the error between the predicted final test lot yield and the true final test lot yield.

[0036] Once trained, the neural network can be used to predict the failure probability at final test for each chip.

Claims

1. 1. A method (100) for training a machine learning system to predict the probability of failure of chips on a wafer, comprising: providing (101) a training data set including wafer-level test measurements of a number of wafers and assigned final test yields; The following steps: Extracting (102) a plurality of wafer level test measurements and an assigned respective final test yield; predicting the final test yield dependent on the wafer-level test measurements by the machine learning system, the machine learning system determining the failure probabilities of chips on the wafer dependent on the wafer-level test measurements, and aggregating the determined failure probabilities into the predicted final test yield (103); training (104) the machine learning system such that a mathematical difference between the predicted final test yield and the assigned final test yield is minimized; The method (100) repeats the above a number of times.

2. 10. The method (100) of claim 1, wherein the machine learning system is configured to accept the wafer-level measurements as input quantities and output, as an output quantity, a probability of failure for each chip on the wafer.

3. The method (100) of claim 1 or 2, wherein the machine learning system is a neural network and an activation function of an output layer of the neural network is a sigmoid activation function.

4. The method (100) of any one of claims 1 to 3, wherein the aggregation of the predicted failure probabilities to the predicted final test yield is based on an average calculation of the predicted failure probabilities.

5. 1. A method for predicting a failure probability of chips on a wafer, comprising:

5. A method of using a machine learning system trained according to any one of claims 1 to 4 to predict the failure probability at final test for each chip on said wafer depending on wafer level test measurements of said wafer currently being processed.

6. 6. The method of claim 5, further comprising removing chips having a predicted failure probability greater than a first predetermined threshold and / or incorporating chips having a predicted failure probability less than a second predetermined threshold into a final product together with other chips having a predicted failure probability less than said second predetermined threshold.

7. A computer program (20), comprising: A computer program (20) comprising instructions for causing a computer (10) to carry out a method (100) according to any one of claims 1 to 6, when the computer program (20) is executed by the computer (10).

8. An apparatus (10) for data processing, comprising: An apparatus (10) configured to perform the method (100) according to any one of the preceding claims.

9. A computer readable storage medium (40), comprising: A computer-readable storage medium (40) comprising instructions that, when executed by a computer (10), cause the computer (10) to perform a method (100) according to any one of claims 1 to 6.

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