Memory device

Abstract

To provide a highly reliable memory device.SOLUTION: In a method for manufacturing a memory device that includes a first insulator, a first conductor including a first opening over the first insulator, a second insulator including a second opening over the first conductor, a second conductor including a third opening over the second insulator, a third insulator over the second conductor, and a semiconductor provided in the first opening to the third opening, the first insulator is formed, the first conductor is formed over the first insulator, the second insulator is formed over the first conductor, a fourth insulator is formed over the second insulator, the third insulator is formed over the fourth insulator, the third opening is formed in the fourth insulator, the second opening is formed in the second insulator, the first opening is formed in the first conductor, the semiconductor is formed in the first opening to the third opening, the fourth insulator is removed, and the second conductor is formed between the second insulator and the third insulator.SELECTED DRAWING: Figure 16

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device and a manufacturing method thereof.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of the invention disclosed in the present specification relates to an object, a method, or a manufacturing method. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter.

[0003] In this specification and the like, a semiconductor device generally refers to anything that can function by utilizing semiconductor characteristics. Thus, semiconductor elements such as transistors and diodes, and circuits including semiconductor elements are semiconductor devices. In addition, display devices, light-emitting devices, lighting devices, electro-optical devices, storage devices, imaging devices, communication devices, information processing devices, electronic devices, and the like may include semiconductor elements and semiconductor circuits. In addition, display devices, light-emitting devices, lighting devices, electro-optical devices, storage devices, imaging devices, communication devices, and electronic devices may also be called semiconductor devices. [Background technology]

[0004] In recent years, with an increase in the amount of data handled, there is a demand for semiconductor devices with larger storage capacity. In order to increase the storage capacity per unit area, it is effective to form memory cells in a stacked manner (see Patent Documents 1 and 2). By providing memory cells in a stacked manner, the storage capacity per unit area can be increased according to the number of stacked memory cells. Patent Documents 3 and 4 disclose memory devices using an oxide semiconductor. Patent Document 5 discloses a semiconductor memory using an oxide semiconductor as a charge storage layer.

[0005] Furthermore, Non-Patent Document 1 discloses CAAC-IGZO as a crystalline oxide semiconductor, and also discloses the growth mechanism of CAAC-IGZO. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] US Patent Publication 2011 / 0065270A1 [Patent Document 2] U.S. Patent Publication No. 9634097B2 [Patent Document 3] JP 2018-207038 A [Patent Document 4] JP 2019-8862 A [Patent Document 5] JP 2018-157205 A [Non-patent literature]

[0007] [Non-Patent Document 1] Noboru Kimizuka and Shunpei Yamazaki, “PHYSICS AND TECHNOLOGY OF CRYSTALLINE OXIDE SEMICONDUCTOR CAAC-IGZO” FUNDAMENTALS (USA), Wiley-SID Series in Display Technology, 2017, p.94-97 Summary of the Invention [Problem to be solved by the invention]

[0008] In Patent Documents 1 and 2, a plurality of storage elements (also called memory cells) are stacked and connected in series to form a three-dimensional memory cell array (also called a memory string).

[0009] In Patent Document 1, a semiconductor provided in a columnar shape is in contact with an insulator having a charge storage layer. In Patent Document 2, a semiconductor provided in a columnar shape is in contact with an insulator that functions as a tunnel dielectric. In both Patent Document 1 and Patent Document 2, writing information to a memory cell is performed by extracting and injecting charges through the insulator. In this case, a trap center may be formed at the interface where the semiconductor and the insulator contact. The trap center may capture electrons and cause the threshold voltage of the transistor to fluctuate. In addition, the extraction and injection of charges may deteriorate one or both of the inside of the insulator and the interface where the semiconductor and the insulator contact, and the charges held in the charge storage layer may leak and disappear. This may have a negative effect on the reliability of the memory device.

[0010] An object of one embodiment of the present invention is to provide a highly reliable memory device.Another object of one embodiment of the present invention is to provide a memory device having a large storage capacity.Another object of one embodiment of the present invention is to provide a memory device having a small occupation area.Another object of one embodiment of the present invention is to provide a memory device having low manufacturing costs.Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device.Another object of one embodiment of the present invention is to provide a semiconductor device having low manufacturing costs.Another object of one embodiment of the present invention is to provide a novel semiconductor device.

[0011] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not need to solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract problems other than these from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0012] One embodiment of the present invention is a method for manufacturing a memory device having a first insulator, a first conductor having a first opening on the first insulator, a second insulator having a second opening on the first conductor, a second conductor having a third opening on the second insulator, a third insulator on the second conductor, and a semiconductor provided in the first opening to a third opening, the method for manufacturing the memory device includes forming the first insulator, forming the first conductor on the first insulator, forming a second insulator on the first conductor, forming a fourth insulator on the second insulator, forming a third insulator on the fourth insulator, forming a third opening in the fourth insulator, forming a second opening in the second insulator, forming a first opening in the first conductor, forming a semiconductor in the first opening to the third opening, removing the fourth insulator, and forming the second conductor between the second insulator and the third insulator.

[0013] In the above, it is preferable that the second conductor has the same material as the first conductor.

[0014] In the above, it is preferable that the second conductor has a material different from that of the first conductor.

[0015] In the above, the diameter of the first opening is preferably larger than the diameter of the second opening and the diameter of the third opening.

[0016] In the above, it is preferable that the diameter of the first opening is made larger than the diameter of the second opening and the diameter of the third opening before the formation of the semiconductor.

[0017] In the above, the semiconductor preferably includes an oxide semiconductor.

[0018] In the above, the semiconductor preferably has crystallinity.

[0019] In the above, the semiconductor preferably has a region in the third opening whose c-axis is oriented in the normal direction to the side surface of the second conductor. Effect of the Invention

[0020] In the fabrication of a three-dimensional memory cell array in which multiple memory elements are stacked and connected in series, the total number of steps can be less than the product of the number of stacked memory elements and the number of steps to fabricate one memory element, which is preferable. In other words, the fabrication steps of the memory cell array are not proportional to the number of stacked memory elements. For example, when comparing the number of fabrication steps of memory cell array A having four layers of memory elements with the number of fabrication steps of memory cell array B having 32 layers of memory elements, the number of fabrication steps of memory cell array B can be significantly less than eight times the number of fabrication steps of memory cell array A, even though the number of stacked memory elements is eight times.

[0021] According to one embodiment of the present invention, a highly reliable memory device can be provided. According to one embodiment of the present invention, a memory device with a large memory capacity can be provided. According to one embodiment of the present invention, a memory device with a small occupation area can be provided. According to one embodiment of the present invention, a memory device with low manufacturing costs can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device with low manufacturing costs can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided.

[0022] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not need to have all of these effects. Note that effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract effects other than these from the description in the specification, drawings, claims, etc. [Brief description of the drawings]

[0023] [Figure 1] FIG. 1 is a perspective view of a storage device. [Diagram 2] FIG. 2 is a cross-sectional view of the storage device. [Diagram 3] FIG. 3 is a cross-sectional view of a memory string. [Figure 4]4A and 4B are cross-sectional views of a memory string. [Diagram 5] FIG. 5 is a cross-sectional view of a memory element. [Figure 6] Fig. 6A is a diagram for explaining the classification of crystal structures, Fig. 6B is a diagram for explaining the XRD spectrum of the CAAC-IGZO film, and Fig. 6C is a diagram for explaining the micro-electron beam diffraction pattern of the CAAC-IGZO film. [Figure 7] 7A to 7C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 8] 8A to 8C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 9] 9A to 9C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 10] 10A to 10C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 11] 11A to 11C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 12] 12A to 12C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 13] 13A to 13C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 14] 14A to 14C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 15] 15A to 15C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 16] 16A to 16C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 17] 17A and 17B are a top view and a cross-sectional view illustrating a film formation apparatus according to an embodiment of the present invention. [Figure 18] 18A to 18C are cross-sectional views illustrating a film formation apparatus according to one embodiment of the present invention. [Figure 19]FIG. 19 is a diagram illustrating an example of a circuit configuration of a memory string. [Figure 20] FIG. 20 is a diagram illustrating an example of a circuit configuration of a memory string. [Figure 21] FIG. 21 is a diagram illustrating an example of a circuit configuration of a memory string. [Figure 22] FIG. 22 is a diagram illustrating an example of a circuit configuration of a memory string. [Diagram 23] FIG. 23 is a diagram illustrating an example of a circuit configuration of a memory string. [Figure 24] FIG. 24 is a timing chart illustrating an example of a write operation of a memory string. [Diagram 25] 25A and 25B are circuit diagrams illustrating an example of a write operation of a memory string. [Figure 26] 26A and 26B are circuit diagrams illustrating an example of a write operation of a memory string. [Figure 27] 27A and 27B are circuit diagrams illustrating an example of a write operation of a memory string. [Figure 28] 28A and 28B are circuit diagrams illustrating an example of a write operation of a memory string. [Figure 29] 29A and 29B are circuit diagrams illustrating an example of a write operation of a memory string. [Diagram 30] 30A and 30B are timing charts illustrating an example of a read operation of a memory string. [Diagram 31] 31A and 31B are circuit diagrams illustrating an example of a read operation of a memory string. [Diagram 32] 32A and 32B are circuit diagrams illustrating an example of a read operation of a memory string. [Diagram 33] 33A and 33B are diagrams illustrating the Id-Vg characteristics of a transistor. [Diagram 34] FIG. 34 is a diagram illustrating an example of a circuit configuration of a memory string. [Diagram 35]FIG. 35 is a diagram illustrating an example of a circuit configuration of a memory string. [Diagram 36] FIG. 36 is a diagram illustrating an example of a circuit configuration of a memory string. [Figure 37] FIG. 37 is a block diagram illustrating a configuration example of a semiconductor device. [Figure 38] 38A to 38C are perspective views for explaining configuration examples of a semiconductor device. [Figure 39] FIG. 39 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 40] FIG. 40A is a perspective view for explaining an example of the configuration of a computer, and FIG. 40B is a perspective view for explaining a monolithic IC. [Diagram 41] 41A and 41B are diagrams illustrating the memory hierarchy of a computer and a monolithic IC, respectively. [Diagram 42] Fig. 42A is a schematic diagram of a semiconductor device, and Fig. 42B is a perspective view of the semiconductor device. [Diagram 43] 43A to 43E are diagrams for explaining an example of a storage device. [Diagram 44] 44A to 44G are diagrams illustrating an example of an electronic device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the form and details of the present invention can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and the repeated description will be omitted.

[0025] In addition, the position, size, range, etc. of each component shown in the drawings, etc. may not represent the actual position, size, range, etc. in order to facilitate understanding of the invention. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings, etc. For example, in the actual manufacturing process, a resist mask, etc. may be unintentionally eroded by a process such as etching, but this may not be reflected in the drawings in order to facilitate understanding.

[0026] In addition, in the drawings, etc., some components may be omitted in order to make the explanation easier to understand.

[0027] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" or "wirings" are formed integrally.

[0028] In addition, in this specification and the like, a "terminal" in an electric circuit refers to a portion where a current is input or output, a voltage is input or output, or a signal is received or transmitted. Therefore, a part of a wiring or an electrode may function as a terminal.

[0029] In this specification, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0030] In addition, the functions of the source and drain are interchangeable depending on the operating conditions, such as when transistors of different polarities are used or when the direction of current changes during circuit operation, so it is difficult to determine which is the source and which is the drain. For this reason, in this specification, the terms source and drain can be used interchangeably.

[0031] In addition, in this specification, "electrically connected" includes a direct connection and a connection via "something having some electrical action." Here, the "something having some electrical action" is not particularly limited as long as it allows the transmission and reception of electrical signals between the connected objects. Therefore, even when it is expressed as "electrically connected," in the actual circuit, there may be no physical connection and only wiring extending therethrough.

[0032] In this specification and elsewhere, "parallel" refers to, for example, a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. This therefore includes cases in which the angle is -5° or more and 5° or less. Furthermore, "perpendicular" and "orthogonal" refer to, for example, a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. This therefore includes cases in which the angle is 85° or more and 95° or less.

[0033] In this specification and elsewhere, when referring to counting values ​​and measurement values, or to objects, methods, and events that can be converted into counting values ​​or measurement values, terms such as "same," "equal," and "uniform" are intended to include an error of plus or minus 20%, unless otherwise expressly stated.

[0034] Furthermore, voltage often refers to the potential difference between a certain potential and a reference potential (for example, a ground potential or a source potential). Therefore, voltage and potential can often be interchanged. In this specification and the like, unless otherwise specified, voltage and potential can be interchanged.

[0035] Even when written as "semiconductor", for example, if the conductivity is sufficiently low, it has the characteristics of an "insulator". Therefore, it is also possible to use "semiconductor" instead of "insulator". In this case, the boundary between "semiconductor" and "insulator" is ambiguous, and it is difficult to strictly distinguish between the two. Therefore, "semiconductor" and "insulator" described in this specification may be read as interchangeable.

[0036] Furthermore, even when written as "semiconductor", if the conductivity is sufficiently high, it has the characteristics of a "conductor". Therefore, it is also possible to use "semiconductor" in place of "conductor". In this case, the boundary between "semiconductor" and "conductor" is ambiguous, and it is difficult to strictly distinguish between the two. Therefore, "semiconductor" and "conductor" described in this specification may be interchangeable.

[0037] In addition, ordinal numbers such as "first" and "second" in this specification are used to avoid confusion of components, and do not indicate any order or ranking, such as the order of processes or stacking. Even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion of components. Even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Even if a term has an ordinal number in this specification, the ordinal number may be omitted in the claims.

[0038] In this specification, the "on state" of a transistor refers to a state in which the source and drain of the transistor can be regarded as being electrically short-circuited (also referred to as a "conductive state"). The "off state" of a transistor refers to a state in which the source and drain of the transistor can be regarded as being electrically disconnected (also referred to as a "non-conductive state").

[0039] In this specification, the term "on-state current" may refer to a current that flows between a source and a drain when a transistor is on, and the term "off-state current" may refer to a current that flows between a source and a drain when a transistor is off.

[0040] In this specification and the like, high power supply potential VDD (hereinafter also simply referred to as "VDD", "H potential", or "H") refers to a power supply potential that is higher than the low power supply potential VSS (hereinafter also simply referred to as "VSS", "L potential", or "L"). Also, VSS refers to a power supply potential that is lower than VDD. Also, ground potential (hereinafter also simply referred to as "GND" or "GND potential") can be used as VDD or VSS. For example, when VDD is the ground potential, VSS is a potential lower than the ground potential, and when VSS is the ground potential, VDD is a potential higher than the ground potential.

[0041] In addition, unless otherwise specified, the transistors described in this specification and the like are enhancement-type (normally-off) n-channel field effect transistors. Therefore, the threshold voltage (also referred to as "Vth") is assumed to be higher than 0 V. In addition, unless otherwise specified, "supplying an H potential to the gate of a transistor" may be synonymous with "turning the transistor on." In addition, unless otherwise specified, "supplying an L potential to the gate of a transistor" may be synonymous with "turning the transistor off."

[0042] In this specification and the like, a gate refers to a gate electrode and a part or the whole of a gate wiring. A gate wiring refers to a wiring for electrically connecting a gate electrode of at least one transistor to another electrode or another wiring.

[0043] In this specification and the like, the source refers to a source region, a source electrode, and a part or all of a source wiring. The source region refers to a region of a semiconductor layer having a resistivity equal to or lower than a certain value. The source electrode refers to a conductive layer connected to the source region. The source wiring refers to a wiring for electrically connecting the source electrode of at least one transistor to another electrode or another wiring.

[0044] In this specification and the like, the drain refers to a part or all of the drain region, the drain electrode, and the drain wiring. The drain region refers to a region of the semiconductor layer whose resistivity is equal to or lower than a certain value. The drain electrode refers to a conductive layer that is connected to the drain region. The drain wiring refers to a wiring for electrically connecting the drain electrode of at least one transistor to another electrode or another wiring.

[0045] In addition, in drawings, etc., to make the potential of wiring and electrodes easier to understand, "H" indicating H potential or "L" indicating L potential may be written next to the wiring and electrode. Wiring and electrodes where a potential change has occurred may be written with "H" or "L" enclosed in a box. When a transistor is in the off state, an "x" symbol may be written over the transistor.

[0046] Generally, a "capacitance" has a configuration in which two electrodes face each other via an insulator (dielectric). In this specification, etc., a "capacitance element" includes the above-mentioned "capacitance." That is, in this specification, etc., a "capacitance element" includes a configuration in which two electrodes face each other via an insulator, a configuration in which two wires face each other via an insulator, or a configuration in which two wires are arranged via an insulator.

[0047] In addition, in this specification and the like, when the same reference numeral is used for multiple elements, and when it is particularly necessary to distinguish between them, the reference numeral may be accompanied by an identifying reference numeral such as "_1", "_2", "[n]", "[m,n]", etc. For example, the second conductor WWL may be described as conductor WWL[2].

[0048] (Embodiment 1) FIG. 1 shows a perspective view of a storage device 100 according to an embodiment of the present invention. The storage device 100 is a storage device having a three-dimensional stacked structure. FIG. 2 is a cross-sectional view of the portion A1-A2 shown by the dashed line in FIG. 1, and the connection portion between the conductor SEL and the wiring. Note that in FIG. 1 and the like, arrows indicating the X direction, the Y direction, and the Z direction may be added. The X direction, the Y direction, and the Z direction are directions that are perpendicular to each other. In the present specification and the like, one of the X direction, the Y direction, and the Z direction may be called the "first direction" or the "first direction". The other one may be called the "second direction" or the "second direction". The remaining one may be called the "third direction" or the "third direction". Note that in the present embodiment and the like, the direction in which the conductor 130 described later extends is the Z direction.

[0049] Fig. 2 shows a cross section of the XZ plane. As mentioned above, some of the components may be omitted in Fig. 1 and Fig. 2 for ease of understanding.

[0050] <Storage device configuration example> A memory device 100 according to one embodiment of the present invention includes a memory cell array 110. The memory cell array 110 includes a plurality of memory strings 120. The memory strings 120 extend in the Z direction and are arranged in a matrix on the XY plane.

[0051] 3 shows an example of a cross-sectional structure of a memory string 120 according to one embodiment of the present invention. The memory string 120 has a configuration in which a plurality of storage elements MC (also referred to as "memory cells") are connected in series. In this embodiment, five storage elements MC are connected in series, but the number of storage elements MC included in the memory string 120 is not limited to five. When the number of storage elements MC included in the memory string 120 is n, n may be an integer of 2 or more.

[0052] The memory string 120 also has a plurality of conductors WWL, a plurality of conductors RWL, a conductor SG, and a conductor SEL. The plurality of conductors WWL and the plurality of conductors RWL are alternately stacked with an insulator 123 interposed therebetween. The conductor SG is provided in a lower layer than the plurality of conductors WWL and the plurality of conductors RWL. The conductor SEL is provided in an upper layer than the plurality of conductors WWL and the plurality of conductors RWL.

[0053] 3, the five memory elements MC are denoted as memory elements MC[1] to MC[5]. Note that when describing matters common to the memory elements MC[1] to MC[5], they are simply referred to as "memory element MC." The same applies to other components such as the conductor WWL, the conductor RWL, and the insulator 123.

[0054] The memory string 120 includes a transistor STr1 connected to the storage element MC[1] and a transistor STr2 connected to the storage element MC[5].

[0055] The conductor WWL, the conductor RWL, the conductor SG, and the conductor SEL extend beyond the memory cell array 110. In addition, the conductor WWL, the conductor RWL, the conductor SG, and the conductor SEL are stacked in a stepped manner outside the memory cell array 110 (see FIGS. 1 and 2).

[0056] Fig. 4A shows a cross section seen from the Z direction of the portion B1-B2 shown by the dashed dotted line in Fig. 3. Fig. 4B shows a cross section seen from the Z direction of the portion C1-C2 shown by the dashed dotted line in Fig. 3. Fig. 5 shows an enlarged view of the region 105 shown by the two-dot dashed line in Fig. 3. Fig. 5 corresponds to a cross section of the memory element MC.

[0057] The memory string 120 has a conductor 122 on a base 121. The base 121 may be, for example, an insulator. Also, on the conductor 122, there are insulator 123[1], conductor SG, insulator 123[2], conductor RWL[1], insulator 123[3], conductor WWL[1], insulator 123[4], conductor RWL[2], insulator 123[5], conductor WWL[2], insulator 123[6], conductor RWL[3], insulator 123[7], conductor WWL[3], insulator 123[8], conductor RWL[4], insulator 123[9], conductor WWL[4], insulator 123

[10] , conductor RWL[5], insulator 123

[11] , conductor WWL[5], insulator 123

[12] , and conductor SEL (see FIG. 3).

[0058] The memory string 120 also has an opening 141 formed by removing a portion of each of the insulator 123[1], the conductor SG, the insulator 123[2], the conductor RWL[1], the insulator 123[3], the conductor WWL[1], the insulator 123[4], the conductor RWL[2], the insulator 123[5], the conductor WWL[2], the insulator 123[6], the conductor RWL[3], the insulator 123[7], the conductor WWL[3], the insulator 123[8], the conductor RWL[4], the insulator 123[9], the conductor WWL[4], the insulator 123

[10] , the conductor RWL[5], the insulator 123

[11] , the conductor WWL[5], the insulator 123

[12] , and the conductor SEL.

[0059] The opening 141 extends in the Z direction and reaches the conductor 122. In the opening 141, the diameter of a region 142 overlapping with the conductor RWL is larger than the diameter of a region 143 overlapping with the conductor WWL. Therefore, the side surface of the opening 141 has an uneven shape.

[0060] Further, an insulator 124 and a semiconductor 125 are provided along the side surface of the opening 141. Further, in the region of the opening 141 overlapping with the conductor RWL, a conductor 128 is provided between the insulator 124 and the semiconductor 125. The semiconductor 125 has a region overlapping with the side surface of the opening 141 with the insulator 124 interposed therebetween.

[0061] The memory string 120 also has a conductor 130 extending in the Z direction. The conductor 130 is provided at or near the center of the opening 141. An insulator 129, a semiconductor 127, and an insulator 126 are provided in a region of the conductor 130 that overlaps with the side surface of the opening 141. The semiconductor 127 has a region that overlaps with the side surface of the conductor 130 via the insulator 129. The insulator 126 has a region that overlaps with the side surface of the conductor 130 via the insulator 129 and the semiconductor 127. At the bottom of the opening 141, the semiconductor 125 and the semiconductor 127 have a region that is electrically connected to the conductor 122. At the bottom of the opening 141, the conductor 130 has a region that overlaps with the conductor 122 via the insulator 129 and the semiconductor 127.

[0062] Between the conductor WWL and the conductor 130, an insulator 181, an insulator 124, a semiconductor 125, an insulator 126, a semiconductor 127, and an insulator 129 are provided in this order from the conductor WWL side (see FIG. 4A). Between the conductor RWL and the conductor 130, an insulator 124, a conductor 128, a semiconductor 125, an insulator 126, a semiconductor 127, and an insulator 129 are provided in this order from the conductor RWL side (see FIG. 4B).

[0063] The memory element MC has a transistor WTr and a transistor RTr (see FIG. 5). The region where the conductor WWL and the conductor 130 overlap functions as the transistor WTr. The conductor WWL functions as the gate electrode of the transistor WTr, and the conductor 130 functions as the backgate electrode of the transistor WTr. A part of the semiconductor 125 functions as a semiconductor layer in which the channel of the transistor WTr is formed. The semiconductor layer in which the channel of the transistor WTr is formed overlaps with the gate electrode (conductor WWL) via a part of the insulator 124. Note that in the present embodiment and the like, an example is shown in which a part of the conductor WWL functions as the gate electrode, but the gate electrode and the conductor WWL may be provided independently and electrically connected to each other.

[0064] The region where the conductor 128, the conductor RWL, and the conductor 130 overlap functions as the transistor RTr. The conductor RWL functions as the gate electrode of the transistor RTr. The conductor 130 functions as the backgate electrode of the transistor RTr. A part of the semiconductor 127 functions as a semiconductor layer in which the channel of the transistor RTr is formed. The semiconductor layer in which the channel of the transistor RTr is formed overlaps with the gate electrode (conductor RWL) via parts of the insulator 126, the semiconductor 125, the conductor 128, and the insulator 124. The semiconductor layer in which the channel of the transistor RTr is formed overlaps with the backgate electrode (conductor 130) via part of the insulator 129.

[0065] The transistor STr1 includes a conductor SG, a semiconductor 125, and a semiconductor 127. The transistor STr2 includes a conductor SEL, a semiconductor 125, and a semiconductor 127.

[0066] Here, we will explain the backgate. The gate and the backgate are arranged so as to overlap with each other via the channel formation region of the semiconductor layer. The backgate can function in the same way as the gate. In addition, the threshold voltage of the transistor can be changed by changing the potential of the backgate. Either the gate or the backgate may be called the "first gate" or "first gate," and the other may be called the "second gate" or "second gate."

[0067] The gate and back gate are formed of a conductive layer or a semiconductor layer with low resistivity, and therefore have the function of preventing an electric field generated outside the transistor from acting on the semiconductor layer in which the channel is formed (particularly, an electrostatic shielding function against static electricity). In other words, it is possible to prevent the electrical characteristics of the transistor from fluctuating due to the influence of an external electric field such as static electricity.

[0068] In addition, the threshold voltage of the transistor can be controlled by controlling the potential of the back gate, which may be the same potential as the gate, a ground potential (GND potential), or any other potential.

[0069] The semiconductor layers in which the channels of the transistors WTr and RTr are formed may be made of single crystal semiconductors, polycrystalline semiconductors, microcrystalline semiconductors, or amorphous semiconductors, either alone or in combination. Examples of the semiconductor material include silicon and germanium. Compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, oxide semiconductors, and nitride semiconductors may also be used. The same is true for the transistors STr1 and STr2.

[0070] Note that the semiconductor layers used in the transistor may be stacked. When the semiconductor layers are stacked, semiconductors having different crystal states or different semiconductor materials may be used for each of the semiconductor layers.

[0071] The semiconductor layer used in the transistors WTr, RTr, STr1, and STr2 is preferably an oxide semiconductor containing a metal oxide. A transistor using a metal oxide in the semiconductor layer can obtain a higher field-effect mobility than a transistor using amorphous silicon in the semiconductor layer. In addition, a transistor using polycrystalline silicon in the semiconductor layer may have a grain boundary in the semiconductor layer. At the grain boundary, carriers are likely to be captured, causing a decrease in the on-current of the transistor, a decrease in the field-effect mobility, and the like. On the other hand, as will be described in detail later, an oxide semiconductor can realize a crystal structure in which no clear grain boundary is confirmed or a crystal structure in which the grain boundary is extremely small. It is preferable to use such an oxide semiconductor in the semiconductor layer because a transistor having good electrical characteristics such as a high on-current and a field-effect mobility can be realized.

[0072] Furthermore, oxide semiconductors, particularly CAAC-IGZO, which is a crystalline oxide semiconductor, have a characteristic structure in which nanoclusters of a few nm (e.g., 1 to 3 nm) are linked together and their c-axes are oriented in the direction perpendicular to the surface on which they are formed. This makes it possible to form a crystal structure in which no clear crystal grain boundaries are visible even within an opening extending in the Z direction.

[0073] In particular, the transistor WTr is preferably a transistor (also referred to as an "OS transistor") that uses an oxide semiconductor, which is a type of metal oxide, in a semiconductor layer in which a channel is formed. An oxide semiconductor has a band gap of 2 eV or more, and therefore has an extremely low off-state current. When an OS transistor is used for the transistor WTr, charge written to a node ND, which will be described later, can be held for a long period of time. When an OS transistor is used as a transistor constituting the memory element MC, the memory element MC can be called an "OS memory." In addition, the memory string 120 including the memory element MC can also be called an "OS memory." In addition, the memory device 100 can also be called an "OS memory."

[0074] The OS memory can retain written information for more than one year, or even more than ten years, even if the power supply is cut off. Therefore, the OS memory can be considered as a non-volatile memory.

[0075] In addition, since the amount of charge written into the OS memory is unlikely to change over a long period of time, the OS memory can hold not only binary (1-bit) information but also multi-value (multi-bit) information.

[0076] In addition, because OS memory uses a method of writing charge to a node via a transistor, it does not require the high voltage required for conventional flash memory, and can achieve high-speed write operations. In addition, OS memory does not require the erase operation before rewriting data, which is performed in flash memory. In addition, since no charge is injected or extracted from the floating gate or charge trapping layer, OS memory can write and read data an unlimited number of times. OS memory is less susceptible to deterioration than conventional flash memory, and is highly reliable.

[0077] In addition, unlike magnetoresistive random access memory (MRAM) or resistive random access memory (ReRAM), OS memory does not undergo structural changes at the atomic level when rewriting memory. Therefore, OS memory has better rewrite endurance than magnetoresistive memory and resistive random access memory.

[0078] Moreover, the off-current of an OS transistor hardly increases even in a high-temperature environment. Specifically, the off-current hardly increases even in an environmental temperature range of room temperature or higher and 200° C. or lower. Moreover, the on-current is unlikely to decrease even in a high-temperature environment. A storage device including an OS memory is stable in operation even in a high-temperature environment, and is highly reliable. Moreover, the OS transistor has a high withstand voltage between the source and drain. By using an OS transistor as a transistor constituting a semiconductor device, a semiconductor device that is stable in operation even in a high-temperature environment and has good reliability can be realized.

[0079] The semiconductor 127 is preferably an n-type semiconductor. Also, the region of the semiconductor 125 that overlaps with the conductor WWL is preferably an i-type or substantially i-type semiconductor. In this case, the transistor WTr is an enhancement type (normally off type) transistor, and the transistor RTr is a depletion type (normally on type) transistor.

[0080] Note that the semiconductor 125 and the semiconductor 127 may be made of the same material or different materials. For example, the semiconductor 125 and the semiconductor 127 may each be an oxide semiconductor. The semiconductor 125 and the semiconductor 127 may each be a semiconductor containing silicon. The semiconductor 125 may be an oxide semiconductor, and the semiconductor 127 may be a semiconductor containing silicon. The semiconductor 125 may be a semiconductor containing silicon, and the semiconductor 127 may be an oxide semiconductor.

[0081] 4A corresponds to the XY plane at or near the center of the transistor WTr, and FIG. 4B corresponds to the XY plane at or near the center of the transistor RTr. In FIG. 4A and FIG. 4B, when the cross-sectional shape of the conductor 130 is circular, the insulator 129 is provided concentrically outside the conductor 130, the semiconductor 127 is provided concentrically outside the insulator 129, the insulator 126 is provided concentrically outside the semiconductor 127, the semiconductor 125 is provided concentrically outside the insulator 126, and the insulator 124 is provided concentrically outside the semiconductor 125. The conductor 128 is provided concentrically between the semiconductor 125 and the insulator 124.

[0082] The cross-sectional shape of the conductor 130 is not limited to a circle. The cross-sectional shape of the conductor 130 may be a rectangle. The cross-sectional shape of the conductor 130 may be a triangle.

[0083] The memory string 120 can also be called a memory device, and the memory element MC can also be called a memory device.

[0084] [Materials Constituting Semiconductor Devices] Next, materials that can be used for the storage device 100 will be described.

[0085] [substrate] The memory device 100 can be provided on a substrate. For example, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used as the substrate. For example, the insulating substrate may be a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria stabilized zirconia substrate), or a resin substrate. For example, the semiconductor substrate may be a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. For example, the semiconductor substrate may be a semiconductor substrate having an insulating region inside the semiconductor substrate, such as an SOI (Silicon On Insulator) substrate. For example, the conductive substrate may be a graphite substrate, a metal substrate, an alloy substrate, or a conductive resin substrate. For example, a substrate having a metal nitride, or a substrate having a metal oxide may be used. For example, a substrate having a conductor or semiconductor provided on an insulating substrate, a substrate having a conductor or insulator provided on a semiconductor substrate, or a substrate having a semiconductor or insulator provided on a conductive substrate may be used. Alternatively, a substrate provided with elements may be used. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0086] [Insulator] Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, each of which has insulating properties.

[0087] In this specification, etc., "oxynitride" refers to a material that contains more oxygen than nitrogen as a main component. For example, "silicon oxynitride" refers to a material that contains more oxygen than nitrogen and contains silicon, nitrogen, and oxygen. In this specification, etc., "nitride oxide" refers to a material that contains more nitrogen than oxygen as a main component. For example, "aluminum nitride oxide" refers to a material that contains more nitrogen than oxygen and contains aluminum, nitrogen, and oxygen.

[0088] For example, as transistors become smaller and more highly integrated, problems such as leakage current can occur due to thinner gate insulators. By using a high-k material for the insulator that functions as the gate insulator, it is possible to reduce the voltage required for transistor operation while maintaining the physical film thickness. On the other hand, by using a material with a low dielectric constant for the insulator that functions as the interlayer film, it is possible to reduce the parasitic capacitance that occurs between wiring. Therefore, it is best to select materials according to the function of the insulator.

[0089] Further, examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0090] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with voids, or resin.

[0091] In addition, the electrical characteristics of the OS transistor can be stabilized by surrounding it with an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. As the insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or a stacked layer. Specifically, as the insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride can be used.

[0092] When an oxide semiconductor is used for the semiconductor 125 and / or the semiconductor 127, the insulator functioning as a gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the semiconductor 125 and / or the semiconductor 127, oxygen vacancies in the semiconductor 125 and / or the semiconductor 127 can be compensated for.

[0093] In addition, it is preferable to provide an insulator 181 in order to suppress oxidation of the conductor 182 functioning as the conductor WWL and the conductor 183 functioning as the conductor SEL. It is preferable to use the above-mentioned material having a barrier property against oxygen and hydrogen as the insulator 181. It is preferable that the insulator 181 is provided so as to be in contact with the lower surface, upper surface, and side surface of the conductor 182 and the conductor 183.

[0094] [conductor] As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal elements as a component, or an alloy combining the above-mentioned metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. In addition, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel are conductive materials that are difficult to oxidize, or materials that maintain conductivity even when oxygen is absorbed, so they are preferable. Furthermore, a semiconductor having high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

[0095] A plurality of conductive layers formed of the above-mentioned materials may be stacked. For example, a stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0096] In the case where an oxide semiconductor, which is a type of metal oxide, is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing the above-mentioned metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0097] In particular, as a conductor functioning as a gate electrode, it is preferable to use a conductive material containing oxygen and a metal element contained in an oxide semiconductor in which a channel is formed. The conductive material containing the above-mentioned metal element and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon is added may be used. Indium gallium zinc oxide containing nitrogen may be used. By using such a material, hydrogen contained in an oxide semiconductor in which a channel is formed may be captured. Alternatively, hydrogen mixed in from an external insulator or the like may be captured.

[0098] [Oxide semiconductor] A metal oxide (oxide semiconductor) functioning as a semiconductor is preferably used as the semiconductor 125 and the semiconductor 127. An oxide semiconductor that can be used for the semiconductor 125 and the semiconductor 127 will be described below.

[0099] The oxide semiconductor preferably contains at least indium or zinc. In particular, it is preferable that the oxide semiconductor contains indium and zinc. In addition to these, it is preferable that the oxide semiconductor contains aluminum, gallium, yttrium, tin, etc. Furthermore, the oxide semiconductor may contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc.

[0100] Here, the case where the oxide semiconductor is an In-M-Zn oxide containing indium, an element M, and zinc is considered. The element M is one or more selected from aluminum, gallium, yttrium, and tin. Other elements applicable to the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt. However, there are cases where the element M may be a combination of a plurality of the above elements.

[0101] In this specification and the like, metal oxides containing nitrogen may also be collectively referred to as metal oxides. Furthermore, metal oxides containing nitrogen may also be referred to as metal oxynitrides.

[0102] [Classification of crystal structures] First, classification of crystal structures in oxide semiconductors will be described with reference to Fig. 6A. Fig. 6A is a diagram for explaining classification of crystal structures of oxide semiconductors, typically IGZO (metal oxide containing In, Ga, and Zn).

[0103] As shown in FIG. 6A, oxide semiconductors are broadly classified into "Amorphous", "Crystalline" and "Crystal". "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc) and cloud-aligned composite (CAC). "Crystalline" excludes single crystal, poly crystal and completely amorphous (excluding single crystal and poly crystal). "Crystal" includes single crystal and poly crystal.

[0104] The structure in the bold frame shown in Fig. 6A is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). In other words, this structure is completely different from the energetically unstable "Amorphous" and "Crystal".

[0105] The crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD) spectrum. Figure 6B shows an XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of the CAAC-IGZO film classified as "Crystalline". The GIXD method is also called the thin film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by the GIXD measurement shown in Figure 6B will be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 6B is approximately In:Ga:Zn=4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 6B is 500 nm.

[0106] As shown in Figure 6B, a clear peak indicating crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ=31° in the XRD spectrum of the CAAC-IGZO film. Note that, as shown in Figure 6B, the peak near 2θ=31° is asymmetric with respect to the angle at which the peak intensity is detected.

[0107] The crystal structure of the film or substrate can be evaluated by a diffraction pattern (also called a nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). The diffraction pattern of the CAAC-IGZO film is shown in Figure 6C. Figure 6C shows a diffraction pattern observed by NBED, which causes an electron beam to be incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 6C is approximately In:Ga:Zn=4:2:3 [atomic ratio]. In the nanobeam electron diffraction method, electron diffraction is performed with a probe diameter of 1 nm.

[0108] As shown in Figure 6C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0109] [Structure of oxide semiconductor] In addition, when focusing on the crystal structure, oxide semiconductors may be classified differently from that shown in FIG. 6A. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. In addition, non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, pseudo-amorphous-like oxide semiconductors (a-like OS), amorphous oxide semiconductors, and the like.

[0110] Next, the details of the above-mentioned CAAC-OS, nc-OS, and a-like OS will be explained.

[0111] [CAAC-OS] CAAC-OS is an oxide semiconductor having a plurality of crystalline regions, each of which has a c-axis aligned in a specific direction. The specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. The crystalline region is a region having periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, the crystalline region is also a region with a uniform lattice arrangement. CAAC-OS has a region in which a plurality of crystalline regions are connected in the ab-plane direction, and the region may have distortion. The distortion refers to a portion in which the direction of the lattice arrangement changes between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement in the region in which the plurality of crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor having a c-axis aligned and no clear orientation in the ab-plane direction.

[0112] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be about several tens of nm.

[0113] In the In-M-Zn oxide, the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter, an In layer) and a layer containing an element M, zinc (Zn), and oxygen (hereinafter, an (M, Zn) layer) are stacked. Note that indium and the element M are mutually substituted. Thus, the (M, Zn) layer may contain indium. Note that the In layer may contain the element M. Note that the In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0114] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD device, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0115] For example, a plurality of bright points (spots) are observed in the electron diffraction pattern of the CAAC-OS film, and the spots are observed at positions symmetrical to each other with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0116] When the crystal region is observed from the specific direction, the lattice arrangement in the crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. The above distortion may have a pentagonal or heptagonal lattice arrangement. In addition, no clear grain boundary can be confirmed in the CAAC-OS even in the vicinity of the distortion. That is, it is found that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is considered to be because the CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the ab-plane direction and the bond distance between atoms changes due to the substitution of metal atoms.

[0117] A crystal structure in which clear grain boundaries are observed is called a polycrystal. The grain boundaries are likely to become recombination centers and capture carriers, causing a decrease in the on-current of a transistor and a decrease in field effect mobility. Therefore, CAAC-OS in which clear grain boundaries are not observed is one of the crystalline oxides having a crystal structure suitable for a semiconductor layer of a transistor. In order to form a CAAC-OS, a structure containing Zn is preferable. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the occurrence of grain boundaries more than In oxide.

[0118] The CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to crystal grain boundaries. In addition, since the crystallinity of an oxide semiconductor can be decreased by the inclusion of impurities or the generation of defects, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of an oxide semiconductor having the CAAC-OS are stable. Therefore, an oxide semiconductor having the CAAC-OS is resistant to heat and has high reliability. In addition, the CAAC-OS is stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, the use of the CAAC-OS in an OS transistor can increase the degree of freedom in the manufacturing process.

[0119] [nc-OS] The nc-OS has periodic atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has minute crystals. Note that the size of the minute crystals is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore the minute crystals are also called nanocrystals. In addition, the nc-OS does not show regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is seen in the entire film. Therefore, depending on the analysis method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structure analysis is performed on an nc-OS film using an XRD device, no peak indicating crystallinity is detected in out-of-plane XRD measurement using θ / 2θ scan. In addition, when an nc-OS film is subjected to electron diffraction (also called selected area electron diffraction) using an electron beam with a probe diameter larger than that of nanocrystals (for example, 50 nm or more), a diffraction pattern like a halo pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter (e.g., 1 nm to 30 nm) that is close to the size of a nanocrystal or smaller than the nanocrystal, an electron diffraction pattern in which multiple spots are observed within a ring-shaped region centered on the direct spot may be obtained.

[0120] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor. The a-like OS has a void or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Moreover, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0121] [Oxide semiconductor composition] Next, the above-mentioned CAC-OS will be described in detail, with reference to its material composition.

[0122] [CAC-OS] CAC-OS is, for example, a material configuration in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof. In the following, a state in which one or more metal elements are unevenly distributed in a metal oxide and the regions having the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof, is also referred to as a mosaic or patch state.

[0123] Furthermore, CAC-OS is a composite metal oxide in which the material is separated into a first region and a second region, forming a mosaic structure, and the first region is distributed throughout the film (hereinafter, also referred to as a cloud structure). In other words, CAC-OS is a composite metal oxide in which the first region and the second region are mixed together.

[0124] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are represented as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. Also, the second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. Also, the second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0125] Specifically, the first region is a region mainly composed of indium oxide, indium zinc oxide, etc., and the second region is a region mainly composed of gallium oxide, gallium zinc oxide, etc. In other words, the first region can be rephrased as a region mainly composed of In, and the second region can be rephrased as a region mainly composed of Ga.

[0126] In addition, there are cases where a clear boundary between the first region and the second region cannot be observed.

[0127] For example, in the case of a CAC-OS of an In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) has confirmed that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0128] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act in a complementary manner, giving the CAC-OS a switching function (On / Off function). In other words, CAC-OS has a conductive function in part of the material and an insulating function in other parts of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, it is possible to maximize both functions. Therefore, by using CAC-OS in a transistor, it is possible to achieve a high on-current (I on ), high field effect mobility (μ), and good switching behavior can be achieved.

[0129] Oxide semiconductors have a variety of structures and have different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0130] [Transistor Having Oxide Semiconductor] Next, the case where the oxide semiconductor is used for a transistor will be described.

[0131] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0132] It is preferable to use an oxide semiconductor having a low carrier concentration for a channel formation region of a transistor. For example, the carrier concentration of the channel formation region of an oxide semiconductor is 1×10 18 cm -3 It is preferable that the value is less than 1×10 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm-3 It is more preferable that the carrier concentration of the oxide semiconductor film is less than 100%. Note that in the case of lowering the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be lowered to lower the density of defect states. In this specification and the like, an oxide semiconductor having a low impurity concentration and a low density of defect states is referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. In addition, a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor may be referred to as an i-type or substantially i-type.

[0133] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states might also be low.

[0134] In addition, charges trapped in the trap states of an oxide semiconductor take a long time to disappear and may behave as if they are fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0135] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in a nearby film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0136] 〔impurities〕 Here, the influence of each impurity in an oxide semiconductor will be described.

[0137] When an oxide semiconductor contains silicon or carbon, which is one of the group 14 elements, defect levels are formed in the oxide semiconductor. For this reason, the concentrations of silicon and carbon in the channel formation region of the oxide semiconductor and the vicinity of the interface with the channel formation region of the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are set to 2×10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0138] In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels are formed and carriers are generated in some cases. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or the alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 To the following:

[0139] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor is likely to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm3 To the following:

[0140] Furthermore, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. In addition, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce hydrogen in the channel formation region of the oxide semiconductor as much as possible. Specifically, the hydrogen concentration measured by SIMS in the channel formation region of the oxide semiconductor is 1×10 20 atoms / cm 3 Less than 5 x 10 19 atoms / cm 3 less than 1×10 19 atoms / cm 3 less than 5×10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0141] When an oxide semiconductor in which impurities are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0142] [Other semiconductor materials] The semiconductor material that can be used for the semiconductor 125 and the semiconductor 127 is not limited to the above-mentioned oxide semiconductors. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may be used for the semiconductor 125 and the semiconductor 127. For example, a semiconductor of a single element such as silicon, a compound semiconductor such as gallium arsenide, a layered material that functions as a semiconductor (also referred to as an atomic layer material, a two-dimensional material, or the like) may be used for the semiconductor material. In particular, it is preferable to use a layered material that functions as a semiconductor for the semiconductor material.

[0143] In this specification, the layered material is a general term for a group of materials having a layered crystal structure. The layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals forces. The layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0144] Layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds that contain chalcogen. Chalcogen is a general term for elements in group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Chalcogenides include transition metal chalcogenides and group 13 chalcogenides.

[0145] It is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor as the semiconductor 125 and the semiconductor 127. Specific examples of transition metal chalcogenides that can be used as the semiconductor 125 and the semiconductor 127 include molybdenum sulfide (representatively MoS2), molybdenum selenide (representatively MoSe2), molybdenum tellurium (representatively MoTe2), tungsten sulfide (representatively WS2), tungsten selenide (representatively WSe2), tungsten tellurium (representatively WTe2), hafnium sulfide (representatively HfS2), hafnium selenide (representatively HfSe2), zirconium sulfide (representatively ZrS2), and zirconium selenide (representatively ZrSe2).

[0146] <Example of how to make a memory device> Next, an example of a method for manufacturing a memory device according to the present invention will be described with reference to FIGS. 7 to 16. Each of FIGS. 7 to 16 shows a cross section in the XZ plane, viewed from the Y direction. In this manufacturing method, an example is shown in which three memory strings 120 each having five (also referred to as "five stages") memory elements MC are manufactured, but this embodiment is not limited to this. The memory string 120 may have two or more stages of memory elements MC. For example, the memory string 120 may have four stages of memory elements MC. In addition, it is preferable that the memory string 120 has 32 or more stages, preferably 64 or more stages, more preferably 128 or more stages, and further preferably 256 or more stages of memory elements MC. In addition, by using one aspect of this embodiment, two or more memory strings 120 can be manufactured at the same time.

[0147] First, a conductor 122 is formed on a base 121 having an insulating surface, and an insulator 132 is formed around the conductor 122 (see FIG. 7).

[0148] Specifically, a conductive film is formed and processed by using a lithography method to form the conductor 122. Next, an insulating film is formed on the base 121 so as to cover the conductor 122. Next, it is preferable to perform a planarization treatment on the insulating film. In the planarization treatment, it is preferable to polish the insulating film until the surface of the conductor 122 is exposed. The insulator 132 can be formed by the above method. However, the method of forming the conductor 122 and the insulator 132 is not limited to this. The insulator 132 may be formed on the base 121, and unnecessary parts of the insulator 132 may be removed to form grooves or openings, and the conductor 122 may be formed to be embedded in the grooves or openings. Such a method of forming a conductor may be called a damascene method (single damascene method, dual damascene method). The above method can obtain the structure shown in FIG. 7.

[0149] The conductor 122 and the insulator 132 can be formed using a sputtering method, a CVD method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like.

[0150] CVD methods can be classified into plasma enhanced CVD (PECVD), which uses plasma, thermal CVD (TCVD), which uses heat, photo CVD (Photo CVD), etc. They can also be further divided into metal CVD (MCVD) and metal organic CVD (MOCVD), depending on the source gas used.

[0151] The plasma CVD method can obtain a high-quality film at a relatively low temperature. Moreover, the thermal CVD method is a film formation method that can reduce plasma damage to the object to be processed because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitive elements, etc.) included in a semiconductor device may be charged up by receiving electric charge from plasma. At this time, the wiring, electrodes, elements, etc. included in the semiconductor device may be destroyed by the accumulated electric charge. On the other hand, in the case of the thermal CVD method that does not use plasma, such plasma damage does not occur, so the yield of the semiconductor device can be increased. Furthermore, in the thermal CVD method, plasma damage does not occur during film formation, so a film with few defects can be obtained.

[0152] The ALD method is also a film formation method that can reduce plasma damage to the workpiece. Also, since the ALD method does not cause plasma damage during film formation, films with fewer defects can be obtained.

[0153] The CVD method and the ALD method are different from the film formation method in which particles emitted from a target or the like are deposited, and are film formation methods in which a film is formed by a reaction on the surface of a workpiece. Therefore, they are film formation methods that are not easily affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, so it is suitable for coating the surface of an opening with a high aspect ratio. However, since the ALD method has a relatively slow film formation speed, it may be preferable to use it in combination with other film formation methods such as the CVD method, which has a fast film formation speed.

[0154] In the CVD method and the ALD method, the composition of the film obtained can be controlled by the flow rate ratio of the raw material gases. For example, in the CVD method and the ALD method, a film of any composition can be formed by changing the flow rate ratio of the raw material gases. In addition, for example, in the CVD method and the ALD method, a film whose composition changes continuously can be formed by changing the flow rate ratio of the raw material gases while forming the film. When forming a film while changing the flow rate ratio of the raw material gases, the time required for film formation can be shortened by the time required for transportation and pressure adjustment compared to the case of forming a film using multiple film formation chambers. Therefore, the productivity of semiconductor devices can be increased in some cases.

[0155] In the lithography method, first, the resist is exposed through a photomask. Next, the exposed area is removed or left using a developer to form a resist mask. Next, a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape by etching through the resist mask. For example, a resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, extreme ultraviolet (EUV: Extreme Ultraviolet) light, or the like. Also, a liquid immersion technique may be used in which a liquid (e.g., water) is filled between the substrate and the projection lens and exposure is performed. Also, an electron beam or an ion beam may be used instead of the light described above. When an electron beam or an ion beam is used, a photomask is not required. To remove the resist mask, a dry etching process such as ashing may be performed, a wet etching process may be performed, a wet etching process may be performed after the dry etching process, or a dry etching process may be performed after the wet etching process.

[0156] Instead of the resist mask, a hard mask made of an insulator or a conductor may be used. In the case of using a hard mask, an insulating film or a conductive film that serves as a hard mask material is formed on a conductive film, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask having a desired shape.

[0157] The above processing can be performed by dry etching or wet etching. Dry etching is suitable for fine processing.

[0158] As the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes can be configured to apply a high frequency power supply to one of the parallel plate electrodes. Alternatively, it can be configured to apply a plurality of different high frequency power supplies to one of the parallel plate electrodes. Alternatively, it can be configured to apply a high frequency power supply of the same frequency to each of the parallel plate electrodes. Alternatively, it can be configured to apply a high frequency power supply of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high density plasma source can be used. As the dry etching apparatus having a high density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus or the like can be used.

[0159] When a hard mask is used for etching the conductive film, the etching process may be performed after removing the resist mask used for forming the hard mask, or may be performed while leaving the resist mask. In the latter case, the resist mask may disappear during etching. The hard mask may be removed by etching after etching the conductive film. On the other hand, if the material of the hard mask does not affect a later process or can be used in a later process, it is not necessarily required to remove the hard mask.

[0160] The conductive film to be the conductor 122 is preferably formed by a sputtering method, and may contain a metal element. Alternatively, the conductive film can be formed by a CVD method.

[0161] If necessary, the surface of the insulator 132 is preferably subjected to planarization processing, which may be performed using chemical mechanical polishing (CMP) or a reflow method.

[0162] An insulating film 123A, an insulating film 135A, and a conductive film 136A are alternately laminated on the conductor 122 and the insulator 132. In this embodiment, an example is shown in which the insulating film 123A is formed on the insulator 132, the insulating film 135A is formed on the insulating film 123A, the insulating film 123A is formed on the insulating film 135A, and the conductive film 136A is formed on the insulating film 123A (see FIG. 7). The insulating film 135A, the conductive film 136A, and the insulating film 123A can be formed by a CVD method. Alternatively, a sputtering method may be used.

[0163] The conductor 122 and the conductive film 136A can be made of a conductive material such as silicon to which an impurity is added or a metal. The conductive film 136A is preferably made of a material that allows selective etching with respect to the conductor 122 and the insulating film 135A because selective etching with respect to the conductor 122 and the insulating film 135A is required in a later step. When silicon is used as the conductor 122 or the conductive film 136A, amorphous silicon or polysilicon can be used. In addition, p-type impurities or n-type impurities may be added to silicon to give it conductivity. As a conductive material containing silicon, silicide containing titanium, cobalt, or nickel can be used as the conductor 122 or the conductive film 136A. Furthermore, when a metal material is used for the conductor 122 or the conductive film 136A, a material containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. can be used.

[0164] An insulating oxide, nitride, oxynitride, nitride oxide, metal oxide, metal oxynitride, metal nitride oxide, or the like can be used as the insulator 132, the insulating film 135A, and the insulating film 123A. Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide or resin having voids, aluminum oxide, gallium oxide, hafnium oxide, zirconium oxide, an oxide having aluminum and hafnium, an oxynitride having aluminum and hafnium, an oxide having silicon and hafnium, an oxynitride having silicon and hafnium, or a nitride having silicon and hafnium can be used.

[0165] Since the insulating film 135A needs to be selectively etched with respect to the insulator 132 and the insulating film 123A in a later process, it is preferable that the insulating film 135A is made of a material that allows selective etching with respect to the insulator 132 and the insulating film 123A. For example, it is preferable that the insulator 132 and the insulating film 123A are made of silicon oxide or silicon oxynitride, and the insulating film 135A is made of silicon nitride or silicon nitride oxide.

[0166] In the present embodiment, an example is shown in which 12 layers of the insulating film 123A, 6 layers of the insulating film 135A, and 5 layers of the conductive film 136A are formed, but the number of layers is not limited to this. They can be formed according to the required performance of the semiconductor device. Here, if the number of layers of the insulating film 135A is m (m is an integer of 2 or more), the number of layers of the insulating film 123A is 2×m, and the number of layers of the conductive film 136A is m-1. For example, m can be 33 or more, preferably 65 or more, more preferably 129 or more, and even more preferably 257 or more.

[0167] An insulating film 137A is formed on the uppermost insulating film 123A, and an insulating film 138A is formed on the insulating film 137A. The insulating film 137A can be formed of the same material as the insulating film 135A using the same method as the insulating film 135A. The insulating film 138A can be formed of the same material as the insulating film 123A using the same method as the insulating film 123A. A mask 140A is formed on the insulating film 138A.

[0168] Next, the insulating film 138A, the insulating film 137A, the insulating film 123A, the insulating film 135A, and the conductive film 136A are processed using the mask 140A to form a first opening so as to expose the conductor 122 (see FIG. 8). By this processing, the mask 140A is etched, and may become a mask 140B.

[0169] Next, isotropic etching is performed on the conductive film 136A to expand the diameter of the opening of the conductive film 136A (see FIG. 9). By this process, the diameter of the opening of the conductive film 136A becomes larger than the diameter of the opening of the insulating film 138A, the insulating film 137A, the insulating film 123A, and the insulating film 135A. It can also be said that the conductive film 136A has a recess on the side of the insulating film 138A, the insulating film 137A, the insulating film 123A, or the insulating film 135A located at the upper or lower part. For such processing, isotropic etching by dry etching using gas, radicals, plasma, or the like, or isotropic etching by wet etching using a liquid can be used. The liquid used for wet etching is sometimes called an etchant. When isotropic etching is performed using dry etching, gas, radicals, plasma, or the like containing at least one of chlorine, bromine, and fluorine can be used. It is preferable to perform isotropic etching without removing the mask used to form the first opening. The first opening obtained by the above process corresponds to the opening 141 shown in FIG. 3.

[0170] Next, the insulating film 124A and the conductive film 128A are formed on the insulating film 138A and the mask 140B, and inside the first opening (see FIG. 9). Although not shown, the insulating film 124A may have a laminated structure. The insulating film 124A can be formed by using a CVD method or an ALD method. In particular, the ALD method is preferable because it can form a film with a uniform thickness even in a groove or an opening with a large aspect ratio. Alternatively, the insulating film 124A may be formed by combining the ALD method and the CVD method. When the insulating film 124A has a laminated structure, each insulating film may be formed by the same film forming apparatus or different film forming apparatuses.

[0171] The insulating film 124A formed by the above method has good coverage, and can be formed even in the recesses of the conductive film 136A. That is, the insulating film 124A can be formed so as to contact not only the side surfaces of the insulating film 123A, the insulating film 135A, and the conductive film 136A, but also part of the upper surface and part of the lower surface of the insulating film 123A.

[0172] The conductive film 128A is formed so as to fill at least the recessed portion of the conductive film 136A through the insulating film 124A, and does not necessarily need to fill the entire inside of the first opening. The conductive film 128A can be formed using a CVD method or an ALD method. In particular, the ALD method is preferable because it allows a film of uniform thickness to be formed even in a groove or an opening with a large aspect ratio. Alternatively, the conductive film 128A may be formed by combining the ALD method and the CVD method.

[0173] Next, the conductive film 128A is processed to form the conductor 128 (see FIG. 10). The conductive film 128A can be processed by isotropic etching or anisotropic etching. In forming the conductive film 128A, if the conductive film 128A fills the recess and the first opening is not completely filled as shown in FIG. 9, it is preferable to use isotropic etching to process the conductive film 128A. On the other hand, if the conductive film 128A is formed so as to fill the recess and the first opening, it is preferable to use anisotropic etching. By the above processing, the conductor 128 can be formed inside the recess.

[0174] Next, the insulating film 124A formed on the bottom of the first opening is removed to obtain the insulator 124. It is preferable to use anisotropic etching to remove the insulating film 124A. At this time, the insulating film 138A and the insulating film 124A on the mask 140B are also removed, so that the insulator 124 is provided only on the sidewall of the first opening (see FIG. 10). By removing the insulating film 124A on the bottom of the first opening, the conductor 122 is exposed again.

[0175] Next, the semiconductor film 125A is formed in the first opening so as to be in contact with the conductor 122 (see FIG. 10). The semiconductor film 125A can be formed by using a CVD method or an ALD method. In particular, the ALD method is preferable because a film with a uniform thickness can be formed even in a groove or an opening with a large aspect ratio. Alternatively, the semiconductor film 125A may be formed by combining the ALD method and the CVD method. The semiconductor film 125A is preferably an oxide semiconductor having a CAAC structure. When the semiconductor film 125A is an oxide semiconductor having a CAAC structure, the c-axis of the semiconductor film 125A is oriented in the normal direction to the surface to be formed inside the first opening. At this time, the c-axis of the semiconductor film 125A located on the side surface of the insulating film 138A, the insulating film 137A, the insulating film 123A, the insulating film 135A, and the conductive film 136A through the insulator 124 is oriented from the surface to be formed toward the axis 185 shown in FIG. 10. The axis 185 can be called the central axis of the first opening. As a result, the c-axis of the semiconductor 125 located above is oriented toward the axis 185 from the formation surface.

[0176] Here, when a metal oxide is formed as the semiconductor film 125A by an ALD method, it is preferable to form an In-Ga-Zn oxide using a precursor containing indium, a precursor containing gallium, and a precursor containing zinc.

[0177] Examples of precursors that can be used include indium-containing triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, and indium(III) chloride. Examples of precursors that can be used include gallium-containing trimethylgallium, triethylgallium, gallium trichloride, tris(dimethylamido)gallium, gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, diethylchlorogallium, and gallium(III) chloride. Examples of precursors that can be used include zinc-containing dimethylzinc, diethylzinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), and zinc chloride.

[0178] Next, an insulating film 126A is formed inside the semiconductor film 125A (see FIG. 10).

[0179] The insulating film 126A can be formed by using a CVD method or an ALD method. In particular, the ALD method is preferable because it allows a film of uniform thickness to be formed even in grooves and openings with a large aspect ratio. Alternatively, the insulating film 126A may be formed by combining the ALD method and the CVD method.

[0180] Next, the insulator 131A is formed on the upper surface of the insulating film 126A. The insulator 131A is preferably formed selectively so as not to be formed inside the first opening. Alternatively, the insulator 131A may be formed on the upper surface of the insulating film 126A and inside the first opening, and a mask may be formed on the upper surface of the insulating film 126A via the insulator 131A, and the insulator 131A inside the first opening may be selectively removed. Silicon nitride is preferably used as the insulator 131A. In order to selectively form the insulator 131A on the upper surface of the insulating film 126A, it is preferable to use a PECVD method. In addition, it is preferable to use a mixed gas containing SiH4 and N2 as the deposition gas, since the formation of the insulator 131A inside the first opening is suppressed. In addition, if the mixed gas contains NH3, the insulator 131A is easily formed inside the first opening, so it is preferable that the mixed gas does not contain NH3. In addition, when the mixed gas contains N2 and NH3, the mixing ratio of NH3 is preferably 10% or less of the mixing ratio of N2, preferably 5% or less, more preferably 1% or less. In addition, if the ratio (flow rate ratio) of N2 to SiH4 in the mixed gas is low, the amount of nitrogen contained in the insulator 131A becomes small, and amorphous silicon may be formed. Therefore, it is preferable to set the ratio (flow rate ratio) of N2 to SiH4 to 100 or more.

[0181] Next, a part of the semiconductor film 125A is made to have high resistance to form a high resistance region (i-type region). The high resistance region may be formed by irradiating the semiconductor film 125A with microwaves to remove hydrogen contained in the semiconductor film 125A. Moreover, it is preferable to irradiate the semiconductor film 125A with microwaves in an atmosphere containing oxygen, since oxygen is supplied to the semiconductor film 125A. In this embodiment, the semiconductor film 125A is irradiated with microwaves in an atmosphere containing oxygen and argon to make the semiconductor film 125A high resistance. At this time, the resistance value of the region of the semiconductor film 125A in contact with the conductor 128 may remain low.

[0182] Here, a heat treatment may be performed. The heat treatment is preferably performed in an atmosphere containing nitrogen at a temperature of 200° C. to 500° C., preferably 300° C. to 400° C. The atmosphere in which the heat treatment is performed is not limited to the above, and may be an atmosphere containing at least one of nitrogen, oxygen, and argon. The heat treatment may be performed in a reduced pressure atmosphere or an atmospheric pressure atmosphere.

[0183] The heat treatment can reduce the resistance of the semiconductor film 125A in contact with the conductor 128, and form a low-resistance region (n-type region). By performing heat treatment while the semiconductor film 125A and the conductor 128 are in contact with each other, a metal compound layer containing a metal element contained in the conductor 128 and a component of the semiconductor film 125A may be formed at the interface between the conductor 128 and the semiconductor film 125A. The formation of the metal compound layer is preferable because it reduces the resistance of the semiconductor film 125A in the region in contact with the conductor 128. In addition, the conductor 128 may absorb oxygen contained in the semiconductor film 125A. By performing heat treatment while the semiconductor film 125A and the conductor 128 are in contact with each other, the resistance of the semiconductor film 125A becomes lower. In addition, the heat treatment may turn the semiconductor film 125A into a CAAC-OS or nc-OS. In addition, the crystallinity of the semiconductor film 125A may be improved. The heat treatment may be performed before the microwave treatment.

[0184] The carrier concentration of the semiconductor film 125A after the microwave treatment and the heat treatment is 1×10 18 / cm 3 Less than 1 x 10 17 / cm 3 Less than or equal to 1×10 16 / cm 3 The carrier concentration in a region of the semiconductor film 125A in contact with the conductor 128 is preferably 1×10 18 / cm 3 More than 1×10 19 / cm 3 More preferably, 1×10 20 / cm 3 More preferably, it is equal to or greater than this.

[0185] In the above, the semiconductor film 125A is subjected to the high resistance treatment after the insulating film 126A is formed, but the present embodiment is not limited to this. The high resistance treatment may be performed before the insulating film 126A is formed.

[0186] Next, the semiconductor film 125A and the insulating film 126A formed on the bottom of the first opening are removed to obtain the semiconductor 125B and the insulator 126B. The semiconductor film 125A and the insulating film 126A are preferably removed by anisotropic etching using the insulator 131A as a mask. At this time, the insulating film 138A and the semiconductor film 125A and the insulating film 126A on the mask 140B are not removed because they are covered by the insulator 131A (see FIG. 11). By removing the semiconductor film 125A and the insulating film 126A on the bottom of the first opening, the conductor 122 is exposed again.

[0187] Next, the semiconductor film 127A is formed in the first opening so as to be in contact with the conductor 122 (see FIG. 11). At this time, the semiconductor film 127A is preferably formed so as to be in contact with the semiconductor 125B at the bottom of the first opening. The semiconductor film 127A can be formed by using a CVD method or an ALD method. In particular, the ALD method is preferable because a film with a uniform thickness can be formed even in a groove or an opening with a large aspect ratio. Alternatively, the semiconductor film 127A may be formed by combining the ALD method and the CVD method. In addition, the semiconductor film 127A is preferably an oxide semiconductor having a CAAC structure. When the semiconductor film 127A is an oxide semiconductor having a CAAC structure, the c-axis of the semiconductor film 127A is oriented in the normal direction to the surface to be formed inside the first opening. At this time, the c-axis of the semiconductor film 127A located on the side surface of the first opening is oriented from the surface to be formed toward the axis 185 shown in FIG. 11. As a result, the c-axis of the semiconductor 127 located above is oriented toward the axis 185 from the surface on which it is formed.

[0188] Here, when a metal oxide is formed as the semiconductor film 127A by an ALD method, it is preferable to form an In-Ga-Zn oxide using a precursor containing indium, a precursor containing gallium, and a precursor containing zinc.

[0189] Examples of precursors that can be used include indium-containing triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, and indium(III) chloride. Examples of precursors that can be used include gallium-containing trimethylgallium, triethylgallium, gallium trichloride, tris(dimethylamido)gallium, gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, diethylchlorogallium, and gallium(III) chloride. Examples of precursors that can be used include zinc-containing dimethylzinc, diethylzinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), and zinc chloride.

[0190] Next, an insulating film 129A is formed inside the semiconductor film 127A, and a conductive film 130A is formed inside the insulating film 129A (see FIG. 11). The semiconductor film 127A, the insulating film 129A, and the conductive film 130A can be formed by using a CVD method or an ALD method. By using the CVD method or the ALD method, a film with a uniform thickness can be formed even in a groove or an opening with a large aspect ratio, which is preferable. Alternatively, the ALD method and the CVD method may be combined to form the films. Also, different film formation methods and film formation devices may be used for each film to be formed. For example, the ALD method is preferably used to form the semiconductor film 127A.

[0191] Here, the semiconductor film 127A may be subjected to high resistance treatment similar to that performed on the semiconductor film 125A. When the semiconductor film 127A is subjected to high resistance treatment, the high resistance treatment is preferably performed before forming the conductive film 130A or before forming the insulating film 129A. When the semiconductor film 127A is subjected to high resistance treatment, the semiconductor film 125A can also be made high-resistance by the high resistance treatment, the previous high resistance treatment may be omitted.

[0192] Next, heat treatment is performed. The heat treatment is preferably performed in an atmosphere containing nitrogen at a temperature of 200° C. to 500° C., preferably 300° C. to 400° C. The atmosphere in which the heat treatment is performed is not limited to the above and may be an atmosphere containing at least one of nitrogen, oxygen, and argon. The heat treatment may be performed in a reduced pressure atmosphere or an atmospheric pressure atmosphere. The heat treatment may cause the semiconductor film 127A to become a CAAC-OS or an nc-OS. The crystallinity of the semiconductor film 127A may be improved.

[0193] Next, the conductive film 130A, the insulating film 129A, the semiconductor film 127A, the insulator 131A, the insulator 126B, the semiconductor 125B, and the mask 140B are processed to obtain the conductor 130, the insulator 129, the semiconductor 127, the insulator 131, the insulator 126, the semiconductor 125, and the mask 140 (see FIG. 12). This processing can be performed using a dry etching method or a wet etching method. Processing using a dry etching method is suitable for fine processing. In this processing, the conductive film 130A may be processed, the insulating film 129A and the semiconductor film 127A may be processed after the processing of the conductive film 130A, and the insulator 131A, the insulator 126B, the semiconductor 125B, and the mask 140B may be processed after the processing of the insulating film 129A and the semiconductor film 127A. In such processing steps, a different mask may be formed in each processing step. Alternatively, the conductive film 130A, the insulating film 129A, the semiconductor film 127A, the insulator 131A, the insulator 126B, the semiconductor 125B, and the mask 140B may be processed using a mask as a first processing, and then the conductive film 130A, the insulating film 129A, and the semiconductor film 127A may be processed again as a second processing, and further the conductive film 130A may be processed again as a third processing. The mask used in the second processing and the third processing may be the mask used in the first processing, which has been processed, or a different mask may be formed.

[0194] Next, an insulator 139 is formed on the insulating film 138A so as to cover the conductor 130, the insulator 129, the semiconductor 127, the insulator 131, the insulator 126, the semiconductor 125, and the mask 140. The insulator 139 can be formed by a method that can be used to form the insulator 132, and can use a material that can be used for the insulator 132.

[0195] Next, the insulator 139, the insulating film 138A, the insulating film 137A, the insulating film 123A, the insulating film 135A, and the conductive film 136A are processed to form the stepped insulator 139, the insulator 138, the insulator 137, the insulator 123, the insulator 135, and the conductor 136 as shown in Fig. 13. In processing the insulator 139, the insulating film 138A, the insulating film 137A, the insulating film 123A, the insulating film 135A, and the conductive film 136A, etching of the insulator 139, the insulating film 138A, the insulating film 137A, the insulating film 123A, the insulating film 135A, and the conductive film 136A and slimming of the mask are alternately performed, whereby the stepped insulator 139, the insulator 138, the insulator 137, the insulator 123, the insulator 135, and the conductor 136 can be formed.

[0196] Next, the insulator 150 is formed (see FIG. 13). The insulator 150 can be formed by using a CVD method. The insulator 150 is preferably subjected to a planarization process by using a CMP method or a reflow method.

[0197] Next, in order to separate the memory strings 120 arranged in the Y direction, the insulators 150, 139, 138, 137, 123, 135, and conductor 136 are processed to form slits. The slits are not shown in the figure because they are formed in the Y direction of the cross section shown in FIG. The slits are formed to extend in the X direction. The slits are preferably formed between each of the memory strings 120 arranged in the Y direction.

[0198] Next, the insulator 137 and the insulator 135 are removed (see FIG. 14). Wet etching or dry etching can be used to remove the insulator 137 and the insulator 135. An etchant used in the wet etching or a gas used in the dry etching is introduced through a slit, and the insulator 137 and the insulator 135 are removed by isotropic etching. At least one of CH3F, CH2F2, and CHF3 can be used as an etching gas for the insulator 137 and the insulator 135. A mixed gas containing at least one of the above gases can also be used. An example of the mixed gas is a mixed gas containing at least one of the above gases and one gas selected from He, Ne, Ar, Kr, Xe, and Rn. Phosphoric acid can also be used as an etchant for the insulator 137 and the insulator 135. When wet etching is used to remove the insulator 137 and the insulator 135, the etching rate of the insulator 137 and the insulator 135 can be controlled by adjusting the temperature of the etchant. It is preferable to etch the insulator 137 and the insulator 135 by heating phosphoric acid.

[0199] By removing the insulators 137 and 135, a layer that becomes a cavity is generated between the insulators 123 located above and below.

[0200] Conductors to become the conductor 182 and the conductor 183 are formed in the region from which the insulator 137 and the insulator 135 have been removed (see FIG. 15). The conductor can be formed by using a CVD method or an ALD method. In particular, the ALD method is preferable because a film with a uniform thickness can be formed even in a groove or an opening with a large aspect ratio. In addition, a material that can be used for the conductor 122 or the conductive film 136A can be used as the conductor. The conductor may contain the same material as the conductor 122 or the conductive film 136A, or may be a different material. In addition, in order to suppress oxidation of the conductor, it is preferable to form the insulator 181 before forming the conductor. It is preferable that the insulator 181 has a barrier property against oxygen. The insulator 181 can be formed by using an ALD method. By using the ALD method, the insulator 181 can be formed on the upper surface of the insulator 123, the lower surface of the insulator 123, the side surface of the insulator 124, and the side surface of the insulator 150.

[0201] Next, the conductors located in the slits formed in the previous step are anisotropically etched to obtain conductors 182 and 183 (see FIG. 15). Here, the conductor formed in the region where insulator 135 was provided is referred to as conductor 182, and the conductor formed in the region where insulator 137 was provided is referred to as conductor 183. Conductors 182 and 183 are covered with insulator 181 on the periphery, except for the surface located on the slit side, i.e., the surface perpendicular to the Y direction.

[0202] Next, an insulator is formed so as to fill the portion removed by the above processing, i.e., the slit portion. The insulator can be formed by using a CVD method or an ALD method. In particular, the ALD method is preferable because it can form a film of uniform thickness even in a groove or an opening with a large aspect ratio. Alternatively, the insulator may be formed by combining the ALD method and the CVD method. The insulator is preferably planarized by using a CMP method or a reflow method.

[0203] Next, insulator 150, insulator 139, insulator 129, insulator 131, insulator 126, insulator 138, and insulator 181 are processed using a lithography method, and second openings are formed so as to expose conductor 182, conductor 136, conductor 130, conductor 183, semiconductor 125, and semiconductor 127. Second openings are formed for conductor 182 and conductor 136, which are formed in a stepped shape (see FIG. 16).

[0204] Next, the conductor 161 electrically connected to the conductor 182, the conductor 162 electrically connected to the conductor 136, the conductor 164 electrically connected to the conductor 183, the conductor 165 electrically connected to the semiconductor 125, and the conductor 166 electrically connected to the semiconductor 127 are formed so as to be embedded in the second opening (see FIG. 16). The conductors 161, 162, 164, 165, and 166 can be formed using a CVD method or an ALD method. In particular, the ALD method is preferable because a film with a uniform thickness can be formed even in a groove or an opening with a large aspect ratio. Alternatively, the conductors may be formed by combining the ALD method and the CVD method. The conductors 161, 162, 164, 165, and 166 may have a laminated structure consisting of a plurality of layers. Conductor 161, conductor 162, conductor 164, conductor 165, and conductor 166 can be formed by forming a conductive film on insulator 150 and inside the second opening, and removing unnecessary conductive film using CMP or the like.

[0205] Next, conductor 171 electrically connected to conductor 161, conductor 172 electrically connected to conductor 162, conductor 174 electrically connected to conductor 164, conductor 175 electrically connected to conductor 165, and conductor 176 electrically connected to conductor 166 are formed (see FIG. 16). Conductors 171, 172, conductor 174, conductor 175, and conductor 176 can be formed by forming a conductive film on insulator 150 and processing it using a lithography method. This processing can be performed using a dry etching method or a wet etching method. Processing using a dry etching method is suitable for fine processing.

[0206] Conductor 171, conductor 161, and conductor 182 function as conductor SG or conductor WWL. Conductor 172, conductor 162, and conductor 136 function as conductor RWL. Conductor 174, conductor 164, and conductor 183 function as conductor SEL. Conductor 175 and conductor 165 function as conductor WBL. Conductor 176 and conductor 166 function as conductor RBL.

[0207] Next, insulator 156 is formed to cover insulator 150, the insulator formed to fill the slits, conductor 171, conductor 172, conductor 174, conductor 175, and conductor 176 (see FIG. 16). Insulator 156 can be formed by using a CVD method, an ALD method, a sputtering method, or the like.

[0208] Next, the insulators 156, 150, and 139 are processed using a lithography method to form a third opening so as to expose the conductor 130 (see FIG. 16).

[0209] Next, a conductor 163 is formed to be electrically connected to the conductor 130 so as to be embedded in the third opening (see FIG. 16). The conductor 163 can be formed by using a CVD method or an ALD method. In particular, the ALD method is preferable because it allows a film of uniform thickness to be formed even in a groove or opening with a large aspect ratio. Alternatively, the conductor may be formed by combining the ALD method and the CVD method. The conductor 163 may have a laminated structure consisting of multiple layers. The conductor 163 can be formed by forming a conductive film on the insulator 156 and inside the third opening, and removing unnecessary conductive film by using CMP or the like.

[0210] Next, a conductor 173 is formed to be electrically connected to the conductor 163 (see FIG. 16). The conductor 173 can be formed by forming a conductive film on the insulator 156 and processing it using a lithography method. This processing can be performed using a dry etching method or a wet etching method. Processing using a dry etching method is suitable for fine processing.

[0211] The conductor 173, the conductor 163, and the conductor 130 function as the conductor BG. Through the above steps, a transistor STr1 having the semiconductor 127 functioning as a channel formation region and the conductor 182 functioning as a gate, a transistor STr2 having the semiconductor 125 functioning as a channel formation region and the semiconductor 127 and the conductor 183 functioning as a gate, a transistor WTr having the semiconductor 125 functioning as a channel formation region and the conductor 182 functioning as a gate, and a transistor RTr having the semiconductor 127 functioning as a channel formation region, the conductor 136 functioning as a gate, the conductor 130 functioning as a back gate, and the conductor 128 between the semiconductor 127 and the conductor 136 can be manufactured. In addition, a memory device including the transistor STr1, the transistor STr2, the transistor WTr, and the transistor RTr can be manufactured.

[0212] <Example of film formation equipment configuration> Here, as an example of an apparatus capable of forming a film by the ALD method, the configuration of a film formation apparatus 4000 will be described with reference to Fig. 17A and Fig. 17B. Fig. 17A is a schematic diagram of a multi-chamber type film formation apparatus 4000, and Fig. 17B is a cross-sectional view of an ALD apparatus that can be used for the film formation apparatus 4000.

[0213] The film forming apparatus 4000 includes a loading / unloading chamber 4002, a loading / unloading chamber 4004, a transfer chamber 4006, a film forming chamber 4008, a film forming chamber 4009, a film forming chamber 4010, and a transfer arm 4014. Here, the loading / unloading chamber 4002, the loading / unloading chamber 4004, and the film forming chambers 4008 to 4010 are independently connected to the transfer chamber 4006. This allows continuous film formation in the film forming chambers 4008 to 4010 without exposure to the atmosphere, and prevents impurities from being mixed into the film. In addition, contamination of the interface between the substrate and the film and the interface between each film is reduced, and clean interfaces are obtained.

[0214] In addition, in order to prevent moisture from adhering to the loading / unloading chamber 4002, the loading / unloading chamber 4004, the transfer chamber 4006, and the film forming chambers 4008 to 4010, it is preferable to fill them with an inert gas (such as nitrogen gas) with a controlled dew point, and it is desirable to maintain a reduced pressure.

[0215] Further, an ALD apparatus can be used in the film formation chambers 4008 to 4010. Further, a film formation apparatus other than an ALD apparatus may be used in any of the film formation chambers 4008 to 4010. Examples of the film formation apparatus that can be used in the film formation chambers 4008 to 4010 include a sputtering apparatus, a plasma CVD (PECVD: Plasma Enhanced CVD) apparatus, a thermal CVD (TCVD: Thermal CVD) apparatus, a photo CVD (Photo CVD) apparatus, a metal CVD (MCVD: Metal CVD) apparatus, and a metal organic CVD (MOCVD: Metal Organic CVD) apparatus. Further, any one or more of the film formation chambers 4008 to 4010 may be provided with an apparatus having a function other than that of a film formation apparatus. Examples of such an apparatus include a heating apparatus (typically, a vacuum heating apparatus) and a plasma generating apparatus (typically, a microwave plasma generating apparatus).

[0216] For example, when the film formation chamber 4008 is an ALD apparatus, the film formation chamber 4009 is a PECVD apparatus, and the film formation chamber 4010 is a metal CVD apparatus, a metal oxide can be formed in the film formation chamber 4008, an insulating film that functions as a gate insulating film can be formed in the film formation chamber 4009, and a conductive film that functions as a gate electrode can be formed in the film formation chamber 4010. At this time, the metal oxide, the insulating film thereon, and the conductive film thereon can be continuously formed without exposing them to the atmosphere.

[0217] Further, although the film forming apparatus 4000 is configured to include a loading / unloading chamber 4002, a loading / unloading chamber 4004, and film formation chambers 4008 to 4010, the present invention is not limited thereto. The film forming apparatus 4000 may be configured to have four or more film formation chambers. Further, the film forming apparatus 4000 may be a single wafer type or a batch type in which a plurality of substrates are film-formed at once.

[0218] <ALD apparatus> Next, the configuration of the ALD apparatus that can be used in the film forming apparatus 4000 will be described with reference to FIG. 17B. The ALD apparatus includes a film formation chamber (chamber 4020), a raw material supply unit 4021 (raw material supply units 4021a and 4021b), a raw material supply unit 4031, high-speed valves 4022a and 4022b that are introduction amount controllers, raw material inlets 4023 (raw material inlets 4023a and 4023b), a raw material inlet 4033, a raw material discharge port 4024, and an exhaust device 4025. The raw material inlets 4023a, 4023b, and 4033 installed in the chamber 4020 are respectively connected to the raw material supply units 4021a, 4021b, and 4031 via supply pipes and valves, and the raw material discharge port 4024 is connected to the exhaust device 4025 via a discharge pipe, a valve, and a pressure regulator.

[0219] Also, by connecting a plasma generator 4028 to the chamber 4020 as shown in FIG. 17B, a film can be formed by the plasma ALD method in addition to the thermal ALD method. The plasma generator 4028 is preferably an ICP type plasma generator using a coil 4029 connected to a high-frequency power source. The high-frequency power source can output power having a frequency of 10 kHz to 100 MHz, preferably 1 MHz to 60 MHz, more preferably 10 MHz to 60 MHz. For example, it can output power having a frequency of 13.56 MHz or 60 MHz. In the plasma ALD method, a film can be formed without decreasing the film formation rate even at a low temperature, so it is suitable for use in a single-wafer type film formation device with low film formation efficiency.

[0220] Inside the chamber, there is a substrate holder 4026, and a substrate 4030 is placed on the substrate holder 4026. The substrate holder 4026 may be provided with a mechanism for applying a constant potential or high frequency. Alternatively, the substrate holder 4026 may be floating or grounded. In addition, a heater 4027 is provided on the outer wall of the chamber, and is capable of controlling the temperature of the inside of the chamber 4020, the substrate holder 4026, the surface of the substrate 4030, and the like. The heater 4027 is preferably capable of controlling the temperature of the surface of the substrate 4030 to 100° C. or more and 500° C. or less, preferably 200° C. or more and 400° C. or less, and the temperature of the heater 4027 itself is preferably capable of being set to 100° C. or more and 500° C. or less.

[0221] In the raw material supplying units 4021a, 4021b, and 4031, a raw material gas is formed from a solid raw material or a liquid raw material by a vaporizer, a heating means, etc. Alternatively, the raw material supplying units 4021a, 4021b, and 4031 may be configured to supply a gaseous raw material gas.

[0222] 17B shows an example in which two raw material supply units 4021 and one raw material supply unit 4031 are provided, but this embodiment is not limited to this. One raw material supply unit 4021, or three or more raw material supply units 4021 may be provided. Two or more raw material supply units 4031 may be provided. High-speed valves 4022a and 4022b can be precisely controlled in time, and are configured to control the supply of raw material gas supplied from raw material supply unit 4021a and raw material supply unit 4021b.

[0223] In the film forming apparatus shown in FIG. 17B, the substrate 4030 is loaded onto the substrate holder 4026, the chamber 4020 is sealed, and then the substrate 4030 is heated to a desired temperature (for example, 100° C. to 500° C., preferably 200° C. to 400° C.) by the heater 4027. A thin film is formed on the substrate surface by repeating the supply of a source gas from the source supply unit 4021a, exhaust by the exhaust device 4025, supply of a source gas from the source supply unit 4031, and exhaust by the exhaust device 4025. In addition, in the formation of the thin film, the supply of a source gas from the source supply unit 4021b and exhaust by the exhaust device 4025 may be further performed. The temperature of the heater 4027 may be appropriately determined depending on the type of film to be formed, the source gas, the desired film quality, and the heat resistance of the substrate and the films and elements provided thereon. For example, the temperature of the heater 4027 may be set to 200° C. or higher and 300° C. or lower during film formation, or may be set to 300° C. or higher and 500° C. or lower during film formation.

[0224] By forming a film while heating the substrate 4030 using the heater 4027, it is possible to omit a heat treatment of the substrate 4030 that is required in a later step. That is, by using the chamber 4020 or the film formation apparatus 4000 provided with the heater 4027, the formation of a film on the substrate 4030 and the heat treatment of the substrate 4030 can be performed at the same time.

[0225] In the film formation apparatus shown in FIG. 17B, a metal oxide can be formed by appropriately selecting the raw materials (such as a volatile organometallic compound) used in the raw material supply unit 4021 and the raw material supply unit 4031.

[0226] When forming an In-Ga-Zn oxide containing indium, gallium, and zinc as a metal oxide, it is preferable to use a film formation apparatus provided with at least three raw material supply parts 4021 in addition to the raw material supply part 4031. That is, it is preferable that a precursor containing indium is supplied from the first raw material supply part 4021, a precursor containing gallium is supplied from the second raw material supply part 4021, and a precursor containing zinc is supplied from the third raw material supply part 4021.

[0227] When a precursor containing gallium and zinc is used to form a metal oxide, at least two raw material supply units 4021 may be provided. The precursor containing indium, the precursor containing gallium, and the precursor containing zinc may be the precursors described above.

[0228] In addition, a reactant is supplied from the raw material supply unit 4031. As the reactant, an oxidizing agent containing at least one of ozone, oxygen, and water can be used.

[0229] In addition, by appropriately selecting the raw materials (such as volatile organometallic compounds) used in the raw material supply units 4021a, 4021b, and 4031, it is possible to form an insulating layer containing an oxide (including a composite oxide) containing one or more elements selected from hafnium, aluminum, tantalum, zirconium, etc. Specifically, it is possible to form an insulating layer containing hafnium oxide, an insulating layer containing aluminum oxide, an insulating layer containing hafnium silicate, or an insulating layer containing aluminum silicate. In addition, by appropriately selecting the raw materials (such as volatile organometallic compounds) used in the raw material supply units 4021a, 4021b, and 4031, it is also possible to form thin films such as metal layers such as a tungsten layer and a titanium layer, and nitride layers such as a titanium nitride layer.

[0230] For example, when a hafnium oxide layer is formed by using an ALD apparatus, a first source gas obtained by vaporizing a liquid containing a solvent and a hafnium precursor compound (hafnium alkoxide or hafnium amide such as tetrakisdimethylamidohafnium (TDMAHf)) and a second source gas of ozone (O3) and oxygen (O2) as oxidizing agents are used. In this case, the first source gas supplied from the source supply unit 4021a is TDMAHf, and the second source gas supplied from the source supply unit 4031 is ozone and oxygen. The chemical formula of tetrakisdimethylamidohafnium is Hf[N(CH3)2]4. Other material liquids include tetrakis(ethylmethylamido)hafnium. Water can be used as the second source gas.

[0231] When forming an aluminum oxide layer using an ALD apparatus, a first source gas obtained by vaporizing a liquid containing a solvent and an aluminum precursor compound (TMA: trimethylaluminum, etc.) and a second source gas containing ozone (O3) and oxygen (O2) as oxidizing agents are used. In this case, the first source gas supplied from the source supply unit 4021a is TMA, and the second source gas supplied from the source supply unit 4031 is ozone and oxygen. The chemical formula of trimethylaluminum is Al(CH3)3. Other material liquids include tris(dimethylamido)aluminum, triisobutylaluminum, and aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate). Water can be used as the second source gas.

[0232] Fig. 18 describes a different configuration of an ALD apparatus that can be used for the film formation apparatus 4000. Note that detailed description of the same configuration and functions as those of the ALD apparatus shown in Fig. 17B may be omitted.

[0233] FIG. 18A is a schematic diagram showing one embodiment of a plasma ALD apparatus. The plasma ALD apparatus 4100 is provided with a reaction chamber 4120 and a plasma generation chamber 4111 above the reaction chamber 4120. The reaction chamber 4120 can be called a chamber. Alternatively, the reaction chamber 4120 and the plasma generation chamber 4111 can be collectively called a chamber. The reaction chamber 4120 has a raw material inlet 4123 and a raw material outlet 4124, and the plasma generation chamber 4111 has a raw material inlet 4133. In addition, a plasma generation device 4128 can apply high frequency such as RF or microwaves to a gas introduced into the plasma generation chamber 4111 to generate plasma 4131 in the plasma generation chamber 4111. When the plasma 4131 is generated using microwaves, microwaves with a frequency of 2.45 GHz are typically used. Such plasma generated using microwaves may be called ECR (Electron Cyclotron Resonance) plasma. The reaction chamber 4120 has a substrate holder 4126 on which a substrate 4130 is placed. The source gas introduced from the source inlet 4123 is decomposed by heat from a heater provided in the reaction chamber 4120 and deposited on the substrate 4130. The source gas introduced from the source inlet 4133 is turned into a plasma state by the plasma generating device 4128. The source gas in the plasma state recombines with electrons and other molecules before reaching the surface of the substrate 4130, and reaches the substrate 4130 in a radical state. An ALD device that uses radicals to form a film in this way may be called a radical ALD (radical-enhanced ALD) device. In addition, the plasma ALD device 4100 shows a configuration in which the plasma generation chamber 4111 is provided at the top of the reaction chamber 4120, but this embodiment is not limited to this. The plasma generation chamber 4111 may be provided adjacent to the side of the reaction chamber 4120.

[0234] FIG. 18B is a schematic diagram showing one embodiment of a plasma ALD apparatus. The plasma ALD apparatus 4200 has a chamber 4220. The chamber 4220 has an electrode 4213, a raw material outlet 4224, and a substrate holder 4226, and a substrate 4230 is placed thereon. The electrode 4213 has a raw material inlet 4223 and a shower head 4214 that supplies the introduced raw material gas into the chamber 4220. A power source 4215 that can apply high frequency power is connected to the electrode 4213 via a capacitor 4217. The substrate holder 4226 may be provided with a mechanism for applying a constant potential or high frequency power. Alternatively, the substrate holder 4226 may be floating or grounded. The electrode 4213 and the substrate holder 4226 function as an upper electrode and a lower electrode for generating a plasma 4231, respectively. The raw material gas introduced from the raw material inlet 4223 is decomposed by heat from a heater provided in the chamber 4220 and deposited on the substrate 4230. Alternatively, the raw material gas introduced from the raw material inlet 4223 becomes a plasma state between the electrode 4213 and the substrate holder 4226. The raw material gas in the plasma state is incident on the substrate 4230 due to a potential difference (also called an ion sheath) generated between the plasma 4231 and the substrate 4230.

[0235] FIG. 18C is a schematic diagram showing an embodiment of a plasma ALD apparatus different from that shown in FIG. 18B. The plasma ALD apparatus 4300 has a chamber 4320. The chamber 4320 has an electrode 4313, a raw material outlet 4324, and a substrate holder 4326, and a substrate 4330 is placed thereon. The electrode 4313 has a raw material inlet 4323 and a shower head 4314 that supplies the introduced raw material gas into the chamber 4320. A power source 4315 that can apply high frequency power is connected to the electrode 4313 via a capacitor 4317. The substrate holder 4326 may be provided with a mechanism for applying a constant potential or high frequency power. Alternatively, the substrate holder 4326 may be floating or grounded. The electrode 4313 and the substrate holder 4326 function as an upper electrode and a lower electrode for generating a plasma 4331, respectively. The plasma ALD apparatus 4300 is different from the plasma ALD apparatus 4200 in that it has a mesh 4319 connected to a power source 4321 capable of applying high frequency through a capacitor 4322 between the electrode 4313 and the substrate holder 4326. By providing the mesh 4319, the plasma 4231 can be separated from the substrate 4130. The source gas introduced from the source inlet 4323 is decomposed by heat from a heater provided in the chamber 4320 and deposited on the substrate 4330. Alternatively, the source gas introduced from the source inlet 4323 becomes a plasma state between the electrode 4313 and the substrate holder 4326. The charge of the source gas in the plasma state is removed by the mesh 4319, and the source gas reaches the substrate 4130 in an electrically neutral state such as radicals. This allows film formation to be performed with reduced incidence of ions and damage caused by plasma.

[0236] By forming the semiconductor 125 or the semiconductor 127 using the ALD method, it may be possible to form a metal oxide having a CAAC structure in which the c-axis is oriented approximately parallel to the normal direction of the deposition surface.

[0237] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes.

[0238] (Embodiment 2) In this embodiment, a circuit configuration and operation of a memory string 120, which is a memory device, will be described. Fig. 19 shows an example of a circuit configuration of the memory string 120. Fig. 20 shows an equivalent circuit diagram of a memory element MC.

[0239] In addition, in drawings and the like, in order to make the potential of a wiring, electrode, conductor, etc. easier to understand, an "H" indicating an H potential or an "L" indicating an L potential may be added next to the wiring, electrode, conductor, etc. Furthermore, a wiring, electrode, conductor, etc. in which a potential change has occurred may be labeled with "H" or "L" enclosed in letters. Furthermore, when a transistor is in an off state, an "x" symbol may be added over the transistor.

[0240] <Memory string circuit configuration example> FIG. 19 shows an example of a circuit configuration of a memory string 120 including five memory elements MC. The memory elements MC have a transistor WTr and a transistor RTr. In FIG. 19, the transistor WTr included in the memory element MC[1] is shown as a transistor WTr[1], and the transistor RTr included in the memory element MC[1] is shown as a transistor RTr[1]. Thus, the memory string 120 shown in FIG. 19 has transistors WTr[1] to WTr[5] and transistors RTr[1] to RTr[5]. The memory string 120 shown in FIG. 19 also has transistors STr1, STr2, and STr3. The memory string 120 is a NAND type memory device.

[0241] In an equivalent circuit diagram, the circuit symbol of a transistor may be marked with "OS" to indicate that the transistor is an OS transistor. Similarly, the circuit symbol of a transistor may be marked with "Si" to indicate that the transistor is a Si transistor (a transistor that uses silicon in the semiconductor layer in which the channel is formed). In FIG. 19, the transistors WTr and RTr are shown to be OS transistors.

[0242] A NAND type storage device that includes an OS memory is also called an "OS NAND type" or "OS NAND type storage device." Additionally, an OS NAND type storage device that has multiple OS memories stacked in the Z direction is also called a "3D OS NAND type" or "3D OS NAND type storage device."

[0243] The transistor WTr is a normally-off transistor. The transistor RTr is a normally-on transistor. As described in the above embodiment, the transistor RTr includes a conductor 128 between the gate and the semiconductor layer. The conductor 128 can function as a floating gate of the transistor RTr. For example, the conductor 128 included in the transistor RTr[1] is called the conductor 128[1].

[0244] A junction where the conductor 128 and one of the source and drain of the transistor WTr are electrically connected is referred to as a node ND. For example, a junction where the conductor 128[1] and one of the source and drain of the transistor WTr[1] are electrically connected is referred to as a node ND[1].

[0245] One of the source or drain of the transistor RTr[1] is electrically connected to one of the source or drain of the transistor STr1, and the other is electrically connected to one of the source or drain of the transistor RTr[2]. The gate of the transistor RTr[1] is electrically connected to the conductor RWL[1]. The back gate of the transistor RTr[1] is electrically connected to the conductor BG. One of the source or drain of the transistor WTr[1] is electrically connected to the conductor 128[1], and the other is electrically connected to the conductor 128[2]. The gate of the transistor WTr[1] is electrically connected to the conductor WWL[1]. In addition, the other of the source or drain of the transistor STr1 is electrically connected to the conductor 122, and the gate is electrically connected to the conductor SG.

[0246] 20, the transistor RTr can be expressed by replacing it with a capacitance Cs and a transistor Tr. The gate of the transistor Tr is electrically connected to the conductor RWL via the capacitance Cs.

[0247] In addition, one of the source or drain of the transistor RTr[5] is electrically connected to the other of the source or drain of the transistor RTr[4], and the other is electrically connected to one of the source or drain of the transistor STr2. The gate of the transistor RTr[5] is electrically connected to the conductor RWL[5]. The back gate of the transistor RTr[5] is electrically connected to the conductor BG. One of the source or drain of the transistor WTr[5] is electrically connected to the conductor 128[5], and the other is electrically connected to one of the source or drain of the transistor STr3. The gate of the transistor WTr[5] is electrically connected to the conductor WWL[5]. In addition, the other of the source or drain of the transistor STr2 is electrically connected to the conductor RBL, and the gate is electrically connected to the conductor RSEL. In addition, the other of the source or drain of the transistor STr3 is electrically connected to the conductor WBL, and the gate is electrically connected to the conductor WSEL.

[0248] When the memory string 120 includes n (n is an integer of 1 or more) memory elements MC, in the i-th (i is an integer of 1 to n) memory element MC[i] excluding the first and n-th memory elements MC, one of the source or drain of the transistor RTr[i] is electrically connected to the other of the source or drain of the transistor RTr[i-1], and the other is electrically connected to one of the source or drain of the transistor RTr[i+1]. The gate of the transistor RTr[i] is electrically connected to the conductor RWL[i]. The back gate of the transistor RTr[i] is electrically connected to the conductor BG. One of the source or drain of the transistor WTr[i] is electrically connected to the conductor 128[i], and the other is electrically connected to the conductor 128[i-1]. The gate of the transistor WTr[i] is electrically connected to the conductor WWL[i].

[0249] The transistors STr1 and STr2 may be, for example, OS transistors or Si transistors. One of the transistors STr1 and STr2 may be an OS transistor, and the other may be a Si transistor. When both the transistors WTr and RTr are formed of OS transistors, it is preferable that the transistors STr1 and STr2 are also formed of OS transistors. By using the same semiconductor material for the transistors, the productivity of the semiconductor device can be improved.

[0250] Alternatively, an OS transistor may be used as the transistor WTr, and a Si transistor may be used as the transistor RTr. An equivalent circuit diagram of the memory string 120 in the case where an OS transistor is used as the transistor WTr, and a Si transistor is used as the transistor RTr is shown in FIG.

[0251] When the transistor RTr is a Si transistor, polycrystalline silicon, for example, may be used for the semiconductor 125. When the transistor WTr is an OS transistor, CAAC-IGZO, for example, may be used for the semiconductor 127.

[0252] Note that, depending on the purpose or application, a Si transistor may be used as the transistor WTr and an OS transistor may be used as the transistor RTr as shown in Fig. 22. Also, depending on the purpose or application, a Si transistor may be used as both the transistor WTr and the transistor RTr as shown in Fig. 23. When Si transistors are used as both the transistor WTr and the transistor RTr, it is preferable to use Si transistors also for the transistors STr1 and STr2.

[0253] <Memory string operation example> Next, an example of the operation of the memory string 120 shown in FIG. 19 will be described.

[0254] [Write operation] In this embodiment, an operation example will be described in which an H potential is written to the memory element MC[1] and the memory element MC[3], and an L potential is written to the other memory element MC. Fig. 24 is a timing chart for explaining the write operation. Fig. 25A to Fig. 29B are circuit diagrams for explaining the write operation.

[0255] In an initial state, an L potential is written to the memory elements MC[1] to MC[5]. In addition, an L potential is supplied to the conductors WWL[1] to WWL[5], the conductors RWL[1] to RWL[5], the conductor WSEL, the conductor RSEL, the conductor BG, the conductor WBL, the conductor RBL, the conductor SG, and the conductor 122. Note that the conductor BG can control the threshold of the transistor RTr. The potential supplied to the conductor BG may be appropriately adjusted so that the transistor RTr becomes a desired normally-on type transistor. Note that the conductors WSEL and RSEL are described as being a common conductor, but may be different conductors.

[0256] [Period T1] In a period T1, an H potential is supplied to conductor WWL[1] to conductor WWL[5], conductor WBL, and conductor WSEL (and conductor RSEL) (see FIG. 25A). Then, the potentials of nodes ND[1] to ND[5] become H potentials.

[0257] [Period T2] In the period T2, the L potential is supplied to the conductor WWL[1] (see FIG. 25B). Then, the transistor WTr[1] is turned off, and the charge written to the node ND[1] is held. Here, a charge equivalent to the H potential is held.

[0258] [Period T3] In a period T3, an L potential is supplied to the conductor WBL (see FIG. 26A). Then, the potentials of the nodes ND[2] to ND[5] become an L potential. At this time, the conductors 128[2] to 128[5] also become an L potential. However, because the transistors RTr are normally-on transistors, the transistors RTr[2] to RTr[5] are not turned off.

[0259] [Period T4] In the period T4, the L potential is supplied to the conductor WWL[2] (see FIG. 26B). Then, the transistor WTr[2] is turned off, and the charge written to the node ND[2] is held. Here, the charge equivalent to the L potential is held.

[0260] [Period T5] In a period T5, an H potential is supplied to the conductor WBL (see FIG. 27A). Then, the potentials of the nodes ND[3] to ND[5] become H potentials.

[0261] [Period T6] In the period T6, the conductor WWL[3] is supplied with an L potential (see FIG. 27B). Then, the transistor WTr[3] is turned off, and the charge written to the node ND[3] is held. Here, a charge equivalent to an H potential is held.

[0262] [Period T7] In a period T7, an L potential is supplied to the conductor WBL (see FIG. 28A). Then, the potentials of the nodes ND[4] and ND[5] become L potential.

[0263] [Period T8] In the period T8, the L potential is supplied to the conductor WWL[4] (see FIG. 28B). Then, the transistor WTr[4] is turned off, and the charge written to the node ND[4] is held. Here, the charge equivalent to the L potential is held.

[0264] [Period T9] In the period T9, the conductor WBL remains at the L potential (see FIG. 29A). Therefore, the potential of the node ND[5] also remains at the L potential.

[0265] [Period T10] In a period T10, an L potential is supplied to the conductor WWL[5] (see FIG. 29B). Then, the transistor WTr[5] is turned off, and the charge written to the node ND[5] is held. Here, a charge equivalent to the L potential is held. Also, an L potential is supplied to the conductor WSEL (and the conductor RSEL).

[0266] In this manner, information can be written to the memory element MC.

[0267] In addition, when writing information to the i-th memory element MC (excluding i=1) among the multiple memory elements MC, the operation of writing information to the i-1th memory elements MC can be omitted. For example, when writing information to the memory element MC[4], it is not necessary to write information to the memory elements MC[1] to MC[3]. In other words, the write operation from the period T1 to the period T6 described in this embodiment can be omitted. Therefore, the time and power consumption required for the write operation of the memory device can be reduced.

[0268] [Read operation] An example of a read operation of the memory string 120 having the above circuit configuration will be described. As an initial state, it is assumed that an H potential is held in the memory element MC[1] and the memory element MC[3]. It is also assumed that an L potential is supplied to the conductor WWL[1] to the conductor WWL[5], the conductor RWL[1] to the conductor RWL[5], the conductor WSEL, the conductor RSEL, the conductor BG, the conductor WBL, the conductor RBL, the conductor SG, and the conductor 122. Figures 30A and 30B are timing charts for explaining the read operation. Figures 31A to 32B are circuit diagrams for explaining the read operation.

[0269] <When holding potential is H potential> First, the read operation of the memory element MC[3] in which the H potential is held will be described.

[0270] [Period T11] In a period T11, an H potential is supplied to the conductors RWL[1] to RWL[5] and the conductor RSEL (and the conductor WSEL) (see FIG. 31A). Then, the transistor STr2 (and the transistor STr3) is turned on, and the semiconductor 127 and the conductor RBL included in the transistor RTr are brought into conduction. In this state, the conductor RBL and the semiconductor 127 are precharged with an H potential, and both are brought into a floating state.

[0271] Here, the Id-Vg characteristics of a transistor will be described. Figures 33A and 33B are diagrams for explaining the Id-Vg characteristics of a transistor. The horizontal axis of Figures 33A and 33B indicates the gate voltage (Vg), and the vertical axis indicates the drain current (Id). Figure 33A shows the Id-Vg characteristics of a normally-off type transistor, and Figure 33B shows the Id-Vg characteristics of a normally-on type transistor.

[0272] The H potential is a higher potential than the L potential. If the L potential is 0V, then the H potential is a positive voltage. In a normally-off transistor, when Vg is at the L potential (0V), the channel resistance (resistance between the source and drain) is extremely large and Id hardly flows. Furthermore, when Vg becomes the H potential, the channel resistance decreases and Id increases (see Figure 33A).

[0273] In a normally-on transistor, the channel resistance is small even when Vg is at potential L, and a large amount of Id flows compared to a normally-off transistor. When Vg becomes potential H, the channel resistance becomes even smaller and Id increases even more (see FIG. 33B).

[0274] Since the transistor RTr is a normally-on transistor, it is possible to precharge the semiconductor 127 even if the potential of the conductor RWL remains at the L potential. However, by supplying the H potential to the conductor RWL, the on-resistance of the transistor RTr decreases, and therefore the time and power consumption required for precharging can be reduced.

[0275] [Period T12] In period T12, an L potential is supplied to the conductor RWL[3] (see FIG. 31B). Because the H potential is held at the node ND[3], the channel resistance of the transistor RTr[3] remains small even when the potential of the conductor RWL[3] becomes an L potential.

[0276] [Period T13] In the period T13, the H potential is supplied to the conductor SG, and the transistor STr1 is turned on (see FIG. 32A). Then, the conductor RBL and the conductor 122 are conductive. At this time, the H potential is supplied to the conductor RWL[1], the conductor RWL[2], the conductor RWL[4], and the conductor RWL[5], so that the channel resistance values ​​of the transistors RTr[1], RTr[2], RTr[4], and RTr[5] are small regardless of the potential of the node ND. Although the L potential is supplied to the conductor RWL[3], the H potential is held at the node ND[3], so that the channel resistance value of the transistor RTr[3] is also small. Therefore, the potential of the conductor RBL, which is in a floating state, changes suddenly from the H potential to the L potential (see FIG. 30A).

[0277] [Period T14] In a period T14, an L potential is supplied to the conductor RSEL (and the conductor WSEL), the conductor RWL, and the conductor SG (see FIG. 32B).

[0278] <When holding potential is L potential> Next, the read operation of the memory element MC[2] holding the L potential will be described. When reading the information (potential) held in the memory element MC[2], the potential of the conductor RWL[2] is set to the L potential in the period T12 (see FIG. 30B). At this time, since the L potential is held in the node ND[2], the channel resistance value of the transistor RTr[2] remains large.

[0279] Next, in period T13, an H potential is supplied to the conductor SG, thereby conducting the conductor RBL and the conductor 122. At this time, since the channel resistance value of the transistor RTr[2] is large, the potential change from the H potential to the L potential of the conductor RBL becomes gradual.

[0280] In this manner, in the period T13, the potential of the conductor RWL corresponding to the memory element MC to be read is set to the L potential, so that the data held in the memory element MC can be known.

[0281] <Modification> 34 shows an example of a circuit configuration of a memory string 120A which is a modified example of the memory string 120. The memory string 120A has a circuit configuration in which a transistor STr3 is added to the memory string 120.

[0282] In the memory string 120A shown in FIG. 34, the other of the source or drain of the transistor WTr[5] is electrically connected to the source or drain of the transistor STr3, not to the source or drain of the transistor STr2. The other of the source or drain of the transistor STr3 is electrically connected to the conductor BL. The gate of the transistor STr2 is electrically connected to the conductor RSEL, and the gate of the transistor STr3 is electrically connected to the conductor WSEL.

[0283] During a write operation, the transistor STr3 is turned on and the transistor STr2 is turned off. During a read operation, the transistor STr3 is turned off and the transistor STr2 is turned on. When writing or reading information via the conductor BL, the information transmission path can be switched by a dedicated transistor. This stabilizes the operation of the memory device and increases the reliability of the memory device.

[0284] Also, as in the memory string 120B shown in FIG. 35, the transistors STr2 and STr3 may be common. In this case, the other of the source or drain of the transistor STr2 may be electrically connected to the conductor BL. In the write operation and the read operation, information is written and read via the conductor BL. By providing a common conductor BL for the write operation and the read operation, the number of wirings can be reduced.

[0285] 36 has a circuit configuration in which a transistor STr4 is added to the memory string 120. One of the source or drain of the transistor STr4 is electrically connected to one of the source or drain of the transistor WTr[1], and the other is electrically connected to the conductor WBL[2]. The gate of the transistor STr4 is electrically connected to the conductor WSEL[2].

[0286] In the memory string 120B, the gate of the transistor STr3 is electrically connected to the conductor WSEL[1], and the other of the source or drain of the transistor STr3 is electrically connected to the conductor WBL[1]. Note that, as shown in FIG. 34, the circuit configuration may be such that the transistors STr2 and STr3 are electrically connected to the conductor BL.

[0287] In the memory string 120B, information can be written from both the conductor WBL[1] and the conductor WBL[2]. This allows the speed at which information can be written to be increased. In addition, the supply of electric charge corresponding to the information to be written can be more reliably achieved.

[0288] Furthermore, when writing information to the i-th memory element MC, if i is close to n, the operation of writing information to the 1st to i-1th memory elements MC can be omitted by writing information from the conductor WBL[1] side. Furthermore, if i is close to 1, the operation of writing information to the i+1th to nth memory elements MC can be omitted by writing information from the conductor WBL[2] side. In the memory string 120B, the time and power consumption required for the write operation can be further reduced.

[0289] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes.

[0290] (Embodiment 3) In this embodiment, a configuration example of a semiconductor device 200 including a memory device 100 will be described.

[0291] Fig. 37 is a block diagram illustrating a configuration example of a semiconductor device 200 according to one embodiment of the present invention. The semiconductor device 200 illustrated in Fig. 37 includes a driver circuit 210 and a memory array 220. The memory array 220 includes one or more memory devices 100. Fig. 37 illustrates an example in which the memory array 220 includes a plurality of memory devices 100 arranged in a matrix.

[0292] The drive circuit 210 has a PSW 241 (power switch), a PSW 242, and a peripheral circuit 215. The peripheral circuit 215 has a peripheral circuit 211, a control circuit 212, and a voltage generating circuit 228. The semiconductor device 200 has elements or circuits having various functions, such as a memory array 220, the PSW 241, the PSW 242, the peripheral circuit 211, the control circuit 212, and the voltage generating circuit 228. Therefore, the semiconductor device 200 may be called a system or a subsystem.

[0293] In the semiconductor device 200, each circuit, each signal, and each voltage can be appropriately selected or omitted as necessary. Alternatively, other circuits or other signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0294] Moreover, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 may be generated by the control circuit 212.

[0295] The control circuit 212 is a logic circuit having a function of controlling the overall operation of the semiconductor device 200. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine an operation mode (e.g., a write operation, a read operation) of the semiconductor device 200. Alternatively, the control circuit 212 generates a control signal for the peripheral circuit 211 so that this operation mode is executed.

[0296] The voltage generating circuit 228 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 228. For example, when an H-level signal is provided as the signal WAKE, the signal CLK is input to the voltage generating circuit 228, and the voltage generating circuit 228 generates a negative voltage.

[0297] The peripheral circuit 211 is a circuit for writing and reading data to and from the memory device 100. The peripheral circuit 211 has a row decoder 221, a column decoder 222, a row driver 223, a column driver 224, an input circuit 225, an output circuit 226, and a sense amplifier 227.

[0298] The row decoder 221 and the column decoder 222 have a function of decoding the signal ADDR. The row decoder 221 is a circuit for specifying a row to be accessed, and the column decoder 222 is a circuit for specifying a column to be accessed. The row driver 223 has a function of selecting a wiring specified by the row decoder 221. The column driver 224 has a function of writing data to the memory device 100, a function of reading data from the memory device 100, a function of holding the read data, and the like.

[0299] The input circuit 225 has a function of holding a signal WDA. The data held by the input circuit 225 is output to the column driver 224. The output data of the input circuit 225 is data (Din) to be written to the memory device 100. The data (Dout) read from the memory device 100 by the column driver 224 is output to the output circuit 226. The output circuit 226 has a function of holding Dout. In addition, the output circuit 226 has a function of outputting Dout to the outside of the semiconductor device 200. The data output from the output circuit 226 is a signal RDA.

[0300] The PSW241 has a function of controlling the supply of VDD to the peripheral circuit 215. The PSW242 has a function of controlling the supply of VHM to the row driver 223. Here, the high power supply voltage of the semiconductor device 200 is VDD, and the low power supply voltage is GND (ground potential). Also, VHM is a high power supply voltage used to set the word line to a high level, and is higher than VDD. The on / off of the PSW241 is controlled by a signal PON1, and the on / off of the PSW242 is controlled by a signal PON2. In FIG. 37, the number of power supply domains to which VDD is supplied in the peripheral circuit 215 is one, but it may be multiple. In this case, a power switch may be provided for each power supply domain.

[0301] The driving circuit 210 and the memory array 220 may be provided on the same plane. Also, as shown in Fig. 38A, the driving circuit 210 and the memory array 220 may be provided so as to overlap each other. By providing the driving circuit 210 and the memory array 220 so as to overlap each other, the signal propagation distance can be shortened. Also, as shown in Fig. 38B, the memory array 220 may be provided in multiple layers on the driving circuit 210.

[0302] Also, as shown in FIG. 38C, memory arrays 220 may be provided above and below the driving circuit 210. FIG. 38C shows an example in which one memory array 220 is provided above and below the driving circuit 210. By arranging the driving circuit 210 between a plurality of memory arrays 220, the signal propagation distance can be further shortened. Note that the number of layers of the memory array 220 stacked above the driving circuit 210 and the memory array 220 stacked below the driving circuit 210 may each be one or more. It is preferable that the number of memory arrays 220 stacked above the driving circuit 210 and the number of memory arrays 220 stacked below the driving circuit 210 are equal.

[0303] <Example of Cross-Sectional Configuration of Semiconductor Device 200> Fig. 39 shows a cross-sectional configuration example of the semiconductor device 200 shown in Fig. 38A. Fig. 39 shows a part of the semiconductor device 200 shown in Fig. 38A.

[0304] FIG. 39 shows transistors 301, 302, and 303 included in the driver circuit 210. The transistors 301 and 302 function as a part of the sense amplifier 227. The transistor 303 functions as a column selection switch. Specifically, the conductor RBL included in the memory array 220 is electrically connected to one of the source and drain of the transistor 301, the gate of the transistor 301 is electrically connected to one of the source and drain of the transistor 302, and the gate of the transistor 302 is electrically connected to the other of the source and drain of the transistor 301. The one of the source and drain of the transistor 301 and the other of the source and drain of the transistor 302 are electrically connected to one of the source and drain of the transistor 303, which functions as a column selection switch. This makes it possible to reduce the layout area of ​​the semiconductor device 200. FIG. 39 shows an example in which seven memory elements MC are provided per memory string. However, the number of memory elements MC provided in one memory string is not limited to this. For example, the number of memory elements MC provided in one memory string may be 32, 64, 128, or 200 or more.

[0305] The conductor RBL of the memory array 220 is electrically connected to the sense amplifier 227 and the transistor 303 functioning as a column selection switch through the conductor 752 formed to be embedded in the conductor 715, the conductor 714, the conductor 705, the insulator 726, the insulator 722, etc. Note that the circuits and transistors included in the driver circuit 210 are merely examples, and are not limited to the circuit configuration and transistor structure. In addition to the above, appropriate circuits and transistors such as a control circuit, a row decoder, a row driver, a source line driver, and an input / output circuit can be provided depending on the configuration of the semiconductor device 200 and its driving method.

[0306] The transistors 301, 302, and 303 are provided on a substrate 311, and each includes a conductor 316, an insulator 315, a semiconductor region 313 formed of a part of the substrate 311, and a low-resistance region 314a and a low-resistance region 314b functioning as a source region or a drain region. As shown in FIG. 39, one low-resistance region may be shared by the transistors 301 and 302 as both the source region or drain region of one of them and the source region or drain region of the other.

[0307] In the transistors 301, 302, and 303, a semiconductor region 313 (a part of a substrate 311) in which a channel is formed has a convex shape. A conductor 316 is provided to cover the side and top surface of the semiconductor region 313 via an insulator 315. Note that the conductor 316 may be made of a material that adjusts the work function. Such transistors 301, 302, and 303 are also called FIN type transistors because they use a convex portion of a semiconductor substrate. Note that an insulator that is in contact with an upper portion of the convex portion and functions as a mask for forming the convex portion may be provided. Note that, although a case where a convex portion is formed by processing a part of a semiconductor substrate has been shown here, a semiconductor film having a convex shape may be formed by processing an SOI substrate.

[0308] The transistors 301, 302, and 303 may each be a p-channel type or an n-channel type, but it is preferable that the transistors 301 and 302 have opposite conductivity types.

[0309] The region where the channel of the semiconductor region 313 is formed, the region nearby, the low resistance region 314a which becomes the source region or the drain region, and the low resistance region 314b preferably contain a semiconductor such as a silicon-based semiconductor, and preferably contain single crystal silicon. Alternatively, they may be formed of a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be used. Alternatively, the transistors 301, 302, and 303 may be HEMTs (High Electron Mobility Transistors) by using GaAs and GaAlAs, or the like.

[0310] Low resistance region 314a and low resistance region 314b contain, in addition to the semiconductor material applied to semiconductor region 313, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0311] The insulator 315 functions as a gate insulating film for the transistor 301 , the transistor 302 , and the transistor 303 .

[0312] The conductor 316 functioning as the gate electrode can be made of a conductive material such as a semiconductor material, such as silicon, containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron, a metal material, an alloy material, or a metal oxide material.

[0313] Since the work function is determined by the material of the conductor, the threshold voltage can be adjusted by changing the material of the conductor. Specifically, it is preferable to use materials such as titanium nitride and tantalum nitride for the conductor. Furthermore, in order to achieve both electrical conductivity and embeddability, it is preferable to use metal materials such as tungsten and aluminum as a laminate for the conductor, and in particular, it is preferable to use tungsten in terms of heat resistance.

[0314] Moreover, an insulator 317 functioning as an etch stopper is preferably provided above the conductor 316. Moreover, an insulator 318 functioning as a spacer is preferably provided on the side of the insulator 315. By providing the insulators 317 and 318, the region where the low resistance region 314a and the low resistance region 314b are electrically connected to the conductor 328 can be determined in a self-aligned manner. Therefore, even if misalignment occurs when forming an opening for exposing a part of the low resistance region 314a and the low resistance region 314b, an opening for exposing an intended region can be formed. By forming the conductor 328 in the opening thus formed, a good contact with reduced contact resistance can be obtained between the low resistance region 314a and the conductor 328 and the low resistance region 314b. The contact between the low resistance region 314a and the low resistance region 314b formed in this manner and the conductor 328 may be called a self-aligned contact. A conductor 329 electrically connected to the conductor 316 may also be provided so as to be embedded in the insulator 317 and the insulator 322 .

[0315] An insulator 320, an insulator 322, an insulator 324, an insulator 326, and an insulator 327 are stacked in this order to cover the transistor 301, the transistor 302, and the transistor 303.

[0316] As the insulators 320, 322, 324, 326, and 327, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like can be used.

[0317] The insulator 322 may function as a planarizing film that planarizes steps caused by the transistor 301 provided therebelow. For example, the top surface of the insulator 322 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to improve the planarity.

[0318] In addition, the insulator 324 is preferably a film having a barrier property that prevents hydrogen or impurities from diffusing from the substrate 311 or the transistor 301 to a region where the memory array 220 is provided.

[0319] As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by a CVD method can be used. Here, hydrogen diffusion into a semiconductor element having an oxide semiconductor such as the memory element MC may deteriorate the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the memory element MC and the transistor 301 or the like. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0320] The amount of desorption of hydrogen can be analyzed, for example, by using thermal desorption spectrometry (TDS). For example, the amount of desorption of hydrogen from the insulator 324 is calculated as 10×10 per area of ​​the insulator 324 when the surface temperature of the film is in the range of 50° C. to 500° C. in the TDS analysis. 15 atoms / cm 2 Less than or equal to 5×10 15 atoms / cm 2 The following is acceptable.

[0321] Note that the insulators 326 and 327 preferably have a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulators 326 and 327 is preferably less than 4, and more preferably less than 3. For example, the relative dielectric constant of the insulators 326 and 327 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced.

[0322] Conductors 328, 329, and 330, which are electrically connected to the memory array 220, are embedded in the insulators 320, 322, 324, 326, and 327. The conductors 328, 329, and 330 function as plugs or wiring. A plurality of structures of conductors that function as plugs or wiring may be collectively given the same reference numeral. In this specification, the wiring and the plug that electrically connects to the wiring may be integrated. That is, a part of the conductor may function as the wiring, and a part of the conductor may function as the plug.

[0323] As the material for each plug and wiring (conductor 328, conductor 329, conductor 330, etc.), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used in a single layer or a laminated layer. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferable to form it from a low resistance conductive material such as aluminum or copper. By using a low resistance conductive material, it is possible to reduce the wiring resistance.

[0324] A wiring layer may be provided over the insulator 327 and the conductor 330. For example, in FIG. 39, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. A conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring. Note that the conductor 356 can be provided using a material similar to that of the conductors 328, 329, and 330.

[0325] Note that, for example, the insulator 350 is preferably an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 356 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 350 having a barrier property against hydrogen. With this structure, the transistor 301 and the like can be separated from the memory element MC by a barrier layer, and diffusion of hydrogen from the transistor 301 and the like to the memory element MC can be suppressed.

[0326] As a conductor having a barrier property against hydrogen, for example, tantalum nitride or the like may be used. By stacking tantalum nitride and tungsten having high conductivity, diffusion of hydrogen from the transistor 301 or the like can be suppressed while maintaining the conductivity as a wiring. In this case, a structure in which the tantalum nitride layer having a barrier property against hydrogen is in contact with the insulator 350 having a barrier property against hydrogen is preferable.

[0327] A wiring layer may be provided over the insulator 354 and the conductor 356. For example, in FIG. 39, an insulator 360, an insulator 362, and an insulator 364 are stacked in this order. A conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364. The conductor 366 functions as a plug or a wiring. The conductor 366 can be provided using a material similar to that of the conductors 328, 329, and 330.

[0328] Note that, for example, the insulator 360 is preferably an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 366 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 360 having a barrier property against hydrogen. With this structure, the transistor 301 and the like can be separated from the memory element MC by a barrier layer, and diffusion of hydrogen from the transistor 301 and the like to the memory element MC can be suppressed.

[0329] An insulator 722 is provided over the insulator 364 and the conductor 366, and the memory array 220 is provided above the insulator 722. A barrier film made of a material similar to that of the insulator 324 may be provided between the insulator 364 and the insulator 722.

[0330] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes.

[0331] (Embodiment 4) In this embodiment, an example of application of a semiconductor device according to one embodiment of the present invention to a data processing device will be described.

[0332] Generally, a computer has components such as a processor, main memory, and storage on a motherboard, and the components are electrically connected by, for example, bus wiring. Therefore, the longer the bus wiring, the higher the parasitic resistance becomes, and the higher the power consumption required for signal transmission becomes.

[0333] Specifically, a computer may have a configuration as shown in Fig. 40A, for example. The computer has a motherboard BD, on which are provided an arithmetic processing device (processor, CPU, etc.) 10, a main memory (DRAM (Dynamic Random Access Memory) etc.) 30, a storage (a three-dimensional structure NAND type storage device, a 3D OS NAND type storage device etc.) 40, an interface 60, etc. Note that Fig. 40A also shows SRAM (Static Random Access Memory) 20 which also functions as the main memory, but this does not necessarily have to be provided on the motherboard BD.

[0334] FIG. 40A illustrates a configuration in which the arithmetic processing device 10 has a register 11.

[0335] 40A, the arithmetic processing device 10 is electrically connected to the SRAM 20, the main memory 30, the storage 40, and the interface 60. The main memory 30 is also electrically connected to the SRAM 20 and the storage 40.

[0336] 40A is electrically connected to the components of the computer by bus wiring BSH. In other words, the more components of the computer are, or the larger the motherboard BD is, the longer the bus wiring BSH is, and the more power consumption is required to transmit signals.

[0337] Incidentally, the computer of Fig. 40A may be configured such that each component of the computer is integrated into one chip to form a monolithic IC (Integrated Circuit). In this case, the information processing device described in the above embodiment can be applied as the main memory 30 and the storage 40. Thus, the computer of Fig. 40A as a monolithic IC is shown in Fig. 40B.

[0338] 40B has a circuit layer LGC on a semiconductor substrate having Si. Also, a memory layer STR is provided on the circuit layer LGC, and a circuit layer OSC is provided on the memory layer STR.

[0339] The circuit layer LGC has, for example, a plurality of circuits including Si transistors formed on a semiconductor substrate SBT having Si. For example, a part of the plurality of circuits may be the arithmetic processing device 10, the SRAM 20, etc. in FIG. 40A. In addition, when the information processing device is applied as the main memory 30 and the storage 40, a part of the plurality of circuits may be a controller 1197 included in the information processing device 50 described later.

[0340] In particular, the SRAM 20 can increase the driving frequency of the SRAM by using Si transistors, for example.

[0341] The memory layer STR functions as a memory unit having a Si transistor and / or an OS transistor. The memory layer STR can be, for example, a three-dimensional NAND type memory circuit, a 3D OS NAND type memory circuit, etc. Therefore, the memory layer STR has a memory unit in an information processing device, a storage 40 in FIG. 40A, etc.

[0342] It should be noted that by using a 3D OS NAND type memory circuit, the power consumption of the monolithic IC in FIG. 40B can be reduced.

[0343] The circuit layer OSC includes, for example, a plurality of circuits including OS transistors. Some of the plurality of circuits may be circuits, such as the arithmetic processing device 10 and the SRAM 20, that are different from the circuits included in the circuit layer LGC.

[0344] In the monolithic IC of Figure 40B, since there is no bus wiring BSH for wiring on the motherboard, the wiring for electrically connecting each component is short, and therefore the power consumption required for signal transmission can be reduced.

[0345] Moreover, the monolithic IC in Fig. 40B has an information processing device 50. Therefore, the information processing device 50 functions as the storage 40 and the main memory 30 in Fig. 40A. Therefore, in the monolithic IC in Fig. 40B, the memory unit of the memory layer STR can have the function of the main memory 30.

[0346] Since the bus wiring BSH is not provided and a storage unit is used instead of the main memory 30, the monolithic IC in FIG. 40B can reduce the circuit area more than the computer in FIG. 40A.

[0347] Next, examples of memory hierarchies for the computer of FIG. 40A and the monolithic IC of FIG. 40B are shown in FIG. 41A and FIG. 41B, respectively.

[0348] In general, in the memory hierarchy, the higher the memory device is located, the faster the operating speed is required, and the lower the memory device is located, the larger the memory capacity and the higher the recording density are required. In Fig. 41A, as an example, a register included in the CPU (arithmetic processing device 10), an SRAM, a DRAM included in the main memory 30, and a three-dimensional structure NAND type memory circuit included in the storage 40 are shown in order from the top layer.

[0349] The registers and SRAM included in the arithmetic processing device 10 are used for temporarily storing arithmetic results, and are therefore frequently accessed by the arithmetic processing device 10. Therefore, a higher operating speed is required rather than a larger memory capacity. The registers also have the function of storing setting information for the arithmetic processing device.

[0350] The DRAM included in the main memory 30 has a function of holding programs and data read from the storage 40, for example. The recording density of the DRAM is approximately 0.1 Gbit / mm 2 ~0.3Gbit / mm 2 It is.

[0351] The storage 40 has a function of storing data that requires long-term storage and various programs used by the processor. Therefore, the storage 40 is required to have a large memory capacity and a high recording density rather than an operating speed. The recording density of the memory device used for the storage 40 is approximately 0.6 Gbit / mm 2 ~6.0Gbit / mm 2 For this reason, the storage 40 may be a three-dimensional NAND type memory circuit, a hard disk drive (HDD), or the like.

[0352] Incidentally, since the monolithic IC in FIG. 40B has the roles of the storage 40 and main memory 30 in FIG. 40A, the memory hierarchy of the monolithic IC in FIG. 40B is as shown in FIG. 41B.

[0353] That is, in the monolithic IC of Fig. 40B, the memory cells included in the storage unit of the information processing device 50 can be treated not only as the cache memory of the storage unit but also as the main memory 30 in the computer of Fig. 40A. Therefore, in the monolithic IC of Fig. 40B, there is no need to provide a main memory 30 such as a DRAM, so that the circuit area of ​​the monolithic IC of Fig. 40B can be reduced, and the power consumption required to operate the main memory 30 such as a DRAM can be reduced.

[0354] The configuration of the monolithic IC shown in Fig. 40B is an example and is not limited to one aspect of the present invention. The configuration of the monolithic IC shown in Fig. 40B may be changed depending on the situation. For example, in the monolithic IC of Fig. 40B, when a high-speed memory of 1 GHz or more is required as the SRAM, the SRAM may be integrated into the arithmetic processing device.

[0355] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0356] (Embodiment 5) In this embodiment, an example of a chip 1200, which is a type of semiconductor device on which a memory device of the present invention is mounted, is shown using Figures 42A and 42B. A plurality of circuits (systems) are mounted on the chip 1200. A technology for integrating a plurality of circuits (systems) on a single chip in this way is sometimes called a system on chip (SoC).

[0357] As shown in FIG. 42A, the chip 1200 includes a CPU 1211, a GPU 1212, one or more analog computing units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

[0358] Chip 1200 is provided with bumps (not shown) and is connected to a first surface of a printed circuit board (PCB) 1201 as shown in Fig. 42B. In addition, a plurality of bumps 1202 are provided on the back side of the first surface of PCB 1201 and are connected to a motherboard 1203.

[0359] The motherboard 1203 may be provided with a storage device such as a DRAM 1221 or a flash memory 1222. The semiconductor device described in the above embodiment is preferably used as the flash memory 1222. By using the semiconductor device described in the above embodiment for the flash memory 1222, the storage capacity of the flash memory 1222 can be increased.

[0360] The CPU 1211 preferably has a plurality of CPU cores. The GPU 1212 preferably has a plurality of GPU cores. The CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided in the chip 1200. The GPU 1212 is suitable for parallel calculation of a large amount of data, and can be used for image processing and multiplication and accumulation. By providing the GPU 1212 with an image processing circuit and a multiplication and accumulation circuit, it becomes possible to execute image processing and multiplication and accumulation with low power consumption.

[0361] In addition, by providing the CPU 1211 and GPU 1212 on the same chip, the wiring between the CPU 1211 and GPU 1212 can be shortened, and data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and GPU 1212, and transfer of calculation results from the GPU 1212 to the CPU 1211 after calculation in the GPU 1212 can be performed quickly.

[0362] The analog calculation unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. The analog calculation unit 1213 may also be provided with the above-mentioned product-sum calculation circuit.

[0363] The memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222 .

[0364] The interface 1215 has an interface circuit with externally connected devices such as a display device, a speaker, a microphone, a camera, and a controller. The controller includes a mouse, a keyboard, a game controller, etc. As such an interface, a USB (Universal Serial Bus), an HDMI (registered trademark) (High-Definition Multimedia Interface), etc. can be used.

[0365] The network circuit 1216 includes a network circuit for connecting to a LAN (Local Area Network), etc. It may also include a circuit for network security.

[0366] The above circuits (systems) can be formed in the same manufacturing process in the chip 1200. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.

[0367] A PCB 1201 on which a chip 1200 having a GPU 1212 is provided, a motherboard 1203 on which a DRAM 1221 and a flash memory 1222 are provided can be referred to as a GPU module 1204.

[0368] The GPU module 1204 has the chip 1200 using SoC technology, so that its size can be reduced. In addition, since it excels in image processing, it is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop PCs, and portable (portable) game consoles. In addition, a multiply-and-accumulate circuit using the GPU 1212 can execute techniques such as deep neural networks (DNN), convolutional neural networks (CNN), recurrent neural networks (RNN), autoencoders, deep Boltzmann machines (DBM), and deep belief networks (DBN), so that the chip 1200 can be used as an AI chip, and the GPU module 1204 can be used as an AI system module.

[0369] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes.

[0370] (Embodiment 6) In this embodiment, an application example of a semiconductor device using the storage device described in the previous embodiment will be described. The storage device described in the previous embodiment can be applied to various removable storage devices such as memory cards (e.g., SD cards), USB memories, and SSDs (solid state drives). Figures 43A to 43E show some configuration examples of removable storage devices. For example, the semiconductor device described in the previous embodiment is processed into a packaged memory chip and used in various storage devices and removable memories.

[0371] 43A is a schematic diagram of a USB memory. A USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a board 1104. The board 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the board 1104. The storage device or semiconductor device described in the above embodiments can be incorporated into the memory chip 1105 or the like.

[0372] FIG. 43B is a schematic diagram of the appearance of an SD card, and FIG. 43C is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. The capacity of the SD card 1110 can be increased by providing a memory chip 1114 on the back side of the substrate 1113 as well. In addition, a wireless chip having a wireless communication function may be provided on the substrate 1113. This makes it possible to read and write data from and to the memory chip 1114 by wireless communication between the host device and the SD card 1110. The memory chip 1114 or the like can be incorporated with the memory device or the semiconductor device described in the above embodiment.

[0373] FIG. 43D is a schematic diagram of the appearance of an SSD, and FIG. 43E is a schematic diagram of the internal structure of the SSD. The SSD 1150 has a housing 1151, a connector 1152, and a board 1153. The board 1153 is housed in the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are attached to the board 1153. The memory chip 1155 is a work memory for the controller chip 1156, and may be, for example, a DOSRAM chip. The capacity of the SSD 1150 can be increased by providing a memory chip 1154 on the back side of the board 1153. The memory chip 1154 or the like can be incorporated with the storage device or semiconductor device shown in the above embodiment.

[0374] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes.

[0375] (Embodiment 7) 44A to 44G illustrate specific examples of electronic devices equipped with a memory device or a semiconductor device according to one embodiment of the present invention.

[0376] <Electronic equipment and systems> The memory device or semiconductor device according to one embodiment of the present invention can be mounted on various electronic devices. Examples of the electronic devices include information terminals, computers, smartphones, e-book terminals, television devices, digital signage, large game machines such as pachinko machines, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, recording and playback devices, navigation systems, and audio playback devices. Note that the term "computer" as used herein includes tablet computers, notebook computers, desktop computers, and large computers such as server systems.

[0377] The electronic device of one embodiment of the present invention may have an antenna. By receiving a signal through the antenna, images, information, and the like can be displayed on a display portion. In addition, when the electronic device has an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0378] An electronic device according to one embodiment of the present invention may have a sensor (including a function of measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0379] The electronic device of one embodiment of the present invention can have various functions, such as a function of displaying various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, time, etc., a function of executing various software (programs), a wireless communication function, a function of reading out a program or data recorded in a recording medium, etc.

[0380] [Information terminal] A memory device for storing programs of a microcontroller can be formed using a memory device or a semiconductor device according to one embodiment of the present invention, and therefore, according to one embodiment of the present invention, a microcontroller chip can be made smaller.

[0381] FIG. 44A illustrates a mobile phone (smartphone), which is a type of information terminal. The information terminal 5100 includes a housing 5101 and a display unit 5102. As input interfaces, a touch panel is provided on the display unit 5102 and buttons are provided on the housing 5101. By using a miniaturized microcontroller according to one embodiment of the present invention, a limited space inside the mobile phone can be effectively used. In addition, a storage device according to one embodiment of the present invention may be used for storage of the mobile phone. This allows the storage capacity per unit area of ​​the storage to be increased.

[0382] FIG. 44B illustrates a notebook information terminal 5200. The notebook information terminal 5200 includes a main body 5201 of the information terminal, a display unit 5202, and a keyboard 5203. By using a miniaturized microcontroller according to one embodiment of the present invention, it is possible to effectively use a limited space inside the notebook information terminal. In addition, a storage device according to one embodiment of the present invention may be used for the storage of the notebook information terminal. This allows the storage capacity per unit area of ​​the storage to be increased.

[0383] In the above description, a smartphone and a notebook type information terminal are illustrated in Fig. 44A and Fig. 44B as examples of electronic devices, but information terminals other than smartphones and notebook type information terminals can also be applied. Examples of information terminals other than smartphones and notebook type information terminals include PDAs (Personal Digital Assistants), desktop type information terminals, and workstations.

[0384] [Game consoles] FIG. 44C illustrates a portable game machine 5300, which is an example of a game machine. The portable game machine 5300 includes a housing 5301, a housing 5302, a housing 5303, a display unit 5304, a connection unit 5305, an operation key 5306, and the like. The housing 5302 and the housing 5303 can be detached from the housing 5301. By attaching the connection unit 5305 of the housing 5301 to another housing (not shown), a video output to the display unit 5304 can be output to another video device (not shown). In this case, the housing 5302 and the housing 5303 can each function as an operation unit. This allows a plurality of players to play a game at the same time. A memory device or a semiconductor device according to one embodiment of the present invention can be incorporated into chips provided on the substrates of the housing 5301, the housing 5302, and the housing 5303.

[0385] 44D shows a stationary game machine 5400, which is an example of a game machine. A controller 5402 is connected to the stationary game machine 5400 wirelessly or via a wire.

[0386] A miniaturized microcontroller according to one embodiment of the present invention can be used effectively in a game machine such as a portable game machine 5300 or a stationary game machine 5400. A storage device or a semiconductor device according to one embodiment of the present invention can be used for storage of the portable game machine. This can increase the storage capacity per unit area of ​​the storage.

[0387] 44C and 44D show a portable game machine and a stationary game machine as examples of game machines, but game machines to which the microcontroller of one embodiment of the present invention is applied are not limited to these. Examples of game machines to which the microcontroller of one embodiment of the present invention is applied include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.

[0388] [Mainframe computers] A memory device or a semiconductor device according to one embodiment of the present invention can be applied to a large-scale computer.

[0389] 44E is a diagram showing a supercomputer 5500, which is an example of a large computer. FIG. 44F is a diagram showing a rack-mounted calculator 5502 included in the supercomputer 5500.

[0390] The supercomputer 5500 includes a rack 5501 and a plurality of rack-mounted computers 5502. The plurality of computers 5502 are stored in the rack 5501. The computer 5502 is provided with a plurality of boards 5504, and a microcontroller according to one embodiment of the present invention can be mounted on the board. By using the miniaturized microcontroller according to one embodiment of the present invention, the limited space of a large computer can be effectively utilized. In addition, a storage device or a semiconductor device according to one embodiment of the present invention may be used for the storage of the large computer. This allows the storage capacity per unit area of ​​the storage to be increased.

[0391] 44E and 44F show a supercomputer as an example of a large computer, but the large computer to which the microcontroller according to an embodiment of the present invention is applied is not limited to this. Examples of large computers to which the microcontroller according to an embodiment of the present invention is applied include computers that provide services (servers) and large general-purpose computers (mainframes).

[0392] [electric appliances] 44G shows an example of an electric appliance, an electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 has a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0393] A memory device or a semiconductor device according to one embodiment of the present invention can also be applied to an electric refrigerator-freezer 5800. For example, by applying a miniaturized microcontroller according to one embodiment of the present invention to the electric refrigerator-freezer 5800, the limited space of the electric refrigerator-freezer can be effectively utilized.

[0394] Although an electric refrigerator-freezer has been described as an example of an electrical appliance, other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water servers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0395] The electronic devices, functions, effects, and the like described in this embodiment mode can be appropriately combined with descriptions of other electronic devices.

[0396] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes. [Explanation of symbols]

[0397] 10: arithmetic processing unit, 11: register, 20: SRAM, 30: main memory, 40: storage, 50: information processing unit, 60: interface, 100: storage device, 105: area, 110: memory cell array, 120: memory string, 120A: memory string, 120B: memory string, 120C: memory string, 121: base, 122: conductor, 123: insulator, 123A: insulating film, 124: insulator, 124A: insulating film, 125: semiconductor, 125A: semiconductor film, 125B: semiconductor, 126: insulator, 126A: insulating film, 126B : insulator, 127: semiconductor, 127A: semiconductor film, 128: conductor, 128[1]: conductor, 128[2]: conductor, 128[3]: conductor, 128[4]: conductor, 128[5]: conductor, 128A: conductive film, 129: insulator, 129A: insulating film, 130: conductor, 130A: conductive film, 131: insulator, 131A: insulator, 132: insulator, 135: insulator, 135A: insulating film, 136: conductor, 136A: conductive film, 137: insulator, 137A: insulating film, 138: insulator, 138A: insulating film, 139: insulator, 140: mask, 140A: mask, 14 0B: mask, 141: opening, 142: region, 143: region, 150: insulator, 156: insulator, 161: conductor, 162: conductor, 163: conductor, 164: conductor, 165: conductor, 166: conductor, 171: conductor, 172: conductor, 173: conductor, 174: conductor, 175: conductor, 176: conductor, 181: insulator, 182: conductor, 183: conductor, 185: shaft, 200: semiconductor device, 210: driver circuit, 211: peripheral circuit, 212: control circuit, 215: peripheral circuit, 220: memory array, 221: row decoder, 222: column decoder 223: row driver, 224: column driver, 225: input circuit, 226: output circuit, 227: sense amplifier, 228: voltage generation circuit, 241: PSW (power switch), 242: PSW (power switch), 301: transistor, 302: transistor, 303: transistor, 311: substrate, 313: semiconductor region, 314a: low resistance region, 314b: low resistance region, 315: insulator, 316: conductor, 317: insulator, 318: insulator, 320: insulator, 322: insulator, 324: insulator, 326: insulator, 327: insulator, 328: conductor,329: conductor, 330: conductor, 350: insulator, 352: insulator, 354: insulator, 356: conductor, 360: insulator, 362: insulator, 364: insulator, 366: conductor, 705: conductor, 714: conductor, 715: conductor, 722: insulator, 726: insulator, 752: conductor, 1100: USB memory, 1101: housing, 1102: cap, 1103: USB connector, 1104: board, 1105: memory chip, 1106: controller chip, 1110: SD card, 1111: housing, 1112: connector, 1113: board, 1114: memory memory chip, 1115: controller chip, 1150: SSD, 1151: housing, 1152: connector, 1153: board, 1154: memory chip, 1155: memory chip, 1156: controller chip, 1197: controller, 1200: chip, 1201: PCB, 1202: bump, 1203: motherboard, 1204: GPU module, 1211: CPU, 1212: GPU, 1213: analogue calculation unit, 1214: memory controller, 1215: interface, 1216: network circuit, 1221: DRAM, 1222: flash memory, 4000: film forming apparatus, 4002: loading / unloading chamber, 4004: loading / unloading chamber, 4006: transfer chamber, 4008: film forming chamber, 4009: film forming chamber, 4010: film forming chamber, 4014: transfer arm, 4020: chamber, 4021: raw material supply unit, 4021a: raw material supply unit, 4021b: raw material supply unit, 4022a: high-speed valve, 4022b: high-speed valve, 4023: raw material inlet, 4023a: raw material inlet, 4023b: raw material inlet, 4024: raw material outlet, 4025: exhaust unit, 4026: substrate holder, 4027: heater, 4028: plasma generator, 4 029: coil, 4030: substrate, 4031: raw material supply unit, 4033: raw material inlet, 4100: plasma ALD device, 4111: plasma generation chamber, 4120: reaction chamber, 4123: raw material inlet, 4124: raw material outlet, 4126: substrate holder, 4128: plasma generation device, 4130: substrate, 4131: plasma, 4133: raw material inlet, 4200: plasma ALD device, 4213: electrode, 4214: shower head, 4215: power supply, 4217: capacitor, 4220: chamber, 4223: raw material inlet, 4224: raw material outlet, 4226: substrate holder,4230: substrate, 4231: plasma, 4300: plasma ALD device, 4313: electrode, 4314: shower head, 4315: power supply, 4317: capacitor, 4319: mesh, 4320: chamber, 4321: power supply, 4322: capacitor, 4323: raw material inlet, 4324: raw material outlet, 4326: substrate holder, 4330: substrate, 4331: plasma, 5100: information terminal, 5101: housing, 5102: display unit, 5200: notebook type information terminal, 5201: main body, 5202: display unit, 5203: keyboard, 5300: portable game machine, 5301 : Housing, 5302: Housing, 5303: Housing, 5304: Display, 5305: Connection, 5306: Operation keys, 5400: Stationary game machine, 5402: Controller, 5500: Supercomputer, 5501: Rack, 5502: Calculator, 5504: Board, 5800: Electric refrigerator-freezer, 5801: Housing, 5802: Refrigerator door, 5803: Freezer door, ADDR: Signal, BD: Motherboard, BG: Conductor, BL: Conductor, BSH: Bus wiring, BW: Signal, CE: Signal, CLK: Signal, Cs: Capacitance, Din: Data to be written, Dout: Data read out ta, GW: signal, GND: ground potential, LGC: circuit layer, MC: memory element, MC[1]: memory element, MC[2]: memory element, MC[3]: memory element, MC[4]: memory element, MC[5]: memory element, ND: node, ND[1]: node, ND[2]: node, ND[3]: node, ND[4]: node, ND[5]: node, OSC: circuit layer, PON1: signal, PON2: signal, RBL: conductor, RDA: signal, RSEL: conductor, RTr: transistor, RTr[1]: transistor, RTr[2]: transistor, RTr[3]: transistor, RTr[ 4]: transistor, RTr[5]: transistor, RWL: conductor, RWL[1]: conductor, RWL[2]: conductor, RWL[3]: conductor, RWL[4]: conductor, RWL[5]: conductor, SBT: semiconductor substrate, SEL: conductor, SG: conductor, STr1: transistor, STr2: transistor, STr3: transistor, STr4: transistor, STR: memory layer, T1: period, T2: period, T3: period, T4: period, T5: period, T6: period, T7: period, T8: period, T9: period, T10: period, T11: period, T12: period, T13: period,T14: Period, Tr: Transistor, VDD: High power supply potential, VHM: High power supply voltage, WAKE: Signal, WBL: Conductor, WDA: Signal, WSEL: Conductor, WTr: Transistor, WTr[1]: Transistor, WTr[2]: Transistor, WTr[3]: Transistor, WTr[4]: Transistor, WTr[5]: Transistor, WWL: Conductor, WWL[1]: Conductor, WWL[2]: Conductor, WWL[3]: Conductor, WWL[4]: Conductor, WWL[5]: Conductor,

Claims

[Claim 1] A first insulator; a first conductor having a first opening on the first insulator; a second insulator having a second opening over the first conductor; a second conductor having a third opening on the second insulator; a third insulator on the second conductor; and a semiconductor provided in the first opening to the third opening, forming the first insulator; forming the first conductor on the first insulator; forming the second insulator on the first conductor; forming a fourth insulator on the second insulator; forming the third insulator on the fourth insulator; forming the third opening in the fourth insulator; forming the second opening in the second insulator; forming the first opening in the first conductor; forming the semiconductor in the first opening to the third opening; removing the fourth insulator; A method for manufacturing a memory device, comprising forming the second conductor between the second insulator and the third insulator.

Images