Imaging device and electronic apparatus

Abstract

To provide an imaging device with an image processing function.SOLUTION: An imaging device with an additional function such as imaging processing can hold analog data acquired by an imaging operation in pixels and can take out data obtained by multiplying the analog data by an arbitrary weighting coefficient. The pixels can acquire differential data between light reception devices adjacent to each other and can obtain information of a luminance gradient. By taking the information into a neutral network, for example, it becomes possible to infer distance information. Also, since a massive amount of image data can be held in pixels in the state of analog data, efficient processing can be performed.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One aspect of the present invention relates to an imaging device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification etc. relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification include a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, a power storage device, a memory device, an imaging device, an operation method thereof, or a manufacturing method thereof.

[0003] Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one embodiment of a semiconductor device. Further, a memory device, a display device, an imaging device, and an electronic device may include a semiconductor device. [Background technology]

[0004] A technology for forming a transistor using an oxide semiconductor thin film formed over a substrate has attracted attention. For example, Patent Document 1 discloses an imaging device in which a transistor that includes an oxide semiconductor and has an extremely low off-state current is used in a pixel circuit.

[0005] Moreover, Patent Document 2 discloses a technique for adding a calculation function to an imaging device. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2011-119711 A [Patent Document 2] JP 2016-123087 A Summary of the Invention [Problem to be solved by the invention]

[0007] In imaging devices mounted on portable devices, etc., a function capable of acquiring high-resolution images has become common. In the next generation, imaging devices are required to be equipped with even more intelligent functions.

[0008] Image data (analog data) acquired by an imaging device is converted to digital data, and after being taken out, image processing is performed as necessary. If this processing can be performed within the imaging device, linking with external devices will be faster, improving user convenience. In addition, the load and power consumption of peripheral devices can be reduced. Furthermore, if complex data processing can be performed on analog data, the time required for data conversion can be shortened.

[0009] For example, distance information can be inferred by calculating the brightness gradient from the difference information of data between adjacent pixels and using the brightness gradient as data in a deep neural network (DNN) or the like. By performing the calculation of the difference data between pixels and part of the calculation of the DNN within the imaging device, high-speed inference with low power consumption is possible.

[0010] In addition, mobile information terminals such as smartphones can obtain information on the distance of an image of a subject and process the image (such as blurring the foreground and background of the subject). The distance information is obtained using parallax from multiple cameras. If distance information can be obtained by image processing, it is possible to reduce the number of cameras to one, thereby reducing manufacturing costs.

[0011] Therefore, one object of one embodiment of the present invention is to provide an imaging device capable of performing image processing. Another object is to provide an imaging device capable of acquiring distance information. Another object is to provide an imaging device capable of acquiring information on a luminance gradient between adjacent pixels. Another object is to provide an imaging device that functions as a part of a neural network. Another object is to provide an imaging device with low power consumption. Another object is to provide an imaging device with high reliability. Another object is to provide a novel imaging device or the like. Another object is to provide a method for driving the imaging device. Another object is to provide a novel semiconductor device or the like.

[0012] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract problems other than these from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0013] One aspect of the present invention relates to an imaging device having an image processing function.

[0014] One embodiment of the present invention is an imaging device that includes a pixel and a readout circuit, the pixel including a first light receiving circuit, a second light receiving circuit, an amplifier circuit, and an arithmetic circuit, the amplifier circuit being capable of outputting a potential corresponding to a difference between first data held in the first light receiving circuit and second data held in the second light receiving circuit to the arithmetic circuit, the arithmetic circuit having a first node and a second node, a first potential output by the amplifier circuit when the first data and the second data are set to the same value is written to the first node, a second potential output by the amplifier circuit when the first data and the second data are generated by photoelectric conversion is written to the second node, and a third potential can be added to each of the first node and the second node, and the readout circuit is capable of extracting a product of the second potential and the third potential by calculation using a current flowing in accordance with the potential of the first node and a current flowing in accordance with the potential of the second node.

[0015] The readout circuit has a current mirror circuit and a correlated double sampling circuit, and the current mirror circuit has a first transistor and a second transistor, and one of the source or drain and the gate of the first transistor can be electrically connected to a first node, and one of the source or drain of the second transistor can be electrically connected to a second node and the correlated double sampling circuit.

[0016] Another embodiment of the present invention includes a pixel and a readout circuit. The pixel includes a first light receiving circuit, a second light receiving circuit, an amplifier circuit, and an arithmetic circuit. The amplifier circuit includes a first input terminal and a second input terminal. The arithmetic circuit includes a first node, a second node, a first capacitor, a second capacitor, a first transistor, and a second transistor. One electrode of the first capacitor and a gate of the first transistor are electrically connected to the first node. One electrode of the second capacitor and a gate of the second transistor are electrically connected to the second node. The readout circuit is electrically connected to one of a source or a drain of the first transistor and one of a source or a drain of the second transistor. The first light receiving circuit is electrically connected to a first input terminal, the second light receiving circuit is electrically connected to a second input terminal, a first potential output by the amplifier circuit when the same potential is input to the first input terminal and the second input terminal is written to the first node, a second potential output by the amplifier circuit according to a difference between data generated by the first light receiving circuit and data generated by the second light receiving circuit is written to the second node, a third potential can be added to each of the first node and the second node via a first capacitor or a second capacitor, and the readout circuit is an imaging device capable of extracting the product of the second potential and the third potential by calculation using a current flowing through the first transistor and a current flowing through the second transistor.

[0017] The readout circuit has a current mirror circuit and a correlated double sampling circuit, and the current mirror circuit has a third transistor and a fourth transistor, and one of the source or drain and the gate of the third transistor can be electrically connected to one of the source or drain of the first transistor, and one of the source or drain of the fourth transistor can be electrically connected to one of the source or drain of the second transistor and the correlated double sampling circuit.

[0018] Each of the first photodetector circuit and the second photodetector circuit has a photoelectric conversion device, a fifth transistor, a sixth transistor, and a third capacitor, one electrode of the photoelectric conversion device is electrically connected to one of the source or drain of the fifth transistor, the other of the source or drain of the fifth transistor is electrically connected to one of the source or drain of the sixth transistor and one electrode of the third capacitor, the other of the source or drain of the sixth transistor in the first photodetector circuit is electrically connected to a first input terminal, and the other of the source or drain of the sixth transistor in the second photodetector circuit is electrically connected to a second input terminal.

[0019] The fifth transistor and the sixth transistor preferably have a metal oxide in a channel formation region, and the metal oxide preferably includes In, Zn, and M (M is one or more of Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, and Hf).

[0020] Each of the first light receiving circuit and the second light receiving circuit further includes a seventh transistor and an eighth transistor, and it is preferable that the gate of the seventh transistor is electrically connected to one electrode of the third capacitor and one of the source or drain of the seventh transistor is electrically connected to one of the source or drain of the eighth transistor.

[0021] The amplifier circuit has a 9th transistor, a 10th transistor, and an 11th transistor, and one of a source or a drain of the 9th transistor is electrically connected to one electrode of a third capacitor in the first light receiving circuit, the other of the source or the drain of the 9th transistor is electrically connected to a first input terminal, one of a source or a drain of the 10th transistor is electrically connected to one electrode of a third capacitor in the second light receiving circuit, the other of the source or the drain of the 10th transistor is electrically connected to a second input terminal, one of a source or a drain of the 11th transistor is electrically connected to the first input terminal, and the other of the source or the drain of the 11th transistor is electrically connected to the second input terminal.

[0022] The ninth to eleventh transistors each preferably have a metal oxide in a channel formation region, and the metal oxide preferably includes In, Zn, and M (M is one or more of Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, or Hf).

[0023] In the above, a plurality of pixels can be electrically connected to one readout circuit.

[0024] Another embodiment of the present invention is an electronic device that processes a part of an image based on an image captured by the imaging device and distance information of a subject in the image analyzed by the imaging device. Effect of the Invention

[0025] By using one embodiment of the present invention, an imaging device capable of performing image processing can be provided. An imaging device capable of acquiring distance information can be provided. An imaging device capable of acquiring luminance gradient information between adjacent pixels can be provided. An imaging device that functions as a part of a neural network can be provided. An imaging device with low power consumption can be provided. An imaging device with high reliability can be provided. A novel imaging device or the like can be provided. A method for driving the imaging device can be provided. A novel semiconductor device or the like can be provided. [Brief description of the drawings]

[0026] [Figure 1] FIG. 1 is a block diagram illustrating an imaging device. [Diagram 2] FIG. 2 is a diagram illustrating a pixel block 200 and a circuit 240. As shown in FIG. [Diagram 3] FIG. 3 is a diagram illustrating the pixel 100. [Figure 4] Fig. 4A is a diagram illustrating a light receiving circuit, and Fig. 4B is a diagram illustrating a differential amplifier circuit. [Diagram 5] 5A and 5B are diagrams for explaining a current source circuit. [Figure 6] FIG. 6 is a timing chart illustrating the operation of the pixel block 200. As shown in FIG. [Figure 7] 7A and 7B are diagrams illustrating the circuit 301 and the circuit 302. FIG. [Figure 8] FIG. 8 is a diagram illustrating a memory cell. [Figure 9] 9A and 9B are diagrams showing examples of the configuration of a neural network. [Figure 10] 10A to 10D are diagrams illustrating the configuration of a pixel of an imaging device. [Figure 11] 11A to 11C are diagrams illustrating the configuration of a photoelectric conversion device. [Figure 12] FIG. 12 is a cross-sectional view illustrating a pixel. [Figure 13] 13A to 13C are diagrams illustrating a Si transistor. [Figure 14] FIG. 14 is a cross-sectional view illustrating a pixel. [Figure 15] FIG. 15 is a cross-sectional view illustrating a pixel. [Figure 16] FIG. 16 is a cross-sectional view illustrating a pixel. [Figure 17] 17A to 17D illustrate OS transistors. [Figure 18] FIG. 18 is a cross-sectional view illustrating a pixel. [Figure 19] 19A to 19C are perspective views (cross-sectional views) illustrating a pixel. [Figure 20] 20A1 to 20A3 and 20B1 to 20B3 are perspective views of a package and a module that house an imaging device. [Figure 21] 21A to 21F are diagrams illustrating an electronic device. [Figure 22] FIG. 22 is a diagram illustrating an automobile. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that the form and details of the present invention can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention is not interpreted as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same reference numerals are used in common between different drawings for the same parts or parts having similar functions, and repeated explanations may be omitted. In addition, hatching of the same elements constituting the drawings may be omitted or changed as appropriate between different drawings.

[0028] In addition, even if a circuit diagram shows a single element, the element may be configured as a plurality of elements as long as there is no functional problem. For example, a plurality of transistors operating as a switch may be connected in series or parallel. A capacitor may also be divided and placed in multiple positions.

[0029] In addition, one conductor may have multiple functions such as wiring, an electrode, and a terminal, and in this specification, multiple names may be used for the same element. Even if elements are shown as being directly connected to each other on a circuit diagram, the elements may actually be connected to each other via one or more conductors, and in this specification, such a configuration is also included in the category of direct connection.

[0030] (Embodiment 1) In this embodiment, an imaging device which is one embodiment of the present invention will be described with reference to drawings.

[0031] One aspect of the present invention is an imaging device with additional functions such as image processing. The imaging device stores analog data (image data) acquired during imaging in pixels, and can extract data obtained by multiplying the analog data by an arbitrary weighting factor.

[0032] In addition, pixels can obtain differential data between adjacent light receiving devices, and can obtain brightness gradient information. By inputting this information into a neural network, distance information and other information can be inferred. In addition, pixels can store huge amounts of image data in the form of analog data, allowing for efficient processing.

[0033] Obtaining distance information from an image can support picking work by robots, automatic driving of mobile objects, distance measurement, etc. Also, while multiple cameras were used to obtain distance information in smartphones, distance information can be obtained with a single camera, which can reduce manufacturing costs.

[0034] <Imaging device> 1 is a block diagram illustrating an imaging device of one embodiment of the present invention. The imaging device includes a pixel array 300, a circuit 301, a circuit 302, a circuit 303, a circuit 304, and a circuit 305. Note that each of the circuits 301 to 305 is not limited to a single circuit configuration and may be configured by combining a plurality of circuits. Alternatively, any of a plurality of the above circuits may be integrated. Furthermore, a circuit other than the above may be connected.

[0035] The pixel array 300 has an imaging function and a calculation function. The circuit 301 has a calculation function. The circuit 302 has a calculation function or a data conversion function. The circuits 303 and 304 have a selection function. The circuit 305 has a function of supplying a potential for a product-sum calculation to the pixel. A shift register, a decoder, or the like can be used as the circuit having the selection function. Note that the circuits 301 and 302 may be provided externally.

[0036] The pixel array 300 includes a plurality of pixel blocks 200. The pixel block 200 includes a pixel array 210 and a circuit 220, as shown in FIG.

[0037] The pixel array 210 has a plurality of pixels 100 arranged in a matrix. Each pixel 100 is electrically connected to a wiring 151 and a wiring 152, and the wiring 151 and the wiring 152 are each electrically connected to a circuit 220.

[0038] The circuit 220 is a readout circuit, and includes a circuit 230 and a circuit 240. The circuit 230 is a current source circuit, and has a function of controlling the current flowing through the pixel array 210 and the circuit 240. The circuit 240 is a difference extraction circuit, and for example, a correlated double sampling circuit (CDS circuit) can be used.

[0039] It is preferable that the circuit 230, the circuit 240, and the pixel array 210 are formed so that two or more of them overlap each other. With this configuration, the area of ​​the pixel block 200 can be reduced, and the resolution can be increased. Note that the circuit 240 can also be provided outside the pixel block 200.

[0040] In FIG. 2, the number of pixels in the pixel array 210 is 3×3 as an example, but is not limited to this. For example, it may be 2×2, 4×4, etc. Alternatively, the number of pixels in the horizontal direction may be different from that in the vertical direction. Alternatively, a switch or the like may be provided between the pixel 100 and the wiring 151 and between the pixel 100 and the wiring 152, respectively, to make the number of pixels variable. Also, some pixels may be shared by adjacent pixel blocks 200. Also, an amplifier circuit or a gain adjustment circuit may be electrically connected to the wiring 151.

[0041] The pixel 100 can acquire image data, generate calculation data using the image data, generate data by adding the calculation data and a weighting factor, etc. The pixel block 200 configured as described above can be operated as a product-sum calculation circuit.

[0042] <Pixel circuit> 3 shows an example of a configuration of a pixel 100. The pixel 100 includes circuits 10a, 10b, a circuit 20, and a circuit 30.

[0043] The circuits 10a and 10b are light receiving circuits and have a function of generating imaging data by a photoelectric conversion device. The circuit 20 is a differential amplifier circuit and has a function of outputting a data potential amplified according to the difference between the data input from the circuits 10a and 10b. The circuit 30 is an arithmetic circuit and has a function of holding the data potential output from the circuit 20 and giving a weight (a potential equivalent to a weighting coefficient) to the data potential.

[0044] <Light receiving circuit> The circuits 10a and 10b may have a similar configuration and may include a photoelectric conversion device 101 (photoelectric conversion devices 101a and 101b), a transistor 102 (transistors 102a and 102b), a transistor 103 (transistors 103a and 103b), and a capacitor 106 (capacitors 106a and 106b).

[0045] One electrode of the photoelectric conversion device 101 is electrically connected to one of the source and the drain of the transistor 102. The other of the source and the drain of the transistor 102 is electrically connected to one of the source and the drain of the transistor 103 and one electrode of the capacitor 106.

[0046] The other electrode of the photoelectric conversion device 101 is electrically connected to a wiring 114. The other of the source and the drain of the transistor 103 is electrically connected to a wiring 115. The gate of the transistor 102 is electrically connected to a wiring 116. The gate of the transistor 103 is electrically connected to a wiring 117.

[0047] Here, an electrical connection point between the other of the source or the drain of the transistor 102, one of the source or the drain of the transistor 103, and one electrode of the capacitor 106 is defined as a node FD (node ​​FDa, node FDb).

[0048] The wirings 114 and 115 can function as power supply lines. For example, the wiring 114 can function as a high-potential power supply line, and the wiring 115 can function as a low-potential power supply line. The wirings 116 and 117 can function as signal lines that control the conduction of each transistor.

[0049] A photodiode can be used as the photoelectric conversion device 101. Any type of photodiode can be used, such as a Si photodiode having silicon in the photoelectric conversion layer, or an organic photodiode having an organic photoconductive film in the photoelectric conversion layer. Note that, when it is desired to increase the light detection sensitivity at low illuminance, it is preferable to use an avalanche photodiode.

[0050] The transistor 102 can have a function of controlling the potential of the node FD. The transistor 103 can have a function of initializing the potential of the node FD.

[0051] When an avalanche photodiode is used for the photoelectric conversion device 101, a high voltage may be applied, and therefore a high-voltage transistor is preferably used for the transistor connected to the photoelectric conversion device 101. For example, a transistor using a metal oxide in a channel formation region (hereinafter, referred to as an OS transistor) can be used for the high-voltage transistor. Specifically, an OS transistor is preferably used for the transistor 102.

[0052] In addition, the OS transistor has a characteristic of having an extremely low off-state current. By using OS transistors for the transistors 102 and 103, the period during which charge can be held in the node FD can be made extremely long. Therefore, a global shutter system in which charge is accumulated simultaneously in all pixels can be applied without complicating the circuit configuration and operation method. In addition, while image data is held in the node FD, multiple calculations can be performed using the image data.

[0053] On the other hand, when high-speed operation is required, it is preferable to use a transistor having high mobility in which silicon is used for a channel formation region (hereinafter, referred to as a Si transistor). Therefore, the transistors 102 and 103 may be Si transistors.

[0054] Note that the present invention is not limited to the above, and any combination of OS transistors and Si transistors may be used. Examples of Si transistors include transistors having amorphous silicon and transistors having crystalline silicon (microcrystalline silicon, low-temperature polysilicon, and single crystal silicon).

[0055] The above is just one example of the circuit configuration of the circuits 10a and 10b, and the photoelectric conversion operation can be performed with other circuit configurations.

[0056] Alternatively, the circuits 10a and 10b may have a configuration including a transistor 175 (transistors 175a and 175b) and a transistor 176 (transistors 176a and 176b) as shown in FIG. 4A.

[0057] A gate of the transistor 175 is electrically connected to the node FD. One of the source and the drain of the transistor 175 is electrically connected to the wiring 118, and the other of the source and the drain of the transistor 175 is electrically connected to the one of the source and the drain of the transistor 176. The other of the source and the drain of the transistor 176 is electrically connected to the wiring OUT. The wiring 118 can function as a power supply line and may be connected to the wiring 115.

[0058] The transistor 175 is an element of a source follower that outputs data according to the potential of the node FD. The transistor 176 functions as a selection transistor for selecting a light receiving circuit to be read out. Therefore, by using the circuits 10a and 10b having the configuration of FIG. 4A, image data can be read out from each light receiving circuit to the wiring OUT. In this configuration, image data can also be read out in parallel with the operation of the circuit 20.

[0059] <Differential amplifier circuit> The circuit 20 may include a transistor 104 (transistors 104a and 104b), a transistor 105 (transistors 105a and 105b), a transistor 107, a transistor 108, and a transistor 131 (transistors 131a and 131b).

[0060] One of the source or drain of the transistor 104a is electrically connected to the gate of the transistor 105a and one of the source or drain of the transistor 107. One of the source or drain of the transistor 104b is electrically connected to the gate of the transistor 105b and the other of the source or drain of the transistor 107. One of the source or drain of the transistor 105a is electrically connected to one of the source or drain and the gate of the transistor 131a. One of the source or drain of the transistor 105b is electrically connected to one of the source or drain and the gate of the transistor 131b. The other of the source or drain of the transistor 105a is electrically connected to the other of the source or drain of the transistor 105b and one of the source or drain of the transistor 108.

[0061] The other of the source and the drain of the transistor 131 is electrically connected to a wiring 124. The other of the source and the drain of the transistor 108 is electrically connected to a reference potential line or a low potential power supply line such as a GND wiring. The gate of the transistor 104a is electrically connected to a wiring 121. The gate of the transistor 104b is electrically connected to a wiring 122. The gate of the transistor 107 is electrically connected to a wiring 123.

[0062] The wiring 124 can function as, for example, a power supply line that supplies high potential power. The wirings 121, 122, and 123 can function as signal lines that control the conduction of each transistor.

[0063] The transistor 104 functions as a switch. The other of the source and the drain of the transistor 104a is electrically connected to a node FDa of the circuit 10a. The other of the source and the drain of the transistor 104b is electrically connected to a node FDb of the circuit 10b. Therefore, it can be said that the transistor 104 is an element of the circuits 10a and 10b.

[0064] The transistors 105 function as a differential transistor pair of a differential amplifier circuit. The gate of the transistor 105a functions as a first input terminal of the circuit 20. The gate of the transistor 105b functions as a second input terminal of the circuit 20. Therefore, data generated by the circuit 10a can be input to the first input terminal. Data generated by the circuit 10b can be input to the second input terminal.

[0065] The transistor 107 functions as a switch and can set the first input terminal and the second input terminal to the same potential. The switch can be used when acquiring reference data.

[0066] The transistor 108 functions as a current source, and an appropriate potential (Bias) is supplied to the gate of the transistor 108. Note that a resistor element may be used instead of the transistor 108.

[0067] The transistor 131 functions as a voltage conversion circuit. Note that although the transistor 131 is illustrated as a diode-connected p-channel transistor in FIG. 3, it may be a diode-connected n-channel transistor. Alternatively, a diode element, a resistor element, or a cascode circuit may be used instead of the transistor 131.

[0068] 3, a part of the wiring connecting one of the source or drain of the transistor 105b and one of the source or drain of the transistor 131b also functions as an output terminal, and is represented as a node N. A data potential amplified according to the difference between the output data of the circuit 10a and the output data of the circuit 10b can be output to the output terminal (node ​​N).

[0069] 4B, the circuit 20 may be configured without the transistors 104 and 107. The transistors 104 and 107 are provided to set the first input terminal and the second input terminal to the same potential. However, if the potential of the wiring 115 supplied from the transistor 103 (reset potential) is used as the same potential, the transistors 104 and 107 can be omitted.

[0070] <Arithmetic circuit> The circuit 30 may include a transistor 132 , a transistor 133 , a transistor 134 , a transistor 142 , a transistor 143 , a transistor 144 , a capacitor 135 , and a capacitor 145 .

[0071] One of the source or drain of the transistor 132 is electrically connected to one electrode of the capacitor 135 and the gate of the transistor 133. The other electrode of the capacitor 135 is electrically connected to one of the source or drain of the transistor 134. One of the source or drain of the transistor 142 is electrically connected to one electrode of the capacitor 145 and the gate of the transistor 143. The other electrode of the capacitor 145 is electrically connected to one of the source or drain of the transistor 144.

[0072] A gate of the transistor 132 is electrically connected to a wiring 125. A gate of the transistor 142 is electrically connected to a wiring 126. A gate of the transistor 134 and a gate of the transistor 144 are electrically connected to a wiring 127. The other of the source or drain of the transistor 132 and the other of the source or drain of the transistor 142 are electrically connected to a node N. The other of the source or drain of the transistor 134 and the other of the source or drain of the transistor 144 are electrically connected to a wiring 128.

[0073] One of a source and a drain of the transistor 133 is electrically connected to a wiring 151. One of a source and a drain of the transistor 143 is electrically connected to a wiring 152. The other of the source and the drain of the transistor 133 and the other of the source and the drain of the transistor 143 are electrically connected to a reference potential line or a low potential power supply line such as a GND wiring.

[0074] The wiring 125, the wiring 126, and the wiring 127 can function as signal lines that control the conduction of each transistor. The wiring 128 is, for example, a wiring that can supply a potential corresponding to a weighting coefficient (such as a filter for convolution processing) and is electrically connected to the circuit 305 (see FIG. 1). The wiring 151 is a wiring that is electrically connected to the circuit 230 and the circuit 240, and the wiring 152 is a wiring that is electrically connected to the circuit 230 (see FIG. 2).

[0075] Here, a point (wiring) where one of the source or drain of the transistor 132, one electrode of the capacitor 135, and the gate of the transistor 133 are connected is referred to as a node P1. Also, a point (wiring) where one of the source or drain of the transistor 142, one electrode of the capacitor 145, and the gate of the transistor 143 are connected is referred to as a node P2.

[0076] The nodes P1 and P2 can store data output by the circuit 20. The nodes P1 and P2 can be floating. Therefore, a potential (weighting coefficient) supplied from the wiring 128 can be applied to the data held in the nodes P1 and P2 by capacitive coupling of the capacitor 135 or the capacitor 145.

[0077] <Readout circuit> Next, a description will be given of the configuration of the read circuit 220. The read circuit 220 has a circuit 230 that functions as a current source circuit, and a circuit 240 that functions as a difference extraction circuit.

[0078] <Current source circuit> 5A。 Circuit 230 can supply a current in accordance with the data held in pixel 100. Circuit 230 can have a configuration shown in Fig. 5A.

[0079] 5A shows a configuration using n-ch transistors. The current supply unit 225 can have a configuration including transistors 222, 252, and transistors 223, 253.

[0080] One of the source and the drain of the transistor 222 is electrically connected to the signal line FG. The other of the source and the drain of the transistor 222 is electrically connected to the gate of the transistor 223. One of the source and the drain of the transistor 252 is electrically connected to the signal line FGREF. The other of the source and the drain of the transistor 252 is electrically connected to the gate of the transistor 253. The gate of the transistor 222 and the gate of the transistor 252 are electrically connected to the wiring 213.

[0081] One of the source and the drain of the transistor 223 is electrically connected to the wiring 151. One of the source and the drain of the transistor 253 is electrically connected to the wiring 152. The other of the source and the drain of the transistor 223 and the other of the source and the drain of the transistor 253 are electrically connected to a high potential power supply line (VDD).

[0082] In the current supply unit 225, an appropriate signal potential is supplied to the signal lines FG and FGREF, and by supplying a high potential ("H") to the wiring 213, the transistors 222, 252 and the transistors 223, 253 become conductive, and current can be supplied to the wiring 151 and the wiring 152.

[0083] The current mirror unit 226 can have a configuration including a transistor 254 and a transistor 224. The gate and one of the source and drain of the transistor 254 are electrically connected to the wiring 152. The one of the source and drain of the transistor 224 is electrically connected to the wiring 151. The other of the source or drain of the transistor 224 and the other of the source or drain of the transistor 254 are electrically connected to the low potential power line (VSS). The gate of the transistor 224 is electrically connected to the gate of the transistor 254, and the same current (ICM) as that of the transistor 254 can flow through the transistor 224.

[0084] 5B, the current supply unit 225 may be configured using p-ch transistors. The output side of the transistor 262 is electrically connected to the wiring 152 and the gate of the transistor 261.

[0085] <Difference extraction circuit> The circuit 240 is a difference extraction circuit, and can extract the product of the data and the weighting coefficient (product-sum operation result) using the currents flowing through the pixel 100 and the circuit 230. As shown in FIG. 2, the pixels 100 are electrically connected to each other by wiring 151. The circuit 240 can perform an operation using the sum of the currents flowing through the transistors 133 of the pixels 100.

[0086] The circuit 240 includes a capacitor 202, a transistor 203, a transistor 204, a transistor 205, a transistor 206, and a transistor 207 as a voltage conversion circuit. A suitable analog potential (Bias) is applied to the gate of the transistor 207.

[0087] One electrode of the capacitor 202 is electrically connected to one of the source or drain of the transistor 203 and the gate of the transistor 204. One of the source or drain of the transistor 204 is electrically connected to one of the source or drain of the transistor 205 and one of the source or drain of the transistor 206. The other electrode of the capacitor 202 is electrically connected to the wiring 151 and one of the source or drain of the transistor 207.

[0088] Here, a point where one electrode of the capacitor 202, one of the source or drain of the transistor 203, and the gate of the transistor 204 are connected is referred to as a node C.

[0089] The other of the source and the drain of the transistor 203 is electrically connected to a wiring 218. The other of the source and the drain of the transistor 204 is electrically connected to a wiring 219. The other of the source and the drain of the transistor 205 is electrically connected to a reference power supply line such as a GND wiring. The other of the source and the drain of the transistor 206 is electrically connected to a wiring 212. The other of the source and the drain of the transistor 207 is electrically connected to a reference power supply line such as a GND wiring. The gate of the transistor 203 is electrically connected to a wiring 216. The gate of the transistor 205 is electrically connected to a wiring 215. The gate of the transistor 206 is electrically connected to a wiring 214.

[0090] The wirings 218 and 219 can function as power supply lines. For example, the wiring 218 can function as a wiring that supplies a reset potential (Vr) for reading. The wiring 219 can function as a high-potential power supply line. The wirings 214, 215, and 216 can function as signal lines that control the conduction of each transistor. The wiring 212 is an output line and can be electrically connected to, for example, the circuit 301 shown in FIG. 1.

[0091] The transistor 203 can have a function of resetting the potential of the node C to the potential of the wiring 218. The transistors 204 and 205 can have a function as a source follower circuit. The transistor 206 can have a function of controlling reading. Note that the circuit 240 has a function as a correlated double sampling circuit (CDS circuit) and can be replaced with a circuit having the same function and having another configuration.

[0092] <Operation> Next, the operation of the imaging device according to one embodiment of the present invention will be described. In one embodiment of the present invention, first, data (reference data) when there is no difference between the outputs of the circuits 10a and 10b is obtained in the pixel 100. Next, image data is obtained by photoelectric conversion in each of the circuits 10a and 10b, and difference data therebetween is obtained.

[0093] Next, circuit 240 extracts a differential potential between data obtained by converting the current flowing from circuit 230 to circuit 240 into a voltage based on the reference data and the difference data, and data obtained by converting the current flowing from circuit 230 to circuit 240 when weights are applied to the reference data and the difference data.

[0094] The differential potential corresponds to data obtained by removing various offset components from the current passed by the circuit 220, and is data obtained by converting the current expressed in terms of the product of the differential data and the weighting coefficient into a voltage. In other words, the product of the differential data and the weighting coefficient can be extracted.

[0095] In order to explain the overall flow of extracting the product of the differential data and the weighting coefficient, explanation of the operation of pixel 100 will be omitted here, and the explanation will be given assuming that node P1 stores a data potential X equivalent to the differential data (the difference between the data obtained by photoelectric conversion) between circuits 10a and 10b, and node P2 stores a data potential (reference data, ideally 0) output by circuit 20 when there is no difference between the outputs of circuits 10a and 10b. The detailed operation of pixel 100 will be described later.

[0096] In the pixel block 200, it is possible to remove offset components other than the product of the difference data (potential X) and the weighting coefficient (potential W) and extract the target WX. The flow of WX extraction when the circuit shown in FIG. 5A is used as the circuit 230 is as follows.

[0097] First, in the circuit 240, the transistor 203 is turned on, and a potential Vr is written from the wiring 218 to the node C. Here, the potential Vr is a reset potential used in a read operation.

[0098] At this time, it is assumed that difference data (potential X) is written to node P1 of the circuit 30 of the pixel 100. It is also assumed that reference data 0 is written to node P2. It is also assumed that the weighting coefficient written from the wiring 128 is 0.

[0099] At this time, the total current flowing from the circuit 230 to the transistor 133 of each pixel 100 is kΣ(XV th ) 2 The total current flowing from the circuit 230 to the transistor 143 of each pixel 100 is kΣ(0-V th ) 2 Here, k is a constant, V th is the threshold voltage of each transistor.

[0100] In the circuit 230, the total current flowing through the transistor 223 is IC, the total current flowing through the transistor 253 is ICFEF, and the current flowing through the transistor 224 and the transistor 254 is ICM (see FIG. 5A).

[0101] In this case, ICREF0 (ICREF when weight is 0) = ICM0 + kΣ(0-V th ) 2 Therefore, ICM0=ICREF0-kΣ(0-V th ) 2 It becomes.

[0102] Here, the current IR0 (IR when the weight is 0) flowing through the transistor 207 of the circuit 240 is IR0=IC-ICM0-kΣ(XVth ) 2 That is, IR0 = IC-ICREF0 + kΣ(0-V th ) 2 -kΣ(XV th ) 2 It becomes.

[0103] Then, the transistor 203 of the circuit 240 is turned off, and the potential Vr is held at the node C.

[0104] Next, a potential corresponding to the weighting factor (W) is supplied to the wiring 128, and the weighting factor (W) is applied to the nodes P1 and P2 by capacitive coupling.

[0105] At this time, the total current flowing from the circuit 230 to the transistor 133 of each pixel 100 is kΣ(X+WV th ) 2 The total current flowing from the circuit 230 to the transistor 143 of each pixel 100 is kΣ(WV th ) 2 It becomes.

[0106] Therefore, the current I flowing through the transistor 207 of the circuit 240 is I = I - I - k Σ (X + W th ) 2 That is, IR=IC-ICREF+kΣ(WV th ) 2 -kΣ(X+WV th ) 2 It becomes.

[0107] Here, the difference between IR0 and IR is IR0-IR=kΣ(Vth 2 -(X-Vth) 2 -(W-Vth) 2 +(W+X-Vth) 2 ) = kΣ(2WX). In other words, the offset component is removed, and the term consisting of WX can be extracted.

[0108] The above difference can be extracted by circuit 240. IR0 is initialized as the potential Vr of node C, and since the potential of wiring 151 changes from a weighting factor 0 state to a weighting factor W state while node C is floating, the potential difference Y (corresponding to the difference between IR0 and IR) is added to node C by the capacitive coupling of capacitor 202. Here, node C becomes Vr+Y, and if we consider the potential Vr=0, Y is the potential itself obtained by voltage-converting the difference between IR0 and IR. In other words, WX can be extracted.

[0109] Next, the operation of the pixel 100 and the operation of the pixel block 200 will be described with reference to the timing chart shown in Fig. 6. The pixel 100 described here has the configuration shown in Fig. 3. It is also assumed that a predetermined potential is supplied to the power supply line, etc.

[0110] <Operation of pixel 100> At time T1, when the potential of wiring 116 is set to "H", the potential of wiring 117 is set to "H", the potential of wiring 121 is set to "H", the potential of wiring 122 is set to "H", and the potential of wiring 123 is set to "L", in circuits 10a and 10b, transistors 102 and 103 are turned on, and the potentials of nodes FDa and FDb become reset potentials (the potential of wiring 115).

[0111] At time T2, when the potential of the wiring 116 is set to "L", the potential of the wiring 117 is set to "L", the potential of the wiring 121 is set to "L", the potential of the wiring 122 is set to "L", and the potential of the wiring 123 is set to "L", the transistors 102, 103, and 104 become non-conductive, and the reset potentials are held at the nodes FDa and FDb. Also, in the photoelectric conversion device 101, an accumulation operation is started.

[0112] At time T3, when the potential of the wiring 116 is set to "H", the potential of the wiring 122 is set to "H", and the potential of the wiring 123 is set to "H", the transistor 102 becomes conductive, and the charge accumulated in the photoelectric conversion device 101 is transferred to the nodes FDa and FDb. After that, the potential of the wiring 116 is set to "L", and the potentials of the nodes FDa and FDb are held.

[0113] Furthermore, the transistor 104b and the transistor 107 are turned on, and the potential of the node FDb is input to the first input terminal (the gate of the transistor 105a) and the second input terminal (the gate of the transistor 105b) of the circuit 20.

[0114] At this time, a data potential amplified according to the difference between the data input to the first input terminal and the data input to the second input terminal is output to the output terminal (node ​​N) of the circuit 20. Here, the data potential output to the output terminal (node ​​N) of the circuit 20 can be called reference data. The reference data is data that is output when there is no difference between the data input to the first input terminal and the data input to the second input terminal.

[0115] When the configuration of FIG. 4B is used for the circuit 20, the reference data may be output when the nodes FDa and FDb are set to the reset potential.

[0116] At time T4, when the potential of the wiring 126 is set to "H", the potential of the output terminal (node ​​N) of the circuit 20 is written to the node P2 of the circuit 30. Thereafter, the potential of the wiring 126 is set to "L" and the potential of the node P2 is maintained. Note that before time T4, the potential of the wiring 127 is set to "H" and the potential of the other electrodes of the capacitors 135 and 145 is set to the potential of the wiring 128 (for example, 0).

[0117] At time T5, when the potential of the wiring 121 is set to "H", the potential of the wiring 122 is set to "H", and the potential of the wiring 123 is set to "L", the transistor 104a is turned on, the transistor 107 is turned off, and the potential of the node FDa is written to the first input terminal of the circuit 20. Note that the potential of the node FDb is written to the second input terminal of the circuit 20.

[0118] Therefore, a data potential amplified according to the difference between node FDa and node FDb is output to the output terminal (node ​​N) of circuit 20. Here, the data potential output to the output terminal (node ​​N) of circuit 20 is a potential amplified according to the difference between the image data acquired by circuit 10a and the image data acquired by circuit 10b, and can be called differential data. Alternatively, it can be called image data or imaging data.

[0119] At time T6, when the potential of the wiring 125 is set to "H", the potential of the output terminal (node ​​N) of the circuit 20 is written to the node P1 of the circuit 30. After that, the potential of the wiring 125 is set to "L" to hold the potential of the node P1.

[0120] At time T7, when the potential of the wiring 121 is set to "L", the potential of the wiring 122 is set to "L", and the potential of the wiring 127 is set to "L", the transistors 104, 134, and 144 are turned off, and a series of operations of the circuits 10a, 10b, and 20 is completed.

[0121] <Operations of Circuit 220 and Circuit 230> Furthermore, when the potential of the wiring 213 is set to "H" at time T7, an appropriate bias is supplied to the gates of the transistors 222 and 252 in the circuit 230, and a current IC flows through the transistor 223 and a current ICREF flows through the transistor 253 (see FIG. 5A). Then, the potential of the wiring 213 is set to "L".

[0122] Here, ICREF is the sum of the current (ICM) flowing through transistor 254 and the current flowing through transistor 143 of circuit 30. In addition, current IC is the sum of the current (ICM) flowing through transistor 224, the current flowing through transistor 133 of circuit 30, and the current flowing through transistor 207 of circuit 240.

[0123] When the potential of the wiring 151 is determined in the above state, the potential of the wiring 216 is set to "H", and the potential of the wiring 218, "Vr", is written to the node C. Then, the potential of the wiring 216 is set to "L", and the node C is made floating to hold the potential "Vr".

[0124] At time T8, the potential of the wiring 127 is set to "H", the transistors 134 and 144 are turned on, and a potential W corresponding to the weighting coefficient is supplied to the wiring 128. The potential W is applied by capacitive coupling to the potentials held at the nodes P1 and P2 of the circuit 30. At this time, the state of the weighting coefficient changes from 0 to W, and the current flowing through the transistor 207 of the circuit 230 changes.

[0125] At this time, the change "Y" in the potential of the wiring 151 is added to the node C by the capacitive coupling of the capacitor 202. Here, the potential of the node C becomes "Vr+Y", and if we consider the potential "Vr"=0, the potential of the node C becomes the potential "Y" obtained by voltage conversion of the difference in the current flowing through the transistor 207. That is, WX can be extracted according to the current equation described above.

[0126] At time T9, when the potential of the wiring 214 is set to "H" and an appropriate bias is supplied to the wiring 215, the circuit 240 can output a signal potential corresponding to WX to the wiring 212 by a source follower operation.

[0127] At time T10, the potential of the wiring 127 is set to "L", the potential of the wiring 213 is set to "L", the potential of the wiring 214 is set to "L", and the potential of the wiring 215 is set to "L", completing the read operation.

[0128] WX output from the circuit 240 by the above operation can be input to the circuit 301.

[0129] In the above example, simultaneous data is written to node P1 and node P2, and data corresponding to the data is extracted. However, there may be a time difference between the data in node P1 and node P2. For example, by writing a first frame of data to node P1 and a second frame of data to node P2, information including motion parallax can be extracted. Depth (distance) information can be obtained from motion parallax, and a stereoscopic image can be constructed.

[0130] <Circuits 301, 302> 7A is a diagram for explaining circuits 301 and 302 connected to circuit 240. Data resulting from product-sum operations output from circuit 240 is sequentially input to circuit 301. Circuit 301 may have various arithmetic functions. Alternatively, the functions of circuit 301 may be replaced by software processing.

[0131] For example, the circuit 301 can have a circuit that performs an activation function calculation. For example, a comparator circuit can be used for the circuit. The comparator circuit compares input data with a set threshold value and outputs the result as binary data. That is, the pixel block 200 and the circuit 301 can act as a part of a neural network.

[0132] The circuit 301 may also have an A / D converter. When outputting image data to the outside without performing a multiply-and-accumulate operation, the circuit 301 can convert analog data into digital data. For example, the circuits 10a and 10b shown in FIG. 4A can be electrically connected to the circuit 301 through a wiring OUT.

[0133] Furthermore, the data output by the pixel block 200 corresponds to multi-bit image data, but if the circuit 301 can binarize the data, it can be said that the image data is compressed.

[0134] Data output from the circuit 301 is input sequentially to the circuit 302. The circuit 302 can have a configuration including, for example, a latch circuit and a shift register. This configuration enables parallel-serial conversion to be performed, and data input in parallel can be output as serial data to the wiring 311. There is no limitation on the connection destination of the wiring 311. For example, the wiring 311 can be connected to a neural network, a storage device, a communication device, or the like.

[0135] As shown in Fig. 7B, the circuit 302 may have a neural network. The neural network has memory cells arranged in a matrix, and each memory cell holds a weighting factor. Data output from the circuit 301 is input to each of the memory cells 320, and a multiply-and-accumulate operation can be performed. Note that the number of memory cells shown in Fig. 7B is an example and is not limited.

[0136] The neural network shown in FIG. 7B includes memory cells 320 and reference memory cells 325 arranged in a matrix, a circuit 330, a circuit 350, a circuit 360, and a circuit 370.

[0137] 8 shows an example of a memory cell 320 and a reference memory cell 325. The reference memory cell 325 is provided in an arbitrary column. The memory cell 320 and the reference memory cell 325 have the same configuration, and include a transistor 161, a transistor 162, and a capacitor 163.

[0138] One of the source or drain of the transistor 161 is electrically connected to the gate of the transistor 162. The gate of the transistor 162 is electrically connected to one electrode of the capacitor 163. Here, a point where one of the source or drain of the transistor 161, the gate of the transistor 162, and one electrode of the capacitor 163 are connected is referred to as a node NM.

[0139] A gate of the transistor 161 is electrically connected to the wiring WL. The other electrode of the capacitor 163 is electrically connected to the wiring RW. One of the source and the drain of the transistor 162 is electrically connected to a reference potential wiring such as a GND wiring.

[0140] In the memory cell 320, the other of the source and the drain of the transistor 161 is electrically connected to a wiring WD. The other of the source and the drain of the transistor 162 is electrically connected to a wiring BL.

[0141] In the reference memory cell 325, the other of the source and the drain of the transistor 161 is electrically connected to a wiring WDref. The other of the source and the drain of the transistor 162 is electrically connected to a wiring BLref.

[0142] The wiring WL is electrically connected to the circuit 330. The circuit 330 can be a decoder, a shift register, or the like.

[0143] The wiring RW is electrically connected to the circuit 301. Binary data output from the circuit 301 is written to each memory cell. Note that a sequential circuit such as a shift register may be provided between the circuit 301 and each memory cell.

[0144] The wiring WD and the wiring WDref are electrically connected to the circuit 350. The circuit 350 can be a decoder, a shift register, or the like. The circuit 350 may also include a D / A converter and an SRAM. The circuit 350 can output the weighting coefficient to be written to the node NM.

[0145] The wiring BL and the wiring BLref are electrically connected to the circuit 360. The circuit 360 can have a structure similar to that of the circuit 240. By using the circuit 360, a signal from which an offset component has been removed from the product-sum operation result can be obtained.

[0146] The circuit 360 is electrically connected to the circuit 370. The circuit 370 can also be called an activation function circuit. The activation function circuit has a function of performing an operation for converting a signal input from the circuit 360 according to a predefined activation function. As the activation function, for example, a sigmoid function, a tanh function, a softmax function, a ReLU function, a threshold function, or the like can be used. The signal converted by the activation function circuit is output to the outside as output data.

[0147] As shown in FIG. 9A, the neural network NN can be composed of an input layer IL, an output layer OL, and an intermediate layer (hidden layer) HL. The input layer IL, the output layer OL, and the intermediate layer HL each have one or more neurons (units). The intermediate layer HL may be one layer or two or more layers. A neural network having two or more intermediate layers HL can also be called a DNN (deep neural network). Learning using a deep neural network can also be called deep learning.

[0148] Input data is input to each neuron in the input layer IL. An output signal from a neuron in the previous or next layer is input to each neuron in the hidden layer HL. An output signal from a neuron in the previous layer is input to each neuron in the output layer OL. Each neuron may be connected to all neurons in the previous or next layer (full connection), or may be connected to only a portion of the neurons.

[0149] FIG. 9B shows an example of a computation by a neuron. Here, neuron N and two neurons in the previous layer that output signals to neuron N are shown. Neuron N receives the output x1 of a neuron in the previous layer and the output x2 of a neuron in the previous layer. Neuron N then calculates the sum x1w1+x2w2 of the multiplication result (x1w1) of the output x1 and the weight w1 and the multiplication result (x2w2) of the output x2 and the weight w2, and then adds a bias b as necessary to obtain a value a=x1w1+x2w2+b. The value a is then transformed by the activation function h, and neuron N outputs an output signal y=ah.

[0150] In this way, the computation by a neuron includes the sum of the output of the previous layer neuron and the weight, that is, the sum of products (x1w1+x2w2 above). This sum of products may be performed by software using a program, or by hardware.

[0151] In one embodiment of the present invention, a multiply-and-accumulate circuit is used as hardware. When an analog circuit is used for the multiply-and-accumulate circuit, the circuit scale of the multiply-and-accumulate circuit can be reduced, or the number of accesses to a memory can be reduced, leading to improved processing speed and reduced power consumption.

[0152] The product-sum circuit preferably includes an OS transistor. Since an OS transistor has an extremely small off-state current, it is suitable as a transistor constituting an analog memory of the product-sum circuit. Note that the product-sum circuit may be configured using both a Si transistor and an OS transistor.

[0153] This embodiment mode can be appropriately combined with the descriptions of other embodiment modes.

[0154] (Embodiment 2) In this embodiment, a structural example of an imaging device according to one embodiment of the present invention will be described.

[0155] <Structure example> FIG. 10A is a diagram showing an example of the structure of a pixel of an imaging device, which can have a stacked structure of a layer 561 and a layer 563.

[0156] The layer 561 includes the photoelectric conversion device 101. The photoelectric conversion device 101 can include a layer 565a and a layer 565b as shown in Fig. 11A. Note that, in some cases, the layer may be referred to as a region.

[0157] 11A is a pn junction photodiode, and may use, for example, a p-type semiconductor for the layer 565a and an n-type semiconductor for the layer 565b. Alternatively, the layer 565a may be an n-type semiconductor, and the layer 565b may be a p-type semiconductor.

[0158] The pn junction photodiode can be typically formed using single crystal silicon. A photodiode using single crystal silicon as a photoelectric conversion layer has a relatively wide spectral sensitivity characteristic from ultraviolet light to near infrared light, and can detect light of various wavelengths by combining it with an optical conversion layer described later.

[0159] Alternatively, a compound semiconductor may be used as the photoelectric conversion layer of a pn junction photodiode. Examples of the compound semiconductor include gallium arsenic phosphide (GaAsP), gallium phosphide (GaP), indium gallium arsenide (InGaAs), lead sulfur compound (PbS), lead selenium compound (PbSe), indium arsenide compound (InAs), indium antimony compound (InSb), and mercury cadmium telluride compound (HgCdTe).

[0160] The compound semiconductor is preferably a compound semiconductor having a Group 13 element (aluminum, gallium, indium, etc.) and a Group 15 element (nitrogen, phosphorus, arsenic, antimony, etc.) (also called a Group 3-5 compound semiconductor), or a compound semiconductor having a Group 12 element (magnesium, zinc, cadmium, mercury, etc.) and a Group 16 element (oxygen, sulfur, selenium, tellurium, etc.) (also called a Group 2-6 compound semiconductor).

[0161] Compound semiconductors allow the band gap to be changed depending on the combination of constituent elements and their atomic ratios, making it possible to form photodiodes that are sensitive to a wide range of wavelengths, from ultraviolet light to infrared light.

[0162] In addition, the wavelength of ultraviolet light can be generally defined as being around 0.01 μm to around 0.38 μm, the wavelength of visible light as being around 0.38 μm to around 0.75 μm, the wavelength of near-infrared light as being around 0.75 μm to around 2.5 μm, the wavelength of mid-infrared light as being around 2.5 μm to around 4 μm, and the wavelength of far-infrared light as being around 4 μm to around 1000 μm.

[0163] For example, to form a photodiode having photosensitivity from ultraviolet light to visible light, GaP or the like can be used for the photoelectric conversion layer. To form a photodiode having photosensitivity from ultraviolet light to near infrared light, the above-mentioned silicon or GaAsP or the like can be used for the photoelectric conversion layer. To form a photodiode having photosensitivity from visible light to mid-infrared light, InGaAs or the like can be used for the photoelectric conversion layer. To form a photodiode having photosensitivity from near infrared light to mid-infrared light, PbS or InAs or the like can be used for the photoelectric conversion layer. To form a photodiode having photosensitivity from mid-infrared light to far-infrared light, PbSe, InSb, HgCdTe or the like can be used for the photoelectric conversion layer.

[0164] The photodiode using the compound semiconductor may have a pin junction instead of a pn junction. The pn junction and the pin junction are not limited to a homojunction structure, and may have a heterojunction structure.

[0165] For example, in a heterojunction, a first compound semiconductor can be used in one layer of a pn junction structure, and a second compound semiconductor different from the first compound semiconductor can be used in the other layer. Also, a first compound semiconductor can be used in one or two layers of a pin junction structure, and a second compound semiconductor different from the first compound semiconductor can be used in the remaining layers. Either the first compound semiconductor or the second compound semiconductor can be a simple semiconductor such as silicon.

[0166] The photoelectric conversion layer of the photodiode may be formed using a different material for each pixel. By using this configuration, an imaging device having two or three types of pixels, such as a pixel that detects ultraviolet light, a pixel that detects visible light, and a pixel that detects infrared light, can be formed.

[0167] Furthermore, the photoelectric conversion device 101 included in the layer 561 may be a laminate of layers 566a, 566b, 566c, and 566d, as shown in Fig. 11B. The photoelectric conversion device 101 shown in Fig. 11B is an example of an avalanche photodiode, in which the layers 566a and 566d correspond to electrodes, and the layers 566b and 566c correspond to a photoelectric conversion unit.

[0168] Layer 566a is preferably a low resistance metal layer, such as aluminum, titanium, tungsten, tantalum, silver, or a laminate of these.

[0169] The layer 566d is preferably a conductive layer having a high light-transmitting property to visible light. For example, indium oxide, tin oxide, zinc oxide, indium-tin oxide, gallium-zinc oxide, indium-gallium-zinc oxide, graphene, or the like can be used. Note that the layer 566d may be omitted.

[0170] The layers 566b and 566c of the photoelectric conversion unit can be configured as a pn junction photodiode with a photoelectric conversion layer made of, for example, a selenium-based material. It is preferable that the layer 566b is made of a selenium-based material that is a p-type semiconductor, and the layer 566c is made of gallium oxide or the like that is an n-type semiconductor.

[0171] Photoelectric conversion devices using selenium-based materials have the characteristic of high external quantum efficiency for visible light. In such photoelectric conversion devices, avalanche multiplication can be used to increase the amplification of electrons relative to the amount of incident light. In addition, selenium-based materials have a high optical absorption coefficient, which offers the advantage of production in that the photoelectric conversion layer can be made as a thin film. Thin films of selenium-based materials can be formed using vacuum deposition or sputtering methods.

[0172] As selenium-based materials, crystalline selenium (single crystal selenium, polycrystalline selenium) and amorphous selenium can be used. These have photosensitivity from ultraviolet light to visible light. In addition, compounds of copper, indium, and selenium (CIS) or compounds of copper, indium, gallium, and selenium (CIGS) can be used. These have photosensitivity from ultraviolet light to near infrared light.

[0173] The n-type semiconductor is preferably made of a material that has a wide band gap and is transparent to visible light. For example, zinc oxide, gallium oxide, indium oxide, tin oxide, or a mixture of these oxides can be used. These materials also function as a hole injection blocking layer, and can reduce dark current.

[0174] Furthermore, the photoelectric conversion device 101 included in the layer 561 may be a laminate of layers 567a, 567b, 567c, 567d, and 567e, as shown in Fig. 11C. The photoelectric conversion device 101 shown in Fig. 11C is an example of an organic photoconductive film, in which the layer 567a is a lower electrode, the layer 567e is a light-transmitting upper electrode, and the layers 567b, 567c, and 567d correspond to photoelectric conversion units.

[0175] One of the layers 567b and 567d of the photoelectric conversion portion can be a hole transport layer, and the other can be an electron transport layer. The layer 567c can be a photoelectric conversion layer.

[0176] For the hole transport layer, for example, molybdenum oxide can be used. For the electron transport layer, for example, C60 , C 70 or derivatives thereof can be used.

[0177] The photoelectric conversion layer can be a mixed layer (bulk heterojunction structure) of n-type organic semiconductor and p-type organic semiconductor. There are various types of organic semiconductors, and a material that has photosensitivity to the desired wavelength can be selected for the photoelectric conversion layer.

[0178] For example, a silicon substrate can be used as the layer 563 shown in FIG. 10A. The silicon substrate has Si transistors and the like. In addition to pixel circuits, the Si transistors can be used to form circuits for driving the pixel circuits, image signal readout circuits, image processing circuits, neural networks, communication circuits, and the like. In addition, memory circuits such as DRAMs (Dynamic Random Access Memory), CPUs (Central Processing Units), MCUs (Micro Controller Units), and the like may be formed. In this embodiment, the above circuits excluding the pixel circuits are called functional circuits.

[0179] For example, some or all of the transistors included in the pixel circuit (pixel 100) and the functional circuits (circuits 220, 301, 302, 303, 304, 305, and the like) described in Embodiment 1 can be provided in the layer 563.

[0180] Also, the layer 563 may be a laminate of multiple layers as shown in FIG. 10B. Although three layers, 563a, 563b, and 563c, are illustrated in FIG. 10B, two layers may be used. Alternatively, the layer 563 may be a laminate of four or more layers. These layers can be laminated using, for example, a bonding process. With this configuration, the pixel circuits and the functional circuits can be distributed among multiple layers and the pixel circuits and the functional circuits can be stacked, so that a small-sized, highly functional imaging device can be manufactured.

[0181] Alternatively, the pixel may have a stacked structure of a layer 561, a layer 562, and a layer 563 as shown in FIG. 10C.

[0182] The layer 562 can include an OS transistor. One or more of the functional circuits described above may be formed using an OS transistor. Alternatively, one or more of the functional circuits may be formed using a Si transistor included in the layer 563 and an OS transistor included in the layer 562. Alternatively, the layer 563 may be used as a supporting substrate such as a glass substrate, and a functional circuit may be formed using the OS transistor included in the layer 562.

[0183] For example, a normally-off CPU (also referred to as an Noff-CPU) can be realized by using OS transistors and Si transistors. Note that an Noff-CPU is an integrated circuit including normally-off transistors that are in a non-conducting state (also referred to as an off state) even when the gate voltage is 0 V.

[0184] The Noff-CPU can stop the power supply to circuits in the Noff-CPU that are not required to operate, and put the circuits into a standby state. When the power supply is stopped and the circuits are in a standby state, no power is consumed. Thus, the Noff-CPU can minimize power consumption. The Noff-CPU can also retain information necessary for operation, such as setting conditions, for a long period of time even if the power supply is stopped. To return from the standby state, it is only necessary to resume the power supply to the circuit, and there is no need to rewrite the setting conditions, etc. In other words, high-speed return from the standby state is possible. In this way, the Noff-CPU can reduce power consumption without significantly reducing the operating speed.

[0185] Also, layer 562 may be a laminate of multiple layers as shown in Fig. 10D. Although two layers, layers 562a and 563b, are illustrated in Fig. 10D, layer 562 may be a laminate of three or more layers. These layers may be formed by stacking them on layer 563, for example. Alternatively, layer 562 may be formed by bonding a layer formed on layer 563 and a layer formed on layer 561.

[0186] As a semiconductor material used for an OS transistor, a metal oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more can be used. A typical example is an oxide semiconductor containing indium, for example, CAAC-OS or CAC-OS described later can be used. CAAC-OS has stable atoms constituting the crystal, and is suitable for transistors that emphasize reliability. In addition, CAC-OS has high mobility characteristics, and is suitable for transistors that operate at high speed.

[0187] OS transistors have a large energy gap in the semiconductor layer, and therefore exhibit extremely low off-current characteristics of a few yA / μm (current value per 1 μm of channel width). OS transistors also have characteristics different from Si transistors, such as the absence of impact ionization, avalanche breakdown, and short channel effects, and can form highly reliable circuits with high voltage resistance. OS transistors are also less susceptible to variations in electrical characteristics caused by non-uniformity in crystallinity, which is a problem with Si transistors.

[0188] The semiconductor layer of the OS transistor can be, for example, a film represented by an In-M-Zn oxide containing indium, zinc, and M (one or more selected from metals such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, and hafnium). The In-M-Zn oxide can be typically formed by a sputtering method. Alternatively, it may be formed by an ALD (atomic layer deposition) method.

[0189] The atomic ratio of the metal elements of the sputtering target used to form the In-M-Zn oxide by the sputtering method preferably satisfies In≧M and Zn≧M. The atomic ratio of the metal elements of such a sputtering target is preferably In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, etc. The atomic ratio of the semiconductor layer to be formed includes a variation of ±40% of the atomic ratio of the metal elements contained in the above sputtering target.

[0190] The semiconductor layer is made of an oxide semiconductor with a low carrier density. For example, the semiconductor layer has a carrier density of 1×10 17 / cm 3 Less than or equal to 1×10 15 / cm 3 Less than 1×10, more preferably 13 / cm 3 Less than or equal to 1×10 11 / cm 3 Less than 1×10, more preferably 10 / cm 3 Less than 1 x 10 -9 / cm 3 An oxide semiconductor having a carrier density of 1000 or more can be used. Such an oxide semiconductor is called a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. The oxide semiconductor has a low density of defect states and is stable in characteristics.

[0191] Note that the composition is not limited to these, and an appropriate composition may be used depending on the required semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, etc.) of the transistor. In order to obtain the required semiconductor characteristics of the transistor, it is preferable to appropriately set the carrier density, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic distance, density, and the like of the semiconductor layer.

[0192] When silicon or carbon, which is one of the group 14 elements, is contained in the oxide semiconductor constituting the semiconductor layer, oxygen vacancies increase and the semiconductor layer becomes n-type. For this reason, the concentration of silicon or carbon in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is set to 2×10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0193] In addition, when an alkali metal or an alkaline earth metal is bonded to an oxide semiconductor, carriers may be generated, which may increase the off-state current of a transistor. For this reason, the concentration of an alkali metal or an alkaline earth metal in a semiconductor layer (concentration obtained by secondary ion mass spectrometry) is set to 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 To the following:

[0194] In addition, when nitrogen is contained in the oxide semiconductor constituting the semiconductor layer, electrons that act as carriers are generated, which increases the carrier density and makes the semiconductor layer more likely to be n-type. As a result, a transistor using an oxide semiconductor that contains nitrogen is likely to have normally-on characteristics. For this reason, the nitrogen concentration in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is 5×10 18 atoms / cm 3 It is preferable to do the following:

[0195] Furthermore, when hydrogen is contained in an oxide semiconductor constituting a semiconductor layer, it reacts with oxygen bonded to a metal atom to form water, which may form oxygen vacancies in the oxide semiconductor. When oxygen vacancies are present in a channel formation region in an oxide semiconductor, the transistor may have normally-on characteristics. Furthermore, defects in which hydrogen has entered the oxygen vacancies may function as donors and generate electrons that serve as carriers. In addition, some of the hydrogen may bond with oxygen that is bonded to a metal atom to generate electrons that serve as carriers. Therefore, a transistor using an oxide semiconductor that contains a large amount of hydrogen is likely to have normally-on characteristics.

[0196] A defect in which hydrogen has entered an oxygen vacancy can function as a donor for an oxide semiconductor. However, it is difficult to quantitatively evaluate the defect. Thus, an oxide semiconductor may be evaluated by its carrier concentration instead of its donor concentration. Thus, in this specification and the like, a carrier concentration assuming a state in which no electric field is applied may be used as a parameter of an oxide semiconductor instead of the donor concentration. In other words, the "carrier concentration" described in this specification and the like may be rephrased as the "donor concentration".

[0197] Therefore, it is preferable that hydrogen in the oxide semiconductor be reduced as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor measured by secondary ion mass spectrometry (SIMS) is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5×10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 When an oxide semiconductor in which impurities such as hydrogen are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0198] The semiconductor layer may have a non-single crystal structure. The non-single crystal structure includes, for example, a C-Axis Aligned Crystalline Oxide Semiconductor (CAAC-OS) having crystals oriented along the c-axis, a polycrystalline structure, a microcrystalline structure, or an amorphous structure. Among the non-single crystal structures, the amorphous structure has the highest density of defect states, and the CAAC-OS has the lowest density of defect states.

[0199] An oxide semiconductor film having an amorphous structure has, for example, a disordered atomic arrangement and does not include a crystalline component, or an oxide film having an amorphous structure has, for example, a completely amorphous structure and does not include a crystalline portion.

[0200] The semiconductor layer may be a mixed film having two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. The mixed film may have a single layer structure or a multilayer structure including two or more of the above-mentioned regions.

[0201] The following describes the structure of a cloud-aligned composite (CAC)-OS, which is one type of non-single crystal semiconductor layer.

[0202] CAC-OS is, for example, a material in which elements constituting an oxide semiconductor are unevenly distributed with a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or thereabouts. Note that, hereinafter, a state in which one or more metal elements are unevenly distributed in an oxide semiconductor and regions containing the metal elements are mixed with a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or thereabouts, is also referred to as a mosaic or patch shape.

[0203] The oxide semiconductor preferably contains at least indium, particularly indium and zinc, and may further contain one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like.

[0204] For example, the CAC-OS in In-Ga-Zn oxide (In-Ga-Zn oxide among CAC-OS may be specifically referred to as CAC-IGZO) is an indium oxide (hereinafter, InO X1 (X1 is a real number greater than 0).) or indium zinc oxide (hereinafter, In X2 Zinc Y2 O Z2 (X2, Y2, and Z2 are real numbers greater than 0.) and gallium oxide (GaO X3 (X3 is a real number greater than 0). ) or gallium zinc oxide (Ga X4 Zinc Y4 O Z4 (X4, Y4, and Z4 are real numbers greater than 0).) The material is separated into a mosaic shape, and the mosaic shape of InO X1 , or In X2 Zinc Y2 O Z2 However, the structure is such that the particles are uniformly distributed in the film (hereinafter, also referred to as a cloud-like structure).

[0205] In other words, CAC-OS is X3 The region where In is the main component and X2 Zinc Y2 O Z2 , or InO X1 In this specification, for example, when the atomic ratio of In to element M in the first region is greater than the atomic ratio of In to element M in the second region, the first region is said to have a higher In concentration than the second region.

[0206] IGZO is a common name and may refer to a compound made of In, Ga, Zn, and O. A typical example is InGaO3(ZnO). m1 (m1 is a natural number), or In (1+x0) Ga (1-x0) O3(ZnO) m0 (-1≦x0≦1, m0 is an arbitrary number).

[0207] The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure, where multiple IGZO nanocrystals have a c-axis orientation and are connected without being oriented in the ab plane.

[0208] On the other hand, CAC-OS is a material composition of oxide semiconductor. CAC-OS is a material composition containing In, Ga, Zn, and O, in which some regions observed as nanoparticles mainly composed of Ga and some regions observed as nanoparticles mainly composed of In are randomly distributed in a mosaic pattern. Therefore, in CAC-OS, the crystal structure is a secondary element.

[0209] Note that the CAC-OS does not include a laminated structure of two or more films with different compositions, such as a two-layer structure consisting of a film mainly containing In and a film mainly containing Ga.

[0210] In addition, GaO X3 The region where In is the main component and X2 Zinc Y2 O Z2 , or InO X1 In some cases, it may be difficult to observe a clear boundary between the region in which the main component is the

[0211] In addition, when one or more elements selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. are contained instead of gallium, the CAC-OS has a configuration in which some regions observed to be in the form of nanoparticles mainly composed of the metal element and some regions observed to be in the form of nanoparticles mainly composed of In are randomly dispersed in a mosaic pattern.

[0212] CAC-OS can be formed, for example, by a sputtering method under conditions where the substrate is not intentionally heated. When CAC-OS is formed by a sputtering method, any one or more selected from an inert gas (typically argon), oxygen gas, and nitrogen gas may be used as a deposition gas. The lower the flow rate ratio of oxygen gas to the total flow rate of deposition gas during deposition, the more preferable it is, for example, 0% or more and less than 30%, preferably 0% or more and 10% or less.

[0213] CAC-OS has the characteristic that no clear peaks are observed when it is measured using the θ / 2θ scan by the out-of-plane method, which is one of the X-ray diffraction (XRD) measurement methods. In other words, the X-ray diffraction measurement shows that there is no orientation in the ab plane direction or the c axis direction in the measurement area.

[0214] In addition, in the electron beam diffraction pattern obtained by irradiating CAC-OS with an electron beam (also called nano-beam electron beam) with a probe diameter of 1 nm, a ring-shaped region of high brightness (ring region) and multiple bright spots are observed in the ring region. Therefore, the electron beam diffraction pattern shows that the crystal structure of CAC-OS has an nc (nano-crystal) structure that does not have orientation in the planar direction and cross-sectional direction.

[0215] For example, in the case of CAC-OS of In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) revealed that GaO X3 The region where In is the main component and X2 Zinc Y2 O Z2 , or InO X1 It can be seen that the region in which the main component is the crystalline silicon is unevenly distributed and mixed.

[0216] CAC-OS has a different structure from IGZO compounds in which metal elements are uniformly distributed, and has different properties from IGZO compounds. X3 The main components are In X2 Zinc Y2 O Z2 , or InO X1 The structure is such that the regions having each element as the main component are separated from each other in a mosaic pattern.

[0217] Here, In X2 Zinc Y2 O Z2 , or InO X1 The area where GaO is the main component X3 This region has a higher electrical conductivity than the region where In is the main component. X2 Zinc Y2 O Z2 , or InO X1 When carriers flow through the region where In is the main component, the conductivity of the oxide semiconductor is expressed. X2 Zinc Y2 O Z2 , or InO X1 When the region mainly composed of is distributed in a cloud shape in the oxide semiconductor, high field-effect mobility (μ) can be achieved.

[0218] On the other hand, GaO X3 The region where the main components are In X2 Zinc Y2 O Z2 , or InOX1 This region has higher insulating properties than the region where GaO is the main component. X3 When a region containing these as main components is distributed in an oxide semiconductor, leakage current can be suppressed and favorable switching operation can be achieved.

[0219] Therefore, when CAC-OS is used in a semiconductor device, GaO X3 Insulation caused by X2 Zinc Y2 O Z2 , or InO X1 The conductivity caused by the MOSFET and the MOSFET's resistance to the MOSFET's resistance work in a complementary manner, resulting in a high on-state current (I on ), and high field-effect mobility (μ).

[0220] In addition, semiconductor elements using CAC-OS have high reliability, making CAC-OS suitable as a constituent material for various semiconductor devices.

[0221] <Laminated structure 1> Next, the laminated structure of the imaging device will be described using a cross-sectional view. Note that the elements such as the insulating layer and the conductive layer shown below are examples, and other elements may be further included. Alternatively, some of the elements shown below may be omitted. Also, the laminated structure shown below can be formed using a bonding process, a polishing process, etc., as necessary.

[0222] FIG. 12 is an example of a cross-sectional view of a laminate having layers 560, 561, and a layer 563, with a bonding surface between layers 563a and 563b that constitute layer 563.

[0223] <layer 563b> The layer 563b can have a functional circuit provided on the silicon substrate 611. Here, the transistor 105, the transistor 108, and the transistor 131 included in the circuit 20 are shown as part of the functional circuit.

[0224] The layer 563b includes a silicon substrate 611 and insulating layers 612, 613, 614, 616, 617, and 618. The insulating layer 612 functions as a protective film. The insulating layers 613, 613, 616, and 617 function as an interlayer insulating film and a planarizing film. The insulating layer 618 and a conductive layer 619 function as bonding layers. The conductive layer 619 is electrically connected to the gate of the transistor 105.

[0225] The protective film may be, for example, a silicon nitride film, a silicon oxide film, or an aluminum oxide film. The interlayer insulating film and the planarizing film may be, for example, an inorganic insulating film such as a silicon oxide film, or an organic insulating film such as an acrylic resin or a polyimide resin. The dielectric layer of the capacitor may be, for example, a silicon nitride film, a silicon oxide film, or an aluminum oxide film. The lamination layer will be described later.

[0226] The conductor that can be used as wiring, electrodes, and plugs for electrical connection between devices may be a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal elements as components, or an alloy combining the above-mentioned metal elements, etc. The conductor is not limited to a single layer, and may be multiple layers composed of different materials.

[0227] <Layer 563a> The layer 563a includes elements of the pixel 100. It may also include elements of a functional circuit. Here, the transistor 102 is shown as one of the elements of the pixel 100. Also, the transistor 104 included in the circuit 20 is shown as an element of the functional circuit.

[0228] The layer 563a is provided with a silicon substrate 632, insulating layers 631, 633, 634, 635, 637, and 638, and conductive layers 636 and 639.

[0229] The insulating layer 631 and the conductive layer 639 function as bonding layers. The insulating layers 634, 635, and 637 function as an interlayer insulating film and a planarizing film. The insulating layer 633 functions as a protective film. The insulating layer 638 functions to insulate the silicon substrate 632 and the conductive layer 639. The insulating layer 638 can be formed of the same material as the other insulating layers. The insulating layer 638 may be formed of the same material as the insulating layer 631.

[0230] The conductive layer 639 is electrically connected to the other of the source and the drain of the transistor 105 and the conductive layer 619. In addition, the conductive layer 636 is electrically connected to the wiring 114 (see FIG. 3).

[0231] The Si transistor shown in Fig. 12 is a fin type having a channel formation region in a silicon substrate (silicon substrates 611 and 632). A cross section in the channel width direction (a cross section of A1-A2 shown in layer 563a in Fig. 12) is shown in Fig. 13A. The Si transistor may be a planar type as shown in Fig. 13B.

[0232] 13C, it may be a transistor having a silicon thin-film semiconductor layer 545. The semiconductor layer 545 may be, for example, single crystal silicon (SOI (Silicon on Insulator)) formed on an insulating layer 546 on a silicon substrate 611.

[0233] <layer 561> The layer 561 has a photoelectric conversion device 101. The photoelectric conversion device 101 can be formed on the layer 563a. Fig. 12 shows a configuration in which the organic photoconductive film shown in Fig. 11C is used as the photoelectric conversion layer for the photoelectric conversion device 101. Here, the layer 567a is a cathode, and the layer 567e is an anode.

[0234] Layer 561 is provided with insulating layers 651, 652, 653, 654 and a conductive layer 655.

[0235] The insulating layers 651, 653, and 654 function as an interlayer insulating film and a planarizing film. The insulating layer 654 is provided to cover the end of the photoelectric conversion device 101, and also functions to prevent a short circuit between the layer 567e and the layer 567a. The insulating layer 652 functions as an element isolation layer. It is preferable to use an organic insulating film or the like as the element isolation layer.

[0236] The layer 567a corresponding to the cathode of the photoelectric conversion device 101 is electrically connected to one of the source and drain of the transistor 102 included in the layer 563a. The layer 567e corresponding to the anode of the photoelectric conversion device 101 is electrically connected to the conductive layer 636 included in the layer 563a through the conductive layer 655.

[0237] <layer 560> The layer 560 is formed on the layer 561. The layer 560 includes a light-shielding layer 671, an optical conversion layer 672, and a microlens array 673.

[0238] The light-shielding layer 671 can suppress the inflow of light into adjacent pixels. A metal layer such as aluminum or tungsten can be used for the light-shielding layer 671. In addition, the metal layer and a dielectric film having a function as an anti-reflection film may be laminated.

[0239] When the photoelectric conversion device 101 has sensitivity to visible light, a color filter can be used for the optical conversion layer 672. A color image can be obtained by assigning colors such as (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta) to the color filters for each pixel. For example, as shown in the perspective view (including the cross section) of FIG. 19A, a color filter 672R (red), a color filter 672G (green), and a color filter 672B (blue) can be assigned to different pixels.

[0240] Furthermore, in a suitable combination of the photoelectric conversion device 101 and the optical conversion layer 672, by using a wavelength cut filter in the optical conversion layer 672, an imaging device capable of obtaining images in various wavelength regions can be obtained.

[0241] For example, an infrared imaging device can be formed by using an infrared filter that blocks light with wavelengths equal to or shorter than visible light in the optical conversion layer 672. A far-infrared imaging device can be formed by using a filter that blocks light with wavelengths equal to or shorter than near-infrared light in the optical conversion layer 672. An ultraviolet imaging device can be formed by using an ultraviolet filter that blocks light with wavelengths equal to or longer than visible light in the optical conversion layer 672.

[0242] In addition, a plurality of different optical conversion layers may be arranged in one imaging device. For example, as shown in FIG. 19B, a color filter 672R (red), a color filter 672G (green), a color filter 672B (blue), and an infrared filter 672IR can be assigned to different pixels. In this configuration, a visible light image and an infrared light image can be acquired simultaneously.

[0243] 19C, color filter 672R (red), color filter 672G (green), color filter 672B (blue), and ultraviolet filter 672UV can be assigned to different pixels. In this configuration, a visible light image and an ultraviolet light image can be acquired simultaneously.

[0244] Furthermore, if a scintillator is used for the optical conversion layer 672, an imaging device can be provided that obtains an image that visualizes the intensity of radiation used in an X-ray imaging device or the like. When radiation such as X-rays that has passed through a subject is incident on the scintillator, it is converted into light (fluorescence) such as visible light or ultraviolet light by the photoluminescence phenomenon. Then, image data is obtained by detecting the light with the photoelectric conversion device 101. An imaging device having such a configuration may also be used for a radiation detector or the like.

[0245] The scintillator contains a substance that absorbs the energy of radiation such as X-rays or gamma rays and emits visible or ultraviolet light when irradiated with the radiation. For example, Gd2O2S:Tb, Gd2O2S:Pr, Gd2O2S:Eu, BaFCl:Eu, NaI, CsI, CaF2, BaF2, CeF3, LiF, LiI, ZnO, etc., dispersed in resin or ceramics can be used.

[0246] By imaging with infrared or ultraviolet light, it is possible to provide the imaging device with an inspection function, a security function, a sensor function, etc. For example, by imaging with infrared light, it is possible to perform non-destructive inspection of produce, sorting of agricultural products (such as a sugar content meter function), vein authentication, medical testing, etc. Furthermore, by imaging with ultraviolet light, it is possible to detect ultraviolet light emitted from a light source or flame, and it is possible to manage light sources, heat sources, production equipment, etc.

[0247] A microlens array 673 is provided on the optical conversion layer 672. Light passing through each lens of the microlens array 673 passes through the optical conversion layer 672 directly below, and is irradiated onto the photoelectric conversion device 101. By providing the microlens array 673, concentrated light can be incident on the photoelectric conversion device 101, so that photoelectric conversion can be performed efficiently. The microlens array 673 is preferably formed of a resin or glass that is highly translucent to light of the target wavelength.

[0248] <Lamination> Next, the bonding of the layer 563b and the layer 563a will be described.

[0249] The layer 563b is provided with an insulating layer 618 and a conductive layer 619. The conductive layer 619 has a region buried in the insulating layer 618. The surfaces of the insulating layer 618 and the conductive layer 619 are flattened so that they are at the same height.

[0250] The layer 563a is provided with an insulating layer 631 and a conductive layer 639. The conductive layer 639 has a region buried in the insulating layer 631. The surfaces of the insulating layer 631 and the conductive layer 639 are flattened so that they are at the same height.

[0251] Here, the conductive layer 619 and the conductive layer 639 preferably contain the same metal element as a main component. The insulating layer 618 and the insulating layer 631 preferably contain the same component.

[0252] For example, Cu, Al, Sn, Zn, W, Ag, Pt, or Au can be used for the conductive layers 619 and 639. Cu, Al, W, or Au is preferably used because of ease of bonding. Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, titanium nitride, or the like can be used for the insulating layers 618 and 631.

[0253] That is, the same metal material as described above is preferably used for the conductive layer 619 and the conductive layer 639. The same insulating material as described above is preferably used for the insulating layer 618 and the insulating layer 631. With this structure, the layer 563b and the layer 563a can be bonded to each other at a boundary between them.

[0254] The conductive layers 619 and 639 may have a multi-layer structure with multiple layers, in which case the surface layers (joint surfaces) may be made of the same metal material. The insulating layers 618 and 631 may also have a multi-layer structure with multiple layers, in which case the surface layers (joint surfaces) may be made of the same insulating material.

[0255] This bonding makes it possible to obtain electrical connection between the conductive layer 619 and the conductive layer 639. Also, it makes it possible to obtain a connection between the insulating layer 618 and the insulating layer 631 that has sufficient mechanical strength.

[0256] To bond metal layers together, a surface activation bonding method can be used, in which oxide films and adsorbed layers of impurities on the surfaces are removed by sputtering or other methods, and cleaned and activated surfaces are brought into contact with each other to bond them. Alternatively, a diffusion bonding method can be used, in which surfaces are bonded together using a combination of temperature and pressure. Both methods involve bonding at the atomic level, resulting in excellent bonding not only electrically but also mechanically.

[0257] In addition, for bonding insulating layers, a hydrophilic bonding method can be used in which high flatness is achieved by polishing, etc., and then the surfaces that have been hydrophilically treated with oxygen plasma or the like are brought into contact with each other to form a temporary bond, and then the final bond is achieved by dehydrating them through heat treatment. Hydrophilic bonding also produces bonds at the atomic level, and therefore can provide mechanically excellent bonds.

[0258] When bonding the layer 563b and the layer 563a, an insulating layer and a metal layer are mixed on each bonding surface, so that, for example, a surface activated bonding method and a hydrophilic bonding method may be combined.

[0259] For example, a method of cleaning the surface after polishing, subjecting the surface of the metal layer to an anti-oxidation treatment, and then subjecting it to a hydrophilic treatment and bonding can be used. The surface of the metal layer may be made of a resistant metal such as Au and then subjected to a hydrophilic treatment. Note that bonding methods other than the above-mentioned methods may also be used.

[0260] By the above-mentioned bonding, the circuit included in the layer 563b can be electrically connected to the elements of the pixel 100 included in the layer 563a.

[0261] <Modification of Laminate Structure 1> FIG. 14 shows a modified example of the stacked structure shown in FIG. 12, in which the configuration of the photoelectric conversion device 101 in the layer 561 and a portion of the configuration of the layer 563a are different, and a bonding surface is also provided between the layer 561 and the layer 563a.

[0262] Layer 561 includes photovoltaic device 101, insulating layers 661, 662, 664, 665 and conductive layers 685,686.

[0263] The photoelectric conversion device 101 is a pn junction type photodiode, and has a layer 565b corresponding to a p-type region and a layer 565a corresponding to an n-type region. Here, an example is shown in which a pn junction type photodiode is formed on a silicon substrate. The photoelectric conversion device 101 is a buried type photodiode, and a thin p-type region (part of layer 565b) provided on the surface side (current extraction side) of layer 565a can suppress dark current and reduce noise.

[0264] The insulating layer 661 and the conductive layers 685 and 686 function as bonding layers. The insulating layer 662 functions as an interlayer insulating film and a planarizing film. The insulating layer 664 functions as an element isolation layer.

[0265] The silicon substrate is provided with grooves for separating pixels, and the insulating layer 665 is provided on the upper surface of the silicon substrate and in the grooves. By providing the insulating layer 665, it is possible to prevent carriers generated in the photoelectric conversion device 101 from flowing out to adjacent pixels. The insulating layer 665 also has a function of preventing the intrusion of stray light. Therefore, the insulating layer 665 can prevent color mixing. An anti-reflection film may be provided between the upper surface of the silicon substrate and the insulating layer 665.

[0266] The insulating layer 664 can be formed by using a LOCOS (LOCal Oxidation of Silicon) method. Alternatively, it may be formed by using a STI (Shallow Trench Isolation) method or the like. For example, an inorganic insulating film such as silicon oxide or silicon nitride, or an organic insulating film such as polyimide resin or acrylic resin can be used as the insulating layer 665. The insulating layer 665 may have a multi-layer structure. A space may be provided in a part of the insulating layer 665. The space may contain a gas such as air or an inert gas. The space may be in a reduced pressure state.

[0267] A layer 565a (n-type region, corresponding to a cathode) of the photoelectric conversion device 101 is electrically connected to a conductive layer 685. A layer 565b (p-type region, corresponding to an anode) is electrically connected to a conductive layer 686. The conductive layers 685 and 686 have regions embedded in an insulating layer 661. The surfaces of the insulating layer 661 and the conductive layers 685 and 686 are flattened so that they are at the same height.

[0268] In the layer 563a, an insulating layer 638 is formed over the insulating layer 637. In addition, a conductive layer 683 electrically connected to one of the source and the drain of the transistor 102, and a conductive layer 684 electrically connected to the conductive layer 636 are formed.

[0269] The insulating layer 638 and the conductive layers 683 and 684 function as bonding layers. The conductive layers 683 and 684 have a region buried in the insulating layer 638. The surfaces of the insulating layer 638 and the conductive layers 683 and 684 are flattened so that they are at the same height.

[0270] Here, the conductive layers 683, 684, 685, and 686 are the same bonding layers as the above-mentioned conductive layers 619 and 639. The insulating layers 638 and 661 are the same bonding layers as the above-mentioned insulating layers 618 and 631.

[0271] Therefore, by bonding the conductive layer 683 and the conductive layer 685 together, it is possible to electrically connect the layer 565a (n-type region, corresponding to the cathode) of the photoelectric conversion device 101 to one of the source or drain of the transistor 102. Also, by bonding the conductive layer 684 and the conductive layer 686 together, it is possible to electrically connect the layer 565b (p-type region, corresponding to the anode) of the photoelectric conversion device 101 to the wiring 114 (see FIG. 3). Also, by bonding the insulating layer 638 and the insulating layer 661 together, it is possible to electrically and mechanically bond the layer 561 to the layer 563a.

[0272] 15 shows a modified example different from the above, in which the transistor 102 is provided in a layer 561. In this configuration, one of the source and the drain of the transistor 102 is directly connected to the photoelectric conversion device 101, and the other of the source and the drain acts as a node FD. In this configuration, the charge accumulated in the photoelectric conversion device 101 can be completely transferred, and an imaging device with low noise can be obtained.

[0273] Here, the other of the source and the drain of the transistor 102 included in the layer 561 is electrically connected to the conductive layer 692. One of the source and the drain of the transistor 104 included in the layer 563 is electrically connected to the conductive layer 691. The conductive layers 691 and 692 are the same bonding layers as the conductive layers 619 and 639 described above.

[0274] <Laminated structure 2> 16 is an example of a cross-sectional view of a stack having layers 560, 561, 562, and 563 and no bonding surface. A Si transistor is provided in the layer 563. An OS transistor is provided in the layer 562. Note that the structures of the layers 563, 561, and 560 are the same as those shown in FIG. 12, and therefore description thereof will be omitted here.

[0275] <layer 562> A layer 562 is formed over the layer 563. The layer 562 includes OS transistors. Here, the transistor 102 and the transistor 104 are shown. In the cross-sectional view shown in FIG. 16, electrical connection between the two is not shown.

[0276] Insulating layers 621, 622, 623, 624, 625, 626, and 628 are provided in the layer 562. In addition, a conductive layer 627 is provided. The conductive layer 627 can be electrically connected to the wiring 114 (see FIG. 3).

[0277] The insulating layer 621 functions as a blocking layer. The insulating layers 622, 623, 625, 626, and 628 function as an interlayer insulating film and a planarizing film. The insulating layer 624 functions as a protective film.

[0278] The blocking layer is preferably a film having a function of preventing hydrogen diffusion. In a Si device, hydrogen is required to terminate dangling bonds, but hydrogen near an OS transistor is one of the factors that generate carriers in an oxide semiconductor layer, thereby reducing reliability. Therefore, a hydrogen blocking film is preferably provided between a layer in which a Si device is formed and a layer in which an OS transistor is formed.

[0279] As the blocking film, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria stabilized zirconia (YSZ), or the like can be used.

[0280] The other of the source and the drain of the transistor 104 is electrically connected to the gate of the transistor 105 through a plug. In addition, the conductive layer 627 is electrically connected to the wiring 114 (see FIG. 3A).

[0281] One of the source and the drain of the transistor 102 is electrically connected to the cathode of the photoelectric conversion device 101 included in the layer 561. The conductive layer 627 is electrically connected to the anode of the photoelectric conversion device 101 included in the layer 561.

[0282] Fig. 17A shows details of an OS transistor. The OS transistor shown in Fig. 17A has a self-aligned structure in which an insulating layer is provided over a stack of an oxide semiconductor layer and a conductive layer, and a source electrode 705 and a drain electrode 706 are formed by providing openings that reach the oxide semiconductor layer.

[0283] The OS transistor can have a structure including a channel formation region 708, a source region 703, and a drain region 704 formed in the oxide semiconductor layer, as well as a gate electrode 701 and a gate insulating film 702. At least the gate insulating film 702 and the gate electrode 701 are provided in the opening. An oxide semiconductor layer 707 may be further provided in the opening.

[0284] As shown in FIG. 17B, the OS transistor may have a self-aligned structure in which a source region 703 and a drain region 704 are formed in a semiconductor layer using a gate electrode 701 as a mask.

[0285] Alternatively, as shown in FIG. 17C, it may be a non-self-aligned top-gate transistor having a region where the source electrode 705 or the drain electrode 706 overlaps with the gate electrode 701.

[0286] Although the OS transistor has a back gate 735, it may have a structure without a back gate. The back gate 735 may be electrically connected to the front gate of the transistor provided opposite to the back gate, as shown in the cross-sectional view of the transistor in the channel width direction in FIG. 17D. Note that FIG. 17D shows the cross section of the transistor taken along line B1-B2 in FIG. 17A as an example, but the same applies to transistors having other structures. In addition, a fixed potential different from that of the front gate may be supplied to the back gate 735.

[0287] <Modification of Laminate Structure 2> FIG. 18 shows a modified example of the stacked structure shown in FIG. 17, in which the configuration of the photoelectric conversion device 101 included in the layer 561 and a portion of the configuration of the layer 562 are different, and a bonding surface is provided between the layers 561 and 562.

[0288] The photoelectric conversion device 101 included in the layer 561 is a pn junction type photodiode, and has the same configuration as that shown in FIG.

[0289] In the layer 562, an insulating layer 648 is formed over the insulating layer 628. In addition, a conductive layer 688 electrically connected to one of the source and the drain of the transistor 102, and a conductive layer 689 electrically connected to the conductive layer 627 are formed.

[0290] The insulating layer 648 and the conductive layers 688 and 689 function as bonding layers. The conductive layers 688 and 689 have a region buried in the insulating layer 648. The surfaces of the insulating layer 648 and the conductive layers 683 and 684 are flattened so that they are at the same height.

[0291] Here, the conductive layers 688 and 689 are the same lamination layer as the above-mentioned conductive layers 619 and 639. The insulating layer 648 is the same lamination layer as the above-mentioned insulating layers 618 and 631.

[0292] Therefore, by bonding the conductive layer 688 and the conductive layer 685 together, it is possible to electrically connect the layer 565a (n-type region, corresponding to the cathode) of the photoelectric conversion device to one of the source or drain of the transistor 102. Also, by bonding the conductive layer 689 and the conductive layer 686 together, it is possible to electrically connect the layer 565b (p-type region, corresponding to the anode) of the photoelectric conversion device to the wiring 114 (see FIG. 3). Also, by bonding the insulating layer 648 and the insulating layer 661 together, it is possible to electrically and mechanically bond the layer 561 to the layer 562a.

[0293] When stacking multiple Si devices, the polishing and bonding processes are required multiple times. This poses issues such as a large number of steps, the need for dedicated equipment, low yields, and high manufacturing costs. OS transistors can be formed by stacking on a semiconductor substrate on which devices are already formed, eliminating the need for the bonding process.

[0294] Note that the structure in which the transistor 102 is provided in the layer 561 shown in FIG. 15 may be applied to this structure.

[0295] <Package, module> Fig. 20A1 is a perspective view showing the appearance of the upper surface of a package containing an image sensor chip. The package includes a package substrate 410 for fixing an image sensor chip 450 (see Fig. 20A3), a cover glass 420, and an adhesive 430 for bonding the two together.

[0296] 20A2 is a perspective view of the bottom surface of the package. The bottom surface of the package has a BGA (Ball grid array) with solder balls as bumps 440. Note that the package is not limited to a BGA, and may have an LGA (Land grid array) or a PGA (Pin Grid Array), etc.

[0297] 20A3 is a perspective view of the package with a portion of the cover glass 420 and the adhesive 430 omitted. Electrode pads 460 are formed on the package substrate 410, and the electrode pads 460 and the bumps 440 are electrically connected via through holes. The electrode pads 460 are electrically connected to the image sensor chip 450 by wires 470.

[0298] 20B1 is a perspective view of the appearance of the upper surface side of a camera module in which an image sensor chip is housed in a lens-integrated package. The camera module has a package substrate 411 for fixing an image sensor chip 451 (FIG. 20B3), a lens cover 421, a lens 435, and the like. Also, an IC chip 490 (FIG. 20B3) having functions such as a drive circuit for an imaging device and a signal conversion circuit is provided between the package substrate 411 and the image sensor chip 451, and the camera module has a configuration as a SiP (System in Package).

[0299] 20B2 is a perspective view of the appearance of the bottom surface side of the camera module. The bottom surface and side surfaces of the package substrate 411 have a QFN (Quad flat no-lead package) configuration with mounting lands 441 provided thereon. Note that this configuration is one example, and a QFP (Quad flat package) or the above-mentioned BGA may also be provided.

[0300] 20B3 is a perspective view of the module in which lens cover 421 and a part of lens 435 are omitted. Land 441 is electrically connected to electrode pad 461, and electrode pad 461 is electrically connected to image sensor chip 451 or IC chip 490 by wire 471.

[0301] By housing the image sensor chip in a package of the above-mentioned type, mounting on a printed circuit board or the like becomes easy, and the image sensor chip can be incorporated into various semiconductor devices and electronic devices.

[0302] This embodiment mode can be appropriately combined with the descriptions of other embodiment modes.

[0303] (Embodiment 3) Examples of electronic devices that can use the imaging device according to one embodiment of the present invention include display devices, personal computers, image storage devices or image playback devices equipped with a recording medium, mobile phones, game machines including portable types, portable data terminals, electronic book terminals, cameras such as video cameras and digital still cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, printer-combined machines, automated teller machines (ATMs), vending machines, etc. Specific examples of these electronic devices are shown in Figures 21A to 21F.

[0304] 21A shows an example of a portable information terminal, which includes a housing 981, a display portion 982, operation buttons 983, an external connection port 984, a speaker 985, a microphone 986, a camera 987, and the like. The portable information terminal includes a touch sensor in the display portion 982. Any operation, such as making a call or inputting characters, can be performed by touching the display portion 982 with a finger or a stylus. The imaging device and the operating method thereof according to one embodiment of the present invention can be applied to the portable information terminal.

[0305] The camera 987 has an imaging device according to one embodiment of the present invention, and can acquire distance information of a subject from an image acquired by the camera 987. A part of the image acquired by the camera 987 can be processed based on the distance information. For example, image processing can be performed to blur the front and rear of the main subject.

[0306] 21B shows an information terminal, which includes a housing 911, a display portion 912, a speaker 913, a camera 919, and the like. Information can be input and output using a touch panel function of the display portion 912. Characters and the like can be recognized from an image acquired by the camera 919, and the characters can be output as voice through the speaker 913. The imaging device and the operating method thereof according to one embodiment of the present invention can be applied to the portable data terminal.

[0307] 21C shows a surveillance camera, which includes a support base 951, a camera unit 952, a protective cover 953, and the like. The camera unit 952 is provided with a rotation mechanism and the like, and can capture images of the entire surroundings by installing it on a ceiling. The imaging device and its operating method according to one embodiment of the present invention can be applied to the elements for acquiring images in the camera unit. Note that the term "surveillance camera" is a common name and is not intended to limit the use. For example, a device having a function as a surveillance camera is also called a camera or a video camera.

[0308] 21D shows a video camera, which has a first housing 971, a second housing 972, a display unit 973, operation keys 974, a lens 975, a connection unit 976, a speaker 977, a microphone 978, and the like. The operation keys 974 and the lens 975 are provided in the first housing 971, and the display unit 973 is provided in the second housing 972. An imaging device and an operation method thereof according to one embodiment of the present invention can be applied to the video camera.

[0309] 21E shows a digital camera, which includes a housing 961, a shutter button 962, a microphone 963, a light-emitting portion 967, a lens 965, and the like. The imaging device and the operating method thereof according to one embodiment of the present invention can be applied to the digital camera.

[0310] 21F shows a wristwatch-type information terminal, which includes a display unit 932, a housing / wristband 933, a camera 939, and the like. The display unit 932 includes a touch panel for operating the information terminal. The display unit 932 and the housing / wristband 933 are flexible and have excellent wearability on the body. The imaging device and the operating method thereof according to one embodiment of the present invention can be applied to this information terminal.

[0311] FIG. 22A illustrates an external view of an automobile as an example of a moving object. The automobile 890 has a plurality of cameras 891 and the like, and can acquire information on the front, rear, left, right, and above the automobile 890. The imaging device and its operation method according to one embodiment of the present invention can be applied to the camera 891. The automobile 890 also includes various sensors (not shown), such as an infrared radar, a millimeter wave radar, and a laser radar. The automobile 890 can analyze images acquired by the camera 891 in a plurality of imaging directions 892, determine surrounding traffic conditions such as the presence or absence of guardrails and pedestrians, and perform automatic driving. The automobile 890 can also be used in a system that performs road guidance, hazard prediction, and the like.

[0312] In the imaging device of one embodiment of the present invention, the obtained image data can be subjected to arithmetic processing such as a neural network, thereby enabling processes such as increasing the image resolution, reducing image noise, face recognition (for crime prevention purposes, etc.), object recognition (for autonomous driving purposes, etc.), image compression, image correction (wide dynamic range), image restoration for lensless image sensors, positioning, character recognition, and reducing reflected glare.

[0313] In the above, an automobile is described as an example of a moving body, but the automobile may be any of an automobile having an internal combustion engine, an electric automobile, a hydrogen automobile, and the like. In addition, the moving body is not limited to an automobile. For example, the moving body may be a train, a monorail, a ship, an aircraft (helicopter, unmanned aerial vehicle (drone), airplane, rocket), and the like. A computer according to one embodiment of the present invention may be applied to these moving bodies to provide a system using artificial intelligence.

[0314] This embodiment mode can be appropriately combined with the descriptions of other embodiment modes. [Explanation of symbols]

[0315] 10a: circuit, 10b: circuit, 20: circuit, 30: circuit, 100: pixel, 101: photoelectric conversion device, 101a: photoelectric conversion device, 101b: photoelectric conversion device, 102: transistor, 102a: transistor, 102b: transistor, 103: transistor, 103a: transistor, 103b: transistor, 104: transistor, 104a: transistor, 104b: transistor, 105: transistor, 105a: transistor, 105b: transistor, 106: capacitor, 106a: capacitor, 106b: capacitor, 107: Transistor, 108: transistor, 114: wiring, 115: wiring, 116: wiring, 117: wiring, 118: wiring, 121: wiring, 122: wiring, 123: wiring, 124: wiring, 125: wiring, 126: wiring, 127: wiring, 128: wiring, 131: transistor, 131a: transistor, 131b: transistor, 132: transistor, 133: transistor, 134: transistor, 135: capacitor, 142: transistor, 143: transistor, 144: transistor, 145: capacitor, 151: wiring, 152: wiring, 161: transistor 162: transistor, 163: capacitor, 175: transistor, 175a: transistor, 175b: transistor, 176: transistor, 176a: transistor, 176b: transistor, 200: pixel block, 202: capacitor, 203: transistor, 204: transistor, 205: transistor, 206: transistor, 207: transistor, 210: pixel array, 212: wiring, 213: wiring, 214: wiring, 215: wiring, 216: wiring, 218: wiring, 219: wiring, 220: circuit, 222: transistor, 2 23: transistor, 224: transistor, 225: current supply unit, 226: current mirror unit, 230: circuit, 240: circuit, 252: transistor, 253: transistor, 254: transistor, 261: transistor, 262: transistor, 300: pixel array, 301: circuit, 302: circuit, 303: circuit, 304: circuit, 305: circuit, 311: wiring, 320: memory cell, 325: reference memory cell, 330: circuit, 350: circuit, 360: circuit, 370: circuit, 410: package substrate, 411: package substrate, 420: cover glass,421: lens cover, 430: adhesive, 435: lens, 440: bump, 441: land, 450: image sensor chip, 451: image sensor chip, 460: electrode pad, 461: electrode pad, 470: wire, 471: wire, 490: IC chip, 545: semiconductor layer, 546: insulating layer, 560: layer, 561: layer, 562: layer, 562a: layer, 563: layer, 563a: layer, 563b: layer, 563c: layer, 565a: layer, 565b: layer, 566a: layer, 566b: layer, 566c: layer, 566d: layer, 567a: layer, 567b: layer, 567c: layer, 567d: layer, 567e: layer, 611: silicon substrate, 612: insulating layer, 613: insulating layer, 614: insulating layer, 616: insulating layer, 617: insulating layer, 618: insulating layer, 619: conductive layer, 621: insulating layer, 622: insulating layer, 623: insulating layer, 624: insulating layer, 625: insulating layer, 626: insulating layer, 627: conductive layer, 628: insulating layer, 631: insulating layer, 632: silicon substrate, 633: insulating layer, 634: insulating layer, 635: insulating layer, 636: conductive layer, 637: insulating layer, 638: insulating layer, 639: conductive layer, 648: insulating layer, 651: insulating layer, 652: insulating layer, 653 : insulating layer, 654: insulating layer, 655: conductive layer, 661: insulating layer, 662: insulating layer, 664: insulating layer, 665: insulating layer, 671: light shielding layer, 672: optical conversion layer, 672B: color filter, 672G: color filter, 672IR: infrared filter, 672R: color filter, 672UV: ultraviolet filter, 673: microlens array, 683: conductive layer, 684: conductive layer, 685: conductive layer, 686: conductive layer, 688: conductive layer, 689: conductive layer, 691: conductive layer, 692: conductive layer, 701: gate electrode, 702: gate insulating film, 703: source region, 7 04: drain region, 705: source electrode, 706: drain electrode, 707: oxide semiconductor layer, 708: channel formation region, 735: back gate, 890: automobile, 891: camera, 892: imaging direction, 911: housing, 912: display unit, 913: speaker, 919: camera, 932: display unit, 933: housing / wristband, 939: camera, 951: support base, 952: camera unit, 953: protective cover, 961: housing, 962: shutter button, 963: microphone, 965: lens, 967: light emitting unit, 971: housing, 972: housing, 973: display unit,974: operation keys, 975: lens, 976: connection section, 977: speaker, 978: microphone, 981: housing, 982: display section, 983: operation buttons, 984: external connection port, 985: speaker, 986: microphone, 987: camera,

Claims

1. having a pixel, The pixel includes a first light receiving circuit, a second light receiving circuit, an amplifier circuit, and an arithmetic circuit; the amplifier circuit includes first to fifth transistors, the arithmetic circuit includes sixth to eleventh transistors and first and second capacitance elements; a first data output from the first light receiving circuit is input to a gate of the first transistor; the second data output from the second light receiving circuit is input to a gate of the second transistor; one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the fifth transistor; one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the fifth transistor; the other of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the third transistor; the other of the source and the drain of the first transistor is electrically connected to the gate of the third transistor; the other of the source and the drain of the second transistor is electrically connected to one of the source and the drain of the fourth transistor; the other of the source and the drain of the second transistor is electrically connected to the gate of the fourth transistor; a gate of the fourth transistor is electrically connected to one of a source and a drain of the sixth transistor; the other of the source and the drain of the sixth transistor is electrically connected to one electrode of the first capacitance element; the other electrode of the first capacitance element is electrically connected to one of the source and the drain of the eighth transistor; the other of the source and the drain of the eighth transistor is electrically connected to one of the source and the drain of the ninth transistor; a gate of the eighth transistor is electrically connected to a gate of the ninth transistor; the other of the source and the drain of the ninth transistor is electrically connected to one electrode of the second capacitance element; the other electrode of the second capacitance element is electrically connected to one of the source and the drain of the tenth transistor; the other electrode of the second capacitance element is electrically connected to the gate of the eleventh transistor; The imaging device, wherein the other of the source and the drain of the tenth transistor is electrically connected to the gate of the fourth transistor.

2. The imaging device according to claim 1, An electronic device that processes a part of an image captured by the imaging device based on distance information of a subject in the image analyzed by the imaging device.

Images