Method, device, and electronic equipment for restarting functional component on system on chip

Abstract

To provide a method, device and electronic equipment for restarting a functional component on a system on a chip.TECHNICAL MEANS: A method includes the steps of: interrupting access by a first bus interface of a first functional component on a system on a chip and a common bus in response to detecting the first functional component being in a first state; restarting the first functional component to change the first functional component from the first state to a second state; and resetting the access interruption by the first bus interface of the first functional component and the common bus, wherein the common bus is shared by at least two operating systems on the system on the chip.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to integrated circuit technology, and more particularly to a method, apparatus and electronic device for restarting functional components on a system-on-chip. [Background technology]

[0002] When multiple operating systems are executed in a system on chip (SoC), an abnormality may occur in the software of one of the multiple operating systems, which may cause an unexpected operation on a hardware functional component in the SoC, thereby causing an abnormality in the hardware functional component, or an abnormality caused by the hardware functional component itself. An abnormality in a hardware functional component is likely to affect the execution of other operating systems in the SoC. Summary of the Invention [Problem to be solved by the invention]

[0003] An embodiment of the present disclosure provides a method, apparatus, and electronic device for restarting functional components on a system-on-chip, which can realize restart of functional components and improve the overall stability of the system-on-chip, under the premise of avoiding affecting the execution of other operating systems. [Means for solving the problem]

[0004] A method for restarting a functional component on a system-on-chip according to a first aspect of an embodiment of the present disclosure includes the steps of: in response to detecting that a state of a first functional component on the system-on-chip is a first state, blocking access between a first bus interface of the first functional component and a shared bus; converting the first functional component from the first state to a second state by restarting the first functional component; and releasing the blockage of access between the first bus interface of the first functional component and the shared bus, wherein the shared bus is a bus shared by at least two operating systems on the system-on-chip.

[0005] An apparatus for restarting a functional component on a system-on-chip according to a second aspect of an embodiment of the present disclosure includes a first processing module for blocking access between a first bus interface of the first functional component and a shared bus in response to detecting that a state of a first functional component on the system-on-chip is a first state, a second processing module for converting the first functional component from the first state to a second state by restarting the first functional component, and a third processing module for unblocking access between the first bus interface of the first functional component and the shared bus, wherein the shared bus is a bus shared by at least two operating systems on the system-on-chip.

[0006] A computer-readable storage medium according to a third aspect of an embodiment of the present disclosure stores a computer program for executing a method for restarting a functional component on a system-on-chip described in any one of the above embodiments of the present disclosure.

[0007] An electronic device according to a fourth aspect of an embodiment of the present disclosure includes a processor and a memory for storing executable instructions of the processor, and the processor reads and executes the executable instructions from the memory to realize a method for restarting a functional component described in any one of the above embodiments of the present disclosure, or includes an apparatus for restarting a functional component on a system-on-chip described in any one of the above embodiments of the present disclosure.

[0008] A fifth aspect of an embodiment of the present disclosure provides a computer program product, which, when instructions in the computer program product are executed by a processor, performs a method for restarting a functional component on a system-on-chip according to any one of the above embodiments of the present disclosure. Effect of the Invention

[0009] According to the method, device, and electronic device for restarting a functional component on a system-on-chip according to the above embodiment of the present disclosure, when it is detected that a state of a first functional component on a system-on-chip is a first state (i.e., an abnormal state), an access between a first bus interface of the first functional component and the shared bus is blocked to prevent the first functional component from accessing the shared bus, thereby avoiding an unexpected access to the shared bus by the abnormal first functional component, thereby avoiding adverse effects on other operating systems and other functional components connected to the shared bus. Furthermore, in the case of access blocking, the first functional component is converted from the abnormal state to a second state (i.e., a normal operating state) by restarting the first functional component, and after the first functional component is normally restored, the access blocking between the first bus interface of the first functional component and the shared bus is released, so that the first functional component can normally access the shared bus. The first functional component in which an abnormality has occurred is restarted without affecting the execution of other operating systems on the shared bus, thereby realizing the recovery of the first functional component's normal access to the shared bus, thereby effectively improving the overall stability of a multi-operating system-on-chip. For example, the system-on-chip is a cockpit-driving integrated system, and one system-on-chip simultaneously executes at least two operating systems (e.g., one operating system for an intelligent cockpit and one operating system for an intelligent drive). According to the functional component restart method of one embodiment of the present disclosure, when an abnormality occurs in one or more functional components on the system-on-chip due to an abnormality in one of the operating systems, the abnormal functional component can be restored to a normal operating state without affecting the execution of the other operating system, thereby ensuring the stability of the other operating system. [Brief description of the drawings]

[0010] [Figure 1] 1 illustrates an exemplary application scenario of a method for restarting a functional component on a system-on-chip according to the present disclosure. [Diagram 2] 1 is a flowchart of a method for restarting functional components on a system-on-chip according to an exemplary embodiment of the present disclosure. [Diagram 3] 11 is a flowchart of a method for restarting a functional component on a system-on-chip according to another exemplary embodiment of the present disclosure. [Figure 4] 11 is a flowchart of a method for restarting functional components on a system-on-chip according to yet another exemplary embodiment of the present disclosure. [Diagram 5] 11 is a flowchart of a method for restarting functional components on a system-on-chip according to yet another exemplary embodiment of the present disclosure. [Figure 6] 11 is a flowchart of a method for restarting functional components on a system-on-chip according to yet another exemplary embodiment of the present disclosure. [Figure 7] 11 is a flowchart of a method for restarting functional components on a system-on-chip according to yet another exemplary embodiment of the present disclosure. [Figure 8] 11 is a flowchart of a method for restarting functional components on a system-on-chip according to yet another exemplary embodiment of the present disclosure. [Figure 9] 11 is a flowchart of a method for restarting functional components on a system-on-chip according to yet another exemplary embodiment of the present disclosure. [Figure 10] 11 is a flowchart of a method for restarting functional components on a system-on-chip according to yet another exemplary embodiment of the present disclosure. [Figure 11] 1 is an overall flowchart of a method for restarting functional components on a system-on-chip according to an exemplary embodiment of the present disclosure. [Figure 12]FIG. 2 is a structural schematic diagram of an apparatus for restarting functional components on a system-on-chip according to an exemplary embodiment of the present disclosure; [Figure 13] FIG. 13 is a structural schematic diagram of an apparatus for restarting functional components on a system-on-chip according to another exemplary embodiment of the present disclosure. [Figure 14] FIG. 13 is a structural schematic diagram of an apparatus for restarting functional components on a system-on-chip according to yet another exemplary embodiment of the present disclosure; [Figure 15] FIG. 13 is a structural schematic diagram of an apparatus for restarting functional components on a system-on-chip according to yet another exemplary embodiment of the present disclosure; [Figure 16] FIG. 13 is a structural schematic diagram of an apparatus for restarting functional components on a system-on-chip according to yet another exemplary embodiment of the present disclosure; [Figure 17] FIG. 2 is a structural block diagram of an apparatus for restarting functional components on a system-on-chip according to an exemplary embodiment of the present disclosure. [Figure 18] FIG. 2 is a structural schematic diagram of an access blocking unit according to an exemplary embodiment of the present disclosure. [Figure 19] FIG. 13 is a structural schematic diagram of an access blocking unit according to another exemplary embodiment of the present disclosure. [Figure 20] FIG. 13 is a structural schematic diagram of an access blocking unit according to yet another exemplary embodiment of the present disclosure. [Figure 21] 1 is a structural diagram of an electronic device according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] In the following, exemplary embodiments of the present disclosure will be described in detail with reference to the drawings in order to interpret the present disclosure. The described embodiments are merely some embodiments of the present disclosure and are not all embodiments, and the present disclosure is not limited to the exemplary embodiments.

[0012] The relative arrangement of components and steps, numerical expressions and values ​​described in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.

[0013] [Summary of this disclosure] In the process of realizing the present disclosure, the inventors have found that when multiple operating systems are executed in a system on chip (abbreviated as SoC, also called a system level chip, can also be abbreviated as chip), an abnormality may occur in the software of any one of the multiple operating systems, which is likely to cause an unexpected operation on a hardware functional component in the system on chip, thereby causing an abnormality in the hardware functional component, or causing an abnormality due to the hardware functional component itself. An abnormality in a hardware functional component may affect the execution of other operating systems in the system on chip.

[0014] [Illustrative Overview] 1 is an exemplary application scenario of the method for restarting functional components on a system-on-chip according to the present disclosure. As shown in FIG. 1, n operating systems can be executed in the system-on-chip 11, including operating system 121, operating system 122, ..., operating system 12n, where n is an integer greater than 1. The system-on-chip 11 can further include m functional components, including functional component 131, functional component 132, ..., functional component 13m, where each functional component is for performing a task of each operating system, where m is a positive integer. The functions of any two functional components may be the same or different. For example, the functional components may include hardware IP (Intellectual Property) cores such as a graphics processing unit (GPU) component, an image signal processing (ISP) component, a universal serial bus (USB) component, a peripheral component interconnect express (PCIE) component, and a neural network processing unit (NPU) component. The shared bus 14 is a bus shared by each operating system. That is, when the system-on-chip 11 executes each operating system, each functional component can execute a corresponding instruction by the functional component to complete a task of the corresponding function by interacting with each other through the shared bus 14.Taking a mobile device (e.g., a vehicle, a drone (unmanned aerial vehicle), etc.) equipped with an intelligent drive and an intelligent cockpit as an example, the operating system 121 can be an operating system corresponding to the intelligent cockpit, that is, the system-on-chip 11 can execute the operating system 121 to execute instructions of an algorithm or model related to the intelligent cockpit to realize the related functions of the intelligent cockpit, for example, the system-on-chip 11 executes the operating system 121 to execute instructions of an intelligent cockpit detection algorithm to detect the inside of the cockpit based on environmental data (e.g., images) in the cockpit collected by a sensor (e.g., a camera) in the cockpit, and obtain the detection results in the cockpit. The system-on-chip 11 executes the operating system 122 to execute instructions of an algorithm or model related to the intelligent drive to realize functions such as detection, planning, and control of the intelligent drive. The sensor in the mobile device collects external environment data, detects the external environment, and plans and controls based on the detection results of the external environment to realize the intelligent drive function of the mobile device. When the method of restarting a functional component on a system-on-chip according to the embodiment of the present disclosure is used to detect that the state of any one of the functional components (called a first functional component, for example, functional component 131, functional component 132, etc.) on the system-on-chip 11 is a first state (i.e., an abnormal state), the first bus interface of the first functional component is blocked from accessing the shared bus 14, thereby preventing the abnormal first functional component from outputting an access request to the shared bus 14, thereby preventing an unexpected operation from occurring. After blocking the access between the first bus interface of the first functional component and the shared bus 14, the first functional component is restarted, thereby converting the first functional component from the abnormal state to a second state (i.e., called a normal state or a normal operating state).In this case, since the first bus interface and the shared bus 14 are in an access blocking state, the first functional component is converted to a normal state but cannot access the shared bus 14. By releasing the access blocking between the first bus interface of the first functional component and the shared bus, the first functional component can be allowed to normally access the shared bus 14. The first functional component in which an abnormality has occurred can be restarted without affecting the execution of other operating systems on the shared bus 14, and the first functional component's normal access to the shared bus 14 is restored, thereby effectively improving the overall stability of the multi-operating system-on-chip 11.

[0015] The method of restarting functional components on a system-on-chip of the embodiment of the present disclosure is not limited to use in an integrated scenario between an intelligent drive and an intelligent cockpit (i.e., cockpit-driving integration), but can also be used in any other scenario in which at least two operating systems can be run simultaneously on a single system-on-chip (e.g., terminal device scenarios such as mobile phones, tablets, computers, etc.).

[0016] [Exemplary Method] 2 is a flowchart of a method for restarting a functional component on a system-on-chip according to an exemplary embodiment of the present disclosure. This embodiment can be used in an electronic device (specifically, a system-level chip (i.e., a system-on-chip) such as an in-vehicle computing platform), and as shown in FIG. 2, the method of the embodiment of the present disclosure can include the following steps 210 to 230.

[0017] In step 210, in response to detecting that a state of a first functional component on the system-on-chip is in a first state, access is blocked between a first bus interface of the first functional component and the shared bus.

[0018] Here, the shared bus is a bus shared by at least two operating systems on a system-on-chip. The system-on-chip may be a system level chip capable of simultaneously executing at least two operating systems at any given time. The first functional component may be any one of the functional components on the system-on-chip. For example, the first functional component may be any one of GPU, ISP, NPU, USB, PCIE, etc. The state of the first functional component may include a first state and a second state. The first state is an abnormal state. The second state is a normal state. In actual use, the state of the first functional component may further include a reset state. The access blocking refers to blocking the access of the first functional component to the shared bus, i.e., blocking (or stopping) the access request of the first functional component from being transmitted to the shared bus, to prevent the abnormal first functional component from initiating an unexpected operation on the shared bus and affecting other functional components and the operating system on the shared bus.

[0019] In some optional embodiments, the first functional component may correspond to a hardware module of any one of the operating systems on the system-on-chip. For example, when an abnormality occurs in software executed by an operating system on the system-on-chip, if the operating system uses the first functional component to execute a corresponding task, the abnormality of the operating system may cause an unexpected operation on the first functional component, for example, an unexpected configuration operation on the first functional component may cause an abnormality of the first functional component. When an abnormality of the first functional component is detected, the first bus interface of the first functional component is blocked from accessing the shared bus, so as to prevent the abnormality of the operating system from affecting the normal operation of the shared bus, thereby preventing the normal use of the shared bus by other operating systems. By recovering the abnormal operating system, the operating system can be restored to a normal state in a timely manner.

[0020] In some optional embodiments, the first bus interface of the first functional component is a bus interface through which the first functional component can spontaneously transmit an access request to the shared bus. For example, when supporting a master (main) bus interface and a slave (subordinate) bus interface, the first bus interface of the first functional component is the master interface of the first functional component. That is, the first functional component transmits an access request to the shared bus via the master bus interface and receives response information of the shared bus. The slave interface of the first functional component is for the shared bus to spontaneously transmit an access request to the first functional component, and the first functional component receives an access request from the shared bus via the slave interface and returns response information to the shared bus.

[0021] In some optional embodiments, the state of the first functional component can be detected in any feasible manner. For example, a built-in detection function of the first functional component detects whether the state of the first functional component is in an abnormal state, and when the abnormal state of the first functional component is detected, an abnormal state signal is fed back to the device executing the method of the embodiment of the present disclosure, and the device of the embodiment of the present disclosure can determine that the state of the first functional component on the system-on-chip is detected to be in an abnormal state. Also, for example, the execution status of the task assigned to the first functional component can be detected to determine whether the state of the first functional component is in an abnormal state. When no task execution result is obtained for a long period of time for the task assigned to the first functional component, it can be determined that the state of the first functional component is in an abnormal state. For example, when the ISP functional component does not feed back the execution result for the assigned signal processing task for a long period of time, it can be determined that the state of the ISP functional component is in an abnormal state. A specific manner of detecting the abnormal state of the first functional component is not limited.

[0022] In some optional embodiments, any feasible access blocking method can be adopted to block access between the first bus interface of the first functional component and the shared bus. For example, the access blocking can be realized by controlling opening and closing of a transmission path between the first bus interface and the shared bus by a bus switch. Also, for example, a transfer controller between the first bus interface and the shared bus is provided to control whether to transfer an access request of the first functional component to the shared bus to realize the access blocking. The specific access blocking method is not limited.

[0023] In step 220, restarting the first functional component causes the first functional component to transform from a first state to a second state.

[0024] The second state is the normal state (or operating state, also called the normal operating state).

[0025] In some optional embodiments, the first functional component can be restarted according to a restart method actually supported by the first functional component, for example, a reset signal or other method triggers the restart of the first functional component, and the first functional component is restored from the abnormal state to the normal state by restarting the first functional component.

[0026] In step 230, the access block between the first bus interface of the first functional component and the shared bus is released.

[0027] Releasing the access blockage between the first bus interface of the first functional component and the shared bus means no longer blocking the first functional component's access to the shared bus and ensuring that the access request of the first functional component can be normally transmitted to the shared bus.

[0028] In some optional embodiments, the access block between the first bus interface of the first functional component and the shared bus can be released based on a release method corresponding to the access block method. For example, when the bus switch realizes the access block by disconnecting the transmission path between the first bus interface and the shared bus, the bus switch is turned off to open the transmission path between the first bus interface and the shared bus, thereby releasing the access block. When the access block is realized by the transfer controller stopping the transfer of the access request of the first functional component to the shared bus, the transfer controller allows the transfer of the access request of the first functional component to the shared bus, thereby releasing the access block.

[0029] In the method for restarting a functional component on a system-on-chip according to the present embodiment, when detecting that a state of a first functional component on the system-on-chip is a first state (i.e., an abnormal state), the method cuts off access between a first bus interface of the first functional component and the shared bus to prevent the first functional component from accessing the shared bus, thereby avoiding an unexpected access to the shared bus by the abnormal first functional component, thereby avoiding adverse effects on other operating systems and other functional components connected to the shared bus. Furthermore, in the case of access cutoff, the first functional component is converted from the first state (i.e., an abnormal state) to a second state (i.e., a normal operating state) by restarting the first functional component, and after the first functional component is restored to normal, the cutoff of access between the first bus interface of the first functional component and the shared bus is released so that the first functional component can normally access the shared bus. The first functional component in which an abnormality has occurred is restarted without affecting the execution of other operating systems on the shared bus, thereby realizing the first functional component to restore normal access to the shared bus, thereby effectively improving the overall stability of the multi-operating system-on-chip. For example, the system-on-chip is a cockpit-driving integrated system, and one system-on-chip simultaneously executes at least two operating systems (e.g., one operating system for an intelligent cockpit and one operating system for an intelligent drive), and by using the method of restarting functional components on the system-on-chip of the embodiment of the present disclosure, if an abnormality occurs in one or more functional components on the system-on-chip due to an abnormality in one of the operating systems, the abnormal functional component can be restored to a normal operating state without affecting the execution of the other operating system, thereby ensuring the stability of the other operating system.

[0030] In some optional embodiments, in accordance with the embodiment shown in FIG. 2 above, blocking access between the first bus interface of the first functional component and the shared bus in step 210 may include cutting off a transmission path between the first bus interface and the shared bus, thereby preventing an access request of the first functional component from being transmitted to the shared bus.

[0031] In some optional embodiments, the purpose of preventing the access request of the first functional component from being transmitted to the shared bus can be achieved by cutting off the transmission path between the first bus interface and the shared bus by a bus switch or other method, so that the access request of the first functional component output from the first bus interface is not transmitted to the shared bus.

[0032] In this embodiment, by cutting off the transmission path between the first bus interface and the shared bus, access blocking between the first functional component and the shared bus is realized, and the first functional component is prevented from requesting unexpected access to the shared bus, so that the normal operation of other functional components and the operating system can be ensured, and the overall stability of the system can be improved.

[0033] In some optional embodiments, in addition to the embodiment shown in FIG. 2 above, blocking access between the first bus interface of the first functional component and the shared bus in step 210 may include ceasing to forward access requests of the first functional component to the shared bus.

[0034] When access to the shared bus of a first functional component is achieved by transferring an access request, if it is detected that the state of the first functional component is abnormal, an access blocking function between the first bus interface and the shared bus can be realized by stopping the transfer of the access request of the first functional component to the shared bus.

[0035] In this embodiment, by stopping the transfer of the access request of the first functional component to the shared bus, access blocking between the first functional component and the shared bus is realized, and the first functional component is prevented from requesting unexpected access to the shared bus, so that the normal operation of other functional components and the operating system can be ensured, and the overall stability of the system can be improved.

[0036] FIG. 3 is a flowchart of a method for restarting functional components on a system-on-chip according to another exemplary embodiment of the present disclosure.

[0037] In some optional embodiments, in addition to the embodiment shown in FIG. 2 above, after blocking access between the first bus interface of the first functional component and the shared bus, as shown in FIG. 3, the method of the embodiment of the present disclosure may further include the following step 310.

[0038] In step 310, it is detected whether the state between the first bus interface of the first functional component and the shared bus is idle.

[0039] Here, whether the relationship between the first bus interface and the shared bus is in an idle state means whether there is an access request that has not been responded to by the shared bus (i.e., whether all access requests sent by the first functional component to the shared bus before access was blocked have been responded to, and an access request being responded to means that response information returned from the shared bus has been received. If there is at least one access request that has not been responded to, it indicates that the relationship between the first bus interface and the shared bus is not in an idle state and is in the process of interaction. If it is determined that there is no access request that has not been responded to and the first functional component has not sent a new access request due to the access blocking, it indicates that the relationship between the first bus interface and the shared bus is in an idle state.

[0040] In some optional embodiments, the access request sent by the first functional component to the shared bus is a request that the first functional component accesses other functional components or the operating system through the shared bus to perform information interaction with the other functional components or the operating system. The access request may include instructions and / or data sent by the first functional component to other functional components or the operating system waiting for access. Taking an intelligent drive as an example, the access request sent by the first functional component may include, for example, sensor data, sensing result data, vehicle status information, etc. sent to other functional components or the operating system. In different situations, the access requests sent by different functional components may be different.

[0041] In some optional embodiments, the access request sent by the first functional component and the response information returned from the shared bus are cached to determine whether the access request has been responded to, and whether an idle state between the first bus interface of the first functional component and the shared bus is detected according to the response status of the access request.

[0042] In some optional embodiments, when the first bus interface and the shared bus are blocked from accessing, the controller can detect whether the first bus interface and the shared bus are in an idle state by ensuring that the response information returned from the shared bus can be received. For example, when the access is blocked by the bus switch, the controller of the bus switch can connect to the first bus interface and the shared bus through a bypass bus, and when the bus switch cuts off the transmission path between the first bus interface and the shared bus, the controller can determine whether the first bus interface and the shared bus are in an idle state based on the transmitted access request and response information. The response information received by the controller may or may not be forwarded to the first functional component. The controller can further return a confirmation signal to the shared bus to confirm that the response information has been received. Also, for example, when the access blocking is performed by the transfer controller, the transfer controller can hold to receive response information returned from the shared bus, and can determine whether the state between the first bus interface and the shared bus is idle according to the transmitted access request and response information. After receiving the response information, the transfer controller can return a confirmation signal to the shared bus to confirm that the response information has been received. When actually used, the access blocking can be performed in other ways to detect whether the state between the first bus interface and the shared bus is idle, and is not limited to the embodiments of the present disclosure.

[0043] The step 220 of transforming the first functional component from a first state to a second state by restarting the first functional component may include the following step 2210.

[0044] In step 2210, in response to detecting an idle state between the first bus interface and the shared bus, the first functional component is restarted, thereby transforming the first functional component from a first state to a second state.

[0045] For the specific operation of restarting the first functional component, refer to the above embodiment, and the description thereof will be omitted here.

[0046] In this embodiment, when it is determined that the relationship between the first bus interface and the shared bus is idle, the first functional component is restarted to ensure completion of the interaction between the first functional component and the shared bus, thereby allowing the shared bus to continue to normally process access requests from other operating systems or functional components, and ensuring normal operation of the shared bus.

[0047] FIG. 4 is a flowchart of a method for restarting functional components on a system-on-chip according to yet another exemplary embodiment of the present disclosure.

[0048] In some optional embodiments, in any one of the above embodiments, as shown in FIG. 4, step 210 of blocking access between a first bus interface of a first functional component and a shared bus in response to detecting that a state of a first functional component on a system-on-chip is in a first state may include the following steps 2110 to 2120.

[0049] In step 2110, in response to detecting a state of a first functional component on the system-on-chip in a first state, an access blocking enable signal is generated.

[0050] The access blocking enable signal can be 1 or a high level signal, or the access blocking enable signal can be 0 or a low level signal, which can be specifically set according to actual needs.

[0051] In some optional embodiments, the access blocking enable signal may be generated by a register, i.e., updating the value of the register from a value indicating not enabled to a value indicating enabled may indicate that the access blocking enable signal has been generated.

[0052] In some optional embodiments, the access blocking enable signal can be generated by controlling the level signal to be high or low.

[0053] In step 2120, access between the first bus interface of the first functional component and the shared bus is blocked based on the access blocking enable signal.

[0054] Execution of the access blocking is triggered by the access blocking enable signal, that is, in response to the access blocking enable signal, the first bus interface of the first functional component and the shared bus are made to access block.

[0055] In some optional embodiments, step 2120 of blocking access between the first bus interface of the first functional component and the shared bus based on the access blocking enable signal may include disconnecting a transmission path between the first bus interface and the shared bus based on the access blocking enable signal to prevent an access request of the first functional component from being transmitted to the shared bus. For example, the access blocking enable signal is provided to a controller of a bus switch provided on the transmission path between the first bus interface and the shared bus, and the controller controls the disconnection of the bus switch in response to the access blocking enable signal to thereby disconnect the transmission path between the first bus interface and the shared bus.

[0056] In some optional embodiments, step 2120 of access blocking the first bus interface of the first functional component and the shared bus based on the access blocking enable signal may include stopping forwarding the access request of the first functional component to the shared bus based on the access blocking enable signal. For example, when the access request and response information are transferred by a transfer controller, the transfer controller is respectively connected to the first bus interface and the shared bus, and when the access blocking enable signal is provided to the transfer controller, the transfer controller stops forwarding the access request of the first functional component to the shared bus in response to the access blocking enable signal.

[0057] In this embodiment, when an abnormality in the first functional component is detected, an access blocking enable signal is generated to trigger access blocking, thereby realizing precise control of the access blocking operation of the hardware for access blocking.

[0058] FIG. 5 is a flowchart of a method for restarting functional components on a system-on-chip according to yet another exemplary embodiment of the present disclosure.

[0059] In some optional embodiments, in any one of the above embodiments, as shown in FIG. 5 , step 220 of converting the first functional component from a first state to a second state by restarting the first functional component may include the following steps 2220 to 2230.

[0060] In step 2220, the first functional component is transitioned from a first state to a reset state by transitioning the reset signal of the first functional component from a non-enabled state to an enabled state.

[0061] The enable state of the reset signal can be 0 or a low level state, and correspondingly, the non-enable state of the reset signal can be 1 or a high level state. In actual use, the enable state of the reset signal can be 1 or a high level state, and correspondingly, the non-enable state of the reset signal can be 0 or a low level. Specifically, there is no limitation.

[0062] In some optional embodiments, the first functional component includes a reset pin, and the reset pin can provide a reset signal to the first functional component. For example, pulling the level of the reset pin from a high level to a low level indicates that the reset signal is converted from a non-enabled state to an enabled state, and the first functional component is reset in response to the reset enable signal to convert from the first state to the reset state. The specific operation of the first functional component resetting in response to the reset enable signal is a normal operation, and the description thereof is omitted here.

[0063] In step 2230, the reset signal of the first functional component is transitioned from an enabled state to a non-enabled state, thereby transitioning the first functional component from a reset state to a second state.

[0064] Since the first functional component cannot operate normally in the reset state, it is necessary to release the reset, i.e., by changing the reset signal of the first functional component from an enable state to a non-enable state, the first functional component is released from the reset state and changed from the reset state to a second state (i.e., the normal state). In such a case, the first functional component can operate normally, but when no task is assigned, the first functional component goes into an idle state, and after a task is assigned, the first functional component goes from the idle state to an operating state.

[0065] In some optional embodiments, the reset signal can be changed from an enabled state to a non-enabled state by pulling the reset pin of the first functional component from a low level to a high level, thereby releasing the first functional component from the reset state. The specific operation of releasing the first functional component from the reset state is a normal operation, and the description thereof is omitted here.

[0066] In this embodiment, by controlling the enable and disable of the reset signal of the first functional component, the first functional component can be reset and de-reset, thereby recovering the first functional component from an abnormal state to a normal state, and the first functional component can be independently restarted, thereby avoiding affecting the normal operation of other functional components and ensuring the overall stability of the system.

[0067] In some optional embodiments, the step 2210 of converting the first functional component from the first state to the second state by restarting the first functional component in response to detecting that the state between the first bus interface and the shared bus is idle may include the steps of converting the reset signal of the first functional component from a non-enabled state to an enabled state in response to detecting that the state between the first bus interface and the shared bus is idle, thereby converting the first functional component from the first state to the reset state, and converting the reset signal of the first functional component from an enabled state to a non-enabled state in response to detecting that the state between the first bus interface and the shared bus is idle, thereby converting the first functional component from the reset state to the second state. For specific operations of converting the first functional component from the first state to the second state, refer to the above embodiments, and the description thereof will be omitted here.

[0068] In some optional embodiments, there is no priority between the reset release in step 2230 and the access block release in step 230. That is, by converting the reset signal of the first functional component from a non-enabled state to an enabled state in step 2220, the first functional component is converted from the first state to a reset state, and then step 230 can be executed to release the access block. For example, the access block may be released after the reset is released, or the reset may be released after the access block is released, or the reset release and the access block release may be performed in parallel. Specifically, there is no limitation.

[0069] FIG. 6 is a flowchart of a method for restarting functional components on a system-on-chip according to yet another exemplary embodiment of the present disclosure.

[0070] In some optional embodiments, in any one of the above embodiments, as shown in FIG. 6 , step 230 of unblocking access between the first bus interface of the first functional component and the shared bus may include the following steps 2310 to 2320.

[0071] In step 2310, an access unblocking signal is generated.

[0072] The access block release signal can be a non-enable signal corresponding to the above access block enable signal. For example, when the access block enable signal is 1 or a high level signal, the access block release signal is 0 or a low level signal. When the access block enable signal is 0 or a low level signal, the access block release signal is 1 or a high level signal. The manner of generating the access block release signal is similar to that of the access block enable signal, and the access block release signal is generated, for example, by updating the value of a register or controlling the high and low levels, and will not be described in detail.

[0073] In step 2320, based on the access unblocking signal, the transmission path between the first bus interface and the shared bus is communicated, thereby allowing the first functional component to access the shared bus again.

[0074] When the access blocking is realized by disconnecting the transmission path between the first bus interface and the shared bus, the transmission path between the first bus interface and the shared bus is connected based on the access blocking release signal to release the access blocking. The operation of connecting the transmission path between the first bus interface and the shared bus is the opposite operation to the operation of disconnecting the transmission path. For example, the bus switch is controlled to be turned off to connect the transmission path between the first bus interface and the shared bus, thereby making the first functional component accessible to the shared bus again.

[0075] In this embodiment, after the first functional component returns to normal, the transmission path between the first bus interface and the shared bus is connected to realize the release of access blocking, thereby ensuring that the first functional component can restore normal access to the shared bus, and making the first functional component reusable to perform the corresponding functional task.

[0076] FIG. 7 is a flowchart of a method for restarting functional components on a system-on-chip according to yet another exemplary embodiment of the present disclosure.

[0077] In some optional embodiments, in any one of the above embodiments, as shown in FIG. 7 , step 230 of unblocking access between the first bus interface of the first functional component and the shared bus may include the following steps 2330 to 2340.

[0078] In step 2330, an access unblocking signal is generated.

[0079] For the access unblocking signal, refer to the above embodiment.

[0080] In step 2340, based on the access unblocking signal, the access request of the first functional component is permitted to be transferred to the shared bus.

[0081] When access blocking is performed by stopping the forwarding of the access request, the access request forwarding function is restarted based on an access unblocking signal, the access request sent by the first functional component is forwarded to the shared bus, so as to ensure that the first functional component has normal access to the shared bus, and the first functional component is called again to perform the corresponding functional task.

[0082] FIG. 8 is a flowchart of a method for restarting functional components on a system-on-chip according to yet another exemplary embodiment of the present disclosure.

[0083] In some optional embodiments, in any one of the above embodiments, as shown in FIG. 8, the method of the embodiment of the present disclosure may further include the following step 320.

[0084] In step 320, if a state of the first functional component is detected to be in a first state, the first functional component is proxied to respond to a request for access to the first functional component on the shared bus according to a preset bus protocol.

[0085] Proxying the first functional component means taking over and managing the task of responding to the access request of the shared bus, that is, responding to the access request of the shared bus instead of the first functional component in order to avoid the shared bus being unable to receive a response for a long period of time and hanging up because the first functional component is in an abnormal state and cannot respond normally to the access request of the shared bus. A bus hang-up means that devices on the bus cannot communicate normally due to some cause. For example, if the first functional component is abnormal and the shared bus cannot receive a response for a long period of time, the shared bus continues to wait for the response of the first functional component, so that other functional components on the shared bus and the operating system cannot start communication normally, and such a phenomenon is called a bus hang-up. In an embodiment of the present disclosure, in order to avoid hanging up of the shared bus, when it is detected that the state of the first functional component is in the first state, the first functional component is proxied to respond to the access request to the first functional component of the shared bus according to a preset bus protocol.

[0086] In some alternative embodiments, the access request to the first functional component of the shared bus can be an access request for another functional component or an operating system to access the first functional component via the shared bus. The access request can include instructions and / or data. For example, the access request can include an instruction for the operating system to assign a task to the first functional component and / or data related to the task, etc. The task can be, for example, a signal processing task, a graphics processing task, etc. The instruction can be an instruction corresponding to the signal processing task, an instruction corresponding to the graphics processing task. The data related to the task can be signal data to be processed corresponding to the signal processing task, graphics data to be processed corresponding to the graphics processing task.

[0087] In some optional embodiments, the preset bus protocol can be a bus protocol adopted for communication between the first functional component and the shared bus. In response to an access request to the first functional component of the shared bus according to the preset bus protocol, the response information to the shared bus is ensured to conform to the corresponding bus protocol, but the first functional component is abnormal, so the first functional component cannot obtain the data to be returned, and the specific data in the response information proxying the response may not be valid data. For example, if the first functional component is an ISP and the access request to the shared bus is a signal processing task assigned to the first functional component, and the first functional component is abnormal, the signal processing task cannot be completed, so the task execution result data cannot be obtained, and the response information responding to the access request by proxying the first functional component conforms to the information format of the preset bus protocol, but the specific result data is invalid result data. Usually, the demand side of the result data (e.g., a detection application program in the operating system) has a function of detecting the result data, and when it detects invalid data, it will not use it or take other related measures, so as not to adversely affect other operating systems and functional components.

[0088] In some optional embodiments, a hang-up prevention function module is provided between the second bus interface of the first functional component and the shared bus, and the first functional component is proxied by the hang-up prevention function module, so that the shared bus can respond to an access request to the first functional component according to a preset bus protocol. The second bus interface is an interface for receiving an access request spontaneously transmitted by the shared bus and returning response information to the shared bus, and the second bus interface can be called a slave (subordinate) bus interface. The hang-up prevention function module can be realized by any electric circuit structure capable of realizing a hang-up prevention function, and is not limited in the embodiments of the present disclosure.

[0089] There is no priority between step 320 and step 210. That is, the order of the access blocking state and the proxy state is not limited, and the access blocking state can be entered first, or the proxy state can be entered first, or the access blocking state and the proxy state can be entered simultaneously.

[0090] In this embodiment, when it is detected that the state of the first functional component is in the first state, the first functional component is proxied to respond to an access request to the first functional component on the shared bus according to a preset bus protocol, thereby effectively avoiding a hang-up of the shared bus and ensuring normal operation of other functional components and the operating system.

[0091] FIG. 9 is a flowchart of a method for restarting functional components on a system-on-chip according to yet another exemplary embodiment of the present disclosure.

[0092] In some optional embodiments, in any one of the above embodiments, when the state of the first functional component is a second state, as shown in FIG. 9, the method of the embodiment of the present disclosure may further include the following step 410.

[0093] In step 410, the response state of the first functional component to an access request from the shared bus is monitored and measured.

[0094] The response state of the first functional component to an access request from the shared bus is a state of whether the first functional component is in a timeout state and has not responded to the access request. The response state of the first functional component to an access request from the shared bus can include two states: a timeout state and a non-timeout state.

[0095] In some optional embodiments, a hang-up prevention function module between the second bus interface of the first functional component and the shared bus can monitor and measure the response state of the first functional component to the access request from the shared bus. For example, after receiving an access request of the shared bus, the hang-up prevention function module can apply a cache to record the access request, start a timer as a timer corresponding to the access request, and transfer the access request to the second bus interface to transmit it to the first functional component. If the hang-up prevention function module receives response information to the access request of the first functional component within a specified time length, it stops the timer corresponding to the access request, transfers the response information to the shared bus, and releases the cache occupied by the access request. If the timer corresponding to the access request exceeds a specified time length but the hang-up prevention function module has not yet received response information corresponding to the access request of the first functional component, or if the cache occupied by the access request has not yet been released even after the specified time length has passed, it determines that the response state of the first functional component to the access request from the shared bus is timed out.

[0096] In step 420, in response to the response status being timeout, it is determined that the state of the first functional component is detected to be in a first state.

[0097] If the response state of the first functional component to the access request from the shared bus is a timeout, it is determined that an abnormality may occur in the first functional component, and it is determined that the state of the first functional component is a first state (i.e., an abnormal state). Furthermore, access between the first bus interface of the first functional component and the shared bus can be blocked.

[0098] In some optional embodiments, in response to the first functional component's response state to an access request from the shared bus being a timeout, the first functional component may be proxied to respond to the access request to the first functional component on the shared bus in accordance with a pre-configured bus protocol.

[0099] In some optional embodiments, if the hang-up prevention functional module detects that the state of the first functional component is in an abnormal state, it can feed back abnormal state information to an associated software module, and in response to detecting that the state of the first functional component is in an abnormal state, the software module blocks access to the first bus interface of the first functional component and the shared bus.

[0100] In this embodiment, by monitoring and measuring the response state of the first functional component to an access request from the shared bus, an abnormal state of the first functional component can be detected in a timely manner, and the first functional component can be restarted in a timely manner by the method of the embodiment of the present disclosure, thereby allowing the first functional component to recover to a normal state as quickly as possible, thereby ensuring the stability of the entire system of the system-on-chip.

[0101] In some optional embodiments, if the response state of the first functional component to an access request from the shared bus is monitored to be timed out, the hang-up prevention functional module can voluntarily enter a proxy state and proxy the first functional component to respond to an access request to the first functional component on the shared bus in accordance with a preset bus protocol.

[0102] In some optional embodiments, when detecting that the state of the first functional component is in the first state, a proxy enable signal is generated, and in response to the proxy enable signal, the first functional component can proxy to respond to an access request to the first functional component of the shared bus according to a preset bus protocol. The proxy enable signal can be a 0 or low level signal, or the proxy enable signal can be a 1 or high level signal. The proxy enable signal is used to indicate to enter the proxy state, i.e., to proxy to respond to an access request to the first functional component of the shared bus according to a preset bus protocol.

[0103] In some optional embodiments, the generated proxy enable signal is transmitted to a hang-up prevention functional module, and the hang-up prevention functional module enters a proxy state in response to the proxy enable signal, proxies the first functional component, and can respond to access requests to the first functional component of the shared bus according to a preset bus protocol.

[0104] FIG. 10 is a flowchart of a method for restarting functional components on a system-on-chip according to yet another exemplary embodiment of the present disclosure.

[0105] In some optional embodiments, in any one of the above embodiments, as shown in FIG. 10, the method of the embodiment of the present disclosure may further include the following steps 240 to 250 after restarting the first functional component.

[0106] In step 240, a state reset signal is generated.

[0107] The state reset signal (also called the proxy non-enable signal or the proxy enable termination signal) is a signal for instructing the first functional component to proxy to stop responding to access requests to the first functional component from the shared bus in accordance with a preset bus protocol, and to begin monitoring and measuring the response status of the first functional component to access requests from the shared bus.

[0108] In step 250, based on the state reset signal, the proxy state is converted to a monitoring measurement state, where the proxy state is a state in which the first functional component proxies and responds to an access request to the first functional component on the shared bus in accordance with a preset bus protocol, and the monitoring measurement state is a state in which the response state of the first functional component to an access request from the shared bus is monitored and measured.

[0109] Converting from the proxy state to the monitor and measure state means proxying the first functional component to stop responding to the access request of the shared bus to the first functional component according to the preset bus protocol, and starting to monitor and measure the response state of the first functional component to the access request from the shared bus. After restarting the first functional component, since the first functional component has already been converted to a normal state and can normally respond to the access request of the shared bus, the operation of proxying the first functional component to respond to the access request can be stopped. Furthermore, by converting the response state of the first functional component to the access request from the shared bus in the above step 410 to monitor and measure, if the first functional component becomes abnormal again, the abnormal state of the first functional component can be detected in a timely manner and a hang-up prevention function can be performed. A detailed description is omitted.

[0110] It should be noted that there is no priority between the execution of steps 240 to 250 and the execution of step 230.

[0111] In this embodiment, after the first functional component is restored to a normal state, a state reset signal is generated to trigger the first functional component to stop responding to access requests by proxy, and the response state of the first functional component to the access request from the shared bus is monitored and measured, thereby ensuring that any abnormality occurring in the first functional component can be detected in a timely manner and recovered independently, and avoiding affecting the normal operations of other functional components on the shared bus and the operating system.

[0112] In some optional embodiments, Figure 11 is an overall flowchart of a method for restarting a functional component on a system-on-chip according to one exemplary embodiment of the present disclosure. As shown in Figure 11, the flow of the method may include the following steps 520 to 5620.

[0113] In step 520, if the state of the first functional component is normal (i.e., the second state), the response state of the first functional component to an access request from the shared bus is monitored and measured.

[0114] In step 5310, in response to the response status being timeout, proxy the first functional component to respond to the request for access to the first functional component on the shared bus according to the pre-established bus protocol.

[0115] In some optional embodiments, in response to the proxy enable signal, the first functional component may be proxied to respond to requests for access to the first functional component on the shared bus according to a pre-established bus protocol.

[0116] In step 5410, in response to the response status being timeout, an access blocking enable signal is generated. That is, if the response status is timeout, it can indicate that the status of the first functional component is a first state (i.e., an abnormal state), and an access blocking enable signal is generated.

[0117] In step 5420, access between the first bus interface of the first functional component and the shared bus is blocked based on the access blocking enable signal.

[0118] In step 5430, it is detected whether the state between the first bus interface of the first functional component and the shared bus is idle.

[0119] In step 5440, in response to detecting an idle state between the first bus interface and the shared bus, the first functional component is converted from an abnormal state to a reset state by converting a reset signal of the first functional component from a non-enabled state to an enabled state.

[0120] In step 5450, the reset signal of the first functional component is converted from an enabled state to a disabled state, thereby converting the first functional component from a reset state to a normal state.

[0121] In step 5510, an access unblocking signal is generated.

[0122] In step 5520, the access block is released based on the access release signal, thereby allowing the first functional component to normally access the shared bus.

[0123] In step 5610, a state reset signal is generated.

[0124] In step 5620, based on the state reset signal, the proxy state is changed to a monitoring measurement state, the proxy state is a state in which the first functional component responds to an access request to the first functional component on the shared bus according to a preset bus protocol by proxying the first functional component, and the monitoring measurement state is a state in which the response state of the first functional component to the access request from the shared bus is monitored and measured. Return to step 510 to execute this step.

[0125] The specific operations from step 510 to step 5620 above can be referred to in the above embodiment, so the description thereof will be omitted.

[0126] In the method of the embodiment of the present disclosure, the response state of the first functional component to an access request from the shared bus is monitored and measured, so that the abnormal state of the first functional component can be detected in a timely manner. When the abnormal state of the first functional component is detected, the access between the first functional component and the shared bus is blocked, so that the abnormal first functional component can be prevented from starting an unexpected access operation to the shared bus, thereby effectively avoiding the normal operation of other functional components on the shared bus and the operating system. Next, when the response of the first functional component times out or the first functional component is abnormal, the first functional component is proxy-responded to the access request of the shared bus to the first functional component, so that the shared bus can be effectively prevented from hanging up without a response for a long period of time. Furthermore, after the first functional component is normally restored, the access block can be released in a timely manner, so that the first functional component can restore normal access to the shared bus. Then, the first functional component is proxy-responded to stop responding to the access request, and the response state of the first functional component to the access request is monitored and measured, so that the re-abnormality of the first functional component can be detected in a timely manner. An automatic flow of functional components is realized, which is monitoring measurement, blocking and proxy response, restart, unblocking (conversion of proxy response to monitoring measurement), monitoring measurement, blocking and proxy response, restart, unblocking (conversion of proxy response to monitoring measurement), monitoring measurement, ..., and an independent reset of functional components is realized without affecting other functional components on the shared bus or normal operation of the operating system.

[0127] Each of the above embodiments of the present disclosure may be implemented alone, or may be implemented in any combination manner if there is no conflict; specifically, they may be set according to actual needs, and are not limited by the present disclosure.

[0128] The method for restarting a functional component on any one of the systems-on-chips according to the embodiments of the present disclosure can be executed by any suitable electronic device having data processing capability (including, but not limited to, electronic devices such as terminal devices and servers). Alternatively, the method for restarting a functional component on any one of the systems-on-chips according to the embodiments of the present disclosure can be executed by a processor, for example, the processor executes the method for restarting a functional component on any one of the systems-on-chips mentioned in the embodiments of the present disclosure by calling a corresponding instruction stored in a memory. Hereinafter, a detailed description thereof will be omitted.

[0129] (Exemplary Apparatus) 12 is a structural schematic diagram of an apparatus for restarting a functional component on a system-on-chip according to an exemplary embodiment of the present disclosure. The apparatus of this embodiment is for implementing the corresponding method embodiment of the present disclosure, and the apparatus of this embodiment can be installed in the system-on-chip. The apparatus shown in FIG. 12 includes a first processing module 710, a second processing module 720, and a third processing module 730.

[0130] The first processing module 710, in response to detecting that a state of a first functional component on the system-on-chip is in a first state, blocks access between a first bus interface of the first functional component and a shared bus, the shared bus being a bus shared by at least two operating systems on the system-on-chip.

[0131] In some optional embodiments, the first processing module 710 can be connected to the first bus interface and the shared bus, respectively. The first processing module 710 can include a hardware unit for blocking access. The hardware unit can be an electric circuit component that can block the access of the first bus interface of the first functional component to the shared bus, such as the above-mentioned bus switch and its controller, a transfer controller, etc.

[0132] In some optional embodiments, the first processing module 710 may further include software functional units, which may be processing units that perform corresponding functions in a processor and are used to control the operation of the hardware units.

[0133] The second processing module 720 is for transforming the first functional component from a first state to a second state by restarting the first functional component.

[0134] In some optional embodiments, the second processing module 720 can be coupled to the first processing module 710 and the first functional component, respectively. The second processing module 720 can be a functional module that can control the restart of the first functional component in the processor.

[0135] The third processing module 730 is for releasing the access blockage between the first bus interface of the first functional component and the shared bus.

[0136] In some optional embodiments, the third processing module 730 can be connected to the second processing module 720 and the first processing module 710, respectively. The third processing module 730 can be a functional module in a processor that can control a hardware unit of the access blocking to release the access blocking.

[0137] FIG. 13 is a structural schematic diagram of an apparatus for restarting functional components on a system-on-chip according to another exemplary embodiment of the present disclosure.

[0138] In some optional embodiments, on top of the embodiment shown in FIG. 12 above, the first processing module 710 may include an access blocking unit 7110.

[0139] In some optional embodiments, the access blocking unit 7110 may cut off the transmission path between the first bus interface and the shared bus, thereby preventing the access request of the first functional component from being transmitted to the shared bus.

[0140] In some optional embodiments, the access blocking unit 7110 may stop forwarding the access request of the first functional component to the shared bus.

[0141] In some optional embodiments, the access blocking units 7110 may be respectively connected to the first functional components and the shared bus.

[0142] In some optional embodiments, the access blocking unit 7110 can be a hardware unit that can cut off the transmission path between the first bus interface and the shared bus, or stop the transfer of the access request of the first functional component to the shared bus. For example, the access blocking unit 7110 can include the above-mentioned bus switch and its controller, or can include the above-mentioned transfer controller.

[0143] In some optional embodiments, as shown in FIG. 13, the first processing module 710 includes an access blocking unit 7110.

[0144] The access blocking unit 7110 can detect whether the relationship between the first bus interface of the first functional component and the shared bus is idle, and send an idle state signal to the second processing module 720 in response to detecting that the relationship between the first bus interface and the shared bus is idle.

[0145] In some optional embodiments, the access blocking unit 7110 can further be directly or indirectly connected to the second processing module 720. For example, the access blocking unit 7110 is connected to the processor through the external pin of the processor in which the second processing module 720 is located, to realize the connection with the second processing module 720. The access blocking unit 7110 can send an idle state signal to the processor, and the processor can transmit the idle state signal to the second processing module 720 in the processor. Or, the access blocking unit 7110 writes a state reset signal to a register, and the processor obtains the state reset signal from the register and transmits it to the second processing module 720.

[0146] The second processing module 720 specifically restarts the first functional component in response to the idle state signal.

[0147] In some optional embodiments, after receiving the idle state signal, the second processing module 720 restarts the first functional component, causing the first functional component to transform from the first state to the second state.

[0148] FIG. 14 is a structural schematic diagram of an apparatus for restarting functional components on a system-on-chip according to yet another exemplary embodiment of the present disclosure.

[0149] In some optional embodiments, the first processing module 710 may include an access blocking unit 7110 and a first processing unit 7120.

[0150] The first processing unit 7120 generates an access blocking enable signal in response to detecting that a state of the first functional component on the system-on-chip is in a first state.

[0151] In some alternative embodiments, the first processing unit 7120 may be a processing unit that executes corresponding functions in a processor.

[0152] The access blocking unit 7110 blocks access between the first bus interface of the first functional component and the shared bus in response to the access blocking enable signal. The access blocking unit 7110 can be directly or indirectly connected to the first processing unit 7120, for example, connected to the first processing unit 7120 by a register and receiving the access blocking enable signal by the register.

[0153] In some optional embodiments, the access blocking unit 7110 can be an electrical circuit component respectively connected to the first bus interface and the shared bus.

[0154] In some optional embodiments, the access blocking unit 7110 may specifically, in response to an access blocking enable signal, disconnect the transmission path between the first bus interface and the shared bus, thereby preventing the access request of the first functional component from being transmitted to the shared bus.

[0155] In some optional embodiments, the access blocking unit 7110 may specifically stop forwarding an access request of the first functional component to the shared bus in response to an access blocking enable signal.

[0156] In some optional embodiments, the access blocking unit 7110 detects whether the first bus interface of the first functional component is in an idle state and the shared bus, and in response to detecting that the first bus interface is in an idle state and the shared bus, sends an idle state signal to the second processing module 720. The second processing module 720 specifically restarts the first functional component in response to the idle state signal.

[0157] In some optional embodiments, second processing module 720 specifically converts the first functional component from a first state to a reset state by converting a reset signal of the first functional component from a non-enabled state to an enabled state, and converts the first functional component from a reset state to a second state by converting a reset signal of the first functional component from an enabled state to a non-enabled state.

[0158] In some optional embodiments, after restarting the first functional component, the access blocking unit 7110 is also involved in the reset and reset release, that is, the first functional component is reset and reset, and the access blocking unit 7110 is also reset and reset, so as to ensure the normal operation of the access blocking unit 7110 and prevent the access blocking unit 7110 from being affected by the abnormal first functional component and causing an abnormality. In this case, the reset signal of the first functional component can be simultaneously provided to the access blocking unit 7110 to trigger the reset and reset release of the access blocking unit 7110, or the reset signal of the first functional component can simultaneously trigger the reset and reset release of the first functional component and the access blocking unit 7110 based on the connection relationship between the first functional component and the access blocking unit, and specifically, the manner of triggering the access blocking unit 7110 is not limited.

[0159] In some optional embodiments, when the access blocking unit 7110 is not easily affected by the abnormal first functional component, only the first functional component may be involved in the reset and reset release. When the access blocking unit 7110 is affected by the abnormal first functional component and an abnormality may occur, the first functional component and the access blocking unit 7110 may be involved in the reset and reset release. The specific involvement in the reset and reset release may be set according to the degree of independence of the access blocking unit 7110 from the first functional component. For example, when the access blocking unit 7110 is not easily affected by the abnormality of the first functional component because the functional logic of the access blocking unit 7110 is relatively complex or relatively strong, only the first functional component is involved in the reset and reset release, and the involvement of the access blocking unit 7110 is not required. Otherwise, the first functional component and the access blocking unit 7110 are involved in the reset and reset release.

[0160] FIG. 15 is a structural schematic diagram of an apparatus for restarting functional components on a system-on-chip according to yet another exemplary embodiment of the present disclosure.

[0161] In some optional embodiments, as shown in FIG. 15, the third processing module 730 can include a second processing unit 7310.

[0162] The second processing unit 7310 generates an access unblocking signal, and transmits the access unblocking signal to the first processing module 710 .

[0163] The second processing unit 7310 is connected to the second processing module 720 and the first processing module 710, respectively.

[0164] In some optional embodiments, the second processing unit 7310 may be connected to the access blocking unit 7110 in the first processing module 710, and may transmit an access unblocking signal to the access blocking unit 7110, triggering the access blocking unit 7110 to perform an operation to unblock the access, thereby restoring normal access of the first functional component to the shared bus.

[0165] In some alternative embodiments, the second processing unit 7310 can be a processing unit in a processor. For example, the second processing unit 7310 writes the access unblocking signal to a register, and provides the access unblocking signal to the first processing module 710 through the register. Or, the second processing unit 7310 updates the level of the access blocking enable terminal of the first processing module 710 to a level indicating non-enablement that is the opposite of the access blocking enable signal, for example, when the access blocking enable signal is at a high level, the non-enablement level is at a low level.

[0166] In response to the access unblocking signal, the first processing module 710 may enable the first functional component to access the shared bus again by connecting a transmission path between the first bus interface and the shared bus, or in response to the access unblocking signal, the first processing module may allow the transfer of an access request of the first functional component to the shared bus.

[0167] In some optional embodiments, the access blocking unit 7110 in the first processing module 710 can, in response to an access unblocking signal, enable the first functional component to access the shared bus by connecting a transmission path between the first bus interface and the shared bus, or can, in response to the access unblocking signal, allow the first functional component's access request to be transferred to the shared bus.

[0168] FIG. 16 is a structural schematic diagram of an apparatus for restarting functional components on a system-on-chip according to yet another exemplary embodiment of the present disclosure.

[0169] In some optional embodiments, in any one of the above embodiments, as shown in Fig. 16, the device of the embodiment of the present disclosure may further include a preset function module 740. The preset function module 740 is the above-mentioned hang-up prevention function module.

[0170] In some optional embodiments, the preset function modules 740 are respectively connected to the second bus interface of the first functional component and the shared bus. The second bus interface of the first functional component is an interface for receiving an access request spontaneously transmitted by the shared bus and returning response information to the shared bus, and the second bus interface can be called a slave bus interface.

[0171] In some optional embodiments, if the preset functional module 740 detects that the state of the first functional component is in the first state, it proxies the first functional component to respond to requests for access to the first functional component on the shared bus according to a preset bus protocol.

[0172] In some optional embodiments, the preset function module 740 can be implemented by adopting any operable electrical circuit components. For example, the preset function module 740 can implement a corresponding proxy response function by adopting a controller or a microprocessor, etc., that is, proxying the first functional component to respond to an access request to the first functional component of the shared bus according to a preset bus protocol.

[0173] In some optional embodiments, when the state of the first functional component is the second state, the preset functional module 740 may monitor and measure a response state of the first functional component to an access request from the shared bus, and determine that the state of the first functional component has been detected to be the first state in response to the response state being a timeout.

[0174] In some optional embodiments, the preset function module 740 can realize monitoring measurement for the response state of the first functional component by a timer, a controller (or microprocessor), a cache, etc. For example, after receiving an access request of the shared bus, the controller of the preset function module 740 can record the access request by a cache, start a timer corresponding to the access request, and transfer the access request to the second bus interface to transmit to the first functional component. If the controller of the preset function module 740 receives response information for the access request of the first functional component within a specified time length, the controller of the preset function module 740 stops the timer corresponding to the access request, transfers the response information to the shared bus, and releases the cache occupied by the access request. If the timer corresponding to the access request exceeds a specified time length and the controller of the preset function module 740 has not yet received response information for the access request of the first functional component, or if the controller of the preset function module 740 has not yet released the cache occupied by the access request after the specified time length has passed, the controller determines that the response state of the first functional component to the access request from the shared bus is timed out.

[0175] In some optional embodiments, if the response state of the first functional component to any one of the access requests from the shared bus is monitored to be timed out, the preset functional module 740 may spontaneously enter a proxy state and proxy the first functional component to respond to the access requests to the first functional component on the shared bus according to the preset bus protocol.

[0176] In some optional embodiments, the preset functional module 740 can be in a passive proxy state in response to a proxy enable signal to proxy the first functional component to respond to requests to access the first functional component of the shared bus according to a preset bus protocol. The proxy enable signal can be generated by a module or unit in the processor and transmitted to the preset functional module 740, and the preset functional module 740 can be in response to the proxy enable signal to proxy the first functional component to respond to requests to access the first functional component of the shared bus according to the preset bus protocol.

[0177] In some optional embodiments, the apparatus of the disclosed embodiments may further include a fourth processing module 750, as shown in FIG.

[0178] The fourth processing module 750 sends a state reset signal to the preset functional module 740 after restarting the first functional component.

[0179] In some optional embodiments, the fourth processing module 750 can be a processing module in a processor and sends a state reset signal to the preset functional module 740 after restarting the first functional component.

[0180] The preset functional module 740 can be converted from the proxy state to the monitor measurement state in response to a state reset signal, the proxy state being a state in which the first functional component responds to an access request to the first functional component of the shared bus in accordance with a preset bus protocol, and the monitor measurement state being a state in which the first functional component's response to the access request from the shared bus is monitored and measured. That is, in response to a state reset signal, the preset functional module 740 can stop proxying the first functional component to respond to an access request to the first functional component of the shared bus in accordance with the preset bus protocol, and start monitoring and measuring the response state of the first functional component to the access request from the shared bus.

[0181] Before the preset functional module 740 receives a state reset signal (i.e., when the preset functional module 740 is in the proxy state), whenever the shared bus sends a new access request to the first functional component, the preset functional module 740 responds by proxying the first functional component, and when the preset functional module 740 is converted from the proxy state to the monitor measurement state, the first functional component responds to the access request from the shared bus.

[0182] In some optional embodiments, FIG. 17 is a structural block diagram of an apparatus for restarting a functional component on a system-on-chip according to one exemplary embodiment of the present disclosure. As shown in FIG. 17, the apparatus for restarting a functional component on a system-on-chip according to an embodiment of the present disclosure may include a software portion 810 and a hardware portion 820. The software portion 810 may include the above-mentioned first processing unit 7120, the second processing module 720, the second processing unit 7310, and the fourth processing module 750. The hardware portion 820 may include the above-mentioned access blocking unit 7110 and a preset function module (i.e., hang-up prevention function module) 740. The first function component 830 may include a master (main) bus interface 8310 and a slave (subordinate) bus interface 8320. The master bus interface 8310 is a first bus interface. The slave bus interface 8320 is a second bus interface. The access blocking unit 7110 is respectively connected to the master bus interface 8310 and the shared bus 840. The preset function module 740 is respectively connected to the slave bus interface 8320 and the shared bus 840. Based on the structure shown in Fig. 17, taking the case where only the first function component 830 is involved in resetting and releasing the resetting, and the access blocking unit 7110 is not involved, as an example, the operation process of the device of the embodiment of the present disclosure includes the following process 1, process 2, and process 3.

[0183] In the process 1, when the state of the first functional component 830 is normal, the access blocking unit 7110 is in a bypass state (or called an unblocked state), that is, the access blocking unit 7110 does not perform access blocking for the master bus interface 8310 and the shared bus 840, and does not affect the transmission path between the master bus interface 8310 and the shared bus 840, and the master bus interface 8310 can normally access the shared bus 840. The first functional component 830 can transmit an access request to the shared bus 840 through the master bus interface 8310 and receive response information to the access request of the shared bus 840. When the state of the first functional component 830 is normal (second state), the shared bus 840 can transmit an access request to the first functional component 830 through the slave bus interface 8320 and receive response information to the access request of the first functional component 830. In such a case, the preset functional module 740 enters a monitoring and measurement state, and monitors and measures the response state of the first functional component 830 to an access request from the shared bus 840. When the preset functional module 740 monitors and measures that the response state of the first functional component 830 is timeout, it determines that it has detected that the state of the first functional component 830 is an abnormal state (first state).

[0184] In step 2, when the preset function module 740 determines that the state of the first functional component 830 is an abnormal state (first state), or when the preset function module 740 monitors and measures that the response state of the first functional component 830 to any one of the access requests from the shared bus 840 is timed out, the preset function module 740 can feed back to the software part 810 a notification message that the first functional component 830 is in an abnormal state. Then, the preset function module 740 can automatically change from the monitoring and measurement state to the proxy state, that is, the preset function module 740 takes over and manages the bus, proxies the first functional component 830, and responds to the access request of the shared bus to the first functional component 830 according to a preset bus protocol, so that the access request of the shared bus 840 to the first functional component 830 can timely obtain response information, and the shared bus 840 can be prevented from hanging up without obtaining response information for a long period of time, so that the shared bus can continue to operate normally and does not affect the normal operations of other functional components and other operating systems. Optionally, the software portion 810 generates and transmits a proxy enable signal to the preset functional module 740, and the preset functional module 740 can be passively converted from a monitoring measurement state to a proxy state in response to the proxy enable signal to proxy the first functional component 830 and respond to an access request to the first functional component 830 on the shared bus according to a preset bus protocol. The proxy enable signal is generated, for example, by the fourth processing module 750, and the proxy enable signal and the state reset signal are inverse signals, which can realize the conversion between the proxy state and the monitoring measurement state of the preset functional module 740.Alternatively, the proxy enable signal and the state reset signal can be provided to the preset function module 740 by controlling the change of a signal at one of the proxy enable ends of the preset function module 740, that is, the proxy enable signal can be provided to the preset function module 740 by setting the signal at the proxy enable end to a signal indicating proxy enable (e.g., 1 or high level), and the state reset signal can be provided to the preset function module 740 by setting the signal at the proxy enable end to a signal indicating proxy non-enable (e.g., 0 or low level). When the first processing unit 7120 of the software part 810 obtains the notification message of the preset function module 740, it determines that the state of the first functional component 830 is detected to be in an abnormal state, generates an access blocking enable signal, and transmits the access blocking enable signal to the access blocking unit 7110, for example, the access blocking enable signal in the drawing is provided to the access blocking unit 7110 through the enable end of the access blocking unit 7110. In response to the access blocking enable signal, the access blocking unit 7110 is converted from a bypass state to an access blocking state, that is, the master bus interface 8310 of the first functional component 830 and the shared bus 840 perform access blocking. For example, the access blocking unit 7110 cuts off the transmission path between the master bus interface 8310 and the shared bus 840, so as to prevent the access request of the first functional component 830 from being transmitted to the shared bus 840, or the access blocking unit 7110 stops transferring the access request of the first functional component 830 to the shared bus 840, so as to achieve the purpose of access blocking.Then, the access blocking unit 7110 waits for response information of the access request transmitted to the shared bus 840 before blocking, i.e. detects whether the state between the master bus interface 8310 of the first functional component 830 and the shared bus 840 is idle. If all the access requests sent by the first functional component 830 obtain response information from the shared bus 840, it can be determined that the state between the master bus interface 8310 and the shared bus 840 is detected to be idle, and the access blocking unit 7110 can send an idle state signal to the second processing module 720. In response to the idle state signal, the second processing module 720 changes the reset signal of the reset end of the first functional component 830 from a non-enabled state to an enabled state, thereby resetting the first functional component 830 and changing it from an abnormal state to a reset state; and the second processing module 720 changes the reset signal of the first functional component 830 from an enabled state to a non-enabled state, thereby releasing the reset of the first functional component 830 and changing it from the reset state to a normal state, thereby realizing the restart of the first functional component 830. In actual use, selectively, the reset signal line connected to the software part 810 in FIG. 17 is simultaneously connected to the first functional component 830 and the access blocking unit 7110, so that the first functional component 830 and the access blocking unit 7110 can participate in resetting and releasing the reset; that is, by changing the reset signal from a non-enabled state to an enabled state, the first functional component 830 can be changed from an abnormal state to a reset state, and the access blocking unit 7110 can be changed to a reset state. Furthermore, by changing the reset signal from an enable state to a non-enable state, the first functional component can be changed from a reset state to a second state, and the access blocking unit 7110 can be changed from a reset state to a normal state. Optionally, there is no priority between the reset release and the access blocking release.If the reset is released first, after the reset is released, the access blocking unit 7110 can perform access blocking for the master bus interface 8310 and the shared bus 840 in response to the access blocking enable signal until the access blocking unit 7110 receives an access blocking release signal and restores the normal access of the first functional component 830 to the shared bus 840 in response to the access blocking release signal. If the access blocking enable signal has already been updated to the access blocking release signal after the reset is released, the access blocking unit 7110 can release the access blocking in response to the access blocking release signal and enter a bypass state. Or, as shown in FIG. 17, a reset signal of one of the first functional components can simultaneously trigger the reset and reset release of the first functional component 830 and the access blocking unit 7110.

[0185] In step 3, after the first functional component 830 is restarted, the second processing unit 7310 can generate an access unblocking signal (i.e., an access blocking non-enable signal), for example, when the access blocking enable signal is 1 or a high level signal, the access unblocking signal is 0 or a low level signal, and when the access blocking enable signal is 0 or a low level signal, the access unblocking signal is 1 or a high level signal. The second processing unit 7310 transmits the access unblocking signal to the access blocking unit 7110, and the access blocking unit 7110 responds to the access unblocking signal by changing the access blocking state to a bypass state, i.e., the access blocking unit 7110 communicates the transmission path between the master bus interface 8310 and the shared bus 840, thereby allowing the first functional component 830 to access the shared bus. Or, the access blocking unit 7110 transfers the access request of the first functional component 830 to the shared bus 840, thereby allowing the first functional component 830 to access the shared bus 840. In addition, after the first functional component 830 is restarted, the fourth processing module 750 can further send a state reset signal (i.e., a proxy non-enable signal or a signal to terminate proxy enable) to the preset functional module 740. In response to the state reset signal, the preset functional module 740 changes from the proxy state to a monitoring measurement state, i.e., stops the first functional component 830 from proxying and responding to the access request of the shared bus 840, and monitors and measures the response state of the first functional component 830 to the access request from the shared bus 840. By moving to the above process 1 and repeating it in this manner, the independent recovery of the functional component can be ensured to avoid affecting other functional components and the operating system, and the stability of the entire system of the system-on-chip can be improved. The software portion 810 may be provided in at least one operating system, or may be provided outside the operating system, and is not specifically limited.When the software portion 810 is provided in an operating system, if a functional component is abnormal due to an abnormality of the operating system, the abnormal operating system is restarted by another operating system or a recovery program other than the operating system, and the operating system is normally restored, and then the method of restarting the functional component on the system-on-chip of the embodiment of the present disclosure can be executed. When the software portion 810 is provided in multiple operating systems, if a functional component is abnormal due to an abnormality of one operating system, the method of the embodiment of the present disclosure can be executed by the other operating system that runs normally. When the software portion 810 is provided other than the operating system and is not affected by the operating system, when it is detected that the functional component is abnormal, the method of the embodiment of the present disclosure can be directly executed. The specific arrangement position of each module and unit of the device of the embodiment of the present disclosure is not limited.

[0186] In some optional embodiments, FIG. 18 is a structural schematic diagram of an access blocking unit 7110 according to an exemplary embodiment of the present disclosure. As shown in FIG. 18, the access blocking unit 7110 may include a bus switch K and a controller C, and the controller C may control the disconnection of the bus switch K, thereby disconnecting the transmission path (i.e., the main transmission path L1) between the master bus interface 8310 and the shared bus 840, so as to disable the transmission of the access request of the first functional component 830 to the shared bus 840, thereby achieving the purpose of access blocking. The controller C is connected to the shared bus 840 through a bypass L2 to enable the transmission of the response information of the shared bus 840 to the controller C, and the controller C may or may not forward the response information to the master bus interface 8310. The controller C can determine whether the state between the master bus interface 8310 and the shared bus 840 is idle according to the response information of the shared bus 840, and when detecting that the state between the master bus interface 8310 and the shared bus 840 is idle, the controller C can send an idle state signal to the second processing module 720 to trigger the restart of the first functional component 830. After restarting the first functional component 830, the controller C can control the bus switch K to be turned off to communicate the transmission path L1 between the master bus interface 8310 and the shared bus 840, and the master bus interface 8310 accesses the shared bus 840 through the main path L1, and the access blocking unit 7110 is in a bypass state and does not affect the access and response interaction of the main path.

[0187] In some optional embodiments, FIG. 19 is a structural schematic diagram of an access blocking unit 7110 according to another exemplary embodiment of the present disclosure. As shown in FIG. 19, the access blocking unit 7110 includes a transfer controller C1, and the access request of the first functional component 830 and the response information of the shared bus 840 output from the master bus interface 8310 are both transferred by the transfer controller C1. When it is necessary to perform access blocking for the master bus interface 8310 and the shared bus 840, the transfer controller C1 stops transferring the access request of the first functional component 830 to the shared bus 840 to realize the access blocking. When it is necessary to release the access blocking, the transfer controller C1 restores the function of transferring the access request to the shared bus 840 to release the access blocking.

[0188] In some optional embodiments, FIG. 20 is a structural schematic diagram of an access blocking unit 7110 according to yet another exemplary embodiment of the present disclosure. As shown in FIG. 20, the access blocking unit 7110 includes a transfer blocking subunit 71110 and a response completion detection subunit 71120. The transfer blocking subunit 71110 includes a blocking enable terminal for receiving an access blocking enable signal and an access unblocking signal. The response completion detection subunit 71120 includes an interface idle indication output terminal for outputting an idle state signal. In response to the access blocking enable signal of the blocking enable terminal, the transfer blocking subunit 71110 enters an access blocking state, blocks the access request output from the master bus interface 8310, and stops transferring the access request to the shared bus 840. The response completion detection subunit 71120 can detect whether all the access requests already sent to the shared bus 840 have been responded to (i.e., whether all of them have received response information of the shared bus 840). When detecting that all the access requests have been responded to, the second processing module 7310 outputs an interface idle indication signal (i.e., an idle state signal). The idle state signal can be sent to the second processing module 720 to trigger the restart of the first functional component 830. After restarting the first functional component 830, the second processing unit 7310 updates the signal of the interruption enable end to an access interruption signal, and the transfer blocking sub-unit 71110 changes the access interruption state to a bypass state in response to the access interruption signal, and transfers the access request output from the master bus interface 8310 to the shared bus 840, so as to restore the normal access of the first functional component 830 to the shared bus 840.

[0189] The beneficial technical effects corresponding to the exemplary embodiments of the present apparatus may be referred to the beneficial technical effects corresponding to the exemplary methods described above, and therefore the description thereof will be omitted.

[0190] [Examples of electronic devices] FIG. 21 is a structural diagram of an electronic device according to an embodiment of the present disclosure, which includes at least one processor 91 and a memory 92.

[0191] The processor 91 may be a central processing unit (CPU) or other type of processing unit having data processing and / or instruction execution capabilities, and may control other components in the electronic device 90 to perform desired functions.

[0192] The memory 92 may include one or more computer program products, which may include various forms of computer-readable storage media, such as, for example, volatile memory and / or non-volatile memory. The volatile memory may include, for example, random access memory (RAM) and / or high-speed buffer memory (cache). The non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. The computer-readable storage media may store one or more computer program instructions, and the processor 91 may execute one or more computer program instructions to realize the methods of the embodiments of the present disclosure described above and / or other desired functions.

[0193] In one example, electronic device 90 may further include input devices 93 and output devices 94 connected to each other via a bus system and / or other type of connection mechanism (not shown).

[0194] The input device 93 may include, for example, a touch screen, a microphone, various sensors, and the like. The sensors may include, for example, an image sensor (for example, a camera, a camera, and the like), a laser radar, a millimeter wave radar, an ultrasonic radar, a positioning sensor, a pressure sensor, an air quality sensor, a temperature sensor, and the like. The image sensor, the laser radar, the millimeter wave radar, the ultrasonic radar, and the like may be used to detect the surrounding environment, that is, to detect dynamic / static objects in the surrounding environment. The dynamic / static objects may include, for example, static objects such as lanes, road edges, arrows, signboards, trees, and buildings, and dynamic objects such as surrounding vehicles, pedestrians, and cyclists. The positioning sensor may realize the positioning of a mobile device (for example, a self-vehicle, a robot, and the like) in which the electronic device is located. The positioning sensor may include, for example, an inertial measurement unit (abbreviated as IMU), a global positioning system (abbreviated as GPS), and the like. The pressure sensor may detect the seat pressure. The temperature sensor can detect the temperature within the vehicle cockpit.The air quality sensor can detect the air quality within the vehicle cockpit.

[0195] The output device 94 can output various information to the outside, and can include, for example, a display, a speaker, a communication network, and a remote output device connected thereto.

[0196] Of course, for the sake of simplicity, Fig. 21 shows only some of the components related to the present disclosure in the electronic device 90, and components such as buses, input / output interfaces, etc. Other than this, the electronic device 90 may further include any other suitable components according to a specific application.

[0197] In some optional embodiments, an electronic device according to an embodiment of the present disclosure may include an apparatus for restarting functional components on a system-on-chip according to any one of the above embodiments of the present disclosure.

[0198] [Exemplary Computer Program Products and Computer-Readable Storage Media] In addition to the methods and apparatus described above, embodiments of the present disclosure may be computer program products that include computer program instructions that, when executed by a processor, can cause the processor to perform the steps of the methods of the various embodiments of the present disclosure described in the "Exemplary Methods" section above of this specification.

[0199] The computer program product may be written in any combination of one or more programming languages ​​to create program code for carrying out the operations of the disclosed embodiments, including object-oriented programming languages ​​such as Java, C++, and the like, as well as general procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed as follows: entirely on the user computing device, partially on the user equipment, as a separate software package, partly on the user computing device and partly on a remote computing device, or entirely on a remote computing device or a server.

[0200] An embodiment of the present disclosure may also be a computer-readable storage medium having stored thereon computer program instructions that, when executed by a processor, can cause the processor to perform the steps of the methods of the various embodiments of the present disclosure described in the "Exemplary Methods" section herein above.

[0201] The computer readable storage medium may be any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may include, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples (non-exhaustive list) of readable storage media include an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read only memory (EPROM or flash memory), optical fiber, a compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0202] Although the basic principles of the present disclosure have been described above with reference to specific embodiments, the advantages, merits, effects, etc. mentioned in the present disclosure are merely illustrative and not limiting, and various embodiments of the present disclosure do not necessarily have these advantages, merits, effects, etc. In addition, the specific details of the above disclosure are merely illustrative and easy to understand, and are not limiting, and the above details do not necessarily limit the present disclosure to be realized by the above specific details.

[0203] Those skilled in the art can make various modifications and variations to the present disclosure without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application are within the scope of the claims of the present disclosure and their equivalent technologies, these modifications and variations can belong to the scope of the present disclosure.

Claims

1. 1. A method for restarting a functional component on a system-on-chip, each step being performed by an apparatus for restarting a functional component on the system-on-chip, comprising: in response to detecting that a state of a first functional component on the system-on-chip is in a first state, blocking access to a first bus interface of the first functional component and a shared bus; transforming the first functional component from the first state to a second state by restarting the first functional component; releasing access blocking between the first bus interface of the first functional component and the shared bus; 11. A method for restarting a functional component on a system-on-chip, comprising: a shared bus that is shared by at least two operating systems on the system-on-chip;

2. The step of blocking access between the first bus interface of the first functional component and the shared bus includes: disconnecting a transmission path between the first bus interface and the shared bus to prevent an access request of the first functional component from being transmitted to the shared bus; or 2. The method of claim 1, further comprising the step of causing the first functional component to stop forwarding access requests to the shared bus.

3. After the step of blocking access between the first bus interface of the first functional component and the shared bus, detecting whether a state between the first bus interface of the first functional component and the shared bus is idle; The step of restarting the first functional component includes:

2. The method of claim 1, further comprising the step of restarting the first functional component in response to detecting the idle state between the first bus interface and the shared bus.

4. In response to detecting that a state of the first functional component on the system-on-chip is the first state, the step of blocking access between the first bus interface of the first functional component and the shared bus includes: generating an access blocking enable signal in response to detecting that a state of the first functional component on the system-on-chip is in the first state; 2. The method for restarting a functional component on a system-on-chip as described in claim 1, further comprising: blocking access between the first bus interface of the first functional component and the shared bus based on the access blocking enable signal.

5. The step of releasing the access blockage between the first bus interface of the first functional component and the shared bus includes: generating an access unblocking signal; 5. The method for restarting a functional component on a system-on-chip described in any one of claims 1 to 4, further comprising: a step of enabling the first functional component to access the shared bus again by communicating a transmission path between the first bus interface and the shared bus based on the access unblocking signal, or a step of allowing the first functional component to transfer an access request to the shared bus based on the access unblocking signal.

6. When detecting that the state of the first functional component is the first state, 5. The method for restarting a functional component on a system-on-chip of claim 1, further comprising the step of proxying the first functional component to respond to a request to access the first functional component of the shared bus according to a preset bus protocol.

7. If the state of the first functional component is the second state, monitoring and measuring a response state of the first functional component to an access request from the shared bus; 7. The method of claim 6, further comprising: determining that a state of the first functional component is detected to be in the first state in response to the response state being a timeout.

8. After the step of restarting the first functional component, generating a state reset signal; and changing the state from the proxy state to a monitoring measurement state based on the state reset signal; the proxy state is a state in which the first functional component is proxied and the first functional component is responded to in accordance with a preset bus protocol in response to an access request to the first functional component of the shared bus; 7. The method for restarting a functional component on a system-on-chip as described in claim 6, further comprising: a step in which the monitoring and measuring state is a state of monitoring and measuring a response state of the first functional component to an access request from the shared bus.

9. The step of transforming the first functional component from the first state to the second state by restarting the first functional component includes: causing a reset signal of the first functional component to transition from a non-enabled state to an enabled state, thereby transitioning the first functional component from the first state to a reset state; and causing the reset signal of the first functional component to transition from an enabled state to a non-enabled state, thereby transitioning the first functional component from the reset state to the second state.

10. 1. An apparatus for restarting a functional component on a system-on-chip, comprising: a first processing module for blocking access between a first bus interface of a first functional component on the system-on-chip and a shared bus in response to detecting that the first functional component is in a first state; a second processing module for transforming the first functional component from the first state to a second state by restarting the first functional component; a third processing module for releasing access blockage between the first bus interface of the first functional component and the shared bus; 13. An apparatus for restarting a functional component on a system-on-chip, wherein the shared bus is a bus shared by at least two operating systems on the system-on-chip.

11. The first processing module is an access blocking unit for blocking a transmission path between the first bus interface and the shared bus to prevent an access request of the first functional component from being transmitted to the shared bus; or 11. The apparatus for restarting a functional component on a system-on-chip according to claim 10, further comprising: the access blocking unit for stopping the transfer of an access request of the first functional component to the shared bus.

12. The first processing module is an access blocking unit for detecting whether an idle state is present between the first bus interface of the first functional component and the shared bus, and for transmitting an idle state signal to the second processing module in response to detecting the idle state between the first bus interface and the shared bus; 11. The apparatus of claim 10, further comprising: the second processing module for restarting the first functional component in response to the idle state signal.

13. The first processing module is a first processing unit for generating an access blocking enable signal in response to detecting that a state of the first functional component on the system-on-chip is in the first state; 11. The apparatus for restarting a functional component on a system-on-chip according to claim 10, further comprising: an access blocking unit for blocking access between the first bus interface of the first functional component and the shared bus in response to the access blocking enable signal.

14. The third processing module is a second processing unit for generating an access unblocking signal and transmitting the access unblocking signal to the first processing module; 14. The apparatus for restarting a functional component on a system-on-chip according to claim 10, further comprising: the first processing module for enabling the first functional component to access the shared bus by communicating a transmission path between the first bus interface and the shared bus in response to the access unblocking signal; or the first processing module for allowing transfer of an access request of the first functional component to the shared bus in response to the access unblocking signal.

15. and a preset function module connected to the second bus interface of the first functional component and the shared bus, respectively; 14. The apparatus for restarting a functional component on a system-on-chip according to claim 10, wherein when the preset functional module detects that the state of the first functional component is the first state, the preset functional module proxies the first functional component and responds to an access request to the first functional component on the shared bus according to a preset bus protocol.

16. 16. The apparatus for restarting a functional component on a system-on-chip of claim 15, wherein the preset functional module monitors and measures a response state of the first functional component to an access request from the shared bus when the state of the first functional component is the second state, and determines that the state of the first functional component is the first state in response to the response state being a timeout.

17. a fourth processing module for sending a state reset signal to the preset functional module after restarting the first functional component; and the preset function module for transitioning from a proxy state to a monitoring measurement state in response to the state reset signal, the proxy state is a state in which the first functional component is proxied and the first functional component is responded to in accordance with a preset bus protocol in response to an access request to the first functional component of the shared bus; 16. The apparatus for restarting a functional component on a system-on-chip according to claim 15, wherein the monitoring and measuring state is a state for monitoring and measuring a response state of the first functional component to an access request from the shared bus.

18. The second processing module is transitioning a reset signal of the first functional component from a non-enabled state to an enabled state, thereby transitioning the first functional component from the first state to a reset state; 14. The apparatus for restarting a functional component on a system-on-chip of claim 10, further comprising: causing the reset signal of the first functional component to change from an enabled state to a non-enabled state, thereby causing the first functional component to change from the reset state to the second state.

19. 1. A computer-readable storage medium, comprising:

5. A computer-readable storage medium having stored thereon a computer program for executing the method for restarting a functional component on a system-on-chip according to claim 1 .

20. 1. An electronic device comprising a processor and a memory for storing instructions executable by the processor, or, the processor reads and executes the executable instructions from the memory to implement the method for restarting functional components on a system-on-chip according to any one of claims 1 to 4; An electronic device comprising the device for restarting a functional component on a system-on-chip according to any one of claims 10 to 13.

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