Semiconductor device

Abstract

To form a pixel circuit and a drive circuit on the same substrate with transistors having different structures according to the characteristics of the circuit to provide a display device having excellent display characteristics.SOLUTION: A semiconductor device includes a pixel unit and a drive circuit unit on the same substrate, and the drive circuit unit includes a transistor for the drive circuit in which a gate electrode layer, a source electrode layer, and a drain electrode layer are composed of a metal film, and a channel layer is composed of an oxide semiconductor. Further, the pixel unit includes a transistor for a pixel in which a gate electrode layer, a source electrode layer, and a drain electrode layer are composed of an oxide conductor, and the semiconductor layer is composed of an oxide semiconductor. The transistor for a pixel is made of a translucent material, and a display device having a high aperture ratio can be manufactured.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a display device using an oxide semiconductor. [Background technology]

[0002] In recent years, transistors have been constructed using semiconductor thin films formed on substrates with insulating surfaces. This technology is attracting attention. Transistors are widely used in electronic devices such as ICs and electro-optical devices. In particular, development as a switching element for image display devices is being accelerated. Indium oxide is a well-known material that has a wide variety of uses. It is used as a transparent electrode material required for liquid crystal displays and other devices.

[0003] Some metal oxides exhibit semiconducting properties. Metal oxides that exhibit semiconducting properties include For example, tungsten oxide, tin oxide, indium oxide, zinc oxide, etc. Transistors that use metal oxides that exhibit excellent semiconductor properties as channel formation regions are already known. (Patent Document 1 and Patent Document 2).

[0004] In addition, a transistor using an oxide semiconductor has a relatively high field-effect mobility. The transistor can also be used to form a driver circuit of a display device or the like. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A Summary of the Invention [Problem to be solved by the invention]

[0006] In display devices, the pixel section (also called the pixel circuit) and the driver circuit section are formed on the same substrate. In this case, the transistors used in the pixel portion are required to have excellent switching characteristics, e.g., a high on-off ratio. The transistors used in the driver circuits are required to operate at high speed.

[0007] In particular, the higher the pixel density of the display device, the shorter the time it takes to write a display image. It is preferable that the transistor used in the pixel portion operates at high speed. The problem was that the higher the density, the smaller the aperture ratio.

[0008] Therefore, one embodiment of the present invention disclosed in this specification is a display device that solves the above problems and a method for manufacturing the same. It relates to the manufacturing method. [Means for solving the problem]

[0009] One embodiment of the present invention disclosed in this specification is a liquid crystal display device having a pixel portion and a driver circuit portion over the same substrate, The pixel portion includes a first gate electrode layer, a gate insulating layer on the first gate electrode layer, and a gate insulating layer. a first source electrode layer and a first drain electrode layer which are partly overlapped with the first gate electrode layer on the first electrode layer; a first source electrode layer and a first drain electrode layer are formed on the gate insulating layer, the first source electrode layer and the first drain electrode layer being partially overlapped with each other; a first transistor including a first oxide semiconductor layer, a first source electrode layer, a first drain electrode layer, a first oxide insulating layer on the first oxide semiconductor layer; a connection electrode layer electrically connected to the first drain electrode layer; a first oxide insulating layer and a connection A second oxide insulating layer on the electrode layer, a protective insulating layer on the second oxide insulating layer, and a second insulating layer on the protective insulating layer. and a pixel electrode layer electrically connected to the connection electrode layer. The drive circuit section is a gate insulating layer on the electrode layer, a second gate electrode layer, and a second oxide semiconductor on the gate insulating layer; a second source electrode disposed on the second oxide semiconductor layer and partially overlapping the second oxide semiconductor layer; a second transistor including a second source electrode layer and a second drain electrode layer; and a second source electrode layer; A second oxide insulating layer and a second oxide insulating film are formed on the second drain electrode layer and the second oxide semiconductor layer. a protective insulating layer on the oxide insulating layer; and a first gate electrode layer, a gate insulating layer, a first oxide A semiconductor layer, a first source electrode layer, a first drain electrode layer, a first oxide insulating layer, a second A display device, characterized in that an oxide insulating layer, a protective insulating layer, and a pixel electrode layer have a light-transmitting property. be.

[0010] In this specification, the ordinal numbers such as 1st and 2nd are used for convenience. In addition, the specific name is not used as a matter for identifying the invention. This does not indicate the

[0011] The first gate electrode layer, the first source electrode layer and the first drain electrode layer of the first transistor The electrode layer is formed of a metal oxide and includes a second gate electrode layer of a second transistor, The second source electrode layer and the second drain electrode layer are formed of a metal.

[0012] The metal oxides include indium oxide, indium oxide tin oxide alloy, indium oxide oxide A zinc oxide alloy or zinc halide can be used.

[0013] In addition, a light-transmitting planarizing insulating layer is provided between the second oxide insulating layer and the protective insulating layer in the pixel portion. may be formed.

[0014] In addition, a conductive layer is formed on the protective insulating layer that overlaps with the second oxide semiconductor layer of the driver circuit section. That's fine.

[0015] The first oxide insulating layer and the second oxide insulating layer are made of inorganic insulating material formed by a sputtering method. For example, silicon oxide, silicon oxynitride, aluminum oxide, or oxide Aluminum nitride or the like can be used.

[0016] In addition, between the second oxide semiconductor layer and the second source electrode layer of the second transistor, An oxide conductive layer is formed between each of the second oxide semiconductor layer and the second drain electrode layer. By adopting such a configuration, the contact resistance can be reduced. As the oxide conductive layer, a transistor capable of high speed operation can be realized. It is preferable that the composition contains indium oxide. Examples of such oxide conductive layers include zinc oxide, zinc aluminum oxide, and zinc aluminum oxynitride. zinc oxide, zinc gallium oxide, etc.

[0017] In another embodiment of the present invention disclosed in this specification, a first gate electrode is provided in a region that becomes a pixel portion. A layer is formed, a second gate electrode layer is formed in a region that will become a driving circuit section, and a first gate electrode layer is formed. A gate insulating layer is formed on the second gate electrode layer, and a first gate electrode is formed on the gate insulating layer. a first source electrode layer and a first drain electrode layer overlapping a portion of the gate insulating layer; A first oxide layer overlapping a portion of the first source electrode layer and a portion of the first drain electrode layer. A semiconductor layer is formed to form a first transistor, and a second gate electrode layer is formed on the gate insulating layer. a second oxide semiconductor layer overlapping a part of the first oxide semiconductor layer; An insulating layer is formed, and a second semiconductor layer is formed on the first oxide insulating layer so as to overlap a part of the second oxide semiconductor layer. A first source electrode layer and a second drain electrode layer are formed to form a second transistor, and the first drain A connection electrode layer is formed to be electrically connected to the rain electrode layer, and a first oxide insulating layer, a second oxide insulating layer, and a second oxide insulating layer are formed. A second oxide insulating layer is formed on the semiconductor layer, the second source electrode layer, and the second drain electrode layer. A protective insulating layer is formed on the second oxide insulating layer, and a protective insulating layer is formed on the protective insulating layer in the region that will become the pixel portion. A method for manufacturing a display device, comprising forming a pixel electrode layer electrically connected to a connection electrode layer. It is law.

[0018] In the above-described manufacturing method, the first gate electrode layer, the gate insulating layer, and the first oxide semiconductor layer, a first source electrode layer, a first drain electrode layer, a first oxide insulating layer, a second oxide insulating layer The border layer, the protective insulating layer, and the pixel electrode layer have a light-transmitting property.

[0019] The shape of the oxide insulating layer formed on the first oxide semiconductor layer and the second oxide semiconductor layer is The oxide semiconductor layer is dehydrated or dehydrogenated, and then the oxide semiconductor layer is oxidized without being exposed to the air. It is preferable to prevent water or hydrogen from re-entering the semiconductor layer.

[0020] In this specification, dehydration or dehydrogenation refers only to the desorption of water or H2. This does not only include the elimination of H, OH, etc.

[0021] Dehydration or dehydrogenation is performed using inert gases such as nitrogen or noble gases (argon, helium, etc.). Heating is performed in an atmosphere at a temperature of 400°C or higher and lower than the distortion point of the substrate, preferably at a temperature of 425°C or higher and 700°C or lower. It is preferably carried out by heat treatment.

[0022] Heat treatment is performed under an inert gas atmosphere of nitrogen or rare gas (argon, helium, etc.). In this case, the oxide semiconductor layer becomes oxygen-deficient by heat treatment and has low resistance, that is, becomes n-type ( n - Then, an oxide insulating layer is formed in contact with the oxide semiconductor layer. It is said that the oxide semiconductor layer is made to have a high resistance, that is, to be an i-type, by making the oxide semiconductor layer into an oxygen-excess state. This makes it possible to manufacture a display device having a transistor with good electrical characteristics and high reliability. It will be possible to manufacture and provide

[0023] The heat treatment conditions for the dehydrated or dehydrogenated oxide semiconductor layer are as follows: Even when the oxide semiconductor layer was measured up to 450℃ by TDS (thermal desorption spectrometry), Two peaks indicating the desorption of , at least one peak appearing around 300 °C, were not detected. Therefore, in the case of a transistor using an oxide semiconductor layer that has been dehydrated or dehydrogenated, Even if TDS is used to measure up to 450°C, water appears at least at around 300°C. No peaks are detected.

[0024] The oxide semiconductor layer that has been dehydrated or dehydrogenated is not exposed to the air and is then cooled to room temperature. It is important not to re-contaminate the oxide semiconductor layer by dehydration or dehydrogenation. To reduce the resistance, that is, to make it n-type (n - type, n + After that, the oxide is made high-resistance and turned into i-type. The threshold voltage of the transistor using the nitride semiconductor layer is positive, and it is called a normally The off-state characteristic is shown. The gate voltage of the transistor used in the display device is as close to 0V as possible. It is preferable that the threshold voltage is positive. In an active matrix display device, The electrical characteristics of the transistors that make up the circuits are important, and these electrical characteristics determine the performance of the display device. In particular, the threshold voltage of a transistor is important. If the voltage is negative, current flows between the source and drain electrodes even if the gate voltage is 0V. This results in what is called a normally-on characteristic, making it difficult to control a circuit configured with this transistor. In addition, even if the threshold voltage is positive, in the case of a transistor whose absolute value is high, In some cases, the driving voltage is insufficient and switching operation itself is not possible. In the case of a transistor of this type, a channel is formed only when a positive voltage is applied to the gate. It is desirable to have a transistor in which the drain current flows out when the driving voltage is high. There are transistors in which a channel does not form unless the voltage is low, and transistors in which a channel forms even under negative voltage conditions. A transistor through which a drain current flows is unsuitable for use in a circuit.

[0025] The atmosphere during the temperature drop from the temperature at which dehydration or dehydrogenation was performed is the same as that during the temperature rise or heat treatment. For example, the atmosphere may be changed to a different atmosphere from that used when dehydration or dehydrogenation was performed. In the same furnace, high-purity oxygen gas, N2O gas, or ultra-high-purity gas are used without exposure to the atmosphere. Cooling can be achieved by filling the tank with dry air (dew point below -40°C, preferably below -60°C). can.

[0026] In addition, since transistors are easily damaged by static electricity, etc., On the other hand, it is preferable to provide a protection circuit for protecting the transistor in the pixel portion on the same substrate. The protection circuit is preferably formed using a nonlinear element using an oxide semiconductor layer.

[0027] A display device according to one embodiment of the present invention includes a driver circuit having a transistor for a driver circuit, and a display device having a driver circuit having a transistor for a driver circuit. A pixel portion having a pixel transistor and an operating circuit portion is manufactured. The manufacturing costs can be reduced. Effect of the Invention

[0028] By using an oxide semiconductor layer that has been subjected to heat treatment for dehydration or dehydrogenation, In addition, it is possible to manufacture a transistor having good electrical characteristics. By forming the star from a light-transmitting material, a display device with a high aperture ratio and excellent display characteristics can be obtained. In addition, in a display device having a pixel circuit and a driver circuit on the same substrate, In order to easily obtain the electrical characteristics required by the circuits, each of the circuits is divided into a transistor having a different structure. It can be formed of a transistor. [Brief description of the drawings]

[0029] [Figure 1] 1A to 1C are cross-sectional process views illustrating one embodiment of the present invention. [Diagram 2] 1A to 1C are cross-sectional process views illustrating one embodiment of the present invention. [Diagram 3] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 4] 1A and 1B are a cross-sectional view and a plan view illustrating one embodiment of the present invention. [Diagram 5] 1A and 1B are a cross-sectional view and a plan view illustrating one embodiment of the present invention. [Figure 6] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 7] FIG. 1 is a block diagram illustrating a display device. [Figure 8] 1A and 1B are a diagram illustrating a configuration of a signal line driver circuit and a timing chart illustrating the operation of the signal line driver circuit. [Figure 9]FIG. 1 is a circuit diagram showing a configuration of a shift register. [Figure 10] 1A and 1B are a diagram illustrating a configuration of a shift register and a timing chart illustrating the operation of the shift register; [Figure 11] FIG. 1 is a cross-sectional view illustrating a display device. [Figure 12] FIG. 1 is a plan view illustrating a display device. [Figure 13] FIG. 1 is a plan view illustrating a display device. [Figure 14] FIG. 2 is a diagram showing an equivalent circuit of a display device. [Figure 15] FIG. 1 is a cross-sectional view illustrating a display device. [Figure 16] FIG. 1 is a plan view illustrating a display device. [Figure 17] FIG. 1 is a plan view illustrating a display device. [Figure 18] FIG. 2 is a diagram showing an equivalent circuit of a display device. [Figure 19] FIG. 1 is a cross-sectional view illustrating a display device. [Figure 20] FIG. 1 is a plan view illustrating a display device. [Figure 21] FIG. 1 is a cross-sectional view illustrating a display device. [Figure 22] FIG. 1 is a plan view illustrating a display device. [Diagram 23] FIG. 1 is a cross-sectional view illustrating a display device. [Figure 24] FIG. 1 is a plan view illustrating a display device. [Diagram 25] FIG. [Figure 26] FIG. [Figure 27] FIG. [Figure 28] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0030] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and various modifications in form and details are possible by those skilled in the art. The present invention is not limited to the description of the following embodiments. In the drawings in this specification, parts having the same parts or similar functions are The same reference numerals will be used to denote the same parts, and their explanations may be omitted.

[0031] (Embodiment 1) In this embodiment mode, one mode of a display device and a manufacturing method thereof will be described in detail with reference to the drawings. FIG. 1(E) shows the transistors of the driver circuit, the transistors of the pixel section, and the 1 shows an example of a cross-sectional structure of a contact portion of a gate wiring (gate electrode).

[0032] The transistor 450 is a bottom-gate type transistor, also called a channel-etch type. The transistor 460 is a bottom-contact type (also called an inverted coplanar type). This is a Tom Gate type transistor.

[0033] The transistor 460 disposed in the pixel is formed on a substrate 400 having an insulating surface, and has a gate electrode the layer 451a, the gate insulating layer 402, the oxide semiconductor layer 454 including the channel formation region, The transistor 460 has a source electrode layer 455a and a drain electrode layer 455b. An oxide insulating layer 426 is provided in contact with the top surface and the side surfaces of the oxide semiconductor layer 454. do.

[0034] In addition, the transistor 460 arranged in the pixel is a transistor having a single gate structure. However, if necessary, a multi-gate structure having a plurality of channel formation regions may be used. A transistor having the above structure may be used.

[0035] Note that the oxide semiconductor layer 454 has a light-transmitting property and is transparent to part of the source electrode layer 455a and the drain electrode layer 455b. The oxide semiconductor layer 454 is formed so as to overlap with a part of the gate electrode layer 455b. The gate electrode layer 451a overlaps with the gate insulating layer 402 having a light-transmitting property therebetween. The channel formation region of the transistor 460 disposed in the oxide semiconductor layer 454 is , a side surface of the source electrode layer 455a and a side surface of the drain electrode layer 455b facing the side surface That is, the region sandwiched between the gate insulating layer 402 and the gate electrode layer 451a is in contact with the gate insulating layer 402 and overlaps with the gate electrode layer 451a. It is an area.

[0036] In order to realize a display device having a high aperture ratio, the source electrode layer of the transistor 460 A light-transmitting conductive film is used for the drain electrode layer 455a and the drain electrode layer 455b.

[0037] A light-transmitting conductive film is also used for a gate electrode layer 451a of the transistor 460.

[0038] The transistor 450 disposed in the driver circuit portion is formed on the substrate 400 having an insulating surface. , a gate electrode layer 421a, a gate insulating layer 402, an oxide semiconductor layer 403, and a source electrode layer 4 The oxide semiconductor layer 403 is made of a gate insulating layer 404 and a drain electrode layer 425a. At least a channel forming region 423, a high-resistance source region 424a, and a high-resistance drain region 424b are formed. In addition, the channel formation region 423, the source electrode layer 425a, and the drain electrode layer 424b are formed. A light-transmitting oxide insulating layer 427 and a protective insulating layer 428 are provided on the inner electrode layer 425b. It is being done.

[0039] In addition, the first region 424c and the second region 424b of the oxide semiconductor layer 403 overlap with the oxide insulating layer 426. The region 424d is in the same oxygen-excess state as the channel formation region 423, and is effective in reducing leakage current and The oxide insulating layer 426 serves to reduce parasitic capacitance. In the case where the first region 424c and the second region 424b of the oxide semiconductor layer 403 do not overlap with each other, Region 424d is not formed.

[0040] In the following, using Fig. 1(A), (B), (C), (D), and (E), The process for manufacturing the transistor 450 and the transistor 460 will be described.

[0041] First, a metal film is formed on a substrate 400 having an insulating surface, and then a first photolithography process is performed. The gate electrode layers 421a and 421b are formed by a process and an etching process. The gate electrode layer 421b corresponds to a gate wiring, but is referred to as a gate electrode layer for convenience.

[0042] The resist mask used in the photolithography process may be formed by an inkjet method. The inkjet method does not require a photomask, which reduces manufacturing costs. This can be done.

[0043] Metal films used for the gate electrode layers 421a and 421b include Al, Cr, Ta, Ti, M An element selected from o, W, or an alloy containing the above elements, or a combination of the above elements Examples of such a laminate include a laminated film in which the above-mentioned films are combined.

[0044] The substrate 400 may be made of, for example, aluminosilicate glass, aluminoborosilicate glass, or burr In addition, when the temperature of the subsequent heat treatment is high, It is advisable to use a material with a strain point of 730°C or higher.

[0045] Instead of a glass substrate, an insulating substrate such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. A substrate made of such a material may also be used.

[0046] In addition, an insulating layer serving as a base film is provided between the substrate 400 and the gate electrode layers 421a and 421b. The undercoat film has a function of preventing diffusion of impurity elements from the substrate 400. a single layer structure of a film selected from a silicon oxide film, a silicon nitride oxide film, and a silicon oxynitride film; can be formed by laminating a plurality of the above-mentioned films.

[0047] Next, a light-transmitting conductive film is formed to cover the gate electrode layers 421a and 421b, and then The gate electrode layers 451a and 45 The gate electrode layer 451b corresponds to a gate wiring layer, but is referred to as a gate It is written as a gate electrode layer. The transparent conductive film is made of a conductive material that is transparent to visible light, such as In--Sn -O series, In-Sn-Zn-O series, In-Al-Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn-O series, In-Zn-O series, Sn-Zn-O Metal oxides such as Al-Zn-O, In-O, Sn-O, and Zn-O are used. The thickness of the conductive film is appropriately selected within the range of 50 nm to 300 nm. In addition, when using a sputtering method, the conductive material is added with 2% by weight or more and 10% by weight or less of SiO2 Alternatively, the film may be formed using a target containing the above.

[0048] In this embodiment, in order to reduce the wiring resistance, a part of the gate wiring arranged in the pixel portion is It is formed from the same metal film as the gate electrode layers 421a and 421b.

[0049] Next, a gate insulating layer 402 is formed on the gate electrode layers 421a, 421b, 451a, and 451b. Form it.

[0050] For the gate insulating layer 402, an insulating film having light transmissivity such as a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer can be used, and it can be formed using a plasma CVD method, a sputtering method, etc. Further, the gate insulating layer 402 is not limited to a single layer of the above insulating film, and a laminate of different films may be used. For example, using silane (SiH4), oxygen, and nitrogen as the film-forming gas, a silicon oxynitride film can be formed by the plasma CVD method. The film thickness of the gate insulating layer 402 is set to 100 nm or more and 500 nm or less. In the case of a laminate, for example, a first gate insulating layer with a film thickness of 50 nm or more and 200 nm or less is formed, and a second gate insulating layer with a film thickness of 5 nm or more and 300 nm or less is formed on the first gate insulating layer. For the gate insulating layer 402, an insulating film having light transmissivity such as a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer can be used, and it can be formed using a plasma CVD method, a sputtering method, etc. Further, the gate insulating layer 402 is not limited to a single layer of the above insulating film, and a laminate of different films may be used. For example, using silane (SiH4), oxygen, and nitrogen as the film-forming gas, a silicon oxynitride film can be formed by the plasma CVD method. The film thickness of the gate insulating layer 402 is set to 100 nm or more and 500 nm or less. In the case of a laminate, for example, a first gate insulating layer with a film thickness of 50 nm or more and 200 nm or less is formed, and a second gate insulating layer with a film thickness of 5 nm or more and 300 nm or less is formed on the first gate insulating layer. For the gate insulating layer 402, an insulating film having light transmissivity such as a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer can be used, and it can be formed using a plasma CVD method, a sputtering method, etc. Further, the gate insulating layer 402 is not limited to a single layer of the above insulating film, and a laminate of different films may be used. For example, using silane (SiH4), oxygen, and nitrogen as the film-forming gas, a silicon oxynitride film can be formed by the plasma CVD method. The film thickness of the gate insulating layer 402 is set to 100 nm or more and 500 nm or less. In the case of a laminate, for example, a first gate insulating layer with a film thickness of 50 nm or more and 200 nm or less is formed, and a second gate insulating layer with a film thickness of 5 nm or more and 300 nm or less is formed on the first gate insulating layer. For the gate insulating layer 402, an insulating film having light transmissivity such as a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer can be used, and it can be formed using a plasma CVD method, a sputtering method, etc. Further, the gate insulating layer 402 is not limited to a single layer of the above insulating film, and a laminate of different films may be used. For example, using silane (SiH4), oxygen, and nitrogen as the film-forming gas, a silicon oxynitride film can be formed by the plasma CVD method. The film thickness of the gate insulating layer 402 is set to 100 nm or more and 500 nm or less. In the case of a laminate, for example, a first gate insulating layer with a film thickness of 50 nm or more and 200 nm or less is formed, and a second gate insulating layer with a film thickness of 5 nm or more and 300 nm or less is formed on the first gate insulating layer. For the gate insulating layer 402, an insulating film having light transmissivity such as a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer can be used, and it can be formed using a plasma CVD method, a sputtering method, etc. Further, the gate insulating layer 402 is not limited to a single layer of the above insulating film, and a laminate of different films may be used. For example, using silane (SiH4), oxygen, and nitrogen as the film-forming gas, a silicon oxynitride film can be formed by the plasma CVD method. The film thickness of the gate insulating layer 402 is set to 100 nm or more and 500 nm or less. In the case of a laminate, for example, a first gate insulating layer with a film thickness of 50 nm or more and 200 nm or less is formed, and a second gate insulating layer with a film thickness of 5 nm or more and 300 nm or less is formed on the first gate insulating layer. For the gate insulating layer 402, an insulating film having light transmissivity such as a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer can be used, and it can be formed using a plasma CVD method, a sputtering method, etc. Further, the gate insulating layer 402 is not limited to a single layer of the above insulating film, and a laminate of different films may be used. For example, using silane (SiH4), oxygen, and nitrogen as the film-forming gas, a silicon oxynitride film can be formed by the plasma CVD method. The film thickness of the gate insulating layer 402 is set to 100 nm or more and 500 nm or less. In the case of a laminate, for example, a first gate insulating layer with a film thickness of 50 nm or more and 200 nm or less is formed, and a second gate insulating layer with a film thickness of 5 nm or more and 300 nm or less is formed on the first gate insulating layer. For the gate insulating layer 402, an insulating film having light transmissivity such as a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer can be used, and it can be formed using a plasma CVD method, a sputtering method, etc. Further, the gate insulating layer 402 is not limited to a single layer of the above insulating film, and a laminate of different films may be used. For example, using silane (SiH4), oxygen, and nitrogen as the film-forming gas, a silicon oxynitride film can be formed by the plasma CVD method. The film thickness of the gate insulating layer 402 is set to 100 nm or more and 500 nm or less. In the case of a laminate, for example, a first gate insulating layer with a film thickness of 50 nm or more and 200 nm or less is formed, and a second gate insulating layer with a film thickness of 5 nm or more and 300 nm or less is formed on the first gate insulating layer. For the gate insulating layer 402, an insulating film having light transmissivity such as a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer can be used, and it can be formed using a plasma CVD method, a sputtering method, etc. Further, the gate insulating layer 402 is not limited to a single layer of the above insulating film, and a laminate of different films may be used. For example, using silane (SiH4), oxygen, and nitrogen as the film-forming gas, a silicon oxynitride film can be formed by the plasma CVD method. The film thickness of the gate insulating layer 402 is set to 100 nm or more and 500 nm or less. In the case of a laminate, for example, a first gate insulating layer with a film thickness of 50 nm or more and 200 nm or less is formed, and a second gate insulating layer with a film thickness of 5 nm or more and 300 nm or less is formed on the first gate insulating layer.

[0051] In this embodiment, silicon oxynitride (SiON (composition ratio N < O)) with a film thickness of 100 nm formed by the plasma CVD method is used for the gate insulating layer 402. In this embodiment, silicon oxynitride (SiON (composition ratio N < O)) with a film thickness of 100 nm formed by the plasma CVD method is used for the gate insulating layer 402.

[0052] Next, after forming a conductive film having light transmissivity on the gate insulating layer 402, a source electrode layer 455a and a drain electrode layer 455b are formed by a third photolithography process and an etching process (see FIG. 1(A)). Next, after forming a conductive film having light transmissivity on the gate insulating layer 402, a source electrode layer 455a and a drain electrode layer 455b are formed by a third photolithography process and an etching process (see FIG. 1(A)). Next, after forming a conductive film having light transmissivity on the gate insulating layer 402, a source electrode layer 455a and a drain electrode layer 455b are formed by a third photolithography process and an etching process (see FIG. 1(A)).

[0053] For the conductive film having light transmissivity, the same materials as those for the gate electrode layers 451a and 451b can be used. For the conductive film having light transmissivity, the same materials as those for the gate electrode layers 451a and 451b can be used.

[0054] Next, a contact hole that selectively etches the gate insulating layer 402 to reach the gate electrode layer 421b is formed by a fourth photolithography process and an etching process. Next, a contact hole that selectively etches the gate insulating layer 402 to reach the gate electrode layer 421b is formed by a fourth photolithography process and an etching process.

[0055] Next, a film having a thickness of 5 nm to 200 nm, preferably 10 nm or more, is deposited on the gate insulating layer 402. A light-transmitting oxide semiconductor film having a thickness of 20 nm or less is formed by a sputtering method. Even if heat treatment for dehydration or dehydrogenation is performed after the formation of the oxide semiconductor film, the oxide semiconductor film remains amorphous. In order to achieve a satisfactory state, the thickness of the oxide semiconductor film is preferably 50 nm or less. By making the film thin, crystallization can be suppressed when the film is subsequently subjected to heat treatment.

[0056] As oxide semiconductor films, there are four-component metal oxide films, such as In-Sn-Ga-Zn-O films and three-component metal oxide films. The In-Ga-Zn-O film, In-Sn-Zn-O film, and In-Al- Zn-O film, Sn-Ga-Zn-O film, Al-Ga-Zn-O film, Sn-Al-Zn-O films, and binary metal oxide films such as In-Zn-O films, Sn-Zn-O films, and Al-Zn-O films , Zn-Mg-O film, Sn-Mg-O film, In-Mg-O film, In-O film, Sn-O film In addition, an oxide semiconductor film such as a Zn-O film can be used. It may contain SiO2.

[0057] The oxide semiconductor film is InMO3(ZnO) m Use a thin film represented by (m>0) Here, M is one or more selected from Ga, Al, Mn and Co. Metal element. For example, M is Ga, Ga and Al, Ga and Mn, or Ga and Co, etc. InMO3(ZnO) m An oxide semiconductor film having a structure represented by (m>0) Among these, oxide semiconductors with a structure containing Ga as M are called In-Ga-Zn-O oxide semiconductors. The thin film is also called an In-Ga-Zn-O system non-single crystal film.

[0058] In this embodiment, an In-Ga-Zn-O based oxide semiconductor target is used as the oxide semiconductor film. A 15 nm thick In-Ga-Zn-O non-single crystal film was formed by sputtering using a do.

[0059] In-Ga-Zn-O non-single crystal film is made from In-Ga-Zn-O oxide semiconductor target (In2O3:Ga2O3:ZnO=1:1:1 [molar ratio] (i.e., In:Ga Zn=1:1:0.5 [atom ratio]) was used, and the distance between the substrate and the target was set at 1 00mm, pressure 0.6Pa, direct current (DC) power 0.5kW, oxygen (oxygen flow rate 100%) ) atmosphere. or In:Ga:Zn=1:1:2 [atom ratio]. The filling rate of these targets is 90% or more and 100% or less, preferably The filling rate is 95% or more and 99.9% or less. By using a metal oxide target with a high filling rate, Therefore, the formed oxide semiconductor film becomes a dense film.

[0060] There are two types of sputtering: RF sputtering, which uses a high-frequency power source for the sputtering power supply, and DC sputtering. There is also the pulsed DC sputtering method, which applies a pulsed bias. The DC sputtering method is mainly used to deposit insulating films, while the DC sputtering method is mainly used to deposit conductive films. It is used in.

[0061] In order to reduce the amount of dust generated during film formation and improve the uniformity of the film thickness distribution, a pulse It is preferred to perform the sputtering using a direct current (DC) power supply.

[0062] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The equipment can deposit layers of different materials in the same chamber, or multiple types of The above materials can be discharged simultaneously to form a film.

[0063] Also, a sputtering apparatus using a magnetron sputtering method equipped with a magnet mechanism inside the chamber and ECR sputtering using plasma generated by microwaves without glow discharge. There is a sputtering apparatus that uses this method.

[0064] In addition, the target material and the sputtering gas components are chemically reacted during the film formation to form a compound thin film. The reactive sputtering method forms a thin film, and the bias sputtering method applies a voltage to the substrate during film formation. There are also other methods such as the TA method.

[0065] Note that before the oxide semiconductor film is formed by a sputtering method, argon gas is introduced to the plasma The reverse sputtering is performed to generate a dummy mask, and the dust adhering to the surface of the gate insulating layer 402 is removed. In the reverse sputtering, an electric current is applied to the substrate side using an RF power source in an argon atmosphere. This is a method in which pressure is applied and ionized argon is bombarded onto the substrate to modify the surface. Instead of argon, nitrogen, helium, oxygen, or the like may be used.

[0066] In addition, before the formation of the oxide semiconductor film, an inert gas atmosphere (nitrogen, helium, neon, Heat treatment (400°C or higher but below the distortion point of the substrate) is performed under argon, etc., and gate insulation is performed. Impurities such as hydrogen and water contained within layer 402 may be removed.

[0067] Next, the oxide semiconductor film is divided into islands by a fifth photolithography step and an etching step. The oxide semiconductor layers are processed into island-shaped oxide semiconductor layers 403 and 453 (see FIG. 1B). The resist masks for forming the semiconductor layers 403 and 453 are formed by an ink-jet method. By using the inkjet method, the manufacturing cost can be reduced.

[0068] In this embodiment, the contact hole reaching the gate electrode layer 421b is formed by using an oxygen ion implantation method. Before the deposition of the nitride semiconductor film, a fourth photolithography step and an etching step are performed to form a gate. The contact hole is formed by selectively etching the insulating layer. Alternatively, the insulating layer 402 may be formed after the island-shaped oxide semiconductor layers 403 and 453 are formed. The oxide semiconductor layers 403 and 453 and the gate insulating layer 402 are adhered to the surfaces of the oxide semiconductor layers 403 and 453 and the gate insulating layer 402. It is preferable to remove resist residues and the like.

[0069] In addition, after an oxide semiconductor film is formed over the gate insulating layer, A contact hole is formed, and then the oxide semiconductor film is selectively etched to form an island-shaped oxide film. This may be a process for processing the semiconductor layers 403 and 453.

[0070] Next, the oxide semiconductor layers 403 and 453 are dehydrated or dehydrogenated. The temperature of the first heat treatment for hydrogenation is 400° C. or higher and lower than the distortion point of the substrate, preferably 42° C. If the temperature is 425°C or higher, the heat treatment time can be 1 hour or less. If the temperature is below 100°C, the heat treatment time should be longer than 1 hour.

[0071] Here, the substrate is placed in an electric furnace, which is a type of heat treatment device, and the oxide semiconductor layers 403 and 4 Heat treatment is performed on the oxide semiconductor layer 53 in a nitrogen atmosphere. From the heating temperature T at which 403 and 453 are dehydrated or dehydrogenated, Use the same furnace until the temperature is sufficient, specifically, until the temperature drops by 100°C or more below the heating temperature T. The mixture is cooled slowly under an atmosphere other than nitrogen. The atmosphere is not limited to nitrogen, and may be helium, neon, argon, etc. may also be used.

[0072] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain water or hydrogen. Or the purity of rare gases such as helium, neon, and argon is 6N (99.9999%) or more. , and preferably 7N (99.99999%) or more.

[0073] The oxide semiconductor layers 403 and 453 are crystallized by the first heat treatment and become a microcrystalline film or a polycrystalline film. In some cases, the oxide semiconductor layers 403 and 453 become crystalline films by the first heat treatment. This results in an oxygen-deficient structure, and the carrier concentration is 1×10 18 / cm 3 Since the resistance is higher than the do. The gate electrode layers 451a and 451b are also crystallized by the first heat treatment and become microcrystalline films. For example, the gate electrode layers 451a and 451b may be made of indium oxide. When a tin oxide alloy film is used, it is easily crystallized by the first heat treatment at 450°C for 1 hour. However, the gate electrode layers 451a and 451b are made of an indium oxide tin oxide alloy containing silicon oxide. When a film is used, crystallization is less likely to occur.

[0074] In addition, the first heat treatment of the oxide semiconductor layer is performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer. It can also be applied to a semiconductor film. In that case, a fifth photolithography process is performed after the first heat treatment. The filling process is carried out.

[0075] Next, a transparent insulating film was formed on the gate insulating layer 402 and the oxide semiconductor layers 403 and 453 by a sputtering method. Then, a sixth photolithography process is performed to form a photoresist insulating layer. A resist mask is formed, and an oxide insulating layer 426 is selectively formed by an etching process. Then, the resist mask is removed. At this stage, the periphery and side surfaces of the oxide semiconductor layers 403 and 453 are The oxide insulating layer 426 overlaps with the surface of the insulating film 422. By the etching process, a contact hole reaching the gate electrode layer 421b and a drain A contact hole reaching the electrode layer 455b is also formed (see FIG. 1C).

[0076] The oxide insulating layer 426 has a thickness of 1 nm or more. The method can be appropriately used to prevent the inclusion of impurities. The oxide insulating layer 426 is formed using a silicon oxide film by a deposition method.

[0077] The substrate temperature during film formation may be from room temperature to 300° C., and in this embodiment, it is set to 100° C. The silicon oxide film is formed by sputtering in a rare gas (typically argon) atmosphere. The treatment is carried out in an oxygen atmosphere or in an atmosphere of rare gas (typically argon) and oxygen. can be done.

[0078] The target may be a silicon oxide target or a silicon target. For example, when using a silicon target, sputtering is performed in an oxygen and rare gas atmosphere. Silicon oxide can be formed by the above. The oxide insulating layer formed in contact with the - As much impurities as possible It is preferable to use an inorganic insulating film that does not contain any inorganic substances and can block the intrusion of these substances from the outside. Typically, a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film, or an aluminum oxynitride film is used. For example, a tungsten film can be used.

[0079] In this embodiment, a boron-doped columnar polycrystalline silicon target (resistivity 0.01 Ωcm The distance between the substrate and the target (TS distance) was 89 mm, and the pressure was 0.4 Pa, direct current (DC) power 6 kW, oxygen (oxygen flow rate 100%) atmosphere, pulse The film is formed by DC sputtering to a thickness of 300 nm.

[0080] Next, the gate insulating layer 402, the oxide insulating layer 426, and the oxide semiconductor layers 403 and 453 After forming a metal film on the substrate, a resist mask is formed by a seventh photolithography process. Then, a source electrode layer 425a and a drain electrode layer 425b are formed by an etching process. A connection electrode layer 429 electrically connected to the gate electrode layer 421b and a drain electrode layer A connection electrode layer 452 that is electrically connected to 455b is also formed.

[0081] The metal film may be formed by a sputtering method, a vacuum deposition method (such as an electron beam deposition method), an arc discharge method, or the like. The metal film may be formed by electrolytic ion plating or spraying. An element selected from Ti, Mo, W, Al, Cr, Cu, Ta, or a material consisting of the above elements. The metal film is an alloy of the above elements or an alloy of the above elements. The present invention is not limited to a single layer of the same element, and a stack of different elements may be used. A titanium film (thickness 100 nm), an aluminum film (thickness 200 nm), and a titanium film (thickness 100 A three-layer metal film with a thickness of 1 nm is formed. A titanium nitride film can also be used instead of the titanium film. good.

[0082] In the etching step after the seventh photolithography step, the oxide semiconductor layer 4 It is necessary to selectively remove the metal film on the 03, 453. A non-aqueous etchant (e.g., ammonia / hydrogen peroxide solution (31% by weight hydrogen peroxide solution: 28% by weight ammonia) By using ammonia water:water ratio of 5:2:2), the metal film can be selectively removed and the In-Ga The oxide semiconductor layers 403 and 453 made of Zn—O-based oxide semiconductors can be left. Cut.

[0083] Note that a resist pattern for forming the source electrode layer 425a and the drain electrode layer 425b was used. The inkjet method may be used to form the inkjet head. By using the inkjet method, the manufacturing cost can be reduced. This can reduce the

[0084] Next, the oxide insulating layer 426, the source electrode layer 425a, the drain electrode layer 425b, and the connecting electrode A light-transmitting oxide insulating layer 427 is formed over the electrode layer 429 and the connection electrode layer 452 ( As the oxide insulating layer 427, a silicon oxide film, a silicon nitride oxide film, an alumina oxide film, or the like can be used. An aluminum film, an aluminum oxynitride film, or the like is used. The oxide insulating layer 427 is formed using a silicon oxide film formed by a CVD method.

[0085] Next, the mixture is heated in an inert gas atmosphere such as nitrogen gas at 200° C. to 400° C., preferably at 25 A second heat treatment is performed at 0° C. to 350° C. For example, the second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. Heat treatment is performed between 100 and 200°C.

[0086] In the second heat treatment, the oxide insulating layer 427, part of the oxide semiconductor layer 403, and the oxide insulating layer 427 are The insulating layer 426 and the oxide semiconductor layer 453 are heated in a state of contact with each other. The oxide semiconductor layers 403 and 453, which have been made to have low resistance by the above-mentioned method, are formed by insulating the oxide insulating layers 427 and 426. When oxygen is supplied, the material becomes oxygen-excessive, resulting in high resistance (i-type).

[0087] When the oxide semiconductor layer 403 is thinner than 15 nm, the oxide semiconductor layer 403 is In a region overlapping with the source electrode layer 425a and the drain electrode layer 425b made of a metal film, Oxygen in the oxide semiconductor region is easily transferred to the metal film side, and the oxide semiconductor region becomes n-type. When the thickness of the metal layer 403 is 15 nm or more and 50 nm or less, the vicinity of the interface between the metal film and the region n-type, but the lower part is i-type or n - It becomes a molded state.

[0088] In this embodiment, the second heat treatment is performed after the silicon oxide film is formed. Timing is not a problem if it is done after the silicon oxide film is formed, but it is limited to the time immediately after the silicon oxide film is formed. isn't it.

[0089] Next, a light-transmitting protective insulating layer 428 is formed over the oxide insulating layer 427 (FIG. 1E The protective insulating layer 428 may be formed of a silicon nitride film, a silicon nitride oxide film, or an aluminum nitride film. In this embodiment, a silicon nitride film formed by RF sputtering is used. A protective insulating layer 428 is formed.

[0090] Although not shown, a transparent insulating film is formed between the oxide insulating layer 427 and the protective insulating layer 428 in the pixel portion. A planarizing insulating layer having optical properties may be provided. The planarizing insulating layer may be made of an acrylic resin, a polyimide resin, or the like. Heat resistance of polyimide, benzocyclobutene resin, polyamide, or epoxy resin In addition to the above organic materials, low dielectric constant materials (lo wk materials), siloxane resin, PSG (phosphorus glass), BPSG (borophosphorus glass) ) can be used. Note that it is also possible to laminate multiple insulating layers made of these materials. good.

[0091] Through the above steps, a channel etch type transistor 450 and a bottom contact A bottom-contact transistor 460 can be fabricated. The transistor 460 is made of a light-transmitting material except for the connection electrode layer 452. Therefore, the aperture ratio can be improved.

[0092] The channel etch type transistor 450 is easy to form with a short channel length, and the driving circuit This is advantageous for forming transistors that require high-speed operation, such as a semiconductor device. All of the circuits formed in the above are formed as bottom contact type like transistor 460. It is possible to manufacture a display device capable of operating at a higher speed than the above.

[0093] In addition, a pixel electrode necessary for the display device is provided on a protective insulating layer 428 of the pixel portion, and a transistor 4 60. In this example, the drain electrode layer 452 is electrically connected to the drain electrode layer 453. The pixel electrode may include gate electrode layers 451a and 451b and a source electrode layer 455a. A light-transmitting conductive film similar to that of the drain electrode layer 455b can be used.

[0094] One embodiment of the present invention is a display device having a driver circuit and a pixel circuit on the same substrate. Each circuit is made up of transistors with different structures so that it is easy to obtain the electrical characteristics required by the As in this embodiment, the driver circuit includes a channel etch type transistor 4. 50, the use of a bottom-contact type transistor 460 in the pixel circuit Thus, a display device with excellent performance can be manufactured.

[0095] Note that this embodiment mode can be freely combined with other embodiment modes.

[0096] (Embodiment 2) In this embodiment mode, an example in which a manufacturing process of a transistor is partly different from that in Embodiment Mode 1 is shown in FIG. Figure 2 is the same as Figure 1 except for some differences in the process, so the same parts are marked with the same symbols. and detailed explanations of the same parts will be omitted.

[0097] First, according to the first embodiment, gate electrode layers 421a and 451a and gate insulating layer 421b are formed on a substrate. An edge layer 402 is formed, and a part of the edge layer 402 overlaps with the gate electrode layer 451a via the gate insulating layer 402. The source electrode layer 455a and the drain electrode layer 455b are formed. 02. An oxide semiconductor film is formed over the source electrode layer 455a and the drain electrode layer 455b. conduct.

[0098] Next, the oxide semiconductor film is dehydrated or dehydrogenated. The temperature of the heat treatment in step 1 is 400° C. or higher and lower than the distortion point of the substrate, preferably 425° C. or higher. If the temperature is 425℃ or higher, the heat treatment time can be 1 hour or less. The heat treatment time is longer than one hour. The substrate is placed in an electric furnace, and the oxide semiconductor film is subjected to heat treatment in a nitrogen atmosphere. After that, the oxide semiconductor film is not exposed to the air, and water or hydrogen is prevented from re-entering the oxide semiconductor film. In the same furnace, high-purity oxygen gas, high-purity NO gas, or ultra-dry air (dew point below -40℃) , preferably -60°C or less) is introduced to cool the system. It is preferable that hydrogen and the like are not included. Alternatively, oxygen gas or The purity of the NO gas is 6N (99.9999%) or more, preferably 7N (99.9999%). 9%) or more (i.e., impurity concentration in oxygen gas or N2O gas is 1 ppm or less, preferably It is preferable that the concentration of the ion exchange resin is 0.1 ppm or less.

[0099] After the first heat treatment for dehydration or dehydrogenation, the temperature is preferably 200° C. or higher and 400° C. or lower. Or heat treatment at a temperature between 200°C and 300°C in an oxygen gas or N2O gas atmosphere. The theory may also be carried out.

[0100] Through the above steps, the entire oxide semiconductor film becomes in an oxygen-excess state, and the oxide semiconductor In this embodiment, the oxide semiconductor film can be made to have a high resistance, that is, to be an i-type film. In the above example, the first heat treatment is performed immediately after the formation of the oxide semiconductor film. There is no particular limitation as long as it is a process subsequent to the film formation.

[0101] Next, a resist mask is formed by a photolithography process, and an acid is applied in an etching process. The nitride semiconductor film and the gate insulating layer 402 are selectively etched to form a gate electrode layer 421b. Then, the resist mask is removed (Figure 2(A)). reference).

[0102] Next, a resist mask is formed by a photolithography process, and an acid is applied in an etching process. The compound semiconductor film is selectively etched to form islands. The resist mask is then removed. Then, oxide semiconductor layers 404 and 405 are formed over the gate insulating layer 402 (see FIG. 2B). ).

[0103] Next, an oxide semiconductor layer 404 and an oxide insulating layer 405 are formed on the gate insulating layer 402 and the oxide semiconductor layers 404 and 405 by a sputtering method. After forming the insulating layer, a resist mask is formed by a photolithography process. Then, an oxide insulating layer 426 is formed by an etching process, and the resist mask is removed. At this stage, a region where the oxide semiconductor layers 404 and 405 overlap with the oxide insulating layer 426 is formed. This process also forms a contact hole reaching the gate electrode layer 421b and A contact hole reaching the inner electrode layer 455b is also formed (see FIG. 2C).

[0104] The oxide insulating layer contains moisture, hydrogen ions, and OH - It contains as few impurities as possible, and these are external It is advisable to use an inorganic insulating film that blocks the penetration of oxygen from the inside of the insulating film. A silicon oxide film, an aluminum oxide film, an aluminum oxynitride film, or the like can be used. can.

[0105] Next, the gate insulating layer 402, the oxide insulating layer 426, and the oxide semiconductor layers 404 and 405 A conductive oxide film and a metal film are laminated on the substrate. The metal films can be deposited continuously without being exposed to the air.

[0106] The oxide conductive film preferably contains zinc oxide as a component, and more preferably contains indium oxide. As such an oxide conductive film, zinc oxide, zinc oxide Examples of the zinc oxide include aluminum, zinc aluminum oxynitride, and zinc gallium oxide. In the embodiment, a zinc oxide film is used.

[0107] The metal film may be made of an element selected from the group consisting of Ti, Mo, W, Al, Cr, Cu, and Ta. Alternatively, an alloy containing the above elements or an alloy combining the above elements may be used. In addition, the metal film is not limited to a single layer of the above-mentioned elements, but may be a laminate of different elements. In this embodiment, a molybdenum film, an aluminum film, and a molybdenum film are stacked. A three-layer laminated film is used.

[0108] Next, a resist mask is formed by a photolithography process, and then an etching process is performed. The metal film is selectively etched to form a source electrode layer 445a, a drain electrode layer 445b, and a connection After the electrode layer 449 and the connection electrode layer 442 are formed, the resist mask is removed.

[0109] The resist stripper used to remove the resist mask is an alkaline solution. When a resist stripper is used, the zinc oxide film is selectively removed using the electrode layer as a mask. Therefore, the oxide conductive layer 446a in contact with the source electrode layer 445a, the drain An oxide conductive layer 446b is formed in contact with the gate electrode layer 445b.

[0110] Since the oxide semiconductor layer and the oxide conductive layer have different etching rates, The overlying oxide conductive layer can be removed in a time controlled manner.

[0111] After selectively etching the metal film, the resist mask is removed by oxygen ashing. Then, the source electrode layer 445a, the drain electrode layer 445b, the connection electrode layer 449, and the connection The zinc oxide film may be selectively etched using the electrode layer 442 as a mask.

[0112] An oxide conductive layer 446a provided between the source electrode layer 445a and the oxide semiconductor layer 404 The source region is provided between the drain electrode layer 445b and the oxide semiconductor layer 404. The oxide conductive layer 446b functions as a drain region. By providing the oxide semiconductor layer 404 and the oxide conductive layer 446b, The contact resistance between the drain electrode layer 445a and the drain electrode layer 445b can be reduced. Transistors with low resistance in the path can operate at high speeds, and the peripheral circuits (drive circuits) The frequency characteristics can be improved.

[0113] Molybdenum is a material that has a relatively high contact resistance with oxide semiconductors. Since it is difficult to oxidize compared to silicon, the effect of extracting oxygen from the oxide semiconductor layer is weak. This is because the contact interface of the conductor layer does not become n-type. The interposition of an oxide conductive layer between the metal electrode layer and the electrode is a very effective method for reducing the contact resistance. It will be an effective measure.

[0114] In the same process, an oxide conductive layer 448 is formed in contact with the connection electrode layer 449. An oxide conductive layer 447 is formed in contact with the oxide layer 442 (see FIG. 2D).

[0115] Next, in order to reduce the variation in the electrical characteristics of the transistors, the transistors are heated in an inert gas atmosphere, e.g. For example, the second heat treatment may be performed under a nitrogen gas atmosphere. It is preferable to perform the heating at a temperature of less than 350° C., for example, at 250° C. for 1 hour in a nitrogen atmosphere. Perform processing.

[0116] Note that oxygen is impregnated into or diffused into the oxide semiconductor layers 404 and 454 by the second heat treatment. The channel is formed by the impregnation or diffusion of oxygen into the oxide semiconductor layers 404 and 454. The formation area can be made highly resistive (i-type). This makes the electrical characteristics normal. In addition, the second heat treatment can be used to obtain a transistor that is turned off. Layers 446a, 446b, 447, and 448 may be crystallized to improve electrical conductivity. .

[0117] Then, an oxide insulating layer 426, the source electrode layer 445a, and the drain electrode layer 445b are formed on the oxide insulating layer 426. The oxide insulating layer 427 and the protective insulating layer 428 are formed (see FIG. 2(E)). The protective insulating layer 428 can be formed using a material and a manufacturing method similar to those in Embodiment 1. .

[0118] Through the above steps, the transistor 440 and the transistor 460 are manufactured over the same substrate. It is possible.

[0119] The transistor 440 disposed in the driving circuit section is formed by forming a gate on a substrate 400 having an insulating surface. a gate electrode layer 421a, a gate insulating layer 402, an oxide semiconductor layer 404, and an oxide conductive layer 446a , 446b, a source electrode layer 445a, and a drain electrode layer 445b. The oxide semiconductor layer 404 includes at least a channel formation region 443 and a high-resistance source region 44 The source region 443 and the drain region 444b are electrically connected to the channel forming region 443. An oxide insulating layer 427 and a protective insulating layer 428 are formed on the source electrode layer 445a and the drain electrode layer 445b. A layer 428 is provided.

[0120] Between the high-resistance source region 444a and the source electrode layer 445a, a region that functions as a source region is provided. The oxide conductive layer 446a is provided, and the high-resistance drain region 444b and the drain electrode layer 445 are provided. The oxide conductive layer 446b functioning as a drain region is provided between the first and second conductive layers 446a and 446b. We are working to reduce this.

[0121] In addition, the first region 444c and the second region 444b of the oxide semiconductor layer 404 overlap with the oxide insulating layer 426. The region 444d is in the same oxygen-excess state as the channel formation region 443, and is effective in reducing leakage current and The oxide insulating layer 426 also serves to reduce parasitic capacitance. In the case where the first region 444c and the second region 444b of the oxide semiconductor layer 404 do not overlap with each other, Region 444d is not formed.

[0122] Note that this embodiment mode can be freely combined with other embodiment modes.

[0123] (Embodiment 3) In this embodiment, the active matrix substrate shown in Embodiment 1 or 2 is used, An example of a liquid crystal display device will be described.

[0124] FIG. 3 shows an example of the cross-sectional structure of an active matrix substrate.

[0125] In the first and second embodiments, the transistors of the driver circuit section and the transistors of the pixel section are formed on the same substrate. In the present embodiment, the contact portion of the gate wiring (gate electrode) is not shown. In addition, a storage capacitor and an intersection of a gate line and a source line are also illustrated and described.

[0126] The capacitor, the gate wiring, and the source wiring are formed by the same manufacturing process as that shown in the first or second embodiment. This can be achieved without increasing the number of photomasks or the number of processes. In addition, in the display area of ​​the pixel section, the gate wiring, the source wiring, and The capacitance wiring layer is formed of a conductive film having light transmitting properties, thereby achieving a high aperture ratio. In addition, the source wiring layer in the non-display area uses metal wiring to reduce wiring resistance. It is possible.

[0127] In FIG. 3, a transistor 450 is provided in a driver circuit portion. The transistor 460 electrically connected to the electrode layer 457 is a transistor provided in a pixel portion. It is Sta.

[0128] In this embodiment, the transistor 460 formed above the substrate 400 is The same structure as transistor 460 or 460 is used.

[0129] The gate electrode layer 451a of the transistor 460 is formed of the same material having a light-transmitting property and in the same process. The formed capacitance wiring layer 430 is connected to the capacitance electrode 43 via the gate insulating layer 402 which serves as a dielectric. The capacitor electrode 431 overlaps with the source electrode 431 of the transistor 460. The light-transmitting material and the process are the same as those of the source electrode layer 455a and the drain electrode layer 455b. Therefore, the transistor 460 is transparent and has a storage capacity. Since the film also has light-transmitting properties, the aperture ratio can be improved.

[0130] It is important for the storage capacitor to have light transmittance in order to improve the aperture ratio. In the following small LCD panels, a high aperture ratio can be achieved even with miniaturized pixel dimensions. In addition, a light-transmitting film can be used as a component of the transistor 460 and the storage capacitor. By using this, a wide viewing angle can be achieved, and high performance can be achieved even if one pixel is divided into multiple sub-pixels. For example, one pixel can have 2 to 4 sub-pixels and a Even when the transistor has a capacitance, the transistor has a light-transmitting property and Since each of the storage capacitors also has light-transmitting properties, the aperture ratio can be improved.

[0131] The storage capacitor is provided below the pixel electrode layer 457, and the capacitor electrode 431 is disposed below the pixel electrode layer 4 57 and electrically connected thereto.

[0132] In this embodiment, a capacitance wiring layer 430, a gate insulating layer 402, and a capacitance electrode 431 are used. However, the structure for forming the storage capacitor is not particularly limited. For example, a capacitance wiring layer may not be provided, and a part of the gate wiring of adjacent pixels may be used as the capacitance wiring layer. In addition to the gate insulating layer, a protective insulating layer, a planarizing insulating layer, etc. may be used in the configuration of the pixel portion. An insulating layer that can be used as the dielectric may be used.

[0133] In addition, the gate wiring layer, the source wiring layer, and the capacitance wiring layer are provided in multiple lines according to the pixel density. In addition, in the terminal section, a first terminal electrode having the same potential as the gate wiring, a source A second terminal electrode having the same potential as the wiring, a third terminal electrode having the same potential as the capacitance wiring layer, etc. are arranged in multiple rows. The number of each terminal electrode may be any number. The implementer should make the appropriate decision.

[0134] In the gate wiring contact portion, the gate electrode layer 421b is formed of a low resistance metal material. The gate electrode layer 421b is formed through a contact hole that reaches the gate wiring. 429. The insulating layer 426 is electrically connected to the connection electrode layer 429 via the insulating layer 426.

[0135] The gate electrode layer of the transistor 450 in the driver circuit is a conductor provided above the oxide semiconductor layer. The insulating layer 417 may be electrically connected to the insulating layer 417.

[0136] In addition, in order to reduce parasitic capacitance at the wiring intersections as shown in FIG. Between the gate insulating layer 402 and the source wiring layer 422, a gate insulating layer 402 and an oxide insulating layer 426 are provided. In addition, FIG. 3 shows an example in which the gate wiring layer 421c is a metal film. However, the same light-transmitting conductive film as the gate electrode layer 451a of the transistor 460 was used. It can also be formed.

[0137] In addition, when an active matrix type liquid crystal display device is manufactured, A liquid crystal layer is provided between the substrate and the opposing substrate on which the opposing electrode is provided, and an active matrix The substrate and the counter substrate are fixed together. The counter electrode is electrically connected to the counter substrate. A common electrode is provided on the active matrix substrate, and a fourth terminal is electrically connected to the common electrode. The fourth terminal electrode is provided on the terminal portion. The fourth terminal electrode is connected to the common electrode at a fixed potential, for example, GND, 0 The fourth terminal electrode is a terminal for setting the pixel electrode layer 457 and the like. The insulating layer may be made of a material having the following properties:

[0138] In addition, gate electrodes, source electrodes, drain electrodes, pixel electrodes, other electrodes, and various wirings If the same material is used for the layers, the sputtering target and manufacturing equipment can be shared. In addition, the cost of the materials and the cost of the etchant and etching gas used during etching Costs can be reduced, resulting in reduced manufacturing costs.

[0139] In the structure of FIG. 3, when a photosensitive resin material is used as the planarization insulating layer 456, The step of forming a resist mask can be omitted.

[0140] Note that this embodiment mode can be freely combined with other embodiment modes.

[0141] (Embodiment 4) In this embodiment, an example of a structure of a terminal portion provided over the same substrate as a transistor will be described. The following description will be given with reference to Fig. 4. In Fig. 4, the same parts as in Fig. 3 are denoted by the same reference numerals. do.

[0142] FIG. 4(A1) and FIG. 4(A2) are a cross-sectional view and a top view, respectively, of a gate line terminal portion. FIG. 4(A1) corresponds to a cross-sectional view taken along line C1-C2 in FIG. 4(A2).

[0143] In FIG. 4(A1), a conductive layer is formed on a stack of an oxide insulating layer 427 and a protective insulating layer 428. The conductive layer 415 is a terminal electrode for connection that functions as an input terminal. In the terminal portion, the first terminal 411 is made of the same material as the gate wiring layer 421c. The connection electrode layer 412 formed of the same material as the source wiring layer 422 and the gate insulating layer 402 The conductive layer 415 overlaps with the pixel electrode layer 457 and is electrically connected to the pixel electrode layer 457 through a conductive layer 415. They can be formed using the same material having the same light-transmitting property and in the same process.

[0144] FIG. 4(B1) and FIG. 4(B2) are a cross-sectional view and a top view of a source wiring terminal portion, respectively. FIG. 4(B1) is a cross-sectional view taken along line C3-C4 in FIG. 4(B2). Corresponding to the figure.

[0145] In FIG. 4B1, a conductive layer is formed over a stack of an oxide insulating layer 427 and a protective insulating layer 428. The conductive layer 418 is a terminal electrode for connection that functions as an input terminal. In the terminal portion, the electrode layer 416 made of the same material as the gate wiring layer 421c is The second terminal 414 is overlapped with the gate insulating layer 402 below the second terminal 414 which is electrically connected to the source wiring. The electrode layer 416 is not electrically connected to the second terminal 414. If the potential is set to a different potential from that of terminal 414 of 2, for example, floating, GND, 0V, etc., The capacitance can be used as a noise countermeasure or a static electricity countermeasure. The second terminal 414 is electrically connected to a conductive layer 418. The conductive layer 418 is a pixel electrode layer. It can be formed using the same material having the same light-transmitting property as 457 and in the same process.

[0146] A plurality of gate lines, source lines, common potential lines, and power supply lines are provided according to the pixel density. In addition, in the terminal section, a first terminal having the same potential as the gate wiring, a source wiring, a second terminal at the same potential as the line; a third terminal at the same potential as the power supply line; and a fourth terminal at the same potential as the common potential line. The number of each terminal can be set to any number. This is acceptable, and the implementer can make the appropriate decision.

[0147] Note that this embodiment mode can be freely combined with other embodiment modes.

[0148] (Embodiment 5) In this embodiment mode, an example of a structure and a manufacturing method of a liquid crystal display device will be described.

[0149] In this embodiment mode, a display device including a liquid crystal element (also called a liquid crystal display element) will be described. However, this is not limited to electronic ink and other displays whose contrast changes due to electrical effects. A medium can also be applied.

[0150] In this specification, the display device includes a panel in which a display element is sealed, and the The display device includes an integrated circuit (IC) for operating the panel. The underlying device substrate is provided at each pixel with means for supplying a current to the display element. Also, connectors, such as FPC (Flexible printed circuit ) or TAB (Tape Automated Bonding) tape or T Module with CP (Tape Carrier Package) attached, TA Modules with printed wiring boards on the ends of B tape or TCP, or CO All modules with ICs directly mounted using the G (Chip On Glass) method are also displayed. This is included in the display device.

[0151] The appearance and cross section of a liquid crystal display panel, which is one form of display device, will be explained with reference to FIG. 5A1 and 5A2 show transistors 4010 and 4011 and a liquid crystal element 40 13 is sealed between a first substrate 4001 and a second substrate 4006 by a sealant 4005. FIG. 5(B) is a plan view of the panel in MN in FIG. 5(A1) and (A2). This corresponds to a cross-sectional view in

[0152] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In this manner, a sealant 4005 is provided. A second substrate 4006 is provided on the path 4004. The scanning line driver circuit 4004 is a circuit board including a first substrate 4001, a sealant 4005, and a second substrate 400. 6, the liquid crystal layer 4008 is sealed. In an area different from the area surrounded by the insulating material 4005, a single A signal line driver circuit 4003 formed of a crystalline semiconductor film or a polycrystalline semiconductor film is mounted. do.

[0153] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG method, a wire The ear bonding method, TAB method, etc. can be used. This is an example of mounting the signal line driver circuit 4003 by the G method, and FIG. 5(A2) is an example of mounting the signal line driver circuit 4003 by the TAB method. This is an example in which a signal line driver circuit 4003 is implemented.

[0154] In addition, a pixel portion 4002 and a scanning line driver circuit 4004 provided on a first substrate 4001 are In FIG. 5B, the transistor included in the pixel portion 4002 is 4010 and a transistor 4011 included in the scanning line driver circuit 4004. Insulating layers 4041, 4020, and 4021 are provided on the transistors 4010 and 4011. It is being done.

[0155] The transistors 4010 and 4011 each include the oxide semiconductor layer described in Embodiment 1 or 2. A highly reliable transistor including the transistor 40 for the driving circuit can be applied. As the transistor 11, the transistor 450 shown in the first or second embodiment, The transistor 4010 can be the transistor 460 described in Embodiment 1 or 2. In this embodiment, the transistors 4010 and 4011 are n-channel transistors. It's Jista.

[0156] The oxide semiconductor layer of the transistor 4011 for the driver circuit is formed over the insulating layer 4021. A conductive layer 4040 is provided in a position overlapping the panel formation region. By providing the transistor 4011 in a position overlapping with the channel formation region of the semiconductor layer, In addition, the conductive layer 4040 can reduce the amount of change in the threshold voltage. The gate electrode of the second gate electrode may be the same as or different from the gate electrode of the transistor 4011. The potential of the conductive layer 4040 can be set to GND, 0 V, or It may be in a floating state.

[0157] In addition, a pixel electrode 4030 of the liquid crystal element 4013 is electrically connected to the transistor 4010. The counter electrode 4031 of the liquid crystal element 4013 is connected to the second substrate 4006. The pixel electrode 4030, the counter electrode 4031, and the liquid crystal layer 4008 are overlapped. The portion where the pixel electrode 4030 and the counter electrode 4031 are disposed corresponds to the liquid crystal element 4013. Insulating layers 4032 and 4033 functioning as alignment films are provided on the substrates 4031 and 4032, respectively.

[0158] The first substrate 4001 and the second substrate 4006 may be light-transmitting substrates. Glass, ceramics, and plastics can be used. , FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film or acrylic resin film Room can be used.

[0159] Also, 4035 is a columnar spacer obtained by selectively etching the insulating layer. In order to control the distance (cell gap) between the pixel electrode 4030 and the counter electrode 4031, It should be noted that a spherical spacer may also be used.

[0160] The counter electrode 4031 is a common potential line provided on the same substrate as the transistor 4010. The common connection portion is electrically connected to the pair of substrates via the conductive particles disposed between the pair of substrates. The counter electrode 4031 and the common potential line can be electrically connected to each other. is contained in the sealing material 4005 .

[0161] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase is expressed only in a narrow temperature range, so the liquid crystal layer 4008 When used in liquid crystal display, 5% by weight or more of chiral agent is mixed to improve the temperature range. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent is preferably a composition comprising: The response speed is short at 1 msec or less, and since it is optically isotropic, no alignment treatment is required. It has the characteristic of having small angle dependence.

[0162] In the transistor 4011, an insulating layer 4041 is formed in contact with an oxide semiconductor layer. The insulating layer 4041 is formed using a material and a method similar to those of the oxide insulating layer 427 described in Embodiment 1. In this embodiment, a silicon oxide film formed by sputtering is used.

[0163] In addition, a protective insulating layer 4020 is formed on the insulating layer 4041. The protective insulating layer 428 may be formed using a material and a method similar to those of the protective insulating layer 428 described in Embodiment 1. As the protective insulating layer 4020, a silicon nitride film formed by a plasma CVD method is used.

[0164] In addition, an insulating layer 4021 is formed as a planarizing insulating layer. Resins such as fluororesins, polyimides, benzocyclobutene resins, polyamides, and epoxy resins. In addition to the above organic materials, low dielectric constant materials ( low-k materials), siloxane resin, PSG (phosphorus glass), BPSG (phosphorus boron gas) In addition, multiple insulating layers made of these materials can be laminated. The insulating layer 4021 may be formed by performing a process similar to that described above.

[0165] Siloxane-based resin is a type of Si-OS formed using siloxane-based materials as starting materials. The substituents of the siloxane resin include organic groups (e.g., arylene bonds). Alternatively, the organic group may have a fluoro group. It's fine if you're there.

[0166] The method for forming the insulating layer 4021 is not particularly limited, and may be sputtering, SOG, or sintering depending on the material. Pin coat, dip, spray coating, inkjet, screen printing, offset printing Also, a doctor knife, a roll coater, a curtain coater, etc. can be used. The insulating layer 4021 can be formed by using a knife coater or the like. By combining this with annealing, it is possible to reduce the number of steps.

[0167] The pixel electrode 4030 and the counter electrode 4031 are made of indium oxide containing tungsten oxide, Indium zinc oxide with tungsten oxide, indium oxide with titanium oxide, Indium tin oxide containing titanium, indium tin oxide (hereinafter referred to as ITO), indium Conductive materials with light-transmitting properties such as indium zinc oxide and indium tin oxide doped with silicon oxide Materials can be used.

[0168] The pixel electrode 4030 and the counter electrode 4031 are made of a conductive polymer. The conductive composition may be used to form the conductive layer. The pixel electrode has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 550 nm. It is preferable that the resistance of the conductive polymer contained in the conductive composition is 70% or more. It is preferable that the electrical conductivity be 0.1 Ω·cm or less.

[0169] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0170] In addition, a signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel portion Various signals and potentials are applied to 4002 through FPC 4018.

[0171] The connection terminal electrode 4015 is formed of the same conductive film as the pixel electrode 4030, and the terminal electrode 4016 The source electrode layer and the drain electrode layer of the transistor 4011 are formed using the same conductive film. There are.

[0172] The connection terminal electrode 4015 is connected to a terminal of the FPC 4018 via an anisotropic conductive film 4019. are electrically connected.

[0173] In FIG. 5, a signal line driver circuit 4003 is formed separately and mounted on a first substrate 4001. The embodiment is not limited to this configuration. Alternatively, only a part of the signal line driver circuit or a part of the scanning line driver circuit may be separately formed. It may be implemented.

[0174] FIG. 6 shows a transistor substrate 2600 fabricated by the fabrication method disclosed herein. As the display device, an example of a liquid crystal display module is shown.

[0175] A transistor substrate 2600 and an opposing substrate 2601 are fixed with a sealing material 2602. A pixel portion 2603 including a transistor or the like, a display element 2604 including a liquid crystal layer, and a coloring layer 26 05 is provided to form the display area.

[0176] The colored layer 2605 is necessary for color display. In the case of the RGB method, it is necessary to provide red, green, A colored layer corresponding to each color of blue is provided for each pixel. On the outer sides of the counter substrate 2601, polarizing plates 2606 and 2607 and a diffusion plate 2613 are disposed. is.

[0177] The light source is composed of a cold cathode fluorescent lamp 2610 and a reflector 2611. External circuits such as control circuits and power circuits are built into the flexible wiring board 2. 609 to the wiring circuit section 2608 of the transistor substrate 2600. A retardation plate may be provided between the plate and the liquid crystal layer.

[0178] The LCD module is available in TN (Twisted Nematic) mode, IPS (In-plane Switching) mode, n-Plane-Switching mode, FFS (Fringe Field Switching) switching mode, MVA (Multi-domain Vertical A alignment) mode, PVA(Patterned Vertical Alignment) mode nment) mode, ASM(Axially Symmetric aligned Micro-cell mode, OCB (Optical Compensated B) irefringence mode, FLC (Ferroelectric Liqui d Crystal) mode, AFLC (AntiFerroelectric Liq. uid Crystal) mode can be used.

[0179] By the above steps, a liquid crystal display panel having high reliability as a display device can be manufactured. .

[0180] Note that this embodiment mode can be freely combined with other embodiment modes.

[0181] (Embodiment 6) In this embodiment, a driver circuit and a pixel portion including transistors formed on the same substrate are An example of how the above is operated will be described.

[0182] In this embodiment mode, a transistor is manufactured on the same substrate by the method for manufacturing the transistor according to the first embodiment mode. A pixel portion and a driver circuit portion are formed in the same region. Note that the transistor described in Embodiment 1 is an n-channel transistor. The driving circuit section is composed of only n-channel transistors. Only some circuits can do this.

[0183] An example of a block diagram of an active matrix display device is shown in FIG. On the plate 5300, a pixel section 5301, a first scanning line driver circuit 5302, a second scanning line driver A circuit 5303 and a signal line driver circuit 5304 are provided. A number of signal lines are arranged extending from a signal line driver circuit 5304, and a number of scanning lines are arranged as a first scanning line. The first scanning line driver circuit 5302 and the second scanning line driver circuit 5303 are arranged to extend therefrom. At the intersections of the scanning lines and the signal lines, pixels each having a display element are arranged in a matrix. The display device substrate 5300 is mounted on a flexible printed circuit board (FPC). A timing control circuit 5305 (controller 5306) is connected to the timing control circuit 5305 via a connection part such as a The power supply is connected to a power amplifier (also called a controller or control IC).

[0184] The first scanning line driver circuit 5302, the second scanning line driver circuit 5303, and The signal line driver circuit 5304 is formed over the same substrate 5300 as the pixel portion 5301. Therefore, the number of externally provided parts such as drive circuits can be reduced, leading to cost reduction. In addition, the number of connections (FPC, etc.) between the substrate 5300 and the external drive circuit can be reduced. This makes it possible to improve reliability and yield.

[0185] The timing control circuit 5305 controls the first scanning line driver circuit 5302 to Start signal for the scanning line driving circuit (GSP1), clock signal for the scanning line driving circuit (GCLK 1) and the like. The second scanning line driver circuit 5303 is supplied with the second scanning line driver Circuit start signal (GSP2) (also called start pulse), clock for scanning line driver circuit It supplies the clock signal (GCLK2), etc.

[0186] A start signal for the signal line driver circuit (SSP), Clock signal for signal line driver circuit (SCLK), data for video signal (DATA) (simply The clock signals (CLK, CLKD, CLKF, etc.) are also supplied. The clock signal may be multiple clock signals with different periods, or an inverted clock signal (C KB) may be supplied together with the first scanning line driver circuit 5302. Alternatively, one of the second scanning line driver circuits 5303 can be omitted.

[0187] In FIG. 7B, circuits with low driving frequencies (for example, the first scanning line driver circuit 5302, the second The scanning line driver circuit 5303) is formed on the same substrate 5300 as the pixel portion 5301, and the signal line driver The circuit 5304 is formed on a substrate different from that of the pixel portion 5301. This structure allows the pixel section and the transistor to be mounted on the same substrate even if they use transistors with relatively low field effect mobility. This allows the driver circuit to be configured as a part of the driver circuit. This reduces costs and improves yields. It is possible to achieve this.

[0188] Next, an example of the configuration and operation of a signal line driver circuit configured with n-channel transistors will be described. This will be described with reference to FIG. 8(A) and FIG. 8(B).

[0189] The signal line driver circuit includes a shift register 5601 and a switching circuit 5602 . The switching circuit 5602 includes switching circuits 5602_1 to 5602_N (N is a natural number). In addition, each of the switching circuits 5602_1 to 5602_N is configured as a transistor. It is composed of transistors 5603_1 to 5603_k (k is a natural number). The transistors 5603_1 to 5603_k are n-channel transistors.

[0190] The connection relationship of the signal line driver circuit will be described using the switching circuit 5602_1 as an example. The first terminals of the transistors 5603_1 to 5603_k are connected to the wirings 5604_1 to 5604_k, respectively. The second terminals of the transistors 5603_1 to 5603_k are connected to , and are connected to signal lines S1 to Sk. The gates of the transistors 5603_1 to 5603_k are , and is connected to wiring 5605_1.

[0191] The shift register 5601 sequentially outputs H level (H signal) to the wirings 5605_1 to 5605_N. , or high power supply potential level), and the switching circuits 5602_1 to 56 It has the function of selecting 02_N in sequence.

[0192] The switching circuit 5602_1 includes wirings 5604_1 to 5604_k and signal lines S1 to Sk. A function of controlling the conduction state (conduction between the first terminal and the second terminal) with the wiring 5604_ The switches have a function of controlling whether or not potentials of 1 to 5604_k are supplied to the signal lines S1 to Sk. In this way, the switching circuit 5602_1 has a function as a selector. The transistors 5603_1 to 5603_k are connected to the wirings 5604_1 to 5604_k, respectively. A function of controlling the conduction state between the wirings S1 to Sk, that is, the wirings 5604_1 to 5604_k. The transistor 5603_1 has a function of supplying a potential to the signal lines S1 to Sk. . . 5603_k each have a function as a switch.

[0193] In addition, the wirings 5604_1 to 5604_k each carry video signal data (DATA). The video signal data (DATA) is analog data corresponding to the image information or image signal. Often a logged signal.

[0194] Next, the operation of the signal line driver circuit in FIG. 8(A) will be described with reference to the timing chart in FIG. 8(B). 8B, signals Sout_1 to Sout_N and a signal Vda An example of signals Sout_1 to Sout_N is shown. 5601. The signals Vdata_1 to Vdata_k are an example of an output signal of the soft register 5601. , are examples of signals input to the wirings 5604_1 to 5604_k. One operation period of the drive circuit corresponds to one gate selection period in the display device. As an example, the period is divided into periods T1 to TN. This is a period for writing video signal data (DATA) to pixels belonging to a selected row.

[0195] In the drawings of this embodiment, the distortion of signal waveforms is exaggerated for clarity. Therefore, the scale is not necessarily limited to that.

[0196] During the period T1 to the period TN, the shift register 5601 outputs an H-level signal to the wiring 560 For example, in the period T1, the shift registers 5 The transistor 601 outputs a high-level signal to the wiring 5605_1. 603_1 to 5603_k are turned on, and wiring 5604_1 to 5604_k and signal line S 1 to Sk are in a conductive state. (S1) to Data(Sk) are input. Data(S1) to Data(Sk) are Each of the pixels belonging to the selected row is supplied with a corresponding one of the transistors 5603_1 to 5603_k. That is, the signals are written to the pixels in the first to kth columns. The video signal data (DATA) is written to the pixels in the selected row in order of k columns. .

[0197] As described above, video signal data (DATA) is written to the pixels in multiple columns. This allows the number of video signal data (DATA) or wiring to be reduced. This reduces the number of connections to external circuits. Also, the video signal is transmitted in multiple columns. By writing to the pixel, the writing time can be increased, and the writing of the video signal This can prevent insufficient filling.

[0198] The shift register 5601 and the switching circuit 5602 are the same as those in the first embodiment. Alternatively, a circuit configured with the transistors shown in FIG. 2 can be used. In this case, All the transistors in the soft resistor 5601 are made of transistors of the same conductivity type. This can be done.

[0199] Next, the configuration of the scanning line driver circuit will be described. The scanning line driver circuit has a shift register. In some cases, a level shifter, a buffer, etc. may be included. In the operation circuit, a clock signal (CLK) and a start pulse signal (S P) is input to generate a selection signal. The generated selection signal is buffered The signal is buffered and amplified at the 1st line and supplied to the corresponding scanning line. The gate electrodes of the transistors are connected. must be turned on at the same time, so the buffer must be capable of passing a large current. is used.

[0200] Regarding one form of a shift register used as a part of a scanning line driver circuit and / or a signal line driver circuit, This will be described with reference to FIG. 9 and FIG.

[0201] The shift register includes a first pulse output circuit 10_1 to an N-th pulse output circuit 10_N ( N is a natural number equal to or greater than 3) (see FIG. 9(A)). The first pulse of the shift register The output circuit 10_1 to the N-th pulse output circuit 10_N are connected to a first clock signal line 11. A clock signal CK1 is input via the second wiring 12, a second clock signal CK2 is input via the third wiring 13, and A third clock signal CK3 is supplied through the third wiring 14, and a fourth clock signal CK4 is supplied through the fourth wiring 14. .

[0202] In addition, in the first pulse output circuit 10_1, a start pulse SP1 from the fifth wiring 15 (first start pulse) is input. In the nth stage (n is a natural number between 2 and N), the signal from the previous stage pulse output circuit (previous stage signal The number OUT(n-1) is input.

[0203] In addition, in the first pulse output circuit 10_1, the third pulse output circuit 10_3, which is two stages behind, Similarly, in the n-th pulse output circuit 10_n in the second stage or later, The signal from the (n+2)th pulse output circuit 10_(n+2) of the stage (n+2) (n+2) of the next stage signal OUT(n+ 2) is entered.

[0204] Therefore, the pulse output circuit of each stage outputs the pulse to the pulse output circuit of the next stage and / or the previous stage. a first output signal OUT(1)(SR) to OUT(N)(SR) for outputting to another circuit; The second output signals OUT(1) to OUT(N) are output, which are electrically input to the As shown in FIG. 9A, the last two stages of the shift register are connected to the rear stage signal OUT Since (n+2) is not input, for example, the second start pulse SP2 and the third The start pulse SP3 may be input to each of the first and second inputs.

[0205] The clock signal (CK) goes between H and L levels (L signal, low power supply potential) at regular intervals. Here, the first clock signal (CK1) to the second clock signal (CK2) are The four clock signals (CK4) are delayed by 1 / 4 of a period in sequence (i.e., 90 degrees from each other). In this embodiment, the first clock signal (CK1) to the fourth clock signal (CK2) are The clock signal (CK4) is used to control the driving of the pulse output circuit. The signal may be called GCK or SCK depending on the drive circuit to which it is input. I will explain as K.

[0206] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are connected to the first wiring 11 to The fourth wiring 14 is electrically connected to the first wiring 14. For example, in FIG. The first pulse output circuit 10_1 has a first input terminal 21 electrically connected to a first wiring 11. The second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal 23 is The second pulse output circuit 10_2 is electrically connected to the wiring 13 of the first The input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 is electrically connected to the third wiring The third input terminal 23 is electrically connected to the fourth wiring 14. do.

[0207] Each of the first pulse output circuit 10_1 to the N-th pulse output circuit 10_N has a first input terminal a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal The input terminal 25, the first output terminal 26, and the second output terminal 27 (see FIG. 9B) ).

[0208] In the first pulse output circuit 10_1, a first clock signal CK is input to a first input terminal 21. 1 is input to the first input terminal 21, the second clock signal CK2 is input to the second input terminal 22, and the third input A third clock signal CK3 is input to a terminal 23, and a start pulse is input to the fifth input terminal 25, the next stage signal OUT(3) is input to the first output terminal 2 A first output signal OUT(1)(SR) is output from the first output terminal 6, and a second The output signal OUT(1) is output.

[0209] In addition, the first pulse output circuit 10_1 to the N-th pulse output circuit 10_N are provided with a three-terminal transistor. In addition to the transistor, a four-terminal transistor 28 (see FIG. 9C) can be used. In this specification, a transistor has two gate electrodes via a semiconductor layer. In this case, the gate electrode below the semiconductor layer is called the lower gate electrode, and the gate electrode above the semiconductor layer is called the upper gate electrode. The gate electrode of the transistor 28 is also called the upper gate electrode. A first control signal G1 input to the gate electrode above the gate electrode and a second control signal G2 input to the gate electrode above the gate electrode This is an element that can perform electrical control between the In terminal and the Out terminal.

[0210] When an oxide semiconductor is used for a semiconductor layer including a channel formation region of a transistor, As a result, the threshold voltage may shift to the negative or positive side. In a transistor in which an oxide semiconductor is used for a semiconductor layer including a channel formation region, the threshold voltage A configuration capable of controlling the voltage is preferable. The transistor 28 shown in FIG. Gate electrodes are provided above and below the channel forming region via gate insulating layers. By controlling the potential of the gate electrode and / or the gate electrode underneath, the threshold voltage can be controlled to a desired value. It can be controlled.

[0211] Next, an example of a specific circuit configuration of the pulse output circuit will be described with reference to FIG. .

[0212] The pulse output circuit shown in FIG. 9D includes a first transistor 31 to a thirteenth transistor 43. The first input terminal 21 to the fifth input terminal 25 and the first In addition to the first output terminal 26 and the second output terminal 27, a power supply to which a first high power supply potential VDD is supplied A power supply line 51 is connected to a second high power supply potential VCC, and a power supply line 52 is connected to a low power supply potential VSS. The power supply lines 53 are connected to the first transistor 31 to the thirteenth transistor A signal or a power supply potential is supplied to the transistor 43 .

[0213] Here, the magnitude relationship of the power supply potentials of the power supply lines in FIG. 9(D) is as follows: the first power supply potential VDD is The second power supply potential VCC is set to a potential equal to or higher than the third power supply potential VSS. The first clock signal (CK1) to the fourth clock signal (CK4) are It is a signal that repeats H and L levels at regular intervals. For example, when it is H level, it is V DD, when it is at L level it is VSS.

[0214] By setting the potential VDD of the power supply line 51 higher than the potential VCC of the power supply line 52, The potential applied to the gate electrode of the transistor can be kept low without affecting the operation of the transistor. This makes it possible to reduce the shift in the threshold voltage of the transistor and suppress degradation.

[0215] As shown in FIG. 9D, the first transistor 31 to the thirteenth transistor 4 3, the first transistor 31, the sixth transistor 36 to the ninth transistor 3 It is preferable to use the four-terminal transistor 28 shown in FIG.

[0216] The operation of the first transistor 31 and the sixth to ninth transistors 36 to 39 is as follows: The potential of the node to which one of the electrodes serving as the source or drain is connected is controlled by controlling the gate electrode. In addition, the gate electrode is required to be switched by a control signal. The fast response (the rise of the on-current is steep) reduces malfunction of the pulse output circuit. It is preferable to use a transistor that can reduce the current. Therefore, a four-terminal transistor By using 28, the threshold voltage can be controlled, and malfunctions can be further reduced. In FIG. 9D, the first control signal G1 and the second control signal G2 are Although the control signal G2 is the same control signal, a configuration in which different control signals are input may be used.

[0217] In FIG. 9D, the first transistor 31 has a first terminal electrically connected to a power supply line 51. The second terminal is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode ( The lower gate electrode and the upper gate electrode are electrically connected to the fourth input terminal 24. .

[0218] The second transistor 32 has a first terminal electrically connected to the power supply line 53 and a second terminal electrically connected to the ninth a gate electrode electrically connected to the first terminal of the fourth transistor 3 The gate electrode of the first transistor is electrically connected to the gate electrode of the second transistor.

[0219] The third transistor 33 has a first terminal electrically connected to the first input terminal 21 and a second terminal The terminal is electrically connected to a first output terminal 26 .

[0220] The fourth transistor 34 has a first terminal electrically connected to the power supply line 53 and a second terminal The output terminal 26 is electrically connected to the

[0221] The fifth transistor 35 has a first terminal electrically connected to the power supply line 53 and a second terminal The gate electrode of the first transistor 32 and the gate electrode of the fourth transistor 34 are electrically connected to The gate electrode is electrically connected to a fourth input terminal 24 .

[0222] The sixth transistor 36 has a first terminal electrically connected to the power supply line 52 and a second terminal The gate electrode of the first transistor 32 and the gate electrode of the fourth transistor 34 are electrically connected to The gate electrodes (the lower gate electrode and the upper gate electrode) are connected to the fifth input terminal 25. are electrically connected.

[0223] The seventh transistor 37 has a first terminal electrically connected to the power supply line 52 and a second terminal electrically connected to the eighth The second terminal of the transistor 38 is electrically connected to the gate electrode (the lower gate electrode and The upper gate electrode is electrically connected to the third input terminal 23 .

[0224] The eighth transistor 38 has a first terminal connected to the gate electrode of the second transistor 32 and a fourth The gate electrode of the transistor 34 is electrically connected to the gate electrode of the gate electrode (the lower gate electrode and The upper gate electrode is electrically connected to a second input terminal 22 .

[0225] The ninth transistor 39 has a first terminal connected to the second terminal of the first transistor 31 and the second terminal of the second transistor 32. The second terminal of the third transistor 33 is electrically connected to the second terminal of the third transistor 32. The gate electrode of the tenth transistor 40 is electrically connected to the gate electrode of the tenth transistor 40. The lower gate electrode and the upper gate electrode are electrically connected to a power supply line 52 .

[0226] The tenth transistor 40 has a first terminal electrically connected to the first input terminal 21 and a second terminal electrically connected to the The terminal is electrically connected to the second output terminal 27, and the gate electrode of the ninth transistor 39 It is electrically connected to the second terminal.

[0227] The eleventh transistor 41 has a first terminal electrically connected to the power supply line 53 and a second terminal The gate electrode of the second transistor 32 is electrically connected to the output terminal 27 of the second transistor 32. The second transistor 32 is electrically connected to the first electrode and the gate electrode of the fourth transistor 34 .

[0228] The twelfth transistor 42 has a first terminal electrically connected to the power supply line 53 and a second terminal The gate electrode of the seventh transistor 37 is electrically connected to the output terminal 27 of the second transistor. The gate electrode is electrically connected to the electrodes (the lower gate electrode and the upper gate electrode).

[0229] The thirteenth transistor 43 has a first terminal electrically connected to the power supply line 53 and a second terminal The gate electrode of the seventh transistor 37 is electrically connected to the output terminal 26 of the first transistor. The gate electrode is electrically connected to the electrodes (the lower gate electrode and the upper gate electrode).

[0230] In FIG. 9D, the gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 40 The connection point of the gate electrode of the ninth transistor 39 and the second terminal of the ninth transistor 39 is referred to as node A. In addition, the gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, the gate electrode of the fifth transistor 35, the second terminal of the sixth transistor 35, the second terminal of the sixth transistor 36, A connection point between the first terminal of the eleventh transistor 38 and the gate electrode of the eleventh transistor 41 is called a node B. (See FIG. 10(A)).

[0231] FIG. 10A shows the pulse output circuit described in FIG. 9D as a first pulse output circuit 10_1. When applied to the first input terminal 21 to the fifth input terminal 25 and the first output terminal 26 and 2 and a signal input to or output from a second output terminal 27.

[0232] Specifically, a first clock signal CK1 is input to the first input terminal 21, and A second clock signal CK2 is input to the third input terminal 22, and a third clock signal CK3 is input to the third input terminal 23. A start pulse is input to the fourth input terminal 24, and a clock signal CK3 is input to the fifth input terminal 25. The next stage signal OUT(3) is input to the first output terminal 25, and the first output signal OUT (1)(SR) is output, and the second output signal OUT(1) is output from the second output terminal 27. will be done.

[0233] A transistor is defined as an element having at least three terminals including a gate, a drain, and a source. The element has a channel region between a drain region and a source region, A current can be passed through the in-region, the channel region, and the source region. Which is the source and which is the drain depends on the transistor structure and operating conditions. Therefore, it is difficult to determine whether the source and drain are In some cases, the region that functions as a source or drain is not called a source or drain. In these cases, they may be referred to as the first terminal and the second terminal, respectively.

[0234] In FIG. 10(A), the node A is left floating, so that the bootstrap operation is In order to hold the potential of the node B, a capacitor may be provided separately. A capacitor having one electrode electrically connected to the node B may be provided separately.

[0235] Here, the timing of the shift register having a plurality of pulse output circuits shown in FIG. The shift register is a scanning line driver circuit. In FIG. 10B, period 61 is a vertical blanking period, and period 62 corresponds to a gate selection period. .

[0236] As shown in FIG. 10A, the ninth transistor has a gate to which the second power supply potential VCC is applied. By providing the transistor 39, the following can be achieved before and after the bootstrap operation: There are such advantages.

[0237] In the absence of the ninth transistor 39, the gate electrode of which is applied with the second power supply potential VCC, When the potential of the node A rises due to the base strap operation, the second transistor 31 The potential of the source terminal rises and becomes higher than the first power supply potential VDD. Then, the source of the first transistor 31 is switched to the first terminal side, that is, the power supply line 51 side. Therefore, in the first transistor 31, between the gate and the source, between the gate and the drain In both cases, a large bias voltage is applied, which places a large stress on the transistor. This can be a cause of deterioration.

[0238] Therefore, a ninth transistor 39 is provided to the gate electrode of which the second power supply potential VCC is applied. By setting the voltage at node A to 0 V, the voltage at node A rises due to the bootstrap operation, but the voltage at node A rises due to the bootstrap operation. This can prevent the potential of the second terminal of the transistor 31 from increasing. By providing the ninth transistor 39, the gate and source of the first transistor 31 are Therefore, the value of the negative bias voltage applied between the electrodes can be reduced. By using the circuit configuration of the above form, a voltage is applied between the gate and source of the first transistor 31. Since the negative bias voltage applied to the first transistor 31 can be reduced, the Deterioration can be suppressed.

[0239] The ninth transistor 39 is provided at a position corresponding to the second gate of the first transistor 31. A terminal is connected between the terminal and the gate of the third transistor 33 via a first terminal and a second terminal. In addition, in the present embodiment, a system having a plurality of pulse output circuits may be provided. In the case of a soft register, the signal line driver circuit has more stages than the scan line driver circuit. The resistor 39 may be omitted, which has the advantage of reducing the number of transistors.

[0240] Note that the semiconductor layers of the first to thirteenth transistors 31 to 43 are made of oxide By using a semiconductor, the off-current of a transistor is reduced, and the on-current and field-effect transition are reduced. This increases mobility and reduces the degree of deterioration, making it ideal for use in circuits. In addition, a transistor using an oxide semiconductor can be formed in an amorphous Compared to a transistor using silicon, the transistor The degree of deterioration of the transistor is small. Therefore, the power supply line that supplies the second power supply potential VCC The same operation can be obtained by supplying the first power supply potential VDD, and the power supply line between the circuits Since the number of circuits can be reduced, the circuit size can be reduced.

[0241] The gate electrodes (lower gate electrode and upper gate electrode) of the seventh transistor 37 a clock signal provided by the third input terminal 23 to the gate of the eighth transistor 38; The input electrodes (lower gate electrode and upper gate electrode) are supplied with a second input terminal 22. The clock signal is applied to the gate electrode of the seventh transistor 37 (the lower gate electrode and the upper gate electrode). A clock signal is supplied to the gate electrode of the eighth transistor by the second input terminal 22. The third input terminal 23 is connected to the gate electrodes (lower gate electrode and upper gate electrode) of the gate electrode of the transistor 38. The same effect can be obtained by swapping the wiring so that the clock signal is supplied by do.

[0242] In the shift register shown in FIG. 10A, the seventh transistor 37 and the eighth The seventh transistor 37 is turned off and the eighth transistor 38 is turned on. Then the seventh transistor 37 is off and the eighth transistor 38 is on. 8 is turned off, the second input terminal 22 (CK2) and the third input terminal The voltage drop at node B caused by the voltage drop at transistor 23 (CK3) is The potential of the gate electrode of the eighth transistor 37 is decreased, and the potential of the gate electrode of the eighth transistor 38 is decreased. This occurs twice due to the decline.

[0243] On the other hand, in the shift register shown in FIG. The seventh transistor 37 is turned on, and the eighth transistor 38 is turned on. Then the seventh transistor 37 is off and the eighth transistor 38 is off. By turning off the input terminal 38, the second input terminal 22 (CK2) and the third input terminal The drop in the potential of node B caused by the drop in the potential of transistor 23 (CK3) is suppressed by the eighth transistor. The potential of the gate electrode of the transistor 38 can be reduced to one time.

[0244] Therefore, the gate electrode of the seventh transistor 37 (the lower gate electrode and the upper gate electrode) A clock signal CK3 is supplied to the eighth transistor 38 from the third input terminal 23. The gate electrodes (lower gate electrode and upper gate electrode) of the It is preferable to have a wiring relationship in which the clock signal CK2 is supplied. This is because the number of fluctuations in position is reduced, and noise can be reduced.

[0245] In this manner, the potentials of the first output terminal 26 and the second output terminal 27 are maintained at the L level. By configuring the node B to periodically receive a high-level signal during the period, the pulse output This makes it possible to suppress malfunction of the power circuit.

[0246] Note that this embodiment mode can be freely combined with other embodiment modes.

[0247] (Embodiment 7) In this embodiment, the transistor shown in Embodiment 1 or 2 is used as one mode of a display device. 11 to 24 are used to show examples of liquid crystal display devices using liquid crystal elements as display elements. explain.

[0248] First, we will explain the VA (Vertical Alignment) type liquid crystal display device. A VA type LCD is a type of LCD that controls the alignment of liquid crystal molecules in the LCD panel. In a VA type LCD device, when no voltage is applied, the liquid crystal molecules are aligned relative to the panel surface. In this embodiment, the pixels are arranged in a vertical direction. Divide into regions (e.g. 2 to 4 sub-pixels) and tilt the molecules in different directions in each region. This is called multi-domain or multi-domain design. A liquid crystal display device in which a multi-domain design is taken into consideration will be described.

[0249] 12 and 13 show a pixel electrode and a counter electrode, respectively. FIG. 2 is a plan view of the substrate side on which electrodes are formed, showing a cross-sectional structure corresponding to a cutting line EF shown in the figure. FIG. 11 shows the structure. FIG. 13 shows a plan view of the substrate on which the counter electrode is formed. The following description will be given with reference to these figures.

[0250] FIG. 11 shows a transistor 628, a pixel electrode layer 624 connected to the transistor 628, and a storage capacitor 63 A substrate 600 on which a counter electrode layer 640 and the like are formed is overlapped with a counter substrate 601 on which a counter electrode layer 640 and the like are formed. The figure shows the state after the two plates are aligned and liquid crystal is injected.

[0251] A colored film 636 and a counter electrode layer 640 are formed on the counter substrate 601. On the pixel electrode layer 624, an alignment film 648 is formed. An alignment film 646 is also formed on the counter electrode layer 640 and the protrusions 644. A liquid crystal layer 650 is formed between opposing substrates 601 .

[0252] On the substrate 600, a transistor 628 and a pixel electrode layer 624 connected thereto, and a storage capacitor The pixel electrode layer 624 is formed by forming an insulating film 620, an insulating film 621, and an insulating film 622. The film 622 is connected to the wiring 618 through a contact hole 623 formed therein. The transistors described in Embodiments 1 and 2 can be used as appropriate for the transistor 628. The storage capacitor 630 is formed at the same time as the gate wiring 602 of the transistor 628. The second insulating layer 606 is formed simultaneously with the capacitance wiring 604, the gate insulating layer 606, and the wirings 616 and 618. It is configured with a capacitance wiring 617 .

[0253] The pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640 are overlapped to form a liquid crystal element. It has been made.

[0254] FIG. 12 shows a planar structure on a substrate 600. The pixel electrode layer 624 is made of the material shown in the first embodiment. The pixel electrode layer 624 is formed using a material. A slit 625 is provided in the pixel electrode layer 624. The slit 625 is It is used to control the alignment of the liquid crystal.

[0255] The transistor 629 and the pixel electrode layer 626 and the storage capacitor 63 connected thereto shown in FIG. 1 are formed in the same manner as the transistor 628, the pixel electrode layer 624, and the storage capacitor portion 630, The transistor 628 and the transistor 629 are both connected to the wiring 616. The pixels of this liquid crystal display panel are made up of a pixel electrode layer 624 and a pixel electrode layer 6 That is, the pixel electrode layer 624 and the pixel electrode layer 626 are In this embodiment, a pixel is composed of two sub-pixels, but it can be further divided into several sub-pixels. It can also be made up of pixels.

[0256] 13 shows the planar structure of the opposing substrate side. The opposing electrode layer 640 is the same as the pixel electrode layer 624. On the counter electrode layer 640, a protrusion for controlling the alignment of the liquid crystal is formed. In addition, in FIG. 13, the pixel electrode layer 624 formed on the substrate 600 is The counter electrode layer 640, the pixel electrode layer 624, and the pixel electrode layer 626 are indicated by dashed lines. The pole layers 626 are shown arranged one on top of the other.

[0257] An equivalent circuit of this pixel structure is shown in FIG. 14. Transistors 628 and 629 are Both are connected to the gate wiring 602 and the wiring 616. In this case, the capacitance wiring 604 and the capacitance wiring By making the potential of the line 605 different, the operation of the liquid crystal element 651 and the liquid crystal element 652 can be made different. That is, the potentials of the capacitance wiring 604 and the capacitance wiring 605 can be controlled individually. This allows for precise control of the orientation of the liquid crystal to expand the viewing angle.

[0258] When a voltage is applied to the pixel electrode layer 624 having the slit 625, The slit 625 and the protrusion on the opposing substrate 601 side cause distortion of the electric field (diagonal electric field). By arranging the 644 in an alternating pattern, a diagonal electric field is effectively generated, and the liquid crystal By controlling the orientation, the direction in which the liquid crystal is oriented can be made to differ depending on the location. The viewing angle of the LCD panel is expanded by creating a multi-domain structure.

[0259] Next, a VA type liquid crystal display device different from the above will be described with reference to FIGS. 15 to 18. do.

[0260] 15 and 16 show the pixel structure of a VA type liquid crystal display panel. FIG. 15 shows a cross-sectional structure corresponding to the cutting line YZ shown in the figure.

[0261] This pixel structure has multiple pixel electrodes in one pixel, and each pixel electrode has a transistor. Each transistor is configured to be driven by a different gate signal. That is, in a pixel with a multi-domain design, the voltage applied to each pixel electrode is It has a configuration in which the signals are controlled independently.

[0262] The pixel electrode layer 624 is connected to a transistor 628 via a wiring 618 through a contact hole 623. The pixel electrode layer 626 is connected to the wiring 619 through a contact hole 627. 629 through a transistor 629.

[0263] The transistor 628 and the transistor 629 are the transistors shown in the first or second embodiment. The gate wiring 602 of the transistor 628 and the The 29 gate wirings 603 are separated so that different gate signals can be applied. On the other hand, the wiring 616 functioning as a data line is connected to a transistor 628 and a transistor The wiring 618 and 619 are commonly used. In addition, the gate insulating layer 6 A capacitance line 690 is provided via .

[0264] The pixel electrode layer 624 and the pixel electrode layer 626 have different shapes and are separated by a slit 625. The pixel electrode layer 626 is arranged so as to surround the outside of the pixel electrode layer 624 that spreads in a V shape. The voltage applied to the pixel electrode layer 624 and the pixel electrode layer 626 is applied to the transistor 6 The alignment of the liquid crystal is controlled by changing the polarity of the pixel electrode 28 and the transistor 629. An equivalent circuit of the pixel structure is shown in FIG. 18. The transistor 628 is connected to the gate wiring 602. The transistor 629 is connected to the gate wiring 603. The transistor 629 is connected to the wiring 616. By applying different gate signals to the gate electrodes 651 and 652, the liquid crystal elements 651 and 652 can be operated differently. That is, the operation of the transistor 628 and the transistor 629 can be individually controlled. By precisely controlling the liquid crystal orientation of the liquid crystal elements 651 and 652, The viewing angle can be widened.

[0265] A colored film 636 and a counter electrode layer 640 are formed on the counter substrate 601. A flattening film 637 is formed between the electrode layer 636 and the counter electrode layer 640 to prevent the alignment of the liquid crystal from being disturbed. FIG. 17 shows the planar structure of the opposing substrate side. The opposing electrode layer 640 is shared between different pixels. The electrode is connected to the substrate, and has a slit 641 formed therein. The element electrode layer 624 and the slits 625 on the pixel electrode layer 626 side are arranged so as to interdigitate with each other. By doing so, it is possible to effectively generate an oblique electric field and control the alignment of the liquid crystal. This allows the orientation direction of the liquid crystal to vary depending on the location, thereby widening the viewing angle. In addition, in FIG. 17, the pixel electrode layer 624 and the pixel electrode layer 626 formed on the substrate 600 are As indicated by the dashed lines, the counter electrode layer 640, the pixel electrode layer 624, and the pixel electrode layer 626 overlap each other. The figure shows how the sensors are arranged.

[0266] An alignment film 648 is formed on the pixel electrode layer 624 and the pixel electrode layer 626. An alignment film 646 is also formed on the layer 640. The pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640 are formed. The first liquid crystal element 651 is formed by overlapping the pixel electrode layer 626. The liquid crystal layer 650 and the counter electrode layer 640 are overlapped to form a second liquid crystal element 652. The pixel structure of the display panel described with reference to FIGS. 15 to 18 has a first liquid crystal element in one pixel. The liquid crystal display has a multi-domain structure in which a first liquid crystal element and a second liquid crystal element are provided.

[0267] Next, we will explain the in-plane switching type liquid crystal display device. In the in-plane switching type, This method applies an electric field in the horizontal direction to drive the liquid crystal and express gradation. If this is done, the viewing angle can be expanded to approximately 180 degrees. A liquid crystal display device to be used will be described.

[0268] FIG. 19 shows a substrate on which an electrode layer 607, a transistor 628, and a pixel electrode layer 624 are formed. The figure shows a state in which the opposing substrate 600 and the opposing substrate 601 are overlapped and liquid crystal is injected. A coloring film 636, a flattening film 637, etc. are formed on the substrate 631. Since the counter electrode is provided on the counter substrate 600 side, the counter electrode is not provided on the counter substrate 601 side. A liquid crystal layer 650 is formed between the substrate 600 and the opposing substrate 601 via an alignment film 646 and an alignment film 648. It has been made.

[0269] On the substrate 600, an electrode layer 607, a capacitance wiring 604 connected to the electrode layer 607, and a transistor The capacitance wiring 604 is connected to the gate wiring 60 of the transistor 628. The transistor 628 can be formed at the same time as the transistor 2. The electrode layer 607 can be formed by using the transistor shown in Embodiment 1 or 2. The electrode layer 607 may be made of a material similar to that of the pixel electrode layer shown in FIG. In addition, a gate insulating film is formed on the electrode layer 607 and the capacitance wiring 604. A layer 606 is formed.

[0270] A wiring 616 and a wiring 618 of a transistor 628 are formed on the gate insulating layer 606. The line 616 is a data line that carries a video signal in the liquid crystal display panel and extends in one direction. At the same time, it is connected to the source region or drain region of the transistor 628 and The wiring 618 is the other of the source and drain electrodes. 624. The wiring is connected to the pixel electrode layer 624.

[0271] An insulating film 620 and an insulating film 621 are formed over the wiring 616 and the wiring 618. On the insulating film 620, a wiring is formed through a contact hole 623 formed in the insulating film 620. A pixel electrode layer 624 is formed to connect to the line 618. The pixel electrode layer 624 is the same as that of the third embodiment. The pixel electrode layer 457 can be formed using a material similar to that of the pixel electrode layer 457 shown in FIG.

[0272] In this manner, a transistor 628 and a pixel electrode layer 624 connected thereto are formed on the substrate 600. A storage capacitor is formed between the electrode layer 607 and the pixel electrode layer 624.

[0273] 20 is a plan view showing the configuration of a pixel electrode. The surface structure is shown in Figure 19. The pixel electrode layer 624 is provided with a slit 625. The bit 625 is for controlling the alignment of the liquid crystal.

[0274] In this case, an electric field is generated between the electrode layer 607 and the pixel electrode layer 624. The gate insulating layer 606 is formed between the electrode layers 624. The thickness is 50 to 200 nm, which is sufficiently thin compared with the thickness of the liquid crystal layer, which is 2 to 10 μm. Thus, an electric field is generated in a direction substantially parallel to the substrate 600 (horizontal direction). The orientation of the liquid crystal is controlled, and the liquid crystal molecules are rotated horizontally using an electric field parallel to the substrate. In this case, the liquid crystal molecules are horizontal in all states, so there is no change in contrast depending on the viewing angle. The viewing angle is increased without any change in the color. Since the electrode is optical, the aperture ratio can be improved.

[0275] Next, another example of a liquid crystal display device of the lateral electric field type will be described.

[0276] 21 and 22 show the pixel structure of an IPS type liquid crystal display device. FIG. 21 shows a cross-sectional structure corresponding to the cutting line VW shown in the figure.

[0277] FIG. 21 shows a substrate 60 on which a transistor 628 and a pixel electrode layer 624 connected thereto are formed. 6 shows a state in which the opposing substrate 601 and the opposing substrate 601 are overlapped and liquid crystal is injected. A coloring film 636, a flattening film 637, etc. are formed on the opposite substrate 601 side. No counter electrode is provided. In addition, an alignment film 646 is provided between the substrate 600 and the counter substrate 601. A liquid crystal layer 650 is formed via an alignment film 648 .

[0278] A common potential line 609 and a transistor 628 are formed on the substrate 600. The line 609 can be formed at the same time as the gate wiring 602 of the transistor 628. The transistor 628 may be the transistor described in Embodiment 1 or 2. can be done.

[0279] A wiring 616 and a wiring 618 of a transistor 628 are formed over the gate insulating layer 606 . The wiring 616 is a data line for supplying a video signal to the liquid crystal display panel. The transistor 628 is connected to the source region or the drain region. The wiring 618 is a wiring that is connected to the pixel electrode layer 624. It also serves as the other of the source and drain electrodes of the transistor 628 .

[0280] An insulating film 620 and an insulating film 621 are formed on the wiring 616 and the wiring 618. On the insulating films 620 and 621, a pixel electrode is formed, which is connected to the wiring 618 through a contact hole 623. The pixel electrode layer 624 is formed. 22, the pixel electrode layer 7 can be formed using the same material. 624 is a common potential line 609 and a comb-shaped electrode formed at the same time so that a horizontal electric field is generated between them. The comb-tooth portion of the pixel electrode layer 624 is formed at the same time as the common potential line 609. The electrodes are formed so as to interdigitate with each other.

[0281] When an electric field is generated between the pixel electrode layer 624 and the common potential line 609, the liquid crystal Therefore, the liquid crystal molecules are rotated horizontally by using an electric field in a direction approximately parallel to the substrate. In this case, the liquid crystal molecules are horizontal in any state, so the liquid crystal molecules are rotated depending on the viewing angle. This results in no change in contrast and a wider viewing angle.

[0282] In this manner, a transistor 628 and a pixel electrode layer 624 connected thereto are formed on the substrate 600. The storage capacitor is formed by a common potential line 609, a gate insulating layer 606, and a capacitance electrode 61. The capacitance electrode 615 and the pixel electrode layer 624 are formed through a contact hole 633. are connected via

[0283] Next, a configuration of a TN type liquid crystal display device will be described.

[0284] 23 and 24 show the pixel structure of a TN type liquid crystal display device. FIG. 23 shows a cross-sectional structure corresponding to the cutting line KL shown in the figure.

[0285] The pixel electrode layer 624 is connected to a transistor 628 via a wiring 618 through a contact hole 623. The wiring 616 functioning as a data line is connected to a transistor 628. The transistor 628 is the transistor described in Embodiment 1 or 2. It can be used.

[0286] The pixel electrode layer 624 is formed using a material similar to that of the pixel electrode layer 457 described in Embodiment 3. can be

[0287] A colored film 636 and a counter electrode layer 640 are formed on the counter substrate 601. A flattening film 637 is formed between the electrode layer 636 and the counter electrode layer 640 to prevent the alignment of the liquid crystal from being disturbed. The liquid crystal layer 650 is formed by disposing an alignment film 648 and an alignment layer 649 between the pixel electrode layer 624 and the counter electrode layer 640. The liquid crystal element is formed by interposing a counter film 646 between the pixel electrode layer 624, the liquid crystal layer 650, and It is formed by overlapping counter electrode layers 640 .

[0288] The colored film 636 may be formed on the substrate 600 side. The surface opposite to the surface on which the transistor is formed, and the surface on which the counter electrode layer 640 of the counter substrate 601 is formed A polarizing plate is attached to the surface opposite to the surface to which the polarizing plate is attached.

[0289] Through the above steps, a liquid crystal display device with a high aperture ratio can be manufactured.

[0290] Note that this embodiment mode can be freely combined with other embodiment modes.

[0291] (Embodiment 8) The display device disclosed in this specification can be applied to various electronic devices (including gaming machines). The electronic device can be, for example, a television device (a television or a television receiver). (also called "transmitting devices"), computer monitors, digital cameras, digital video cameras , digital photo frames, mobile phones (also called mobile phones or mobile phone devices), portable games Examples include gaming machines, mobile information terminals, audio playback devices, and large game machines such as pachinko machines. .

[0292] FIG. 25A shows an example of a mobile phone. A mobile phone 1100 includes a housing 1101. In addition to the display unit 1102, the operation buttons 1103, the external connection port 1104, It is equipped with a speaker 1105, a microphone 1106, etc.

[0293] In the mobile phone 1100 shown in FIG. 25A, information is displayed by touching a display unit 1102 with a finger or the like. In addition, operations such as making calls and sending and receiving e-mails can be performed by pointing at the display unit 1102. This can be done by touching it with a

[0294] The screen of the display unit 1102 has three main modes. The first is a display mode that is mainly used for displaying images. The first mode is a display mode, the second is an input mode for inputting information such as characters, and the third mode is a display mode. This is a display + input mode that combines the display mode and the input mode.

[0295] For example, when making a call or composing an e-mail, the display unit 1102 is used mainly for inputting characters. In this case, the display unit 11 is switched to the input mode and the user can input characters displayed on the screen. It is preferable to display a keyboard or number buttons on 02 that are easy to recognize.

[0296] In addition, the mobile phone 1100 may include a sensor for detecting tilt, such as a gyro or an acceleration sensor. By providing a detection device having the above configuration, the orientation of the mobile phone 1100 (portrait or landscape) can be determined and the display The screen display of the display unit 1102 can be automatically switched.

[0297] The screen mode can be changed by touching the display unit 1102 or by operating the housing 1101. The type of image displayed on the display unit 1102 can be selected by operating the operation button 1103. For example, the image signal to be displayed on the display unit may be changed by If the data is text data, the mode switches to input mode.

[0298] In the input mode, the optical sensor of the display unit 1102 detects a signal and displays If there is no input by touch operation of the unit 1102 for a certain period of time, the screen mode is changed to the input mode. Alternatively, the display mode may be switched from the normal mode to the display mode.

[0299] The display unit 1102 can also function as an image sensor. 02 can capture palm prints, fingerprints, etc., and perform personal authentication. It also emits near-infrared light. If a light source that can capture images of finger veins, palm veins, etc. is used, the display unit 110 In the second embodiment, a plurality of transistors 460 shown in the first or second embodiment are arranged. Since the transistor 460 has a light-transmitting property, a photosensor is disposed under the transistor 460. In addition, even when a light source that emits near-infrared light is used, the transistor Since the light is not blocked by the 460, a sufficient amount of near-infrared light can be irradiated onto the subject. can be done.

[0300] FIG. 25(B) is also an example of a mobile phone. The portable information terminal shown in FIG. 25(B) is It can have multiple functions. For example, in addition to the telephone function, it can have a built-in computer and perform various functions. It can also be equipped with various data processing functions.

[0301] The portable information terminal shown in FIG. 25B is configured with two housings, a housing 1800 and a housing 1801. The housing 1800 includes a display panel 1802, a speaker 1803, a microphone, and a microphone array. Phone 1804, pointing device 1806, camera 1807, external connection terminal 18 08, and the housing 1801 includes a keyboard 1810, an external memory slot 1811, and The antenna is built into the housing 1801.

[0302] The display panel 1802 is equipped with a touch panel, and in FIG. A plurality of operation keys 1805 are indicated by dotted lines.

[0303] In addition to the above configuration, a non-contact IC chip, a small recording device, etc. may be built in.

[0304] The display device is used as a display panel 1802, and the display direction can be changed appropriately depending on the usage mode. In addition, since the camera 1807 is provided on the same surface as the display panel 1802, The speaker 1803 and microphone 1804 are not limited to voice calls. It can also be used for recording and playback. Furthermore, the housing 1800 and the housing 1801 are slide-type. As shown in Figure 25(B), the unfolded state can be folded up into a folded state. It is possible to make it compact enough to fit a obi.

[0305] The external connection terminal 1808 is an input / output terminal for power input and information communication, and is used for charging and personal It is possible to communicate data with a global computer. Also, an external memory slot 1811 By inserting a recording medium, it is possible to store and transfer larger amounts of data.

[0306] In addition to the above functions, even if the device has infrared communication function, TV reception function, etc. good.

[0307] FIG. 26A shows an example of a television device. The television device 9600 includes: A display unit 9603 is incorporated in a housing 9601. The display unit 9603 displays images. In this embodiment, the housing 9601 is supported by a stand 9605. The figure shows a configuration in which

[0308] The television device 9600 can be operated using an operation switch on the housing 9601 or a remote control. The remote control 9610 includes an operation key 960 9, channel switching and volume control can be performed, and the display unit 9603 displays The remote control unit 9610 can control the image displayed on the screen. A display unit 9607 for displaying information output from the machine 9610 may be provided.

[0309] The television device 9600 includes a receiver and a modem. It can receive more general television broadcasts, and can also be connected to a modem via wired or wireless connection. By connecting to a network, communication can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0310] FIG. 26B shows an example of a digital photo frame. Digital Photo Frame In the device 9700, a display unit 9703 is incorporated in a housing 9701. It is possible to display various images, for example image data taken with a digital camera. By displaying this, it can function just like a normal photo frame.

[0311] The Digital Photo Frame 9700 includes an operation unit, external connection terminals (USB terminals, etc.), The device is configured with an external memory slot, etc. These components are built into the same surface as the display unit. However, providing it on the side or back is preferable since it improves the design. For example, The external memory slot of the digital photo frame can store image data taken with a digital camera. The image data is then input to a memory that stores the image data, and the input image data is displayed on the display unit 9. 703.

[0312] The digital photo frame 9700 may also be configured to transmit and receive information wirelessly. It is also possible to wirelessly import and display desired image data.

[0313] FIG. 27 shows a portable gaming machine, which is composed of two cabinets, a cabinet 9881 and a cabinet 9891. The housing 9881 includes a display unit 988 and a connector 9893 for connecting the display unit 988 to the housing 9881 in an openable and closable manner. 2 is incorporated in the housing 9891, and a display unit 9883 is incorporated in the housing 9891.

[0314] In addition, the portable gaming machine shown in FIG. 27 includes a speaker 9884 and an external memory slot 9886. , LED lamp 9890, input means (operation keys 9885, connection terminal 9887, sensor 98 88 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical Chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration 9889) equipped with a microphone, etc. Of course, the configuration of the portable gaming machine is not limited to the above, and at least The configuration may be one having the display device disclosed in the document, and other auxiliary equipment may be provided as appropriate. The portable game machine shown in FIG. 27 can be implemented as a game machine that uses a program recorded on a recording medium. It has the function of reading the game program or data and displaying it on the display, and also wirelessly communicating with other portable gaming machines. The functions of the portable gaming machine shown in FIG. The function is not limited to the above, but may have various functions.

[0315] As described above, the display device shown in the other embodiment can be used for displaying various electronic devices as described above. It can be placed in the section.

[0316] Note that this embodiment mode can be freely combined with other embodiment modes.

[0317] (Embodiment 9) In this embodiment, a configuration of a storage capacitor different from that of the third embodiment is shown in FIG. 28(A) and 28(B) show the transistor 46 in the pixel portion. 28(A) and (B) are cross-sectional views of the storage capacitor and the structure of the storage capacitor shown in FIG. Since the same parts are the same except for the difference in the number of parts, the same reference numerals are used for the same parts, and detailed explanations of the same parts will be omitted. is omitted.

[0318] FIG. 28(A) shows a dielectric layer including oxide insulating layers 426, 427, a protective insulating layer 428 and a planar insulating layer. In this example, a pixel electrode layer 457 and a capacitance wiring layer 432 form a storage capacitance by using an edge layer 456. The capacitor wiring layer 432 has the same light-transmitting property as the source electrode layer of the transistor 460 in the pixel portion. Since the material is the same and the layer is formed in the same process, the source wiring layer of the transistor 460 is not overlapped with the source wiring layer of the transistor 460. The layout is designed so that

[0319] In the storage capacitor shown in FIG. 28A, a pair of electrodes and a dielectric are transparent. The entire structure is translucent.

[0320] FIG. 28B shows an example of a storage capacitor configuration different from that shown in FIG.

[0321] FIG. 28B shows a structure in which a gate insulating layer 402 is used as a dielectric, a capacitance wiring layer 430, a capacitance electrode 43 In this example, a storage capacitor is formed by the capacitance electrode 431 and the oxide semiconductor layer 405. The oxide semiconductor layer 405 formed in contact with the semiconductor layer 402 functions as one electrode of a storage capacitor. The oxide semiconductor layer 405 is a source electrode layer or a drain electrode layer of the transistor 460. The capacitor wiring layer 430 is formed of the same material having the same light-transmitting property as the transistor 430 and in the same process. The gate electrode layer of the transistor 460 is formed of the same material having a light-transmitting property and in the same process. Therefore, it is laid out so as not to overlap with the gate wiring layer of the transistor 460.

[0322] Although not shown, the capacitance electrode 431 is electrically connected to the pixel electrode layer 457 .

[0323] The storage capacitor shown in FIG. 28B also has a pair of electrodes and a dielectric material that transmit light. The entire structure is translucent.

[0324] The storage capacitors shown in FIGS. 28A and 28B are transparent, and thus can display images with high precision. Even if the pixel size is reduced to achieve finer resolution, sufficient capacitance can be obtained and high development speed is possible. The rate can be realized.

[0325] Note that this embodiment mode can be freely combined with other embodiment modes. [Explanation of symbols]

[0326] 11 Wiring 12 Wiring 13 Wiring 14 Wiring 15 Wiring 21 Input terminal 22 Input terminal 23 Input terminal 24 Input terminals 25 Input terminal 26 Output terminal 27 Output terminal 28 Transistor 31 Transistor 32 Transistor 33 Transistor 34 Transistor 35 Transistor 36 Transistor 37 Transistor 38 Transistor 39 Transistor 40 Transistor 41 Transistor 42 Transistor 43 Transistor 51 Power line 52 Power line 53 Power line 61 period 62 period 400 Substrates 402 Gate insulating layer 403 Oxide semiconductor layer 404 Oxide semiconductor layer 405 Oxide semiconductor layer 411 Terminal 412 Connection electrode layer 414 Terminal 415 Conductive Layer 416 Electrode layer 417 Conductive Layer 418 Conductive Layer 422 Source wiring layer 423 Channel formation region 426 Oxide Insulation Layer 427 Oxide insulating layer 428 Protective Insulation Layer 429 Connection electrode layer 430 Capacitive wiring layer 431 Capacitive electrode 432 Capacitive wiring layer 440 Transistor 442 Connection electrode layer 443 Channel formation region 447 Oxide Conductive Layer 448 Oxide Conductive Layer 449 Connection electrode layer 450 Transistors 452 Connection electrode layer 453 Oxide Semiconductor Layer 454 Oxide semiconductor layer 456 Planarizing Insulation Layer 457 Pixel electrode layer 460 Transistors 421a Gate electrode layer 421b Gate electrode layer 421c Gate wiring layer 424a High resistance source region 424b High-resistance drain region 424c 1st area 424d 2nd area 425a Source electrode layer 425b Drain electrode layer 444a High resistance source region 444b High-resistance drain region 444c 1st area 444d 2nd area 445a Source electrode layer 445b Drain electrode layer 446a Oxide conductive layer 446b Oxide conductive layer 451a Gate electrode layer 451b Gate electrode layer 455a Source electrode layer 455b Drain electrode layer 600 Substrates 601 Opposing substrate 602 Gate wiring 603 Gate wiring 604 Capacitance wiring 605 Capacitance wiring 606 Gate Insulation Layer 607 Electrode layer 609 Common potential line 615 Capacitive electrode 616 Wiring 617 Capacitance wiring 618 Wiring 619 Wiring 620 Insulating film 621 Insulating film 622 Insulating film 623 Contact Hole 624 Pixel electrode layer 625 Slit 626 Pixel electrode layer 627 Contact Hole 628 Transistor 629 Transistor 630 Holding capacity section 631 Holding capacity section 633 Contact Hole 634 Colored film 636 Colored film 637 Planarization film 638 Colored film 640 Counter electrode layer 641 Slit 644 Protrusion 646 Orientation Film 648 Orientation Film 650 Liquid crystal layer 651 Liquid crystal element 652 Liquid crystal element 690 Capacitance wiring 1100 Mobile Phone 1101 Case 1102 Display section 1103 Operation button 1104 External connection port 1105 Speaker 1106 Mike 1800 Case 1801 Case 1802 Display Panel 1803 Speaker 1804 Microphone 1805 Operation key 1806 Pointing Device 1807 Camera 1808 External connection terminal 1810 Keyboard 1811 External memory slot 2600 Transistor Board 2601 Opposing substrate 2602 Sealing material 2603 Pixel section 2604 Display element 2605 Colored layer 2606 Polarizing plate 2607 Polarizing plate 2608 Wiring circuit section 2609 Flexible wiring board 2610 cold cathode tube 2611 Reflector 2612 Circuit Board 2613 Diffuser 4001 Board 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 Substrate 4008 Liquid crystal layer 4010 Transistor 4011 Transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive film 4020 Protective insulation layer 4021 Insulation layer 4030 Pixel electrode 4031 Counter electrode 4032 Insulation layer 4040 Conductive layer 4041 Insulation layer 5300 Board 5301 Pixel unit 5302 Scanning line driver circuit 5303 Scanning line driver circuit 5304 Signal line driver circuit 5305 Timing Control Circuit 5601 Shift Register 5602 Switching Circuit 5603 Transistor 5604 Wiring 5605 Wiring 9600 Television Equipment 9601 Case 9603 Display section 9605 Stand 9607 Display section 9609 Operation key 9610 Remote control device 9700 Digital Photo Frame 9701 Case 9703 Display section 9881 Case 9882 Display section 9883 Display section 9884 Speaker 9885 Operation key 9886 External memory slot 9887 Connection terminal 9888 Sensor 9889 Microphone 9890 LED Lamp 9891 Case 9893 Connection section

Claims

1. A semiconductor device having a first transistor and a second transistor, a first conductive layer having a region functioning as a gate electrode of the first transistor; a second conductive layer having a region functioning as a gate electrode of the second transistor; a first insulating layer having a region located above the first conductive layer and a region located above the second conductive layer, the first insulating layer having a region functioning as a gate insulating film of the first transistor and a region functioning as a gate insulating film of the second transistor; a first semiconductor layer having a region located above the first insulating layer and functioning as a channel formation region of the first transistor; a third conductive layer having a region located above the first insulating layer and functioning as a source electrode or a drain electrode of the second transistor; a fourth conductive layer having a region located above the first semiconductor layer and functioning as a source electrode or a drain electrode of the first transistor; a second semiconductor layer having a region located above the third conductive layer and functioning as a channel formation region of the second transistor; a second insulating layer having a region in contact with an upper surface of the second semiconductor layer; a third insulating layer having a region in contact with an upper surface of the first semiconductor layer and a region in contact with an upper surface of the second insulating layer.

2. In claim 1, the second semiconductor layer includes an oxide semiconductor; The oxide semiconductor device includes In, Ga, and Zn.

3. In claim 1, the second semiconductor layer includes an oxide semiconductor; The semiconductor device, wherein the oxide semiconductor is an In—O film.

Images