Semiconductor storage device

Abstract

To provide a suitably operating semiconductor storage device.SOLUTION: A semiconductor storage device comprises: a plurality of first semiconductor layers laminated in a lamination direction; a first via wiring electrically connected to the plurality of first semiconductor layers; a plurality of memory parts electrically connected to the plurality of first semiconductor layers; a plurality of first gate electrodes facing the plurality of first semiconductor layers; a plurality of first wirings electrically connected to the plurality of first gate electrodes; a plurality of second semiconductor layers electrically connected to the plurality of first gate electrodes via the plurality of first wirings; a second via wiring electrically connected to the plurality of second semiconductor layers; and a plurality of second gate electrodes facing the plurality of second semiconductor layers. The plurality of second semiconductor layers include a material different from the plurality of first semiconductor layers. A composition ratio of materials included in the plurality of second semiconductor layers differs from a composition ratio of materials included in the plurality of first semiconductor layers.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present embodiment relates to a semiconductor memory device. [Background technology]

[0002] 2. Description of the Related Art With the increasing integration density of semiconductor memory devices, studies on three-dimensional semiconductor memory devices are underway. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2022 / 0068933 [Patent Document 2] US Patent Application Publication No. 2020 / 0303400 [Patent Document 3] US Patent Application Publication No. 2022 / 0005830 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor memory device that operates favorably is provided. [Means for solving the problem]

[0005] A semiconductor memory device according to one embodiment includes a substrate, a plurality of first semiconductor layers stacked in a stacking direction intersecting a surface of the substrate, a first via wiring extending in the stacking direction and electrically connected to the plurality of first semiconductor layers, a plurality of memory units stacked in the stacking direction and electrically connected to the plurality of first semiconductor layers, a plurality of first gate electrodes stacked in the stacking direction and facing the plurality of first semiconductor layers, a plurality of first wirings stacked in the stacking direction, extending in a first direction intersecting the stacking direction and electrically connected to the plurality of first gate electrodes, a plurality of second semiconductor layers stacked in the stacking direction and electrically connected to the plurality of first wirings, a second via wiring extending in the stacking direction and electrically connected to the plurality of second semiconductor layers, and a plurality of second gate electrodes stacked in the stacking direction and facing the plurality of second semiconductor layers. The plurality of second semiconductor layers include a material different from the plurality of first semiconductor layers, or a composition ratio of a material included in the plurality of second semiconductor layers is different from a composition ratio of a material included in the plurality of first semiconductor layers. [Brief description of the drawings]

[0006] [Figure 1] 1 is a schematic circuit diagram showing a configuration of a semiconductor memory device according to a first embodiment. [Diagram 2] 11 is a schematic circuit diagram for illustrating a read operation of the semiconductor memory device. FIG. [Diagram 3] 11 is a schematic graph showing the relationship in magnitude between the voltages supplied to the word line WL and the layer select line LL in the read operation. [Figure 4] 1 is a schematic perspective view showing a configuration of a portion of a semiconductor memory device according to a first embodiment. [Diagram 5] 2 is a schematic XY cross-sectional view showing a configuration of a part of the memory layer ML. FIG. [Figure 6] 2 is a schematic XY cross-sectional view showing a configuration of a part of the memory layer ML. FIG. [Figure 7] The structure shown in FIG. 6 is cut along the line AA′, and the cross section is viewed in the direction of the arrow. [Figure 8] 2 is a schematic XY cross-sectional view showing a configuration of a part of the memory layer ML. FIG. [Figure 9] The structure shown in FIG. 8 is cut along line BB' and the cross section is viewed in the direction of the arrow. [Figure 10] 1 is a schematic cross-sectional view showing a configuration of a semiconductor memory device according to a first embodiment. [Figure 11] 5A to 5C are schematic cross-sectional views for explaining a manufacturing method of the semiconductor memory device. [Figure 12] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 13] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 14] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 15] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 16] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 17] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 18] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 19] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 20] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 21] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 22] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 23] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 24] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 25] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 26] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 27]5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 28] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 29] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 30] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 31] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 32] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 33] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 34] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 35] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 36] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 37] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 38] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 39] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 40] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 41] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 42] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 43] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 44] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 45] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 46] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 47] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 48] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 49] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 50] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 51] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 52] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 53] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 54] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 55] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 56] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 57] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 58] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 59] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 60] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 61] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 62] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 63] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 64] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 65] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 66] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 67] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 68] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 69] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 70] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 71] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 72] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 73] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 74] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 75] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 76] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 77] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 78] 11 is a schematic cross-sectional view showing a configuration of a portion of a semiconductor memory device according to a second embodiment. FIG. [Figure 79] 10A to 10C are schematic cross-sectional views for illustrating a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 80] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 81] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 82] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 83]5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 84] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 85] FIG. 11 is a schematic cross-sectional view showing a configuration of a portion of a semiconductor memory device according to a third embodiment. [Figure 86] FIG. 11 is a schematic cross-sectional view showing a configuration of a portion of a semiconductor memory device according to a third embodiment. [Figure 87] 13A to 13C are schematic cross-sectional views for illustrating a method for manufacturing a semiconductor memory device according to a third embodiment. [Figure 88] 13A to 13C are schematic cross-sectional views for illustrating a method for manufacturing a semiconductor memory device according to a third embodiment. [Figure 89] FIG. 11 is a schematic cross-sectional view showing a configuration of a portion of a semiconductor memory device according to a fourth embodiment. [Figure 90] FIG. 11 is a schematic cross-sectional view showing a configuration of a portion of a semiconductor memory device according to a fourth embodiment. [Figure 91] FIG. 13 is a schematic cross-sectional view showing a configuration of a portion of a semiconductor memory device according to a fifth embodiment. [Figure 92] FIG. 13 is a schematic cross-sectional view showing a configuration of a portion of a semiconductor memory device according to a fifth embodiment. [Figure 93] 13 is a schematic cross-sectional view showing a configuration of a portion of a semiconductor memory device according to a sixth embodiment. FIG. [Figure 94] FIG. 13 is a schematic circuit diagram showing a configuration of a portion of a semiconductor memory device according to a seventh embodiment. [Figure 95] 1 is a schematic perspective view showing a configuration of a portion of a semiconductor memory device according to an embodiment of the present invention. [Figure 96] 11 is a schematic XY cross-sectional view showing the configuration of a portion of the memory layer ML7. FIG. [Figure 97] The structure shown in FIG. 96 is cut along line AA' and shown in a cross section viewed in the direction of the arrow. [Figure 98] The structure shown in FIG. 96 is cut along line BB' and shown in a cross section viewed in the direction of the arrow. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Next, a semiconductor memory device according to an embodiment will be described in detail with reference to the drawings. Note that the following embodiment is merely an example, and is not intended to limit the present invention. Also, the following drawings are schematic, and for the sake of explanation, some configurations may be omitted. Also, parts common to multiple embodiments may be given the same reference numerals, and explanations may be omitted.

[0008] In addition, in this specification, the term "semiconductor memory device" may refer to a memory die, or may refer to a memory system including a controller die, such as a memory chip, a memory card, or an SSD (Solid State Drive). Furthermore, it may refer to a configuration including a host computer, such as a smartphone, a tablet terminal, or a personal computer.

[0009] In addition, in this specification, when it is said that a first configuration is "electrically connected" to a second configuration, the first configuration may be directly connected to the second configuration, or the first configuration may be connected to the second configuration via wiring, a semiconductor member, a transistor, etc. For example, when three transistors are connected in series, the first transistor is "electrically connected" to the third transistor even if the second transistor is in an OFF state.

[0010] Furthermore, in this specification, when it is said that a first configuration is "electrically connected between" a second configuration and a third configuration, it may mean that the first configuration, the second configuration, and the third configuration are connected in series, and that the second configuration is electrically connected to the third configuration via the first configuration.

[0011] In addition, in this specification, when it is said that a circuit or the like "conducts" two wirings or the like, it may mean, for example, that the circuit or the like includes a transistor or the like, that the transistor or the like is provided in a current path between the two wirings, and that the transistor or the like is in an ON state.

[0012] In this specification, a predetermined direction parallel to the upper surface of the substrate is called the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is called the Y direction, and a direction perpendicular to the upper surface of the substrate is called the Z direction.

[0013] In this specification, the direction intersecting with the surface of the substrate may be referred to as the stacking direction. Also, the direction along a specific plane intersecting with the stacking direction may be referred to as the first direction, and the direction intersecting with the first direction along this plane may be referred to as the second direction. The stacking direction may or may not match the Z direction. Also, the first and second directions may or may not correspond to either the X direction or the Y direction.

[0014] In this specification, expressions such as "upper" and "lower" are based on the substrate. For example, the direction away from the substrate along the Z direction is called "up," and the direction toward the substrate along the Z direction is called "down." Furthermore, when referring to a certain configuration, the lower surface or lower end refers to the surface or end of the configuration facing the substrate, and when referring to the upper surface or upper end, refers to the surface or end of the configuration facing away from the substrate. Furthermore, surfaces that intersect with the X or Y direction are called side surfaces, etc.

[0015] Furthermore, in this specification, the "center position" of a certain feature may mean, for example, the center position of the circumscribing circle of this feature, or may mean the center of gravity of this feature on an image.

[0016] [First embodiment] [Circuit configuration] Fig. 1 is a schematic circuit diagram showing the configuration of a semiconductor memory device according to the first embodiment. As shown in Fig. 1, the semiconductor memory device according to this embodiment includes a memory cell array MCA. The memory cell array MCA includes a plurality of memory layers MLa-MLc (hereinafter, sometimes referred to as "memory layers ML"), a transistor layer TL, a plurality of bit lines BL connected to the plurality of memory layers ML and the transistor layer TL, a plurality of global bit lines GBL electrically connected to the plurality of bit lines BL via the transistor layer TL, and a plate line PL connected to the plurality of memory layers ML.

[0017] Each of the memory layers ML includes a plurality of word lines WL0 to WL2 (hereinafter sometimes referred to as "word lines WL") and a plurality of memory cells MC connected to the plurality of word lines WL0 to WL2. Each of the memory cells MC includes a transistor TrC and a capacitor CpC. One electrode of the transistor TrC is connected to a bit line BL. The other electrode of the transistor TrC is connected to the capacitor CpC. The one and the other electrodes of the transistor TrC function as a source electrode or a drain electrode depending on the voltage supplied to the transistor TrC. The gate electrode of the transistor TrC is connected to one of the word lines WL0 to WL2. One electrode of the capacitor CpC is connected to the other electrode of the transistor TrC. The other electrode of the capacitor CpC is connected to a plate line PL.

[0018] Each bit line BL is connected to a plurality of memory cells MC corresponding to a plurality of memory layers ML.

[0019] The memory layer ML includes a plurality of transistors TrL0a, TrL0b, TrL1a, TrL1b, TrL2a, and TrL2b (hereinafter, sometimes referred to as "transistors TrL") provided corresponding to a plurality of word lines WL0 to WL2. One electrode of the transistor TrL is connected to one of the word lines WL0 to WL2. The other electrode of the transistor TrL is connected to a word line selection line LW0a, LW0b, LW1a, LW1b, LW2a, and LW2b (hereinafter, sometimes referred to as "word line selection line LW"). The one and the other electrodes of the transistor TrL function as a source electrode or a drain electrode depending on the voltage supplied to the transistor TrL. The gate electrodes of the transistors TrL are connected to layer selection lines LL0a, LL0b, LL1a, LL1b, LL2a, and LL2b (hereinafter, sometimes referred to as "layer selection line LL").

[0020] The word line selection line LW is connected to a plurality of transistors TrL corresponding to a plurality of memory layers ML. The layer selection lines LL0a, LL1a, and LL2a are connected in common to all of the transistors TrL0a, TrL1a, and TrL2a corresponding to the plurality of memory layers ML, respectively. Similarly, the layer selection lines LL0b, LL1b, and LL2b are connected in common to all of the transistors TrL0b, TrL1b, and TrL2b corresponding to the memory layers MLa to MLc, respectively.

[0021] The transistor layer TL includes a plurality of bit line selection lines LB0 to LB2 (hereinafter sometimes referred to as "bit line selection lines LB") and a plurality of transistors TrB connected to the plurality of bit line selection lines LB0 to LB2. One electrode of the transistor TrB is connected to a global bit line GBL. The other electrode of the transistor TrB is connected to a bit line BL. The one and the other electrodes of the transistor TrB function as a source electrode or a drain electrode depending on the voltage supplied to the transistor TrB. The gate electrode of the transistor TrB is connected to any one of the bit line selection lines LB0 to LB2.

[0022] The transistor layer TL includes a plurality of transistors TrTa, TrTb (hereinafter, sometimes referred to as "transistors TrT") provided corresponding to the plurality of bit line selection lines LB0 to LB2. One electrode of the transistor TrT is connected to one of the bit line selection lines LB0 to LB2. The other electrode of the transistor TrT is connected to a word line selection line LW. The one and other electrodes of the transistor TrT function as a source electrode or a drain electrode depending on the voltage supplied to the transistor TrT. The gate electrodes of the transistor TrT are connected to wirings LTa, LTb (hereinafter, sometimes referred to as "wirings LT").

[0023] The wiring LTa is commonly connected to all the transistors TrTa, and similarly, the wiring LTb is commonly connected to all the transistors TrTb.

[0024] [Read operation] FIG. 2 is a schematic circuit diagram for explaining the read operation of the semiconductor memory device according to the first embodiment.

[0025] In a read operation, one of the multiple memory layers MLa to MLc is selected. In the illustrated example, the memory layer MLa is selected. When selecting the memory layers MLa to MLc, for example, a voltage V ON ´ and supplies voltage V OFF In addition, for example, among the multiple layer selection lines LL0b, LL1b, and LL2b, a voltage V OFF ´ and supply voltage V ON Also, the voltage V ON ´ and voltage V OFF ´ to supply.

[0026] Voltage VON The voltage V′ has a magnitude sufficient to turn on the transistors TrL and TrT. OFF For example, when the transistors TrL and TrT are NMOS transistors, the voltage V ON ´ is the voltage V OFF For example, when the transistors TrL and TrT are PMOS transistors, the voltage V ON ´ is the voltage V OFF ´ is smaller than.

[0027] In addition, in a read operation, one of the multiple word lines WL0 to WL2 is selected. In the illustrated example, the word line WL0 is selected. When selecting the word line WL0 to WL2, for example, a voltage V ON and supply the voltage V OFF In addition, for example, a voltage V OFF supplies.

[0028] Voltage V ON For example, the voltage V has a magnitude sufficient to turn on the transistors TrC and TrB. OFF For example, when the transistors TrC and TrB are NMOS transistors, the voltage V ON is the voltage V OFF For example, when the transistors TrC and TrB are PMOS transistors, the voltage V ON is the voltage V OFF Less than.

[0029] Here, a voltage V ON This causes the transistor TrC in the selected memory cell MC to be turned on. The transistor TrB connected to the selected memory cell MC is supplied with a voltage V ON is supplied. This turns the transistor TrB to an ON state, and the capacitor CpC in the selected memory cell MC becomes conductive with the global bit line GBL. As a result, the voltage of the global bit line GBL fluctuates, or a current flows through the global bit line GBL. By detecting this voltage fluctuation or current, it is possible to read the data stored in the selected memory cell MC.

[0030] In addition, the word lines WL1 and WL2 other than the selected word line WL0 corresponding to the same memory layer MLa as the selected memory cell MC (hereinafter referred to as "unselected word lines WL1, WL2") are supplied with a voltage V OFF This causes the transistor TrC in the memory cell MC to be turned off. The transistor TrB connected to this memory cell MC is supplied with a voltage V OFF This causes the transistor TrB to be turned off.

[0031] In addition, the unselected word lines WL0, WL1, and WL2 corresponding to the memory layers MLb and MLc different from the selected memory cell MC are supplied with a voltage V OFF As a result, the transistor TrC in the memory cell MC is turned off.

[0032] [Voltage supplied during read operation] 3 is a schematic graph showing the magnitude relationship of the voltages supplied to the word line WL and the layer select line LL in a read operation, where the horizontal axis represents time and the vertical axis represents the magnitude of the voltage.

[0033] In the read operation, in the memory layer ML including the selected memory cell MC, a plurality of transistors TrL (a plurality of transistors TrL0a in the example of FIG. 2) are turned on. Therefore, the gate-source voltage V GS1 ,V GS2 is higher than the threshold voltage of the transistor TrL.

[0034] Among these multiple transistors TrL, the gate-source voltage V GS1 is decreased by increasing the voltage of the selected word line WL, and the voltage V supplied to the layer selection line LL is decreased by increasing the voltage of the selected word line WL. ON ´, the voltage V supplied to the word line selection line LW ON The voltage is the voltage subtracted from the

[0035] Among these multiple transistors TrL, the gate-source voltage V GS2 is the voltage V supplied to the layer selection line LL ON ´, the voltage V supplied to the word line selection line LW OFF is the voltage subtracted from

[0036] In addition, in the read operation, in the memory layer ML including the selected memory cell MC, a plurality of transistors TrL (a plurality of transistors TrL0b in the example of FIG. 2) are turned off. Therefore, the gate-source voltage V GS3 is lower than the threshold voltage of the transistor TrL.

[0037] Among these multiple transistors TrL, the gate-source voltage V GS3 is the voltage V supplied to the layer selection line LL OFF ´, the voltage V supplied to the word line selection line LW OFF The gate-source voltage V GS3 This shows an example where is negative in magnitude.

[0038] [Threshold voltage of transistor TrL] In a read operation, a voltage V ON In order to transfer data at high speed, the gate-source voltage V of the transistor TrL corresponding to the selected memory cell MC must be GS1 It is desirable to keep the voltage V sufficiently higher than the threshold voltage of the transistor TrL to increase the current flowing through the transistor TrL. ON It may be possible to set ' to a large value.

[0039] However, the voltage V ON When ´ is set to a large value, the gate-source voltage V GS2 becomes large, and it becomes necessary to configure the transistor TrL so that it can withstand a higher voltage. To achieve this, it is possible to thicken the gate insulating film of the transistor TrL. However, if the gate insulating film of the transistor TrL is thickened, the length of the entire memory layer ML in the Z direction becomes large, which becomes an obstacle to high integration of the semiconductor memory device.

[0040] Therefore, in this embodiment, the threshold voltage of the transistor TrL is set to a lower value (for example, a value lower than the threshold voltage of the transistor TrC). ON ' to a large value and without hindering high integration of a semiconductor memory device, a voltage V ON It is possible to transfer data at high speed.

[0041] It is also possible to set the threshold voltage of not only the transistor TrL but also the transistor TrC to a lower value. However, if the threshold voltage of the transistor TrC is low, a leakage current may occur in the transistor TrC, which may make it difficult to retain data. For this reason, it is preferable not to set the threshold voltage of the transistor TrC to a lower value.

[0042] [structure] Fig. 4 is a schematic perspective view showing a configuration of a portion of the semiconductor memory device according to this embodiment, which shows a portion of a semiconductor substrate Sub and a memory cell array MCA provided above the semiconductor substrate Sub.

[0043] The semiconductor substrate Sub is, for example, a semiconductor substrate such as silicon (Si) containing a P-type impurity such as boron (B). An insulating layer and an electrode layer (not shown) are provided on the upper surface of the semiconductor substrate Sub. The upper surface of the semiconductor substrate Sub and the insulating layer and electrode layer (not shown) constitute a control circuit for controlling the semiconductor memory device according to the first embodiment. For example, a sense amplifier circuit is provided in a region directly below the memory cell array MCA. The sense amplifier circuit is electrically connected to the bit line BL via the global bit line GBL. In a read operation, the sense amplifier circuit is capable of reading data stored in the selected memory cell MC by detecting a change in voltage or a current of the bit line BL.

[0044] The memory cell array MCA includes a plurality of memory layers ML stacked in the Z direction, a transistor layer TL provided between the memory layer ML and a semiconductor substrate Sub, a wiring layer M0 provided between the transistor layer TL and the semiconductor substrate Sub, and a wiring layer M1 provided between the wiring layer M0 and the semiconductor substrate Sub. Insulating layers 103 such as silicon oxide (SiO2) are provided between the plurality of memory layers ML and between the bottommost memory layer ML and the transistor layer TL.

[0045] 5 is a schematic XY cross-sectional view showing a configuration of a part of the memory layer ML. As shown in FIG. 5, the memory layer ML includes a memory cell region R MC and the transistor area R TrL Although not shown, the transistor region R TrL is a memory cell region R in the Y direction. MC are provided on both sides of the

[0046] [Memory cell area R MC Structure of Next, referring to FIGS. 6, 7, and 10 in addition to FIGS. 4 and 5, the memory cell region R MC The structure of the memory layer ML will be described. Fig. 6 is a schematic XY cross-sectional view showing the configuration of a part of the memory layer ML, and shows an enlarged portion of Fig. 5. Fig. 7 shows a cross-section of the structure shown in Fig. 6 taken along line AA' and viewed in the direction of the arrow. Fig. 10 is a schematic cross-sectional view showing the configuration of the semiconductor memory device according to this embodiment.

[0047] As shown in FIG. 5, the memory cell region R MC has a plurality of insulating layers 101 aligned in the X direction, and a conductive layer 102 provided between two insulating layers 101 adjacent to each other in the X direction. The insulating layers 101 and the conductive layers 102 extend in the Y direction and the Z direction, and divide the plurality of memory layers ML in the X direction (see FIG. 4).

[0048] The insulating layer 101 includes, for example, silicon oxide (SiO2).

[0049] The conductive layer 102 may include, for example, a laminated structure of titanium nitride (TiN) and tungsten (W). It may also include, for example, a conductive oxide. The conductive layer 102 may include ruthenium (Ru), iridium (Ir) or other metals instead of a conductive oxide. The conductive layer 102 may also include only a conductive oxide, or may include only ruthenium (Ru), iridium (Ir) or other metals. The conductive layer 102 functions, for example, as a plate line PL (FIG. 1).

[0050] As used herein, "conductive oxide" includes, for example, indium tin oxide (ITO), indium zinc oxide (IZO), ruthenium oxide (RuO2), iridium oxide (IrO2), or other conductive materials that contain oxygen.

[0051] A plurality of via wirings 104 are provided in the region between the insulating layer 101 and the conductive layer 102. The plurality of via wirings 104 are aligned in the Y direction and extend in the Z direction, penetrating the plurality of memory layers ML, as shown in FIG.

[0052] 7, the via wiring 104 includes, for example, a conductive oxide film 104a including a conductive oxide, a barrier conductive film 104b such as titanium nitride (TiN), and a conductive member 104c such as tungsten (W). The via wiring 104 may include ruthenium (Ru), iridium (Ir), or other metals instead of the conductive oxide film 104a. The via wiring 104 may also include only a conductive oxide, or may include only ruthenium (Ru), iridium (Ir), or other metals.

[0053] The conductive member 104c has a substantially cylindrical shape extending in the Z direction. The barrier conductive film 104b has a substantially cylindrical shape extending in the Z direction along the outer circumferential surface of the conductive member 104c. The conductive oxide film 104a has a substantially cylindrical shape extending in the Z direction along the outer circumferential surface of the barrier conductive film 104b.

[0054] The via wiring 104 functions as, for example, a bit line BL (FIG. 1). As shown in FIG. 1, a plurality of bit lines BL are provided corresponding to a plurality of transistors TrC included in the memory layer ML.

[0055] The memory layer ML includes a plurality of transistor structures 110 corresponding to the plurality of via wirings 104, a conductive layer 120 provided on the opposite side of the conductive layer 102 relative to the plurality of transistor structures 110, and a plurality of capacitor structures 130 provided between the plurality of transistor structures 110 and the conductive layer 102.

[0056] As shown in FIG. 6 , for example, the transistor structure 110 includes a semiconductor layer 111 connected to the outer peripheral surface of the via wiring 104 and extending in the X direction, an insulating layer 112 provided on an upper surface, a lower surface, both side surfaces in the Y direction, and one side surface in the X direction (the conductive layer 120 side) of the semiconductor layer 111, and a conductive layer 113 provided on an upper surface, a lower surface, both side surfaces in the Y direction, and one side surface in the X direction (the conductive layer 120 side) of the insulating layer 112.

[0057] 6, a side surface on one side in the X direction of the semiconductor layer 111 (the conductive layer 102 side) may be formed along a circle centered on the central position of the via wiring 104. In addition, side surfaces on the other side in the X direction of the semiconductor layer 111, the insulating layer 112, and the conductive layer 113 (the conductive layer 120 side) may be formed linearly along the side surface of the conductive layer 120. In addition, both side surfaces in the Y direction of the semiconductor layer 111, the insulating layer 112, and the conductive layer 113 may be formed linearly along the side surface of the insulating layer 115.

[0058] The semiconductor layer 111 functions as, for example, a channel region of the transistor TrC (FIG. 1). The semiconductor layer 111 may be, for example, a semiconductor containing at least one element of gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O), or may be another oxide semiconductor. The multiple semiconductor layers 111 aligned in the Z direction are commonly connected to a via wiring 104 extending in the Z direction.

[0059] The insulating layer 112 functions as, for example, a gate insulating film of the transistor TrC (FIG. 1). The insulating layer 112 includes, for example, silicon oxide (SiO2).

[0060] The conductive layer 113 functions as, for example, a gate electrode of the transistor TrC (FIG. 1). The conductive layer 113 includes, for example, a conductive oxide such as titanium nitride (TiN) or indium tin oxide (ITO). The multiple conductive layers 113 aligned in the Y direction are commonly connected to a conductive layer 120 extending in the Y direction (see FIG. 5). The conductive layer 113 faces the upper surface, the lower surface, both side surfaces in the Y direction, and one side surface in the X direction (the conductive layer 120 side) of the semiconductor layer 111 via the insulating layer 112.

[0061] An insulating layer 115 made of silicon oxide (SiO2) or the like is provided between two semiconductor layers 111 adjacent to each other in the Y direction. The insulating layer 115 extends in the Z direction, penetrating the multiple memory layers ML.

[0062] The conductive layer 120 functions as, for example, a word line WL (FIG. 1). The conductive layer 120 extends in the Y direction and is connected to a plurality of conductive layers 113 arranged in the Y direction. The conductive layer 120 includes, for example, a barrier conductive film 121 made of titanium nitride (TiN) or the like, and a conductive film 122 made of tungsten (W).

[0063] As shown in FIGS. 6 and 7 , the capacitor structure 130 includes a conductive layer 131, an insulating layer 132 provided on an upper surface, a lower surface, both side surfaces in the Y direction, and one side surface in the X direction (the transistor structure 110 side) of the conductive layer 131, and a conductive layer 133 provided on an upper surface, a lower surface, both side surfaces in the Y direction, and one side surface in the X direction (the transistor structure 110 side) of the insulating layer 132.

[0064] The conductive layer 131 functions as one electrode of the capacitor CpC (FIG. 1). The conductive layer 131 can include, for example, a laminated structure of titanium nitride (TiN) and tungsten (W). It may also include, for example, a conductive oxide. The conductive layer 131 may include ruthenium (Ru), iridium (Ir) or other metals instead of a conductive oxide. The conductive layer 131 may also include only a conductive oxide, or may include only ruthenium (Ru), iridium (Ir) or other metals. The conductive layer 131 is continuous with the conductive layer 102.

[0065] The insulating layer 132 functions as an insulating layer for the capacitor CpC (FIG. 1). The insulating layer 132 may be, for example, zirconia (ZrO2), alumina (Al2O3), or other insulating metal oxide. The insulating layer 132 may also be, for example, a laminated film of multiple insulating metal oxides (for example, a laminated film of zirconia and alumina).

[0066] The conductive layer 133 functions as, for example, the other electrode of the capacitor CpC (FIG. 1). The conductive layer 133 includes, for example, a conductive oxide such as indium tin oxide (ITO). The conductive layer 133 is insulated from the conductive layer 131 via the insulating layer 132. The conductive layer 133 is connected to a side surface of the semiconductor layer 111 in the X direction.

[0067] The transistor layer TL is configured similarly to the memory layer ML. However, in the example of FIG. 10, the length in the Z direction of the transistor layer TL is greater than the length in the Z direction of the memory layer ML. Also, the length in the Z direction of the insulating layer 103 provided between the transistor layer TL and the memory layer ML adjacent to the transistor layer TL is greater than the length in the Z direction of the other insulating layers 103. The semiconductor layer 111, the insulating layer 112, and the conductive layer 113 in the transistor layer TL function as the channel region, the gate insulating film, and the gate electrode of the transistor TrB, respectively. Also, the conductive layer 120 in the transistor layer TL functions as the bit line selection line LB. Also, the conductive layer 133 in the transistor layer TL functions as the source electrode or the drain electrode of the transistor TrB.

[0068] The length in the Z direction of the insulating layer 112 and the conductive layer 113 in the transistor layer TL is the same as the length in the Z direction of the insulating layer 112 and the conductive layer 113 in the memory layer ML. On the other hand, the length in the Z direction of the semiconductor layer 111 in the transistor layer TL is greater than the length in the Z direction of the semiconductor layer 111 in the memory layer ML. With this configuration, it is possible to suppress the deterioration of the mobility of electrons in the semiconductor layer 111 in the transistor layer TL, increase the current in the ON state of the transistor TrB, and transfer the voltage to the bit line BL and the global bit line GBL at high speed. In addition, since there is no need to increase the length in the Z direction of the memory layer ML, this configuration can be realized without hindering high integration in the Z direction of the memory cell array MCA.

[0069] 4, the wiring layer M1 includes a plurality of global bit lines GBL aligned in the Y direction and extending in the X direction. The wiring layer M0 is provided corresponding to the plurality of conductive layers 133 and includes a plurality of wirings m0 aligned in the Y direction.

[0070] The wiring m0 is connected to the conductive layer 133 in the transistor layer TL through a via contact electrode V0 extending in the Z direction. The via contact electrode V0 is provided at a position overlapping the conductive layer 133 and the wiring m0 when viewed from the Z direction, and has an upper end connected to the conductive layer 133 and a lower end connected to the wiring m0.

[0071] Moreover, the wiring m0 is electrically connected to the global bit line GBL through a via contact electrode V1 extending in the Z direction. The via contact electrode V1 is provided at a position overlapping the global bit line GBL and the wiring m0 when viewed from the Z direction, and has a lower end connected to the global bit line GBL and an upper end connected to the wiring m0.

[0072] [Transistor area R TrL Structure of Next, referring to FIGS. 8 and 9 in addition to FIGS. 4 and 5, the transistor region R TrLThe structure of the memory layer ML will be described. Fig. 8 is a schematic XY cross-sectional view showing a configuration of a part of the memory layer ML, and shows an enlarged part of Fig. 5. Fig. 9 shows a cross section of the structure shown in Fig. 8 taken along line BB' and viewed in the direction of the arrow.

[0073] As shown in Figure 5, the transistor region R TrL is provided with a plurality of insulating layers 151 aligned in the X direction corresponding to the plurality of insulating layers 101, and an insulating layer 152 provided between two insulating layers 151 adjacent in the X direction. The insulating layer 151 has a portion extending in the Y direction and the Z direction, and a portion extending in the X direction and the Z direction. The insulating layer 152 extends in the Y direction and the Z direction. The portion of the insulating layer 151 extending in the Y direction and the Z direction and the insulating layer 152 divide the plurality of memory layers ML in the X direction. The portion of the insulating layer 151 extending in the X direction and the Z direction divides the plurality of memory layers ML in the Y direction. The insulating layer 151 and the insulating layer 152 include, for example, silicon oxide (SiO2) or the like.

[0074] In addition, the memory cell region R MC and the transistor area R TrL An insulating layer 165 is provided between the conductive layers 120 and extending in the X direction in a range between two conductive layers 120 adjacent in the X direction. The insulating layer 165 extends in the X direction and the Z direction, and divides the multiple memory layers ML in the Y direction. The insulating layer 165 includes, for example, silicon oxide (SiO2) or the like.

[0075] Moreover, the insulating layer 151 is divided in the Y direction via an insulating layer 153. The insulating layer 153 extends in the Z direction, penetrating the multiple memory layers ML. The insulating layer 153 includes, for example, silicon oxide (SiO2) or the like.

[0076] A plurality of via wirings 154 are provided in the region between the insulating layer 151 and the insulating layer 152. The plurality of via wirings 154 are aligned in the Y direction and extend in the Z direction, penetrating a plurality of memory layers ML, as shown in FIG.

[0077] 9, the via wiring 154 includes, for example, a conductive oxide film 154a including a conductive oxide, a barrier conductive film 154b such as titanium nitride (TiN), and a conductive member 154c such as tungsten (W). The via wiring 154 may include ruthenium (Ru), iridium (Ir), or other metals instead of the conductive oxide film 154a. The via wiring 154 may also include only a conductive oxide, or may include only ruthenium (Ru), iridium (Ir), or other metals.

[0078] The conductive member 154c has a generally cylindrical shape extending in the Z direction. The barrier conductive film 154b has a generally cylindrical shape extending in the Z direction along the outer circumferential surface of the conductive member 154c. The conductive oxide film 154a has a generally cylindrical shape extending in the Z direction along the outer circumferential surface of the barrier conductive film 154b.

[0079] The via wirings 154 arranged in the Y direction function as, for example, one word line selection line LW (FIG. 1). As shown in FIG. 1, the word line selection line LW is provided in a plurality of lines corresponding to the word lines WL included in the memory layer ML.

[0080] The memory layer ML includes a plurality of transistor structures 160 corresponding to a plurality of conductive layers 120, a wiring 171 provided between the transistor structures 160 and an insulating layer 151, and a wiring 172 provided between the transistor structures 160 and an insulating layer 152.

[0081] As shown in FIG. 8 , the transistor structure 160 includes a semiconductor layer 161 connected to the outer peripheral surfaces of the via wirings 154 and extending in the Y direction along the outer peripheral surfaces of the via wirings 154, an insulating layer 162 provided on the upper surface, lower surface, both side surfaces in the Y direction, and one side surface in the X direction (the insulating layer 152 side) of the semiconductor layer 161, and a conductive layer 163 provided on the upper surface, lower surface, both side surfaces in the Y direction, and one side surface in the X direction (the insulating layer 152 side) of the insulating layer 162.

[0082] In the XY cross section as illustrated in Fig. 8, the side surface of one side in the X direction of the semiconductor layer 161 (the insulating layer 151 side) may be formed along a plurality of overlapping circles centered on the central positions of the via wirings 154. Furthermore, the side surfaces of the other side in the X direction of the semiconductor layer 161, the insulating layer 162, and the conductive layer 163 (the insulating layer 152 side) may be formed linearly along the side surface of the wiring 172. Furthermore, both side surfaces in the Y direction of the semiconductor layer 161, the insulating layer 162, and the conductive layer 163 may be formed linearly along the portions of the insulating layer 165 and the insulating layer 151 described with reference to Fig. 5 that extend in the X direction and the Z direction.

[0083] The semiconductor layer 161 functions as, for example, a channel region of the transistor TrL (FIG. 1). The semiconductor layer 161 may be, for example, a semiconductor containing at least one element of gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O), or may be another oxide semiconductor. The multiple semiconductor layers 161 aligned in the Z direction are commonly connected to a via wiring 154 extending in the Z direction.

[0084] Here, the concentration of indium in the semiconductor layer 161 is greater than the concentration of indium in the semiconductor layer 111. Moreover, the concentration of gallium in the semiconductor layer 161 is equal to or less than the concentration of gallium in the semiconductor layer 111. As a result, the threshold voltage of the transistor TrL (FIG. 1) becomes lower than the threshold voltage of the transistor TrC (FIG. 1).

[0085] The insulating layer 162 functions as, for example, a gate insulating film of the transistor TrL (FIG. 1). The insulating layer 162 includes, for example, silicon oxide (SiO2).

[0086] The conductive layer 163 functions as, for example, a gate electrode of the transistor TrL (FIG. 1). The conductive layer 163 includes, for example, a conductive oxide such as titanium nitride (TiN) or indium tin oxide (ITO). One side surface in the X direction of the conductive layer 163 (the insulating layer 152 side) is connected to the wiring 172. The conductive layer 163 faces the upper surface, the lower surface, both side surfaces in the Y direction, and the side surface in the X direction (the insulating layer 152 side) of the semiconductor layer 161 via the insulating layer 162.

[0087] The wiring 171 is connected to the conductive layer 120 and the semiconductor layer 161, and has a function of connecting the word line WL (FIG. 1) and the drain electrode of the transistor TrL (FIG. 1). The wiring 171 includes, for example, a conductive oxide. Note that the wiring 171 may include ruthenium (Ru), iridium (Ir), or other metals instead of a conductive oxide. The wiring 171 may include only a conductive oxide, or may include only ruthenium (Ru), iridium (Ir), or other metals.

[0088] The wiring 171 includes, for example, a portion formed on the lower surface of the insulating layer 103 via a portion of the insulating layer 162, a portion formed on the upper surface of the insulating layer 103 via a portion of the insulating layer 162, a portion formed on a side surface in the X direction of the conductive layer 120, and a portion formed on a side surface in the X direction of the semiconductor layer 161. Furthermore, a semiconductor layer 173 such as silicon (Si) may be provided in the region surrounded by the wiring 171.

[0089] 5, the wiring 172 has a portion extending in the Y direction and a portion extending in the X direction. The portion of the wiring 172 extending in the Y direction is connected to the conductive layer 163. The wiring 172 functions as a layer selection line LL (FIG. 1). The wiring 172 includes, for example, a conductive oxide. Note that the wiring 172 may include ruthenium (Ru), iridium (Ir), or other metals instead of a conductive oxide. The wiring 172 may include only a conductive oxide, or may include only ruthenium (Ru), iridium (Ir), or other metals.

[0090] The wiring 172 includes, for example, a portion formed on the lower surface of the insulating layer 103, a portion formed on the upper surface of the insulating layer 103, and a portion formed on the X-direction side surface of the conductive layer 163. Furthermore, an insulating layer 174 such as silicon oxide (SiO2) may be provided in the region surrounded by the wiring 172.

[0091] The transistor layer TL is configured similarly to the memory layer ML. However, the semiconductor layer 161, the insulating layer 162, and the conductive layer 163 in the transistor layer TL function as the channel region, the gate insulating film, and the gate electrode of the transistor TrT, respectively. The wiring 171 in the transistor layer TL functions as the bit line selection line LB. The wiring 172 in the transistor layer TL functions as the wiring LT.

[0092] [Manufacturing method] 11 to 77 are schematic cross-sectional views illustrating the method for manufacturing the semiconductor memory device according to the first embodiment.

[0093] Figures 11, 14, 16, 18, 21, 23, 25, 27, 29, 31, 33, 35, 37, 40, 41, 43, 45, 47, 49, 51, 53, 55, 57 to 60, 65, 67, 69, 71 to 73 and 76 show cross sections corresponding to Figure 7.

[0094] 12, 13, 20 and 39 show cross sections corresponding to FIG.

[0095] Figures 15, 17, 19, 22, 24, 26, 28, 30, 32, 34, 36, 38, 42, 44, 46, 48, 50, 52, 54, 56, 61 to 64, 66, 68, 70, 74, 75 and 77 show cross sections corresponding to Figure 9.

[0096] In this manufacturing method, for example, as shown in Fig. 11, a plurality of insulating layers 103 and a plurality of sacrificial layers MLA are alternately formed. The sacrificial layers MLA include, for example, silicon nitride (Si3N4) etc. This process is performed, for example, by CVD (Chemical Vapor Deposition) etc.

[0097] Next, as shown in FIG. 12, insulating layers 115, 151, and 165 are formed. In this step, for example, openings are formed at positions corresponding to the insulating layers 115, 151, and 165. These openings extend in the Z direction and penetrate the multiple insulating layers 103 and the multiple sacrificial layers MLA stacked in the Z direction. This step is performed by, for example, RIE. After the openings are formed, the insulating layers 115, 151, and 165 are formed. This step is performed by, for example, CVD.

[0098] Next, as shown in Figures 13 to 15, for example, openings 104A, 154A are formed at positions corresponding to the via wirings 104, 154. The openings 104A, 154A extend in the Z direction as shown in Figures 13 to 15, and penetrate the multiple insulating layers 103 and the multiple sacrificial layers MLA stacked in the Z direction. This step is performed by, for example, RIE or the like.

[0099] Next, as shown in, for example, FIGS. 16 and 17, an oxidation process is performed on the surfaces of the sacrificial layer MLA exposed to the openings 104A and 154A to form an oxide film MLB.

[0100] 18 and 19, sacrificial layers 104B, 154B made of silicon (Si) or the like are formed inside the openings 104A, 154A. This process is performed by, for example, CVD or the like.

[0101] 20 to 22, openings 101A and 152A are formed at positions corresponding to the insulating layers 101 and 152. The openings 101A and 152A extend in the Y and Z directions, penetrating the insulating layers 103 and the sacrificial layers MLA stacked in the Z direction, and dividing these structures in the X direction. This process is performed by, for example, RIE or the like.

[0102] Next, as shown in Figs. 23 and 24, openings 120A and 172A are formed at positions corresponding to the conductive layer 120 and the wiring 172. Part of the upper surface and part of the lower surface of the insulating layer 103 and part of the side surface in the X direction of the sacrificial layer MLA are exposed inside the openings 120A and 172A. In this step, for example, a part of the sacrificial layer MLA is selectively removed through the openings 101A and 152A. This step is performed by, for example, wet etching or the like. The openings 120A and 172A do not communicate with the openings 104A and 154A.

[0103] 25 and 26, a sacrificial layer 120B such as silicon (Si) is embedded in the openings 101A and 120A. Also, a sacrificial layer 172B such as silicon (Si) is embedded in the openings 152A and 172A. This process is performed by, for example, CVD.

[0104] Next, the sacrificial layers 104B and 154B are removed as shown in Figures 27 and 28. This step is performed by, for example, wet etching.

[0105] 29 and 30, the oxide film MLB is removed by, for example, wet etching.

[0106] Next, as shown in, for example, Figures 31 and 32, openings 111A, 161A are formed at positions corresponding to the semiconductor layers 111, 161. In the openings 111A, 161A, a part of the upper surface and a part of the lower surface of the insulating layer 103, a part of the side surface in the X direction of the sacrificial layer MLA, a part of the side surface in the Y direction of the insulating layers 115, 151, 165 (see Figure 20), and a part of the side surface in the X direction of the sacrificial layers 120B, 172B are exposed. In this step, for example, a part of the sacrificial layer MLA is selectively removed through the openings 104A, 154A. This step is performed by, for example, wet etching or the like.

[0107] Next, as shown in, for example, FIGS. 33 and 34, an oxidation process is performed on the surfaces of the sacrificial layers MLA, 120B, and 172B exposed to the openings 104A and 154A to form oxide films MLB.

[0108] Next, as shown in FIG. 35 and FIG. 36, conductive layers 113A and 163A are formed inside the openings 111A and 161A. In this step, for example, a conductive film such as titanium nitride (TiN) and a sacrificial layer such as silicon (Si) are formed inside the openings 104A and 111A and inside the openings 154A and 161A. This step is performed so that the openings 111A and 161A are filled with the sacrificial layer and the openings 104A and 154A are not filled with the sacrificial layer. Next, a part of the sacrificial layer is removed inside the openings 104A and 154A to expose a part of the conductive film (a part formed on the side of the insulating layer 103). Next, a part of the conductive film is removed to divide the conductive film in the Z direction to form the conductive layers 113A and 163A. Then, the sacrificial layer is removed.

[0109] 37 and 38, sacrificial layers 104B and 154B made of silicon (Si) or the like are embedded in the openings 104A and 154A. This process is performed by, for example, CVD or the like.

[0110] Next, as shown in Fig. 39 and Fig. 40, for example, an opening 102A is formed at a position corresponding to the conductive layer 102. The opening 102A extends in the Y direction and the Z direction, and penetrates the insulating layers 103 and the sacrificial layers MLA stacked in the Z direction, as well as the insulating layer 115, to divide these structures in the X direction. Also, an opening 153A is formed at a position corresponding to the insulating layer 153. The opening 153A extends in the Z direction, and penetrates the insulating layers 103 and the sacrificial layers MLA stacked in the Z direction, as well as the insulating layer 151. This process is performed by, for example, RIE or the like.

[0111] Next, as shown in Fig. 41, for example, an opening 131A is formed at a position corresponding to the capacitor structure 130. Also, as shown in Fig. 42, an opening 171A is formed at a position corresponding to the wiring 171. In this step, the sacrificial layer MLA is removed through the openings 102A and 153A. This step is performed by, for example, wet etching or the like.

[0112] 43 and 44, a part of the oxide film MLB is removed through the openings 131A and 171A. This step is performed by, for example, wet etching or the like.

[0113] Next, the conductive layers 113 and 163 are formed, for example, as shown in Fig. 45 and Fig. 46. In this step, a part of the conductive layer 113A is removed through the opening 131A. Also, in this step, a part of the conductive layer 163A is removed through the opening 171A. This step is performed by, for example, wet etching or the like.

[0114] Next, the sacrificial layers 104B and 154B are removed as shown in Figures 47 and 48. This step is performed by, for example, wet etching.

[0115] Next, as shown in Fig. 49, for example, an insulating layer 112 is formed inside the openings 111A, 104A, 131A, and 102A. Furthermore, as shown in Fig. 50, for example, an insulating layer 162 is formed inside the openings 171A, 161A, and 154A. The insulating layers 112 and 162 are formed on the upper and lower surfaces of the conductive layers 113 and 163, part of the upper surface, part of the lower surface, and the surface exposed to the openings 104A and 154A of the insulating layer 103, part of the side surface of the sacrificial layer 120B in the X direction, and part of the side surface of the insulating layers 115 and 165 in the Y direction.

[0116] Next, as shown in FIG. 51, for example, a sacrificial layer 111B of silicon nitride (Si3N4) or the like is formed inside the openings 111A, 104A, 131A, and 102A. Also, as shown in FIG. 52, for example, a sacrificial layer 161B of silicon nitride (Si3N4) or the like is formed inside the openings 171A, 161A, and 154A. The openings 111A and 161A are filled with the sacrificial layers 111B and 161B, and the openings 102A, 104A, 131A, 154A, and 171A are not filled with the sacrificial layers 111B and 161B. This process is performed by, for example, CVD or the like. Although not shown, after the formation of the sacrificial layers 111B and 161B, the upper portions of the openings 104A and 154A are blocked by an insulating layer or the like.

[0117] Next, as shown in Figures 53 and 54, parts of the sacrificial layers 111B and 161B are removed through the openings 102A and 153A (Figure 39). This step is performed by, for example, wet etching.

[0118] Next, as shown in Fig. 55, for example, a conductive layer 133A is formed on one side in the X direction of the sacrificial layer 111B (side on the opening 102A side), the upper and lower surfaces and one side in the X direction of the insulating layer 112 (side on the opening 102A side), and the side in the Y direction, through the opening 102A and the opening 131A. Also, as shown in Fig. 56, for example, a conductive layer 171B is formed on one side in the X direction of the sacrificial layer 161B (side on the opening 171A side), the upper and lower surfaces and one side in the X direction of the insulating layer 162 (side on the opening 171A side), and the side in the Y direction, through the opening 153A (Fig. 39) and the opening 171A. This process is performed by, for example, ALD (Atomic Layer Deposition) or the like.

[0119] Next, as shown in Fig. 57, for example, a sacrificial layer 131B of silicon (Si) or the like is formed inside opening 102A. Opening 131A is filled with sacrificial layer 131B, and opening 102A is not filled with sacrificial layer 131B. Furthermore, although not shown, a sacrificial layer of silicon (Si) or the like is formed inside opening 171A. Opening 171A is filled with the sacrificial layer, and opening 153A (Fig. 39) is not filled with the sacrificial layer. This process is performed by, for example, CVD or the like.

[0120] Also, as shown in FIG. 58, the conductive layer 133 is formed. In this step, for example, the sacrificial layer 131B is removed from the side surfaces of the insulating layer 115 and the insulating layer 103 in the X direction to expose a part of the conductive layer 133A. In addition, the conductive layer 133A is removed from the side surfaces of the insulating layer 115 and the insulating layer 103 in the X direction to divide the conductive layer 133A in the Y direction and the Z direction. This step is performed by, for example, wet etching or the like. Although not shown, in this step, the conductive layer 171B is divided in the Z direction, thereby forming the wiring 171. After the conductive layer 133 is formed, the upper part of the opening 153A (FIG. 39) is closed by an insulating layer or the like.

[0121] Next, the sacrificial layer 131B is removed as shown in Fig. 59. This step is performed by, for example, wet etching.

[0122] 60, for example, insulating layer 132 and conductive layer 131 are formed on the upper surface, lower surface, one side surface in the X direction (the side surface on the opening 102A side), both side surfaces in the Y direction of conductive layer 133, and the X direction side surfaces of insulating layer 115 and insulating layer 103 through opening 131A and opening 102A. This process is performed by, for example, CVD or the like.

[0123] 61, a semiconductor layer 173 is formed on the upper surface, lower surface, and side surfaces in the X direction and Y direction of the wiring 171 through the opening 153A (FIG. 39) and the opening 171A. This process is performed by, for example, CVD or the like.

[0124] Next, the sacrificial layer 172B is removed, for example, as shown in Fig. 61. This step is performed by, for example, wet etching or the like.

[0125] Next, the oxide film MLB is removed as shown in Fig. 62. This step is performed by, for example, wet etching.

[0126] Next, for example, as shown in Fig. 63, the wiring 172 is formed. This step is performed by a method similar to the steps described with reference to Figs.

[0127] Next, as shown in Fig. 64, for example, an insulating layer 174 is formed. This step is performed by a method such as CVD.

[0128] Next, the sacrificial layer 120B is removed, for example, as shown in Figures 65 and 66. This step is performed by, for example, wet etching or the like.

[0129] 67 and 68, the oxide film MLB and a part of the insulating layer 162 (the part exposed in the opening 120A) are removed. This step is performed by, for example, wet etching or the like.

[0130] Next, as shown in Figures 69 and 70, for example, a conductive layer 120 is formed. This process is performed by a method such as CVD.

[0131] 71, the sacrificial layer 111B is removed from the inside of the opening 104A. This step is performed by, for example, wet etching.

[0132] 72, a semiconductor layer 111 is formed inside the openings 111A and 104A. The opening 111A is filled with the semiconductor layer 111. On the other hand, the opening 104A is not filled with the semiconductor layer 111. This step is performed by, for example, ALD or the like.

[0133] Next, as shown in FIG. 73, for example, a resist 104C is formed inside the opening 104A.

[0134] 74, the sacrificial layer 161B is removed from the inside of the opening 154A. This step is performed by, for example, wet etching.

[0135] 75, for example, a semiconductor layer 161 is formed inside the openings 161A and 154A. The opening 161A is filled with the semiconductor layer 161. On the other hand, the opening 154A is not filled with the semiconductor layer 161. This step is performed by, for example, ALD or the like.

[0136] Next, as shown in FIG. 76, for example, the resist 104C is removed.

[0137] Next, as shown in Fig. 76, a conductive oxide film 104a is formed inside the opening 104A. Also, as shown in Fig. 77, a conductive oxide film 154a is formed inside the opening 154A. This process is performed by, for example, ALD or the like.

[0138] Thereafter, for example, as shown in Fig. 7, a barrier conductive film 104b and a conductive member 104c are formed inside the opening 104A. Further, for example, as shown in Fig. 9, a barrier conductive film 154b and a conductive member 154c are formed inside the opening 154A. This step is performed by a method such as CVD. As a result, the structure described with reference to Figs. 4 to 10 is formed.

[0139] [Second embodiment] In the first embodiment, the composition ratio of the material contained in the semiconductor layer 111 in the transistor layer TL is the same as the composition ratio of the material contained in the semiconductor layer 111 in the memory layer ML. However, such a configuration is merely an example, and the specific configuration of the transistor layer TL can be adjusted as appropriate. For example, the composition ratio of the material contained in the semiconductor layer 111 in the transistor layer TL may be different from the composition ratio of the material contained in the semiconductor layer 111 in the memory layer ML. This makes it possible to set the threshold voltage of the transistor TrB to a lower value (for example, a value lower than the threshold voltage of the transistor TrC). Hereinafter, such a configuration will be exemplified as a semiconductor memory device according to the second embodiment.

[0140] [composition] 78 is a schematic cross-sectional view showing a configuration of a portion of the semiconductor memory device according to the second embodiment. In the following description, the same parts as those in the first embodiment are given the same reference numerals, and description thereof will be omitted.

[0141] The semiconductor memory device according to the second embodiment is basically configured similarly to the semiconductor memory device according to the first embodiment, except that the semiconductor memory device according to the second embodiment includes a transistor layer TL2 instead of the transistor layer TL.

[0142] The transistor layer TL2 is basically configured in the same manner as the transistor layer TL, except that the transistor layer TL2 includes a transistor structure 210 instead of the transistor structure 110.

[0143] The transistor structure 210 is basically configured in the same manner as the transistor structure 110. However, the transistor structure 210 includes a semiconductor layer 211 instead of the semiconductor layer 111.

[0144] The semiconductor layer 211 is basically configured in the same manner as the semiconductor layer 111. However, the concentration of indium in the semiconductor layer 211 is greater than the concentration of indium in the semiconductor layer 111. Moreover, the concentration of gallium in the semiconductor layer 211 is equal to or less than the concentration of gallium in the semiconductor layer 111. As a result, the threshold voltage of the transistor TrB (FIG. 1) becomes lower than the threshold voltage of the transistor TrC (FIG. 1).

[0145] [Manufacturing method] Next, a method for manufacturing the semiconductor memory device according to the second embodiment will be described. Here, an example is shown in which the configuration of the memory cell array MCA, the semiconductor substrate Sub (FIG. 4), and the above-mentioned control circuit are formed on separate wafers, and the semiconductor memory device according to the second embodiment is manufactured by bonding these two wafers.

[0146] 79 to 84 are schematic cross-sectional views illustrating the method for manufacturing the semiconductor memory device according to the second embodiment.

[0147] In manufacturing the semiconductor memory device according to the second embodiment, for example, the steps described with reference to Figures 11 to 72 are performed. However, these steps are performed above a wafer (not shown) such that a structure located above in the memory cell array MCA is provided below, and a structure located below is provided above. For example, in the step described with reference to Figure 11, first, a plurality of sacrificial layers MLA corresponding to the memory layer ML are formed, and then a sacrificial layer MLA corresponding to the transistor layer TL is formed.

[0148] Next, a sacrificial layer 204A is formed inside the opening 104A as shown in Fig. 79. This process is performed by, for example, CVD or the like.

[0149] 80, a part of the sacrificial layer 204A is removed to expose a part of the semiconductor layer 111 that is provided at a position corresponding to the transistor layer TL inside the opening 104A. This step is performed by, for example, wet etching or the like.

[0150] 81, a portion of the semiconductor layer 111 that is provided at a position corresponding to the transistor layer TL is removed. This step is performed by, for example, wet etching or the like.

[0151] 82, a semiconductor layer 211A is formed inside the openings 111A and 104A and on the upper surface of the sacrificial layer 204A. The opening 111A is filled with the semiconductor layer 211A. On the other hand, the opening 104A is not filled with the semiconductor layer 211A. This process is performed by, for example, ALD or the like.

[0152] 83, the portion of the semiconductor layer 211A provided on the upper surface of the sacrificial layer 204A is removed, thereby forming the semiconductor layer 211. This step is performed by, for example, RIE or the like.

[0153] Next, the sacrificial layer 204A is removed as shown in Fig. 84. This step is performed by, for example, wet etching.

[0154] Next, by performing the steps of the manufacturing method according to the first embodiment, which are subsequent to the step described with reference to Fig. 72, the memory cell array MCA of the semiconductor memory device according to the second embodiment is formed. The wafer on which the memory cell array MCA is formed is then turned upside down and bonded to a wafer on which the semiconductor substrate Sub (Fig. 4) and the above-mentioned control circuit are formed. This completes the manufacture of the semiconductor memory device according to the second embodiment.

[0155] [Third embodiment] In the first embodiment, as described with reference to Figs. 71 to 75, the semiconductor layer 111 and the semiconductor layer 161, which have different compositions, are formed in separate steps. In the second embodiment, as described with reference to Figs. 79 to 84, the semiconductor layer 111 and the semiconductor layer 211, which have different compositions, are formed in separate steps. However, such a method is merely an example, and the method for forming the semiconductor layers, which have different compositions, can be appropriately adjusted, and for example, they can be formed in a lump. This makes it possible to reduce the number of manufacturing steps. Below, such a configuration is illustrated as a semiconductor memory device according to the third embodiment.

[0156] [composition] 85 and 86 are schematic cross-sectional views showing a configuration of a portion of the semiconductor memory device according to the third embodiment. In the following description, the same parts as those in the second embodiment are denoted by the same reference numerals, and description thereof will be omitted.

[0157] The semiconductor memory device according to the third embodiment is basically configured in the same manner as the semiconductor memory device according to the second embodiment.

[0158] However, the semiconductor memory device according to the third embodiment includes a memory layer ML3 and a transistor layer TL3 instead of the memory layer ML and the transistor layer TL2.

[0159] The memory layer ML3 and the transistor layer TL3 are basically configured in the same manner as the memory layer ML and the transistor layer TL2. However, the memory layer ML3 includes a transistor structure 360 ​​instead of the transistor structure 160. Moreover, the transistor layer TL3 includes a transistor structure 310 instead of the transistor structure 210.

[0160] The transistor structure 360 ​​is basically configured in the same manner as the transistor structure 160. However, the transistor structure 360 ​​includes a semiconductor layer 361 and an insulating layer 362 instead of the semiconductor layer 161 and the insulating layer 162.

[0161] The semiconductor layer 361 is basically configured in the same manner as the semiconductor layer 161. However, the length of the semiconductor layer 161 in the Z direction is equal to the length of the semiconductor layer 111 in the Z direction. On the other hand, the length of the semiconductor layer 361 in the Z direction is greater than the length of the semiconductor layer 111 in the Z direction.

[0162] In addition, the upper and lower surfaces of the semiconductor layer 361 and the region R SL and a region R in the vicinity of the center position of the semiconductor layer 361 in the Z direction. CL When we focus on and, the area R CL The concentration of indium in the region R SL The concentration of indium in the region R CL The concentration of gallium in the region R SL The concentration of gallium in the region R SL and region R CL Thus, the concentrations of indium and gallium may be equal.

[0163] The insulating layer 362 is basically configured in the same manner as the insulating layer 162. However, the film thickness of the insulating layer 162 (the distance between the semiconductor layer 161 and the conductive layer 163) is equal to the film thickness of the semiconductor layer 111 (the distance between the semiconductor layer 111 and the conductive layer 113). On the other hand, the film thickness of the insulating layer 362 (the distance between the semiconductor layer 361 and the conductive layer 163) is smaller than the film thickness of the semiconductor layer 111.

[0164] The transistor structure 310 is basically configured in the same manner as the transistor structure 210. However, the transistor structure 310 includes a semiconductor layer 311 instead of the semiconductor layer 211.

[0165] The semiconductor layer 311 is basically configured in the same manner as the semiconductor layer 211. However, the upper surface, the lower surface, and the region R in the vicinity of the conductive layer 133 of the semiconductor layer 311 are SB and a region R in the vicinity of the center position of the semiconductor layer 311 in the Z direction. CB When we focus on and, the area R CB The concentration of indium in the region R SB The concentration of indium in the region R CB The concentration of gallium in the region R SB The concentration of gallium in the region R SB and region R CB Thus, the concentrations of indium and gallium may be equal.

[0166] [Manufacturing method] 87 and 88 are schematic cross-sectional views for explaining a method for manufacturing the semiconductor memory device according to the third embodiment.

[0167] In manufacturing the semiconductor memory device according to the third embodiment, for example, the steps described with reference to FIGS. 11 to 70 are performed.

[0168] Next, as shown in Fig. 71, sacrificial layer 111B is removed from inside opening 104A. Also, as shown in Fig. 74, sacrificial layer 161B is removed from inside opening 154A. This step is performed by, for example, wet etching. Although not shown, after removing sacrificial layers 111B and 161B, the upper part of opening 104A is closed with an insulating layer or the like.

[0169] 87, inside the opening 154A, a part of the insulating layer 112 is removed to thin the insulating layer 112, thereby forming an insulating layer 362. This step is performed by, for example, wet etching or the like.

[0170] Next, after removing the insulating layer and the like from above the opening 104A, a semiconductor layer 111 is formed inside the openings 111A and 104A, as shown in FIG. 72, for example. The opening 111A is filled with the semiconductor layer 111. On the other hand, the opening 104A is not filled with the semiconductor layer 111. Furthermore, as shown in FIG. 88, for example, a semiconductor layer 361 is formed inside the openings 161A and 154A. The opening 161A is filled with the semiconductor layer 361. On the other hand, the opening 154A is not filled with the semiconductor layer 361. This process is performed by, for example, ALD or the like.

[0171] In this process, the concentration of indium is increased continuously or stepwise from the start of film formation to the end of film formation, and the concentration of gallium may be decreased continuously or stepwise.

[0172] Here, at the timing after the process described with reference to FIG. 87 is performed, the length of the opening 161A in the Z direction is greater than the length of the opening 111A (FIG. 71) in the Z direction. Therefore, if films are simultaneously formed inside the openings 111A and 161A, the opening 111A will be closed first. Therefore, after the opening 111A is closed, the concentration of indium in the semiconductor layer 361 is increased and the concentration of gallium is maintained or decreased, so that the above-mentioned region R is formed inside the semiconductor layer 361. CL It is possible to form

[0173] 86, the length in the Z direction of the semiconductor layer 111 in the transistor layer TL is greater than the length in the Z direction of the semiconductor layer 111 in the memory layer ML. In manufacturing such a configuration, at the timing after the process described with reference to FIG. 87 is performed, the length in the Z direction of the opening 111A in the transistor layer TL3 becomes greater than the length in the Z direction of the opening 111A in the memory layer ML3. Therefore, after the opening 111A in the memory layer ML3 is blocked, the concentration of indium in the semiconductor layer 311 is increased and the concentration of gallium is decreased, so that the above-mentioned region R is formed inside the semiconductor layer 311. CB It is possible to form

[0174] [Fourth embodiment] In the first to third embodiments, the semiconductor layers 111, 161, etc. contain an oxide semiconductor. However, such a configuration is merely an example, and the specific configuration can be appropriately adjusted. For example, the semiconductor layers 111, 161, etc. may contain a material other than an oxide semiconductor, such as silicon (Si) or germanium (Ge). Hereinafter, such a configuration will be exemplified as a semiconductor memory device according to a fourth embodiment.

[0175] [composition] 89 and 90 are schematic cross-sectional views showing a configuration of a portion of the semiconductor memory device according to the fourth embodiment. In the following description, the same parts as those in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.

[0176] The semiconductor memory device according to the fourth embodiment is basically configured similarly to the semiconductor memory device according to the first embodiment.

[0177] However, the semiconductor memory device according to the fourth embodiment includes via wirings 404, 454, a memory layer ML4, and a transistor layer TL4, instead of the via wirings 104, 154, the memory layer ML, and the transistor layer TL.

[0178] The via wiring 404, 454 is basically configured in the same manner as the via wiring 104, 154. However, the via wiring 404, 454 includes a semiconductor film 404a, 454a instead of the conductive oxide film 104a (FIG. 7) and the conductive oxide film 154a (FIG. 9). The semiconductor film 404a, 454a is basically configured in the same manner as the conductive oxide film 104a, 154a. However, the semiconductor film 404a, 454a is mainly composed of silicon (Si) and contains N-type impurities such as phosphorus (P) and arsenic (As). In this specification, the term "main component" refers to the element that is contained most abundantly. For example, the element that is contained most abundantly in the semiconductor film 404a, 454a is silicon (Si).

[0179] The memory layer ML4 and the transistor layer TL4 are basically configured in the same manner as the memory layer ML and the transistor layer TL, except that the memory layer ML4 and the transistor layer TL4 include transistor structures 410 and 460 instead of the transistor structures 110 and 160, respectively.

[0180] The transistor structure 410 is basically configured similarly to the transistor structure 110. However, the transistor structure 410 includes a semiconductor layer 411 instead of the semiconductor layer 111.

[0181] The semiconductor layer 411 is basically configured in the same manner as the semiconductor layer 111. However, the semiconductor layer 411 is mainly composed of silicon (Si) and contains P-type impurities such as boron (B).

[0182] In the fourth embodiment, the conductive layer 133 is mainly composed of silicon (Si) and contains N-type impurities such as phosphorus (P) and arsenic (As).

[0183] The transistor structure 460 is basically configured in the same manner as the transistor structure 160. However, the transistor structure 460 includes a semiconductor layer 461 instead of the semiconductor layer 161.

[0184] The semiconductor layer 461 is basically configured in the same manner as the semiconductor layer 161. However, the semiconductor layer 461 is mainly composed of silicon (Si) and contains P-type impurities such as boron (B).

[0185] In the fourth embodiment, the wiring 171 is mainly composed of silicon (Si) and contains N-type impurities such as phosphorus (P) and arsenic (As).

[0186] Here, the concentration of P-type impurities in the semiconductor layer 461 is lower than the concentration of P-type impurities in the semiconductor layer 411. This makes the threshold voltage of the transistor TrL (FIG. 1) lower than the threshold voltage of the transistor TrC (FIG. 1).

[0187] [Fifth embodiment] In the first to third embodiments, the semiconductor layer 161 functioning as the channel region of the transistor TrL and the semiconductor layer 111 functioning as the channel region of the transistor TrB contain an oxide semiconductor, similar to the semiconductor layer 111 functioning as the channel region of the transistor TrC. In the fourth embodiment, the semiconductor layer 461 functioning as the channel region of the transistor TrL and the semiconductor layer 411 functioning as the channel region of the transistor TrB contain silicon as a main component and P-type impurities such as boron (B), similar to the semiconductor layer 411 functioning as the channel region of the transistor TrC.

[0188] However, such a configuration is merely an example, and the specific configuration can be adjusted as appropriate. For example, the semiconductor layer 161 etc. functioning as the channel region of the transistor TrL and the semiconductor layer 111 etc. functioning as the channel region of the transistor TrB may contain a material different from the semiconductor layer 111 etc. functioning as the channel region of the transistor TrC. For example, one to three of the semiconductor layers 111 etc. in the memory layer ML, the semiconductor layer 161 etc. in the memory layer ML, the semiconductor layer 111 etc. in the transistor layer TL, and the semiconductor layer 161 etc. in the transistor layer TL may contain an oxide semiconductor, and one of the remaining three may contain a material other than an oxide semiconductor, such as silicon or germanium. Hereinafter, such a configuration will be exemplified as a semiconductor memory device according to the fifth embodiment.

[0189] [composition] 91 and 92 are schematic cross-sectional views showing a configuration of a portion of the semiconductor memory device according to the fifth embodiment. In the following description, the same parts as those in the second embodiment are denoted by the same reference numerals, and description thereof will be omitted.

[0190] The semiconductor memory device according to the fifth embodiment is basically configured similarly to the semiconductor memory device according to the second embodiment.

[0191] However, the semiconductor memory device according to the fifth embodiment includes a via wiring 454, a memory layer ML5, and a transistor layer TL5, instead of the via wiring 154, the memory layer ML, and the transistor layer TL2.

[0192] The memory layer ML5 and the transistor layer TL5 are basically configured in the same manner as the memory layer ML and the transistor layer TL2, except that the memory layer ML5 and the transistor layer TL5 each include a transistor structure 460 instead of the transistor structure 160.

[0193] In the fifth embodiment, the wiring 171 is mainly composed of silicon (Si) and contains N-type impurities such as phosphorus (P) and arsenic (As).

[0194] In the fifth embodiment, the threshold voltage of the transistor TrL (FIG. 1) is also lower than the threshold voltage of the transistor TrC (FIG. 1).

[0195] [Sixth embodiment] In the first to fifth embodiments, an example in which the transistor TrL (FIG. 1) is an N-channel type field effect transistor has been mainly shown. However, such a configuration is merely an example, and the specific configuration can be appropriately adjusted. For example, the transistor TrL can be configured as a P-channel type field effect transistor. Hereinafter, such a configuration will be exemplified as a semiconductor memory device according to the sixth embodiment.

[0196] [composition] 93 is a schematic cross-sectional view showing a configuration of a portion of the semiconductor memory device according to the sixth embodiment. In the following description, the same parts as those in the fourth embodiment are denoted by the same reference numerals, and description thereof will be omitted.

[0197] The semiconductor memory device according to the sixth embodiment is basically configured similarly to the semiconductor memory device according to the fourth embodiment.

[0198] However, the semiconductor memory device according to the sixth embodiment includes a via wiring 654, a memory layer ML6, and a transistor layer TL6 instead of the via wiring 454, the memory layer ML4, and the transistor layer TL4.

[0199] The via wiring 654 is basically configured in the same way as the via wiring 454. However, the via wiring 654 includes a semiconductor film 654a instead of the semiconductor film 454a (FIG. 89). The semiconductor film 654a is basically configured in the same way as the semiconductor film 454a. However, the semiconductor film 654a includes a P-type impurity such as boron (B) instead of an N-type impurity.

[0200] The memory layer ML6 and the transistor layer TL6 are basically configured in the same manner as the memory layer ML4 and the transistor layer TL4, except that the memory layer ML6 and the transistor layer TL6 each include a transistor structure 660 instead of the transistor structure 460.

[0201] The transistor structure 660 is basically configured similarly to the transistor structure 460. However, the transistor structure 660 includes a semiconductor layer 661 instead of the semiconductor layer 461.

[0202] The semiconductor layer 661 is basically configured in the same manner as the semiconductor layer 461. However, the semiconductor layer 661 is mainly composed of silicon (Si) and contains N-type impurities such as phosphorus (P) and arsenic (As).

[0203] In the sixth embodiment, the wiring 171 is mainly composed of silicon (Si) and contains P-type impurities such as boron (B).

[0204] [Seventh embodiment] In the first to sixth embodiments, the bit line BL is realized by the via wiring 104 extending in the Z direction, and the word line WL is realized by a plurality of conductive layers 120 aligned in the Z direction. However, such a configuration is merely an example, and the specific configuration can be adjusted as appropriate. For example, the word line WL may be realized by a via wiring (via electrode) extending in the Z direction, and the bit line BL may be realized by a plurality of conductive layers aligned in the Z direction. Hereinafter, such a configuration will be exemplified as a semiconductor memory device according to the seventh embodiment.

[0205] [Circuit configuration] 94 is a schematic circuit diagram showing a configuration of a portion of a semiconductor memory device according to the seventh embodiment. In the following description, the same reference numerals are used for the same parts as in the first embodiment, and the description thereof will be omitted.

[0206] The semiconductor memory device according to the seventh embodiment includes a memory cell array MCA7. The memory cell array MCA7 includes a plurality of memory layers ML7, a plurality of word lines WL connected to the plurality of memory layers ML7, and a plate line PL connected to the plurality of memory layers ML7.

[0207] Each of the memory layers ML7 includes a plurality of bit lines BL0 to BL2 (hereinafter, sometimes referred to as "bit lines BL") and a plurality of memory cells MC7 connected to the plurality of bit lines BL. Each of the memory cells MC7 includes a transistor TrC7 and a capacitor CpC. One electrode of the transistor TrC7 is connected to the bit line BL. The other electrode of the transistor TrC7 is connected to the capacitor CpC. The one and the other electrodes of the transistor TrC7 function as a source electrode or a drain electrode depending on the voltage supplied to the transistor TrC7. The gate electrode of the transistor TrC7 is connected to the word line WL. One electrode of the capacitor CpC is connected to the drain electrode of the transistor TrC7. The other electrode of the capacitor CpC is connected to the plate line PL.

[0208] Each word line WL is connected to a plurality of memory cells MC7 corresponding to a plurality of memory layers ML7.

[0209] The memory layer ML7 includes a plurality of transistors TrL0a, TrL0b, TrL1a, TrL1b, TrL2a, TrL2b, TrL3a, and TrL3b, which are provided corresponding to the plurality of bit lines BL0 to BL2. One electrode of the transistor TrL is connected to one of the bit lines BL0 to BL2. The other electrode of the transistor TrL is connected to the layer selection lines LL0a, LL0b, LL1a, LL1b, LL2a, LL2b, LL3a, and LL3b, respectively. The one and the other electrodes of the transistor TrL function as source electrodes or drain electrodes depending on the voltage supplied to the transistor TrL. The gate electrodes of the transistors TrL are connected to the bit line selection lines LB0a, LB0b, LB1a, LB1b, LB2a, and LB2b (hereinafter, sometimes referred to as "bit line selection lines LB7").

[0210] The bit line selection line LB7 is connected to a plurality of transistors TrL corresponding to a plurality of memory layers ML7. The layer selection lines LL0a, LL1a, LL2a, and LL3a are connected in common to all of the transistors TrL0a, TrL1a, TrL2a, and TrL3a corresponding to the plurality of memory layers ML7. Similarly, the layer selection lines LL0b, LL1b, LL2b, and LL3b are connected in common to all of the transistors TrL0b, TrL1b, TrL2b, and TrL3b corresponding to the plurality of memory layers ML7.

[0211] [structure] Fig. 95 is a schematic perspective view showing a configuration of a portion of the semiconductor memory device according to this embodiment, which shows a portion of the semiconductor substrate Sub and a memory cell array MCA7 provided above the semiconductor substrate Sub.

[0212] The memory cell array MCA7 includes a plurality of memory layers ML7 stacked in the Z direction. In addition, insulating layers 103 such as silicon oxide (SiO2) are provided between the plurality of memory layers ML7.

[0213] 96 is a schematic XY cross-sectional view showing a configuration of a part of the memory layer ML7. As shown in FIG. 96, the memory layer ML7 has a memory cell region R MC7 and the transistor area R TrL7 Although not shown, the transistor region R TrL7 is a memory cell region R in the Y direction. MC7 are provided on both sides of the

[0214] [Memory cell area R MC7 Structure of Next, referring to FIG. 97 in addition to FIG. 95 and FIG. 96, the memory cell region R MC7 The structure of Fig. 97 is a cross-sectional view of the structure shown in Fig. 96 taken along line AA' and viewed in the direction of the arrow.

[0215] As shown in FIG. 96, the memory cell region R MC7 95 includes a plurality of insulating layers 101 aligned in the X direction, and a conductive layer 102 provided between two insulating layers 101 adjacent to each other in the X direction. The insulating layers 101 and the conductive layers 102 extend in the Y direction and the Z direction, and divide the plurality of memory layers ML7 in the X direction (see FIG. 95).

[0216] A plurality of via electrodes 704 are provided in the region between the insulating layer 101 and the conductive layer 102. The plurality of via electrodes 704 are aligned in the Y direction and extend in the Z direction, penetrating the plurality of memory layers ML7, as shown in FIG.

[0217] As shown in FIG. 97, the via electrode 704 includes a barrier conductive film 704a made of, for example, titanium nitride (TiN) and a conductive member 704b made of, for example, tungsten (W).

[0218] The conductive member 704b has a substantially cylindrical shape extending in the Z direction. The barrier conductive film 704a has a substantially cylindrical shape extending in the Z direction along the outer circumferential surface of the conductive member 704b.

[0219] The via electrodes 704 function as, for example, word lines WL (FIG. 94). As shown in FIG. 94, a plurality of word lines WL are provided corresponding to a plurality of transistors TrC7 included in the memory layer ML7.

[0220] The memory layer ML7 includes a plurality of transistor structures 710 corresponding to the plurality of via electrodes 704, a conductive layer 720 provided on the opposite side of the conductive layer 102 relative to the plurality of transistor structures 710, and a plurality of capacitor structures 730 provided between the plurality of transistor structures 710 and the conductive layer 102.

[0221] The transistor structure 710 includes a substantially disk-shaped conductive layer 711 continuous with the conductive member 704b, a barrier conductive film 712 continuous with the barrier conductive film 704a and provided on an upper surface, a lower surface, both side surfaces in the Y direction, and both side surfaces in the X direction of the conductive layer 711, an insulating layer 713 provided on the upper surface, lower surface, both side surfaces in the Y direction, and both side surfaces in the X direction of the barrier conductive film 712, and a semiconductor layer 714 provided on the upper surface, lower surface, both side surfaces in the Y direction, and both side surfaces in the X direction of the insulating layer 713.

[0222] 96, both side surfaces of the semiconductor layer 714 in the X direction may be formed along a circle centered on the central position of the via electrode 704. Also, both side surfaces of the semiconductor layer 714 in the Y direction may be formed linearly along the side surfaces of the insulating layer 115. Also, the outer peripheral surfaces of the barrier conductive film 712 and the insulating layer 713 may be formed along a circle centered on the central position of the via electrode 704.

[0223] The conductive layer 711 and the barrier conductive film 712 function as, for example, a gate electrode of the transistor TrC7 (FIG. 94). The conductive layer 711 includes, for example, a conductive member such as tungsten (W). The barrier conductive film 712 includes, for example, titanium nitride (TiN).

[0224] The insulating layer 713 functions as, for example, a gate insulating film of the transistor TrC7 (FIG. 94). The insulating layer 713 includes, for example, silicon oxide (SiO2).

[0225] The semiconductor layer 714 functions as, for example, a channel region of the transistor TrC7 (FIG. 94). The semiconductor layer 714 may be, for example, a semiconductor containing at least one element of gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O), or may be another oxide semiconductor. The multiple semiconductor layers 714 aligned in the Y direction are commonly connected to a conductive layer 720 extending in the Y direction. The semiconductor layer 714 faces the upper surface, the lower surface, both side surfaces in the Y direction, and both side surfaces in the X direction of the barrier conductive film 712 via the insulating layer 713.

[0226] An insulating layer 115 made of silicon oxide (SiO2) or the like is provided between two semiconductor layers 714 adjacent to each other in the Y direction. The insulating layer 115 extends in the Z direction, penetrating the multiple memory layers ML7.

[0227] The conductive layer 720 functions as, for example, a bit line BL (FIG. 94). The conductive layer 720 extends in the Y direction and is connected to a plurality of semiconductor layers 714 arranged in the Y direction. The conductive layer 720 includes, for example, a conductive oxide film 723 including a conductive oxide, a barrier conductive film 722 such as titanium nitride (TiN), and a conductive film 721 of tungsten (W). The conductive layer 720 may include ruthenium (Ru), iridium (Ir), or other metals instead of the conductive oxide film 723. The conductive layer 720 may include only a conductive oxide, or may include only ruthenium (Ru), iridium (Ir), or other metals.

[0228] 97, the capacitor structure 730 includes a conductive layer 731, a barrier conductive film 732 provided on the upper surface, lower surface, both side surfaces in the Y direction, and one side surface in the X direction (the transistor structure 710 side) of the conductive layer 731, an insulating layer 733 provided on the upper surface, lower surface, both side surfaces in the Y direction, and one side surface in the X direction (the transistor structure 710 side) of the barrier conductive film 732, and an insulating layer 733 provided on the upper surface, lower surface, both side surfaces in the Y direction, and one side surface in the X direction (the transistor structure 710 side) of the insulating layer 733. a conductive layer 734 provided on a side surface of the insulating layer 103 in the X direction (the transistor structure 710 side); an insulating layer 735 provided on an upper surface, a lower surface, and both side surfaces in the Y direction of the conductive layer 734 and on the side surface of the insulating layer 103 in the X direction; a barrier conductive film 736 provided on the upper surface, lower surface, and both side surfaces in the Y direction of the insulating layer 735 and on the side surface of the insulating layer 103 in the X direction; and a conductive layer 737 provided on the upper surface, lower surface, and both side surfaces in the Y direction of the barrier conductive film 736 and on a side surface on one side in the X direction (the transistor structure 710 side).

[0229] The conductive layers 731 and 737 and the barrier conductive films 732 and 736 function as one electrode of the capacitor CpC (FIG. 94). The conductive layers 731 and 737 include a conductive member such as tungsten (W). The barrier conductive films 732 and 736 include titanium nitride (TiN). The conductive layers 731 and 737 and the barrier conductive films 732 and 736 are continuous with the conductive layer 102.

[0230] The insulating layers 733 and 735 function as insulating layers of the capacitor CpC (FIG. 94). The insulating layers 733 and 735 may be, for example, zirconia (ZrO2), alumina (Al2O3), or other insulating metal oxides. The insulating layers 733 and 735 may also be, for example, a laminated film of multiple insulating metal oxides (for example, a laminated film of zirconia and alumina).

[0231] The conductive layer 734 functions as, for example, the other electrode of the capacitor CpC (FIG. 94). The conductive layer 734 includes, for example, a conductive oxide such as indium tin oxide (ITO). The conductive layer 734 is insulated from the barrier conductive films 732 and 736 via the insulating layers 733 and 735. The conductive layer 734 is connected to the side surface of the semiconductor layer 714 in the X direction.

[0232] [Transistor area R TrL7 Structure of Next, referring to FIG. 98 in addition to FIG. 95 and FIG. 96, the transistor region R TrL7 Fig. 98 shows a cross section of the structure shown in Fig. 96 taken along line BB' and viewed in the direction of the arrow.

[0233] As shown in Figure 96, the transistor region R TrL7 1 includes a plurality of insulating layers 151 arranged in the X direction corresponding to the plurality of insulating layers 101, and an insulating layer 152 provided between two insulating layers 151 adjacent to each other in the X direction.

[0234] In addition, the memory cell region R MC7 and the transistor area R TrL7 Between them, an insulating layer 165 is provided, which extends in the X direction in the range between two conductive layers 720 adjacent in the X direction.

[0235] A plurality of via electrodes 754 are provided in the region between the insulating layer 151 and the insulating layer 152. The plurality of via electrodes 754 are aligned in the Y direction and extend in the Z direction, penetrating the plurality of memory layers ML7, as shown in FIG.

[0236] As shown in FIG. 98, the via electrode 754 includes a barrier conductive film 754a made of, for example, titanium nitride (TiN) or the like, and a conductive member 754b made of, for example, tungsten (W) or the like.

[0237] The conductive member 754b has a substantially cylindrical shape extending in the Z direction. The barrier conductive film 754a has a substantially cylindrical shape extending in the Z direction along the outer circumferential surface of the conductive member 754b.

[0238] The via electrodes 754 arranged in the Y direction function as, for example, one bit line selection line LB7 (FIG. 94). As shown in FIG. 94, for example, a plurality of bit line selection lines LB7 are provided corresponding to the plurality of bit lines BL included in the memory layer ML7.

[0239] The memory layer ML7 includes a plurality of transistor structures 760 corresponding to a plurality of conductive layers 720, a wiring 171 provided between the transistor structures 760 and an insulating layer 151, and a wiring 772 provided between the transistor structures 760 and an insulating layer 152.

[0240] The transistor structure 760 includes a conductive layer 761 continuous with the outer peripheral surfaces of the multiple via electrodes 754, a barrier conductive film 762 provided on an upper surface, a lower surface, both side surfaces in the Y direction, and both side surfaces in the X direction of the conductive layer 761, an insulating layer 763 provided on an upper surface, a lower surface, both side surfaces in the Y direction, and both side surfaces in the X direction of the barrier conductive film 762, and a semiconductor layer 764 provided on an upper surface, a lower surface, both side surfaces in the Y direction, and both side surfaces in the X direction of the insulating layer 763.

[0241] 96, both side surfaces in the X direction of the semiconductor layer 764 may be formed along a plurality of overlapping circles centered on the central positions of the via electrodes 754. In addition, the outer peripheral surfaces of the barrier conductive film 762 and the insulating layer 763 may be formed along a plurality of circles centered on the central positions of the via electrodes 754 and spaced apart from each other.

[0242] The conductive layer 761 and the barrier conductive film 762 function as, for example, a gate electrode of the transistor TrL7 (FIG. 94). The conductive layer 761 includes, for example, a conductive member such as tungsten (W). The barrier conductive film 762 includes, for example, titanium nitride (TiN).

[0243] The insulating layer 763 functions as, for example, a gate insulating film of the transistor TrL7 (FIG. 94). The insulating layer 763 includes, for example, silicon oxide (SiO 2 ).

[0244] The semiconductor layer 764 functions as, for example, a channel region of the transistor TrL7 (FIG. 94). The semiconductor layer 764 may be, for example, a semiconductor containing at least one element of gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O), or may be another oxide semiconductor. The semiconductor layer 764 is electrically connected to the wirings 171 and 772.

[0245] Here, the concentration of indium in the semiconductor layer 764 is greater than the concentration of indium in the semiconductor layer 714. Moreover, the concentration of gallium in the semiconductor layer 764 is equal to or less than the concentration of gallium in the semiconductor layer 714. As a result, the threshold voltage of the transistor TrL (FIG. 94) becomes lower than the threshold voltage of the transistor TrC7 (FIG. 94).

[0246] As shown in FIG. 96, the wiring 772 has a portion extending in the Y direction and a portion extending in the X direction. The portion of the wiring 772 extending in the Y direction is connected to the semiconductor layer 764. The wiring 772 has a function of connecting the source electrode of the transistor TrL (FIG. 94) and the control circuit. The wiring 772 includes, for example, a conductive oxide. Note that the wiring 772 may include ruthenium (Ru), iridium (Ir), or other metals instead of a conductive oxide. The wiring 772 may also include only a conductive oxide, or may include only ruthenium (Ru), iridium (Ir), or other metals.

[0247] [Other embodiments] The semiconductor memory devices according to the first to seventh embodiments have been described above. However, the semiconductor memory devices according to these embodiments are merely examples, and the specific configurations and the like can be appropriately adjusted.

[0248] For example, in the semiconductor memory devices according to the fourth to sixth embodiments, the P-type impurity concentrations in the semiconductor layers 411, 111 in the transistor layers TL4, TL5, TL6 may be made lower than the P-type impurity concentrations in the semiconductor layers 411, 111 in the memory layers ML4, ML5, ML6. This allows the threshold voltage of the transistor TrB (FIG. 1) to be lower than the threshold voltage of the transistor TrC (FIG. 1).

[0249] Also, for example, in the semiconductor memory devices according to the second to fourth embodiments, it is possible to adjust only the threshold voltage of the transistor TrB (FIG. 1) and not adjust the threshold voltage of the transistor TrL (FIG. 1). For example, in the second and third embodiments, the indium concentration and the gallium concentration in the semiconductor layers 161 and 361 may be equal to the indium concentration and the gallium concentration in the semiconductor layer 111, respectively. Also, in the fourth embodiment, the P-type impurity concentration in the semiconductor layer 461 may be equal to the P-type impurity concentration in the semiconductor layer 411.

[0250] Also, for example, in manufacturing the semiconductor memory device according to the fourth embodiment, the semiconductor layers 411 and 461 can be formed at once by the method exemplified in the third embodiment. In this case, the region R as described with reference to FIG. 85 is formed in the semiconductor layer 461. SL ,R CL is provided, and the area R CL The concentration of P-type impurities in the region R SL The concentration of the P-type impurity in the first region may be smaller than that in the second region.

[0251] In addition, for example, in the manufacture of the semiconductor memory device according to any of the embodiments, the region R CL In the region R SL Similarly, the region R may contain a material different from that of the region R. CB In the region R SB It may contain materials different from those mentioned above.

[0252] Also, for example, in the semiconductor memory device according to the seventh embodiment, the semiconductor layers 714, 764 may be mainly composed of silicon (Si) and contain P-type impurities such as boron (B). In this case, the concentration of the P-type impurities in the semiconductor layer 764 may be lower than the concentration of the P-type impurities in the semiconductor layer 714. Also, the semiconductor layer 764 may contain a different material from the semiconductor layer 714.

[0253] In the semiconductor memory devices according to the first to third embodiments, the via wirings 104, 154, etc., which function as bit lines, contain a conductive oxide such as indium tin oxide (ITO). However, such a conductive oxide may be included in the transistor structures 110, 160, etc., instead of the via wirings 104, 154, etc., which extend in the Z direction. The via wirings 104, 154, etc., and the transistor structures 110, 160 may contain other materials, etc.

[0254] In the semiconductor memory devices according to the fourth and sixth embodiments, the via wirings 404, 454, etc. functioning as bit lines include semiconductor films 404a, 454a, etc. However, such semiconductor films 404a, 454a, etc. may be included in the transistor structures 410, 460, etc., instead of the via wirings 404, 454, etc. extending in the Z direction. In addition, the via wirings 404, 454, etc. and the transistor structures 410, 460 may include other materials, etc.

[0255] Furthermore, in the semiconductor memory devices according to the first to sixth embodiments, the conductive layer 113 functioning as the gate electrode of the transistor TrC may face only one of the upper surface and the lower surface of the semiconductor layer 111 functioning as the channel region of the transistor TrC.

[0256] In the above description, an example has been described in which a capacitor CpC is adopted as the memory unit connected to the transistor structure 110. However, the memory unit does not have to be the capacitor CpC. For example, the memory unit may include a ferroelectric material, a ferromagnetic material, a chalcogen material such as GeSbTe, or other material, and may record data by utilizing the properties of these materials. For example, in any of the structures described above, the insulating layer between the electrodes that forms the capacitor CpC may include any of these materials.

[0257] Furthermore, the methods for manufacturing the semiconductor memory devices according to the first to sixth embodiments can also be adjusted as appropriate. For example, the order of any two of the above-described steps can be changed, or any two of the above-described steps can be performed simultaneously.

[0258] [others] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0259] Sub...semiconductor substrate, ML...memory layer, BL...bit line, WL...word line, PL...plate line, TrC, TrL, TrB...transistor, CpC...capacitor, 102...conductive layer, 104...via wiring, 110, 160...transistor structure, 111, 161...semiconductor layer, 112, 162...insulating layer, 113, 163...conductive layer, 120...conductive layer, 130...capacitor structure, 171, 172...wiring.

Claims

1. A substrate; A plurality of first semiconductor layers stacked in a stacking direction intersecting a surface of the substrate; a first via wiring extending in the stacking direction and electrically connected to the first semiconductor layers; a plurality of memory units stacked in the stacking direction and electrically connected to the plurality of first semiconductor layers; a plurality of first gate electrodes stacked in the stacking direction and facing the plurality of first semiconductor layers; a plurality of first wirings stacked in the stacking direction, extending in a first direction intersecting the stacking direction, and electrically connected to the plurality of first gate electrodes; a plurality of second semiconductor layers stacked in the stacking direction and electrically connected to the plurality of first gate electrodes via the plurality of first wirings; a second via wiring extending in the stacking direction and electrically connected to the second semiconductor layers; a plurality of second gate electrodes stacked in the stacking direction and facing the plurality of second semiconductor layers; Equipped with The second semiconductor layers include a material different from that of the first semiconductor layers, or a composition ratio of the material included in the second semiconductor layers is different from a composition ratio of the material included in the first semiconductor layers. Semiconductor memory device.

2. The first semiconductor layer and the second semiconductor layer each contain at least one element of gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O), The concentration of indium in the second semiconductor layer is greater than the concentration of indium in the first semiconductor layer.

2. The semiconductor memory device according to claim 1.

3. The first semiconductor layer and the second semiconductor layer each have silicon (Si) as a main component.

2. The semiconductor memory device according to claim 1.

4. the first semiconductor layer and the second semiconductor layer each contain a P-type impurity, The concentration of P-type impurities in the second semiconductor layer is lower than the concentration of P-type impurities in the first semiconductor layer.

4. The semiconductor memory device according to claim 3.

5. the first semiconductor layer contains a P-type impurity; The second semiconductor layer contains an N-type impurity.

4. The semiconductor memory device according to claim 3.

6. The length of the second semiconductor layer in the stacking direction is greater than the length of the first semiconductor layer in the stacking direction.

2. The semiconductor memory device according to claim 1.

7. The second semiconductor layer is A first region and a second region aligned in the stacking direction; a third region provided between the first region and the second region; and Including, The third region includes a material different from those of the first region and the second region, or a composition ratio of the material included in the third region is different from a composition ratio of the material included in the first region and the second region.

2. The semiconductor memory device according to claim 1.

8. a second wiring provided on one side of the plurality of first semiconductor layers in the stacking direction and extending in a second direction intersecting the stacking direction and the first direction; a third semiconductor layer provided between the plurality of first semiconductor layers and the second wiring and electrically connected to the first via wiring and the second wiring; a third gate electrode facing the third semiconductor layer; Equipped with The third semiconductor layer includes a material different from that of the first semiconductor layers, or a composition ratio of the material included in the third semiconductor layer is different from a composition ratio of the material included in the first semiconductor layers.

2. The semiconductor memory device according to claim 1.

9. The memory unit is a capacitor.

2. The semiconductor memory device according to claim 1.

10. the first gate electrode faces one or both of a surface on one side and a surface on the other side in the stacking direction of the first semiconductor layer, the memory unit is provided on one side of the first semiconductor layer in a second direction intersecting the stacking direction and the first direction, The first wiring is provided on the other side of the first semiconductor layer in the second direction.

2. The semiconductor memory device according to claim 1.

11. A substrate; A plurality of semiconductor layers stacked in a stacking direction intersecting a surface of the substrate; via wiring extending in the stacking direction and electrically connected to the plurality of semiconductor layers; a plurality of memory units stacked in the stacking direction and electrically connected to the plurality of semiconductor layers; a plurality of gate electrodes stacked in the stacking direction and facing the plurality of semiconductor layers; a plurality of first wirings stacked in the stacking direction, extending in a first direction intersecting the stacking direction, and electrically connected to the plurality of gate electrodes; a second wiring provided on one side of the plurality of semiconductor layers in the stacking direction and extending in a second direction intersecting the stacking direction and the first direction; Another semiconductor layer is provided between the plurality of semiconductor layers and the second wiring and is electrically connected to the via wiring and the second wiring; Another gate electrode facing the other semiconductor layer; Equipped with The other semiconductor layer includes a material different from that of the plurality of semiconductor layers, or a composition ratio of the material included in the other semiconductor layer is different from a composition ratio of the material included in the plurality of semiconductor layers. Semiconductor memory device.

12. The semiconductor layer and the other semiconductor layer each contain at least one element of gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O), The concentration of indium in the other semiconductor layer is greater than the concentration of indium in the semiconductor layer.

12. The semiconductor memory device according to claim 11.

13. The semiconductor layer and the other semiconductor layer each have silicon (Si) as a main component.

12. The semiconductor memory device according to claim 11.

14. the semiconductor layer and the other semiconductor layer each contain a P-type impurity, The concentration of the P-type impurity in the other semiconductor layer is lower than the concentration of the P-type impurity in the semiconductor layer.

14. The semiconductor memory device according to claim 13.

15. the semiconductor layer contains a P-type impurity, The other semiconductor layer contains an N-type impurity.

14. The semiconductor memory device according to claim 13.

16. The length of the other semiconductor layer in the stacking direction is greater than the length of the semiconductor layer in the stacking direction.

12. The semiconductor memory device according to claim 11.

17. The other semiconductor layer is A first region and a second region aligned in the stacking direction; a third region provided between the first region and the second region; and Including, The third region includes a material different from those of the first region and the second region, or a composition ratio of the material included in the third region is different from a composition ratio of the material included in the first region and the second region.

12. The semiconductor memory device according to claim 11.

18. The memory unit is a capacitor.

12. The semiconductor memory device according to claim 11.

19. the gate electrode faces one or both of a surface on one side and a surface on the other side in the stacking direction of the semiconductor layer, the memory unit is provided on one side of the semiconductor layer in the second direction, The first wiring is provided on the other side of the semiconductor layer in the second direction.

12. The semiconductor memory device according to claim 11.

20. A substrate; A plurality of first semiconductor layers stacked in a stacking direction intersecting a surface of the substrate; a first via electrode extending in the stacking direction and facing the first semiconductor layers; a plurality of memory units stacked in the stacking direction and electrically connected to the plurality of first semiconductor layers; a plurality of wirings stacked in the stacking direction, extending in a first direction intersecting the stacking direction, and electrically connected to the plurality of first semiconductor layers; a plurality of second semiconductor layers stacked in the stacking direction and electrically connected to the plurality of first semiconductor layers via the plurality of wirings; a second via electrode extending in the stacking direction and facing the second semiconductor layers; Equipped with The second semiconductor layers include a material different from that of the first semiconductor layers, or a composition ratio of the material included in the second semiconductor layers is different from a composition ratio of the material included in the first semiconductor layers. Semiconductor memory device.

Images