Power supply circuit and method for starting the same

Abstract

To suppress transient variations in a power supply voltage generated by a regulator.SOLUTION: A power supply circuit includes: a reference voltage generating circuit that generates a reference voltage lower than an input voltage; a first regulator that generates a first power supply voltage higher than the reference voltage based on the input voltage and the reference voltage; a first startup circuit that controls the reference voltage generating circuit so that the reference voltage rises after the input voltage rises; and a second startup circuit that controls the first regulator so that the first power supply voltage rises after the reference voltage rises.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a power supply circuit and a start-up method thereof. [Background technology]

[0002] 2. Description of the Related Art A power supply regulator is known that includes a startup circuit for starting up a reference voltage generating circuit in order to realize a stable rise of a reference voltage without overshoot (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2005-208968 A Summary of the Invention [Problem to be solved by the invention]

[0004] A power supply circuit may include a reference voltage generation circuit that generates a reference voltage lower than an input voltage, and a regulator that generates a power supply voltage higher than the reference voltage based on the input power supply voltage and the reference voltage. In this case, if the reference power supply generation circuit and the regulator start operating simultaneously with the rise of the input voltage, the internal signal state of the reference power supply generation circuit or the regulator is unstable, and thus the transient fluctuation of the power supply voltage may become large.

[0005] The present disclosure provides a power supply circuit capable of suppressing transient fluctuations in a power supply voltage generated by a regulator, and a startup method thereof. [Means for solving the problem]

[0006] The first aspect is a reference voltage generating circuit for generating a reference voltage lower than an input voltage; a first regulator that generates a first power supply voltage higher than the reference voltage based on the input voltage and the reference voltage; a first startup circuit that controls the reference voltage generating circuit so that the reference voltage rises after the input voltage rises; and a second startup circuit that controls the first regulator so that the first power supply voltage rises after the reference voltage rises.

[0007] A second aspect is the power supply circuit of the first aspect, The first startup circuit may include a first delay circuit that generates a first time from the rising edge of the input voltage, and may raise the reference voltage after the first time has elapsed.

[0008] A third aspect is the power supply circuit of the second aspect, The first startup circuit may assert a first startup signal for the reference voltage generating circuit after the first time period has elapsed.

[0009] A fourth aspect is the power supply circuit of the third aspect, the reference voltage generating circuit includes a bandgap reference circuit that generates the reference voltage; The bandgap reference circuit may ramp up the reference voltage when the first start-up signal is asserted.

[0010] A fifth aspect is the power supply circuit of the third or fourth aspect, The second startup circuit may start up the first power supply voltage after the first startup signal is asserted.

[0011] A sixth aspect is the power supply circuit of the fifth aspect, The second startup circuit may include a second delay circuit that generates a second time after the first startup signal is asserted, and may start up the first power supply voltage after the second time has elapsed.

[0012] A seventh aspect is the power supply circuit of the sixth aspect, The second startup circuit may assert a second startup signal for the first regulator after the second time period has elapsed.

[0013] An eighth aspect is a power supply circuit according to any one of the first to seventh aspects, a second regulator configured to generate a second power supply voltage higher than the reference voltage based on the first power supply voltage and the reference voltage; The second startup circuit may control the second regulator so that the second power supply voltage rises after the first power supply voltage rises.

[0014] A ninth aspect is the power supply circuit of the eighth aspect, The second start-up circuit is a second delay circuit that generates a second time from a rising edge of the reference voltage; a third delay circuit that generates a third time that is longer than the second time from the rising edge of the reference voltage; after the second time period has elapsed, the first power supply voltage is started up; The second power supply voltage may be raised after the third period of time has elapsed.

[0015] A tenth aspect is the power supply circuit of the ninth aspect, The second delay circuit may share a portion of the third delay circuit.

[0016] The eleventh aspect is The first startup circuit may raise the reference voltage after a first delay time has elapsed since the rise of the input voltage, The second startup circuit may raise the first power supply voltage after a second delay time, which is longer than the first delay time, has elapsed from the rising edge of the input voltage.

[0017] A twelfth aspect is the power supply circuit of the eleventh aspect, a second regulator configured to generate a second power supply voltage higher than the reference voltage based on the first power supply voltage and the reference voltage; The second startup circuit may raise the first power supply voltage and the second power supply voltage after the second delay time has elapsed from the rising edge of the input voltage.

[0018] A thirteenth aspect is the power supply circuit of the twelfth aspect, When a delay time longer than the second delay time from the rising edge of the input voltage is set as a third delay time, The second startup circuit may raise the first power supply voltage during a period from the second delay time to the third delay time, and may raise the second power supply voltage after the third delay time has passed.

[0019] The fourteenth aspect is a reference voltage generating circuit for generating a reference voltage lower than an input voltage; a first regulator that generates a first power supply voltage higher than the reference voltage based on the input voltage and the reference voltage, This is a method for starting up a power supply circuit, in which the reference voltage is raised after the input voltage is raised, and the first power supply voltage is raised after the reference voltage is raised. Effect of the Invention

[0020] The present disclosure can suppress transient fluctuations in the power supply voltage generated by a regulator. [Brief description of the drawings]

[0021] [Figure 1] FIG. 2 is a diagram illustrating a configuration example of a power supply circuit according to the first embodiment. [Diagram 2] 11 is a timing chart showing an example of voltage behavior at the time of start-up of a power supply circuit of a comparative example. [Diagram 3] 4 is a timing chart showing an example of voltage behavior at the time of start-up of the power supply circuit according to the first embodiment. [Figure 4] FIG. 11 is a diagram illustrating a configuration example of a power supply circuit according to a second embodiment. [Diagram 5] FIG. 13 is a diagram illustrating a configuration example of a power supply circuit according to a third embodiment. [Figure 6] FIG. 13 is a diagram illustrating an example of the configuration of a power supply circuit according to a fourth embodiment. [Figure 7] FIG. 2 is a diagram illustrating an example of a configuration of a reference voltage generating circuit. [Figure 8]FIG. 13 is a diagram illustrating an example of a configuration of a startup circuit. [Figure 9] FIG. 4 is a diagram illustrating an example of a configuration of a first regulator. [Figure 10] FIG. 4 is a diagram illustrating an example of a configuration of a second regulator. [Figure 11] FIG. 2 is a diagram illustrating a first configuration example of a start timing control circuit. [Figure 12] FIG. 13 is a diagram illustrating a second configuration example of the activation timing control circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.

[0023] Fig. 1 is a diagram showing an example of the configuration of a power supply circuit according to a first embodiment. A power supply circuit 101 shown in Fig. 1 generates a first power supply voltage VDD1 and a second power supply voltage VDD2 from an input voltage VDD, and supplies the second power supply voltage VDD2 to a load 201. The power supply circuit 101 is, for example, a semiconductor integrated circuit that operates with a ground AVSS as a reference potential. The power supply circuit 101 includes a reference voltage generating circuit 40, a first regulator 10, a second regulator 20, and a start-up timing control circuit 50.

[0024] The reference voltage generating circuit 40 generates a reference voltage VREF lower than the input voltage VDD. The reference voltage generating circuit 40 generates a constant reference voltage VREF lower than the input voltage VDD, for example, by using a bandgap reference circuit 42. The reference voltage generating circuit 40 may generate the reference voltage VREF by a known means (for example, a voltage divider circuit that divides the input voltage VDD by resistors) without using a bandgap reference circuit.

[0025] The input voltage VDD is, for example, a power supply voltage supplied from outside the power supply circuit 101. For example, a steady voltage value V1 after the input voltage VDD rises is 5 volts, and a constant voltage value V2 after the reference voltage VREF rises is 1.25 volts.

[0026] The first regulator 10 is a circuit that generates a first power supply voltage VDD1 higher than the reference voltage VREF based on an input voltage VDD and a reference voltage VREF. The first regulator 10 controls the first power supply voltage VDD1 to maintain it at a constant voltage value V3 higher than the reference voltage VREF.

[0027] The first regulator 10 is, for example, a linear regulator that controls the first power supply voltage VDD1 to be kept at a constant voltage value V3 that is lower than the input voltage VDD and higher than the reference voltage VREF. A specific example of the first regulator 10 is an LDO (Low Drop Out) regulator that operates even when the input / output voltage difference is small.

[0028] The steady voltage value V3 after the first power supply voltage VDD1 rises is, for example, 3.3 volts.

[0029] The first regulator 10 may be a switching regulator that controls the first power supply voltage VDD1 to be kept at a constant voltage value V3 that is lower or higher than the input voltage VDD and higher than the reference voltage VREF.

[0030] The second regulator 20 is a circuit that generates a second power supply voltage VDD2 higher than the reference voltage VREF based on the first power supply voltage VDD1 and the reference voltage VREF. The second regulator 20 controls the second power supply voltage VDD2 to maintain it at a constant voltage value V4 higher than the reference voltage VREF.

[0031] The second regulator 20 is, for example, a linear regulator that controls the second power supply voltage VDD2 to be kept at a constant voltage value V4 that is lower than the first power supply voltage VDD1 and higher than the reference voltage VREF. A specific example of the second regulator 20 is an LDO regulator that operates even when the input / output voltage difference is small.

[0032] The steady voltage value V4 after the second power supply voltage VDD2 rises is, for example, 1.8 volts.

[0033] The second regulator 20 may be a switching regulator that controls the second power supply voltage VDD2 to maintain a constant voltage value V4 that is lower or higher than the first power supply voltage VDD1 and higher than the reference voltage VREF.

[0034] The start-up timing control circuit 50 controls the start-up timing of each of the first regulator 10 and the second regulator 20.

[0035] Fig. 2 is a timing chart showing an example of voltage behavior at the start of a power supply circuit of a comparative embodiment. Fig. 3 is a timing chart showing an example of voltage behavior at the start of a power supply circuit of the first embodiment. The power supply circuit of the comparative embodiment differs from the power supply circuit 101 of the first embodiment in that it does not have a start-up timing control circuit 50.

[0036] 2, when the reference voltage generating circuit 40, the first regulator 10, and the second regulator 20 start operating simultaneously with the rising edge of the input voltage VDD, the internal signal state of the reference voltage generating circuit 40, the first regulator 10, or the second regulator 20 may become unstable. In this case, the transient fluctuation of the reference voltage VREF, the first power supply voltage VDD1, or the second power supply voltage VDD2 may become large.

[0037] When the transient fluctuation of the reference voltage VREF becomes large, the first regulator 10 or the second regulator 20 to which the reference voltage VREF is input is more likely to malfunction or suffer a voltage breakdown. When the transient fluctuation of the first power supply voltage VDD1 becomes large, the second regulator 20 to which the first power supply voltage VDD1 is input is more likely to malfunction or suffer a voltage breakdown. When the transient fluctuation of the second power supply voltage VDD2 becomes large, the load 201 to which the second power supply voltage VDD2 is input is more likely to malfunction or suffer a voltage breakdown.

[0038] 3, the reference voltage generating circuit 40 raises the reference voltage VREF after the first delay time d1 has elapsed since the rising edge of the input voltage VDD. The start-up timing control circuit 50 controls the start-up of the first regulator 10 so that the first power supply voltage VDD1 rises after the second delay time d2 has elapsed since the rising edge of the input voltage VDD. The second delay time d2 is longer than the first delay time d1. The start-up timing control circuit 50 controls the start-up of the second regulator 20 so that the second power supply voltage VDD2 rises after the third delay time d3 has elapsed since the rising edge of the input voltage VDD. The third delay time d3 is longer than the second delay time d2.

[0039] In this way, the reference voltage VREF rises after the first delay time d1 has elapsed since the rise of the input voltage VDD. Then, the first power supply voltage VDD1 rises after the second delay time d2, which is longer than the first delay time d1, has elapsed since the rise of the input voltage VDD. Furthermore, the second power supply voltage VDD2 rises after the third delay time d3, which is longer than the second delay time d2, has elapsed since the rise of the input voltage VDD. By controlling the rise timing of the voltage generated by each circuit by such a startup method, the voltage generated by each circuit rises after the stability of the internal signal state of the reference voltage generating circuit 40, the first regulator 10, or the second regulator 20 has increased. As a result, as shown in FIG. 3, the increase in the transient fluctuation of the reference voltage VREF, the first power supply voltage VDD1, or the second power supply voltage VDD2 is suppressed compared to the case shown in FIG. 2. Therefore, the possibility of malfunction or voltage breakdown of the first regulator 10, the second regulator 20, or the load 201 is reduced.

[0040] 3, the start-up timing control circuit 50 controls the start-up of the first regulator 10 so that the first power supply voltage VDD1 rises between the lapse of the second delay time d2 and the lapse of the third delay time d3. As a result, the first power supply voltage VDD1 rises before the second power supply voltage VDD2 rises, suppressing an increase in the transient fluctuation of the second power supply voltage VDD2 generated by the second regulator 20 based on the first power supply voltage VDD1. This reduces the possibility of the load 201 malfunctioning or breaking down.

[0041] The first delay time d1 is set to, for example, a time or longer for the input voltage VDD to rise from zero to a voltage value V1. This allows the reference voltage generating circuit 40 to start raising the reference voltage VREF after the input voltage VDD rises to the voltage value V1 and the stability of the internal signal state of the reference voltage generating circuit 40 increases. This suppresses an increase in the transient fluctuation of the reference voltage VREF.

[0042] The second delay time d2 is set to, for example, a time period longer than the time it takes for the reference voltage VREF to rise from zero to a voltage value V2 after the input voltage VDD rises from zero. This allows the first regulator 10 to start raising the first power supply voltage VDD1 after the reference voltage VREF rises to the voltage value V2 and the internal signal state of the first regulator 10 becomes more stable. This suppresses an increase in the transient fluctuation of the first power supply voltage VDD1.

[0043] The third delay time d3 is set, for example, to be equal to or longer than the time it takes for the first power supply voltage VDD1 to rise from zero to a voltage value V5 after the input voltage VDD rises from zero. This allows the second regulator 20 to start raising the second power supply voltage VDD2 after the first power supply voltage VDD1 rises to the voltage value V5 and the internal signal state of the second regulator 20 becomes more stable. This suppresses an increase in the transient fluctuation of the second power supply voltage VDD2. The voltage value V5 is, for example, higher than the voltage value V4 and lower than the voltage value V3.

[0044] The third delay time d3 may be set to be equal to or longer than the time it takes for the first power supply voltage VDD1 to rise from zero to a voltage value V3 after the input voltage VDD rises from zero. This allows the second regulator 20 to start raising the second power supply voltage VDD2 after the first power supply voltage VDD1 rises to the voltage value V3 and the internal signal state of the second regulator 20 becomes more stable. This suppresses an increase in the transient fluctuation of the second power supply voltage VDD2.

[0045] 1, the reference voltage generating circuit 40 includes a startup circuit 41 that controls the startup of a band gap reference circuit 42 so that the reference voltage VREF starts to rise after the input voltage VDD rises. The startup circuit 41 is an example of a first startup circuit that starts the reference voltage VREF after the input voltage VDD rises. The startup circuit 41 is a part of the configuration of the reference voltage generating circuit 40, but may also be a part of the configuration of the startup timing control circuit 50.

[0046] The startup circuit 41 may include a first delay circuit that generates a first time T1 from the rising edge of the input voltage VDD. The startup circuit 41 asserts a startup signal STA of the reference voltage generating circuit 40 after a predetermined first time T1 has elapsed from the rising edge of the input voltage VDD. The startup signal STA is an example of a first start signal. The first time T1 corresponds to a first delay time d1.

[0047] The start-up timing control circuit 50 controls the start-up of the first regulator 10 so that the first power supply voltage VDD1 starts to rise after the reference voltage VREF rises. The start-up timing control circuit 50 is an example of a second start-up circuit that starts the first power supply voltage VDD1 after the reference voltage VREF rises.

[0048] The activation timing control circuit 50 includes a first control circuit 55 that asserts an enable signal CE1 of the first regulator 10 after a predetermined second time T2 has elapsed since the start-up signal STA was asserted. The first control circuit 55 is an example of a second delay circuit that generates the second time T2 from the rising edge of the reference voltage VREF, or an example of a second delay circuit that generates the second time T2 from the assertion of the first activation signal.

[0049] When the enable signal CE1 is asserted, the first regulator 10 raises the first power supply voltage VDD1. This allows the first regulator 10 to raise the first power supply voltage VDD1 after the second delay time d2 has elapsed since the rise of the input voltage VDD. The enable signal CE1 is an example of a second start-up signal.

[0050] The activation timing control circuit 50 includes a second control circuit 56 that asserts an enable signal CE2 of the second regulator 20 after a predetermined third time T3 has elapsed since the start-up signal STA was asserted. The second control circuit 56 is an example of a third delay circuit that generates a third time T3 that is longer than the second time T2 from the rising edge of the reference voltage VREF, or an example of a third delay circuit that generates the third time T3 from the assertion of the first activation signal.

[0051] When the enable signal CE2 is asserted, the second regulator 20 raises the second power supply voltage VDD2. This allows the second regulator 20 to raise the second power supply voltage VDD2 after the third delay time d3 has elapsed since the rise of the input voltage VDD. The enable signal CE2 is an example of a third start-up signal.

[0052] 4 is a diagram showing an example of the configuration of a power supply circuit according to the second embodiment. In the second embodiment, the description of the configuration, operation, and effects similar to those of the first embodiment will be omitted by incorporating the above description. The power supply circuit 102 of the second embodiment differs from the power supply circuit 101 of the first embodiment in that the second regulator 20 generates a second power supply voltage VDD2 higher than the reference voltage VREF based on the input voltage VDD and the reference voltage VREF.

[0053] In the second embodiment, the second regulator 20 is, for example, a linear regulator that controls the second power supply voltage VDD2 to maintain a constant voltage value V4 that is lower than the input voltage VDD and higher than the reference voltage VREF. The second regulator 20 may be a switching regulator that controls the second power supply voltage VDD2 to maintain a constant voltage value V4 that is lower or higher than the input voltage VDD and higher than the reference voltage VREF.

[0054] In the second embodiment, the rising timing of the voltage generated by each circuit is controlled as shown in Fig. 3, thereby suppressing the transient fluctuation of the reference voltage VREF, the first power supply voltage VDD1, or the second power supply voltage VDD2. This reduces the possibility of malfunction or voltage breakdown of the first regulator 10, the second regulator 20, or the load 201.

[0055] In the second embodiment, the start-up timing control circuit 50 may control the start-up of the first regulator 10 and the second regulator 20 so that the first power supply voltage VDD1 and the second power supply voltage VDD2 rise simultaneously after the second delay time d2 has elapsed since the rise of the input voltage VDD. This suppresses transient fluctuations in the first power supply voltage VDD1 or the second power supply voltage VDD2, thereby reducing the possibility of the second regulator 20 or the load 201 malfunctioning or suffering a voltage breakdown.

[0056] 5 is a diagram showing an example of the configuration of a power supply circuit according to the third embodiment. In the third embodiment, the description of the configuration, operation, and effects similar to those of the first embodiment will be omitted by incorporating the above description. The power supply circuit 103 of the third embodiment differs from the power supply circuit 101 of the first embodiment in that it does not include a second regulator 20 and a first power supply voltage VDD1 generated by a first regulator 10 is supplied to a load 201.

[0057] In the third embodiment, the rising timing of the voltage generated by each circuit is controlled as shown in Fig. 3, thereby suppressing the transient fluctuation of the reference voltage VREF or the first power supply voltage VDD1. This reduces the possibility of the first regulator 10 or the load 201 malfunctioning or suffering a voltage breakdown.

[0058] 6 is a diagram showing an example of the configuration of a power supply circuit according to the fourth embodiment. In the fourth embodiment, the description of the configuration, operation, and effects similar to those of the first embodiment will be omitted by incorporating the above description. The power supply circuit 104 of the fourth embodiment differs from the power supply circuit 101 of the first embodiment in that it further includes a third regulator 30.

[0059] The third regulator 30 is a circuit that generates a third power supply voltage VDD3 higher than the reference voltage VREF based on the input voltage VDD and the reference voltage VREF. The third regulator 30 controls the third power supply voltage VDD3 to be kept at a constant voltage value V6 higher than the reference voltage VREF. The third power supply voltage VDD3 is supplied to the load 202.

[0060] The third regulator 30 is, for example, a linear regulator that controls the third power supply voltage VDD3 to be kept at a constant voltage value V6 that is lower than the input voltage VDD and higher than the reference voltage VREF. A specific example of the third regulator 30 is an LDO regulator that operates even when the input / output voltage difference is small.

[0061] A steady voltage value V6 after the third power supply voltage VDD3 rises is, for example, 2.5 volts.

[0062] The third regulator 30 may be a switching regulator that controls the third power supply voltage VDD3 to be kept at a constant voltage value V6 that is lower or higher than the input voltage VDD and higher than the reference voltage VREF.

[0063] In the fourth embodiment, the rising timing of the voltage generated by each circuit is controlled as shown in Fig. 3, thereby suppressing the transient fluctuation of the reference voltage VREF, the first power supply voltage VDD1, the second power supply voltage VDD2, or the third power supply voltage VDD3. This reduces the possibility of malfunction or voltage breakdown of the first regulator 10, the second regulator 20, the third regulator 30, the load 201, or the load 202.

[0064] In the fourth embodiment, the start-up timing control circuit 50 may control the start-up of the first regulator 10 and the third regulator 30 so that the first power supply voltage VDD1 and the third power supply voltage VDD3 rise simultaneously or with a time lag after the second delay time d2 has elapsed since the rise of the input voltage VDD. This suppresses transient fluctuations in the first power supply voltage VDD1 or the third power supply voltage VDD3, thereby reducing the possibility of malfunction or voltage breakdown of the second regulator 20, the load 201, or the load 202.

[0065] The activation timing control circuit 50 asserts the enable signal CE3 of the third regulator 30 after a predetermined second time T2 or a predetermined fourth time T4 has elapsed since the start-up signal STA was asserted. When the enable signal CE3 is asserted, the third regulator 30 raises the third power supply voltage VDD3. This allows the third regulator 30 to raise the third power supply voltage VDD3 after the second delay time d2 has elapsed since the rise of the input voltage VDD. The enable signal CE3 is an example of a fourth activation signal.

[0066] 7 is a diagram showing an example of the configuration of a reference voltage generating circuit 40. The reference voltage generating circuit 40 includes a startup circuit 41 and a bandgap reference circuit 42.

[0067] The startup circuit 41 asserts a startup signal STA that controls the startup of the reference voltage generating circuit 40 so that the reference voltage VREF starts to rise after a predetermined first time T1 has elapsed since the rise of the input voltage VDD. The first time T1 corresponds to a first delay time d1.

[0068] The bandgap reference circuit 42 includes resistors R1, R2, R3, and R4, a pair of diodes (here, diode-connected PNP bipolar transistors Q1 and Q2), and an operational amplifier 43. The bandgap reference circuit 42 may have another known circuit configuration.

[0069] The operational amplifier 43 operates with an input voltage VDD. The operational amplifier 43 has a non-inverting input terminal connected to a node N1 between the emitter of the bipolar transistor Q1 and a resistor R1, and an inverting input terminal connected to a node N2 between the resistors R2 and R3. The resistor R3 is connected in series between the node N2 and the emitter of the bipolar transistor Q2. The output terminal of the operational amplifier 43 is connected to the node N1 via resistors R4 and R1, and to the node N2 via resistors R4 and R2.

[0070] By having such a configuration, the bandgap reference circuit 42 can maintain the reference voltage VREF at a constant value (about 1.25 volts) even if the input voltage VDD or the ambient temperature changes.

[0071] When the startup signal STA is asserted, the bandgap reference circuit 42 raises the reference voltage VREF, which allows the reference voltage generating circuit 40 to start outputting the reference voltage VREF after the input voltage VDD rises to the steady-state voltage value V1 and the stability of the internal signal state of the bandgap reference circuit 42 increases.

[0072] For example, when the start-up signal STA is asserted, the input voltage VDD is applied to the operational amplifier 43. This causes the reference voltage generating circuit 40 to start outputting the reference voltage VREF to each of the regulators described above.

[0073] 8 is a diagram showing an example of the configuration of a startup circuit 41. The startup circuit 41 includes a first delay circuit 80 that generates a first time T1 from the rising edge of the input voltage VDD. The startup circuit 41 asserts a startup signal STA for raising the reference voltage VREF after the first time T1 has elapsed.

[0074] The first delay circuit 80 has a capacitor 82, a charging circuit 81 that charges the capacitor 82 with an input voltage VDD, and a buffer circuit 83 that receives the voltage of the capacitor 82 and outputs a startup signal STA. The charging circuit 81 includes a plurality of MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) connected in series to the capacitor 82. The plurality of MOSFETs include a diode-connected first MOSFET and a plurality of second MOSFETs whose gates are connected to each other. The source of the first MOSFET is connected to a terminal of the input voltage VDD. The gates of the plurality of second MOSFETs are connected to a ground AVSS.

[0075] 9 is a diagram showing an example of the configuration of the first regulator. The first regulator 10 has an output transistor 11, an input circuit 12, an error amplifier 13, a feedback circuit 14, and a discharge transistor 15. The input circuit 12 includes an inverter 12a and an inverter 12b. The feedback circuit 14 includes a capacitor 14c and bleeder resistors 14a and 14b.

[0076] When the enable signal CE1 is asserted, the input circuit 12 turns off the discharge transistor 16 by the output of the inverter 12a, and starts the error amplifier 13, which controls the output transistor 11, by the output of the inverter 12b. The error amplifier 13 controls the gate of the output transistor 11 in accordance with the difference between the reference voltage VREF from the reference voltage generation circuit 40 and the output feedback voltage from the feedback circuit 14. In this way, the first regulator 10 maintains the first power supply voltage VDD1 at a constant voltage value.

[0077] When the enable signal CE1 is negated, the input circuit 12 turns on the discharge transistor 16 by the output of the inverter 12a, and stops the error amplifier 13 that controls the output transistor 11 by the output of the inverter 12b. As a result, the first regulator 10 reduces the first power supply voltage VDD1 toward zero.

[0078] 10 is a diagram showing an example of the configuration of the second regulator. The second regulator 20 has an output transistor 21, an input circuit 22, an error amplifier 23, a feedback circuit 24, and a discharge transistor 25. The input circuit 22 includes an inverter 22a and an inverter 22b. The feedback circuit 24 includes a capacitor 24c and bleeder resistors 24a and 24b. The second regulator 20 differs from the first regulator 10 in the size of the output transistor and the resistance value of the bleeder resistor.

[0079] When the enable signal CE2 is asserted, the input circuit 22 turns off the discharge transistor 26 by the output of the inverter 22a, and starts the error amplifier 23, which controls the output transistor 21, by the output of the inverter 22b. The error amplifier 23 controls the gate of the output transistor 21 in accordance with the difference between the reference voltage VREF from the reference voltage generation circuit 40 and the output feedback voltage from the feedback circuit 24. In this way, the second regulator 20 maintains the second power supply voltage VDD2 at a constant voltage value.

[0080] When the enable signal CE2 is negated, the input circuit 22 turns on the discharge transistor 26 by the output of the inverter 22a, and stops the error amplifier 23 that controls the output transistor 21 by the output of the inverter 22b. As a result, the second regulator 20 reduces the second power supply voltage VDD2 toward zero.

[0081] 11 is a diagram showing a first configuration example of the start-timing control circuit. The start-timing control circuit 50A is an example of the start-timing control circuit 50. The start-timing control circuit 50A has a plurality of (four in this example) delay circuits 51, 52, 53, and 54 that are identical to each other in configuration.

[0082] The delay circuit 51 includes a transistor 51a, a capacitor 51b, a constant current source 51c, and an inverting circuit 51d. The transistor 51a is turned on or off depending on the logic level of a startup signal STA input to the gate. The capacitor 51b is connected in parallel to the transistor 51a. The capacitor 51b is discharged when the transistor 51a is turned on, and is charged by a constant current supplied from the constant current source 51c when the transistor 51a is turned off. The inverting circuit 51d outputs a signal obtained by inverting the voltage level of the capacitor 51b to the next-stage delay circuit 52. The delay circuits 52, 53, and 54 each receive the output of the delay circuit in the previous stage.

[0083] The delay circuits 51 and 52 assert the enable signal CE1 of the first regulator 10 after a predetermined second time T2 has elapsed since the start-up signal STA was asserted. The delay circuits 51 and 52 are an example of a second delay circuit that generates the second time T2 from the rising edge of the reference voltage VREF.

[0084] The delay circuits 51, 52, 53, and 54 assert the enable signal CE2 of the second regulator 20 after a predetermined third time T3 has elapsed since the start-up signal STA was asserted. The delay circuits 51, 52, 53, and 54 are an example of a third delay circuit that generates a third time T3 that is longer than the second time T2 from the rising edge of the reference voltage VREF.

[0085] The delay circuits 51 and 52 that generate the enable signal CE1 share a portion of the delay circuits 51, 52, 53, and 54 that generate the enable signal CE2. By sharing some of the circuits, the circuit scale of the activation timing control circuit 50A that generates the enable signals CE1 and CE2 can be reduced.

[0086] 12 is a diagram showing a second configuration example of the start timing control circuit. The start timing control circuit 50B is an example of the start timing control circuit 50. The start timing control circuit 50B has a voltage dividing circuit 61 which resistively divides the reference voltage VREF, a voltage dividing circuit 62 which resistively divides the input voltage VDD, and a comparison circuit 63 which compares the divided output of the voltage dividing circuit 61 with the divided output of the voltage dividing circuit 62. When the reference voltage VREF rises above the first divided voltage of the input voltage VDD, the comparison circuit 63 asserts an enable signal CE1. The voltage dividing circuits 61 and 62 and the comparison circuit 63 function as a second delay circuit which generates a second time T2 from the rising edge of the reference voltage VREF.

[0087] The start timing control circuit 50B has a voltage dividing circuit 71 which resistively divides the first power supply voltage VDD1, a voltage dividing circuit 72 which resistively divides the input voltage VDD, and a comparison circuit 73 which compares the divided output of the voltage dividing circuit 71 with the divided output of the voltage dividing circuit 72. When the first power supply voltage VDD1 rises above the second divided voltage of the input voltage VDD, the comparison circuit 73 asserts an enable signal CE2. The voltage dividing circuits 71 and 72 and the comparison circuit 73 function as a third delay circuit which generates a third time T3 which is longer than the second time T2 from the rising edge of the reference voltage VREF.

[0088] As described above, the embodiment has been described, but the above embodiment is presented as an example, and the present invention is not limited to the above embodiment. The above embodiment can be implemented in various other forms, and various combinations, omissions, substitutions, modifications, etc. can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0089] 10 First regulator 12 Input circuit 12a, 12b Inverter 12b Inverter 13 Error Amplifier 14 Feedback Circuit 14a, 14b Bleeder resistance 14c capacitor 15,16 Discharge transistor 20 Second regulator 21 Output transistor 22 Input circuit 22a, 22b Inverter 23 Error Amplifier 24 Feedback Circuit 24a, 24b Bleeder resistance 24c capacitor 25,26 Discharge transistor 30 Third regulator 40 Reference voltage generation circuit 41 Start-up circuit 42 Bandgap Reference Circuit 43 Operational Amplifiers 50, 50A, 50B Start-up timing control circuit 51, 52, 53, 54 Delay circuit 51a Transistor 51b Capacitor 51c constant current source 51d Inverting circuit 55 First control circuit 56 Second control circuit 61,62 Voltage divider circuit 63 Comparison circuit 71,72 Voltage divider circuit 73 Comparison circuit 80 First delay circuit 81 Charging circuit 82 Capacitor 83 Buffer Circuit 101,102,103,104 Power supply circuit 201,202 Load AVSS Grand N1,N2 nodes Q1, Q2 Bipolar transistor R1,R2,R3,R4 Resistance

Claims

1. a reference voltage generating circuit for generating a reference voltage lower than an input voltage; a first regulator that generates a first power supply voltage higher than the reference voltage based on the input voltage and the reference voltage; a first startup circuit that controls the reference voltage generating circuit so that the reference voltage rises after the input voltage rises; a second startup circuit that controls the first regulator so that the first power supply voltage rises after the reference voltage rises.

2. 2. The power supply circuit according to claim 1, wherein the first startup circuit includes a first delay circuit that generates a first time from a rising edge of the input voltage, and causes the reference voltage to rise after the first time has elapsed.

3. 3. The power supply circuit according to claim 2, wherein the first startup circuit asserts a first startup signal of the reference voltage generating circuit after the first time period has elapsed.

4. the reference voltage generating circuit includes a bandgap reference circuit that generates the reference voltage; The power supply circuit according to claim 3 , wherein the bandgap reference circuit raises the reference voltage when the first startup signal is asserted.

5. 4. The power supply circuit according to claim 3, wherein the second startup circuit starts up the first power supply voltage after the first startup signal is asserted.

6. 6. The power supply circuit according to claim 5, wherein the second startup circuit includes a second delay circuit that generates a second time after the first startup signal is asserted, and raises the first power supply voltage after the second time has elapsed.

7. 7. The power supply circuit according to claim 6, wherein the second startup circuit asserts a second startup signal for the first regulator after the second time period has elapsed.

8. a second regulator configured to generate a second power supply voltage higher than the reference voltage based on the first power supply voltage and the reference voltage; 2. The power supply circuit according to claim 1, wherein the second startup circuit controls the second regulator so that the second power supply voltage rises after the first power supply voltage rises.

9. The second start-up circuit includes: a second delay circuit that generates a second time from a rising edge of the reference voltage; a third delay circuit that generates a third time period from the rising edge of the reference voltage that is longer than the second time period; After the second time has elapsed, the first power supply voltage is started up; 9. The power supply circuit according to claim 8, wherein the second power supply voltage is raised after the third period of time has elapsed.

10. 10. The power supply circuit according to claim 9, wherein the second delay circuit is common to a portion of the third delay circuit.

11. the first startup circuit causes the reference voltage to rise after a first delay time has elapsed since the rise of the input voltage; 2. The power supply circuit according to claim 1, wherein the second startup circuit raises the first power supply voltage after a second delay time, which is longer than the first delay time, has elapsed from the rising edge of the input voltage.

12. a second regulator configured to generate a second power supply voltage higher than the reference voltage based on the first power supply voltage and the reference voltage; 12. The power supply circuit according to claim 11, wherein the second startup circuit raises the first power supply voltage and the second power supply voltage after the second delay time has elapsed since the rise of the input voltage.

13. When a delay time longer than the second delay time from the rising edge of the input voltage is set as a third delay time, 13. The power supply circuit according to claim 12, wherein the second startup circuit raises the first power supply voltage during a period from the second delay time to the third delay time, and raises the second power supply voltage after the third delay time has passed.

14. a reference voltage generating circuit for generating a reference voltage lower than an input voltage; a first regulator that generates a first power supply voltage higher than the reference voltage based on the input voltage and the reference voltage, A power supply circuit startup method, comprising: raising the reference voltage after the input voltage has risen; and raising the first power supply voltage after the reference voltage has risen.

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