Semiconductor device

Abstract

To obtain a semiconductor device capable of sufficiently reducing loss.SOLUTION: A trench 5 in a first region 1a includes a first trench 5a and two or more second trenches 5b sandwiching the first trench 5a from both sides. Gate electrodes 7 formed in the two or more second trenches 5b are connected to each other and are not connected to the gate electrode 7 formed in the first trench 5a. The gate electrode 7 formed in the trench 5 in the second region 1b is connected to an emitter electrode 9. A base layer 3 is connected to the emitter electrode 9 in the region sandwiched between the first region 1a and the second region 1b.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] A semiconductor device has been proposed that reduces turn-on loss by using a macro thinning-out structure in which a first region in which three or more active trenches are arranged alternately with a second region in which a plurality of dummy trenches are arranged (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6743026 Summary of the Invention [Problem to be solved by the invention]

[0004] Conventional semiconductor devices with a macro thinning-out structure have not taken multi-gate driving into consideration, and therefore have had the problem of being unable to sufficiently reduce losses.

[0005] The present disclosure has been made to solve the above-mentioned problems, and has an object to obtain a semiconductor device that can sufficiently reduce losses. [Means for solving the problem]

[0006] A semiconductor device according to the present disclosure includes a semiconductor substrate of a first conductivity type having a first region and a second region adjacent to each other, a base layer of a second conductivity type formed on an upper surface of the semiconductor substrate, a source layer of the first conductivity type formed on an upper surface of the base layer, a plurality of gate electrodes formed via gate insulating films inside a plurality of trenches extending from the upper surface of the semiconductor substrate through the source layer and the base layer, an emitter electrode formed on the upper surface of the semiconductor substrate, a collector layer of a second conductivity type formed on a lower surface of the semiconductor substrate, and a collector electrode formed on the lower surface of the semiconductor substrate, wherein the trench in the first region has a first trench and two or more second trenches sandwiching the first trench from both sides, the gate electrodes formed in the two or more second trenches are connected to each other and are not connected to the gate electrode formed in the first trench, the gate electrode formed in the trench in the second region is connected to the emitter electrode, and the base layer is connected to the emitter electrode in a region sandwiched between the first region and the second region. Effect of the Invention

[0007] In the present disclosure, two or more second trenches are formed in the first region of the macro thinning structure so as to sandwich the first trench from both sides. The gate electrodes of the two or more second trenches are connected to each other and are not connected to the gate electrode of the first trench. In addition, the base layer is connected to the emitter electrode in the region sandwiched between the first and second regions. For example, by turning off the gate electrode of the second trench at an earlier timing than the gate electrode of the first trench at the time of turn-off, holes flowing from below the second region to below the first region can be discharged to the emitter electrode through the side of the second trench, thereby reducing the turn-off loss. As a result, the loss can be sufficiently reduced. [Brief description of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view showing a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a diagram illustrating driving of the semiconductor device according to the first embodiment. [Diagram 3] 1 is a cross-sectional view showing a first modified example of the semiconductor device according to the first embodiment. [Figure 4] 10 is a cross-sectional view showing a second modified example of the semiconductor device according to the first embodiment. [Diagram 5] 11 is a cross-sectional view showing a third modified example of the semiconductor device according to the first embodiment. FIG. [Figure 6] FIG. 11 is a cross-sectional view showing a fourth modified example of the semiconductor device according to the first embodiment. [Figure 7] FIG. 11 is a cross-sectional view showing a semiconductor device according to a second embodiment. [Figure 8] FIG. 11 is a cross-sectional view showing a modified example of the semiconductor device according to the second embodiment. [Figure 9] FIG. 11 is a cross-sectional view showing a semiconductor device according to a third embodiment. [Figure 10] FIG. 11 is a cross-sectional view showing a first modified example of the semiconductor device according to the third embodiment. [Figure 11] FIG. 11 is a cross-sectional view showing a second modified example of the semiconductor device according to the third embodiment. [Figure 12] FIG. 11 is a cross-sectional view showing a third modified example of the semiconductor device according to the third embodiment. [Figure 13] FIG. 11 is a cross-sectional view showing a fourth modified example of the semiconductor device according to the third embodiment. [Figure 14] FIG. 11 is a cross-sectional view showing a fifth modified example of the semiconductor device according to the third embodiment. [Figure 15] FIG. 11 is a cross-sectional view showing a semiconductor device according to a fourth embodiment. [Figure 16] FIG. 11 is a cross-sectional view showing a modified example of the semiconductor device according to the fourth embodiment. [Figure 17] FIG. 11 is a cross-sectional view showing a semiconductor device according to a fifth embodiment. [Figure 18] FIG. 13 is a cross-sectional view showing a modified example of the semiconductor device according to the fifth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] A semiconductor device according to an embodiment will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted.

[0010] In the following description, n and p indicate the conductivity type of a semiconductor, and the first conductivity type will be described as n-type and the second conductivity type as p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type. - indicates that the impurity concentration is lower than n, and n + indicates that the impurity concentration is higher than n. Similarly, p + indicates that the impurity concentration is higher than p. The effects of the present invention may be enhanced by appropriately combining the features of the semiconductor device according to each embodiment.

[0011] Embodiment 1 1 is a cross-sectional view showing a semiconductor device according to embodiment 1. This semiconductor device is an insulated gate bipolar transistor (hereinafter abbreviated as IGBT).

[0012] The semiconductor substrate 1 is n - The n-type impurity in the semiconductor substrate 1 is, for example, arsenic or phosphorus. The concentration of the n-type impurity in the semiconductor substrate 1 is 1.0E+12 / cm 3 ~1.0E+15 / cm 3 The semiconductor substrate 1 has a first region 1a and a second region 1b adjacent to each other.

[0013] The n-type carrier accumulation layer 2 is - The n-type impurity of the n-type carrier accumulation layer 2 is, for example, arsenic or phosphorus. The concentration of the n-type impurity of the n-type carrier accumulation layer 2 is 1.0E+13 / cm 3 ~1.0E+17 / cm 3 By forming the n-type carrier accumulation layer 2, it is possible to reduce the current loss when a current flows. -The n-type drift layer may be provided. - The above-mentioned layer and the type drift layer may be collectively referred to as a drift layer.

[0014] The p-type base layer 3 is formed on the upper surface side of the n-type carrier accumulation layer 2. That is, the n-type carrier accumulation layer 2 is formed below the p-type base layer 3. The p-type impurity of the p-type base layer 3 is, for example, boron or aluminum. The impurity concentration of the p-type base layer 3 is 1.0E+12 / cm 3 ~1.0E+19 / cm 3 n + The p-type source layer 4 is formed on the upper surface side of the p-type base layer 3. + The n-type impurity in the n-type source layer 4 is, for example, arsenic or phosphorus. + The impurity concentration of the source layer 4 is 1.0E+17 / cm 3 ~1.0E+20 / cm 3 It is.

[0015] A plurality of trenches 5 are formed on the semiconductor substrate 1 from the upper surface side thereof. + The n-type source layer 4, the p-type base layer 3, and the n-type carrier accumulation layer 2 are penetrated by the n - The trench 5 is formed so as to reach the n-type drift layer. A gate insulating film 6 is formed along the inner wall of the trench 5. A plurality of gate electrodes 7 are formed inside the plurality of trenches 5 with the gate insulating film 6 interposed therebetween. The gate electrodes 7 are connected to the n-type drift layer through the gate insulating film 6. + a p-type source layer 4, a p-type base layer 3, an n-type carrier accumulation layer 2, and an n - The semiconductor substrate 1 faces the drift layer.

[0016] Along the extension direction of the trench 5, + Type source layer 4 and p + Alternating contact layers (not shown) are formed on the n + The source layer 4 and the p + The contact layer constitutes the upper surface of the semiconductor substrate 1. + The p-type impurity of the p-type contact layer is, for example, boron or aluminum. + The p-type impurity concentration of the contact layer is higher than that of the p-type base layer 3, and is 1.0E+15 / cm3 ~1.0E+20 / cm 3 It is. + When it is necessary to distinguish between the p-type contact layer and the p-type base layer 3, they may be referred to individually. + The type contact layer and the p-type base layer 3 may be collectively referred to as a p-type base layer.

[0017] An interlayer insulating film 8 is formed on the trench 5. Although not shown, a barrier metal is formed on the region of the upper surface of the semiconductor substrate 1 where the interlayer insulating film 8 is not formed, and on the interlayer insulating film 8. The barrier metal is a conductor containing titanium (Ti), such as titanium nitride or TiSi, which is an alloy of titanium and silicon (Si). The barrier metal is a n + The source layer 4 and the p + Ohmic contact to the n-type contact layer + The source layer 4 and the p + The emitter electrode 9 is formed on the upper surface of the semiconductor substrate 1 and is electrically connected to the n-type contact layer. An emitter electrode 9 is formed on the upper surface of the semiconductor substrate 1 and is connected to a barrier metal. The emitter electrode 9 is, for example, an aluminum alloy such as an aluminum silicon alloy (Al-Si alloy), and may be an electrode made of a multi-layer metal film formed by forming a plating film by electroless plating or electrolytic plating on an electrode formed of an aluminum alloy. The plating film formed by electroless plating or electrolytic plating is, for example, a nickel (Ni) plating film. If the emitter electrode 9 cannot be used to fill the fine region between adjacent interlayer insulating films 8 satisfactorily, tungsten, which has better filling properties than the emitter electrode 9, may be formed in the fine region, and the emitter electrode 9 may be formed on the tungsten. Note that it is also possible to form the n-type contact layer without forming a barrier metal. + The source layer 4 and the p + An emitter electrode 9 may be formed on the contact layer. + Alternatively, the barrier metal may be formed only on the n-type semiconductor layer such as the n-type source layer 4. The combination of the barrier metal and the emitter electrode 9 may be called the emitter electrode.

[0018] The n-type buffer layer 10 is -The n-type impurities in the n-type buffer layer 10 are, for example, phosphorus (P) and protons (H + The concentration of the n-type impurity in the n-type buffer layer 10 is n - Higher than the drift layer, 1.0E+12 / cm 3 ~1.0E+18 / cm 3 The n-type buffer layer 10 is provided to suppress punch-through of a depletion layer extending from the p-type base layer 3 to the lower surface side when the semiconductor device is in an off state. - The n-type buffer layer 10 and the n-type drift layer may be provided. - The above-mentioned layer and the type drift layer may be collectively referred to as a drift layer.

[0019] The p-type collector layer 11 is formed on the lower surface side of the n-type buffer layer 10. - A p-type collector layer 11 is formed between the drift layer and the lower surface of the semiconductor substrate 1. The p-type impurity of the p-type collector layer 11 is, for example, boron or aluminum. The impurity concentration of the p-type collector layer 11 is 1.0E+16 / cm 3 ~1.0E+20 / cm 3 The semiconductor substrate 1 is + The source layer 4 and the p + The range is from the p-type contact layer to the p-type collector layer 11 .

[0020] A collector electrode 12 is formed on the lower surface of the semiconductor substrate 1. Similar to the emitter electrode 9, the collector electrode 12 is made of an aluminum alloy or an aluminum alloy and a plating film. The collector electrode 12 may have a different structure from the emitter electrode 9. The collector electrode 12 is in ohmic contact with the p-type collector layer 11 and is electrically connected to the p-type collector layer 11.

[0021] Three or more trenches 5 are formed in the first region 1a. In this embodiment, the trenches 5 in the first region 1a include an active trench 5a and two or more control gate trenches 5b sandwiching the active trench 5a from both sides. The gate electrodes 7 formed in the two or more control gate trenches 5b are connected to each other and are not connected to the gate electrode 7 formed in the active trench 5a.

[0022] One or more trenches 5 are formed in the second region 1b. The trenches 5 in the second region 1b are dummy trenches 5c. The gate electrode 7 formed in the dummy trench 5c is connected to the emitter electrode 9. In a region sandwiched between the first region 1a and the second region 1b, the p-type base layer 3 is connected to the emitter electrode 9.

[0023] The gate insulating film 6 of the active trench 5a is connected to the p-type base layer 3 and the n + When a gate drive voltage is applied to the gate electrode 7 of the active trench 5a, a channel is formed in the p-type base layer 3 that is in contact with the gate insulating film 6 of the active trench 5a. + The n-type source layer 4 only needs to be in contact with the active trench 5a, and does not need to be in contact with the dummy trench 5c. + The type source layer 4 does not have to be formed in the region sandwiched between the dummy trenches 5c.

[0024] 2 is a diagram showing the operation of the semiconductor device according to the first embodiment. When the IGBT is turned on, the control unit 13 turns on the gate electrode 7 of the control gate trench 5b at a timing that is later than the gate electrode 7 of the active trench 5a by a time t1. When the IGBT is turned off, the control unit 13 turns off the gate electrode 7 of the control gate trench 5b at a timing that is earlier than the gate electrode 7 of the active trench 5a by a time t2.

[0025] Next, a method for manufacturing the semiconductor device according to the first embodiment will be described. -A semiconductor substrate 1 constituting a type drift layer is prepared. For example, an FZ wafer produced by the FZ (Floating Zone) method or an MCZ wafer produced by the MCZ (Magnetic applied CZochralki) method is used as the semiconductor substrate 1. An n-type wafer containing n-type impurities may be used as the semiconductor substrate 1. The concentration of the n-type impurities contained in the semiconductor substrate 1 is appropriately selected depending on the withstand voltage of the semiconductor device to be fabricated. For example, in a semiconductor device with a withstand voltage of 1200V, - The concentration of n-type impurities in the semiconductor substrate 1 is adjusted so that the resistivity of the n-type drift layer is about 40 to 120 Ω·cm. In the step of preparing the semiconductor substrate 1, the entire semiconductor substrate 1 is - A p-type or n-type drift layer is formed by injecting p-type or n-type impurity ions from the upper surface or the lower surface of the semiconductor substrate 1 and then diffusing the ions into the semiconductor substrate 1 by heat treatment or the like, thereby forming a p-type or n-type semiconductor layer.

[0026] Next, n-type impurities such as phosphorus (P) are implanted from the upper surface side of the semiconductor substrate 1. - The n-type carrier accumulation layer 2 is formed by diffusing the n-type impurities into the n-type drift layer. In addition, p-type impurities such as boron (B) are injected from the upper surface side of the semiconductor substrate 1 to form a p-type base layer 3. The n-type carrier accumulation layer 2 and the p-type base layer 3 are formed by injecting impurity ions into the semiconductor substrate 1 and then diffusing the impurity ions by heat treatment. The n-type impurities and the p-type impurities are ion-injected after masking the upper surface of the semiconductor substrate 1, so that the n-type carrier accumulation layer 2 and the p-type base layer 3 are selectively formed on the upper surface side of the semiconductor substrate 1. The masking process is a process in which a resist is applied to the upper surface of the semiconductor substrate 1 and openings are formed in predetermined areas of the resist using photolithography to form a mask. Ion implantation or etching is performed in predetermined areas of the semiconductor substrate 1 through the openings in the mask.

[0027] Next, n-type impurities are selectively injected into the upper surface of the p-type base layer 3 by mask processing. +The n-type source layer 4 is formed. The n-type impurity to be implanted is, for example, arsenic (As) or phosphorus (P). In addition, the p-type impurity is selectively implanted into the upper surface side of the p-type base layer 3 by mask processing to form a p + A p-type contact layer is formed. The p-type impurity to be implanted is, for example, boron (B) or aluminum (Al).

[0028] Next, an oxide film such as SiO2 is deposited on the upper surface of the semiconductor substrate 1, and then an opening is formed in the oxide film at a portion where the trench 5 is to be formed by masking. The semiconductor substrate 1 is etched using the oxide film with the opening formed as a mask to form the trench 5. The trench 5 is formed by arranging the p-type base layer 3 and the n-type base layer 4 from the upper surface side of the semiconductor substrate 1. + The n-type source layer 4 is penetrated - The drift layer is reached. + The sidewall of the trench 5 penetrating the n-type source layer 4 + It constitutes a part of the mold source layer 4 .

[0029] Next, the semiconductor substrate 1 is heated in an atmosphere containing oxygen to form a gate insulating film 6 on the inner wall of the trench 5 and on the upper surface of the semiconductor substrate 1. In the trench 5 with the gate insulating film 6 formed on the inner wall, polysilicon doped with n-type or p-type impurities is deposited by CVD (chemical vapor deposition) or the like to form a gate electrode 7.

[0030] Next, the interlayer insulating film 8 is formed on the trench 5, and then the gate insulating film 6 formed on the upper surface of the semiconductor substrate 1 is removed. The interlayer insulating film 8 is, for example, SiO2. + The source layer 4 and the p + A contact hole is formed in the interlayer insulating film 8 above the mold contact layer by mask processing.

[0031] Next, a barrier metal is formed on the upper surface of the semiconductor substrate 1 and on the interlayer insulating film 8. An emitter electrode 9 is formed on the barrier metal. For example, the barrier metal is formed by depositing titanium nitride by physical vapor deposition (PDV) or CVD. For example, an aluminum silicon alloy (Al-Si alloy) is deposited on the barrier metal by PVD such as sputtering or evaporation to form the emitter electrode 9. Alternatively, a nickel alloy (Ni alloy) may be further formed on the formed aluminum silicon alloy by electroless plating or electrolytic plating to form the emitter electrode 9. Since a thick metal film can be easily formed as the emitter electrode 9 by plating, the heat capacity of the emitter electrode 9 can be increased to improve its heat resistance.

[0032] Next, the lower surface side of the semiconductor substrate 1 is ground to thin the semiconductor substrate 1 to a predetermined thickness. The thickness of the semiconductor substrate 1 after grinding is, for example, 80 μm to 200 μm. Note that, when a nickel alloy is further formed by plating after forming the emitter electrode 9 made of an aluminum silicon alloy by PVD, the plating for forming the nickel alloy may be performed after processing the lower surface side of the semiconductor substrate 1.

[0033] Next, n-type impurities are implanted from the bottom surface of the semiconductor substrate 1 to form an n-type buffer layer 10. For example, phosphorus (P) ions or protons (H +) to form the n-type buffer layer 10. Both protons and phosphorus may be implanted. Protons can be implanted to a deep position from the bottom surface of the semiconductor substrate 1 with a relatively low acceleration energy. The depth to which protons are implanted can be changed relatively easily by changing the acceleration energy. For this reason, when forming the n-type buffer layer 10 with protons, if protons are implanted multiple times while changing the acceleration energy, an n-type buffer layer 10 that is wider in the thickness direction of the semiconductor substrate 1 than that formed with phosphorus can be formed. In addition, phosphorus can increase the activation rate as an n-type impurity compared to protons. For this reason, by forming the n-type buffer layer 10 with phosphorus, punch-through of the depletion layer can be more reliably suppressed even in the semiconductor substrate 1 that has been thinned. To further thin the semiconductor substrate 1, it is preferable to form the n-type buffer layer 10 by implanting both protons and phosphorus. In this case, protons are implanted deeper from the bottom surface than phosphorus.

[0034] Next, p-type impurities are injected from the lower surface side of the semiconductor substrate 1 to form a p-type collector layer 11. For example, boron (B) is injected to form the p-type collector layer 11. After ion injection from the lower surface side of the semiconductor substrate 1, the lower surface is irradiated with a laser to perform laser annealing, thereby activating the injected boron and forming the p-type collector layer 11. At this time, phosphorus for the n-type buffer layer 10, which is injected at a relatively shallow position from the lower surface of the semiconductor substrate 1, is also activated at the same time. On the other hand, since protons are activated at a relatively low annealing temperature of 350°C to 500°C, care must be taken not to raise the temperature of the entire semiconductor substrate 1 to a temperature higher than 350°C to 500°C after the protons are injected, except for the process for activating the protons. Since laser annealing can raise the temperature only near the lower surface of the semiconductor substrate 1, it can be used to activate n-type impurities or p-type impurities even after the protons are injected.

[0035] Next, a collector electrode 12 is formed on the lower surface of the semiconductor substrate 1. The collector electrode 12 may be formed over the entire lower surface of the n-type wafer, which is the semiconductor substrate 1. The collector electrode 12 is formed by depositing an aluminum silicon alloy (Ai-Si alloy) or titanium (Ti) by PVD such as sputtering or vapor deposition, but may also be formed by laminating a plurality of metals such as an aluminum silicon alloy, titanium, nickel, or gold. The collector electrode 12 may also be formed by forming a further metal film by electroless plating or electrolytic plating on a metal film formed by PVD.

[0036] The semiconductor device according to the present embodiment is manufactured by the above-mentioned process. A plurality of semiconductor devices are manufactured in a matrix on one n-type wafer. The semiconductor devices are completed by cutting the wafer into individual semiconductor devices by laser dicing or blade dicing.

[0037] As described above, the semiconductor device according to this embodiment has a macro thinning structure in which the first region 1a in which three or more trenches 5 including the active trench 5a are formed and the second region 1b in which one or more dummy trenches 5c are formed are adjacent to each other. Such a macro thinning structure can reduce turn-on loss. However, holes below the second region 1b in which no electrons are injected flow below the first region 1a in which electrons are injected, causing a lateral bias in hole density and increasing turn-off loss. Therefore, in this embodiment, two or more control gate trenches 5b are formed in the first region 1a so as to sandwich the active trench 5a from both sides. In addition, the p-type base layer 3 is connected to the emitter electrode 9 in the region sandwiched between the first region 1a and the second region 1b. By turning off the gate electrode 7 of the control gate trench 5b at an earlier timing than the gate electrode 7 of the active trench 5a at the time of turn-off, holes flowing from below the second region 1b to below the first region 1a can be discharged to the emitter electrode 9 through the side of the control gate trench 5b, thereby reducing turn-off loss. As a result, loss can be sufficiently reduced.

[0038] Furthermore, when turning on the IGBT, the control unit 13 turns on the gate electrode 7 of the control gate trench 5b at a later timing than the gate electrode 7 of the active trench 5a. Therefore, since the gate electrode 7 of the active trench 5a turns on first, the charging period of the gate capacitance required for turning on can be shortened, and the IGBT can be turned on at high speed. This can further reduce turn-on loss. Note that the control unit 13 may perform only one of the above-mentioned control at the time of turn-off and control at the time of turn-on.

[0039] Furthermore, by forming the n-type carrier accumulation layer 2 below the p-type base layer 3, the electron injection is promoted and the hole accumulation effect is increased, thereby reducing the on-voltage. However, the bias in the hole density in the macro thinning-out structure is further increased, and the turn-off loss increases. In contrast, in this embodiment, holes flowing from below the second region 1b to below the first region 1a can be discharged to the emitter electrode 9 through the side of the control gate trench 5b, thereby reducing the turn-off loss. As a result, the on-voltage can be reduced while the turn-off loss can be reduced.

[0040] FIG. 3 is a cross-sectional view showing a first modified example of the semiconductor device according to the first embodiment. The second region 1b includes one dummy trench 5c, which is less than the three trenches 5 included in the first region 1a. FIG. 4 is a cross-sectional view showing a second modified example of the semiconductor device according to the first embodiment. The second region 1b includes four trenches 5, which is more than the three trenches 5 included in the first region 1a. In this way, it is preferable that the number of dummy trenches 5c included in the second region 1b is equal to or greater than the number of trenches 5 included in the first region 1a. This enhances the effect of reducing the gate-emitter capacitance, which is a feature of the macro thinning structure, and can reduce turn-on loss. In addition, the amount of holes flowing from below the second region 1b to below the first region 1a increases, and the increased amount of holes is discharged to the emitter electrode 9, thereby further reducing turn-on loss.

[0041] 5 is a cross-sectional view showing a third modified example of the semiconductor device according to the first embodiment. An interlayer insulating film 8 is formed across the second region 1b. Therefore, the p-type base layer 3 sandwiched between the dummy trenches 5c in the second region 1b is not connected to the emitter electrode 9. This increases the amount of holes flowing from below the second region 1b to below the first region 1a, and the increased amount of holes is discharged to the emitter electrode 9, thereby further reducing the turn-on loss.

[0042] 6 is a cross-sectional view showing a fourth modified example of the semiconductor device according to the first embodiment. In the first region 1a, the number of control gate trenches 5b is three times or more the number of active trenches 5a. This further enhances the effect of discharging holes from the control gate trenches 5b, thereby further reducing the turn-off loss.

[0043] Embodiment 2 7 is a cross-sectional view showing a semiconductor device according to embodiment 2. In this embodiment, trench 5 in first region 1a has a control gate trench 5b and two or more active trenches 5a sandwiching control gate trench 5b on both sides.

[0044] At the time of turn-off, the control unit 13 turns off the gate electrode 7 of the active trench 5a at a later timing than the gate electrode 7 of the control gate trench 5b. Therefore, at the time of turn-off, electron injection from the control gate trench 5b is eliminated, and the conduction loss (on-voltage) increases. This on-voltage at the time of transition is called a transient on-voltage.

[0045] In the first region 1a, the control gate trench 5b is sandwiched between the active trenches 5a on both sides. This allows electrons to be injected from the active trenches 5a on both sides below the control gate trench 5b that has been turned off at an early timing and no longer injects electrons, thereby reducing conduction loss (excessive on-voltage). As a result, loss can be sufficiently reduced.

[0046] 8 is a cross-sectional view showing a modified example of the semiconductor device according to the second embodiment. In the first region 1a, the number of active trenches 5a is three times or more the number of control gate trenches 5b. This increases the amount of electrons injected from the active trenches 5a, thereby further reducing the conduction loss (transient on-voltage).

[0047] Embodiment 3 9 is a cross-sectional view showing a semiconductor device according to a third embodiment. The semiconductor substrate 1 further includes a third region 1c. A second region 1b is disposed between the first region 1a and the third region 1c. In the first region 1a, an active trench 5a and two or more control gate trenches 5b sandwiching the active trench 5a from both sides are formed, as in the first embodiment. Meanwhile, in the third region 1c, a control gate trench 5b and two or more active trenches 5a sandwiching the control gate trench 5b from both sides are formed.

[0048] There is a trade-off between the conduction loss (transient on-voltage) that can be reduced by a high carrier density and the turn-off loss that can be reduced by a low carrier density, and the ratio of the loss changes depending on the driving frequency used. For example, in high-speed applications where the ratio of switching loss is large, the turn-off loss is emphasized, and in low-speed applications where the ratio of conduction loss is large, the transient on-voltage is emphasized. Therefore, a configuration that can flexibly adjust the loss ratio of the transient on-voltage and the turn-off loss depending on the application is desirable. In contrast, in this embodiment, the ratio of the number of the first regions 1a to the number of the third regions 1c is adjusted to adjust the amount of electron injection and the amount of hole emission, and the loss ratio of the transient on-voltage and the turn-off loss can be adjusted. In FIG. 9, the ratio of the number of the first regions 1a to the number of the third regions 1c is set to 1:1, so the transient on-voltage is lower than in the case of only the first regions 1a.

[0049] 10 is a cross-sectional view showing a first modified example of the semiconductor device according to the third embodiment. The ratio of the number of first regions 1a to the number of third regions 1c is set to 2:1 to adjust the turn-off loss to a lower value. The ratio may be set to 1:2 to adjust the turn-off loss to a lower value. The range of the ratio is described as 1:2 to 2:1, but is not limited thereto. For example, the range of the ratio may be expanded to 1:5 to 5:1 to further expand the adjustment range.

[0050] 11 is a cross-sectional view showing Modification 2 of the semiconductor device according to the third embodiment. Three or more trenches 5 are formed in the third region 1c, and they include one or more active trenches 5a and zero or one or more control gate trenches 5b. The ratio of the active trenches 5a among the trenches 5 formed in the third region 1c is greater than the ratio of the active trenches 5a among the trenches 5 formed in the first region 1a. This allows the gate electrode 7 of the control gate trench 5b to increase the amount of electrons injected during the period after turn-off, and therefore the loss ratio of the transient on-voltage and the turn-off loss can be adjusted to a lower transient on-voltage side.

[0051] Fig. 12 is a cross-sectional view showing Modification 3 of the semiconductor device according to the third embodiment. In Fig. 11, the ratio between the number of first regions 1a and the number of third regions 1c is 1:1, but the ratio may be adjusted to 1:2 as shown in Fig. 12 to further reduce the transient on-state voltage. The ratio is not limited to this, and the reduction rate of the transient on-state voltage can be adjusted by appropriately adjusting it.

[0052] 13 is a cross-sectional view showing a fourth modified example of the semiconductor device according to the third embodiment. In the third region 1c, only one or more control gate trenches 5b are formed as the trenches 5. This can enhance the hole ejection effect, and adjust the loss ratio of the excess on-voltage and the turn-off loss to the low turn-off loss side.

[0053] Fig. 14 is a cross-sectional view showing Modification 5 of the semiconductor device according to the third embodiment. In Fig. 13, the ratio between the number of first regions 1a and the number of third regions 1c is 1:1, but as shown in Fig. 14, the ratio may be adjusted to 1:2 to further reduce the turn-off loss. The ratio is not limited to this, and the reduction rate of the turn-off loss can be adjusted by appropriately adjusting it.

[0054] Embodiment 4 15 is a cross-sectional view showing a semiconductor device according to a fourth embodiment. In this embodiment, the impurity concentration of the n-type carrier accumulation layer 2a in the first region 1a where a channel is formed is higher than the impurity concentration of the n-type carrier accumulation layer 2b in the second region 1b where a channel is not formed. Since the amount of electrons injected from the active trench 5a and the control gate trench 5b can be increased and the amount of holes discharged from the second region 1b can be increased, the trade-off between the on-voltage and the turn-off loss can be improved. The other configurations and effects are the same as those of the first embodiment and the like.

[0055] FIG. 16 is a cross-sectional view showing a modified example of the semiconductor device according to the fourth embodiment. When the amount of electron injection is large at the time of turning on, the time change of the current becomes large, which causes electromagnetic radiation noise. Therefore, the impurity concentration of the n-type carrier accumulation layer 2c in contact with the control gate trench 5b that turns on at a later timing is made higher than the impurity concentration of the n-type carrier accumulation layer 2a in contact with the active trench 5a that turns on at an earlier timing and affects the time change of the current. This makes it possible to reduce the on-voltage without increasing the time change of the current. Therefore, the trade-off between the electromagnetic radiation noise and the on-voltage can be improved.

[0056] Embodiment 5. FIG. 17 is a cross-sectional view showing a semiconductor device according to a fifth embodiment. The semiconductor devices of the first to fourth embodiments are IGBTs, but the semiconductor device of the present embodiment is an RC-IGBT. An n-type cathode layer 14 is formed on the lower surface side of a semiconductor substrate 1. The hole density can be reduced by turning on the gate electrode 7 of the active trench 5a or the control gate trench 5b before the recovery operation of the diode to inject electrons, thereby reducing the recovery loss. The other configurations and effects are the same as those of the first embodiment and the like.

[0057] Fig. 18 is a cross-sectional view showing a modification of the semiconductor device according to the embodiment 5. In Fig. 17, the n-type cathode layer 14 is formed in the second region 1b, but as shown in Fig. 18, the n-type cathode layer 14 may be formed in the second region 1b and the third region 1c.

[0058] The semiconductor substrate 1 is not limited to being made of silicon, and may be made of a wide band gap semiconductor having a band gap larger than that of silicon. The wide band gap semiconductor is, for example, silicon carbide, gallium nitride-based material, Ga2O3, or diamond. A semiconductor device made of such a wide band gap semiconductor has high voltage resistance and allowable current density, and can be miniaturized. By using this miniaturized semiconductor device, a semiconductor module incorporating this semiconductor device can also be miniaturized and highly integrated. In addition, since the semiconductor device has high heat resistance, the heat dissipation fins of the heat sink can be miniaturized, and the water-cooled part can be air-cooled, so the semiconductor module can be further miniaturized. In addition, since the power loss of the semiconductor device is low and highly efficient, the semiconductor module can be highly efficient.

[0059] Although the preferred embodiments have been described above in detail, the present disclosure is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims. Various aspects of the present disclosure are described below as appendices. (Appendix 1) a semiconductor substrate of a first conductivity type having a first region and a second region adjacent to each other; a second conductivity type base layer formed on an upper surface side of the semiconductor substrate; a first conductivity type source layer formed on an upper surface side of the base layer; a plurality of gate electrodes formed in a plurality of trenches penetrating the source layer and the base layer from an upper surface side of the semiconductor substrate, with a gate insulating film interposed therebetween; an emitter electrode formed on an upper surface of the semiconductor substrate; a collector layer of a second conductivity type formed on a lower surface side of the semiconductor substrate; a collector electrode formed on a lower surface of the semiconductor substrate; The trench in the first region includes a first trench and two or more second trenches sandwiching the first trench from both sides, the gate electrodes formed in the two or more second trenches are connected to each other and are not connected to the gate electrode formed in the first trench; the gate electrode formed in the trench in the second region is connected to the emitter electrode; 2. A semiconductor device comprising: a first region and a second region, the first region being sandwiched between the first region and the second region; a second region being sandwiched between the first region and the second region; (Appendix 2) A control unit is further provided for turning off the gate electrode of the control gate trench at an earlier timing than the gate electrode of the active trench at the time of turning off, the first trench is the active trench; 2. The semiconductor device according to claim 1, wherein the second trench is the control gate trench. (Appendix 3) 3. The semiconductor device according to claim 2, wherein the number of the control gate trenches in the first region is three or more times the number of the active trenches. (Appendix 4) A control unit is further provided which turns on the gate electrode of the control gate trench at a timing slower than that of the gate electrode of the active trench when the gate electrode is turned on. the first trench is the active trench; 2. The semiconductor device according to claim 1, wherein the second trench is the control gate trench. (Appendix 5) A control unit is further provided for turning off the gate electrode of the control gate trench at an earlier timing than the gate electrode of the active trench at the time of turning off, the first trench is the control gate trench; 2. The semiconductor device according to claim 1, wherein the second trench is the active trench. (Appendix 6) 6. The semiconductor device according to claim 5, wherein the number of the active trenches in the first region is three or more times the number of the control gate trenches. (Appendix 7) the semiconductor substrate has a third region; the second region is disposed between the first region and the third region, The semiconductor device according to any one of claims 2 to 4, wherein the control gate trench and two or more active trenches sandwiching the control gate trench from both sides are formed in the third region. (Appendix 8) the semiconductor substrate has a third region; the second region is disposed between the first region and the third region, The semiconductor device according to any one of claims 2 to 6, wherein a proportion of the active trenches formed in the third region is greater than a proportion of the active trenches formed in the first region. (Appendix 9) the semiconductor substrate has a third region; the second region is disposed between the first region and the third region, 7. The semiconductor device according to claim 2, wherein one or more of the control gate trenches are formed in the third region. (Appendix 10) 10. The semiconductor device according to any one of claims 1 to 9, wherein the number of the trenches included in the second region is equal to or greater than the number of the trenches included in the first region. (Appendix 11) 11. The semiconductor device according to any one of claims 1 to 10, further comprising a carrier accumulation layer of a first conductivity type formed below the base layer. (Appendix 12) 12. The semiconductor device according to claim 11, wherein the impurity concentration of the carrier accumulation layer in the first region is higher than the impurity concentration of the carrier accumulation layer in the second region. (Appendix 13) a first conductive type carrier accumulation layer formed below the base layer; 5. The semiconductor device according to claim 4, wherein the impurity concentration of the carrier accumulation layer in contact with the control gate trench is higher than the impurity concentration of the carrier accumulation layer in contact with the active trench. (Appendix 14) 14. The semiconductor device according to any one of claims 1 to 13, which is an RC-IGBT. (Appendix 15) 15. The semiconductor device according to any one of claims 1 to 14, wherein the semiconductor substrate is made of a wide band gap semiconductor. [Explanation of symbols]

[0060] 1 semiconductor substrate, 1a first region, 1b second region, 1c third region, 2 n-type carrier accumulation layer, 3 p-type base layer, 4 n + a p-type source layer, 5 trench, 5a active trench, 5b control gate trench, 6 gate insulating film, 7 gate electrode, 9 emitter electrode, 11 p-type collector layer, 12 collector electrode, 13 control unit

Claims

1. a semiconductor substrate of a first conductivity type having a first region and a second region adjacent to each other; a second conductivity type base layer formed on an upper surface side of the semiconductor substrate; a first conductivity type source layer formed on an upper surface side of the base layer; a plurality of gate electrodes formed in a plurality of trenches penetrating the source layer and the base layer from an upper surface side of the semiconductor substrate, with a gate insulating film interposed therebetween; an emitter electrode formed on an upper surface of the semiconductor substrate; a collector layer of a second conductivity type formed on a lower surface side of the semiconductor substrate; a collector electrode formed on a lower surface of the semiconductor substrate; The trench in the first region includes a first trench and two or more second trenches sandwiching the first trench from both sides, the gate electrodes formed in the two or more second trenches are connected to each other and are not connected to the gate electrode formed in the first trench; the gate electrode formed in the trench in the second region is connected to the emitter electrode; a first region and a second region, the first region being sandwiched between the first region and the second region, the second ...

2. A control unit is further provided for turning off the gate electrode of the control gate trench at an earlier timing than the gate electrode of the active trench at the time of turning off, the first trench is the active trench; 2. The semiconductor device according to claim 1, wherein the second trench is the control gate trench.

3. 3. The semiconductor device according to claim 2, wherein the number of the control gate trenches in the first region is three times or more the number of the active trenches.

4. A control unit is further provided which turns on the gate electrode of the control gate trench at a timing later than the gate electrode of the active trench when the gate electrode is turned on. the first trench is the active trench; 2. The semiconductor device according to claim 1, wherein the second trench is the control gate trench.

5. A control unit is further provided for turning off the gate electrode of the control gate trench at an earlier timing than the gate electrode of the active trench at the time of turning off, the first trench is the control gate trench; 2. The semiconductor device according to claim 1, wherein the second trench is the active trench.

6. 6. The semiconductor device according to claim 5, wherein the number of the active trenches in the first region is three times or more the number of the control gate trenches.

7. the semiconductor substrate has a third region; the second region is disposed between the first region and the third region, 5. The semiconductor device according to claim 2, wherein the control gate trench and two or more active trenches sandwiching the control gate trench from both sides are formed in the third region.

8. the semiconductor substrate has a third region; the second region is disposed between the first region and the third region, 7. The semiconductor device according to claim 2, wherein a ratio of the active trenches formed in the third region is greater than a ratio of the active trenches formed in the first region.

9. the semiconductor substrate has a third region; the second region is disposed between the first region and the third region, 7. The semiconductor device according to claim 2, wherein one or more of the control gate trenches are formed in the third region.

10. 7. The semiconductor device according to claim 1, wherein the number of said trenches included in said second region is equal to or greater than the number of said trenches included in said first region.

11. 7. The semiconductor device according to claim 1, further comprising a carrier accumulation layer of the first conductivity type formed below the base layer.

12. 12. The semiconductor device according to claim 11, wherein the impurity concentration of the carrier accumulation layer in the first region is higher than the impurity concentration of the carrier accumulation layer in the second region.

13. a carrier accumulation layer of a first conductivity type formed below the base layer; 5. The semiconductor device according to claim 4, wherein the impurity concentration of the carrier accumulation layer in contact with the control gate trench is higher than the impurity concentration of the carrier accumulation layer in contact with the active trench.

14. 7. The semiconductor device according to claim 1, wherein the semiconductor device is an RC-IGBT.

15. 7. The semiconductor device according to claim 1, wherein the semiconductor substrate is made of a wide band gap semiconductor.

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