Nitride semiconductor epitaxial wafer and manufacturing method for nitride semiconductor epitaxial wafer

Abstract

To provide a nitride semiconductor epitaxial wafer in which melt-back etching can be suppressed even in a structure in which a nitride semiconductor is grown on a silicon single-crystal layer and ohmic contact is secured easily in the silicon single-crystal layer at the manufacture of devices.SOLUTION: A nitride semiconductor epitaxial wafer 100 includes: a composite substrate 3 including a ceramic wafer 1 and a silicon single-crystal layer 2 bonded onto the ceramic wafer 1; and a nitride semiconductor layer 4 epitaxially grown on the silicon single-crystal layer 2 of the composite substrate 3. A thermal expansion coefficient of the ceramic wafer 1 is substantially equal to that of the nitride semiconductor layer 4. A thickness of the silicon single-crystal layer 2 is 100 nm or more and 200 nm or less.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a nitride semiconductor epitaxial wafer and a method for producing the nitride semiconductor epitaxial wafer. [Background technology]

[0002] Nitride semiconductors such as GaN and AlN can be used to fabricate high electron mobility transistors (HEMTs) using two-dimensional electron gas, and are therefore expected to be used as semiconductor devices for high-frequency applications.

[0003] The above-mentioned nitrides are also piezoelectric materials with excellent mechanical properties, and are expected to be used in high-frequency filters for communication, sensors, energy harvesters, etc. Furthermore, beyond communication applications, the use of nitride semiconductors to manufacture micro LEDs for displays is also being considered, and there is a demand for even larger diameters, higher quality, and lower costs.

[0004] However, it is difficult to produce wafers of these nitrides, and it is difficult to grow them using the general melt method, as with silicon single crystal substrates. For industrial applications, thin films grown by vapor phase growth on sapphire, SiC, or Si substrates are used, but there are concerns that the stress caused by the difference in physical properties between the substrate and the thin film may cause deformation, cracks, or peeling of the substrate, which limits the growth conditions and device structures.

[0005] In addition, the growth of gallium nitride on silicon single crystals is attractive for industrial applications because it allows the production of large-area single crystals at low cost. However, there is a problem in that a eutectic reaction between silicon and gallium (hereinafter also referred to as melt-back etching) occurs during the growth of gallium nitride and during device formation after growth, generating defects.

[0006] For example, Patent Document 1 discloses a technology for reducing stress caused by cooling after epitaxial growth by epitaxially growing GaN on a substrate with a thermal expansion coefficient matching that of GaN. However, since the single crystal layer on which the nitride semiconductor is grown in Patent Document 1 uses Si or SiGe, a eutectic reaction may occur during GaN growth, resulting in defects.

[0007] In response to this, Patent Document 2 describes that the eutectic reaction is prevented by thinning the transferred SOI layer.

[0008] In addition, in order to stabilize the characteristics of high electron mobility transistors, it is necessary to provide an electrode on the substrate side. The electrode is fabricated by making ohmic contact with the underlying silicon layer, but there is an issue that the contact resistance with the electrode increases when the electrode is thinned.

[0009] In response to this, Patent Document 3 describes a technique for reducing ohmic resistance by forming a silicon layer, which serves as a base for epitaxially growing GaN, on a substantially single crystal layer by epitaxial growth. [Prior art documents] [Patent documents]

[0010] [Patent Document 1] Special Publication No. 2020-505767 [Patent Document 2] JP 2007-246289 A [Patent Document 3] Special Publication No. 2019-523994 Summary of the Invention [Problem to be solved by the invention]

[0011] However, in Patent Document 2, when cracks occur from the outer periphery or non-transferred areas, the cracks reach the Si substrate and cause melt-back etching, and it is considered that melt-back etching cannot be completely suppressed.

[0012] Furthermore, in Patent Document 3, the addition of an epitaxial process has the disadvantage of increasing costs. Also, the silicon layer thickness of the combined substantially single crystal layer and epitaxial layer is 400 nm to 20,300 nm, and there is a concern that melt-back etching may increase.

[0013] The present invention has been made to solve the above problems, and has an object to provide a nitride semiconductor epitaxial wafer that can suppress melt-back etching even in a structure in which a nitride semiconductor is grown on a silicon single crystal layer, and that makes it easy to obtain ohmic contact in the silicon single crystal layer during device fabrication.

[0014] Another object of the present invention is to provide a method for manufacturing a nitride semiconductor epitaxial wafer that can suppress melt-back etching even when a nitride semiconductor is grown on a silicon single crystal layer, and that makes it easy to obtain ohmic contact with the silicon single crystal layer during device fabrication. [Means for solving the problem]

[0015] The present invention has been made to achieve the above-mentioned object, and provides a nitride semiconductor epitaxial wafer comprising a composite substrate comprising a ceramic wafer and a silicon single crystal layer bonded onto the ceramic wafer, and a nitride semiconductor layer epitaxially grown on the silicon single crystal layer of the composite substrate, wherein the thermal expansion coefficient of the ceramic wafer is substantially equal to that of the nitride semiconductor layer, and the silicon single crystal layer has a thickness of 100 nm or more and 200 nm or less.

[0016] In such a nitride semiconductor epitaxial wafer, the thickness of the silicon single crystal layer is 200 nm or less, so that melt-back etching is unlikely to occur, and the thickness of the silicon single crystal layer is 100 nm or more, so that ohmic contact can be easily obtained.

[0017] In this case, the ceramic wafer may comprise a heat-resistant support substrate having a core made of nitride ceramics and a sealing layer having a thickness of 0.05 μm or more and 1.5 μm or less that covers and seals the surface of the core, and a planarization layer having a thickness of 0.2 μm or more and 3.0 μm or less that is provided on the surface of the heat-resistant support substrate and serves as a base on which the silicon single crystal layer is provided.

[0018] As a result, the ceramic wafer has a core made of nitride ceramics, which is advantageous in suppressing deformation of the nitride semiconductor epitaxial wafer. Also, the provision of a sealing layer can prevent substances contained in the ceramic core from leaking to the outside. Furthermore, the provision of a planarizing layer on the heat-resistant support substrate can fill voids and irregularities in the heat-resistant support substrate, making it easier to bond the silicon single crystal layer.

[0019] In this case, the nitride ceramic may be composed mainly of polycrystalline AlN ceramic.

[0020] This is preferable from the viewpoint of the difference in thermal expansion coefficient and thermal conductivity.

[0021] At this time, the sealing layer is SiO x N y (wherein x=0 to 2, y=0 to 1.5, and x+y>0) can be used as the composition.

[0022] This is more preferable in terms of preventing the substances contained in the ceramic core from leaking to the outside.

[0023] In this case, the planarization layer may contain any one of silicon nitride, silicon oxynitride, and aluminum arsenide.

[0024] This is more advantageous in that the planarizing layer fills in voids and irregularities in the heat-resistant supporting substrate, facilitating bonding of the silicon single crystal layer.

[0025] The present invention has been made to achieve the above-mentioned object, and provides a method for producing a nitride semiconductor epitaxial wafer, comprising: a composite substrate formation step of bonding a silicon single crystal layer to a ceramic wafer to obtain a composite substrate; and a growth step of growing a nitride semiconductor layer on the silicon single crystal layer of the composite substrate by vapor phase growth, wherein the ceramic wafer has a thermal expansion coefficient substantially equal to that of the nitride semiconductor layer, and the method is characterized in that in the composite substrate formation step, the thickness of the silicon single crystal layer is controlled to be 100 nm or more and 200 nm or less.

[0026] According to this method for producing a nitride semiconductor epitaxial wafer, the thickness of the silicon single crystal layer is controlled to 200 nm or less, making it difficult for melt-back etching to occur, and the thickness of the silicon single crystal layer is controlled to 100 nm or more, making it easier to obtain ohmic contact. Effect of the Invention

[0027] As described above, according to the nitride semiconductor epitaxial wafer of the present invention, melt-back etching can be suppressed even in a structure in which a nitride semiconductor is grown on a silicon single crystal layer, and ohmic contact can be easily obtained in the silicon single crystal layer during device fabrication.

[0028] Specifically, the nitride semiconductor epitaxial wafer of the present invention can be used as a nitride semiconductor substrate, particularly as a nitride semiconductor epitaxial substrate suitable for GaN-based high mobility transistors (HEMTs) for micro LEDs, high frequency switches, power amplifiers, and power switching devices.

[0029] Furthermore, according to the method for manufacturing a nitride semiconductor epitaxial wafer, melt-back etching can be suppressed even when a nitride semiconductor is grown on a silicon single crystal layer, and a method for manufacturing a nitride semiconductor epitaxial wafer can be provided in which ohmic contact can be easily achieved in the silicon single crystal layer during device fabrication.

[0030] In particular, by forming a nitride semiconductor layer on a composite substrate produced by the method for producing a nitride semiconductor epitaxial wafer of the present invention, a thick gallium nitride layer can be grown and melt-back etching of silicon and gallium during epitaxial growth or due to heat treatment in the device process can be suppressed, thereby obtaining an epitaxial substrate that enables ohmic contact with the silicon single crystal layer.

[0031] Specifically, the company can manufacture nitride semiconductor epitaxial substrates suitable for GaN-based high mobility transistors (HEMTs) for use in micro LEDs, high frequency switches, power amplifiers, and power switching devices. [Brief description of the drawings]

[0032] [Figure 1] 1 shows a longitudinal sectional view of a nitride semiconductor epitaxial wafer according to an embodiment of the present invention. [Diagram 2] 2 shows a cross-sectional view of the nitride semiconductor layer of FIG. [Diagram 3] An example of a method for manufacturing a nitride semiconductor epitaxial wafer according to an embodiment of the present invention will be described. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0033] The present invention will be described in detail below, but the present invention is not limited thereto.

[0034] As described above, there has been a demand for a nitride semiconductor epitaxial wafer that can suppress melt-back etching even in a structure in which a nitride semiconductor is grown on a silicon single crystal layer, and that facilitates establishing ohmic contact with the silicon single crystal layer during device fabrication.

[0035] As a result of intensive research into the above-mentioned problems, the present inventors have found that a nitride semiconductor epitaxial wafer is provided with a composite substrate including a ceramic wafer and a silicon single crystal layer bonded onto the ceramic wafer, and a nitride semiconductor layer epitaxially grown on the silicon single crystal layer of the composite substrate, the thermal expansion coefficient of the ceramic wafer being substantially equal to the thermal expansion coefficient of the nitride semiconductor layer, and the thickness of the silicon single crystal layer is 100 nm or more and 200 nm or less. The inventors have found that a nitride semiconductor epitaxial wafer can suppress meltback etching even in a structure in which a nitride semiconductor is grown on a silicon single crystal layer, and that a nitride semiconductor epitaxial wafer in which ohmic contact is easily obtained in the silicon single crystal layer during device fabrication can be obtained, thereby completing the present invention.

[0036] As described above, there has been a demand for a method for manufacturing a nitride semiconductor epitaxial wafer that can suppress melt-back etching even when a nitride semiconductor is grown on a silicon single crystal layer and that can easily obtain ohmic contact with the silicon single crystal layer during device fabrication.

[0037] As a result of intensive research into the above-mentioned problems, the present inventors have found that a method for producing a nitride semiconductor epitaxial wafer includes a composite substrate formation step of bonding a silicon single crystal layer to a ceramic wafer to obtain a composite substrate, and a growth step of growing a nitride semiconductor layer by vapor phase growth on the silicon single crystal layer of the composite substrate, and the ceramic wafer has a thermal expansion coefficient substantially equal to that of the nitride semiconductor layer. In the composite substrate formation step, the thickness of the silicon single crystal layer is controlled to 100 nm or more and 200 nm or less. This method for producing a nitride semiconductor epitaxial wafer is characterized in that meltback etching can be suppressed even when a nitride semiconductor is grown on a silicon single crystal layer, and an ohmic contact can be easily made in the silicon single crystal layer during device fabrication. Thus, the present invention has been completed.

[0038] The following description will be given with reference to the drawings. First, a nitride semiconductor epitaxial wafer according to an embodiment of the present invention will be described with reference to FIGS.

[0039] 1 includes a ceramic wafer 1 and a composite substrate 3 including a silicon single crystal layer 2 bonded onto the ceramic wafer 1. The nitride semiconductor epitaxial wafer 100 also includes a nitride semiconductor layer 4 epitaxially grown on the silicon single crystal layer 2 of the composite substrate 3. The thermal expansion coefficient of the ceramic wafer 1 is substantially equal to that of the nitride semiconductor layer 4.

[0040] The ceramic wafer 1 is a substrate supporting the silicon single crystal layer 2 and the nitride semiconductor layer 4, and includes a heat-resistant support substrate 7 including a ceramic core 5 and a sealing layer 6 that covers and seals the surface of the ceramic core 5. The ceramic wafer 1 also includes a planarization layer 8 that is provided on the surface of the heat-resistant support substrate 7 and serves as a base on which the silicon single crystal layer 2 is provided.

[0041] The ceramic core 5 is a member that supports other members constituting the nitride semiconductor epitaxial wafer 100 as the core of the ceramic wafer 1, and is made of nitride ceramics. A specific material can be selected from the viewpoint of making the thermal expansion coefficient of the ceramic wafer 1 substantially equal to that of the nitride semiconductor layer 4, and for example, aluminum nitride (AlN), silicon nitride (Si3N4), gallium nitride (GaN), boron nitride (BN), or a mixture thereof can be used. From the viewpoint of the difference in thermal expansion coefficient and thermal conductivity, however, it is preferable to make the ceramic core 5 from a ceramic containing AlN as a main component, such as polycrystalline AlN ceramics. Note that the "main component" means the one having the largest content ratio by mass ratio.

[0042] The sealing layer 6 is a layer for preventing the substances contained in the ceramic core 5 from leaking out, and is formed on the entire surface of the ceramic core 5 so as to encase the ceramic core 5. The sealing layer 6 is made of SiO x N y It is preferable that the composition be made of a composition represented by the formula (where x=0 to 2, y=0 to 1.5, and x+y>0).

[0043] The thickness of the sealing layer 6 is not particularly limited, but a thickness of 0.05 μm or more and 1.5 μm or less is preferable because it is thick enough to cover and seal the surface of the ceramic core 5 .

[0044] The planarization layer 8 is a layer formed to fill voids and irregularities in the heat-resistant support substrate 7 and facilitate bonding of the silicon single crystal layer 2. The planarization layer 8 is laminated on the heat-resistant support substrate 7 to a thickness of 0.2 μm or more and 3.0 μm or less, preferably 0.5 μm or more and 3.0 μm or less. The planarization layer 8 preferably contains any one of silicon nitride, silicon oxynitride, and aluminum arsenide.

[0045] Although not shown, the ceramic wafer 1 may have a conductive layer containing polysilicon if necessary. The conductive layer contains polysilicon, is deposited by an LPCVD process or the like, and has a thickness of about 50 to 500 nm. This is a layer for imparting conductivity, and is doped with, for example, boron (B) or phosphorus (P). This conductive layer is provided if necessary, and may not be required, or may be formed on only one side. The position where the film is formed is not limited to the inside of the sealing layer 6 (the ceramic core 5 side), and may be provided on the outside.

[0046] The silicon single crystal layer 2 is a layer composed of a silicon single crystal, and serves as a base layer when forming the nitride semiconductor layer 4. By using the silicon single crystal layer 2 as a base, a ceramic wafer 1 having a large diameter and low cost for industrial application can be obtained, and therefore the nitride semiconductor layer 4 formed thereon can also have a large diameter.

[0047] The thickness of the silicon single crystal layer 2 is 100 nm or more and 200 nm or less. If the thickness of the silicon single crystal layer 2 exceeds 200 nm, a eutectic reaction (melt-back etching) between Si and Ga is likely to occur on the side surface of the silicon single crystal layer 2, which has a different plane orientation from the main surface, resulting in an increase in defects and a decrease in wafer yield.

[0048] On the other hand, if the thickness of the silicon single crystal layer 2 is less than 100 nm, the layer thickness becomes too thin, resulting in high contact resistance and making it difficult to form an ohmic electrode on the back surface side.

[0049] The nitride semiconductor layer 4 is a layer containing a nitride semiconductor, and is epitaxially grown on the silicon single crystal layer 2 of the composite substrate 3. A cross section of the nitride semiconductor layer 4 is shown in Fig. 2. The nitride semiconductor layer 4 in Fig. 2 includes an intermediate layer 10 and a device layer 13. Note that the structure of the nitride semiconductor layer 4 described below is merely an example, and is not limited to this structure.

[0050] The intermediate layer 10 acts as a buffer layer inserted to improve the crystallinity and control stress of the device layer 13. The intermediate layer 10 is preferably a nitride since it can be fabricated in the same facility as the device layer 13.

[0051] Device layer 13 is formed on intermediate layer 10 and is a thin layer of nitride in which devices are formed.

[0052] The nitride for the device layer 13 may be, for example, GaN, AlN, InN, AlGaN, InGaN, AlInN, AlScN, etc. The nitride thin film has a thickness of 1 to 10 μm and can be designed according to the device. The device layer 13 can have a multi-layer structure. For example, in a high-electron-transistor-mobility transistor (HEMT) structure, the device layer 13 is composed of a gallium nitride layer 11 and an electron supply layer 12 made of AlGaN formed thereon, as shown in FIG.

[0053] In order to improve device characteristics, the device layer 13 is preferably made of a crystal having few crystal defects and few impurities such as carbon and oxygen.

[0054] The above is a description of the nitride semiconductor epitaxial wafer 100 according to an embodiment of the present invention.

[0055] Next, a method for manufacturing the nitride semiconductor epitaxial wafer 100 according to the embodiment of the present invention will be described with reference to FIGS.

[0056] First, a ceramic wafer 1 is prepared whose thermal expansion coefficient is substantially equal to that of the nitride semiconductor layer 4 (S0 in FIG. 3). Specifically, as shown in FIG. 1, a sealing layer 6 is formed on the surface of a ceramic core 5 to cover the surface of the ceramic core 5 to form a heat-resistant support substrate 7, and a planarizing layer 8 is formed on the surface of the heat-resistant support substrate 7 to manufacture the ceramic wafer 1.

[0057] The sealing layer 6 can be formed on the surface of the ceramic core 5 by a film formation method such as an MOCVD method, an atmospheric pressure CVD method, an LPCVD (low pressure CVD) method, a sputtering method, etc. In particular, the LPCVD method is preferable because it can form a dense film and has excellent film coverage.

[0058] The planarizing layer 8 can be formed on the surface of the heat-resistant supporting substrate 7 by plasma CVD, LPCVD, or low-pressure MOCVD, but is not limited to these.

[0059] Next, a silicon single crystal layer 2 is bonded to the ceramic wafer 1 to obtain a composite substrate 3 (S1 in FIG. 3, composite substrate formation step). The silicon single crystal layer 2 can be bonded to the ceramic wafer 1 by peeling off a surface layer from a silicon single crystal substrate and transferring it onto the surface of the planarizing layer 8 of the ceramic wafer 1 .

[0060] The peeling and transferring method is not limited to the following method, but can be fabricated by the steps of preparing a silicon single crystal substrate, implanting ions into the silicon single crystal substrate to form a brittle layer, and bonding the substrate to the planarized layer 8 of the ceramic wafer 1 and separating the silicon single crystal layer 2 at the brittle layer. The type of ions to be implanted is not limited to the following elements, but for example, H2, Ar, He, etc. can be used.

[0061] In S1, the thickness of the silicon single crystal layer 2 is controlled to 100 nm or more and 200 nm or less by, for example, optimizing ion implantation conditions, polishing, or etching. If the thickness of the silicon single crystal layer 2 exceeds 200 nm, melt-back etching is likely to occur on the side surface of the silicon single crystal layer 2, and if it is less than 100 nm, it becomes difficult to obtain ohmic contact.

[0062] Next, the nitride semiconductor layer 4 is epitaxially grown on the silicon single crystal layer 2 of the composite substrate 3 by vapor phase growth (S2 in FIG. 3, growth step). 2, for example, an intermediate layer 10 is formed by MOVPE or the like, and a device layer 13 made of a thin film of a nitride is formed on the intermediate layer 10 by vapor phase growth such as MOVPE or sputtering. The device layer 13 is preferably formed at 900°C to 1350°C by MOVPE.

[0063] A method for growing the nitride semiconductor layer 4 suitable for a GaN HEMT in the growth process, specifically, steps S2-1 to S2-5 in FIG. 3 will be exemplified below.

[0064] [S2-1] Introduction to the reactor The composite substrate 3 is introduced into the reaction furnace of the MOVPE device. Before the composite substrate 3 is introduced into the reaction furnace, it is cleaned with a chemical such as hydrofluoric acid. After the composite substrate 3 is introduced into the reaction furnace, the inside of the furnace is filled with a high-purity inert gas such as nitrogen to replace the atmosphere inside the furnace.

[0065] [S2-2] Step of cleaning the surface of the composite substrate 3 in a furnace The composite substrate 3 is heated in a reaction furnace to clean the surface of the substrate. The temperature at which cleaning is performed can be determined as the temperature of the substrate surface between 1000° C. and 1200° C., but a particularly clean surface can be obtained by performing cleaning at 1050° C.

[0066] Cleaning is performed after the pressure inside the furnace is reduced, and the pressure inside the furnace can be set between 200 mbar (2 Pa) and 30 mbar (0.3 Pa). In this embodiment, cleaning can be performed with the pressure inside the furnace set to 50 mbar (0.5 Pa), for example. Cleaning is performed for 10 minutes, for example, while hydrogen or nitrogen is supplied into the furnace.

[0067] [S2-3] Step of growing the intermediate layer In this step, AlN or Al is deposited on the composite substrate 3 by introducing gases that are the raw materials Al, Ga, and N at a specified furnace pressure and substrate temperature. x Ga 1-xEpitaxially grow N(0≦x<1).

[0068] In this step, for example, growth is carried out at a furnace pressure of 50 mbar and a substrate temperature of 1120°C. As the Al source, trimethylaluminum (TMAl) can be used, as the Ga source, trimethylgallium (TMGa) can be used, and as the N source, ammonia (NH3) can be used. Also, in order to obtain a mixed crystal with a desired Al composition, considering the material efficiency of the source gas, the flow rates of the raw materials TMAl and TMGa are set so that the Al / Ga ratio incorporated into the thin film becomes the set ratio.

[0069] In this step, the growth of AlN can be carried out with a flow rate of TMAl of 0.24 L / min (240 sccm) and a flow rate of NH3 of 2 L / min (2000 sccm) under standard conditions. As the carrier gas for TMAl, TMGa, and NH3, for example, hydrogen can be used. These conditions are just examples and are not particularly limited.

[0070] [S2-4] Step of growing gallium nitride layer 11 In this step, at a specified furnace pressure and substrate temperature, by introducing the raw materials Ga and the gas serving as the N source, GaN or Al x Ga 1-x Epitaxially grow GaN(0<x≦1).

[0071] In this step, for example, growth can be carried out at a furnace pressure of 200 mbar and a substrate temperature of 1120°C. As the Ga source, trimethylgallium (TMGa) can be used, and as the N source, ammonia (NH3) can be used.

[0072] Also, in order to obtain a mixed crystal with a desired Al composition, considering the material efficiency of the source gas, the flow rates of the raw materials TMAl and TMGa are set so that the Al / Ga ratio incorporated into the thin film becomes the set ratio. As the carrier gas for TMAl, TMGa, and NH3, for example, hydrogen can be used. These conditions are just examples and are not particularly limited.

[0073] [S2-5] Step of growing the electron supply layer 12 In this step, at a specified furnace internal pressure and substrate temperature, by introducing gases that are sources of Al, Ga, and N, which are raw materials, for example, Al x Ga 1-x N (0 < x ≤ 1) is epitaxially grown on the gallium nitride layer 11 as the electron supply layer 12.

[0074] In this step, for example, growth can be performed at a furnace internal pressure of 150 mbar and a substrate temperature of 1120°C. Trimethylaluminum (TMAl) can be used as the Al source, trimethylgallium (TMGa) can be used as the Ga source, and ammonia (NH3) can be used as the N source.

[0075] Also, in order to obtain a mixed crystal with a desired Al composition, considering the material efficiency of the raw material gases, the flow rates of the raw materials TMAl and TMGa are set so that the Al / Ga ratio incorporated into the thin film becomes the set ratio. For example, hydrogen can be used as the carrier gas for TMAl, TMGa, and NH3. These conditions are just an example and are not particularly limited. The above is the description of the method for growing the nitride semiconductor layer 4 suitable for GaN HEMT.

[0076] By using the method for manufacturing the nitride semiconductor epitaxial wafer 100 of the present invention, even when a thick gallium nitride layer 11 is grown, the eutectic reaction (melt back etching) between silicon and gallium due to heat treatment in the growth process and the device process can be suppressed, and a nitride semiconductor epitaxial wafer 100 in which ohmic contact in the single crystal silicon layer 2 is easy to obtain can be obtained.

[0077] The above is the description of the method for manufacturing the nitride semiconductor epitaxial wafer 100 according to the embodiment of the present invention.

Example

[0078] Hereinafter, the present invention will be specifically described with reference to examples, but this does not limit the present invention.

[0079] Example 1 AlN ceramics (resistivity 10 14 A ceramic core 5 made of a silicon nitride having a thickness of 300 nm was then prepared. The ceramic core 5 was then covered and sealed with a sealing layer 6 made of silicon nitride having a thickness of 300 nm, and a planarizing layer 8 made of silicon oxide was grown to a thickness of 2 μm on the surface of the sealing layer 6 to produce a ceramic wafer 1 having a diameter of 150 mm.

[0080] Thereafter, a silicon single crystal layer 2 having a thickness of 200 nm was bonded to the ceramic wafer 1 to prepare a composite substrate 3. The silicon single crystal layer 2 was made of low-resistance Si <111> A substrate was prepared, a brittle layer was formed by ion implantation, and the surface layer was transferred to the ceramic wafer 1 to form the brittle layer.

[0081] An intermediate layer 10 made of AlN and AlGaN was formed by MOCVD on the composite substrate 3 thus fabricated. The AlN layer was grown to 250 nm, and three 150 nm AlGaN layers were formed so that the Al composition of the AlGaN layer decreased from the substrate side to the surface side.

[0082] After the intermediate layer 10 was formed, the gallium nitride layer 11 which would become the device layer 13 was grown to a thickness of 5750 nm, and the electron supply layer 12 made of AlGaN was grown to a thickness of 25 nm, thereby producing the nitride semiconductor epitaxial wafer 100. The thickness of the gallium nitride layer 11 was 5750 nm, which is a thickness that provides sufficient dislocation density and breakdown voltage for fabricating a GaN HEMT device. Through the above steps, 50 nitride semiconductor epitaxial wafers 100 were manufactured.

[0083] Example 2 A composite substrate 3 was produced using the same materials and manufacturing conditions as in Example 1, except that a 100 nm-thick silicon single crystal layer was bonded to the ceramic wafer 1. 50 nitride semiconductor epitaxial wafers 100 were produced in which an intermediate layer 10 and a device layer 13 were formed using the same materials and manufacturing conditions as in Example 1.

[0084] Comparative Example 1 A composite substrate 3 was produced using the same materials and manufacturing conditions as in Example 1, except that a silicon single crystal layer having a thickness of 210 nm was bonded to the ceramic wafer 1. 50 nitride semiconductor epitaxial wafers were produced, each having an intermediate layer 10 and a device layer 13 formed thereon using the same materials and manufacturing conditions as in Example 1.

[0085] Comparative Example 2 A composite substrate 3 was produced using the same materials and manufacturing conditions as in Example 1, except that a 90 nm-thick silicon single crystal layer was bonded to the ceramic wafer 1. 50 nitride semiconductor epitaxial wafers were produced, each having an intermediate layer 10 and a device layer 13 formed thereon using the same materials and manufacturing conditions as in Example 1.

[0086] The appearances of the nitride semiconductor epitaxial wafers produced in the above Examples 1 and 2 and Comparative Examples 1 and 2 were observed visually and with a stereomicroscope, and the ratio of wafers in which melt-back etching occurred among 50 wafers in each Example and Comparative Example was calculated as the melt-back etching occurrence rate.

[0087] In addition, to stabilize the potential on the back surface during GaN HEMT formation, it is preferable to form an ohmic electrode on the bottom of the device. The method of forming the electrode on the bottom is to etch the epitaxial layer from the surface layer only to the electrode part and contact it with the lower silicon layer, so only the back electrode is formed and the resistance of the electrode was measured with a commercially available curve tracer.

[0088] Table 1 shows the results of the appearance inspection (melt-back etching occurrence rate) of the produced nitride semiconductor epitaxial wafers and the measurement results of the resistance value of the back surface electrode.

[0089] [Table 1]

[0090] Examples 1 and 2 are products of the present invention manufactured according to the manufacturing method of the present invention, and no meltback etching was observed in the outer periphery. On the other hand, in Comparative Example 1, meltback etching occurred in the sidewall of the silicon single crystal layer in the outer periphery and in the untransferred portion of the silicon single crystal layer, and the meltback etching occurrence rate was high, resulting in a low yield of nitride semiconductor epitaxial wafers.

[0091] This is because the thickness of the silicon single crystal layer in Comparative Example 1 was thicker than in Examples 1 and 2, and the plane orientation was Si <111> This is thought to be because the area of ​​the surface that differs from the surface becomes larger, increasing the possibility of melt-back etching occurring.

[0092] In addition, in the nitride semiconductor epitaxial wafers 100 of Examples 1 and 2, the back surface electrode resistance value was low, so ohmic contact was established and the contact resistance between the electrode and the silicon single crystal layer 2 was low, but in the nitride semiconductor epitaxial wafer of Comparative Example 2, the back surface electrode resistance value was so high that it was impossible to measure, so non-ohmic contact was established, so the contact resistance between the electrode and the silicon single crystal layer was high and the back surface electrode did not function as an electrode.

[0093] This is believed to be because the thickness of the silicon single crystal layer 2 in Comparative Example 2 was thinner than in Examples 1 and 2, and the thinner silicon single crystal layer 2 resulted in a higher resistivity, and further because it was difficult to target and etch the silicon single crystal layer 2 during device fabrication, resulting in a higher contact resistance.

[0094] As described above, according to the examples of the present invention, it is possible to suppress melt-back etching even in a structure in which a nitride semiconductor is grown on a silicon single crystal layer, and it is possible to manufacture a nitride semiconductor epitaxial wafer in which ohmic contact can be easily achieved in the silicon single crystal layer during device fabrication.

[0095] The present specification includes the following aspects. [1]: A nitride semiconductor epitaxial wafer comprising a composite substrate including a ceramic wafer and a silicon single crystal layer bonded onto the ceramic wafer, and a nitride semiconductor layer epitaxially grown on the silicon single crystal layer of the composite substrate, wherein the thermal expansion coefficient of the ceramic wafer is substantially equal to the thermal expansion coefficient of the nitride semiconductor layer, A nitride semiconductor epitaxial wafer, wherein the silicon single crystal layer has a thickness of 100 nm or more and 200 nm or less. [2]: The ceramic wafer, a heat-resistant support substrate including a core made of a nitride ceramic and a sealing layer having a thickness of 0.05 μm or more and 1.5 μm or less that covers and seals a surface of the core; a planarization layer having a thickness of 0.2 μm or more and 3.0 μm or less provided on the surface of the heat-resistant support substrate, the planarization layer serving as a base on which the silicon single crystal layer is provided; The nitride semiconductor epitaxial wafer according to the above [1], [3]: The nitride semiconductor epitaxial wafer according to [2] above, characterized in that the nitride ceramics is mainly composed of polycrystalline AlN ceramics. [4]: The sealing layer is made of SiO x N y The nitride semiconductor epitaxial wafer according to the above [2] or [3], characterized in that the composition is represented by a composition formula: (wherein x=0 to 2, y=0 to 1.5, and x+y>0). [5]: The nitride semiconductor epitaxial wafer according to any one of [2] to [4] above, wherein the planarization layer contains any one of silicon nitride, silicon oxynitride, and aluminum arsenide. [6]: A method for producing a nitride semiconductor epitaxial wafer, comprising: a composite substrate forming step of bonding a silicon single crystal layer to a ceramic wafer to obtain a composite substrate; and a growth step of growing a nitride semiconductor layer by vapor phase epitaxy on the silicon single crystal layer of the composite substrate, the ceramic wafer having a thermal expansion coefficient substantially equal to that of the nitride semiconductor layer, A method for producing a nitride semiconductor epitaxial wafer, wherein in the composite substrate formation step, the thickness of the silicon single crystal layer is controlled to 100 nm or more and 200 nm or less.

[0096] The present invention is not limited to the above-described embodiment. The above-described embodiment is merely an example, and anything that has substantially the same configuration as the technical idea described in the claims of the present invention and exhibits similar effects is included in the technical scope of the present invention. [Explanation of symbols]

[0097] 1...ceramic wafer, 2...silicon single crystal layer, 3...composite substrate, 4...nitride semiconductor layer, 5...ceramic core, 6...sealing layer, 7...heat-resistant support substrate, 8...planarization layer, 10...intermediate layer, 11...gallium nitride layer, 12...electron supply layer, 13...device layer, 100...nitride semiconductor epitaxial wafer.

Claims

1. A nitride semiconductor epitaxial wafer comprising: a composite substrate comprising a ceramic wafer and a silicon single crystal layer bonded onto the ceramic wafer; and a nitride semiconductor layer epitaxially grown on the silicon single crystal layer of the composite substrate, the ceramic wafer having a thermal expansion coefficient substantially equal to a thermal expansion coefficient of the nitride semiconductor layer, A nitride semiconductor epitaxial wafer, wherein the silicon single crystal layer has a thickness of 100 nm or more and 200 nm or less.

2. The ceramic wafer comprises: a heat-resistant support substrate including a core made of a nitride ceramic and a sealing layer having a thickness of 0.05 μm or more and 1.5 μm or less that covers and seals a surface of the core; a planarization layer having a thickness of 0.2 μm or more and 3.0 μm or less provided on the surface of the heat-resistant support substrate, the planarization layer serving as a base on which the silicon single crystal layer is provided; 2. The nitride semiconductor epitaxial wafer according to claim 1, comprising:

3. 3. The nitride semiconductor epitaxial wafer according to claim 2, wherein the nitride ceramics is mainly composed of polycrystalline AlN ceramics.

4. The sealing layer is made of SiO ｘ N ｙ 4. The nitride semiconductor epitaxial wafer according to claim 2, characterized in that the composition is represented by the composition formula: (wherein x=0 to 2, y=0 to 1.5, and x+y>0).

5. 4. The nitride semiconductor epitaxial wafer according to claim 2, wherein the planarization layer contains any one of silicon nitride, silicon oxynitride, and aluminum arsenide.

6. A method for producing a nitride semiconductor epitaxial wafer, comprising: a composite substrate forming step of bonding a silicon single crystal layer to a ceramic wafer to obtain a composite substrate; and a growth step of growing a nitride semiconductor layer by vapor phase growth on the silicon single crystal layer of the composite substrate, the ceramic wafer having a thermal expansion coefficient substantially equal to that of the nitride semiconductor layer, A method for producing a nitride semiconductor epitaxial wafer, characterized in that in the composite substrate formation step, the thickness of the silicon single crystal layer is controlled to be 100 nm or more and 200 nm or less.

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