Semiconductor device

Abstract

To improve dielectric breakdown voltage of a semiconductor device.SOLUTION: A semiconductor device 10 includes: a first chip 50 including a first circuit 20; a second chip 60, including a second circuit 30, which is disposed away from the first chip 50 in an X-direction; and a transformer chip 70, including a transformer 40, which is disposed on the first chip 50. The first circuit 20 and the second circuit 30 transmit signals to each other via the transformer 40. The transformer chip 70 includes: a third element insulation layer 72; and an outer coil 100 and an inner coil 110 which are disposed, as the transformer 40, inside the third element insulation layer 72. In plan view, the inner coil 110 is disposed inside the outer coil 100 in such a manner that it does not overlap the outer coil 100.SELECTED DRAWING: Figure 11

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a transformer chip including a semiconductor substrate, an insulating layer laminated structure formed on the substrate, and an upper coil and a lower coil formed in the insulating layer laminated structure. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2018-78169 A

[0004] [overview] By the way, there are cases where it is required to improve the dielectric strength voltage of a transformer chip.

[0005] A semiconductor device according to one embodiment of the present disclosure includes a first chip including a first circuit, a second chip including a second circuit arranged at a distance from the first chip in a first direction, and a transformer chip arranged on the first chip and including a transformer, wherein the first circuit and the second circuit are configured to transmit signals or power via the transformer, and the transformer chip includes a third element insulating layer and an outer coil and an inner coil arranged in the third element insulating layer as the transformer, and when viewed from the thickness direction of the third element insulating layer, the inner coil is arranged inside the outer coil so as not to overlap the outer coil. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic circuit diagram of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a schematic plan view of the semiconductor device of FIG. [Diagram 3]FIG. 3 is a schematic cross-sectional view of the semiconductor device taken along line F3-F3 in FIG. [Figure 4] FIG. 4 is a schematic plan view of the first chip in the semiconductor device of FIG. [Diagram 5] FIG. 5 is a schematic cross-sectional view of the first chip taken along line F5-F5 in FIG. [Figure 6] FIG. 6 is a schematic plan view of the second chip in the semiconductor device of FIG. [Figure 7] FIG. 7 is a schematic cross-sectional view of the second chip taken along line F7-F7 in FIG. [Figure 8] FIG. 8 is a schematic plan view of the transformer chip in the semiconductor device of FIG. [Figure 9] FIG. 9 is a schematic cross-sectional view of the transformer chip taken along line F9-F9 in FIG. [Figure 10] FIG. 10 is a schematic cross-sectional view of the transformer chip taken along line F10-F10 in FIG. [Figure 11] FIG. 11 is an enlarged schematic cross-sectional view of the first chip, the second chip, the transformer chip, and their periphery in the semiconductor device of FIG. [Figure 12] FIG. 12 is a schematic cross-sectional view of a transformer chip in the semiconductor device of the second embodiment. [Figure 13] FIG. 13 is a schematic circuit diagram of a semiconductor device according to the third embodiment. [Figure 14] FIG. 14 is a schematic plan view of the semiconductor device of FIG. [Figure 15] FIG. 15 is a schematic plan view of the transformer chip in the semiconductor device of FIG. [Figure 16] FIG. 16 is a schematic cross-sectional view of the transformer chip and the first chip taken along line F16-F16 in FIG. [Figure 17] FIG. 17 is a schematic cross-sectional view of the transformer chip and the first chip taken along line F17-F17 in FIG. [Figure 18] FIG. 18 is a schematic cross-sectional view of a transformer chip in a first modification of the semiconductor device of the first embodiment. [Figure 19] FIG. 19 is a schematic cross-sectional view of a transformer chip in a second modification of the semiconductor device of the first embodiment. [Figure 20] FIG. 20 is an exploded perspective view of a part of a transformer chip in a second modification of the semiconductor device of the first embodiment. [Figure 21] FIG. 21 is a schematic cross-sectional view of a transformer chip in a third modification of the semiconductor device of the first embodiment. [Figure 22] FIG. 22 is a schematic cross-sectional view of a transformer chip in a fourth modification of the semiconductor device of the first embodiment. [Figure 23] FIG. 23 is a schematic cross-sectional view of a part of a transformer chip in a modification of the semiconductor device of the second embodiment. [Figure 24] FIG. 24 is a schematic cross-sectional view of a transformer chip in a first modification of the semiconductor device of the third embodiment. [Diagram 25] FIG. 25 is a schematic cross-sectional view of a transformer chip in a second modification of the semiconductor device of the third embodiment. [Figure 26] FIG. 26 is an exploded perspective view of a part of a transformer chip in a second modification of the semiconductor device of the third embodiment. [Figure 27] FIG. 27 is a schematic cross-sectional view of a transformer chip in a third modification of the semiconductor device of the third embodiment. [Figure 28] FIG. 28 is a schematic cross-sectional view of a transformer chip in a fourth modification of the semiconductor device of the third embodiment. [Figure 29] FIG. 29 is a schematic plan view of a transformer chip in a fifth modification of the semiconductor device of the third embodiment. [Diagram 30] FIG. 30 is a schematic plan view of a transformer chip in a fifth modification of the semiconductor device of the third embodiment. [Diagram 31] FIG. 31 is a schematic cross-sectional view of a part of a transformer chip in a modification of the semiconductor device of the third embodiment. [Diagram 32] FIG. 32 is a schematic cross-sectional view of a part of a transformer chip in a modification of the semiconductor device of the third embodiment. [Diagram 33] FIG. 33 is a schematic cross-sectional view of a part of a transformer chip in a modification of the semiconductor device of the third embodiment. [Diagram 34] FIG. 34 is a schematic cross-sectional view of a part of a transformer chip in a modification of the semiconductor device of the third embodiment. [Diagram 35] FIG. 35 is a schematic cross-sectional view of a first chip, a transformer chip, and their periphery in a semiconductor device of a modified example. [Diagram 36] FIG. 36 is a schematic cross-sectional view of a first chip, a second chip, a transformer chip, and their periphery in a semiconductor device of a modified example. [Figure 37] FIG. 37 is a schematic plan view of a semiconductor device according to a modified example. [Figure 38] FIG. 38 is a schematic plan view of a semiconductor device according to a modified example. [Figure 39] FIG. 39 is a schematic circuit diagram of a semiconductor device according to a modified example.

[0007] [Detailed Description] Hereinafter, some embodiments of the semiconductor device of the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of description, components shown in the drawings are not necessarily drawn to scale. Also, hatching lines may be omitted in cross-sectional views to facilitate understanding. The accompanying drawings are merely illustrative of embodiments of the present disclosure and should not be considered as limiting the present disclosure. Terms such as "first", "second", and "third" in the present disclosure are used merely to distinguish objects and are not used to rank the objects.

[0008] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0009] The term "at least one" as used herein means "one or more" of the desired options. As an example, the term "at least one" as used herein means "only one option" or "both of two options" if the number of options is two. As another example, the term "at least one" as used herein means "only one option" or "any combination of two or more options" if the number of options is three or more.

[0010] As used in this specification, "the length (dimension) of A is equal to the length (dimension) of B" or "the length (dimension) of A and the length (dimension) of B are equal to each other" also includes a relationship in which the difference between the length (dimension) of A and the length (dimension) of B is within 10% of the length (dimension) of A, for example.

[0011] First Embodiment [Schematic configuration of semiconductor device] A schematic configuration of a semiconductor device 10 according to a first embodiment will be described with reference to Figs. 1 to 3. Fig. 1 diagrammatically illustrates the circuit configuration of the semiconductor device 10 according to the first embodiment. Fig. 2 diagrammatically illustrates an example of the internal configuration (planar structure) of the semiconductor device 10. In Fig. 2, a sealing resin 200, which will be described later, is indicated by a two-dot chain line in order to illustrate the internal configuration of the semiconductor device 10. Fig. 3 diagrammatically illustrates a cross-sectional structure of the semiconductor device 10 of Fig. 2 taken along line F3-F3.

[0012] In addition, since the circuit configuration of the semiconductor device 10 is shown in a simplified manner in Fig. 1, the number of external terminals of the semiconductor device 10 in Fig. 2 is greater than the number of external terminals of the semiconductor device 10 in Fig. 1. Here, the number of external terminals of the semiconductor device 10 refers to the number of external electrodes capable of connecting the semiconductor device 10 to electronic components external to the semiconductor device 10.

[0013] (Circuit configuration of semiconductor device) 1, the semiconductor device 10 includes a first circuit 20, a second circuit 30, and a transformer 40. The transformer 40 is configured to electrically insulate the first circuit 20 and the second circuit 30 from each other.

[0014] The first circuit 20 is configured to operate by a first voltage V1. In one example, the first circuit 20 includes a transmitting circuit or a receiving circuit. In the first embodiment, the first circuit 20 includes a transmitting circuit 21. The transmitting circuit 21 includes at least one transistor. The second circuit 30 is configured to operate by a second voltage V2. In one example, the second circuit 30 includes a transmitting circuit or a receiving circuit. In the first embodiment, the second circuit 30 includes a receiving circuit 31. The receiving circuit 31 includes at least one transistor. The first voltage V1 and the second voltage V2 may be the same as each other or may be different. In one example, the second voltage V2 is equal to the first voltage V1. The semiconductor device 10 may be referred to as a digital isolator. Therefore, the semiconductor device 10 can also be referred to as a signal transmission device that transmits a signal from the first circuit 20 to the second circuit 30.

[0015] The transformer 40 includes a first coil 41 and a second coil 42. The first coil 41 is electrically connected to the transmission circuit 21 of the first circuit 20. The second coil 42 is electrically connected to the reception circuit 31 of the second circuit 30.

[0016] The transmitting circuit 21 of the first circuit 20 receives the input signal and pulse-drives the transformer 40. The pulse signal excited in the first coil 41 of the transformer 40 is transmitted through the second coil 42 and input to the receiving circuit 31 of the second circuit 30. The receiving circuit 31 outputs an output signal based on the input pulse signal.

[0017] (Internal structure of semiconductor device) 2, the semiconductor device 10 includes a first chip 50, a second chip 60, a transformer chip 70, a first lead frame 80, a second lead frame 90, and a sealing resin 200. The sealing resin 200 is configured to seal the first chip 50, the second chip 60, and the transformer chip 70, and to partially seal the first lead frame 80 and the second lead frame 90. In FIG. 2, the sealing resin 200 is indicated by a two-dot chain line for the convenience of explaining the internal configuration of the semiconductor device 10.

[0018] Thus, in semiconductor device 10, first chip 50, second chip 60, and transformer chip 70 are packaged as a plurality of semiconductor chips by sealing resin 200.

[0019] The package format of the semiconductor device 10 is an SO (Small Outline) type, which is an SOP (Small Outline Package) in the first embodiment. The package format of the semiconductor device 10 can be changed arbitrarily. The package format is not limited to SOP, and may be QFN (Quad For Non Lead Package), DFP (Dual Flat Package), DIP (Dual Inline Package), QFP (Quad Flat Package), SIP (Single Inline Package), SOJ (Small Outline J-leaded Package), or various package structures similar to these.

[0020] The sealing resin 200 is made of a resin material having electrical insulation properties. The resin material includes, for example, black epoxy resin. The sealing resin 200 is formed in a rectangular plate shape with the Z direction as the thickness direction. The sealing resin 200 has four sealing side surfaces 201 to 204. More specifically, the sealing resin 200 has sealing side surfaces 201 and 202 as both end surfaces in the X direction and sealing side surfaces 203 and 204 as both end surfaces in the Y direction. The X direction and the Y direction are directions perpendicular to the Z direction. The X direction and the Y direction are perpendicular to each other when viewed from the Z direction. The sealing resin 200 is rectangular in shape with the X direction as the long side direction and the Y direction as the short side direction when viewed from the Z direction. Here, the X direction corresponds to the "first direction." In the following description, "plan view" means that the semiconductor device 10 or a component of the semiconductor device 10 is viewed from the Z direction.

[0021] Each of the first lead frame 80 and the second lead frame 90 is a conductor and is formed of a material containing, for example, Cu (copper), Fe (iron), Al (aluminum), etc. Each of the lead frames 80, 90 is provided straddling the inside and outside of the sealing resin 200. The first lead frame 80 and the second lead frame 90 are arranged at a distance from each other in the X direction.

[0022] The first lead frame 80 has a first die pad 81 disposed within the sealing resin 200, and a plurality of first leads 82 disposed across the inside and outside of the sealing resin 200. Each of the first leads 82 constitutes an external terminal that electrically connects the semiconductor device 10 to an external electronic device.

[0023] The first chip 50 is mounted on the first die pad 81. In a plan view, the first die pad 81 is disposed such that the center in the Y direction is closer to the sealing side surface 201 than the center in the Y direction of the sealing resin 200. In the first embodiment, the first die pad 81 is not exposed from the sealing resin 200. In one example, the shape of the first die pad 81 in a plan view is a rectangle whose long side direction is the X direction and whose short side direction is the Y direction.

[0024] The multiple first leads 82 are arranged spaced apart from one another in the Y direction. Of the multiple first leads 82, the first leads 82 arranged at the end closer to the sealing side surface 203 in the Y direction are integrated with the first die pad 81. The remaining first leads 82 are arranged spaced apart from the first die pad 81 in the X direction. A portion of each first lead 82 protrudes from the sealing side surface 201 outward from the sealing resin 200.

[0025] The second lead frame 90 has a second die pad 91 disposed within the sealing resin 200, and a plurality of second leads 92 disposed across the inside and outside of the sealing resin 200. Each of the second leads 92 constitutes an external terminal that electrically connects the semiconductor device 10 to an external electronic device.

[0026] The second die pad 91 is mounted with the second chip 60. It can be said that the second die pad 91 supports the second chip 60. In plan view, the second die pad 91 is disposed closer to the sealing side surface 202 than the first die pad 81 in the X direction. That is, the first die pad 81 and the second die pad 91 are arranged at a distance from each other in the X direction. Therefore, the X direction can also be said to be the arrangement direction of both die pads 81, 91. The second chip 60 is disposed at a distance from the first chip 50 in the X direction. In the first embodiment, the second die pad 91 is not exposed from the sealing resin 200. In one example, the shape of the second die pad 91 in plan view is a rectangle with the X direction being the long side direction and the Y direction being the short side direction. Note that the shape of the second die pad 91 in plan view can be arbitrarily changed according to the number and shape of the semiconductor chips mounted on the second die pad 91.

[0027] The multiple second leads 92 are arranged spaced apart from one another in the Y direction. Of the multiple second leads 92, the second leads 92 arranged at the ends closer to the sealing side surface 204 in the Y direction are integrated with the second die pad 91. The remaining second leads 92 are arranged spaced apart from the second die pad 91 in the X direction. A portion of each second lead 92 protrudes from the sealing side surface 202 outward from the sealing resin 200.

[0028] In the first embodiment, the number of second leads 92 is the same as the number of first leads 82. As can be seen from Fig. 2, the multiple first leads 82 and the multiple second leads 92 are arranged in a direction (Y direction) perpendicular to the arrangement direction (X direction) of the first die pad 81 and the second die pad 91 in a plan view. Note that the number of second leads 92 and the number of first leads 82 can each be changed arbitrarily. In one example, the number of first leads 82 and the number of second leads 92 may be different from each other.

[0029] In the first embodiment, the first die pad 81 is supported by a first lead 82 integrated with the first die pad 81. The second die pad 91 is supported by a second lead 92 integrated with the second die pad 91. Therefore, each of the die pads 81, 91 is not provided with a hanging lead exposed from the sealing side surfaces 203, 204. Therefore, the insulation distance (creepage distance) between the first lead frame 80 and the second lead frame 90 can be made large.

[0030] The first chip 50 mounted on the first die pad 81 includes the first circuit 20 of FIG. 1. The first chip 50 is formed in a rectangular shape having short sides and long sides in a plan view. In a plan view, the first chip 50 is mounted on the first die pad 81 so that the long sides run along the X direction and the short sides run along the Y direction. As shown in FIG. 3, the first chip 50 is bonded to the first die pad 81 by a conductive bonding material SD. The conductive bonding material SD may be a solder paste, an Ag (silver) paste, or the like.

[0031] The first chip 50 includes a plurality of first pads 55. The plurality of first pads 55 are electrically connected to the first circuit 20. The plurality of first pads 55 are also individually connected to a plurality of first leads 82 by wires W1. Each of the first pads 55 is formed of a material including one or more appropriately selected from Ti (titanium), TiN (titanium nitride), Au (gold), Ag, Cu, Al (aluminum), and W (tungsten). Each of the wires W1 is a bonding wire formed by a wire bonding device, and is formed of a conductor including, for example, Au, Al, Cu, etc.

[0032] As shown in Fig. 2, the second chip 60 mounted on the second die pad 91 includes the second circuit 30 of Fig. 1. The second chip 60 is formed in a rectangular shape having short sides and long sides in a plan view. In a plan view, the second chip 60 is mounted on the second die pad 91 so that the long sides are aligned along the X direction and the short sides are aligned along the Y direction. As shown in Fig. 3, the second chip 60 is bonded to the second die pad 91 by a conductive bonding material SD.

[0033] As shown in FIG. 2, the second chip 60 includes a plurality of second pads 65. The plurality of second pads 65 are electrically connected to the second circuit 30. The plurality of second pads 65 are also individually connected to a plurality of second leads 92 by wires W2. Each of the second pads 65 is formed of a material including one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W. Each of the wires W2 is a bonding wire formed by a wire bonding device, and is formed of a conductor including, for example, Au, Al, Cu, etc.

[0034] As shown in FIG. 2 and FIG. 3, in the first embodiment, the transformer chip 70 is disposed on the first chip 50. The transformer chip 70 includes the transformer 40 of FIG. 1. The transformer chip 70 is formed in a rectangular shape having short and long sides in a plan view. In a plan view, the transformer chip 70 is disposed on the first chip 50 so that the long side is along the X direction and the short side is along the Y direction. As shown in FIG. 2, in the first embodiment, the dimension of the transformer chip 70 in the Y direction is smaller than both the dimension of the first chip 50 in the Y direction and the dimension of the second chip 60 in the Y direction. Note that the dimension of the transformer chip 70 in the Y direction can be changed arbitrarily. In one example, the dimension of the transformer chip 70 in the Y direction may be equal to the dimension of the first chip 50 in the Y direction. In one example, the dimension of the transformer chip 70 in the Y direction may be equal to the dimension of the second chip 60 in the Y direction. Note that the electrical connection structure between the transformer chip 70 and the first chip 50 and the second chip 60 will be described later.

[0035] 1 to 3 is an example, and the circuit configurations included in the first chip 50 and the second chip 60 may be changed as appropriate. The first circuit 20 may include a circuit other than the transmitting circuit 21. The second circuit 30 may include a circuit other than the receiving circuit 31. For example, the first circuit 20 may include an analog-digital conversion circuit. In this case, the semiconductor device 10 is configured as an isolated A / D conversion device.

[0036] For example, the second circuit 30 may include a driver circuit that drives the gate of the switching element. The driver circuit may be connected to an external terminal of the semiconductor device 10 (for example, the second lead 92 shown in FIG. 2). In this case, the semiconductor device 10 is configured as an insulated gate driver that drives the switching element. The switching element is a power semiconductor element such as a SiMOSFET (Si Metal-Oxide-Semiconductor Field-Effect Transistor), a SiCMOSFET, or an IGBT (Insulated Gate Bipolar Transistor). The driver circuit is generally a half-bridge circuit in which a low-side switching element and a high-side switching element are connected in a totem pole configuration.

[0037] The semiconductor device 10 used as an insulated gate driver applies a drive voltage signal to the control terminal of a switching element. In this case, the transmission circuit 21 of the first circuit 20 converts a control signal input from, for example, a control device into a pulse signal. The driver circuit of the second circuit 30 outputs a drive voltage signal to the control terminal of the switching element in response to a signal received by the reception circuit 31 through the transformer 40.

[0038] Thus, in the semiconductor device 10 used as an insulated gate driver, the power supply voltage of the first circuit 20 that receives a signal from the control device is 5V, 3.3V, etc., with respect to the ground potential. On the other hand, in the case of the second circuit 30 connected to the high-side switching element, a voltage equivalent to the voltage applied to the drain of the high-side switching element (for example, 600V or more) is transiently applied. For this reason, the semiconductor device 10 is required to have a dielectric strength voltage between the first circuit 20 and the second circuit 30, more specifically, between the first coil 41 and the second coil 42 of the transformer 40. This dielectric strength voltage is, for example, 2500Vrms or more and 7500Vrms or less. In one example, the dielectric strength voltage of the semiconductor device 10 is about 5000Vrms. However, the specific value of the dielectric strength voltage of the semiconductor device 10 is not limited to this and is arbitrary.

[0039] (First chip configuration) An example of the configuration of first chip 50 will be described with reference to FIGS. Fig. 4 is a schematic diagram showing a planar structure of the first chip 50. Fig. 5 is a schematic diagram showing a cross-sectional structure of the first chip 50 taken along line F5-F5 in Fig. 4. Note that Fig. 5 shows one transistor of the transmission circuit 21 as the transmission circuit 21.

[0040] 4 and 5, the rectangular flat first chip 50 includes a chip front surface 50S and a chip back surface 50R facing opposite directions in the Z direction, and four chip side surfaces 50A to 50D connecting the chip front surface 50S and the chip back surface 50R. The chip front surface 50S of the first chip 50 is a surface that contacts, for example, a transformer chip 70 (see FIG. 3). The chip back surface 50R is a surface that faces the first die pad 81 (see FIG. 3). The chip side surfaces 50A and 50B form both end surfaces of the first chip 50 in the X direction, and the chip side surfaces 50C and 50D form both end surfaces of the first chip 50 in the Y direction.

[0041] As shown in FIG. 3, the first chip 50 includes a first semiconductor substrate 51 and a first element insulating layer 52 formed on the first semiconductor substrate 51. The first semiconductor substrate 51 constitutes the chip back surface 50R of the first chip 50. The chip back surface 50R (first semiconductor substrate 51) is bonded to the first die pad 81 by a conductive bonding material SD. The first semiconductor substrate 51 is formed of, for example, a material containing Si. In the first embodiment, the first semiconductor substrate 51 is a Si substrate. Note that a wide band gap semiconductor or a compound semiconductor may be used for the first semiconductor substrate 51. The wide band gap semiconductor is a semiconductor substrate having a band gap of 2.0 eV or more. The wide band gap semiconductor may be SiC (silicon carbide). The compound semiconductor may be a III-V group compound semiconductor. The compound semiconductor may include at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).

[0042] 5, the first element insulating layer 52 includes a first element front surface 52S facing the transformer chip 70 (see FIG. 3) and a first element back surface 52R opposite to the first element front surface 52S. The first element back surface 52R is in contact with the first semiconductor substrate 51. The first element front surface 52S constitutes the chip front surface 50S of the first chip 50.

[0043] The first element insulating layer 52 includes an insulator 52T in which a plurality of insulating films 52A are stacked in the Z direction. Therefore, the Z direction can be said to be the thickness direction of the first element insulating layer 52. Each insulating film 52A is, for example, an oxide film formed of a material containing SiO2 (silicon oxide). Each insulating film 52A has a thickness of, for example, 500 nm or more and 5000 nm or less. In the first embodiment, each insulating film 52A has a thickness of about 300 nm. Note that the number of layers of the insulating films 52A is not limited to the example shown in FIG. 5 and can be changed arbitrarily.

[0044] The first element insulating layer 52 includes a first protective film 53 and a first passivation film 54 . The first protective film 53 is a film that protects the insulator 52T. The first protective film 53 is formed on the insulator 52T. The first protective film 53 is formed of a material containing, for example, SiO2. In one example, the first protective film 53 is formed over the entire surface of the insulator 52T in a plan view. The material constituting the first protective film 53 can be changed arbitrarily. The first protective film 53 may be formed of a material containing, for example, SiN (silicon nitride).

[0045] The first passivation film 54 is a surface protection film of the first chip 50. The first passivation film 54 is formed on the first protective film 53. The first passivation film 54 constitutes the first element surface 52S of the first element insulating layer 52. The first passivation film 54 is formed of a material containing at least one of PI (polyimide), SiN, and SiO2. In one example, the first passivation film 54 is formed of a material containing SiO2. In one example, the first passivation film 54 is formed over the entire surface of the first protective film 53 in a plan view. The material constituting the first passivation film 54 can be changed arbitrarily. The first passivation film 54 may be formed of the same material as the first protective film 53, or may be formed of a material different from the first protective film 53.

[0046] 4, the first pads 55 are arranged at one of both ends in the X direction of the chip surface 50S, which is closer to the chip side surface 50A. Here, the chip side surface 50A is the side surface of the first chip 50 near the first leads 82 (see FIG. 2).

[0047] The first chip 50 includes a plurality of (two in the first embodiment) intermediate pads 56 electrically connected to the transformer chip 70. The intermediate pads 56 are arranged at the same position in the X direction and spaced apart from each other in the Y direction. The intermediate pads 56 are arranged, for example, closer to the chip side surface 50B than the first pads 55 in the X direction. As shown in FIG. 5, the intermediate pads 56 are arranged at the same positions as the first pads 55 in the Z direction. Each intermediate pad 56 is formed of a material including one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W.

[0048] In the first chip 50, there are provided a first circuit 20, a first connection wiring 57 connecting the first circuit 20 and the first pad 55, and a second connection wiring 58 connecting the first circuit 20 and the intermediate pad 56. That is, the first circuit 20 and the first pad 55 are electrically connected in the first chip 50. The first circuit 20 and the intermediate pad 56 are electrically connected in the first chip 50.

[0049] As shown in FIG. 5, the first connection wiring 57 includes a first circuit side connection portion 57A electrically connected to the transmission circuit 21, a first pad side connection portion 57B electrically connected to the first pad 55, and a first wiring 57C connecting the first circuit side connection portion 57A and the first pad side connection portion 57B.

[0050] The first circuit side connection portion 57A is formed of, for example, a via penetrating the insulating film 52A of the lowest layer of the insulator 52T in the Z direction. The first wiring 57C is a wiring layer formed on the insulating film 52A of the lowest layer. The first wiring 57C extends along the X direction from the first circuit side connection portion 57A toward the chip side surface 50A in a plan view, for example. The first pad side connection portion 57B is configured such that a plurality of wiring layers and a plurality of vias are alternately stacked one by one in the Z direction. The first pad side connection portion 57B is provided at a position overlapping with the first pad 55 in a plan view. Here, the insulating film 52A of the lowest layer is an insulating film that constitutes the first element back surface 52R of the first element insulating layer 52 and is in contact with the first semiconductor substrate 51.

[0051] The second connection wiring 58 includes a second circuit side connection portion 58A, a first intermediate wiring 58B, an intermediate connection portion 58C, a second intermediate wiring 58D, and a second pad side connection portion 58E. The second circuit side connection portion 58A is electrically connected to the transmission circuit 21. The second circuit side connection portion 58A is formed of, for example, a via penetrating the insulating film 52A of the lowest layer of the insulator 52T in the Z direction. In one example, the second circuit side connection portion 58A is disposed closer to the chip side surface 50B in the X direction than the first circuit side connection portion 57A of the first connection wiring 57. The first intermediate wiring 58B electrically connects the second circuit side connection portion 58A and the intermediate connection portion 58C. The first intermediate wiring 58B extends along the X direction from the second circuit side connection portion 58A toward the chip side surface 50B in a plan view, for example. The first intermediate wiring 58B is a wiring layer formed on the insulating film 52A of the lowest layer. That is, the first intermediate wiring 58B is disposed at the same position as the first wiring 57C of the first connection wiring 57 in the Z direction. The intermediate connection portion 58C is electrically connected to the second intermediate wiring 58D. The intermediate connection portion 58C is provided closer to the chip side surface 50B than the transmission circuit 21. The intermediate connection portion 58C has a configuration in which a plurality of vias and a plurality of wiring layers are alternately stacked one by one. The second intermediate wiring 58D is electrically connected to the second pad side connection portion 58E. The second intermediate wiring 58D extends along the X direction from the second pad side connection portion 58E toward the chip side surface 50A in a plan view. The second intermediate wiring 58D is disposed between the first intermediate wiring 58B and the intermediate pad 56 in the Z direction. The second pad side connection portion 58E electrically connects the second intermediate wiring 58D and the intermediate pad 56. The second pad side connection portion 58E is disposed at a position overlapping with the intermediate pad 56 in a plan view.

[0052] (Configuration of the second chip) An example of the configuration of the second chip 60 will be described with reference to FIGS. 3, 6, and 7. FIG. Fig. 6 is a schematic diagram showing a planar structure of the second chip 60. Fig. 7 is a schematic diagram showing a cross-sectional structure of the second chip 60 taken along line F7-F7 in Fig. 6. Note that Fig. 7 shows one transistor of the receiving circuit 31 as the receiving circuit 31.

[0053] As shown in FIG. 6 and FIG. 7, the second chip 60 in the shape of a rectangular plate includes a chip front surface 60S and a chip back surface 60R facing opposite directions in the Z direction, and four chip side surfaces 60A to 60D connecting the chip front surface 60S and the chip back surface 60R. The chip front surface 60S of the second chip 60 faces the same side as the chip front surface 50S of the first chip 50. The chip back surface 60R faces the second die pad 91 (see FIG. 3). The chip side surfaces 60A and 60B constitute both end surfaces of the second chip 60 in the X direction, and the chip side surfaces 60C and 60D constitute both end surfaces of the second chip 60 in the Y direction. The chip side surface 60A faces the same side as the chip side surface 50A of the first chip 50 (see FIG. 4), and the chip side surface 60B faces the same side as the chip side surface 50B of the first chip 50 (see FIG. 4). Chip side surface 60C faces the same side as chip side surface 50C of first chip 50 (see FIG. 4), and chip side surface 60D faces the same side as chip side surface 50D of first chip 50 (see FIG. 4).

[0054] As shown in FIG. 3, the second chip 60 includes a second semiconductor substrate 61 and a second element insulating layer 62 formed on the second semiconductor substrate 61. The second semiconductor substrate 61 constitutes the chip back surface 60R of the second chip 60. The chip back surface 60R (second semiconductor substrate 61) is bonded to the second die pad 91 by a conductive bonding material SD. The second semiconductor substrate 61 is formed of a material containing, for example, Si. In the first embodiment, the second semiconductor substrate 61 is a Si substrate. Note that the second semiconductor substrate 61 may be made of a wide band gap semiconductor or a compound semiconductor.

[0055] 7, the second element insulating layer 62 includes a second element front surface 62S facing away from the second die pad 91 (see FIG. 3), and a second element back surface 62R opposite to the second element front surface 62S. The second element back surface 62R is in contact with the second semiconductor substrate 61. The second element front surface 62S constitutes a chip front surface 60S of the second chip 60.

[0056] The second element insulating layer 62 includes an insulator 62T in which a plurality of insulating films 62A are stacked in the Z direction. Therefore, the Z direction can be said to be the thickness direction of the second element insulating layer 62. Each insulating film 62A is, for example, an oxide film formed of a material containing SiO2. The thickness of each insulating film 62A is, for example, the same as the thickness of each insulating film 52A (see FIG. 5 for both) of the first element insulating layer 52. Note that the number of layers of the insulating film 62A is not limited to the example shown in FIG. 7 and can be changed arbitrarily. The number of layers of the insulating film 62A may be, for example, the same as the number of layers of the insulating film 52A. Also, the number of layers of the insulating film 62A may be, for example, more or less than the number of layers of the insulating film 52A.

[0057] The second element insulating layer 62 includes a second protective film 63 and a second passivation film 64 . The second protective film 63 is a film that protects the insulator 62T. The configuration of the second protective film 63 is the same as the configuration of the first protective film 53 of the first chip 50, for example.

[0058] The second passivation film 64 is a surface protective film for the second chip 60. The second passivation film 64 is formed on the second protective film 63. The second passivation film 64 constitutes the second element surface 62S of the second element insulating layer 62. The configuration of the second passivation film 64 is the same as the configuration of, for example, the first passivation film 54 of the first chip 50 (see FIG. 5).

[0059] 6, the second pads 65 are arranged at one of both ends in the X direction of the chip surface 60S, which is closer to the chip side surface 60B. Here, the chip side surface 60B is the side surface of the second chip 60 that is closer to the second leads 92 (see FIG. 2).

[0060] The second chip 60 includes a plurality of (two in the first embodiment) intermediate pads 66 electrically connected to the transformer chip 70. The intermediate pads 66 are arranged at the same positions in the X direction and spaced apart from each other in the Y direction. The intermediate pads 66 are arranged closer to the chip side surface 60A than the second pads 65 in the X direction. In one example, the intermediate pads 66 are provided at the end closer to the transformer chip 70 (first chip 50) among both ends in the X direction of the chip surface 60S. Each intermediate pad 66 is formed of a material including one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W.

[0061] In the second chip 60, there are provided a second circuit 30, a third connection wiring 67 that connects the second circuit 30 and the second pad 65, and a fourth connection wiring 68 that connects the second circuit 30 and the intermediate pad 66. That is, the second circuit 30 and the second pad 65 are electrically connected in the second chip 60. The second circuit 30 and the intermediate pad 66 are electrically connected in the second chip 60.

[0062] As shown in Figure 7, the third connection wiring 67 includes a third circuit side connection portion 67A electrically connected to the receiving circuit 31, a third pad side connection portion 67B electrically connected to the second pad 65, and a third wiring 67C connecting the third circuit side connection portion 67A and the third pad side connection portion 67B.

[0063] The third circuit side connection portion 67A is formed of, for example, a via penetrating the insulating film 62A of the lowest layer of the insulator 62T in the Z direction. The third wiring 67C is a wiring layer formed on the insulating film 62A of the lowest layer. The third wiring 67C extends along the X direction from the third circuit side connection portion 67A toward the chip side surface 60B in a plan view, for example. The third pad side connection portion 67B is configured such that a plurality of wiring layers and a plurality of vias are alternately stacked one by one in the Z direction. The third pad side connection portion 67B is provided at a position overlapping with the second pad 65 in a plan view. Here, the insulating film 62A of the lowest layer is an insulating film that constitutes the second element back surface 62R of the second element insulating layer 62 and is in contact with the second semiconductor substrate 61.

[0064] The fourth connection wiring 68 includes a fourth circuit-side connection portion 68A, a first intermediate wiring 68B, an intermediate connection portion 68C, a second intermediate wiring 68D, and a fourth pad-side connection portion 68E. The fourth circuit side connection portion 68A is electrically connected to the receiving circuit 31. The fourth circuit side connection portion 68A is formed by, for example, a via penetrating the insulating film 62A of the lowest layer of the insulator 62T in the Z direction. In one example, the fourth circuit side connection portion 68A is disposed closer to the chip side surface 60A in the X direction than the third circuit side connection portion 67A of the third connection wiring 67. The first intermediate wiring 68B electrically connects the fourth circuit side connection portion 68A and the intermediate connection portion 68C. The first intermediate wiring 68B extends along the X direction from the fourth circuit side connection portion 68A toward the chip side surface 60A in a plan view, for example. The first intermediate wiring 68B is formed on the insulating film 62A of the lowest layer. That is, the first intermediate wiring 68B is disposed at the same position as the third wiring 67C of the third connection wiring 67 in the Z direction. The intermediate connection portion 68C is electrically connected to the second intermediate wiring 68D. The intermediate connection portion 68C is provided closer to the chip side surface 60A than the receiving circuit 31. The intermediate connection portion 68C is configured such that a plurality of vias and a plurality of wiring layers are alternately stacked one by one. The second intermediate wiring 68D is electrically connected to the fourth pad side connection portion 68E. The second intermediate wiring 68D extends along the X direction from the fourth pad side connection portion 68E toward the chip side surface 60A in a plan view. The second intermediate wiring 68D is disposed between the first intermediate wiring 68B and the intermediate pad 66 in the Z direction. The fourth pad side connection portion 68E electrically connects the second intermediate wiring 68D and the intermediate pad 66. The fourth pad side connection portion 68E is disposed at a position overlapping with the intermediate pad 66 in a plan view.

[0065] (Transformer chip configuration) An example of the configuration of transformer chip 70 will be described with reference to Fig. 3 and Figs. 8 to 10. Fig. 8 shows a schematic planar structure of transformer chip 70. Fig. 9 shows a schematic cross-sectional structure of transformer chip 70 taken along line F9-F9 in Fig. 8. Fig. 10 shows a schematic cross-sectional structure of transformer chip 70 taken along line F10-F10 in Fig. 8.

[0066] As shown in FIGS. 8 to 10, the rectangular flat transformer chip 70 includes a chip front surface 70S and a chip back surface 70R (see FIG. 9) that face opposite to each other in the Z direction, and four chip side surfaces 70A to 70D that connect the chip front surface 70S and the chip back surface 70R. The chip front surface 70S of the transformer chip 70 faces the same side as the chip front surface 50S (see FIG. 3) of the first chip 50. The chip back surface 70R faces the same side as the chip back surface 50R (see FIG. 3). The chip side surfaces 70A and 70B constitute both end surfaces of the transformer chip 70 in the X direction, and the chip side surfaces 70C and 70D constitute both end surfaces of the transformer chip 70 in the Y direction. The chip side surface 70A faces the same side as the chip side surface 50A (see FIG. 3) of the first chip 50, and the chip side surface 70B faces the same side as the chip side surface 50B (see FIG. 3) of the first chip 50. Chip side surface 70C faces the same side as chip side surface 50C of first chip 50 (see FIG. 4), and chip side surface 70D faces the same side as chip side surface 50D of first chip 50 (see FIG. 4).

[0067] As shown in FIG. 8, the transformer chip 70 includes first transformer pads 75A, 75B and second transformer pads 76A, 76B exposed in the Z direction from a chip surface 70S. The first transformer pads 75A, 75B are pads electrically connected to the first chip 50 (see FIG. 3). The first transformer pads 75A, 75B are arranged closer to the chip side surface 70A and closer to the chip side surface 70C in a plan view. The first transformer pads 75A, 75B are arranged at the same positions as each other in the X direction and spaced apart from each other in the Y direction.

[0068] The second transformer pads 76A, 76B are pads electrically connected to the second chip 60 (see FIG. 3). The second transformer pads 76A, 76B are arranged approximately in the center in the X direction and closer to the chip side surface 60D in the Y direction in a plan view. The second transformer pads 76A, 76B are arranged at the same positions as each other in the X direction and spaced apart from each other in the Y direction.

[0069] As shown in FIG. 9, the transformer chip 70 includes a third semiconductor substrate 71 and a third element insulating layer 72 formed on the third semiconductor substrate 71. The third semiconductor substrate 71 constitutes the chip back surface 70R of the transformer chip 70. The third semiconductor substrate 71 is formed of a material containing, for example, Si. In the first embodiment, the third semiconductor substrate 71 is a Si substrate. Note that the third semiconductor substrate 71 may be made of a wide band gap semiconductor or a compound semiconductor.

[0070] The Z-direction dimension (thickness) of the third semiconductor substrate 71 may be the same as, for example, the Z-direction dimension (thickness) of the first semiconductor substrate 51 (see FIG. 5). The Z-direction dimension (thickness) of the third element insulating layer 72 may be greater than, for example, the Z-direction dimension (thickness) of the first element insulating layer 52 (see FIG. 5). Therefore, the Z-direction dimension of the transformer chip 70 may be greater than the Z-direction dimension of the first chip 50.

[0071] Here, the dimension in the Z direction of the third semiconductor substrate 71 can be changed arbitrarily. In one example, the dimension in the Z direction of the third semiconductor substrate 71 may be smaller than the dimension in the Z direction of the first semiconductor substrate 51. In addition, the dimension in the Z direction of the third element insulating layer 72 can be changed arbitrarily. In one example, the dimension in the Z direction of the third element insulating layer 72 may be equal to the dimension in the Z direction of the first element insulating layer 52.

[0072] The third element insulating layer 72 includes a third element front surface 72S and a third element back surface 72R facing opposite directions. The third element front surface 72S constitutes a chip front surface 70S of the transformer chip 70. The third element back surface 72R is in contact with the third semiconductor substrate 71.

[0073] The third element insulating layer 72 includes a plurality of first insulating films 72P and a plurality of second insulating films 72Q. That is, the third element insulating layer 72 includes an insulating layer stack structure 72T which is a stack of a plurality of first insulating films 72P and a plurality of second insulating films 72Q. The insulating layer stack structure 72T is configured by stacking a plurality of first insulating films 72P and a plurality of second insulating films 72Q one by one in the Z direction. Here, if a stack of one first insulating film 72P and one second insulating film 72Q is an insulator 72U, the insulating layer stack structure 72T can be said to be a structure in which a plurality of insulators 72U are stacked. In this way, the Z direction can also be said to be the thickness direction of the third element insulating layer 72.

[0074] The first insulating film 72P is an etching stopper film, and is formed of a material including at least one of, for example, SiN, SiC, and SiCN (nitrogen-doped silicon carbide). The first insulating film 72P may have a function of preventing the diffusion of, for example, Cu. In other words, the first insulating film 72P may be a film preventing the diffusion of Cu.

[0075] The second insulating film 72Q is an interlayer insulating film, and is, for example, an oxide film formed of a material containing SiO2. The second insulating film 72Q has a thickness greater than that of the first insulating film 72P. The first insulating film 72P has a thickness of, for example, 50 nm or more and less than 1000 nm. The second insulating film 72Q has a thickness of, for example, 500 nm or more and 5000 nm or less. In the first embodiment, the first insulating film 72P has a thickness of about 300 nm, and the second insulating film 72Q has a thickness of about 2000 nm. In one example, both the uppermost and lowermost insulating films of the insulating layer stack structure 72T are composed of the second insulating film 72Q. In order to easily understand the drawings, the ratio of the thickness of the first insulating film 72P to the thickness of the second insulating film 72Q in the drawings is different from the actual ratio of the thickness of the first insulating film 72P to the thickness of the second insulating film 72Q.

[0076] The third element insulating layer 72 includes a third protective film 73 and a third passivation film 74 . The third protective film 73 is a film that protects the insulating layer stack structure 72T. The third protective film 73 is formed on the insulating layer stack structure 72T. The third protective film 73 is formed of a material containing SiO2, for example. In one example, the third protective film 73 is formed over the entire surface of the insulating layer stack structure 72T in a plan view. The material constituting the third protective film 73 can be changed arbitrarily. In one example, the third protective film 73 may be formed of a material containing SiN.

[0077] The third passivation film 74 is a surface protection film of the transformer chip 70. The third passivation film 74 is formed on the third protective film 73. The third passivation film 74 constitutes the third element surface 72S of the third element insulating layer 72. The third passivation film 74 is formed of a material containing at least one of PI, SiN, and SiO2. In one example, the third passivation film 74 is formed of a material containing SiO2. In one example, the third passivation film 74 is formed over the entire surface of the third protective film 73 in a plan view. The material constituting the third passivation film 74 can be changed arbitrarily. The third passivation film 74 may be formed of the same material as the third protective film 73, or may be formed of a material different from the third protective film 73.

[0078] As shown in Fig. 8, the transformer chip 70 includes an outer coil 100 and an inner coil 110. As shown in Fig. 9 and Fig. 10, both the outer coil 100 and the inner coil 110 are embedded in a third element insulating layer 72. The outer coil 100 corresponds to the first coil 41 of the transformer 40 in Fig. 1, and the inner coil 110 corresponds to the second coil 42 of the transformer 40.

[0079] In one example, the outer coil 100 and the inner coil 110 are arranged at the same position in the Z direction. It can be said that the outer coil 100 and the inner coil 110 are arranged on the same plane perpendicular to the Z direction. Specifically, the outer coil 100 and the inner coil 110 are provided so as to penetrate a specific insulator 72UA, which is a specific insulator 72U. In the example shown in FIG. 9 and FIG. 10, the specific insulator 72UA is an insulator 72U immediately below the top insulator 72U in the insulating layer laminate structure 72T. In other words, the specific insulator 72UA is the second insulator 72U from the third element surface 72S in the insulating layer laminate structure 72T. That is, in the example shown in FIG. 9 and FIG. 10, the outer coil 100 and the inner coil 110 are arranged closer to the third element surface 72S than the center of the third element insulating layer 72 in the Z direction. Note that the specific insulator 72UA in the insulating layer laminate structure 72T is optional. In one example, the specific insulator 72UA may be the uppermost insulator 72U of the insulating layer stack structure 72T.

[0080] In plan view, the inner coil 110 is disposed inside the outer coil 100. The inner coil 110 is disposed so as not to overlap the outer coil 100 in plan view. In other words, the inner coil 110 is disposed apart from the outer coil 100 in a direction perpendicular to the Z direction. Therefore, a specific insulator 72UA is disposed between the inner coil 110 and the outer coil 100 in a direction perpendicular to the Z direction. In this way, the outer coil 100 and the inner coil 110 are electrically insulated from each other and are configured to be magnetically coupled. In the transformer 40 of the first embodiment, the outer coil 100 and the inner coil 110 are configured to be magnetically coupled in a direction perpendicular to the Z direction. Therefore, a current flows in the inner coil 110 in a direction corresponding to the direction of the magnetic flux generated by the current flowing in the outer coil 100.

[0081] As shown in FIG. 8, the outer coil 100 includes a first end 101 and a second end 102 opposite to the first end 101. The outer coil 100 is formed in a circular spiral shape in a plan view. In the spiral outer coil 100, the first end 101 is disposed inside the spiral, and the second end 102 is disposed outside the spiral. That is, the outer coil 100 is wound in a spiral shape with the first end 101 as the inner circumferential end and the second end 102 as the outer circumferential end. The outer coil 100 includes a lead wire 100A extending from the second end 102 toward the chip side surface 70A along the X direction. The lead wire 100A is disposed at the same position as the outer coil 100 in the Z direction. In one example, the lead wire 100A is formed integrally with the outer coil 100.

[0082] The tip of the lead wire 100A constitutes the first transformer pad 75B. In one example, the third element insulating layer 72 is provided with a second outer opening that exposes the tip of the lead wire 100A in the Z direction. The tip of the lead wire 100A exposed by the second outer opening constitutes the first transformer pad 75B.

[0083] The inner coil 110 disposed inside the outer coil 100 includes a first end 111 and a second end 112 opposite to the first end 111. The inner coil 110 is formed in a circular spiral shape in a plan view. In the spiral inner coil 110, the first end 111 is disposed inside the spiral, and the second end 112 is disposed outside the spiral. In other words, the inner coil 110 is wound in a spiral shape with the first end 111 as the inner circumferential end and the second end 112 as the outer circumferential end.

[0084] The first end 111 constitutes the second transformer pad 76A, and the second end 112 constitutes the second transformer pad 76B. In one example, the third element insulating layer 72 is individually provided with a first inner opening exposing the first end 111 in the Z direction and a second inner opening in the Z direction exposing the second end 112. The first end 111 exposed by the first inner opening constitutes the second transformer pad 76A, and the second end 112 exposed by the second inner opening constitutes the second transformer pad 76B.

[0085] Both the outer coil 100 and the inner coil 110 are made of a material including one or more of Ti (titanium), TiN (titanium nitride), Au, Ag, Cu, Al, and W (tungsten). In one example, the outer coil 100 and the inner coil 110 may be made of the same material. In one example, the outer coil 100 and the inner coil 110 may be made of a material including Cu.

[0086] 8, the transformer chip 70 includes a wiring portion 77 that electrically connects the first end 101 of the outer coil 100 and the first transformer pad 75A. The wiring portion 77 is made of a material including one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W.

[0087] As shown in FIG. 9, the wiring portion 77 includes a connection wiring 77A and vias 77B and 77C. The connection wiring 77A is disposed closer to the third semiconductor substrate 71 than the outer coil 100 in the Z direction. The connection wiring 77A extends in the X direction from the first end 101 of the outer coil 100 toward the chip side surface 70A in a plan view. The connection wiring 77A includes a first end 77AA and a second end 77AB, which are both ends in the X direction. The first end 77AA of the connection wiring 77A is electrically connected to the first end 101 of the outer coil 100 by a via 77B. The second end 77AB of the connection wiring 77A is electrically connected to the first transformer pad 75A by a via 77C. The first transformer pad 75A is exposed in the Z direction by a first outer opening provided in the third element insulating layer 72.

[0088] (Configuration with transformer chip placed on top of first chip) A configuration in a state where the transformer chip 70 is arranged on the first chip 50 (hereinafter, "chip arrangement state") will be described with reference to Figures 2 and 11. Figure 11 is an enlarged view of the first chip 50, the second chip 60, the transformer chip 70, and the periphery of these chips in Figure 3. In Figure 11, the sealing resin 200 is omitted to make the drawing easier to understand.

[0089] As shown in FIG. 2, the transformer chip 70 is smaller than the first chip 50 in a plan view. In one example, the dimension of the transformer chip 70 in the X direction is smaller than the dimension of the first chip 50 in the X direction. The dimension of the transformer chip 70 in the Y direction is smaller than the dimension of the first chip 50 in the Y direction. The transformer chip 70 is arranged biased toward the chip side surface 50B with respect to the first chip 50 in the X direction. The transformer chip 70 is arranged closer to the chip side surface 50B than the intermediate pad 56 of the first chip 50. In one example, the transformer chip 70 is arranged on the first chip 50 so that the chip side surface 70B of the transformer chip 70 and the chip side surface 50B of the first chip 50 are in the same position in a plan view.

[0090] In one example, in the chip arrangement state, the first transformer pads 75A, 75B and the two intermediate pads 56 of the first chip 50 are at the same position in the Y direction. In one example, in the chip arrangement state, the second transformer pads 76A, 76B and the two intermediate pads 66 of the second chip 60 are at the same position in the Y direction.

[0091] In addition, in the chip arrangement state, the first transformer pads 75A, 75B may be arranged shifted toward the sealing side surface 203 or the sealing side surface 204 of the sealing resin 200 with respect to the two intermediate pads 56. In addition, in the chip arrangement state, the second transformer pads 76A, 76B may be arranged shifted toward the sealing side surface 203 or the sealing side surface 204 with respect to the two intermediate pads 66.

[0092] 11, in the chip arrangement state, the transformer chip 70 is arranged on the first chip 50 such that the third semiconductor substrate 71 is closer to the first chip 50 than the third element insulating layer 72. In other words, in the chip arrangement state, the third semiconductor substrate 71 is interposed between the third element insulating layer 72 and the first chip 50. The third semiconductor substrate 71 is in contact with the first element insulating layer 52 of the first chip 50. In the first embodiment, the third semiconductor substrate 71 is in contact with the first element insulating layer 52 but is not bonded thereto.

[0093] The first transformer pads 75A, 75B and the two intermediate pads 56 of the first chip 50 are individually connected by two transmission wires WT. The first transformer pads 75A, 75B are electrically connected to the outer coil 100, and one of the two intermediate pads 56 is electrically connected to the transmission circuit 21, so that, for example, the first end 101 of the outer coil 100 is electrically connected to the transmission circuit 21. The other of the two intermediate pads 56 is connected to ground GND1 (see FIG. 1). Therefore, for example, the second end 102 of the outer coil 100 is electrically connected to ground GND1. In one example, the lengths of the two transmission wires WT are equal to each other in a plan view.

[0094] The second transformer pads 76A, 76B and the two intermediate pads 66 of the second chip 60 are individually connected by two receiving wires WR. The second transformer pads 76A, 76B are electrically connected to the inner coil 110, and one of the two intermediate pads 66 is electrically connected to the receiving circuit 31, so that, for example, the first end 111 of the inner coil 110 is electrically connected to the receiving circuit 31. The other of the two intermediate pads 66 is connected to the ground GND2 (see FIG. 1). Therefore, for example, the second end 112 of the inner coil 110 is electrically connected to the ground GND2. In one example, the lengths of the two receiving wires WR are equal to each other in a plan view.

[0095] The dielectric strength voltage of the semiconductor device 10 is determined by, for example, the distance DZ in the Z direction between the second intermediate wiring 58D of the second connection wiring 58 of the first chip 50 and the inner coil 110 of the transformer chip 70. Here, different from Fig. 11, the distance between the inner coil 110 and the outer coil 100 in the planar direction perpendicular to the Z direction is equal to or greater than the distance DZ.

[0096] [Method of manufacturing semiconductor device] Next, an example of a method for manufacturing the semiconductor device 10 of the first embodiment will be described. In the following description, for the reference numerals relating to the components of the semiconductor device 10, please refer to FIGS.

[0097] The manufacturing method of the semiconductor device 10 includes the steps of preparing a first chip 50, a second chip 60, a transformer chip 70, and a first lead frame 80 and a second lead frame 90.

[0098] The process of preparing the first chip 50 includes a process of forming a first element insulating layer 52, a plurality of first pads 55, a plurality of intermediate pads 56, a first connection wiring 57, and a second connection wiring 58 on a first semiconductor substrate 51 on which the first circuit 20 is formed. The plurality of first pads 55, the plurality of intermediate pads 56, the first connection wiring 57, and the second connection wiring 58 are formed by etching and sputtering using a metal mask in the process of laminating the insulating film 52A of the first element insulating layer 52.

[0099] The step of preparing the second chip 60 includes a step of forming a second element insulating layer 62, a plurality of second pads 65, a plurality of intermediate pads 66, a third connection wiring 67, and a fourth connection wiring 68 on a second semiconductor substrate 61 on which the second circuit 30 is formed. The plurality of second pads 65, the plurality of intermediate pads 66, the third connection wiring 67, and the fourth connection wiring 68 are formed by etching and sputtering using a metal mask in the process of laminating the insulating film 62A of the second element insulating layer 62.

[0100] The process of preparing the transformer chip 70 includes a process of forming a third element insulating layer 72, an outer coil 100, an inner coil 110, first transformer pads 75A and 75B, second transformer pads 76A and 76B, and a wiring section 77 on a third semiconductor substrate 71. The outer coil 100, the inner coil 110, the first transformer pads 75A and 75B, the second transformer pads 76A and 76B, and the wiring section 77 are formed by etching and sputtering using a metal mask in the process of laminating the first insulating film 72P and the second insulating film 72Q of the third element insulating layer 72.

[0101] The method for manufacturing the semiconductor device 10 includes a step of mounting a first chip 50 on a first die pad 81 of a first lead frame 80 and a step of mounting a second chip 60 on a second die pad 91 of a second lead frame 90.

[0102] In the process of mounting the first chip 50 on the first die pad 81, first, a conductive bonding material SD is applied to the first die pad 81. Next, the first chip 50 is placed on the conductive bonding material SD. Next, the first chip 50 is bonded to the first die pad 81 by melting and solidifying the conductive bonding material SD.

[0103] In the process of mounting the second chip 60 on the second die pad 91, first, a conductive bonding material SD is applied to the second die pad 91. Then, the second chip 60 is placed on the conductive bonding material SD. Then, the conductive bonding material SD is melted and solidified to bond the second chip 60 to the second die pad 91. Here, the conductive bonding material SD applied to the first die pad 81 and the conductive bonding material SD applied to the second die pad 91 may be melted and solidified at the same time.

[0104] The manufacturing method of the semiconductor device 10 includes a step of forming a plurality of wires W1 and a plurality of wires W2. The plurality of wires W1 are formed using a wire bonding device so as to individually connect the plurality of first pads 55 of the first chip 50 to the plurality of first leads 82 of the first lead frame 80. The plurality of wires W2 are formed using a wire bonding device so as to individually connect the plurality of second pads 65 of the second chip 60 to the plurality of second leads 92 of the second lead frame 90.

[0105] The manufacturing method of the semiconductor device 10 includes a step of arranging the transformer chip 70 on the first chip 50. By arranging the transformer chip 70 on the first chip 50, the third semiconductor substrate 71 of the transformer chip 70 contacts the first element insulating layer 52 of the first chip 50.

[0106] The manufacturing method of the semiconductor device 10 includes a step of forming a plurality of transmitting wires WT and a plurality of receiving wires WR. The plurality of transmitting wires WT are formed by using a wire bonding device so as to individually connect the first transformer pads 75A, 75B to the two intermediate pads 56 of the first chip 50. The plurality of receiving wires WR are formed by using a wire bonding device so as to individually connect the second transformer pads 76A, 76B to the two intermediate pads 66 of the second chip 60.

[0107] The manufacturing method of the semiconductor device 10 includes a step of forming the sealing resin 200. In this step, the sealing resin 200 is formed by, for example, transfer molding. As a result, the sealing resin 200 seals the first chip 50, the second chip 60, the transformer chip 70, the first die pad 81, the second die pad 91, the multiple wires W1 and W2, the multiple transmitting wires WT, and the multiple receiving wires WR. Through the above steps, the semiconductor device 10 is manufactured.

[0108] In the manufacturing method of the semiconductor device 10, the order of the steps of forming the wires W1 and W2 can be changed as desired. In one example, the step of forming the wires W1 and W2 may be performed simultaneously with the step of forming the transmitting wires WT and the receiving wires WR. In other words, in the chip arrangement state, the wires W1 and W2, the transmitting wires WT, and the receiving wires WR may be formed consecutively by a wire bonding device.

[0109] [Operation of the first embodiment] The operation of the semiconductor device 10 of the first embodiment will be described. In the following description, the transformer chip in which two coils are arranged facing each other in the Z direction in the third element insulating layer 72 is referred to as the "transformer chip of the comparative example." The transformer chip of the comparative example is bonded to the first die pad 81 by the conductive bonding material SD, not on the first chip 50.

[0110] In the transformer chip of the comparative example, the dielectric strength of the semiconductor device is determined based on the distance between the two coils arranged opposite to each other in the Z direction. Therefore, in order to improve the dielectric strength of the semiconductor device, it is necessary to increase the distance between the two coils arranged opposite to each other in the Z direction by increasing the thickness of the third element insulating layer 72. However, if the thickness of the third element insulating layer 72 is increased, the third semiconductor substrate 71 is more likely to warp during the manufacture of the transformer chip of the comparative example. The thicker the third element insulating layer 72, the greater the warp that occurs in the third semiconductor substrate 71.

[0111] In the first embodiment, the transformer chip 70 is disposed on the first chip 50, and thus the withstand voltage of the semiconductor device 10 is determined based on the distance DZ in the Z direction between the second intermediate wiring 58D of the second connection wiring 58 in the first chip 50 and the inner coil 110 of the transformer chip 70. In other words, the withstand voltage of the semiconductor device 10 is determined not only by the thickness of the third element insulating layer 72, but also by the distance between the second intermediate wiring 58D of the first chip 50 and the chip surface 50S, and the thickness of the third semiconductor substrate 71. Therefore, in the first embodiment, the withstand voltage of the semiconductor device 10 can be improved without increasing the thickness of the third element insulating layer 72.

[0112] In addition, the inner coil 110 and the outer coil 100 are disposed facing each other in a direction perpendicular to the Z direction. Therefore, by increasing the size of the transformer chip 70 in the X direction and the Y direction, the distance between the inner coil 110 and the outer coil 100 in the direction perpendicular to the Z direction can be made equal to or greater than the distance DZ. In other words, the distance between the inner coil 110 and the outer coil 100 in the direction perpendicular to the Z direction can be made equal to or greater than the distance DZ without increasing the thickness of the third element insulating layer 72. Therefore, the dielectric strength of the semiconductor device 10 can be improved.

[0113] Furthermore, the wiring resistance values ​​of the outer coil 100 and the inner coil 110 affect the amount of current flowing through the outer coil 100 and the inner coil 110, and the degree of magnetic coupling. The wiring resistance value of the outer coil 100 can be reduced by widening the wiring width of the outer coil 100 and reducing the aspect ratio of the wiring thickness to the wiring width. Similarly, the wiring resistance value of the inner coil 110 can be reduced by widening the wiring width of the inner coil 110 and reducing the aspect ratio of the wiring thickness to the wiring width.

[0114] Here, in the transformer chip of the comparative example, two coils are arranged facing each other in the Z direction, so if the wiring width of these coils is increased, the facing area of ​​the two coils increases, and the capacitance value of the parasitic capacitor increases.

[0115] In the first embodiment, the outer coil 100 and the inner coil 110 face each other in a direction perpendicular to the Z direction. Therefore, even if the wiring width of each of the outer coil 100 and the inner coil 110 is increased, the facing area of ​​the outer coil 100 and the inner coil 110 does not change. That is, the capacitance value of the parasitic capacitor between the outer coil 100 and the inner coil 110 does not change. That is, compared to the transformer chip of the comparative example, the wiring resistance value of each coil can be reduced without increasing the capacitance value of the parasitic capacitor between the coils. As a result, since the current flows easily in the outer coil 100 and the inner coil 110, the amount of magnetic flux generated in the transformer 40 can be increased. Then, the efficiency of the magnetic coupling between the outer coil 100 and the inner coil 110 can be improved, and the transfer characteristics can be improved.

[0116] [Effects of the first embodiment] According to the semiconductor device 10 of the first embodiment, the following effects can be obtained. (1-1) The semiconductor device 10 includes a first chip 50 including a first circuit 20, a second chip 60 including a second circuit 30 and disposed apart from the first chip 50 in the X direction, and a transformer chip 70 including a transformer 40 and disposed on the first chip 50. The first circuit 20 and the second circuit 30 are configured to transmit signals via the transformer 40. The transformer chip 70 includes a third element insulating layer 72, and an outer coil 100 and an inner coil 110 disposed in the third element insulating layer 72 as the transformer 40. In a plan view, the inner coil 110 is disposed inside the outer coil 100 so as not to overlap with the outer coil 100.

[0117] According to this configuration, by disposing the transformer chip 70 on the first chip 50, the distance between the transformer 40 in the transformer chip 70 and the first circuit 20, which contribute to the dielectric strength of the semiconductor device 10, can be increased. In addition, since the inner coil 110 and the outer coil 100 are disposed apart from each other in a direction perpendicular to the Z direction, the distance between the inner coil 110 and the outer coil 100, which contribute to the dielectric strength of the semiconductor device 10, can be increased without increasing the thickness of the third element insulating layer 72. In other words, by increasing the size of the third element insulating layer 72 in the direction perpendicular to the Z direction, the distance between the inner coil 110 and the outer coil 100 can be increased. Therefore, the dielectric strength of the semiconductor device 10 can be improved without increasing the thickness of the third element insulating layer 72.

[0118] (1-2) The transformer chip 70 includes a third semiconductor substrate 71 in contact with a third element insulating layer 72. In a chip arrangement state in which the transformer chip 70 is arranged on the first chip 50, the third semiconductor substrate 71 is interposed between the third element insulating layer 72 and the first chip 50.

[0119] According to this configuration, the distance between the transformer 40 and the first circuit 20 in the transformer chip 70, which contributes to the dielectric strength of the semiconductor device 10, can be increased by the thickness of the third semiconductor substrate 71. Therefore, the dielectric strength of the semiconductor device 10 can be improved.

[0120] (1-3) The third element insulating layer 72 includes a third element front surface 72S and a third element back surface 72R opposite to the third element front surface 72S. The outer coil 100 is electrically connected to the first circuit 20. The inner coil 110 is disposed in the third element insulating layer 72 closer to the third element front surface 72S than to the third element back surface 72R.

[0121] According to this configuration, by disposing the transformer chip 70 on the first chip 50, it is possible to increase the distance between the first circuit 20 and the inner coil 110 in the transformer chip 70, which contributes to the dielectric strength of the semiconductor device 10. Therefore, it is possible to improve the dielectric strength of the semiconductor device 10.

[0122] (1-4) The first circuit 20 includes a transmitting circuit 21. The second circuit 30 includes a receiving circuit 31. The outer coil 100 and the transmitting circuit 21 are electrically connected via a transmitting wire WT. The inner coil 110 and the receiving circuit 31 are electrically connected via a receiving wire WR. The length of the transmitting wire WT is shorter than the length of the receiving wire WR.

[0123] According to this configuration, by shortening the length of the receiving wire WR, which has a greater influence on the transmission characteristics than the transmitting wire WT, the transmission characteristics of the semiconductor device 10 can be improved compared to when the length of the transmitting wire WT is longer than the length of the receiving wire WR.

[0124] In addition, because the outer coil 100 and the transmitting circuit 21 are connected by the transmitting side wire WT, the connection structure between the outer coil 100 and the transmitting circuit 21 can be simplified compared to a configuration in which the outer coil 100 and the transmitting circuit 21 are connected by wiring provided in the transformer chip 70 and wiring provided in the first chip 50. In addition, because there is no need to position the arrangement position of the transformer chip 70 with respect to the first chip 50 with high precision, the semiconductor device 10 can be easily manufactured.

[0125] (1-5) The inner coil 110 and the outer coil 100 are disposed at the same position relative to each other in the Z direction. According to this configuration, the inner coil 110 and the outer coil 100 can be formed using a common mask when manufacturing the transformer chip 70. Therefore, compared with a configuration in which the inner coil 110 and the outer coil 100 are disposed at different positions in the Z direction, the manufacturing process of the transformer chip 70 can be simplified, and the manufacturing cost of the transformer chip 70 can be reduced.

[0126] (1-6) In a plan view, the transformer chip 70 is smaller than the first chip 50. The transformer chip 70 is disposed closer to the second chip 60 than the first chip 50 in the X direction.

[0127] According to this configuration, the distance in the X direction between the transformer chip 70 and the second chip 60 is reduced in a plan view. Therefore, the length of the receiving wire WR connecting the transformer chip 70 and the second chip 60 can be shortened.

[0128] (1-7) The transformer chip 70 includes chip side surfaces 70A, 70B which are both end faces in the X direction. The first chip 50 includes chip side surfaces 50A, 50B which are both end faces in the X direction. The chip side surface 70A faces the same side as the chip side surface 50A, and the chip side surface 70B faces the same side as the chip side surface 50B. The chip side surfaces 70B, 50B are chip side surfaces closer to the second chip 60. The transformer chip 70 is disposed on the first chip 50 such that the chip side surface 70B is in the same position as the chip side surface 50B of the first chip 50 in a plan view.

[0129] According to this configuration, the distance in the X direction between the transformer chip 70 and the second chip 60 is further reduced in a plan view. Therefore, the length of the receiving wire WR connecting the transformer chip 70 and the second chip 60 can be further shortened.

[0130] (1-8) Both the inner coil 110 and the outer coil 100 are disposed closer to the third element surface 72S of the third element insulating layer 72 in the Z direction. According to this configuration, the distance in the Z direction between the outer coil 100 and the inner coil 110 and the third semiconductor substrate 71 can be made larger than in a configuration in which two coils are arranged facing each other in the Z direction. Therefore, the magnetic flux generated in the outer coil 100 and the inner coil 110 is less likely to pass through the third semiconductor substrate 71. This makes it possible to suppress the generation of eddy currents caused by the magnetic flux penetrating the third semiconductor substrate 71. Therefore, it is possible to suppress the decrease in efficiency of magnetic coupling caused by eddy currents.

[0131] <Second embodiment> A semiconductor device 10 of the second embodiment will be described with reference to Fig. 12. The semiconductor device 10 of the second embodiment differs from the semiconductor device 10 of the first embodiment mainly in the configuration of the third element insulating layer 72 of the transformer chip 70. Below, differences from the first embodiment will be described in detail, and components common to the first embodiment will be denoted by the same reference numerals and their description will be omitted.

[0132] Fig. 12 shows a cross-sectional structure of a specific insulator 72UA and its periphery in the third element insulating layer 72 of the transformer chip 70. The cross-sectional position in Fig. 12 is the same as the cross-sectional position in Fig. 10 of the first embodiment.

[0133] As shown in FIG. 12, the third element insulating layer 72 of the transformer chip 70 includes a specific insulator 72UA in which the outer coil 100 and the inner coil 110 are provided, and a cover insulating film 72UB that covers the outer coil 100 and the inner coil 110 from the Z direction.

[0134] The cover insulating film 72UB is composed of the first insulating film 72P. The cover insulating film 72UB is in contact with the second insulating film 72Q of the specific insulator 72UA. In one example, the cover insulating film 72UB is in contact with the outer coil 100 and the inner coil 110.

[0135] The third element insulating layer 72 includes a plurality of isolation insulating films 78A and a plurality of cover-side isolation insulating films 78B. Here, the second insulating film 72Q directly below the specific insulator 72UA is referred to as a "second insulating film 72QA," and the second insulating film 72Q formed on the cover insulating film 72UB is referred to as a "second insulating film 72QB."

[0136] In a direction perpendicular to the Z direction, a plurality of grooves 72V are formed in the first insulating film 72P of the specific insulator 72UA between the outer coil 100 and the inner coil 110. In the second embodiment, each groove 72V is a rectangular groove that penetrates the first insulating film 72P of the specific insulator 72UA in the Z direction and forms a concave shape in the second insulating film 72QA. Each groove 72V is formed in a ring shape in a plan view. In one example, the plurality of grooves 72V are formed in a concentric shape in a plan view. In one example, the centers of the plurality of grooves 72V are concentric with the centers of the outer coil 100 and the inner coil 110. In this way, the plurality of grooves 72V separate the first insulating film 72P of the specific insulator 72UA between the outer coil 100 and the inner coil 110 in a direction perpendicular to the Z direction.

[0137] A second insulating film 72Q of a specific insulator 72UA is filled in the grooves 72V. This forms a plurality of isolation insulating films 78A. That is, each isolation insulating film 78A is formed of a second insulating film 72Q containing SiO2. In this way, between the outer coil 100 and the inner coil 110, the first insulating film 72P formed of SiN is separated by the isolation insulating film 78A formed of SiO2. That is, the first insulating film 72P between the outer coil 100 and the inner coil 110 is separated by a second insulating film 72Q (isolation insulating film 78A) having a smaller dielectric constant than the first insulating film 72P. A plurality of first insulating films 72P between the outer coil 100 and the inner coil 110 are provided at a distance from each other in a plane direction perpendicular to the Z direction. A separation insulating film 78A (second insulating film 72Q) is interposed between the plurality of first insulating films 72P. Since each groove 72V is formed in an annular shape, each isolation insulating film 78A provided in each groove 72V is formed in an annular shape in a planar view. When a plurality of grooves 72V are formed in a concentric shape in a planar view, the plurality of isolation insulating films 78A are formed in a concentric shape in a planar view. In this manner, the first insulating film 72P and the second insulating film 72Q are alternately arranged between the outer coil 100 and the inner coil 110 in a direction perpendicular to the Z direction.

[0138] In a surface direction perpendicular to the Z direction, a plurality of grooves 72W are formed in the cover insulating film 72UB between the outer coil 100 and the inner coil 110. In the second embodiment, each groove 72W is a rectangular groove that penetrates the cover insulating film 72UB in the Z direction and forms a concave shape in the second insulating film 72Q of the specific insulator 72UA. Each groove 72W is formed in a ring shape in a plan view. In one example, the plurality of grooves 72W are formed in a concentric shape in a plan view. In one example, the centers of the plurality of grooves 72W are concentric with the centers of the outer coil 100 and the inner coil 110. In this way, the cover insulating film 72UB is provided between the outer coil 100 and the inner coil 110 at a distance in a direction perpendicular to the Z direction by the plurality of grooves 72W.

[0139] In one example, the width dimension of each groove 72W is equal to the width dimension of each groove 72V. Furthermore, the width dimensions of the multiple grooves 72W are equal to each other. Furthermore, the width dimensions of the multiple grooves 72V are equal to each other. Here, the width dimension of each groove 72V, 72W can be defined by the distance between the side surfaces constituting each groove 72V, 72W in a direction perpendicular to the Z direction.

[0140] A second insulating film 72QB is buried in the grooves 72W. This forms a plurality of cover-side isolation insulating films 78B. That is, each cover-side isolation insulating film 78B is formed by the second insulating film 72QB containing SiO2. In this manner, the cover insulating film 72UB made of SiN is separated between the outer coil 100 and the inner coil 110 by the cover-side isolation insulating film 78B made of SiO2. That is, the cover insulating film 72UB is separated between the outer coil 100 and the inner coil 110 by the second insulating film 72Q (cover-side isolation insulating film 78B) having a smaller dielectric constant than the cover insulating film 72UB. A plurality of cover insulating films 72UB between the outer coil 100 and the inner coil 110 are provided at a distance from each other in a surface direction perpendicular to the Z direction. A cover-side isolation insulating film 78B (second insulating film 72QB) is interposed between the plurality of cover insulating films 72UB. Since each groove 72W is formed in an annular shape, each cover-side isolation insulating film 78B provided in each groove 72W is formed in an annular shape in plan view. When a plurality of grooves 72W are formed concentrically in plan view, the plurality of cover-side isolation insulating films 78B are formed concentrically in plan view. In this manner, the cover insulating film 72UB (first insulating film 72P) and the cover-side isolation insulating film 78B (second insulating film 72Q) are alternately arranged in the direction perpendicular to the Z direction between the outer coil 100 and the inner coil 110 of the cover insulating film 72UB.

[0141] When the width of each groove 72W is equal to the width of each groove 72V, the width of each cover-side isolation insulating film 78B is equal to the width of each isolation insulating film 78A. When the widths of the grooves 72W are equal to each other, the widths of the cover-side isolation insulating films 78B are equal to each other. When the widths of the grooves 72V are equal to each other, the widths of the isolation insulating films 78A are equal to each other. Here, the width of the isolation insulating film 78A can be defined by the distance between the side surfaces of the isolation insulating film 78A that contact the side surfaces that constitute the groove 72V in the direction perpendicular to the Z direction. The width of the cover-side isolation insulating film 78B can be defined by the distance between the side surfaces of the cover-side isolation insulating film 78B that contact the side surfaces that constitute the groove 72W in the direction perpendicular to the Z direction.

[0142] The number of the grooves 72V, 72W can be changed arbitrarily. In the second embodiment, the grooves 72V, 72W are arranged at positions where they overlap each other in a plan view, but this is not limited thereto. The grooves 72V, 72W may be arranged at positions different from each other in a plan view. In other words, the number of the isolation insulating films 78A and the number of the cover-side isolation insulating films 78B can be changed arbitrarily. In the second embodiment, the isolation insulating films 78A and the cover-side isolation insulating films 78B are arranged at positions where they overlap each other in a plan view, but this is not limited thereto. The isolation insulating films 78A and the cover-side isolation insulating films 78B may be arranged at positions different from each other in a plan view.

[0143] The widths of the grooves 72V and 72W can be changed arbitrarily. In one example, the widths of the grooves 72V and 72W can be different from each other. That is, the widths of the isolation insulating film 78A and the cover-side isolation insulating film 78B can be different from each other. In one example, the width of at least one of the grooves 72V can be different from the width of the remaining grooves 72V. That is, the width of at least one of the isolation insulating films 78A can be different from the width of the remaining isolation insulating films 78A. In one example, the width of at least one of the grooves 72W can be different from the width of the remaining grooves 72W. That is, the width of at least one of the cover-side isolation insulating films 78B can be different from the width of the remaining cover-side isolation insulating films 78B. In addition, the shapes of the grooves 72V and 72W are not limited to a rectangular concave shape and can be changed arbitrarily. In one example, the grooves 72V and 72W can be V-shaped.

[0144] [Effects of the second embodiment] According to the semiconductor device 10 of the second embodiment, the following effects can be obtained. (2-1) The third element insulating layer 72 includes an insulating layer stack structure 72T in which a plurality of insulators 72U are stacked, each of which includes a first insulating film 72P containing silicon nitride and a second insulating film 72Q containing silicon oxide stacked on the first insulating film 72P. The inner coil 110 and the outer coil 100 are provided to penetrate a specific insulator 72UA that is a specific insulator 72U. The third element insulating layer 72 includes a cover insulating film 72UB that is formed of the first insulating film 72P and contacts the second insulating film 72Q of the specific insulator 72UA so as to cover the inner coil 110 and the outer coil 100. A portion of the first insulating film 72P of the specific insulator 72UA between the inner coil 110 and the outer coil 100 includes a plurality of isolation insulating films 78A that are spaced apart in a direction perpendicular to the Z direction. A portion of the cover insulating film 72UB between the inner coil 110 and the outer coil 100 includes a plurality of cover-side isolation insulating films 78B that are spaced apart in a direction perpendicular to the Z direction. Each of the multiple isolation insulating films 78A and the cover-side isolation insulating film 78B is made of a second insulating film 72Q.

[0145] According to this configuration, in the portion of the first insulating film 72P of the specific insulator 72UA between the inner coil 110 and the outer coil 100, the multiple isolation insulating films 78A and the second insulating film 72Q are alternately arranged. Therefore, the creeping distance between the inner coil 110 and the outer coil 100 can be made large. In addition, in the portion of the cover insulating film 72UB between the inner coil 110 and the outer coil 100, the multiple cover-side isolation insulating films 78B and the second insulating film 72Q are alternately arranged. Therefore, the creeping distance between the inner coil 110 and the outer coil 100 can be made large. Therefore, the dielectric strength of the semiconductor device 10 can be improved while suppressing the size increase of the transformer chip 70.

[0146] (2-2) Each of the spaces between the isolation insulating films 78A and each of the cover-side isolation insulating films 78B are formed in an annular shape. According to this configuration, the second insulating film 72Q interposed between the plurality of isolation insulating films 78A is formed in an annular shape, and the second insulating film 72Q interposed between the plurality of cover-side isolation insulating films 78B is formed in an annular shape. Therefore, in the portion between the inner coil 110 and the outer coil 100, the insulation distance (creepage distance) between the inner coil 110 and the outer coil 100 can be made large over the entire circumference of the inner coil 110.

[0147] <Third embodiment> A semiconductor device 10 of the third embodiment will be described with reference to Figures 13 to 17. The semiconductor device 10 of the third embodiment differs from the semiconductor device 10 of the first embodiment mainly in the configuration of the transformer chip 70. Below, differences from the first embodiment will be described in detail, and components common to the first embodiment will be denoted by the same reference numerals and descriptions thereof will be omitted.

[0148] (Circuit configuration of semiconductor device) FIG. 13 diagrammatically illustrates a circuit configuration of a semiconductor device 10 according to the third embodiment. 13, in the semiconductor device 10, a transformer 40 provided between the transmitting circuit 21 of the first circuit 20 and the receiving circuit 31 of the second circuit 30 includes first to third coils 41 to 43. The first coil 41 is electrically connected to the transmitting circuit 21 as in the first embodiment. The second coil 42 and the third coil 43 are electrically connected to each other. The second coil 42 and the third coil 43 are electrically connected to the receiving circuit 31. The first coil 41, the second coil 42, and the third coil 43 are electrically insulated from each other and configured to be magnetically coupled.

[0149] (Configuration of Semiconductor Device) FIG. 14 is a schematic diagram showing an example of the planar structure of the semiconductor device 10 of FIG. As shown in Fig. 14, the semiconductor device 10 includes a first chip 50 including the first circuit 20 shown in Fig. 13, a second chip 60 including the second circuit 30 shown in Fig. 13, and a transformer chip 70 including the first to third coils 41 to 43 shown in Fig. 13. The transformer chip 70 is disposed on the first chip 50, as in the first embodiment. Furthermore, the semiconductor device 10 includes a first lead frame 80, a second lead frame 90, and a sealing resin 200, as in the first embodiment.

[0150] Unlike the first embodiment, the two intermediate pads 56 of the first chip 50 are disposed in the center in the Y direction on the chip surface 50S of the first chip 50. The two intermediate pads 56 are arranged at the same position as each other in the X direction and spaced apart from each other in the Y direction.

[0151] Unlike the first embodiment, the two intermediate pads 66 of the second chip 60 are disposed in the center in the Y direction of the chip surface 60S of the second chip 60. The two intermediate pads 66 are disposed at one of both ends in the X direction of the chip surface 60S that is closer to the chip side surface 60A. The two intermediate pads 66 are arranged at the same position as each other in the X direction and spaced apart from each other in the Y direction.

[0152] The transformer chip 70 includes first to sixth transformer pads 141 to 146. Both the first transformer pad 141 and the second transformer pad 142 are disposed closer to the chip side surface 70A than the third to sixth transformer pads 143 to 146 in a plan view. In one example, both the first transformer pad 141 and the second transformer pad 142 are disposed at the end closer to the chip side surface 70A among both ends in the X direction of the chip surface 70S. Both the first transformer pad 141 and the second transformer pad 142 are disposed at the center of the chip surface 70S in the Y direction. In one example, the first transformer pad 141 and the second transformer pad 142 are disposed at the same position in the Y direction as the two intermediate pads 56 of the first chip 50 in a plan view.

[0153] The third to sixth transformer pads 143 to 146 are arranged in the center of the chip surface 70S in the X direction. The third to sixth transformer pads 143 to 146 are arranged at the same positions in the X direction and spaced apart from each other in the Y direction. Both the third transformer pad 143 and the fourth transformer pad 144 are arranged closer to the chip side surface 70C of the chip surface 70S in the Y direction. Both the fifth transformer pad 145 and the sixth transformer pad 146 are arranged closer to the chip side surface 70D of the chip surface 70S in the Y direction. The electrical connection structure of the first to sixth transformer pads 141 to 146, the first chip 50, and the second chip 60 will be described later.

[0154] (Internal structure of the transformer chip) An example of the internal configuration of the transformer chip 70 will be described with reference to FIGS. Fig. 15 is a schematic diagram showing the planar structure of the inside of the transformer chip 70. Fig. 16 is a schematic diagram showing the cross-sectional structure along the line F16-F16 in Fig. 15. Fig. 17 is a schematic diagram showing the cross-sectional structure along the line F17-F17 in Fig. 15. For convenience, an outer coil 120 and an inner coil 130, which will be described later, are shown by solid lines in Fig. 15.

[0155] 15, the transformer chip 70 includes an outer coil 120 and an inner coil 130. The outer coil 120 corresponds to the first coil 41 shown in FIG. 13. The inner coil 130 includes a first inner coil 131 corresponding to the second coil 42 shown in FIG. 13, and a second inner coil 132 corresponding to the third coil 43 shown in FIG. 13. As shown in FIG. 16, each of the outer coil 120, the first inner coil 131, and the second inner coil 132 is embedded in the third element insulating layer 72.

[0156] 15, the outer coil 120 includes a first outer coil 121 and a second outer coil 122. The first outer coil 121 includes a first end 121A and a second end 121B opposite the first end 121A. The second outer coil 122 includes a first end 122A and a second end 122B opposite the first end 122A. The second end 121B of the first outer coil 121 and the second end 122B of the second outer coil 122 are electrically connected to each other.

[0157] Each of the first outer coil 121 and the second outer coil 122 is formed in a circular spiral shape in a plan view. The first outer coil 121 and the second outer coil 122 are wound so that magnetic fluxes in opposite directions are generated when a current flows from a first end of one of the first outer coil 121 and the second outer coil 122 to a first end of the other outer coil. In one example, the first outer coil 121 and the second outer coil 122 are symmetrical in a plan view. In the third embodiment, the first outer coil 121 and the second outer coil 122 are point-symmetrical in a plan view.

[0158] In the first outer coil 121 having a spiral shape, the first end 121A is disposed inside the spiral, and the second end 121B is disposed outside the spiral. That is, the first outer coil 121 is wound in a spiral shape with the first end 121A as the inner circumferential end and the second end 121B as the outer circumferential end. Similarly, in the second outer coil 122 having a spiral shape, the first end 122A is disposed inside the spiral, and the second end 122B is disposed outside the spiral. That is, the second outer coil 122 is wound in a spiral shape with the first end 122A as the inner circumferential end and the second end 122B as the outer circumferential end. The first outer coil 121 and the second outer coil 122 are electrically connected to each other at their second ends 121B and 122B, which are the outer circumferential edge ends. In one example, the first outer coil 121 and the second outer coil 122 are integrated together.

[0159] As shown in FIG. 16, the first outer coil 121 and the second outer coil 122 of the outer coil 120 are disposed at the same position in the Z direction. Both the first outer coil 121 and the second outer coil 122 are disposed closer to the third element surface 72S than the center in the Z direction of the third element insulating layer 72. In the third embodiment, both the first outer coil 121 and the second outer coil 122 are provided on the uppermost insulator 72U of the insulating layer stack structure 72T of the third element insulating layer 72. The outer coil 120 is formed of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W. The outer coil 120 of the third embodiment is formed of a material containing Cu. In addition, the first outer coil 121 and the second outer coil 122 may be provided not in the uppermost insulator 72U of the insulating layer stack structure 72T of the third element insulating layer 72, but, for example, in an insulator 72U directly below the uppermost insulator 72U.

[0160] 15, the first inner coil 131 is disposed inside the first outer coil 121. The first inner coil 131 is disposed apart from the first outer coil 121 in a planar direction perpendicular to the Z direction. In one example, the winding center of the first inner coil 131 and the winding center of the first outer coil 121 are concentric.

[0161] The second inner coil 132 is disposed on the inside of the second outer coil 122. The second inner coil 132 is disposed spaced apart from the second outer coil 122 in a planar direction perpendicular to the Z direction. In one example, the winding center of the second inner coil 132 and the winding center of the second outer coil 122 are concentric. The first inner coil 131 and the second inner coil 132 are arranged at the same positions as each other in the X direction and spaced apart from each other in the Y direction.

[0162] Each of the first inner coil 131 and the second inner coil 132 is formed in a circular spiral shape in a planar view. In one example, the first inner coil 131 and the second inner coil 132 are symmetrical in a planar view. In the third embodiment, the first inner coil 131 and the second inner coil 132 are point-symmetrical in a planar view.

[0163] A current flows through the first inner coil 131 in a direction corresponding to the direction of magnetic flux generated by a current flowing through the first outer coil 121. Similarly, a current flows through the second inner coil 132 in a direction corresponding to the direction of magnetic flux generated by a current flowing through the second outer coil 122.

[0164] The first inner coil 131 includes a first end 131A and a second end 131B opposite to the first end 131A. In the spiral-shaped first inner coil 131, the first end 131A is disposed on the inside of the spiral, and the second end 131B is disposed on the outside of the spiral. In other words, the first inner coil 131 is wound in a spiral shape with the first end 131A as the inner circumferential end and the second end 131B as the outer circumferential end.

[0165] The second inner coil 132 includes a first end 132A and a second end 132B opposite to the first end 132A. In the spiral-shaped second inner coil 132, the first end 132A is disposed on the inside of the spiral, and the second end 132B is disposed on the outside of the spiral. In other words, the second inner coil 132 is wound in a spiral shape with the first end 132A as the inner circumferential end and the second end 132B as the outer circumferential end.

[0166] As shown in FIG. 16 and FIG. 17, the first inner coil 131 and the second inner coil 132 are disposed at the same position in the Z direction. Both the first inner coil 131 and the second inner coil 132 are disposed closer to the third element surface 72S than the center in the Z direction of the third element insulating layer 72. In the third embodiment, both the first inner coil 131 and the second inner coil 132 are provided on the uppermost insulator 72U of the insulating layer stack structure 72T of the third element insulating layer 72. In this manner, both the first inner coil 131 and the second inner coil 132 are disposed at the same position in the Z direction as both the first outer coil 121 and the second outer coil 122. The inner coil 130 is formed of a material including one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W. In one example, the inner coil 130 is formed of the same material as the outer coil 120. The inner coil 130 of the third embodiment is formed of a material containing Cu. The first inner coil 131 and the second inner coil 132 may be provided in the insulator 72U directly below the uppermost insulator 72U, rather than in the uppermost insulator 72U of the insulating layer stack structure 72T of the third element insulating layer 72.

[0167] As shown in FIG. 15, the transformer chip 70 includes first to sixth openings 70SA to 70SF. The first to sixth openings 70SA to 70SF are provided in the third element insulating layer 72. The first opening 70SA is an opening that exposes the first transformer pad 141. The second opening 70SB is an opening that exposes the second transformer pad 142. The third opening 70SC is an opening that exposes the first end 131A of the first inner coil 131. The fourth opening 70SD is an opening that exposes the second end 131B of the first inner coil 131. The fifth opening 70SE is an opening that exposes the first end 132A of the second inner coil 132. The sixth opening 70SF is an opening that exposes the second end 132B of the second inner coil 132.

[0168] The first transformer pad 141 and the second transformer pad 142 are pads electrically connected to the outer coil 120. The first transformer pad 141 is electrically connected to a first end 121A of the first outer coil 121 of the outer coil 120. The second transformer pad 142 is electrically connected to a first end 122A of the second outer coil 122 of the outer coil 120. In one example, the first transformer pad 141 and the second transformer pad 142 are disposed at the same position as the outer coil 120 in the Z direction.

[0169] The third to sixth transformer pads 143 to 146 may be pads electrically connected to the inner coil 130. In the third embodiment, the third to sixth transformer pads 143 to 146 are formed by a part of the inner coil 130. More specifically, the third transformer pad 143 is formed by exposing the first end 131A of the first inner coil 131 of the inner coil 130 in the Z direction from the third opening 70SC of the third element insulating layer 72. The fourth transformer pad 144 is formed by exposing the second end 131B of the first inner coil 131 in the Z direction from the fourth opening 70SD of the third element insulating layer 72. The fifth transformer pad 145 is formed by exposing the first end 132A of the second inner coil 132 of the inner coil 130 in the Z direction from the fifth opening 70SE of the third element insulating layer 72. The sixth transformer pad 146 is configured by exposing the second end 132B of the second inner coil 132 from the sixth opening 70SF of the third element insulating layer 72 in the Z direction.

[0170] 15 and 17, the transformer chip 70 includes a first wiring section 150 and a second wiring section 160. The first wiring section 150 is a wiring that electrically connects the first end 121A of the first outer coil 121 and the first transformer pad 141. The second wiring section 160 is a wiring that electrically connects the first end 122A of the second outer coil 122 and the second transformer pad 142. The first wiring section 150 and the second wiring section 160 are formed of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W.

[0171] As shown in FIG. 15 and FIG. 16, the first wiring section 150 includes a connection wiring 151 and vias 152 and 153. The connection wiring 151 is disposed closer to the third semiconductor substrate 71 than the first outer coil 121 in the Z direction. The connection wiring 151 extends in the X direction. The connection wiring 151 includes a first end 151A and a second end 151B as both ends in the X direction. The connection wiring 151 extends from the first end 121A of the first outer coil 121 to the first transformer pad 141 in a plan view. The first end 151A of the connection wiring 151 is disposed at a position overlapping the first end 121A of the first outer coil 121 in a plan view. The first end 151A is electrically connected to the first end 121A of the first outer coil 121 by the via 152. The second end 151B of the connection wiring 151 is disposed at a position overlapping the first transformer pad 141 in a plan view. The second end 151B is electrically connected to the first transformer pad 141 by a via 153.

[0172] 15 and 17, the second wiring section 160 includes a connection wiring 161 and vias 162 and 163. The connection wiring 161 and the vias 162 and 163 are arranged in the same manner as the connection wiring 151 and the vias 152 and 153 of the first wiring section 150. The connection wiring 161 includes a first end 161A and a second end 161B, similar to the connection wiring 151. The first end 161A of the connection wiring 161 is electrically connected to the first end 122A of the second outer coil 122 by the via 162, and the second end 161B of the connection wiring 161 is electrically connected to the second transformer pad 142 by the via 163.

[0173] 14 and 15, the first transformer pad 141 and the second transformer pad 142 are connected to the two intermediate pads 56 of the first chip 50 by the first transmission wire WT1 and the second transmission wire WT2, respectively. Each of the first transmission wire WT1 and the second transmission wire WT2 is provided outside the transformer chip 70. In one example, in a plan view, the length of the first transmission wire WT1 and the length of the second transmission wire WT2 are equal to each other.

[0174] Since one of the two intermediate pads 56 is electrically connected to the transmission circuit 21, for example, the first transformer pad 141 formed by the first end 121A of the first outer coil 121 of the outer coil 120 is electrically connected to the transmission circuit 21 (see FIG. 13) by the first transmission wire WT1. Therefore, it can be said that the first outer coil 121 is electrically connected to the first chip 50 by the first transmission wire WT1. The other of the two intermediate pads 56 is connected to the ground GND1 (see FIG. 13). Therefore, for example, the second transformer pad 142 formed by the first end 122A of the second outer coil 122 of the outer coil 120 is electrically connected to the ground GND1 by the second transmission wire WT2. Therefore, it can be said that the second outer coil 122 is electrically connected to the first chip 50 by the second transmission wire WT2. Here, the first transmission wire WT1 is an example of a "first chip connecting wire", and the second transmission wire WT2 is an example of a "second chip connecting wire".

[0175] The first end 131A of the first inner coil 131 and the first end 132A of the second inner coil 132 of the inner coil 130 are electrically connected by a wire WC. As a result, when a current generated in the first inner coil 131 flows through the wire WC to the second inner coil 132, the direction of the current is the same as the direction of the current generated in the second inner coil 132. Here, the wire WC is an example of a "coil connecting wire."

[0176] The fourth transformer pad 144 and the sixth transformer pad 146 are individually connected to the two intermediate pads 66 of the second chip 60 by a first receiver wire WR1 and a second receiver wire WR2. Each of the first receiver wire WR1 and the second receiver wire WR2 is provided outside the transformer chip 70. In one example, in a plan view, the length of the first receiver wire WR1 and the length of the second receiver wire WR2 are equal to each other.

[0177] Since one of the two intermediate pads 66 is electrically connected to the receiving circuit 31, for example, the fourth transformer pad 144 formed by the second end 131B of the first inner coil 131 is electrically connected to the receiving circuit 31 (see FIG. 13) by the first receiving wire WR1. Therefore, it can be said that the first inner coil 131 is electrically connected to the second chip 60 by the first receiving wire WR1. The other of the two intermediate pads 66 is connected to the ground GND2 (see FIG. 13). Therefore, for example, the sixth transformer pad 146 formed by the second end 132B of the second inner coil 132 is electrically connected to the ground GND2. Therefore, it can be said that the second inner coil 132 is electrically connected to the second chip 60 by the second receiving wire WR2. Here, the first receiving wire WR1 is an example of a "third chip connecting wire", and the second receiving wire WR2 is an example of a "fourth chip connecting wire".

[0178] [Effects of the third embodiment] According to the semiconductor device 10 of the third embodiment, the following effects can be obtained. (3-1) The outer coil 120 includes a first outer coil 121 and a second outer coil 122 each having a first end 121A, 122A and a second end 121B, 122B. The second end 121B of the first outer coil 121 and the second end 122B of the second outer coil 122 are connected to each other. The first outer coil 121 and the second outer coil 122 are configured such that when a current flows from a first end of one of the first outer coil 121 and the second outer coil 122 to a first end of the other outer coil, magnetic fluxes in opposite directions are generated. The inner coil 130 includes a first inner coil 131 and a second inner coil 132 each having a first end 131A, 132A and a second end 131B, 132B. In a planar view, the first inner coil 131 is positioned inside the first outer coil 121 so as not to overlap with the first outer coil 121, and the second inner coil 132 is positioned inside the second outer coil 122 so as not to overlap with the second outer coil 122.

[0179] According to this configuration, it is possible to suppress the spread of the magnetic flux generated by the outer coil 120. This makes it possible to increase the amount of magnetic flux crossing the inner coil 130. Therefore, it is possible to improve the efficiency of the magnetic coupling between the outer coil 120 and the inner coil 130. As a result, it is possible to improve the transfer characteristics between the outer coil 120 and the inner coil 130.

[0180] (3-2) The first inner coil 131 and the second inner coil 132 are connected to each other by a wire WC provided outside the transformer chip 70. This configuration can simplify the configuration of the transformer chip 70 compared to a configuration in which the first inner coil 131 and the second inner coil 132 are electrically connected by wiring provided in the transformer chip 70. In other words, since a layer for providing wiring is not required in the third element insulating layer 72, a dedicated mask for providing wiring is not required when manufacturing the third element insulating layer 72. Therefore, the manufacturing process of the transformer chip 70 can be simplified, and the cost of the transformer chip 70 can be reduced.

[0181] (3-3) The first outer coil 121 is electrically connected to the first chip 50 by a first transmission side wire WT1 provided outside the transformer chip 70. The second outer coil 122 is electrically connected to the first chip 50 by a second transmission side wire WT2 provided outside the transformer chip 70.

[0182] According to this configuration, the connection structure between the first outer coil 121 and the first chip 50 can be simplified, for example, compared to a configuration in which the first outer coil 121 and the first chip 50 are connected by wiring provided in the transformer chip 70. Also, the connection structure between the second outer coil 122 and the first chip 50 can be simplified, for example, compared to a configuration in which the second outer coil 122 and the first chip 50 are connected by wiring provided in the transformer chip 70. In addition, since it is not necessary to position the arrangement position of the transformer chip 70 with high precision relative to the first chip 50, the semiconductor device 10 can be easily manufactured.

[0183] (3-4) Each of the first outer coil 121, the second outer coil 122, the first inner coil 131, and the second inner coil 132 is disposed closer to the third element surface 72S of the third element insulating layer 72 in the Z direction.

[0184] According to this configuration, the distance between each of the first outer coil 121, the second outer coil 122, the first inner coil 131, and the second inner coil 132 and the third semiconductor substrate 71 in the Z direction can be made larger than in a configuration in which two coils are arranged opposite each other in the Z direction. Therefore, the magnetic flux generated in the first outer coil 121, the second outer coil 122, the first inner coil 131, and the second inner coil 132 is less likely to pass through the third semiconductor substrate 71. This makes it possible to suppress the generation of eddy currents caused by the magnetic flux penetrating the third semiconductor substrate 71. Therefore, it is possible to suppress the decrease in efficiency of magnetic coupling caused by eddy currents.

[0185] (3-5) The first outer coil 121, the second outer coil 122, the first inner coil 131, and the second inner coil 132 are disposed at the same positions relative to one another in the Z direction. According to this configuration, the first outer coil 121, the second outer coil 122, the first inner coil 131, and the second inner coil 132 can be formed using a common mask when manufacturing the transformer chip 70. Therefore, compared to a configuration in which the first outer coil 121, the second outer coil 122, the first inner coil 131, and the second inner coil 132 are disposed at different positions in the Z direction, the manufacturing process of the transformer chip 70 can be simplified, and the manufacturing cost of the transformer chip 70 can be reduced.

[0186] <Example of change> The above-described embodiments can be modified as follows: The following modified examples can be combined with each other as long as no technical contradiction occurs.

[0187] [Combination of embodiments] The first and second embodiments may be implemented in combination with each other. The second and third embodiments may be implemented in combination with each other.

[0188] [Modification of the first embodiment] In the first embodiment, the configuration of the transformer chip 70 can be modified as desired. The transformer chip 70 may be modified, for example, like the transformer chips 70 of first to fourth modified examples shown in Figs.

[0189] (First modified example) 18, the transformer chip 70 of the first modified example includes two outer coils 100 arranged spaced apart in the Z direction in the third element insulating layer 72, and a via 171 connecting the two outer coils 100. The two outer coils 100 are connected in parallel by the via 171. The two outer coils 100 are arranged in positions overlapping each other in a plan view. The wiring portion 77 is arranged closer to the third semiconductor substrate 71 than the two outer coils 100.

[0190] According to this configuration, it is possible to reduce the wiring resistance value of the outer coil 100 by connecting two outer coils 100 in parallel. Note that the number of outer coils 100 may be three or more.

[0191] Moreover, the transformer chip 70 of the first modified example includes two inner coils 110 arranged in the third element insulating layer 72 at a distance from each other in the Z direction, and a via 172 connecting the two inner coils 110. The two inner coils 110 are connected in parallel by the via 172. The two inner coils 110 are arranged in positions overlapping each other in a plan view. With this configuration, the wiring resistance value of the inner coil 110 can be reduced by connecting the two inner coils 110 in parallel. The number of inner coils 110 may be three or more.

[0192] (Second modified example) As shown in FIG. 19 and FIG. 20, the transformer chip 70 of the second modified example includes an outer coil 100, an outer coil 103 connected to the outer coil 100, and a via 104 connecting the outer coils 100 and 103. The outer coil 103 is arranged so as to overlap the outer coil 100 in a plan view. The outer coil 103 includes coil portions 103A and 103B arranged to be spaced apart in the Z direction. The coil portions 103A and 103B are connected in series between the outer coil 100 and the wiring portion 77 by the via 104. More specifically, the coil portion 103B is arranged closer to the outer coil 100 than the coil portion 103A in the Z direction. The coil portion 103B is connected in series to the outer coil 100. The coil portion 103B is electrically connected to the first end 101 of the outer coil 100 by the via 104. The coil portion 103A is connected in series to the coil portion 103B. The coil portion 103A is electrically connected to the wiring portion 77. That is, the coil portion 103A is electrically connected to the first transformer pad 75A. On the other hand, the second end 102 of the outer coil 100 constitutes the first transformer pad 75B.

[0193] In the transformer chip 70 of the second modified example, the outer coil 103 is connected between the wiring portion 77 and the outer coil 100. Therefore, the number of turns of the outer coil consisting of the outer coil 100 and the outer coil 103 can be increased. This makes it possible to increase the amount of magnetic flux generated by this outer coil.

[0194] The coil portions 103A and 103B of the outer coil 103 may be connected in parallel. Also, a plurality of outer coils 100 may be provided as in a first modified example shown in FIG. 18. In this case, the plurality of outer coils 100 may be connected in parallel. In this way, by connecting the outer coil 100 and the outer coil 103 in parallel, it is possible to increase the number of turns and suppress an increase in the wiring resistance value.

[0195] As shown in FIG. 19, in the transformer chip 70 of the second modified example, the inner coil 110 is disposed at the same position in the Z direction as the coil portion 103B of the outer coil 103. The configuration of the inner coil 110 can be changed arbitrarily. The position of the inner coil 110 in the Z direction can be changed arbitrarily. In one example, the inner coil 110 may be disposed at the same position in the Z direction as the outer coil 100. In one example, the inner coil 110 may be disposed at the same position in the Z direction as the coil portion 103A of the outer coil 103.

[0196] A first end 111 of the inner coil 110 is electrically connected to the second transformer pad 76A by a via 172. The second transformer pad 76A is disposed closer to the chip surface 70S than the inner coil 110 in the Z direction. In one example, the second transformer pad 76A is disposed in the same position as the outer coil 100.

[0197] (Third modified example) As shown in Fig. 21, the transformer chip 70 of the third modified example is different from the transformer chip 70 of the second modified example shown in Fig. 19 in that the coil portion 103B of the outer coil 103 is arranged so as not to overlap with both the outer coil 100 and the coil portion 103A in a plan view. By arranging the outer coil 100 and the coil portions 103A and 103B in this way, the facing area between the outer coil 100 and the coil portion 103A and the coil portion 103B in the Z direction is reduced. Therefore, the capacitance of the parasitic capacitor caused by this facing area can be reduced.

[0198] (Fourth modified example) 22, in the transformer chip 70 of the fourth modified example, the inner coil 110 may be disposed at a position different from that of the outer coil 100 in the Z direction. In the example shown in FIG. 22, the inner coil 110 is disposed closer to the third semiconductor substrate 71 than the outer coil 100 in the Z direction. With this configuration, the opposing area between the outer coil 100 and the inner coil 110 in the direction perpendicular to the Z direction is reduced. Therefore, the capacitance of the parasitic capacitor caused by this opposing area can be reduced.

[0199] In the transformer chip 70 of the fourth modified example, the outer coil 100 may be disposed closer to the third semiconductor substrate 71 than the inner coil 110 in the Z direction. In this case, the inner coil 110 is disposed, for example, in the uppermost insulator 72U of the insulating layer stack structure 72T of the third element insulating layer 72. The inner coil 110 may also be disposed, for example, in the insulator 72U immediately below the uppermost insulator 72U of the insulating layer stack structure 72T.

[0200] The shapes of the outer coil 100 and the inner coil 110 in a plan view can be changed as desired. In one example, the outer coil 100 and the inner coil 110 may be formed in a rectangular shape in a plan view. In one example, the outer coil 100 and the inner coil 110 may be formed in a rectangular shape with rounded corners in a circular arc shape in a plan view. In one example, the outer coil 100 and the inner coil 110 may be formed in an elliptical shape in a plan view.

[0201] [Modification of the second embodiment] In the second embodiment, the configuration of the third element insulating layer 72 of the transformer chip 70 can be changed arbitrarily. In one example, as shown in FIG. 23, the first insulating film 72P of the specific insulator 72UA includes a plurality of recesses 72PC that open toward the cover insulating film 72UB. The plurality of recesses 72PC are arranged at a distance from each other in a direction perpendicular to the Z direction. In one example, each recess 72PC is formed in a ring shape in a plan view. In one example, the plurality of recesses 72PC are formed in a concentric shape in a plan view. In one example, the centers of the plurality of recesses 72PC are concentric with, for example, the center of the outer coil 100 and the center of the inner coil 110. The second insulating film 72Q of the specific insulator 72UA is embedded in the plurality of recesses 72PC. The cover insulating film 72UB includes a plurality of cover side recesses 72PD that open toward the first insulating film 72P of the specific insulator 72UA. The plurality of cover side recesses 72PD are arranged at a distance from each other in a surface direction perpendicular to the Z direction. In one example, the cover side recesses 72PD are formed concentrically in a plan view. The centers of the cover side recesses 72PD are concentric with the centers of the outer coil 100 and the inner coil 110, for example. The second insulating film 72Q of the specific insulator 72UA is embedded in the cover side recesses 72PD. This configuration provides the same effects as those of (2-1) and (2-2) of the second embodiment.

[0202] In the second embodiment, the number of isolation insulating films 78A and the number of cover-side isolation insulating films 78B can be changed arbitrarily. In one example, the number of isolation insulating films 78A may be one. In one example, the number of cover-side isolation insulating films 78B may be one. In another example, the number of isolation insulating films 78A may be different from the number of cover-side isolation insulating films 78B.

[0203] In the second embodiment, the multiple isolation insulating films 78A may be disposed at positions different from the multiple cover side isolation insulating films 78B. That is, in a plan view, the multiple isolation insulating films 78A may be disposed at positions not overlapping with the multiple cover side isolation insulating films 78B. In one example, in a plan view, the multiple isolation insulating films 78A may be disposed at positions partially overlapping with the multiple cover side isolation insulating films 78B.

[0204] In the second embodiment, it is sufficient that the isolation insulating film 78A penetrates the first insulating film 72P of the specific insulator 72UA in the Z direction, and the concave shape of the second insulating film 72Q may be omitted. In the second embodiment, the cover-side isolation insulating film 78B only needs to penetrate the cover insulating film 72UB in the Z direction, and the concave shape of the second insulating film 72Q of the specific insulator 72UA may be omitted.

[0205] [Modification of the third embodiment] In the third embodiment, the configuration of the transformer chip 70 can be arbitrarily modified. The transformer chip 70 may be modified, for example, as in the first to fifth modified examples shown in Figs. 24 to 30. Figs. 24, 25, 27, and 28 are schematic cross-sectional views of the transformer chip 70. The cross-sectional positions of Figs. 24, 25, 27, and 28 are the same as the cross-sectional position of the line F16-F16 in Fig. 15 of the third embodiment. Fig. 26 is a schematic exploded perspective view of a portion of the transformer chip 70. Figs. 29 and 30 are schematic planar views of the transformer chip 70. For convenience, the outer coil 120 and the inner coil 130 are shown by solid lines in Figs. 29 and 30.

[0206] (First modified example) As shown in FIG. 24, the transformer chip 70 of the first modified example includes two outer coils 120 arranged at a distance from each other in the Z direction, and vias 181 and 182 connecting the two outer coils 120. The two first outer coils 121 arranged at a distance from each other in the Z direction are connected in parallel by the vias 181. The two second outer coils 122 arranged at a distance from each other in the Z direction are connected in parallel by the vias 182. According to this configuration, the two first outer coils 121 are connected in parallel, and the two second outer coils 122 are connected in parallel, thereby reducing the wiring resistance value of the outer coil 120. Note that three or more outer coils 120 may be provided at a distance from each other in the Z direction.

[0207] The inner coil 130 includes two inner coils 130 arranged at a distance from each other in the Z direction, and vias 183, 184 connecting the two inner coils 130. The first inner coils 131 arranged at a distance from each other in the Z direction are connected in parallel by the vias 183. The second inner coils 132 arranged at a distance from each other in the Z direction are connected in parallel by the vias 184. With this configuration, the two first inner coils 131 are connected in parallel, and the two second inner coils 132 are connected in parallel, thereby reducing the wiring resistance value of the inner coil 130. Note that three or more inner coils 130 may be provided at a distance from each other in the Z direction.

[0208] (Second modified example) As shown in Figures 25 and 26, in the second modified example transformer chip 70, the outer coil 120 includes a first outer coil 121 and a second outer coil 122, a third outer coil 123 connected to the first outer coil 121, and a fourth outer coil 124 connected to the second outer coil 122.

[0209] The third outer coil 123 is disposed so as to overlap the first outer coil 121 in a plan view. The third outer coil 123 includes coil portions 123A and 123B disposed spaced apart from each other in the Z direction. The coil portions 123A and 123B are connected in series between the first end 121A of the first outer coil 121 and the first wiring portion 150.

[0210] The fourth outer coil 124 is disposed so as to overlap with the second outer coil 122 in a plan view. The fourth outer coil 124 includes coil portions 124A and 124B disposed spaced apart from each other in the Z direction. The coil portions 124A and 124B are connected in series between the first end 122A of the second outer coil 122 and the second wiring portion 160.

[0211] In the transformer chip 70 of the second modification, the third outer coil 123 and the first outer coil 121 are connected in series between the first wiring section 150 and the second outer coil 122. In addition, the second outer coil 122 and the fourth outer coil 124 are connected in series between the first outer coil 121 and the second wiring section 160. Therefore, the number of turns of the outer coil 120 disposed outside each of the first inner coil 131 and the second inner coil 132 can be increased. Therefore, the amount of magnetic flux generated by the outer coil 120 can be increased.

[0212] The third outer coil 123 (coil portions 123A, 123B) arranged at a distance from each other in the Z direction may be connected in parallel. Similarly, the fourth outer coil 124 (coil portions 124A, 124B) arranged at a distance from each other in the Z direction may be connected in parallel. In this way, by connecting the third outer coil 123 and the fourth outer coil 124 in parallel, the number of turns of the outer coil 120 can be increased and an increase in the wiring resistance value can be suppressed.

[0213] As shown in FIG. 25, in the transformer chip 70 of the second modification, the inner coil 130 is disposed at the same position in the Z direction as the coil portion 123B of the third outer coil 123 and the coil portion 124B of the fourth outer coil 124. The configuration of the inner coil 130 can be changed arbitrarily. The position of the inner coil 130 in the Z direction can be changed arbitrarily. In one example, the inner coil 130 may be disposed at the same position as the outer coil 120 in the Z direction. In one example, the inner coil 130 may be disposed at the same position in the Z direction as the coil portion 123A of the third outer coil 123 and the coil portion 124A of the fourth outer coil 124.

[0214] (Third modified example) The transformer chip 70 of the third modified example shown in Fig. 27 is different from the transformer chip 70 of the second modified example shown in Fig. 25 in that the coil portion 123B of the third outer coil 123 is arranged so as not to overlap the first outer coil 121, the second outer coil 122, and the coil portion 123A in a plan view. By arranging the first outer coil 121 and the third outer coil 123 in this manner, the facing area between the coil portion 123B and the first outer coil 121, the second outer coil 122, and the coil portion 123A in the Z direction is reduced. Therefore, the capacitance of the parasitic capacitor caused by this facing area can be reduced.

[0215] (Fourth modified example) In the transformer chip 70 of the fourth modified example shown in FIG. 28, the first inner coil 131 and the second inner coil 132 of the inner coil 130 are disposed at positions different from the first outer coil 121 and the second outer coil 122 of the outer coil 120 in the Z direction. In one example, the first inner coil 131 and the second inner coil 132 are disposed closer to the third semiconductor substrate 71 than the first outer coil 121 and the second outer coil 122 in the Z direction. With this configuration, the opposing area between the inner coil 130 and the outer coil 120 in the direction perpendicular to the Z direction is reduced. Therefore, the capacitance of the parasitic capacitor caused by this opposing area can be reduced.

[0216] In the transformer chip 70 of the fourth modified example, the outer coil 120 may be disposed closer to the third semiconductor substrate 71 than the inner coil 130 in the Z direction. In this case, the inner coil 130 is disposed, for example, in the uppermost insulator 72U of the insulating layer stack structure 72T of the third element insulating layer 72. The inner coil 130 may also be disposed, for example, in the insulator 72U immediately below the uppermost insulator 72U of the insulating layer stack structure 72T.

[0217] (Fifth modified example) The shapes of the outer coil 120 and the inner coil 130 in plan view can be changed arbitrarily. In one example, as shown in FIG. 29, each of the outer coil 120 and the inner coil 130 may be formed in a rectangular shape in plan view. In another example, as shown in FIG. 30, each of the outer coil 120 and the inner coil 130 may be formed in a rectangular shape with rounded corners in a circular arc shape in plan view. Although not shown, each of the outer coil 120 and the inner coil 130 may be formed in an elliptical shape in plan view.

[0218] The positional relationship in the Z direction between the first outer coil 121 and the second outer coil 122 of the outer coil 120 can be changed arbitrarily. In one example, the first outer coil 121 and the second outer coil 122 may be disposed at different positions in the Z direction. In this case, the second end 121B of the first outer coil 121 and the second end 122B of the second outer coil 122 may be formed to overlap each other in a plan view. The second end 121B of the first outer coil 121 and the second end 122B of the second outer coil 122 may be directly electrically connected to each other.

[0219] The positional relationship in the Z direction between the first inner coil 131 and the second inner coil 132 of the inner coil 130 can be changed arbitrarily. In one example, the first inner coil 131 and the second inner coil 132 may be disposed at different positions from each other in the Z direction.

[0220] The first end 131A of the first inner coil 131 and the first end 132A of the second inner coil 132 of the inner coil 130 may be connected to the second chip 60. The second chip 60 may include a pad connected to the first end 131A of the first inner coil 131 of the inner coil 130 and a pad connected to the first end 132A of the second inner coil 132. The second circuit 30 of the second chip 60 may include a first receiving circuit that receives a signal transmitted by the first inner coil 131 and a second receiving circuit that receives a signal transmitted by the second inner coil 132.

[0221] A configuration in which the third embodiment is combined with the second embodiment will be described with reference to Fig. 31 and Fig. 32. Fig. 31 shows an enlarged cross-sectional structure of the first outer coil 121, the first inner coil 131, and the surrounding areas. Fig. 32 shows an enlarged cross-sectional structure of the second outer coil 122, the second inner coil 132, and the surrounding areas.

[0222] As shown in FIG. 31, a plurality of first grooves 72V1 are provided in a portion between the first inner coil 131 and the first outer coil 121 of the first insulating film 72P of the specific insulator 72UA in which the first inner coil 131, the second inner coil 132 (see FIG. 32), the first outer coil 121, and the second outer coil 122 (see FIG. 32) are provided. The plurality of first grooves 72V1 are provided at a distance from each other in a direction perpendicular to the Z direction. Each of the first grooves 72V1 is formed in an annular shape in a planar view. In one example, the plurality of first grooves 72V1 are formed in a concentric shape in a planar view. In one example, the centers of the plurality of first grooves 72V1 are concentric with the center of the first outer coil 121 and the center of the first inner coil 131. In this manner, the first insulating film 72P of the specific insulator 72UA is provided between the first outer coil 121 and the first inner coil 131, separated from each other in a direction perpendicular to the Z direction, by the multiple first grooves 72V1.

[0223] Each first groove 72V1 is a rectangular groove that penetrates the first insulating film 72P of the specific insulator 72UA in the Z direction and forms a concave shape in the second insulating film 72QA directly below the specific insulator 72UA. The second insulating film 72Q of the specific insulator 72UA enters each first groove 72V1. This forms a plurality of first isolation insulating films 78A1. In this way, the portion of the first insulating film 72P of the specific insulator 72UA between the first inner coil 131 and the first outer coil 121 includes a plurality of first isolation insulating films 78A1 that are spaced apart from each other in a direction perpendicular to the Z direction. That is, the first insulating film 72P between the first outer coil 121 and the first inner coil 131 is separated by the second insulating film 72Q (first isolation insulating film 78A1) that has a smaller dielectric constant than the first insulating film 72P. Since each first groove 72V1 is formed in an annular shape, each first isolation insulating film 78A1 provided in each first groove 72V1 is formed in an annular shape in a planar view. When a plurality of first grooves 72V1 are formed in a concentric shape in a planar view, the plurality of first isolation insulating films 78A1 are formed in a concentric shape in a planar view. In this manner, the first insulating film 72P and the second insulating film 72Q are alternately arranged between the first outer coil 121 and the first inner coil 131 in a direction perpendicular to the Z direction.

[0224] As shown in FIG. 32, a plurality of second grooves 72V2 are provided in a portion of the first insulating film 72P of the specific insulator 72UA between the second inner coil 132 and the second outer coil 122. The plurality of second grooves 72V2 are provided at a distance from each other in a direction perpendicular to the Z direction. Each of the second grooves 72V2 is formed in an annular shape in a plan view. In one example, the plurality of second grooves 72V2 are formed in a concentric shape in a plan view. In one example, the centers of the plurality of second grooves 72V2 are concentric with the centers of the second outer coil 122 and the second inner coil 132. In this way, the plurality of second grooves 72V2 allow the first insulating film 72P of the specific insulator 72UA to be provided at a distance from each other in a direction perpendicular to the Z direction between the second outer coil 122 and the second inner coil 132.

[0225] Each second groove 72V2 is a rectangular groove that penetrates the first insulating film 72P of the specific insulator 72UA in the Z direction and forms a concave shape in the second insulating film 72QA directly below the specific insulator 72UA. The second insulating film 72Q of the specific insulator 72UA enters each second groove 72V2. This forms a plurality of second isolation insulating films 78A2. In this manner, the portion of the first insulating film 72P of the specific insulator 72UA between the second inner coil 132 and the second outer coil 122 includes a plurality of second isolation insulating films 78A2 that are spaced apart from each other in a direction perpendicular to the Z direction. That is, the first insulating film 72P between the second outer coil 122 and the second inner coil 132 is separated by the second insulating film 72Q (second isolation insulating film 78A2) that has a smaller dielectric constant than the first insulating film 72P. Since each second groove 72V2 is formed in an annular shape, each second isolation insulating film 78A2 provided in each second groove 72V2 is formed in an annular shape in a planar view. When a plurality of second grooves 72V2 are formed in a concentric shape in a planar view, the plurality of second isolation insulating films 78A2 are formed in a concentric shape in a planar view. In this manner, the first insulating film 72P and the second insulating film 72Q are alternately arranged between the second outer coil 122 and the second inner coil 132 in a direction perpendicular to the Z direction.

[0226] As shown in FIG. 31, a plurality of first grooves 72W1 are provided in a portion of the cover insulating film 72UB that contacts the second insulating film 72Q of the specific insulator 72UA between the first inner coil 131 and the first outer coil 121. The plurality of first grooves 72W1 are provided at a distance from each other in a direction perpendicular to the Z direction. Each of the first grooves 72W1 is formed in an annular shape in a plan view. In one example, the plurality of first grooves 72W1 are formed in a concentric shape in a plan view. In one example, the centers of the plurality of first grooves 72W1 are concentric with the centers of the first outer coil 121 and the first inner coil 131. In this way, the cover insulating film 72UB is provided at a distance from each other in a direction perpendicular to the Z direction between the first outer coil 121 and the first inner coil 131 by the plurality of first grooves 72W1.

[0227] Each first groove 72W1 is a rectangular groove penetrating the cover insulating film 72UB in the Z direction and formed in a concave shape in the second insulating film 72Q of the specific insulator 72UA. The second insulating film 72QB on the cover insulating film 72UB is inserted into each first groove 72W1. This constitutes a plurality of first cover side isolation insulating films 78B1. In this manner, the portion of the cover insulating film 72UB between the first inner coil 131 and the first outer coil 121 includes a plurality of first cover side isolation insulating films 78B1 provided at a distance from each other in a direction perpendicular to the Z direction. That is, the cover insulating film 72UB between the first outer coil 121 and the first inner coil 131 is separated by the second insulating film 72Q (first cover side isolation insulating film 78B1) having a smaller dielectric constant than the first insulating film 72P. Since each first groove 72W1 is formed in an annular shape, each first cover side isolation insulating film 78B1 provided in each first groove 72W1 is formed in an annular shape in a plan view. When the first grooves 72W1 are formed concentrically in a plan view, the first cover side isolation insulating films 78B1 are formed concentrically in a plan view. In this manner, the first insulating films 72P and the second insulating films 72Q are alternately arranged between the first outer coil 121 and the first inner coil 131 in a direction perpendicular to the Z direction.

[0228] As shown in FIG. 32, a plurality of second grooves 72W2 are provided in a portion between the second inner coil 132 and the second outer coil 122 of the cover insulating film 72UB in contact with the second insulating film 72Q of the specific insulator 72UA. The plurality of second grooves 72W2 are provided at a distance from each other in a direction perpendicular to the Z direction. Each of the second grooves 72W2 is formed in an annular shape in a plan view. In one example, the plurality of second grooves 72W2 are formed in a concentric shape in a plan view. In one example, the centers of the plurality of second grooves 72W2 are concentric with the centers of the second outer coil 122 and the second inner coil 132. In this way, the plurality of second grooves 72W2 provide the cover insulating film 72UB at a distance from each other in a direction perpendicular to the Z direction between the second outer coil 122 and the second inner coil 132.

[0229] Each second groove 72W2 is a rectangular groove penetrating the cover insulating film 72UB in the Z direction and formed in the second insulating film 72Q of the specific insulator 72UA in a concave shape. The second insulating film 72QB on the cover insulating film 72UB is inserted into each second groove 72W2. This constitutes a plurality of second cover side isolation insulating films 78B2. In this manner, the portion of the cover insulating film 72UB between the second inner coil 132 and the second outer coil 122 includes a plurality of second cover side isolation insulating films 78B2 provided at a distance from each other in a direction perpendicular to the Z direction. That is, the cover insulating film 72UB between the second outer coil 122 and the second inner coil 132 is separated by the second insulating film 72Q (second cover side isolation insulating film 78B2) having a smaller dielectric constant than the first insulating film 72P. Since each second groove 72W2 is formed in an annular shape, each second cover side isolation insulating film 78B2 provided in each second groove 72W2 is formed in an annular shape in a plan view. When the second grooves 72W2 are formed concentrically in a plan view, the second cover side isolation insulating films 78B2 are formed concentrically in a plan view. In this manner, the first insulating films 72P and the second insulating films 72Q are alternately arranged between the second outer coil 122 and the second inner coil 132 in a direction perpendicular to the Z direction.

[0230] In one example, the width dimension of each first groove 72W1 is equal to the width dimension of each first groove 72V1. Moreover, the width dimensions of the multiple first grooves 72W1 are equal to each other. Moreover, the width dimensions of the multiple first grooves 72V1 are equal to each other. In one example, the width dimension of each second groove 72W2 is equal to the width dimension of each second groove 72V2. Moreover, the width dimensions of the multiple second grooves 72W2 are equal to each other. Moreover, the width dimensions of the multiple second grooves 72V2 are equal to each other. Here, the width dimension of each first groove 72V1, 72W1 can be defined by the distance between the side surfaces constituting each first groove 72V1, 72W1 in a direction perpendicular to the Z direction. The width dimension of each second groove 72V2, 72W2 can be defined by the distance between the side surfaces constituting each second groove 72V2, 72W2 in a direction perpendicular to the Z direction.

[0231] When the width of each first groove 72W1 is equal to the width of each first groove 72V1, the width of each first cover side isolation insulating film 78B1 is equal to the width of each first isolation insulating film 78A1. When the widths of the first grooves 72W1 are equal to each other, the widths of the first cover side isolation insulating films 78B1 are equal to each other. When the widths of the first grooves 72V1 are equal to each other, the widths of the first isolation insulating films 78A1 are equal to each other. Here, the width of the first isolation insulating film 78A1 can be defined by the distance between the side surfaces of the first isolation insulating film 78A1 that contact the side surfaces constituting the first groove 72V1 in the direction perpendicular to the Z direction. The width of the first cover side isolation insulating film 78B1 can be defined by the distance between the side surfaces of the first cover side isolation insulating film 78B1 that contact the side surfaces constituting the first groove 72W1 in the direction perpendicular to the Z direction.

[0232] When the width of each second groove 72W2 is equal to the width of each second groove 72V2, the width of each second cover side isolation insulating film 78B2 is equal to the width of each second isolation insulating film 78A2. When the widths of the second grooves 72W2 are equal to each other, the widths of the second cover side isolation insulating films 78B2 are equal to each other. When the widths of the second grooves 72V2 are equal to each other, the widths of the second isolation insulating films 78A2 are equal to each other. Here, the width of the second isolation insulating film 78A2 can be defined by the distance between the side surfaces of the second isolation insulating film 78A2 that contact the side surfaces constituting the second groove 72V2 in the direction perpendicular to the Z direction. The width of the second cover side isolation insulating film 78B2 can be defined by the distance between the side surfaces of the second cover side isolation insulating film 78B2 that contact the side surfaces constituting the second groove 72W2 in the direction perpendicular to the Z direction.

[0233] According to this configuration, in the portion of the first insulating film 72P of the specific insulator 72UA between the first inner coil 131 and the first outer coil 121, a plurality of first isolation insulating films 78A1 and the second insulating film 72Q are alternately arranged. Therefore, the longitudinal distance between the first inner coil 131 and the first outer coil 121 can be made large. In the portion of the first insulating film 72P of the specific insulator 72UA between the second inner coil 132 and the second outer coil 122, a plurality of second isolation insulating films 78A2 and the second insulating film 72Q are alternately arranged. Therefore, the longitudinal distance between the second inner coil 132 and the second outer coil 122 can be made large.

[0234] In addition, in a portion of the cover insulating film 72UB between the first inner coil 131 and the first outer coil 121, a plurality of first cover side isolation insulating films 78B1 and the second insulating film 72Q are alternately arranged. Therefore, the creeping distance between the first inner coil 131 and the first outer coil 121 can be made large. In a portion of the cover insulating film 72UB between the second inner coil 132 and the second outer coil 122, a plurality of second cover side isolation insulating films 78B2 and the second insulating film 72Q are alternately arranged. Therefore, the creeping distance between the second inner coil 132 and the second outer coil 122 can be made large. Therefore, the dielectric strength of the semiconductor device 10 can be improved while suppressing the size increase of the transformer chip 70.

[0235] The number of the first grooves 72V1, 72W1 can be changed arbitrarily. In addition, in the modification shown in FIG. 31 and FIG. 32, the first grooves 72V1, 72W1 are arranged at positions where they overlap each other in a plan view, but this is not limited thereto. The first grooves 72V1, 72W1 may be arranged at positions different from each other in a plan view. In other words, the number of the first isolation insulating films 78A1 and the number of the first cover side isolation insulating films 78B1 can be changed arbitrarily. In addition, in the modification shown in FIG. 31 and FIG. 32, the first isolation insulating films 78A1 and the first cover side isolation insulating films 78B1 are arranged at positions where they overlap each other in a plan view, but this is not limited thereto. The first isolation insulating films 78A1 and the first cover side isolation insulating films 78B1 may be arranged at positions different from each other in a plan view.

[0236] The number of the second grooves 72V2, 72W2 can be changed arbitrarily. In the modification shown in FIG. 31 and FIG. 32, the second grooves 72V2, 72W2 are arranged at positions where they overlap each other in a plan view, but this is not limited thereto. The second grooves 72V2, 72W2 may be arranged at positions different from each other in a plan view. In other words, the number of the second isolation insulating films 78A2 and the number of the second cover side isolation insulating films 78B2 can be changed arbitrarily. In the modification shown in FIG. 31 and FIG. 32, the second isolation insulating films 78A2 and the second cover side isolation insulating films 78B2 are arranged at positions where they overlap each other in a plan view, but this is not limited thereto. The second isolation insulating films 78A2 and the second cover side isolation insulating films 78B2 may be arranged at positions different from each other in a plan view.

[0237] The widths of the first grooves 72V1 and 72W1 can be changed arbitrarily. In one example, the widths of the first grooves 72V1 and the first grooves 72W1 may be different from each other. That is, the widths of the first isolation insulating film 78A1 and the first cover-side isolation insulating film 78B1 may be different from each other. In one example, the width of at least one of the first grooves 72V1 may be different from the widths of the remaining first grooves 72V1. That is, the width of at least one of the first isolation insulating films 78A1 may be different from the widths of the remaining first isolation insulating films 78A1. In one example, the width of at least one of the first grooves 72W1 may be different from the widths of the remaining first grooves 72W1. That is, at least one of the first cover side isolation insulating films 78B1 may have a width dimension different from that of the remaining first cover side isolation insulating films 78B1. The shape of the first grooves 72V1 and 72W1 is not limited to a rectangular recessed shape and may be changed as desired. In one example, the first grooves 72V1 and 72W1 may be V-shaped.

[0238] The widths of the second grooves 72V2 and 72W2 can be changed arbitrarily. In one example, the widths of the second grooves 72V2 and 72W2 may be different from each other. That is, the widths of the second isolation insulating film 78A2 and the second cover-side isolation insulating film 78B2 may be different from each other. In one example, the width of at least one of the second grooves 72V2 may be different from the widths of the remaining second grooves 72V2. That is, the width of at least one of the second isolation insulating films 78A2 may be different from the widths of the remaining second isolation insulating films 78A2. In one example, the width of at least one of the second grooves 72W2 may be different from the widths of the remaining second grooves 72W2. That is, at least one of the second cover side isolation insulating films 78B2 may have a width dimension different from that of the remaining second cover side isolation insulating films 78B2. The shape of the second grooves 72V2 and 72W2 is not limited to a rectangular recessed shape and may be changed as desired. In one example, the second grooves 72V2 and 72W2 may be V-shaped.

[0239] The first isolation insulating film 78A1, the second isolation insulating film 78A2, the first cover side isolation insulating film 78B1, and the second cover side isolation insulating film 78B2 in the modified example shown in Figures 31 and 32 may be changed to the configurations shown in Figures 33 and 34. Figure 33 shows an enlarged cross-sectional structure of the first outer coil 121, the first inner coil 131, and the surrounding areas. Figure 34 shows an enlarged cross-sectional structure of the second outer coil 122, the second inner coil 132, and the surrounding areas.

[0240] As shown in FIG. 33, a portion of the first insulating film 72P of the specific insulator 72UA between the first inner coil 131 and the first outer coil 121 is provided with a plurality of first recesses 79A that open toward the cover insulating film 72UB. Each of the first recesses 79A is formed in an annular shape in a plan view. In one example, the plurality of first recesses 79A are formed in a concentric shape in a plan view. In one example, the centers of the plurality of first recesses 79A are concentric with the centers of the first inner coil 131 and the first outer coil 121. The second insulating film 72Q of the specific insulator 72UA is inserted into each of the first recesses 79A. As shown in FIG. 34, a portion of the first insulating film 72P of the specific insulator 72UA between the second inner coil 132 and the second outer coil 122 is provided with a plurality of second recesses 79B that open toward the cover insulating film 72UB. Each of the second recesses 79B is formed in an annular shape in a plan view. In one example, the plurality of second recesses 79B are formed in a concentric shape in a plan view. In one example, the centers of the multiple second recesses 79B are concentric with the center of the second inner coil 132 and the center of the second outer coil 122. The second insulating film 72Q of the specific insulator 72UA fills each of the second recesses 79B.

[0241] As shown in FIG. 33, a portion of the cover insulating film 72UB between the first inner coil 131 and the first outer coil 121 is provided with a plurality of first cover side recesses 79C that open toward the first insulating film 72P of the specific insulator 72UA. Each of the first cover side recesses 79C is formed in a ring shape in a plan view. In one example, the plurality of first cover side recesses 79C are formed in a concentric shape in a plan view. In one example, the centers of the plurality of first cover side recesses 79C are concentric with the centers of the first inner coil 131 and the first outer coil 121. The second insulating film 72Q of the specific insulator 72UA is inserted into each of the first cover side recesses 79C. As shown in FIG. 34, a portion of the cover insulating film 72UB between the second inner coil 132 and the second outer coil 122 is provided with a plurality of second cover side recesses 79D that open toward the first insulating film 72P of the specific insulator 72UA. Each of the second cover side recesses 79D is formed in a ring shape in a plan view. In one example, the second cover side recesses 79D are formed concentrically in a plan view. In one example, the centers of the second cover side recesses 79D are concentric with the centers of the second inner coil 132 and the second outer coil 122. The second insulating film 72Q of the specific insulator 72UA is inserted into each of the second cover side recesses 79D.

[0242] 31 and 32, this configuration allows the creepage distance between the first inner coil 131 and the first outer coil 121 to be increased by the multiple first recesses 79A and the multiple first cover side recesses 79C. Also, the creepage distance between the second inner coil 132 and the second outer coil 122 can be increased by the multiple second recesses 79B and the multiple second cover side recesses 79D. Therefore, the dielectric strength of the semiconductor device 10 can be improved while preventing the transformer chip 70 from becoming large.

[0243] [Modifications common to the first to third embodiments] In each embodiment, the configuration of the third element insulating layer 72 of the transformer chip 70 can be changed as desired. In one example, the first insulating film 72P may be omitted from the third element insulating layer 72. In other words, the insulating layer stack structure 72T of the third element insulating layer 72 may be formed by stacking a plurality of second insulating films 72Q.

[0244] 35, the transformer chip 70 may be joined onto the first chip 50 by an insulating bonding material SDA. That is, an insulating bonding material SDA may be interposed between the transformer chip 70 and the first chip 50 in the Z direction. With this configuration, the distance DZ in the Z direction between the second intermediate wiring 58D of the first chip 50 and the inner coil 110 of the transformer chip 70 can be increased by the thickness of the insulating bonding material SDA. Therefore, the withstand voltage of the semiconductor device 10 can be improved.

[0245] The position of the second middle wiring 58D in the Z direction can be changed arbitrarily. In one example, the second middle wiring 58D may be disposed closer to the first semiconductor substrate 51 than the center of the insulator 52T in the Z direction. This makes it possible to increase the distance in the Z direction between the second middle wiring 58D and the inner coil 110. As a result, the withstand voltage of the semiconductor device 10 can be improved.

[0246] The arrangement of the transformer chip 70 on the first chip 50 can be changed as desired. In one example, the transformer chip 70 may be arranged on the first chip 50 such that the third semiconductor substrate 71 is located on the opposite side to the first chip 50 with respect to the third element insulating layer 72. In this case, the first transformer pads 75A, 75B and the second transformer pads 76A, 76B may be provided on the third semiconductor substrate 71.

[0247] The outer coil 100 (120) and the inner coil 110 (130) may be disposed at different positions in the Z direction. When the transformer chip 70 is disposed on the first chip 50, the outer coil 100 (120) may be disposed closer to the third element back surface 72R of the third element insulating layer 72 than the inner coil 110 (130) in the Z direction.

[0248] According to this configuration, it is possible to reduce the opposing area between the outer coil 100 (120) and the inner coil 110 (130) while increasing the distance DZ in the Z direction between the inner coil 110 (130) and the second intermediate wiring 58D of the second connection wiring 58 of the first chip 50. Therefore, it is possible to reduce the capacitance of the parasitic capacitor caused by this opposing area.

[0249] The position of the intermediate pad 56 of the first chip 50 can be changed as desired. The intermediate pad 56 may be disposed at one of both ends in the X direction of the chip surface 50S that is closer to the chip side surface 50A. As a result, the length of the transmitting wires WT (WT1, WT2) may be equal to or longer than the length of the receiving wires WR (WR1, WR2).

[0250] The third semiconductor substrate 71 may be omitted from the transformer chip 70. The position of the transformer chip 70 in the X direction relative to the first chip 50 can be changed arbitrarily. In one example, the transformer chip 70 may be disposed on the first chip 50 such that the chip side surface 70B is closer to the chip side surface 50A than the chip side surface 50B of the first chip 50.

[0251] 36, the transformer chip 70 may be arranged shifted toward the second chip 60 with respect to the first chip 50 in the X direction. That is, the chip side surface 70B of the transformer chip 70 is arranged closer to the second chip 60 than the chip side surface 50B of the first chip 50. In the example shown in FIG. 36, the inner coil 110 is arranged closer to the second chip 60 than the second intermediate wiring 58D of the second connection wiring 58. That is, the inner coil 110 does not face the second intermediate wiring 58D in the Z direction.

[0252] According to this configuration, the first chip 50 and the second chip 60 are closer to each other in a plan view, so that the length of the receiving side wire WR can be shortened. Note that the inner coil 110 may be disposed opposite the second middle wiring 58D in the Z direction.

[0253] 37, the transformer chip 70 may be disposed on the second chip 60. According to this configuration, the length of the receiving wire WR can be shortened. 38, the transformer chip 70 may be disposed above the first chip 50 and the second chip 60 so as to straddle the X-direction between the first chip 50 and the second chip 60. With this configuration, the length of the receiving wire WR can be shortened.

[0254] The semiconductor device 10 is not limited to being configured as a signal transmission device that transmits signals via the transformer 40, and may be configured as a power transmission device that transmits power via the transformer 40.

[0255] FIG. 39 shows an example of a circuit configuration of a power transmission device 300 as a modified example of the semiconductor device 10. The power transmission device 300 may include a control circuit 301, an oscillator 302, a transformer 40, diodes 303 to 306, and a smoothing capacitor 307. The control circuit 301 and the oscillator 302 may be included in the first circuit 20. The first circuit 20 may include the oscillator 302 and may not include the control circuit 301. The diodes 303 to 306 and the smoothing capacitor 307 may be included in the second circuit 30. The second circuit 30 may include the diodes 303 to 306 and may not include the smoothing capacitor 307. The number of diodes included in the second circuit 30 may be changed as appropriate depending on the configuration of the rectifier circuit. In one example, the first chip 50 including the control circuit 301 and the oscillator 302, the transformer chip 70 including the transformer 40, and the second chip 60 including the diodes 303 to 306 and the smoothing capacitor 307 are sealed with the sealing resin 200, similar to the semiconductor device 10 of the first embodiment.

[0256] A DC power supply 311 is connected to the control circuit 301. The oscillator 302 is controlled by the control circuit 301. The oscillator 302 outputs an AC signal. This AC signal is transmitted by the transformer 40. A DC voltage is supplied to the load 312 by the diodes 303-306 and the smoothing capacitor 307. In other words, the power transmission device 300 functions as a DC voltage conversion circuit (DC-DC converter) that converts the voltage of the DC power supply 311 into the operating voltage of the load 312.

[0257] The term "on" as used in this disclosure includes the meanings "on" and "above" unless the context clearly indicates otherwise. Thus, for example, the expression "a first element is disposed on a second element" is intended to mean that in some embodiments, the first element may be disposed directly on the second element in contact with the second element, while in other embodiments, the first element may be disposed above the second element without contacting the second element. In other words, the term "on" does not exclude a structure in which another element is formed between the first element and the second element.

[0258] The Z direction used in this disclosure does not necessarily have to be a vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" of the Z direction described in this specification being "up" and "down" of the vertical direction. For example, the X direction may be a vertical direction, or the Y direction may be a vertical direction.

[0259] <Additional Notes> The technical ideas that can be understood from this disclosure are described below. Note that, for the purpose of aiding understanding, not for the purpose of limitation, the components described in the appendices are given the reference numbers of the corresponding components in the above embodiment. The reference numbers are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numbers.

[0260] [Appendix 1] a first chip (50) including a first circuit (20); a second chip (60) that is spaced apart from the first chip (50) in a first direction (X direction) and includes a second circuit (30); a transformer chip (70) disposed on the first chip (50) and including a transformer (40); the first circuit (20) and the second circuit (30) are configured to transmit a signal or power via the transformer (40); The transformer chip (70) is A third element insulating layer (72); The transformer (40) includes an outer coil (100) and an inner coil (110) disposed within the third element insulating layer (72); Including, When viewed from the thickness direction (Z direction) of the third element insulating layer (72), the inner coil (110) is disposed inside the outer coil (100) so as not to overlap with the outer coil (100). A semiconductor device (10).

[0261] [Appendix 2] The transformer chip (70) includes a third semiconductor substrate (71) in contact with the third element insulating layer (72), In a chip arrangement state in which the transformer chip (70) is arranged on the first chip (50), the third semiconductor substrate (71) is interposed between the third element insulating layer (72) and the first chip (50). 2. The semiconductor device according to claim 1.

[0262] [Appendix 3] the third element insulating layer (72) includes a third element front surface (72S) and a third element back surface (72R) opposite to the third element front surface (72S), The outer coil (100) is electrically connected to the first circuit (20), The inner coil (110) is disposed in the third element insulating layer (72) closer to the third element front surface (72S) than to the third element back surface (72R). 3. The semiconductor device according to claim 2.

[0263] [Appendix 4] The first circuit (20) includes a transmission circuit (21), The second circuit (30) includes a receiving circuit (31), The outer coil (100) and the transmission circuit (21) are electrically connected via a transmission wire (WT), The inner coil (110) and the receiving circuit (31) are electrically connected via a receiving wire (WR), The length of the transmitting wire (WT) is shorter than the length of the receiving wire (WR). 4. The semiconductor device according to claim 1, wherein the first and second electrodes are arranged in a first direction.

[0264] [Appendix 5] The inner coil (100) and the outer coil (110) are disposed at the same position in the thickness direction (Z direction). 5. The semiconductor device according to claim 1,

[0265] [Appendix 6] The third element insulating layer (72) includes a structure in which a plurality of insulators (72U) are stacked, the insulators (72U) including a first insulating film (72P) containing silicon nitride and a second insulating film (72Q) containing silicon oxide stacked on the first insulating film (72P), The inner coil (110) and the outer coil (100) are provided so as to penetrate a specific insulator (72UA) which is a specific one of the insulators (72U), the third element insulating layer (72) is formed of the first insulating film (72P) and includes a cover insulating film (72UB) in contact with the second insulating film (72Q) of the specific insulator (72U) so as to cover the inner coil (110) and the outer coil (100); A portion of the first insulating film (72P) of the specific insulator (72UA) between the inner coil (110) and the outer coil (100) includes a plurality of isolation insulating films (77A) spaced apart in a direction perpendicular to a thickness direction (Z direction) of the third element insulating layer (72), a portion of the cover insulating film (72UB) between the inner coil (110) and the outer coil (100) includes a plurality of cover-side isolation insulating films (77B) spaced apart in a direction perpendicular to the thickness direction (Z direction); Each of the plurality of isolation insulating films (77A) and the cover-side isolation insulating film (77B) is formed of the second insulating film (72Q). 6. The semiconductor device according to claim 1,

[0266] [Appendix 7] Each of the plurality of isolation insulating films (77A) and the cover-side isolation insulating film (77B) is formed in an annular shape. 7. The semiconductor device according to claim 6.

[0267] [Appendix 8] The third element insulating layer (72) has a structure in which a plurality of insulators (72U) are stacked, the insulators including a first insulating film (72P) containing silicon nitride and a second insulating film (72Q) containing silicon oxide stacked on the first insulating film (72P), The inner coil (110) and the outer coil (100) are provided so as to penetrate a specific insulator (72UA) which is a specific one of the insulators (72U), the third element insulating layer (72) is formed of the first insulating film (72P) and includes a cover insulating film (72UB) in contact with the second insulating film (72Q) of the specific insulator (72UA) so as to cover the inner coil (110) and the outer coil (100); a portion of the first insulating film (72P) of the specific insulator (72UA) between the inner coil (110) and the outer coil (100) includes a plurality of recesses (72PC) ​​spaced apart in a direction perpendicular to a thickness direction (Z direction) of the third element insulating layer (72) and opening toward the cover insulating film (72UB); A portion of the cover insulating film (72UB) between the inner coil (110) and the outer coil (100) includes a plurality of cover side recesses (72PD) that are spaced apart in a direction perpendicular to the thickness direction (Z direction) and open toward the first insulating film (72P) of the specific insulator (72UA), The second insulating film (72Q) is embedded in each of the plurality of recesses (72PC) ​​and the plurality of cover side recesses (72PD). 6. The semiconductor device according to claim 1,

[0268] [Appendix 9] Each of the plurality of recesses (72PC) ​​and the plurality of cover side recesses (72PD) is formed in an annular shape. 9. The semiconductor device according to claim 8.

[0269] [Appendix 10] The outer coil (120) includes a first outer coil (121) and a second outer coil (122) having first ends (121A, 122A) and second ends (121B, 122B), respectively; a second end (121B) of the first outer coil (121) and a second end (122B) of the second outer coil (122) are connected to each other, the first outer coil (121) and the second outer coil (122) are configured such that, when a current flows from a first end of one of the first outer coil (121) and the second outer coil (122) to a first end of the other outer coil, magnetic fluxes in opposite directions are generated; The inner coil (130) includes a first inner coil (131) and a second inner coil (132) having first ends (131A, 132A) and second ends (131B, 132B), respectively; When viewed from the thickness direction (Z direction) of the third element insulating layer (72), the first inner coil (131) is disposed inside the first outer coil (121) so as not to overlap with the first outer coil (121), and the second inner coil (132) is disposed inside the second outer coil (122) so as not to overlap with the second outer coil (122). 6. The semiconductor device according to claim 1,

[0270] [Appendix 11] The first inner coil (131) and the second inner coil (132) are connected by a coil connecting wire (WC) provided outside the transformer chip (70). 11. The semiconductor device according to claim 10.

[0271] [Appendix 12] The first outer coil (121) is electrically connected to the first chip (50) by a first chip connecting wire (WT1) provided outside the transformer chip (70), The second outer coil (122) is electrically connected to the first chip (50) by a second chip connecting wire (WT2) provided outside the transformer chip (70). 12. The semiconductor device according to claim 10 or 11.

[0272] [Appendix 13] The first inner coil (131) is electrically connected to the second chip (60) by a third chip connecting wire (WR1) provided outside the transformer chip (70), The second inner coil (132) is electrically connected to the second chip (60) by a fourth chip connecting wire (WR2) provided outside the transformer chip (70). 13. The semiconductor device according to any one of claims 10 to 12.

[0273] [Appendix 14] The transformer chip (70) is smaller than the first chip (50) when viewed in the thickness direction (Z direction) and is disposed closer to the second chip (60) than the first chip (50) in the first direction (X direction). 14. The semiconductor device according to claim 1, wherein the first and second electrodes are arranged in a first direction.

[0274] [Appendix 15] The transformer chip (70) is disposed so as to be shifted toward the second chip (60) with respect to the first chip (50) in the first direction (X direction). 14. The semiconductor device according to claim 1, wherein the first and second electrodes are arranged in a first direction.

[0275] [Appendix 16] An insulating bonding material (SDA) is interposed between the first chip (50) and the transformer chip (70). 16. The semiconductor device according to claim 1,

[0276] [Appendix 17] a first die pad (81) supporting the first chip (50); a second die pad (91) supporting the second chip (60); a sealing resin (200) that seals the first chip (50), the second chip (60), the transformer chip (70), the first die pad (81), and the second die pad (91); Includes 17. The semiconductor device according to any one of claims 1 to 16.

[0277] [Appendix 18] a first chip (50) including a first circuit (20); a second chip (60) that is spaced apart from the first chip (50) in a first direction (X direction) and includes a second circuit (30); a transformer chip (70) disposed on the second chip (60) and including a transformer (40); the first circuit (20) and the second circuit (30) are connected via the transformer (40) and configured to transmit a signal or power via the transformer (40); The transformer chip (70) is A third element insulating layer (72); The transformer (40) includes an outer coil (100) and an inner coil (110) disposed within the third element insulating layer (72); Including, When viewed from the thickness direction (Z direction) of the third element insulating layer (72), the inner coil (110) is disposed inside the outer coil (100) so as not to overlap with the outer coil (100). A semiconductor device (10).

[0278] [Appendix 19] The transformer chip (70) is disposed above the first chip (50) and above the second chip (60) so as to straddle the first direction (X direction) between the first chip (50) and the second chip (60). 14. The semiconductor device according to claim 1, wherein the first and second electrodes are arranged in a first direction.

[0279] [Appendix 20] The first inner coil (131), the second inner coil (132), the first outer coil (121), and the second outer coil (122) are disposed at the same positions as one another in the thickness direction (Z direction). 14. The semiconductor device according to any one of claims 10 to 13.

[0280] [Appendix 21] The third element insulating layer (72) has a structure in which a plurality of insulators (72U) are stacked, the insulators including a first insulating film (72P) containing silicon nitride and a second insulating film (72Q) containing silicon oxide stacked on the first insulating film (72P), the first inner coil (131), the second inner coil (132), the first outer coil (121), and the second outer coil (122) are arranged to penetrate a specific insulator (72UA) that is a specific one of the insulators (72U); the third element insulating layer (72) is composed of the first insulating film (72P), and includes a cover insulating film (72UB) in contact with the second insulating film (72Q) of the specific insulator (72UA) so as to cover the first inner coil (131), the second inner coil (132), the first outer coil (121), and the second outer coil (122); a portion of the first insulating film (72P) of the specific insulator (72UA) between the first inner coil (131) and the first outer coil (121) includes a plurality of first isolation insulating films (78A1) spaced apart in a direction perpendicular to the thickness direction (Z direction); a portion of the first insulating film (72P) of the specific insulator (72UA) between the second inner coil (132) and the second outer coil (122) includes a plurality of second isolation insulating films (78A2) spaced apart in a direction perpendicular to the thickness direction (Z direction), a portion of the cover insulating film (72UB) between the first inner coil (131) and the first outer coil (121) includes a plurality of first cover side isolation insulating films (78B1) spaced apart in a direction perpendicular to the thickness direction (Z direction), a portion of the cover insulating film (72UB) between the second inner coil (132) and the second outer coil (122) includes a plurality of second cover side isolation insulating films (78B2) spaced apart in a direction perpendicular to the thickness direction (Z direction), Each of the plurality of first isolation insulating films (78A1), the plurality of second isolation insulating films (78A2), the plurality of first cover side isolation insulating films (78B1), and the plurality of second cover side isolation insulating films (78B2) is composed of the second insulating film (72Q). 14. The semiconductor device according to any one of claims 10 to 13.

[0281] [Appendix 22] Each of the plurality of first isolation insulating films (78A1), the plurality of second isolation insulating films (78A2), the plurality of first cover side isolation insulating films (78B1), and the plurality of second cover side isolation insulating films (78B2) is formed in a ring shape. 22. The semiconductor device according to claim 21.

[0282] [Appendix 23] The third element insulating layer (72) has a structure in which a plurality of insulators (72U) are stacked, the insulators including a first insulating film (72P) containing silicon nitride and a second insulating film (72Q) containing silicon oxide stacked on the first insulating film (72P), the first inner coil (131), the second inner coil (132), the first outer coil (121), and the second outer coil (122) are arranged to penetrate a specific insulator (72UA) that is a specific one of the insulators (72U); the third element insulating layer (72) is composed of the first insulating film (72P), and includes a cover insulating film (72UB) in contact with the second insulating film (72Q) of the specific insulator (72UA) so as to cover the first inner coil (131), the second inner coil (132), the first outer coil (121), and the second outer coil (122); a portion of the first insulating film (72P) of the specific insulator (72UA) between the first inner coil (131) and the first outer coil (121) includes a plurality of first recesses (79A) that are spaced apart in a direction perpendicular to the thickness direction (Z direction) and open toward the cover insulating film (72UB); a portion of the first insulating film (72P) of the specific insulator (72UA) between the second inner coil (132) and the second outer coil (122) includes a plurality of second recesses (79B) that are spaced apart in a direction perpendicular to the thickness direction (Z direction) and open toward the cover insulating film (72UB), a portion of the cover insulating film (72UB) between the first inner coil (131) and the first outer coil (121) includes a plurality of first cover side recesses (79C) that are spaced apart in a direction perpendicular to the thickness direction (Z direction) and open toward the first insulating film (72P) of the specific insulator (72UA); a portion of the cover insulating film (72UB) between the second inner coil (132) and the second outer coil (122) includes a plurality of second cover side recesses (79C) that are spaced apart in a direction perpendicular to the thickness direction (Z direction) and open toward the first insulating film (72P) of the specific insulator (72UA), The second insulating film (72Q) is embedded in each of the plurality of first recesses (79A), the plurality of second recesses (79B), the plurality of first cover side recesses (79C), and the plurality of second cover side recesses (79D). 14. The semiconductor device according to any one of claims 10 to 13.

[0283] [Appendix 24] Each of the first recesses (79A), the second recesses (79B), the first cover side recesses (79C), and the second cover side recesses (79D) is formed in an annular shape. 24. The semiconductor device according to claim 23.

[0284] [Appendix 25] a first chip (50) including a first circuit (20); a second chip (60) that is spaced apart from the first chip (50) in a first direction (X direction) and includes a second circuit (30); a transformer chip (70) including a transformer (40), the transformer chip (70) being disposed on the first chip (50) and on the second chip (60) so as to straddle the first direction (X direction) between the first chip (50) and the second chip (60); the first circuit (20) and the second circuit (30) are connected via the transformer (40) and configured to transmit a signal or power via the transformer (40); The transformer chip (70) is A third element insulating layer (72); The transformer (40) includes an outer coil (100) and an inner coil (110) disposed within the third element insulating layer (72); Including, When viewed from the thickness direction (Z direction) of the third element insulating layer (72), the inner coil (110) is disposed inside the outer coil (100) so as not to overlap with the outer coil (100). A semiconductor device (10).

[0285] The above description is merely illustrative. Those skilled in the art may recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of describing the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and alterations that fall within the scope of the present disclosure, including the scope of the claims. [Explanation of symbols]

[0286] 10...Semiconductor device 20...1st circuit 21...Transmitting circuit 30…Second circuit 31...Receiver circuit 40...Trans 41…First coil 42…Second coil 43…Third coil 50…First tip 50S…Chip surface 50R…Chip back 50A~50D: Chip side 51...first semiconductor substrate 52...first element insulating layer 52A…Insulating film 52S…First element surface 52R…Back side of first element 52T…insulator 53…First protective film 54…First passivation film 55…First pad 56...Middle pad 57…First connection wire 57A…First circuit side connection part 57B…First pad side connection part 57C…1st wiring 58…Second connection wire 58A…Second circuit side connection part 58B…First intermediate wiring 58C…Intermediate connection 58D…Second intermediate wiring 58E…Second pad side connection part 60…Second chip 60S…Chip surface 60R…Chip backside 60A~60D: Chip side 61...second semiconductor substrate 62...Second element insulating layer 62A…Insulating film 62S: Second element surface 62R…Second element back side 62T…Insulator 63…Second protective film 64…Second passivation film 65…Second pad 66...Middle pad 67…Third connection wire 67A…3rd circuit side connection part 67B…Third pad side connection part 67C…3rd wiring 68…4th connection wire 68A…4th circuit side connection part 68B…First intermediate wiring 68C…Intermediate connection 68D…Second intermediate wiring 68E…4th pad side connection part 70...Trans chip 70S…Chip surface 70R…Chip backside 70A~70D: Chip side 70SA~70SF...1st~6th opening 71...Third semiconductor substrate 72...Third element insulating layer 72S…Third element surface 72R…3rd element back side 72T…Insulating layer laminated structure 72U…Insulator 72UA…Specific insulator 72UB…Cover insulating film 72P…First insulating film 72PC…Concave 72PD…Cover side recess 72Q, 72QA, 72QB...Second insulating film 72V,72W…Groove 72V1…1st groove 72V2…2nd groove 72W1…1st groove 72W2…Second groove 73…Third protective film 74…Third passivation film 75A, 75B…Pads for the first transformer 76A, 76B: Pads for the second transformer 77…Wiring section 77A…Connection wiring 77AA…1st end 77AB…2nd end 77B, 77C...Via 78A…Isolation insulating film 78A1...First isolation insulating film 78A2...Second isolation insulating film 78B…Cover side isolation insulating film 78B1...First cover side isolation insulating film 78B2...Second cover side isolation insulating film 79A…First recess 79B…Second recess 79C…First cover side recess 79D…Second cover side recess 80…First lead frame 81…First die pad 82…1st lead 90…2nd lead frame 91…Second die pad 92…2nd lead 100…Outer coil 100A…Outlet wire 101...1st end 102…Second end 103…Outer coil 103A, 103B... Coil section 104…Beer 110…Inner coil 111...1st end 112…Second end 120…Outer coil 121…First outer coil 121A…1st end 121B…Second end 122…Second outer coil 122A…1st end 122B…Second end 123…Third outer coil 123A, 123B…Coil section 124…4th outer coil 124A, 124B…Coil section 130…Inner coil 131…First inner coil 131A…1st end 131B…Second end 132…Second inner coil 132A…1st end 132B…Second end 141~146...Pads for transformers 1~6 150...1st wiring section 151…Connection wiring 151A…1st end 151B…Second end 152,153…Beer 160…Second wiring section 161…Connection wiring 161A…1st end 161B…Second end 162,163…Beer 171,172…Beer 181~184...Beer 200…Sealing resin 201~204…Sealing side 300...Power transmission device 301...Control circuit 302…Oscillator 303~306...Diodes 307...Smoothing capacitor 311…DC power supply 312…Load SD: Conductive adhesive SDA: Insulating adhesive W1…First wire W2…Second wire WT: Transmitting wire WT1: 1st transmitter wire WT2: Second transmitter wire WR: Receiver wire WR1…first receiver wire WR2: 2nd receiver wire WC…Wire DZ…Distance

Claims

1. a first chip including a first circuit; a second chip disposed apart from the first chip in a first direction and including a second circuit; a transformer chip disposed on the first chip and including a transformer; the first circuit and the second circuit are configured to transmit a signal or power through the transformer; The transformer chip is A third element insulating layer; an outer coil and an inner coil disposed in the third element insulating layer as the transformer; Including, When viewed from a thickness direction of the third element insulating layer, the inner coil is disposed inside the outer coil so as not to overlap with the outer coil. Semiconductor device.

2. the transformer chip includes a third semiconductor substrate in contact with the third element insulating layer; In a chip arrangement state in which the transformer chip is arranged on the first chip, the third semiconductor substrate is interposed between the third element insulating layer and the first chip. The semiconductor device according to claim 1 .

3. the third element insulating layer includes a third element front surface and a third element back surface opposite to the third element front surface; the outer coil is electrically connected to the first circuit; The inner coil is disposed in the third element insulating layer closer to the third element front surface than to the third element back surface. The semiconductor device according to claim 2 .

4. the first circuit includes a transmission circuit; the second circuit includes a receiving circuit; the outer coil and the transmission circuit are electrically connected via a transmission wire; the inner coil and the receiving circuit are electrically connected via a receiving wire; The length of the sending wire is shorter than the length of the receiving wire The semiconductor device according to claim 1 .

5. The inner coil and the outer coil are disposed at the same position relative to each other in the thickness direction. The semiconductor device according to claim 1 .

6. the third element insulating layer includes a structure in which a plurality of insulators are stacked, the plurality of insulators including a first insulating film including silicon nitride and a second insulating film including silicon oxide stacked on the first insulating film; the inner coil and the outer coil are provided to penetrate a specific insulator, the third element insulating layer is made of the first insulating film and includes a cover insulating film in contact with the second insulating film of the specific insulator so as to cover the inner coil and the outer coil, a portion of the first insulating film of the specific insulator between the inner coil and the outer coil includes a plurality of isolation insulating films spaced apart in a direction perpendicular to a thickness direction of the third element insulating layer, a portion of the cover insulating film between the inner coil and the outer coil includes a plurality of cover-side isolation insulating films spaced apart in a direction perpendicular to the thickness direction, Each of the plurality of isolation insulating films and the cover-side isolation insulating film is made of the second insulating film. The semiconductor device according to claim 1 .

7. Each of the plurality of isolation insulating films and the cover-side isolation insulating film is formed in an annular shape. The semiconductor device according to claim 6.

8. the third element insulating layer has a structure in which a plurality of insulators are stacked, the plurality of insulators including a first insulating film containing silicon nitride and a second insulating film containing silicon oxide stacked on the first insulating film; the inner coil and the outer coil are provided to penetrate a specific insulator, the third element insulating layer is made of the first insulating film and includes a cover insulating film in contact with the second insulating film of the specific insulator so as to cover the inner coil and the outer coil, a portion of the first insulating film of the specific insulator between the inner coil and the outer coil includes a plurality of recesses that are spaced apart in a direction perpendicular to a thickness direction of the third element insulating layer and open toward the cover insulating film, a portion of the cover insulating film between the inner coil and the outer coil includes a plurality of cover-side recesses spaced apart in a direction perpendicular to the thickness direction and opening toward the first insulating film of the specific insulator, The second insulating film is embedded in each of the plurality of recesses and the plurality of cover-side recesses. The semiconductor device according to claim 1 .

9. Each of the plurality of recesses and the plurality of cover-side recesses is formed in an annular shape. The semiconductor device according to claim 8.

10. the outer coil includes a first outer coil and a second outer coil having a first end and a second end, respectively; a second end of the first outer coil and a second end of the second outer coil are connected to each other; the first outer coil and the second outer coil are configured such that, when a current flows from a first end of one of the first outer coil and the second outer coil to a first end of the other outer coil, magnetic fluxes in opposite directions are generated; the inner coil includes a first inner coil and a second inner coil having a first end and a second end, respectively; When viewed from the thickness direction of the third element insulating layer, the first inner coil is disposed inside the first outer coil so as not to overlap with the first outer coil, and the second inner coil is disposed inside the second outer coil so as not to overlap with the second outer coil. The semiconductor device according to claim 1 .

11. The first inner coil and the second inner coil are connected by a coil connecting wire provided outside the transformer chip. The semiconductor device according to claim 10.

12. the first outer coil is electrically connected to the first chip by a first chip connecting wire provided outside the transformer chip, The second outer coil is electrically connected to the first chip by a second chip connecting wire provided outside the transformer chip. The semiconductor device according to claim 10.

13. the first inner coil is electrically connected to the second chip by a third chip connecting wire provided outside the transformer chip, The second inner coil is electrically connected to the second chip by a fourth chip connecting wire provided outside the transformer chip. The semiconductor device according to claim 10.

14. The transformer chip is smaller than the first chip when viewed in the thickness direction and is disposed closer to the second chip than the first chip in the first direction. The semiconductor device according to claim 1 .

15. The transformer chip is disposed so as to be shifted toward the second chip with respect to the first chip in the first direction. The semiconductor device according to claim 1 .

16. An insulating bonding material is interposed between the first chip and the transformer chip. The semiconductor device according to claim 1 .

17. a first die pad supporting the first chip; a second die pad supporting the second chip; a sealing resin that seals the first chip, the second chip, the transformer chip, the first die pad, and the second die pad; Includes The semiconductor device according to any one of claims 1 to 16.

18. a first chip including a first circuit; a second chip disposed apart from the first chip in a first direction and including a second circuit; a transformer chip disposed on the second chip and including a transformer; the first circuit and the second circuit are connected via the transformer and configured to transmit a signal or power via the transformer; The transformer chip is A third element insulating layer; an outer coil and an inner coil disposed in the third element insulating layer as the transformer; Including, When viewed from a thickness direction of the third element insulating layer, the inner coil is disposed inside the outer coil so as not to overlap with the outer coil. Semiconductor device.

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