Semiconductor device

Abstract

To improve dielectric breakdown voltage of a semiconductor device.SOLUTION: A semiconductor device 10 includes: a first chip 50; a second chip 60 which is disposed away from the first chip 50 in an X-direction; a sub-mount chip 120 which is provided separately from the first chip 50 and the second chip 60; and a transformer chip 70, including a transformer 40, which is disposed on the sub-mount chip 120. The transformer chip 70 includes: a third semiconductor substrate 71; and a third element insulation layer 72 formed on the third semiconductor substrate 71. The transformer 40 is embedded in the third element insulation layer 72. The sub-mount chip 120 includes: a fourth semiconductor substrate 121; and an insulation layer 122 formed on the fourth semiconductor substrate 121.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a transformer chip including a semiconductor substrate, an insulating layer laminated structure formed on the substrate, and an upper coil and a lower coil formed in the insulating layer laminated structure. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2018-78169 A

[0004] [overview] By the way, there are cases where it is required to improve the dielectric strength voltage of a transformer chip.

[0005] A semiconductor device according to one embodiment of the present disclosure includes a first chip including a first semiconductor substrate, a first circuit formed on the first semiconductor substrate, and a first element insulating layer formed on the first semiconductor substrate, a second semiconductor substrate, a second circuit formed on the second semiconductor substrate, and a second element insulating layer formed on the second semiconductor substrate, and is disposed apart from the first chip in a first direction, a sub-mount chip provided separately from the first chip and the second chip, and a transformer chip disposed on the sub-mount chip and including a transformer, wherein the first circuit and the second circuit are configured to transmit a signal or power via the transformer, the transformer chip includes a third semiconductor substrate and a third element insulating layer formed on the third semiconductor substrate, and the transformer is embedded in the third element insulating layer, and the sub-mount chip includes a fourth semiconductor substrate and an insulating layer formed on the fourth semiconductor substrate. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic circuit diagram of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a schematic plan view of the semiconductor device of FIG. [Diagram 3] FIG. 3 is a schematic cross-sectional view of the semiconductor device taken along line F3-F3 in FIG. [Figure 4] FIG. 4 is a schematic plan view of the transformer chip in the semiconductor device of FIG. [Diagram 5] FIG. 5 is a schematic cross-sectional view of the transformer chip taken along line F5-F5 in FIG. [Figure 6] FIG. 6 is a schematic cross-sectional view of the transformer chip taken along line F6-F6 in FIG. [Figure 7] FIG. 7 is a schematic cross-sectional view of the submount chip in the semiconductor device of FIG. [Figure 8] FIG. 8 is a schematic enlarged cross-sectional view of the first chip, the second chip, the submount chip, the transformer chip, and the periphery thereof in the semiconductor device of FIG. [Figure 9] FIG. 9 is a schematic cross-sectional view of a transformer chip in a semiconductor device according to the second embodiment. [Figure 10] FIG. 10 is a schematic circuit diagram of a semiconductor device according to the third embodiment. [Figure 11] FIG. 11 is a schematic plan view of the semiconductor device of FIG. [Figure 12] FIG. 12 is a schematic plan view of the transformer chip in the semiconductor device of FIG. [Figure 13] FIG. 13 is a schematic cross-sectional view of the transformer chip and the submount chip taken along line F13-F13 in FIG. [Figure 14] FIG. 14 is a schematic cross-sectional view of the transformer chip and the submount chip taken along line F14-F14 in FIG. [Figure 15] FIG. 15 is a schematic cross-sectional view of a transformer chip in a first modification of the semiconductor device of the first embodiment. [Figure 16]FIG. 16 is a schematic cross-sectional view of a transformer chip in a second modification of the semiconductor device of the first embodiment. [Figure 17] FIG. 17 is an exploded perspective view of a part of a transformer chip in a second modification of the semiconductor device of the first embodiment. [Figure 18] FIG. 18 is a schematic cross-sectional view of a transformer chip in a third modification of the semiconductor device of the first embodiment. [Figure 19] FIG. 19 is a schematic cross-sectional view of a transformer chip in a fourth modification of the semiconductor device of the first embodiment. [Figure 20] FIG. 20 is a schematic cross-sectional view of a part of a transformer chip in a modification of the semiconductor device of the second embodiment. [Figure 21] FIG. 21 is a schematic cross-sectional view of a transformer chip in a first modification of the semiconductor device of the third embodiment. [Figure 22] FIG. 22 is a schematic cross-sectional view of a transformer chip in a second modification of the semiconductor device of the third embodiment. [Figure 23] FIG. 23 is an exploded perspective view of a part of a transformer chip in a second modification of the semiconductor device of the third embodiment. [Figure 24] FIG. 24 is a schematic cross-sectional view of a transformer chip in a third modification of the semiconductor device of the third embodiment. [Diagram 25] FIG. 25 is a schematic cross-sectional view of a transformer chip in a fourth modification of the semiconductor device of the third embodiment. [Figure 26] FIG. 26 is a schematic plan view of a transformer chip in a fifth modification of the semiconductor device of the third embodiment. [Figure 27] FIG. 27 is a schematic plan view of a transformer chip in a fifth modification of the semiconductor device of the third embodiment. [Figure 28] FIG. 28 is a schematic cross-sectional view of a part of a transformer chip in a modification of the semiconductor device of the third embodiment. [Figure 29] FIG. 29 is a schematic cross-sectional view of a part of a transformer chip in a modification of the semiconductor device of the third embodiment. [Diagram 30]FIG. 30 is a schematic cross-sectional view of a part of a transformer chip in a modification of the semiconductor device of the third embodiment. [Diagram 31] FIG. 31 is a schematic cross-sectional view of a part of a transformer chip in a modification of the semiconductor device of the third embodiment. [Diagram 32] FIG. 32 is a schematic cross-sectional view of the first chip, the second chip, the sub-mount chip, the transformer chip, and their periphery in a semiconductor device of the modified example. [Diagram 33] FIG. 33 is a schematic cross-sectional view of the first chip, the second chip, the sub-mount chip, the transformer chip, and their periphery in a semiconductor device of the modified example. [Diagram 34] FIG. 34 is a schematic cross-sectional view of the first chip, the sub-mount chip, the transformer chip, and their periphery in a semiconductor device of the modified example. [Diagram 35] FIG. 35 is a schematic cross-sectional view of a part of the first chip, a part of the second chip, the submount chip, the transformer chip, and their periphery in a semiconductor device of the modified example. [Diagram 36] FIG. 36 is a schematic cross-sectional view of the first chip, the sub-mount chip, the transformer chip, and their periphery in a semiconductor device of the modified example. [Figure 37] FIG. 37 is a schematic cross-sectional view of the first chip, the second chip, the sub-mount chip, the transformer chip, and their periphery in a semiconductor device of the modified example. [Figure 38] FIG. 38 is a schematic cross-sectional view of the first chip, the sub-mount chip, the transformer chip, and their periphery in a semiconductor device of the modified example. [Figure 39] FIG. 39 is a schematic circuit diagram of a semiconductor device according to a modified example. [Diagram 40] FIG. 40 is a schematic cross-sectional view of the first chip, the second chip, the submount chip, the transformer chip, and the periphery thereof in the semiconductor device of FIG. [Diagram 41] FIG. 41 is a schematic circuit diagram of a semiconductor device according to a modified example.

[0007] [Detailed Description] Hereinafter, some embodiments of the semiconductor device of the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of description, components shown in the drawings are not necessarily drawn to scale. Also, hatching lines may be omitted in cross-sectional views to facilitate understanding. The accompanying drawings are merely illustrative of embodiments of the present disclosure and should not be considered as limiting the present disclosure. Terms such as "first", "second", and "third" in the present disclosure are used merely to distinguish objects and are not used to rank the objects.

[0008] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0009] The term "at least one" as used herein means "one or more" of the desired options. As an example, the term "at least one" as used herein means "only one option" or "both of two options" if the number of options is two. As another example, the term "at least one" as used herein means "only one option" or "any combination of two or more options" if the number of options is three or more.

[0010] As used in this specification, "the length (dimension) of A is equal to the length (dimension) of B" or "the length (dimension) of A and the length (dimension) of B are equal to each other" also includes a relationship in which the difference between the length (dimension) of A and the length (dimension) of B is within 10% of the length (dimension) of A, for example.

[0011] First Embodiment [Schematic configuration of semiconductor device] A schematic configuration of a semiconductor device 10 according to a first embodiment will be described with reference to Figs. 1 to 3. Fig. 1 diagrammatically illustrates the circuit configuration of the semiconductor device 10 according to the first embodiment. Fig. 2 diagrammatically illustrates an example of the internal configuration (planar structure) of the semiconductor device 10. In Fig. 2, a sealing resin 200, which will be described later, is indicated by a two-dot chain line in order to illustrate the internal configuration of the semiconductor device 10. Fig. 3 diagrammatically illustrates a cross-sectional structure of the semiconductor device 10 of Fig. 2 taken along line F3-F3.

[0012] In addition, since the circuit configuration of the semiconductor device 10 is shown in a simplified manner in Fig. 1, the number of external terminals of the semiconductor device 10 in Fig. 2 is greater than the number of external terminals of the semiconductor device 10 in Fig. 1. Here, the number of external terminals of the semiconductor device 10 refers to the number of external electrodes capable of connecting the semiconductor device 10 to electronic components external to the semiconductor device 10.

[0013] (Circuit configuration of semiconductor device) 1, the semiconductor device 10 includes a first circuit 20, a second circuit 30, and a transformer 40. The transformer 40 is configured to electrically insulate the first circuit 20 and the second circuit 30 from each other.

[0014] The first circuit 20 is configured to operate by a first voltage V1. In one example, the first circuit 20 includes a transmitting circuit or a receiving circuit. In the first embodiment, the first circuit 20 includes a transmitting circuit 21. The transmitting circuit 21 includes at least one transistor. The second circuit 30 is configured to operate by a second voltage V2. In one example, the second circuit 30 includes a transmitting circuit or a receiving circuit. In the first embodiment, the second circuit 30 includes a receiving circuit 31. The receiving circuit 31 includes at least one transistor. The first voltage V1 and the second voltage V2 may be the same as each other or may be different. In one example, the second voltage V2 is equal to the first voltage V1. The semiconductor device 10 may be referred to as a digital isolator. Therefore, the semiconductor device 10 can also be referred to as a signal transmission device that transmits a signal from the first circuit 20 to the second circuit 30.

[0015] The transformer 40 includes a first coil 41 and a second coil 42. The first coil 41 is electrically connected to the transmission circuit 21 of the first circuit 20. The second coil 42 is electrically connected to the reception circuit 31 of the second circuit 30.

[0016] The transmitting circuit 21 of the first circuit 20 receives the input signal and pulse-drives the transformer 40. The pulse signal excited in the first coil 41 of the transformer 40 is transmitted through the second coil 42 and input to the receiving circuit 31 of the second circuit 30. The receiving circuit 31 outputs an output signal based on the input pulse signal.

[0017] (Internal structure of semiconductor device) 2, the semiconductor device 10 includes a first chip 50, a second chip 60, a transformer chip 70, a first lead frame 80, a second lead frame 90, and a sealing resin 200. The sealing resin 200 is configured to seal the first chip 50, the second chip 60, and the transformer chip 70, and to partially seal the first lead frame 80 and the second lead frame 90. In FIG. 2, the sealing resin 200 is indicated by a two-dot chain line for the convenience of explaining the internal configuration of the semiconductor device 10.

[0018] Thus, in the semiconductor device 10, the first chip 50, the second chip 60, and the transformer chip 70 are packaged as a plurality of semiconductor chips by the sealing resin 200. Here, the transformer chip 70 is an example of an "insulating chip".

[0019] The package format of the semiconductor device 10 is an SO (Small Outline) type, and in the first embodiment, is an SOP (Small Outline Package). The package format of the semiconductor device 10 can be changed arbitrarily. The package format is not limited to SOP, and may be QFN (Quad For Non Lead Package), DFP (Dual Flat Package), DIP (Dual Inline Package), QFP (Quad Flat Package), SIP (Single Inline Package), SOJ (Small Outline J-leaded Package), or various package structures similar to these.

[0020] The sealing resin 200 is made of a resin material having electrical insulation properties. The resin material includes, for example, black epoxy resin. The sealing resin 200 is formed in a rectangular plate shape with the Z direction as the thickness direction. The sealing resin 200 has four sealing side surfaces 201 to 204. More specifically, the sealing resin 200 has sealing side surfaces 201 and 202 as both end surfaces in the X direction and sealing side surfaces 203 and 204 as both end surfaces in the Y direction. The X direction and the Y direction are directions perpendicular to the Z direction. The X direction and the Y direction are perpendicular to each other when viewed from the Z direction. The sealing resin 200 is rectangular in shape with the X direction as the long side direction and the Y direction as the short side direction when viewed from the Z direction. Here, the X direction corresponds to the "first direction." In the following description, "plan view" means that the semiconductor device 10 or a component of the semiconductor device 10 is viewed from the Z direction.

[0021] Each of the first lead frame 80 and the second lead frame 90 is a conductor and is formed of a material containing, for example, Cu (copper), Fe (iron), Al (aluminum), etc. Each of the lead frames 80, 90 is provided straddling the inside and outside of the sealing resin 200. The first lead frame 80 and the second lead frame 90 are arranged at a distance from each other in the X direction.

[0022] The first lead frame 80 has a first die pad 81 disposed within the sealing resin 200, and a plurality of first leads 82 disposed across the inside and outside of the sealing resin 200. Each of the first leads 82 constitutes an external terminal that electrically connects the semiconductor device 10 to an external electronic device.

[0023] The first chip 50 is mounted on the first die pad 81. It can be said that the first die pad 81 supports the first chip 50. In a plan view, the first die pad 81 is disposed such that the center in the Y direction is closer to the sealing side surface 201 than the center in the Y direction of the sealing resin 200. In the first embodiment, the first die pad 81 is not exposed from the sealing resin 200. In one example, the shape of the first die pad 81 in a plan view is a rectangle whose long side direction is the X direction and whose short side direction is the Y direction.

[0024] The multiple first leads 82 are arranged spaced apart from one another in the Y direction. Of the multiple first leads 82, the first leads 82 arranged at the end closer to the sealing side surface 203 in the Y direction are integrated with the first die pad 81. The remaining first leads 82 are arranged spaced apart from the first die pad 81 in the X direction. A portion of each first lead 82 protrudes from the sealing side surface 201 outward from the sealing resin 200.

[0025] The second lead frame 90 has a second die pad 91 disposed within the sealing resin 200, and a plurality of second leads 92 disposed across the inside and outside of the sealing resin 200. Each of the second leads 92 constitutes an external terminal that electrically connects the semiconductor device 10 to an external electronic device.

[0026] The second die pad 91 is mounted with the second chip 60. It can be said that the second die pad 91 supports the second chip 60. In plan view, the second die pad 91 is disposed closer to the sealing side surface 202 than the first die pad 81 in the X direction. That is, the first die pad 81 and the second die pad 91 are disposed apart from each other in the X direction. For this reason, the X direction can also be said to be the arrangement direction of both die pads 81, 91. The second chip 60 is disposed apart from the first chip 50 in the X direction. In the first embodiment, the second die pad 91 is not exposed from the sealing resin 200. In one example, the shape of the second die pad 91 in plan view is a rectangle with the X direction being the long side direction and the Y direction being the short side direction. Note that the shape of the second die pad 91 in plan view can be arbitrarily changed according to the number and shape of the semiconductor chips mounted on the second die pad 91.

[0027] The multiple second leads 92 are arranged spaced apart from one another in the Y direction. Of the multiple second leads 92, the second leads 92 arranged at the ends closer to the sealing side surface 204 in the Y direction are integrated with the second die pad 91. The remaining second leads 92 are arranged spaced apart from the second die pad 91 in the X direction. A portion of each second lead 92 protrudes from the sealing side surface 202 outward from the sealing resin 200.

[0028] In the first embodiment, the number of second leads 92 is the same as the number of first leads 82. As can be seen from Fig. 2, the multiple first leads 82 and the multiple second leads 92 are arranged in a direction (Y direction) perpendicular to the arrangement direction (X direction) of the first die pad 81 and the second die pad 91 in a plan view. Note that the number of second leads 92 and the number of first leads 82 can each be changed arbitrarily. In one example, the number of first leads 82 and the number of second leads 92 may be different from each other.

[0029] In the first embodiment, the first die pad 81 is supported by a first lead 82 integrated with the first die pad 81. The second die pad 91 is supported by a second lead 92 integrated with the second die pad 91. Therefore, each of the die pads 81, 91 is not provided with a hanging lead exposed from the sealing side surfaces 203, 204. Therefore, the insulation distance between the first lead frame 80 and the second lead frame 90 can be made large.

[0030] The first chip 50 mounted on the first die pad 81 includes the first circuit 20 of FIG. 1. The first chip 50 is formed in a rectangular shape having short and long sides in a plan view. In a plan view, the first chip 50 is mounted on the first die pad 81 so that the long sides run along the Y direction and the short sides run along the X direction. As shown in FIG. 3, the first chip 50 is bonded to the first die pad 81 by a conductive bonding material SD. The conductive bonding material SD may be a solder paste, an Ag (silver) paste, or the like.

[0031] 2 and 3, the first chip 50 includes a plurality of first pads 55 and a plurality of first intermediate pads 56. Each of the plurality of first pads 55 and the plurality of first intermediate pads 56 is electrically connected to the first circuit 20. The plurality of first pads 55 are individually connected to a plurality of first leads 82 by first wires W1. The plurality of first intermediate pads 56 are individually electrically connected to the transformer chip 70 by first intermediate wires WA.

[0032] As shown in Fig. 2, the second chip 60 mounted on the second die pad 91 includes the second circuit 30 of Fig. 1. The second chip 60 is formed in a rectangular shape having short sides and long sides in a plan view. In a plan view, the second chip 60 is mounted on the second die pad 91 so that the long sides are aligned along the X direction and the short sides are aligned along the Y direction. As shown in Fig. 3, the second chip 60 is bonded to the second die pad 91 by a conductive bonding material SD.

[0033] 2 and 3, the second chip 60 includes a plurality of second pads 65 and a plurality of second intermediate pads 66. Each of the plurality of second pads 65 and the plurality of second intermediate pads 66 is electrically connected to the second circuit 30. The plurality of second pads 65 are individually connected to a plurality of second leads 92 by second wires W2. The plurality of second intermediate pads 66 are individually electrically connected to the transformer chip 70 by second intermediate wires WB.

[0034] Each of the first pads 55, each of the first intermediate pads 56, each of the second pads 65, and each of the second intermediate pads 66 is formed of a material including one or more appropriately selected from Ti (titanium), TiN (titanium nitride), Au (gold), Ag, Cu, Al (aluminum), and W (tungsten). Each of the first wires W1, each of the first intermediate wires WA, each of the second wires W2, and each of the second intermediate wires WB is a bonding wire formed by a wire bonding device, and is formed of a conductor including, for example, Au, Al, Cu, etc.

[0035] 2 and 3, in the first embodiment, the transformer chip 70 is disposed on the first die pad 81. It can be said that both the first chip 50 and the transformer chip 70 are disposed on the first die pad 81. The transformer chip 70 is disposed between the first chip 50 and the second chip 60 in the X direction. The distance between the transformer chip 70 and the second chip 60 in the X direction is greater than the distance between the transformer chip 70 and the first chip 50 in the X direction.

[0036] The transformer chip 70 includes the transformer 40 of FIG. 1. The transformer chip 70 is formed in a rectangular shape having short and long sides in a plan view. In a plan view, the transformer chip 70 is disposed on the first chip 50 so that the long side is along the X direction and the short side is along the Y direction. As shown in FIG. 2, in the first embodiment, the dimension of the transformer chip 70 in the Y direction is smaller than both the dimension of the first chip 50 in the Y direction and the dimension of the second chip 60 in the Y direction. The dimension of the transformer chip 70 in the Y direction can be changed arbitrarily. In one example, the dimension of the transformer chip 70 in the Y direction may be equal to the dimension of the first chip 50 in the Y direction. In one example, the dimension of the transformer chip 70 in the Y direction may be equal to the dimension of the second chip 60 in the Y direction. A detailed description of the electrical connection structure between the transformer chip 70 and the first chip 50 and the second chip 60 will be given later.

[0037] 1 to 3 is an example, and the circuit configurations included in the first chip 50 and the second chip 60 may be changed as appropriate. The first circuit 20 may include a circuit other than the transmitting circuit 21. The second circuit 30 may include a circuit other than the receiving circuit 31. For example, the first circuit 20 may include an analog-digital conversion circuit. In this case, the semiconductor device 10 is configured as an isolated A / D conversion device.

[0038] For example, the second circuit 30 may include a driver circuit that drives the gate of the switching element. The driver circuit may be connected to an external terminal of the semiconductor device 10 (for example, the second lead 92 shown in FIG. 2). In this case, the semiconductor device 10 is configured as an insulated gate driver that drives the switching element. The switching element is a power semiconductor element such as a SiMOSFET (Si Metal-Oxide-Semiconductor Field-Effect Transistor), a SiCMOSFET, or an IGBT (Insulated Gate Bipolar Transistor). The driver circuit is generally a half-bridge circuit in which a low-side switching element and a high-side switching element are connected in a totem pole configuration.

[0039] The semiconductor device 10 used as an insulated gate driver applies a drive voltage signal to the control terminal of a switching element. In this case, the transmission circuit 21 of the first circuit 20 converts a control signal input from, for example, a control device into a pulse signal. The driver circuit of the second circuit 30 outputs a drive voltage signal to the control terminal of the switching element in response to a signal received by the reception circuit 31 through the transformer 40.

[0040] Thus, in the semiconductor device 10 used as an insulated gate driver, the power supply voltage of the first circuit 20 that receives a signal from the control device is 5V, 3.3V, etc., with respect to the ground potential. On the other hand, in the case of the second circuit 30 connected to the high-side switching element, a voltage equivalent to the voltage applied to the drain of the high-side switching element (for example, 600V or more) is transiently applied. For this reason, the semiconductor device 10 is required to have a dielectric strength voltage between the first circuit 20 and the second circuit 30, more specifically, between the first coil 41 and the second coil 42 of the transformer 40. This dielectric strength voltage is, for example, 2500Vrms or more and 7500Vrms or less. In one example, the dielectric strength voltage of the semiconductor device 10 is about 5000Vrms. However, the specific value of the dielectric strength voltage of the semiconductor device 10 is not limited to this and is arbitrary.

[0041] (First chip configuration) An example of the configuration of the first chip 50 will be described with reference to FIGS. 2 and 3, the rectangular, flat first chip 50 includes a chip front surface 50S and a chip back surface 50R that face opposite each other in the Z direction. The chip front surface 50S of the first chip 50 is, for example, the surface of the first chip 50 that faces the first die pad 81 in the Z direction. The chip back surface 50R is the surface of the first chip 50 that faces the first die pad 81. The multiple first pads 55 and the multiple first intermediate pads 56 are exposed from the chip front surface 50S.

[0042] 3, the first chip 50 includes a first semiconductor substrate 51 and a first element insulating layer 52 formed on the first semiconductor substrate 51. The first semiconductor substrate 51 constitutes a chip back surface 50R, and the first element insulating layer 52 constitutes a chip front surface 50S.

[0043] The first semiconductor substrate 51 (chip back surface 50R) is bonded to the first die pad 81 by a conductive bonding material SD. The first semiconductor substrate 51 is formed of, for example, a material containing Si. In the first embodiment, the first semiconductor substrate 51 is a Si substrate. Note that a wide band gap semiconductor or a compound semiconductor may be used for the first semiconductor substrate 51. The wide band gap semiconductor is a semiconductor substrate having a band gap of 2.0 eV or more. The wide band gap semiconductor may be SiC (silicon carbide). The compound semiconductor may be a III-V group compound semiconductor. The compound semiconductor may include at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide). The first circuit 20 of FIG. 1 is formed on the first semiconductor substrate 51.

[0044] The first element insulating layer 52 includes a laminated structure in which a plurality of insulating films are laminated in the Z direction. The insulating film is formed of a material containing at least one of, for example, SiN and SiO2. In one example, the first element insulating layer 52 includes a laminated structure in which a plurality of insulating films containing SiO2 are laminated in the Z direction. In the first element insulating layer 52, a first circuit 20, a first connection wiring 53 connecting the first circuit 20 and the first pad 55, and a second connection wiring 54 connecting the first circuit 20 and the first intermediate pad 56 are provided. The first connection wiring 53 is provided in a plurality of numbers corresponding to, for example, the number of the first pads 55. The second connection wiring 54 is provided in a plurality of numbers corresponding to, for example, the number of the first intermediate pads 56. In this way, the first circuit 20 and the plurality of first pads 55 are individually electrically connected in the first element insulating layer 52. The first circuit 20 and the plurality of first intermediate pads 56 are individually electrically connected in the first element insulating layer 52.

[0045] (Configuration of the second chip) An example of the configuration of the second chip 60 will be described with reference to FIGS. 2 and 3, the rectangular, flat second chip 60 includes a chip front surface 60S and a chip back surface 60R that face opposite each other in the Z direction. The chip front surface 60S of the second chip 60 faces the same side as the chip front surface 50S of the first chip 50. The chip back surface 60R faces the second die pad 91 (see FIG. 3). The multiple second pads 65 and the multiple second intermediate pads 66 are exposed from the chip front surface 60S.

[0046] 3, the second chip 60 includes a second semiconductor substrate 61 and a second element insulating layer 62 formed on the second semiconductor substrate 61. The second semiconductor substrate 61 constitutes a chip back surface 60R, and the second element insulating layer 62 constitutes a chip front surface 60S.

[0047] The second semiconductor substrate 61 (chip back surface 60R) is bonded to the second die pad 91 by a conductive bonding material SD. The second semiconductor substrate 61 is formed of a material containing Si, for example. In the first embodiment, the second semiconductor substrate 61 is a Si substrate. Note that a wide band gap semiconductor or a compound semiconductor may be used for the second semiconductor substrate 61. The second circuit 30 of FIG. 1 is formed on the second semiconductor substrate 61.

[0048] The second element insulating layer 62 includes a laminated structure in which a plurality of insulating films are laminated in the Z direction. The insulating film is formed of a material containing at least one of, for example, SiN and SiO2. In one example, the second element insulating layer 62 includes a laminated structure in which a plurality of insulating films containing SiO2 are laminated in the Z direction. In the second element insulating layer 62, the second circuit 30, a third connection wiring 63 connecting the second circuit 30 and the second pad 65, and a fourth connection wiring 64 connecting the second circuit 30 and the second intermediate pad 66 are provided. The plurality of third connection wirings 63 are provided in a number corresponding to the number of the second pads 65. The plurality of fourth connection wirings 64 are provided in a number corresponding to the number of the second intermediate pads 66. In this way, the second circuit 30 and the plurality of second pads 65 are individually electrically connected in the second element insulating layer 62. The second circuit 30 and the plurality of second intermediate pads 66 are individually electrically connected in the second element insulating layer 62.

[0049] (Transformer chip configuration) An example of the configuration of the transformer chip 70 and its surroundings will be described with reference to Figs. 3 to 7. Fig. 4 shows a schematic planar structure of the transformer chip 70. Fig. 5 shows a schematic cross-sectional structure of the transformer chip 70 taken along line F5-F5 in Fig. 4. Fig. 6 shows a schematic cross-sectional structure of the transformer chip 70 taken along line F6-F6 in Fig. 4. Fig. 7 shows a schematic cross-sectional structure of the sub-mount chip 120 supporting the transformer chip 70. The cross-sectional position of Fig. 7 is the same as the cross-sectional position of the transformer chip 70 in Fig. 5, for example.

[0050] As shown in FIG. 4, the rectangular flat transformer chip 70 includes a chip front surface 70S and a chip back surface 70R (see FIG. 5) facing opposite sides in the Z direction, and four chip side surfaces 70A to 70D connecting the chip front surface 70S and the chip back surface 70R. The chip front surface 70S of the transformer chip 70 faces the same side as the chip front surface 50S (see FIG. 3) of the first chip 50. The chip back surface 70R faces the same side as the chip back surface 50R (see FIG. 3). The chip side surfaces 70A and 70B constitute both end surfaces of the transformer chip 70 in the X direction, and the chip side surfaces 70C and 70D constitute both end surfaces of the transformer chip 70 in the Y direction. The chip side surface 70A faces the first chip 50 (see FIG. 2), and the chip side surface 70B faces the second chip 60 (see FIG. 2). Chip side surface 70C faces the same side as sealing side surface 203 of sealing resin 200 (see FIG. 2), and chip side surface 70D faces the same side as sealing side surface 204 of sealing resin 200 (see FIG. 2).

[0051] The transformer chip 70 includes first transformer pads 75A, 75B and second transformer pads 76A, 76B exposed in the Z direction from a chip surface 70S. The first transformer pads 75A, 75B are pads electrically connected to a plurality of first intermediate pads 56 (see FIG. 2) of the first chip 50. Specifically, the first transformer pads 75A, 75B and the plurality of first intermediate pads 56 are individually connected by a plurality of first intermediate wires WA (see FIG. 2). The first transformer pads 75A, 75B are disposed on the chip side surface 70A and closer to the chip side surface 70C in a plan view. In the example shown in FIG. 4, the first transformer pads 75A, 75B are arranged at the same positions as each other in the X direction and spaced apart from each other in the Y direction.

[0052] The second transformer pads 76A, 76B are pads electrically connected to a plurality of second intermediate pads 66 (see FIG. 2) of the second chip 60. Specifically, the second transformer pads 76A, 76B and the plurality of second intermediate pads 66 are individually connected by a plurality of second intermediate wires WB (see FIG. 2). The second transformer pads 76A, 76B are disposed approximately in the center in the X direction and closer to the sealing side surface 204 (see FIG. 2) in the Y direction in a plan view. In one example, the second transformer pads 76A, 76B are arranged at the same positions as each other in the X direction and spaced apart from each other in the Y direction.

[0053] 5, the transformer chip 70 includes a third semiconductor substrate 71 and a third element insulating layer 72 formed on the third semiconductor substrate 71. Here, the third semiconductor substrate 71 is an example of a "semiconductor substrate of an insulating chip", and the third element insulating layer 72 is an example of an "element insulating layer of an insulating chip".

[0054] The third semiconductor substrate 71 constitutes the chip back surface 70R of the transformer chip 70. The third semiconductor substrate 71 is formed of a material containing, for example, Si. In the first embodiment, the third semiconductor substrate 71 is a Si substrate. Note that the third semiconductor substrate 71 may be made of a wide band gap semiconductor or a compound semiconductor.

[0055] The Z-direction dimension (thickness) of the third semiconductor substrate 71 may be, for example, the same as the Z-direction dimension (thickness) of the first semiconductor substrate 51. The Z-direction dimension (thickness) of the third element insulating layer 72 may be, for example, smaller than the Z-direction dimension (thickness) of the first element insulating layer 52 (see FIG. 3). Therefore, the Z-direction dimension of the transformer chip 70 may be smaller than the Z-direction dimension of the first chip 50.

[0056] Here, the dimension in the Z direction of the third semiconductor substrate 71 can be changed arbitrarily. In one example, the dimension in the Z direction of the third semiconductor substrate 71 may be smaller than the dimension in the Z direction of the first semiconductor substrate 51. In addition, the dimension in the Z direction of the third element insulating layer 72 can be changed arbitrarily. In one example, the dimension in the Z direction of the third element insulating layer 72 may be equal to the dimension in the Z direction of the first element insulating layer 52.

[0057] The third element insulating layer 72 includes a third element front surface 72S and a third element back surface 72R facing opposite directions. The third element front surface 72S constitutes a chip front surface 70S of the transformer chip 70. The third element back surface 72R is in contact with the third semiconductor substrate 71.

[0058] The third element insulating layer 72 includes a plurality of first insulating films 72P and a plurality of second insulating films 72Q. That is, the third element insulating layer 72 includes an insulating layer stack structure 72T which is a stack of a plurality of first insulating films 72P and a plurality of second insulating films 72Q. The insulating layer stack structure 72T is configured by stacking a plurality of first insulating films 72P and a plurality of second insulating films 72Q one by one in the Z direction. Here, if a stack of one first insulating film 72P and one second insulating film 72Q is an insulator 72U, the insulating layer stack structure 72T can be said to be a structure in which a plurality of insulators 72U are stacked. In this way, the Z direction can also be said to be the thickness direction of the third element insulating layer 72.

[0059] The first insulating film 72P is an etching stopper film, and is formed of a material including at least one of, for example, SiN, SiC, and SiCN (nitrogen-doped silicon carbide). The first insulating film 72P may have a function of preventing the diffusion of, for example, Cu. In other words, the first insulating film 72P may be a film preventing the diffusion of Cu.

[0060] The second insulating film 72Q is an interlayer insulating film, and is, for example, an oxide film formed of a material containing SiO2. The second insulating film 72Q has a thickness greater than that of the first insulating film 72P. The first insulating film 72P has a thickness of, for example, 50 nm or more and less than 1000 nm. The second insulating film 72Q has a thickness of, for example, 500 nm or more and 5000 nm or less. In the first embodiment, the first insulating film 72P has a thickness of about 300 nm, and the second insulating film 72Q has a thickness of about 2000 nm. In one example, both the uppermost and lowermost insulating films of the insulating layer stack structure 72T are composed of the second insulating film 72Q. In order to easily understand the drawings, the ratio of the thickness of the first insulating film 72P to the thickness of the second insulating film 72Q in the drawings is different from the actual ratio of the thickness of the first insulating film 72P to the thickness of the second insulating film 72Q.

[0061] The third element insulating layer 72 further includes a protective film 73 and a passivation film 74 . The protective film 73 is a film that protects the insulating layer stack structure 72T. The protective film 73 is formed on the insulating layer stack structure 72T. The protective film 73 is formed of a material containing, for example, SiO2. In one example, the protective film 73 is formed over the entire surface of the insulating layer stack structure 72T in a plan view. The material constituting the protective film 73 can be changed as desired. In one example, the protective film 73 may be formed of a material containing SiN.

[0062] The passivation film 74 is a surface protective film of the transformer chip 70. The passivation film 74 is formed on the protective film 73. The passivation film 74 constitutes the third element surface 72S of the third element insulating layer 72. The passivation film 74 is formed of a material containing at least one of PI (polyimide), SiN, and SiO2. In one example, the passivation film 74 is formed of a material containing SiO2. In one example, the passivation film 74 is formed over the entire surface of the protective film 73 in a plan view. The material constituting the passivation film 74 can be changed arbitrarily. The passivation film 74 may be formed of the same material as the protective film 73, or may be formed of a material different from the protective film 73.

[0063] As shown in FIG. 4, the transformer chip 70 includes an outer coil 100 and an inner coil 110. As shown in FIGS. 5 and 6, both the outer coil 100 and the inner coil 110 are embedded in the third element insulating layer 72. In other words, the transformer 40 is embedded in the third element insulating layer 72. The outer coil 100 corresponds to the first coil 41 of the transformer 40 in FIG. 1, and the inner coil 110 corresponds to the second coil 42 of the transformer 40. Here, both the outer coil 100 and the inner coil 110 are examples of "insulating elements."

[0064] In one example, the outer coil 100 and the inner coil 110 are arranged at the same position in the Z direction. It can be said that the outer coil 100 and the inner coil 110 are arranged on the same plane perpendicular to the Z direction. Specifically, the outer coil 100 and the inner coil 110 are provided so as to penetrate a specific insulator 72UA, which is a specific insulator 72U. In the example shown in FIG. 5 and FIG. 6, the specific insulator 72UA is an insulator 72U immediately below the top insulator 72U in the insulating layer laminate structure 72T. In other words, the specific insulator 72UA is the second insulator 72U from the third element surface 72S in the insulating layer laminate structure 72T. That is, in the example shown in FIG. 5 and FIG. 6, the outer coil 100 and the inner coil 110 are arranged closer to the third element surface 72S than the center of the third element insulating layer 72 in the Z direction. Note that the specific insulator 72UA in the insulating layer laminate structure 72T is optional. In one example, the specific insulator 72UA may be the uppermost insulator 72U of the insulating layer stack structure 72T.

[0065] In plan view, the inner coil 110 is disposed inside the outer coil 100. The inner coil 110 is disposed so as not to overlap the outer coil 100 in plan view. In other words, the inner coil 110 is disposed apart from the outer coil 100 in a direction perpendicular to the Z direction. Therefore, a specific insulator 72UA is disposed between the inner coil 110 and the outer coil 100 in a direction perpendicular to the Z direction. In this way, the outer coil 100 and the inner coil 110 are electrically insulated from each other and are configured to be magnetically coupled. In the transformer 40 of the first embodiment, the outer coil 100 and the inner coil 110 are configured to be magnetically coupled along a direction perpendicular to the Z direction. Therefore, a current flows in the inner coil 110 in a direction corresponding to the direction of the magnetic flux generated by the current flowing in the outer coil 100.

[0066] As shown in FIG. 4, the outer coil 100 includes a first end 101 and a second end 102 opposite to the first end 101. The outer coil 100 is formed in a circular spiral shape in a plan view. In the spiral outer coil 100, the first end 101 is disposed inside the spiral, and the second end 102 is disposed outside the spiral. That is, the outer coil 100 is wound in a spiral shape with the first end 101 as the inner circumferential end and the second end 102 as the outer circumferential end. The outer coil 100 includes a lead wire 100A extending from the second end 102 toward the chip side surface 70A along the X direction. The lead wire 100A is disposed at the same position as the outer coil 100 in the Z direction. In one example, the lead wire 100A is formed integrally with the outer coil 100.

[0067] The tip of the lead wire 100A constitutes the first transformer pad 75B. In one example, the third element insulating layer 72 is provided with a second outer opening that exposes the tip of the lead wire 100A in the Z direction. The tip of the lead wire 100A exposed by the second outer opening constitutes the first transformer pad 75B.

[0068] The inner coil 110 disposed inside the outer coil 100 includes a first end 111 and a second end 112 opposite to the first end 111. The inner coil 110 is formed in a circular spiral shape in a plan view. In the spiral inner coil 110, the first end 111 is disposed inside the spiral, and the second end 112 is disposed outside the spiral. In other words, the inner coil 110 is wound in a spiral shape with the first end 111 as the inner circumferential end and the second end 112 as the outer circumferential end.

[0069] The first end 111 constitutes the second transformer pad 76A, and the second end 112 constitutes the second transformer pad 76B. In one example, the third element insulating layer 72 is individually provided with a first inner opening exposing the first end 111 in the Z direction and a second inner opening in the Z direction exposing the second end 112. The first end 111 exposed by the first inner opening constitutes the second transformer pad 76A, and the second end 112 exposed by the second inner opening constitutes the second transformer pad 76B.

[0070] Both the outer coil 100 and the inner coil 110 are made of a material including one or more of Ti (titanium), TiN (titanium nitride), Au, Ag, Cu, Al, and W (tungsten). In one example, the outer coil 100 and the inner coil 110 may be made of the same material. In one example, the outer coil 100 and the inner coil 110 may be made of a material including Cu.

[0071] The transformer chip 70 includes a wiring portion 77 that electrically connects the first end 101 of the outer coil 100 and the first transformer pad 75A. The wiring portion 77 is formed of a material including one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W.

[0072] As shown in FIG. 5, the wiring portion 77 includes a connection wiring 77A and vias 77B and 77C. The connection wiring 77A is disposed closer to the third semiconductor substrate 71 than the outer coil 100 in the Z direction. The connection wiring 77A extends in the X direction from the first end 101 of the outer coil 100 toward the chip side surface 70A in a plan view. The connection wiring 77A includes a first end 77AA and a second end 77AB, which are both ends in the X direction. The first end 77AA of the connection wiring 77A is electrically connected to the first end 101 of the outer coil 100 by a via 77B. The second end 77AB of the connection wiring 77A is electrically connected to the first transformer pad 75A by a via 77C. The first transformer pad 75A is exposed in the Z direction by a first outer opening provided in the third element insulating layer 72.

[0073] 3, the semiconductor device 10 includes a sub-mount chip 120 provided separately from the first chip 50 and the second chip 60. The sub-mount chip 120 is disposed on a first die pad 81. The sub-mount chip 120 is bonded to the first die pad 81 by, for example, a conductive bonding material SD. The transformer chip 70 is disposed on the sub-mount chip 120. In the following description, the state in which the transformer chip 70 is disposed on the sub-mount chip 120 is referred to as a "chip disposed state."

[0074] As shown in FIG. 2 and FIG. 7, the sub-mount chip 120 includes a chip front surface 120S and a chip back surface 120R facing in opposite directions in the Z direction, and four chip side surfaces 120A to 120D connecting the chip front surface 120S and the chip back surface 120R. The chip front surface 120S of the sub-mount chip 120 faces the same side as the chip front surface 50S (see FIG. 3) of the first chip 50. The chip back surface 120R faces the same side as the chip back surface 50R (see FIG. 3). The chip back surface 120R is in contact with the conductive bonding material SD. The chip side surfaces 120A and 120B constitute both end surfaces of the sub-mount chip 120 in the X direction, and the chip side surfaces 120C and 120D constitute both end surfaces of the sub-mount chip 120 in the Y direction. The chip side surface 120A faces the first chip 50 side, and the chip side surface 120B faces the second chip 60 side. Chip side surface 120C faces the same side as sealing side surface 203 of sealing resin 200 (see FIG. 2), and chip side surface 120D faces the same side as sealing side surface 204 of sealing resin 200 (see FIG. 2).

[0075] 2 and 8, the sub-mount chip 120 has the same size as the transformer chip 70 in a plan view. In the first embodiment, in the chip arrangement state, the chip side surface 120A of the sub-mount chip 120 and the chip side surface 70A of the transformer chip 70 are flush with each other, and the chip side surface 120B of the sub-mount chip 120 and the chip side surface 70B of the transformer chip 70 are flush with each other. Also, as shown in FIG. 2, in the first embodiment, in the chip arrangement state, the chip side surface 120C of the sub-mount chip 120 and the chip side surface 70C of the transformer chip 70 are flush with each other, and the chip side surface 120D of the sub-mount chip 120 and the chip side surface 70D of the transformer chip 70 are flush with each other.

[0076] 7, the submount chip 120 includes a fourth semiconductor substrate 121 and an insulating layer 122 formed on the fourth semiconductor substrate 121. Here, the fourth semiconductor substrate 121 is an example of a "submount semiconductor substrate."

[0077] The fourth semiconductor substrate 121 constitutes the chip back surface 120R of the submount chip 120. The fourth semiconductor substrate 121 is in contact with a conductive bonding material SD (see FIG. 8). The fourth semiconductor substrate 121 is formed of, for example, a material containing Si. In the first embodiment, the fourth semiconductor substrate 121 is a Si substrate. Note that the fourth semiconductor substrate 121 may be made of a wide band gap semiconductor or a compound semiconductor.

[0078] The insulating layer 122 includes an element front surface 122S and an element back surface 122R facing in opposite directions. The element front surface 122S constitutes a chip front surface 120S of the submount chip 120. The element back surface 122R is in contact with the fourth semiconductor substrate 121.

[0079] The insulating layer 122 includes a plurality of first insulating films 122P and a plurality of second insulating films 122Q. That is, the insulating layer 122 includes an insulating layer stack structure 122T which is a stack of a plurality of first insulating films 122P and a plurality of second insulating films 122Q. The insulating layer stack structure 122T is configured by stacking a plurality of first insulating films 122P and a plurality of second insulating films 122Q one by one in the Z direction. Here, if a stack of one first insulating film 122P and one second insulating film 122Q is an insulator 122U, the insulating layer stack structure 122T can be said to be a structure in which a plurality of insulators 122U are stacked. In this way, the Z direction can also be said to be the thickness direction of the insulating layer 122.

[0080] The first insulating film 122P is an etching stopper film and is formed of a material including at least one of SiN, SiC, and SiCN. The first insulating film 122P has a thickness of, for example, 50 nm or more and less than 1000 nm. In the first embodiment, the first insulating film 122P has a thickness of about 300 nm.

[0081] The second insulating film 122Q is an interlayer insulating film, and is, for example, an oxide film formed of a material containing SiO2. The second insulating film 122Q has a thickness greater than that of the first insulating film 122P. The second insulating film 122Q has a thickness of, for example, 500 nm or more and 5000 nm or less. In the first embodiment, the second insulating film 122Q has a thickness of about 2000 nm. In one example, the insulating films of the uppermost layer and the lowermost layer of the insulating layer stack structure 122T are both composed of the second insulating film 122Q. In addition, in order to easily understand the drawings, the ratio of the thickness of the first insulating film 122P to the thickness of the second insulating film 122Q in the drawings is different from the actual ratio of the thickness of the first insulating film 122P to the thickness of the second insulating film 122Q.

[0082] In one example, the thickness of the first insulating film 122P is equal to the thickness of the first insulating film 72P of the third element insulating layer 72 of the transformer chip 70. In one example, the thickness of the second insulating film 122Q is equal to the thickness of the second insulating film 122Q of the third element insulating layer 72. Note that the thicknesses of the first insulating film 122P and the second insulating film 122Q can each be changed arbitrarily.

[0083] The insulating layer 122 further includes a protective film 123 and a passivation film 124. Both the protective film 123 and the passivation film 124 are formed on the surface side of the insulating layer 122. Here, the surface side of the insulating layer 122 means a portion of the insulating layer 122 that is close to the element surface 122S and includes the element surface 122S. For this reason, it can be said that the surface side of the insulating layer 122 is also a portion that is close to the chip surface 120S and includes the chip surface 120S of the submount chip 120.

[0084] The protective film 123 is a film that protects the insulating layer stack structure 122T. The protective film 123 is formed on the insulating layer stack structure 122T. The protective film 123 is formed of a material containing, for example, SiO2. In one example, the protective film 123 is formed over the entire surface of the insulating layer stack structure 122T in a plan view. The material constituting the protective film 123 can be changed as desired. In one example, the protective film 123 may be formed of a material containing SiN.

[0085] The passivation film 124 is a surface protective film of the submount chip 120. The passivation film 124 is formed on the protective film 123. The passivation film 124 constitutes the element surface 122S of the insulating layer 122. The passivation film 124 is formed of a material containing at least one of PI, SiN, and SiO2. In one example, the passivation film 124 is formed of a material containing SiO2. In one example, the passivation film 124 is formed over the entire surface of the protective film 123 in a plan view. The material constituting the passivation film 124 can be changed arbitrarily. The passivation film 124 may be formed of the same material as the protective film 123, or may be formed of a material different from the protective film 123.

[0086] As shown in FIG. 8, the Z-direction dimension (thickness) of the fourth semiconductor substrate 121 may be equal to, for example, the Z-direction dimension (thickness) of the third semiconductor substrate 71. The Z-direction dimension (thickness) of the insulating layer 122 may be greater than, for example, the Z-direction dimension (thickness) of the third element insulating layer 72. Therefore, the Z-direction dimension (thickness) of the submount chip 120 may be greater than, for example, the Z-direction dimension (thickness) of the transformer chip 70. In addition, the Z-direction dimension of the fourth semiconductor substrate 121 may be equal to, for example, the Z-direction dimension (thickness) of the first semiconductor substrate 51. The Z-direction dimension of the insulating layer 122 may be equal to, for example, the Z-direction dimension (thickness) of the first element insulating layer 52. Therefore, the Z-direction dimension of the submount chip 120 may be equal to, for example, the Z-direction dimension (thickness) of the first chip 50. Similarly, the Z-direction dimension of the fourth semiconductor substrate 121 may be equal to, for example, the Z-direction dimension (thickness) of the second semiconductor substrate 61. The Z-direction dimension of the insulating layer 122 may be equal to, for example, the Z-direction dimension (thickness) of the second element insulating layer 62. Therefore, the Z-direction dimension of the submount chip 120 may be equal to the Z-direction dimension (thickness) of the second chip 60.

[0087] Here, the dimension in the Z direction of the fourth semiconductor substrate 121 can be changed arbitrarily. In one example, the dimension in the Z direction of the fourth semiconductor substrate 121 may be smaller than the dimension in the Z direction of the third semiconductor substrate 71. In addition, the dimension in the Z direction of the insulating layer 122 can be changed arbitrarily. In one example, the dimension in the Z direction of the insulating layer 122 may be the same as the dimension in the Z direction of the third element insulating layer 72.

[0088] In the chip arrangement state, the third semiconductor substrate 71 of the transformer chip 70 is in contact with the insulating layer 122 of the submount chip 120. More specifically, in the chip arrangement state, the third semiconductor substrate 71 is in contact with the passivation film 124 of the insulating layer 122. Thus, in the chip arrangement state, the third semiconductor substrate 71 is interposed between the third element insulating layer 72 and the submount chip 120 in the Z direction. More specifically, the third semiconductor substrate 71 is interposed between the third element insulating layer 72 and the insulating layer 122 in the Z direction.

[0089] 8, the dielectric strength of the semiconductor device 10 is determined by a distance DZ1 in the Z direction between the conductive bonding material SD between the first die pad 81 and the submount chip 120 and the inner coil 110. The distance DZ1 can be defined by the distance in the Z direction between the chip back surface 120R of the submount chip 120 and the inner coil 110.

[0090] Here, the submount chip 120 may be bonded to the first die pad 81 by an insulating bonding material instead of the conductive bonding material SD. In this case, the dielectric strength voltage of the semiconductor device 10 is determined by the distance DZ2 between the first die pad 81 and the inner coil 110 in the Z direction.

[0091] [Method of manufacturing semiconductor device] Next, an example of a method for manufacturing the semiconductor device 10 of the first embodiment will be described. In the following description, for the reference numerals relating to the components of the semiconductor device 10, please refer to FIGS.

[0092] A manufacturing method for semiconductor device 10 includes the steps of preparing a first chip 50, preparing a second chip 60, preparing a transformer chip 70, preparing a submount chip 120, and preparing a first lead frame 80 and a second lead frame 90.

[0093] The process of preparing the first chip 50 includes a process of forming a first element insulating layer 52, a plurality of first pads 55, a plurality of first intermediate pads 56, a first connection wiring 53, and a second connection wiring 54 on a first semiconductor substrate 51 on which the first circuit 20 is formed. The plurality of first pads 55, the plurality of first intermediate pads 56, the first connection wiring 53, and the second connection wiring 54 are formed by etching and sputtering using a metal mask in the process of stacking the insulating film of the first element insulating layer 52.

[0094] The step of preparing the second chip 60 includes a step of forming a second element insulating layer 62, a plurality of second pads 65, a plurality of second intermediate pads 66, a third connection wiring 63, and a fourth connection wiring 64 on a second semiconductor substrate 61 on which the second circuit 30 is formed. The plurality of second pads 65, the plurality of second intermediate pads 66, the third connection wiring 63, and the fourth connection wiring 64 are formed by etching and sputtering using a metal mask in the process of stacking the insulating film of the second element insulating layer 62.

[0095] The process of preparing the transformer chip 70 includes a process of forming a third element insulating layer 72, an outer coil 100, an inner coil 110, first transformer pads 75A and 75B, second transformer pads 76A and 76B, and a wiring section 77 on a third semiconductor substrate 71. The third element insulating layer 72 is formed by first forming a second insulating film 72Q on the third semiconductor substrate 71. Then, the first insulating film 72P and the second insulating film 72Q are alternately laminated on the second insulating film 72Q in this order. The outer coil 100, the inner coil 110, the first transformer pads 75A and 75B, the second transformer pads 76A and 76B, and the wiring section 77 are formed by etching and sputtering using a metal mask in the process of laminating the first insulating film 72P and the second insulating film 72Q of the third element insulating layer 72.

[0096] The step of preparing the submount chip 120 includes a step of forming an insulating layer 122 on a fourth semiconductor substrate 121. In this step, the insulating layer 122 is formed by alternately stacking a plurality of first insulating films 122P and a plurality of second insulating films 122Q one by one in the Z direction. The step of forming the insulating layer 122 is similar to the step of forming the third element insulating layer 72 of the transformer chip 70, for example.

[0097] The manufacturing method of the semiconductor device 10 includes a step of mounting the first chip 50 and the submount chip 120 on the first die pad 81 of the first lead frame 80, and a step of mounting the second chip 60 on the second die pad 91 of the second lead frame 90.

[0098] In the process of mounting the first chip 50 and the sub-mount chip 120 on the first die pad 81, first, a conductive bonding material SD is applied to two locations on the first die pad 81 that are spaced apart from each other in the X direction. Then, the first chip 50 is placed on one of the conductive bonding materials SD. Then, the sub-mount chip 120 is placed on the remaining conductive bonding material SD. Then, the first chip 50 and the sub-mount chip 120 are bonded to the first die pad 81 by melting and solidifying each conductive bonding material SD.

[0099] In the step of mounting the sub-mount chip 120, an insulating bonding material may be applied to the first die pad 81 instead of the conductive bonding material SD. Then, the sub-mount chip 120 is placed on the insulating bonding material. Then, the insulating bonding material is melted and solidified to bond the sub-mount chip 120 to the first die pad 81.

[0100] In the process of mounting the second chip 60 on the second die pad 91, first, a conductive bonding material SD is applied to the second die pad 91. Then, the second chip 60 is placed on the conductive bonding material SD. Then, the conductive bonding material SD is melted and solidified to bond the second chip 60 to the second die pad 91. Here, the conductive bonding material SD applied to the first die pad 81 and the conductive bonding material SD applied to the second die pad 91 may be melted and solidified at the same time.

[0101] The manufacturing method of the semiconductor device 10 includes a step of forming a plurality of first wires W1 and a plurality of second wires W2. The plurality of first wires W1 are formed using a wire bonding device so as to individually connect the plurality of first pads 55 of the first chip 50 to the plurality of first leads 82 of the first lead frame 80. The plurality of second wires W2 are formed using a wire bonding device so as to individually connect the plurality of second pads 65 of the second chip 60 to the plurality of second leads 92 of the second lead frame 90.

[0102] The manufacturing method of the semiconductor device 10 includes a step of arranging the transformer chip 70 on the submount chip 120. By arranging the transformer chip 70 on the submount chip 120, the third semiconductor substrate 71 of the transformer chip 70 contacts the insulating layer 122 of the submount chip 120.

[0103] The manufacturing method of the semiconductor device 10 includes a step of forming a plurality of first intermediate wires WA and a plurality of second intermediate wires WB. The plurality of first intermediate wires WA are formed using a wire bonding device so as to individually connect the first transformer pads 75A, 75B to the two first intermediate pads 56 of the first chip 50. The plurality of second intermediate wires WB are formed using a wire bonding device so as to individually connect the second transformer pads 76A, 76B to the two second intermediate pads 66 of the second chip 60.

[0104] The manufacturing method of the semiconductor device 10 includes a step of forming the sealing resin 200. In this step, the sealing resin 200 is formed by, for example, transfer molding. As a result, the sealing resin 200 seals the first chip 50, the second chip 60, the submount chip 120, the transformer chip 70, the first die pad 81, the second die pad 91, the multiple first wires W1, the multiple second wires W2, the multiple first intermediate wires WA, and the multiple second intermediate wires WB. Through the above steps, the semiconductor device 10 is manufactured.

[0105] In the manufacturing method of the semiconductor device 10, the order of the steps of forming the multiple first wires W1 and the multiple second wires W2 can be changed as desired. In one example, the step of forming the multiple first wires W1 and the multiple second wires W2 may be performed simultaneously with the step of forming the multiple first intermediate wires WA and the multiple second intermediate wires WB. In other words, in the chip arrangement state, the multiple first wires W1, the multiple second wires W2, the multiple first intermediate wires WA, and the multiple second intermediate wires WB may be formed consecutively by a wire bonding device.

[0106] [Operation of the first embodiment] The operation of the first embodiment will be described. In the following description, the transformer chip bonded to the first die pad 81 by the conductive bonding material SD is referred to as the "transformer chip of the comparative example." The transformer chip of the comparative example includes an outer coil 100 and an inner coil 110 provided in the third element insulating layer 72, similar to the transformer chip 70 of the first embodiment. In addition, a semiconductor device including the transformer chip of the comparative example is referred to as the "semiconductor device of the comparative example."

[0107] The dielectric strength of the semiconductor device of the comparative example is mainly determined by the distance in the Z direction between the inner coil 110 and the conductive bonding material SD of the transformer chip of the comparative example. In order to improve the dielectric strength of the semiconductor device of the comparative example, it is necessary to increase the distance in the Z direction between the inner coil 110 and the conductive bonding material SD. Therefore, it is possible to increase the thickness of the third element insulating layer 72 of the transformer chip of the comparative example. However, if the thickness of the third element insulating layer 72 is increased, the third semiconductor substrate 71 becomes more likely to warp during the manufacture of the transformer chip of the comparative example. The thicker the third element insulating layer 72, the greater the warp that occurs in the third semiconductor substrate 71.

[0108] In the first embodiment, the sub-mount chip 120 is interposed between the transformer chip 70 and the first die pad 81. The sub-mount chip 120 is bonded to the first die pad 81 by, for example, a conductive bonding material SD. On the other hand, the transformer chip 70 is disposed on the sub-mount chip 120, but is not bonded to the sub-mount chip 120 by the conductive bonding material SD. For this reason, the distance DZ1 between the inner coil 110 of the transformer chip 70 in the first embodiment and the conductive bonding material SD in the Z direction is larger by the thickness of the sub-mount chip 120 than the distance between the inner coil 110 of the transformer chip 70 in the comparative example and the conductive bonding material SD in the Z direction. In addition, when the sub-mount chip 120 is bonded to the first die pad 81 by, for example, an insulating bonding material, the distance DZ2 between the inner coil 110 and the first die pad 81 in the Z direction, which determines the dielectric strength voltage of the semiconductor device 10, is larger by the sum of the thickness of the sub-mount chip 120 and the thickness of the insulating bonding material, compared to the semiconductor device in the comparative example. As a result, in the first embodiment, the withstand voltage of the semiconductor device 10 can be improved without excessively increasing the thickness of the third element insulating layer 72 of the transformer chip 70.

[0109] In addition, the inner coil 110 and the outer coil 100 are disposed opposite to each other in a direction perpendicular to the Z direction. Therefore, by increasing the size of the transformer chip 70 in the X direction and the Y direction, the distance between the inner coil 110 and the outer coil 100 in the direction perpendicular to the Z direction can be made equal to or greater than the distance DZ1 (DZ2). In other words, the distance between the inner coil 110 and the outer coil 100 in the direction perpendicular to the Z direction can be made equal to or greater than the distance DZ1 (DZ2) without increasing the thickness of the third element insulating layer 72. Therefore, the dielectric strength of the semiconductor device 10 can be improved.

[0110] Furthermore, the wiring resistance values ​​of the outer coil 100 and the inner coil 110 affect the amount of current flowing through the outer coil 100 and the inner coil 110, and the degree of magnetic coupling. The wiring resistance value of the outer coil 100 can be reduced by widening the wiring width of the outer coil 100 and reducing the aspect ratio of the wiring thickness to the wiring width. Similarly, the wiring resistance value of the inner coil 110 can be reduced by widening the wiring width of the inner coil 110 and reducing the aspect ratio of the wiring thickness to the wiring width.

[0111] Here, for example, in the case of a configuration in which two coils are arranged facing each other in the Z direction, if the wiring width of these coils is increased, the facing area of ​​the two coils increases, which increases the capacitance value of the parasitic capacitor.

[0112] In the first embodiment, the outer coil 100 and the inner coil 110 face each other in a direction perpendicular to the Z direction. Therefore, even if the wiring width of each of the outer coil 100 and the inner coil 110 is increased, the facing area of ​​the outer coil 100 and the inner coil 110 does not change. That is, the capacitance value of the parasitic capacitor between the outer coil 100 and the inner coil 110 does not change. Therefore, the wiring resistance value of each coil can be reduced without increasing the capacitance value of the parasitic capacitor between the coils. As a result, the current flows easily in the outer coil 100 and the inner coil 110, so that the amount of magnetic flux generated in the transformer 40 can be increased. Then, the efficiency of the magnetic coupling between the outer coil 100 and the inner coil 110 can be improved, and the transfer characteristics can be improved.

[0113] [Effects of the first embodiment] According to the semiconductor device 10 of the first embodiment, the following effects can be obtained. (1-1) The semiconductor device 10 includes a first chip 50 including a first semiconductor substrate 51, a first circuit 20 formed on the first semiconductor substrate 51, and a first element insulating layer 52 formed on the first semiconductor substrate 51, a second chip 60 including a second semiconductor substrate 61, a second circuit 30 formed on the second semiconductor substrate 61, and a second element insulating layer 62 formed on the second semiconductor substrate 61 and disposed apart from the first chip 50 in the X direction, a sub-mount chip 120 provided separately from the first chip 50 and the second chip 60, and a transformer chip 70 disposed on the sub-mount chip 120 and including a transformer 40. The first circuit 20 and the second circuit 30 are configured to transmit a signal or power via the transformer 40. The transformer chip 70 includes a third semiconductor substrate 71 and a third element insulating layer 72 formed on the third semiconductor substrate 71. The transformer 40 is embedded in the third element insulating layer 72. The submount chip 120 includes a fourth semiconductor substrate 121 and an insulating layer 122 formed on the fourth semiconductor substrate 121 .

[0114] According to this configuration, by disposing the transformer chip 70 on the submount chip 120, it is possible to increase the distance between the transformer 40 in the transformer chip 70 and the conductive member outside the transformer chip 70 in the stacking direction (Z direction) of the transformer chip 70 and the submount chip 120. Therefore, it is possible to improve the dielectric strength of the semiconductor device 10.

[0115] In addition, since the submount chip 120 is composed of the fourth semiconductor substrate 121 and the insulating layer 122 formed on the fourth semiconductor substrate 121, the submount chip 120 can be manufactured in the same process as the transformer chip 70. Also, since the dielectric strength voltage of the semiconductor device 10 can be adjusted by adjusting the thickness of the insulating layer 122 of the submount chip 120, semiconductor devices 10 with a plurality of types of dielectric strength voltages can be manufactured without changing the configuration of the transformer chip 70.

[0116] (1-2) The third element insulating layer 72 of the transformer chip 70 includes an insulating layer stack structure 72T in which a first insulating film 72P containing silicon nitride and a second insulating film 72Q containing silicon oxide are alternately stacked multiple times.

[0117] This configuration makes it possible to increase the thickness of the insulating layer stack structure 72T while suppressing warpage of the transformer chip 70. This allows the distance between the transformer 40 in the transformer chip 70 and the conductive member outside the transformer chip 70 to be further increased. This allows the dielectric strength of the semiconductor device 10 to be further improved.

[0118] (1-3) The insulating layer 122 of the submount chip 120 includes a structure in which a first insulating film 122P containing silicon nitride and a second insulating film 122Q containing silicon oxide are alternately laminated in multiple layers.

[0119] This configuration makes it possible to increase the thickness of the insulating layer 122 while suppressing warpage of the submount chip 120. This allows the distance between the transformer 40 in the transformer chip 70 and the conductive member outside the transformer chip 70 to be further increased, thereby improving the dielectric strength of the semiconductor device 10.

[0120] (1-4) The thickness of the submount chip 120 is equal to or greater than the thickness of the transformer chip 70. This configuration makes it possible to increase the distance between the transformer 40 in the transformer chip 70 and the conductive member outside the transformer chip 70 while suppressing warping of the transformer chip 70. Therefore, the dielectric strength of the semiconductor device 10 can be improved.

[0121] (1-5) The dimension of the submount chip 120 in the X direction is equal to the dimension of the transformer chip 70 in the X direction. According to this configuration, compared to a configuration in which the dimension of the submount chip 120 in the X direction is smaller than the dimension of the transformer chip 70 in the X direction, the transformer chip 70 can be stably disposed on the submount chip 120. In addition, by making the position of the transformer chip 70 in the X direction the same as the position of the submount chip 120 in the X direction, the position of the transformer chip 70 in the X direction relative to the submount chip 120 can be easily determined.

[0122] (1-6) The thickness of the submount chip 120 is equal to or greater than the thickness of the first chip 50 or the second chip 60. According to this configuration, the dielectric strength of the semiconductor device 10 can be improved.

[0123] (1-7) In a chip arrangement state in which the transformer chip 70 is arranged on the submount chip 120, a third semiconductor substrate 71 is interposed between the insulating layer 122 of the submount chip 120 and the third element insulating layer 72 of the transformer chip 70.

[0124] According to this configuration, compared to a configuration in which the third element insulating layer 72 is interposed between the insulating layer 122 of the submount chip 120 and the third semiconductor substrate 71 of the transformer chip 70, it is possible to increase the distance between the transformer 40 in the transformer chip 70 and the conductive member outside the transformer chip 70 in the stacking direction (Z direction) of the transformer chip 70 and the submount chip 120. Therefore, it is possible to improve the dielectric strength voltage of the semiconductor device 10.

[0125] (1-8) The insulating layer 122 of the submount chip 120 includes a protective film 123 and a passivation film 124 as a protective layer formed on the surface side of the insulating layer 122. In the chip arrangement state, the third semiconductor substrate 71 is in contact with the passivation film 124.

[0126] According to this configuration, the thickness of the insulating layer 122 can be made thicker than in a configuration in which the protective film 123 and the passivation film 124 are omitted from the insulating layer 122. This allows a large distance to be secured between the transformer 40 in the transformer chip 70 and the conductive member outside the transformer chip 70 in the stacking direction (Z direction) of the transformer chip 70 and the submount chip 120. This allows the dielectric strength of the semiconductor device 10 to be improved.

[0127] (1-9) The transformer 40 includes an outer coil 100 and an inner coil 110 disposed in a third element insulating layer 72. In a plan view, the inner coil 110 is disposed inside the outer coil 100 so as not to overlap with the outer coil 100.

[0128] According to this configuration, the inner coil 110 and the outer coil 100 do not overlap in a plan view, so even if the wiring width of each of the outer coil 100 and the inner coil 110 is increased, the opposing area of ​​the outer coil 100 and the inner coil 110 does not change. In other words, the capacitance value of the parasitic capacitor between the outer coil 100 and the inner coil 110 does not change. Therefore, the wiring resistance value of each coil can be reduced without increasing the capacitance value of the parasitic capacitor between the coils.

[0129] (1-10) Both the outer coil 100 and the inner coil 110 are disposed on the side farther away from the third semiconductor substrate 71 than the center of the third element insulating layer 72 in the thickness direction (Z direction). According to this configuration, compared to a configuration in which both the outer coil 100 and the inner coil 110 are disposed closer to the third semiconductor substrate 71 than the center in the thickness direction (Z direction) of the third element insulating layer 72, the distance between the transformer 40 in the transformer chip 70 and the conductive member outside the transformer chip 70 can be made larger in the stacking direction (Z direction) of the transformer chip 70 and the submount chip 120. Therefore, the dielectric strength of the semiconductor device 10 can be improved.

[0130] In addition, compared to a configuration in which both the outer coil 100 and the inner coil 110 are disposed closer to the third semiconductor substrate 71 than the center of the third element insulating layer 72 in the Z direction, the distance between the outer coil 100 and the inner coil 110 and the third semiconductor substrate 71 in the Z direction can be made larger. Therefore, the magnetic flux generated in the outer coil 100 and the inner coil 110 is less likely to pass through the third semiconductor substrate 71. This makes it possible to suppress the generation of eddy currents caused by the magnetic flux penetrating the third semiconductor substrate 71. Therefore, it is possible to suppress the decrease in efficiency of magnetic coupling caused by eddy currents.

[0131] (1-11) The inner coil 110 and the outer coil 100 are disposed at the same position relative to each other in the Z direction. According to this configuration, the inner coil 110 and the outer coil 100 can be formed using a common mask when manufacturing the transformer chip 70. Therefore, compared with a configuration in which the inner coil 110 and the outer coil 100 are disposed at different positions in the Z direction, the manufacturing process of the transformer chip 70 can be simplified, and the manufacturing cost of the transformer chip 70 can be reduced.

[0132] <Second embodiment> A semiconductor device 10 of the second embodiment will be described with reference to Fig. 9. The semiconductor device 10 of the second embodiment differs from the semiconductor device 10 of the first embodiment mainly in the configuration of the third element insulating layer 72 of the transformer chip 70. Below, differences from the first embodiment will be described in detail, and components common to the first embodiment will be denoted by the same reference numerals and their description will be omitted.

[0133] Fig. 9 shows a cross-sectional structure of a specific insulator 72UA and its periphery in the third element insulating layer 72 of the transformer chip 70. The cross-sectional position in Fig. 9 is the same as the cross-sectional position in Fig. 6 of the first embodiment.

[0134] As shown in FIG. 9, the third element insulating layer 72 of the transformer chip 70 includes a specific insulator 72UA in which the outer coil 100 and the inner coil 110 are provided, and a cover insulating film 72UB that covers the outer coil 100 and the inner coil 110 from the Z direction.

[0135] The cover insulating film 72UB is composed of the first insulating film 72P. The cover insulating film 72UB is in contact with the second insulating film 72Q of the specific insulator 72UA. In one example, the cover insulating film 72UB is in contact with the outer coil 100 and the inner coil 110.

[0136] The third element insulating layer 72 includes a plurality of isolation insulating films 78A and a plurality of cover-side isolation insulating films 78B. Here, the second insulating film 72Q directly below the specific insulator 72UA is referred to as a "second insulating film 72QA," and the second insulating film 72Q formed on the cover insulating film 72UB is referred to as a "second insulating film 72QB."

[0137] In a surface direction perpendicular to the Z direction, a plurality of grooves 72V are formed between the outer coil 100 and the inner coil 110 in the first insulating film 72P of the specific insulator 72UA. In the second embodiment, each groove 72V is a rectangular groove that penetrates the first insulating film 72P of the specific insulator 72UA in the Z direction and forms a concave shape in the second insulating film 72QA. Each groove 72V is formed in a ring shape in a plan view. In one example, the plurality of grooves 72V are formed in a concentric shape in a plan view. In one example, the centers of the plurality of grooves 72V are concentric with the centers of the outer coil 100 and the inner coil 110. In this way, the plurality of grooves 72V separate the first insulating film 72P of the specific insulator 72UA between the outer coil 100 and the inner coil 110 in a direction perpendicular to the Z direction.

[0138] A second insulating film 72Q of a specific insulator 72UA is filled in the grooves 72V. This forms a plurality of isolation insulating films 78A. That is, each isolation insulating film 78A is formed of a second insulating film 72Q containing SiO2. In this way, between the outer coil 100 and the inner coil 110, the first insulating film 72P formed of SiN is separated by the isolation insulating film 78A formed of SiO2. That is, the first insulating film 72P between the outer coil 100 and the inner coil 110 is separated by a second insulating film 72Q (isolation insulating film 78A) having a smaller dielectric constant than the first insulating film 72P. A plurality of first insulating films 72P between the outer coil 100 and the inner coil 110 are provided at a distance from each other in a direction perpendicular to the Z direction. A separation insulating film 78A (second insulating film 72Q) is interposed between the plurality of first insulating films 72P. Since each groove 72V is formed in an annular shape, each isolation insulating film 78A provided in each groove 72V is formed in an annular shape in a planar view. When a plurality of grooves 72V are formed in a concentric shape in a planar view, the plurality of isolation insulating films 78A are formed in a concentric shape in a planar view. In this manner, the first insulating film 72P and the second insulating film 72Q are alternately arranged between the outer coil 100 and the inner coil 110 in a direction perpendicular to the Z direction.

[0139] In a surface direction perpendicular to the Z direction, a plurality of grooves 72W are formed in the cover insulating film 72UB between the outer coil 100 and the inner coil 110. In the second embodiment, each groove 72W is a rectangular groove that penetrates the cover insulating film 72UB in the Z direction and forms a concave shape in the second insulating film 72Q of the specific insulator 72UA. Each groove 72W is formed in a ring shape in a plan view. In one example, the plurality of grooves 72W are formed in a concentric shape in a plan view. In one example, the centers of the plurality of grooves 72W are concentric with the centers of the outer coil 100 and the inner coil 110. In this way, the cover insulating film 72UB is provided between the outer coil 100 and the inner coil 110 at a distance in a direction perpendicular to the Z direction by the plurality of grooves 72W.

[0140] In one example, the width dimension of each groove 72W is equal to the width dimension of each groove 72V. Furthermore, the width dimensions of the multiple grooves 72W are equal to each other. Furthermore, the width dimensions of the multiple grooves 72V are equal to each other. Here, the width dimension of each groove 72V, 72W can be defined by the distance between the side surfaces constituting each groove 72V, 72W in a direction perpendicular to the Z direction.

[0141] A second insulating film 72QB is buried in the grooves 72W. This forms a plurality of cover-side isolation insulating films 78B. That is, each cover-side isolation insulating film 78B is formed by the second insulating film 72QB containing SiO2. In this manner, the cover insulating film 72UB made of SiN is separated between the outer coil 100 and the inner coil 110 by the cover-side isolation insulating film 78B made of SiO2. That is, the cover insulating film 72UB is separated between the outer coil 100 and the inner coil 110 by the second insulating film 72Q (cover-side isolation insulating film 78B) having a smaller dielectric constant than the cover insulating film 72UB. A plurality of cover insulating films 72UB between the outer coil 100 and the inner coil 110 are provided at a distance from each other in a direction perpendicular to the Z direction. A cover-side isolation insulating film 78B (second insulating film 72QB) is interposed between the plurality of cover insulating films 72UB. Since each groove 72W is formed in an annular shape, each cover-side isolation insulating film 78B provided in each groove 72W is formed in an annular shape in plan view. When a plurality of grooves 72W are formed concentrically in plan view, the plurality of cover-side isolation insulating films 78B are formed concentrically in plan view. In this manner, the cover insulating film 72UB (first insulating film 72P) and the cover-side isolation insulating film 78B (second insulating film 72Q) are alternately arranged in the direction perpendicular to the Z direction between the outer coil 100 and the inner coil 110 of the cover insulating film 72UB.

[0142] When the width of each groove 72W is equal to the width of each groove 72V, the width of each cover-side isolation insulating film 78B is equal to the width of each isolation insulating film 78A. When the widths of the grooves 72W are equal to each other, the widths of the cover-side isolation insulating films 78B are equal to each other. When the widths of the grooves 72V are equal to each other, the widths of the isolation insulating films 78A are equal to each other. Here, the width of the isolation insulating film 78A can be defined by the distance between the side surfaces of the isolation insulating film 78A that contact the side surfaces that constitute the groove 72V in the direction perpendicular to the Z direction. The width of the cover-side isolation insulating film 78B can be defined by the distance between the side surfaces of the cover-side isolation insulating film 78B that contact the side surfaces that constitute the groove 72W in the direction perpendicular to the Z direction.

[0143] The number of the grooves 72V, 72W can be changed arbitrarily. In the second embodiment, the grooves 72V, 72W are arranged at positions where they overlap each other in a plan view, but this is not limited thereto. The grooves 72V, 72W may be arranged at positions different from each other in a plan view. In other words, the number of the isolation insulating films 78A and the number of the cover-side isolation insulating films 78B can be changed arbitrarily. In the second embodiment, the isolation insulating films 78A and the cover-side isolation insulating films 78B are arranged at positions where they overlap each other in a plan view, but this is not limited thereto. The isolation insulating films 78A and the cover-side isolation insulating films 78B may be arranged at positions different from each other in a plan view.

[0144] The widths of the grooves 72V and 72W can be changed arbitrarily. In one example, the widths of the grooves 72V and 72W can be different from each other. That is, the widths of the isolation insulating film 78A and the cover-side isolation insulating film 78B can be different from each other. In one example, the width of at least one of the grooves 72V can be different from the width of the remaining grooves 72V. That is, the width of at least one of the isolation insulating films 78A can be different from the width of the remaining isolation insulating films 78A. In one example, the width of at least one of the grooves 72W can be different from the width of the remaining grooves 72W. That is, the width of at least one of the cover-side isolation insulating films 78B can be different from the width of the remaining cover-side isolation insulating films 78B. In addition, the shapes of the grooves 72V and 72W are not limited to a rectangular concave shape and can be changed arbitrarily. In one example, the grooves 72V and 72W can be V-shaped.

[0145] [Effects of the second embodiment] According to the semiconductor device 10 of the second embodiment, the following effects can be obtained. (2-1) The third element insulating layer 72 includes an insulating layer stack structure 72T in which a plurality of insulators 72U are stacked, each of which includes a first insulating film 72P containing silicon nitride and a second insulating film 72Q containing silicon oxide stacked on the first insulating film 72P. The inner coil 110 and the outer coil 100 are provided to penetrate a specific insulator 72UA that is a specific insulator 72U. The third element insulating layer 72 includes a cover insulating film 72UB that is formed of the first insulating film 72P and contacts the second insulating film 72Q of the specific insulator 72UA so as to cover the inner coil 110 and the outer coil 100. A portion of the first insulating film 72P of the specific insulator 72UA between the inner coil 110 and the outer coil 100 includes a plurality of isolation insulating films 78A that are spaced apart in a direction perpendicular to the Z direction. A portion of the cover insulating film 72UB between the inner coil 110 and the outer coil 100 includes a plurality of cover-side isolation insulating films 78B that are spaced apart in a direction perpendicular to the Z direction. Each of the multiple isolation insulating films 78A and the cover-side isolation insulating film 78B is made of a second insulating film 72Q.

[0146] According to this configuration, in the portion of the first insulating film 72P of the specific insulator 72UA between the inner coil 110 and the outer coil 100, the multiple isolation insulating films 78A and the second insulating film 72Q are alternately arranged. Therefore, the interface distance (interface distance) between the inner coil 110 and the outer coil 100 can be made large. That is, the insulation distance between the inner coil 110 and the outer coil 100 can be made large. Also, in the portion of the cover insulating film 72UB between the inner coil 110 and the outer coil 100, the multiple cover-side isolation insulating films 78B and the second insulating film 72Q are alternately arranged. Therefore, the interface distance between the inner coil 110 and the outer coil 100 can be made large. That is, the insulation distance between the inner coil 110 and the outer coil 100 can be made large. Therefore, the dielectric strength voltage of the semiconductor device 10 can be improved while suppressing the size increase of the transformer chip 70.

[0147] (2-2) Each of the spaces between the isolation insulating films 78A and each of the cover-side isolation insulating films 78B are formed in an annular shape. According to this configuration, the second insulating film 72Q interposed between the plurality of isolation insulating films 78A is formed in an annular shape, and the second insulating film 72Q interposed between the plurality of cover-side isolation insulating films 78B is formed in an annular shape. Therefore, in the portion between the inner coil 110 and the outer coil 100, the interface distance between the inner coil 110 and the outer coil 100 can be made large over the entire circumference of the inner coil 110.

[0148] <Third embodiment> A semiconductor device 10 according to a third embodiment will be described with reference to Figures 10 to 14. The semiconductor device 10 according to the third embodiment differs from the semiconductor device 10 according to the first embodiment mainly in the configuration of the transformer chip 70. Below, differences from the first embodiment will be described in detail, and components common to the first embodiment will be denoted by the same reference numerals and their description will be omitted.

[0149] (Circuit configuration of semiconductor device) FIG. 10 diagrammatically illustrates a circuit configuration of a semiconductor device 10 according to the third embodiment. As shown in FIG. 10, in the semiconductor device 10, a transformer 40 provided between the transmitting circuit 21 of the first circuit 20 and the receiving circuit 31 of the second circuit 30 includes first to third coils 41 to 43. The first coil 41 is electrically connected to the transmitting circuit 21 as in the first embodiment. The second coil 42 and the third coil 43 are electrically connected to each other. The second coil 42 and the third coil 43 are electrically connected to the receiving circuit 31. The first coil 41, the second coil 42, and the third coil 43 are electrically insulated from each other and configured to be magnetically coupled.

[0150] (Configuration of Semiconductor Device) FIG. 11 diagrammatically illustrates an example of the planar structure of the semiconductor device 10 of FIG. As shown in Fig. 11, the semiconductor device 10 includes a first chip 50 including a first circuit 20 shown in Fig. 10, a second chip 60 including a second circuit 30 shown in Fig. 10, and a transformer chip 70 including first to third coils 41 to 43 shown in Fig. 10. The transformer chip 70 is disposed on a submount chip 120, similar to the first embodiment. Furthermore, the semiconductor device 10 includes a first lead frame 80, a second lead frame 90, and a sealing resin 200, similar to the first embodiment.

[0151] Unlike the first embodiment, the two first intermediate pads 56 of the first chip 50 are disposed in the center in the Y direction on the chip surface 50S of the first chip 50. The two first intermediate pads 56 are arranged at the same position as each other in the X direction and spaced apart from each other in the Y direction.

[0152] Unlike the first embodiment, the two second intermediate pads 66 of the second chip 60 are disposed in the center in the Y direction of the chip surface 60S of the second chip 60. The two second intermediate pads 66 are disposed at one of both ends in the X direction of the chip surface 60S that is closer to the first chip 50. The two second intermediate pads 66 are arranged at the same position as each other in the X direction and spaced apart from each other in the Y direction.

[0153] The transformer chip 70 includes first to sixth transformer pads 151 to 156. Both the first transformer pad 151 and the second transformer pad 152 are disposed closer to the chip side surface 70A than the third to sixth transformer pads 153 to 156 in a plan view. In one example, both the first transformer pad 151 and the second transformer pad 152 are disposed at the end closer to the chip side surface 70A among both ends in the X direction of the chip surface 70S. Both the first transformer pad 151 and the second transformer pad 152 are disposed at the center of the chip surface 70S in the Y direction. In one example, the first transformer pad 151 and the second transformer pad 152 are disposed at the same position in the Y direction as the two first intermediate pads 56 of the first chip 50 in a plan view.

[0154] The third to sixth transformer pads 153 to 156 are arranged in the center of the chip surface 70S in the X direction. The third to sixth transformer pads 153 to 156 are arranged at the same positions in the X direction and spaced apart from each other in the Y direction. Both the third transformer pad 153 and the fourth transformer pad 154 are arranged closer to the chip side surface 70C of the chip surface 70S in the Y direction. Both the fifth transformer pad 155 and the sixth transformer pad 156 are arranged closer to the chip side surface 70D of the chip surface 70S in the Y direction. A detailed description of the electrical connection structure of the first to sixth transformer pads 151 to 156, the first chip 50, and the second chip 60 will be given later.

[0155] (Internal structure of the transformer chip) An example of the internal configuration of the transformer chip 70 will be described with reference to FIGS. Fig. 12 is a schematic diagram showing the planar structure of the inside of the transformer chip 70. Fig. 13 is a schematic diagram showing the cross-sectional structure along the line F13-F13 in Fig. 12. Fig. 14 is a schematic diagram showing the cross-sectional structure along the line F14-F14 in Fig. 12. For convenience, an outer coil 130 and an inner coil 140, which will be described later, are shown by solid lines in Fig. 12.

[0156] As shown in FIG. 12, the transformer chip 70 includes an outer coil 130 and an inner coil 140. The outer coil 130 corresponds to the first coil 41 shown in FIG. 10. The inner coil 140 includes a first inner coil 141 corresponding to the second coil 42 shown in FIG. 10, and a second inner coil 142 corresponding to the third coil 43 shown in FIG. 10. As shown in FIG. 13, each of the outer coil 130, the first inner coil 141, and the second inner coil 142 is embedded in a third element insulating layer 72. Here, both the outer coil 130 and the inner coil 140 are examples of an "insulating element".

[0157] 12, the outer coil 130 includes a first outer coil 131 and a second outer coil 132. The first outer coil 131 includes a first end 131A and a second end 131B opposite the first end 131A. The second outer coil 132 includes a first end 132A and a second end 132B opposite the first end 132A. The second end 131B of the first outer coil 131 and the second end 132B of the second outer coil 132 are electrically connected to each other.

[0158] Each of the first outer coil 131 and the second outer coil 132 is formed in a circular spiral shape in a plan view. The first outer coil 131 and the second outer coil 132 are wound so that when a current flows from a first end of one of the first outer coil 131 and the second outer coil 132 to a first end of the other outer coil, magnetic fluxes in opposite directions are generated. In one example, the first outer coil 131 and the second outer coil 132 are symmetrical in a plan view. In the third embodiment, the first outer coil 131 and the second outer coil 132 are point-symmetrical in a plan view.

[0159] In the first outer coil 131 having a spiral shape, the first end 131A is disposed inside the spiral, and the second end 131B is disposed outside the spiral. That is, the first outer coil 131 is wound in a spiral shape with the first end 131A as the inner circumferential end and the second end 131B as the outer circumferential end. Similarly, in the second outer coil 132 having a spiral shape, the first end 132A is disposed inside the spiral, and the second end 132B is disposed outside the spiral. That is, the second outer coil 132 is wound in a spiral shape with the first end 132A as the inner circumferential end and the second end 132B as the outer circumferential end. The first outer coil 131 and the second outer coil 132 are electrically connected to each other at their second ends 131B and 132B, which are the outer circumferential ends. In one example, the first outer coil 131 and the second outer coil 132 are integrated together.

[0160] As shown in FIG. 13 and FIG. 14, the first outer coil 131 and the second outer coil 132 of the outer coil 130 are disposed at the same position in the Z direction. Both the first outer coil 131 and the second outer coil 132 are disposed closer to the third element surface 72S than the center in the Z direction of the third element insulating layer 72. In the third embodiment, both the first outer coil 131 and the second outer coil 132 are provided in the insulator 72U immediately below the uppermost insulator 72U of the insulating layer stack structure 72T of the third element insulating layer 72. The outer coil 130 is formed of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W. The outer coil 130 of the third embodiment is formed of a material containing Cu. In addition, the first outer coil 131 and the second outer coil 132 may be provided not in the uppermost insulator 72U of the insulating layer stack structure 72T of the third element insulating layer 72, but, for example, in an insulator 72U directly below the uppermost insulator 72U.

[0161] 12, the first inner coil 141 is disposed inside the first outer coil 131. The first inner coil 141 is disposed so as not to overlap with the first outer coil 131 in a plan view. The first inner coil 141 is disposed spaced apart from the first outer coil 131 in a planar direction perpendicular to the Z direction. In one example, the winding center of the first inner coil 141 and the winding center of the first outer coil 131 are concentric.

[0162] The second inner coil 142 is disposed inside the second outer coil 132. The second inner coil 142 is disposed so as not to overlap with the second outer coil 132 in a plan view. The second inner coil 142 is disposed spaced apart from the second outer coil 132 in a planar direction perpendicular to the Z direction. In one example, the winding center of the second inner coil 142 and the winding center of the second outer coil 132 are concentric. The first inner coil 141 and the second inner coil 142 are arranged at the same position as each other in the X direction and spaced apart from each other in the Y direction.

[0163] Each of the first inner coil 141 and the second inner coil 142 is formed in a circular spiral shape in a planar view. In one example, the first inner coil 141 and the second inner coil 142 have a symmetric shape in a planar view. In the third embodiment, the first inner coil 141 and the second inner coil 142 have a point-symmetric shape in a planar view.

[0164] A current flows through the first inner coil 141 in a direction corresponding to the direction of magnetic flux generated by a current flowing through the first outer coil 131. Similarly, a current flows through the second inner coil 142 in a direction corresponding to the direction of magnetic flux generated by a current flowing through the second outer coil 132.

[0165] The first inner coil 141 includes a first end 141A and a second end 141B opposite to the first end 141A. In the spiral-shaped first inner coil 141, the first end 141A is disposed on the inside of the spiral, and the second end 141B is disposed on the outside of the spiral. In other words, the first inner coil 141 is wound in a spiral shape with the first end 141A as the inner circumferential end and the second end 141B as the outer circumferential end.

[0166] The second inner coil 142 includes a first end 142A and a second end 142B opposite to the first end 142A. In the spiral-shaped second inner coil 142, the first end 142A is disposed on the inside of the spiral, and the second end 142B is disposed on the outside of the spiral. In other words, the second inner coil 142 is wound in a spiral shape with the first end 142A as the inner circumferential end and the second end 142B as the outer circumferential end.

[0167] As shown in FIG. 13 and FIG. 14, the first inner coil 141 and the second inner coil 142 are disposed at the same position in the Z direction. Both the first inner coil 141 and the second inner coil 142 are disposed closer to the third element surface 72S than the center in the Z direction of the third element insulating layer 72. In the third embodiment, both the first inner coil 141 and the second inner coil 142 are provided in the insulator 72U immediately below the uppermost insulator 72U of the insulating layer stack structure 72T of the third element insulating layer 72. In this manner, both the first inner coil 141 and the second inner coil 142 are disposed at the same position in the Z direction as both the first outer coil 131 and the second outer coil 132. The inner coil 140 is formed of a material including one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W. In one example, the inner coil 140 is formed of the same material as the outer coil 130. The inner coil 140 of the third embodiment is formed of a material containing Cu. The first inner coil 141 and the second inner coil 142 may be provided not in the uppermost insulator 72U of the insulating layer stack structure 72T of the third element insulating layer 72 but in, for example, the insulator 72U immediately below the uppermost insulator 72U.

[0168] As shown in FIG. 12, the transformer chip 70 includes first to sixth openings 70SA to 70SF. The first to sixth openings 70SA to 70SF are provided in the third element insulating layer 72. The first opening 70SA is an opening that exposes the first transformer pad 151. The second opening 70SB is an opening that exposes the second transformer pad 152. The third opening 70SC is an opening that exposes the first end 141A of the first inner coil 141. The fourth opening 70SD is an opening that exposes the second end 141B of the first inner coil 141. The fifth opening 70SE is an opening that exposes the first end 142A of the second inner coil 142. The sixth opening 70SF is an opening that exposes the second end 142B of the second inner coil 142.

[0169] The first transformer pad 151 and the second transformer pad 152 are pads electrically connected to the outer coil 130. The first transformer pad 151 is electrically connected to a first end 131A of the first outer coil 131 of the outer coil 130. The second transformer pad 152 is electrically connected to a first end 132A of the second outer coil 132 of the outer coil 130. In one example, the first transformer pad 151 and the second transformer pad 152 are disposed at the same position as the outer coil 130 in the Z direction.

[0170] The third to sixth transformer pads 153 to 156 may be pads electrically connected to the inner coil 140. In the third embodiment, the third to sixth transformer pads 153 to 156 are formed by a part of the inner coil 140. More specifically, the third transformer pad 153 is formed by exposing the first end 141A of the first inner coil 141 of the inner coil 140 in the Z direction from the third opening 70SC of the third element insulating layer 72. The fourth transformer pad 154 is formed by exposing the second end 141B of the first inner coil 141 in the Z direction from the fourth opening 70SD of the third element insulating layer 72. The fifth transformer pad 155 is formed by exposing the first end 142A of the second inner coil 142 of the inner coil 140 in the Z direction from the fifth opening 70SE of the third element insulating layer 72. The sixth transformer pad 156 is configured by exposing the second end 142B of the second inner coil 142 from the sixth opening 70SF of the third element insulating layer 72 in the Z direction.

[0171] 12 and 14, the transformer chip 70 includes a first wiring section 160 and a second wiring section 170. The first wiring section 160 is a wiring that electrically connects the first end 131A of the first outer coil 131 and the first transformer pad 151. The second wiring section 170 is a wiring that electrically connects the first end 132A of the second outer coil 132 and the second transformer pad 152. The first wiring section 160 and the second wiring section 170 are formed of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W.

[0172] As shown in FIG. 12 and FIG. 13, the first wiring portion 160 includes a connection wiring 161 and vias 162 and 163. The connection wiring 161 extends in the X direction. The connection wiring 161 includes a first end 161A and a second end 161B as both ends in the X direction. The connection wiring 161 extends from the first end 131A of the first outer coil 131 to the first transformer pad 151 in a plan view. The connection wiring 161 is disposed closer to the third semiconductor substrate 71 than the first outer coil 131 in the Z direction. The first end 161A of the connection wiring 161 is disposed at a position overlapping the first end 131A of the first outer coil 131 in a plan view. The first end 161A is electrically connected to the first end 131A of the first outer coil 131 by the via 162. The second end 161B of the connection wiring 161 is disposed at a position overlapping the first transformer pad 151 in a plan view. The second end 161B is electrically connected to the first transformer pad 151 by a via 163.

[0173] 12 and 14, the second wiring section 170 includes a connection wiring 171 and vias 172, 173. The connection wiring 171 and the vias 172, 173 are arranged in the same manner as the connection wiring 161 and the vias 162, 163 of the first wiring section 160. The connection wiring 171 includes a first end 171A and a second end 171B, similar to the connection wiring 171. The first end 171A of the connection wiring 171 is electrically connected to the first end 132A of the second outer coil 132 by the via 172, and the second end 171B of the connection wiring 171 is electrically connected to the second transformer pad 152 by the via 173.

[0174] 11 and 12, the first transformer pad 151 and the second transformer pad 152 are individually connected to the two first intermediate pads 56 of the first chip 50 by two first intermediate wires WA. The two first intermediate wires WA are provided outside the transformer chip 70. In the following description, for convenience, the two first intermediate wires WA are referred to as the "first intermediate wire WA1" and the "first intermediate wire WA2."

[0175] Since one of the two first intermediate pads 56 is electrically connected to the transmission circuit 21, for example, the first transformer pad 151 formed by the first end 131A of the first outer coil 131 of the outer coil 130 is electrically connected to the transmission circuit 21 (see FIG. 10) by the first intermediate wire WA1. Therefore, it can be said that the first outer coil 131 is electrically connected to the first chip 50 by the first intermediate wire WA1. The other of the two first intermediate pads 56 is connected to the ground GND1 (see FIG. 10). Therefore, for example, the second transformer pad 152 formed by the first end 132A of the second outer coil 132 of the outer coil 130 is electrically connected to the ground GND1 by the first intermediate wire WA2. Therefore, it can be said that the second outer coil 132 is electrically connected to the first chip 50 by the first intermediate wire WA2. Here, the first intermediate wire WA1 is an example of a "first chip connecting wire", and the first intermediate wire WA2 is an example of a "second chip connecting wire".

[0176] The first end 141A of the first inner coil 141 and the first end 142A of the second inner coil 142 of the inner coil 140 are electrically connected by a wire WC. As a result, when a current generated in the first inner coil 141 flows through the wire WC to the second inner coil 142, the direction of the current is the same as the direction of the current generated in the second inner coil 142. Here, the wire WC is an example of a "coil connecting wire."

[0177] The fourth transformer pad 154 and the sixth transformer pad 156 are individually connected to the two second intermediate pads 66 of the second chip 60 by two second intermediate wires WB. Each of the two second intermediate wires WB is provided outside the transformer chip 70. In the following description, for convenience, the two second intermediate wires WB are referred to as a "second intermediate wire WB1" and a "second intermediate wire WB2."

[0178] Since one of the two second intermediate pads 66 is electrically connected to the receiving circuit 31, for example, the fourth transformer pad 154 formed by the second end 141B of the first inner coil 141 is electrically connected to the receiving circuit 31 (see FIG. 10) by the second intermediate wire WB1. Therefore, it can be said that the first inner coil 141 is electrically connected to the second chip 60 by the second intermediate wire WB1. The other of the two second intermediate pads 66 is connected to the ground GND2 (see FIG. 10). Therefore, for example, the sixth transformer pad 156 formed by the second end 142B of the second inner coil 142 is electrically connected to the ground GND2. Therefore, it can be said that the second inner coil 142 is electrically connected to the second chip 60 by the second intermediate wire WB2. Here, the second intermediate wire WB1 is an example of a "third chip connecting wire", and the second intermediate wire WB2 is an example of a "fourth chip connecting wire".

[0179] [Effects of the third embodiment] According to the semiconductor device 10 of the third embodiment, the following effects can be obtained. (3-1) The outer coil 130 includes a first outer coil 131 and a second outer coil 132 having first ends 131A, 132A and second ends 131B, 132B, respectively. The second end 131B of the first outer coil 131 and the second end 132B of the second outer coil 132 are connected to each other. The first outer coil 131 and the second outer coil 132 are configured such that when a current flows from the first end of one of the first outer coil 131 and the second outer coil 132 to the first end of the other outer coil, magnetic fluxes in opposite directions are generated. The inner coil 140 includes a first inner coil 141 and a second inner coil 142 having first ends 141A, 142A and second ends 141B, 142B, respectively. In a planar view, the first inner coil 141 is positioned inside the first outer coil 131 so as not to overlap with the first outer coil 131, and the second inner coil 142 is positioned inside the second outer coil 132 so as not to overlap with the second outer coil 132.

[0180] According to this configuration, it is possible to suppress the spread of the magnetic flux generated by the outer coil 130. This makes it possible to increase the amount of magnetic flux crossing the inner coil 140. Therefore, it is possible to improve the efficiency of the magnetic coupling between the outer coil 130 and the inner coil 140. As a result, it is possible to improve the transfer characteristics between the outer coil 130 and the inner coil 140.

[0181] (3-2) The first inner coil 141 and the second inner coil 142 are connected to each other by a wire WC provided outside the transformer chip 70. This configuration can simplify the configuration of the transformer chip 70 compared to a configuration in which the first inner coil 141 and the second inner coil 142 are electrically connected by wiring provided in the transformer chip 70. In other words, since a layer for providing wiring is not required in the third element insulating layer 72, a dedicated mask for providing wiring is not required when manufacturing the third element insulating layer 72. Therefore, the manufacturing process of the transformer chip 70 can be simplified, and the cost of the transformer chip 70 can be reduced.

[0182] (3-3) The first outer coil 131 is electrically connected to the first chip 50 by a first intermediate wire WA1 provided outside the transformer chip 70. The second outer coil 132 is electrically connected to the first chip 50 by a first intermediate wire WA2 provided outside the transformer chip 70.

[0183] According to this configuration, the connection structure between the first outer coil 131 and the first chip 50 can be simplified, for example, compared to a configuration in which the first outer coil 131 and the first chip 50 are connected by wiring provided in the transformer chip 70. Also, the connection structure between the second outer coil 132 and the first chip 50 can be simplified, for example, compared to a configuration in which the second outer coil 132 and the first chip 50 are connected by wiring provided in the transformer chip 70. In addition, since it is not necessary to position the arrangement position of the transformer chip 70 with high precision relative to the first chip 50, the semiconductor device 10 can be easily manufactured.

[0184] (3-4) Each of the first outer coil 131, the second outer coil 132, the first inner coil 141, and the second inner coil 142 is disposed closer to the third element surface 72S of the third element insulating layer 72 in the Z direction.

[0185] According to this configuration, the distance between each of the first outer coil 131, the second outer coil 132, the first inner coil 141, and the second inner coil 142 and the third semiconductor substrate 71 in the Z direction can be made larger than in a configuration in which two coils are arranged opposite each other in the Z direction. Therefore, the magnetic flux generated in the first outer coil 131, the second outer coil 132, the first inner coil 141, and the second inner coil 142 is less likely to pass through the third semiconductor substrate 71. This makes it possible to suppress the generation of eddy currents caused by the magnetic flux penetrating the third semiconductor substrate 71. Therefore, it is possible to suppress the decrease in efficiency of magnetic coupling caused by eddy currents.

[0186] (3-5) The first outer coil 131, the second outer coil 132, the first inner coil 141, and the second inner coil 142 are disposed at the same positions relative to one another in the Z direction. According to this configuration, the first outer coil 131, the second outer coil 132, the first inner coil 141, and the second inner coil 142 can be formed using a common mask when manufacturing the transformer chip 70. Therefore, compared to a configuration in which the first outer coil 131, the second outer coil 132, the first inner coil 141, and the second inner coil 142 are disposed at different positions in the Z direction, the manufacturing process of the transformer chip 70 can be simplified, and the manufacturing cost of the transformer chip 70 can be reduced.

[0187] <Example of change> The above-described embodiments can be modified as follows: The following modified examples can be combined with each other as long as no technical contradiction occurs.

[0188] [Combination of embodiments] The first and second embodiments may be implemented in combination with each other. The second and third embodiments may be implemented in combination with each other.

[0189] [Modification of the first embodiment] (Example of transformer tip change) In the first embodiment, the configuration of the transformer chip 70 can be modified as desired. The transformer chip 70 may be modified, for example, as in the first to fifth modified examples.

[0190] (First modified example) 15, the transformer chip 70 of the first modified example includes two outer coils 100 arranged spaced apart in the Z direction in the third element insulating layer 72, and a via 181 connecting the two outer coils 100. The two outer coils 100 are connected in parallel by the via 181. The two outer coils 100 are arranged in positions overlapping each other in a plan view. The wiring portion 77 is arranged closer to the third semiconductor substrate 71 than the two outer coils 100.

[0191] According to this configuration, it is possible to reduce the wiring resistance value of the outer coil 100 by connecting two outer coils 100 in parallel. Note that the number of outer coils 100 may be three or more.

[0192] Moreover, the transformer chip 70 of the first modified example includes two inner coils 110 arranged in the third element insulating layer 72 at a distance from each other in the Z direction, and a via 182 connecting the two inner coils 110. The two inner coils 110 are connected in parallel by the via 182. The two inner coils 110 are arranged in positions overlapping each other in a plan view. With this configuration, the wiring resistance value of the inner coil 110 can be reduced by connecting the two inner coils 110 in parallel. The number of inner coils 110 may be three or more.

[0193] (Second modified example) As shown in FIG. 16 and FIG. 17, the transformer chip 70 of the second modified example includes an outer coil 100, an outer coil 103 connected to the outer coil 100, and a via 104 connecting the outer coils 100 and 103. The outer coil 103 is arranged so as to overlap the outer coil 100 in a plan view. The outer coil 103 includes coil portions 103A and 103B arranged to be spaced apart in the Z direction. The coil portions 103A and 103B are connected in series between the outer coil 100 and the wiring portion 77 by the via 104. More specifically, the coil portion 103B is arranged closer to the outer coil 100 than the coil portion 103A in the Z direction. The coil portion 103B is connected in series to the outer coil 100. The coil portion 103B is electrically connected to the first end 101 of the outer coil 100 by the via 104. The coil portion 103A is connected in series to the coil portion 103B. The coil portion 103A is electrically connected to the wiring portion 77. That is, the coil portion 103A is electrically connected to the first transformer pad 75A. On the other hand, the second end 102 of the outer coil 100 constitutes the first transformer pad 75B.

[0194] In the transformer chip 70 of the second modified example, the outer coil 103 is connected between the wiring portion 77 and the outer coil 100. Therefore, the number of turns of the outer coil consisting of the outer coil 100 and the outer coil 103 can be increased. This makes it possible to increase the amount of magnetic flux generated by this outer coil.

[0195] The coil portions 103A and 103B of the outer coil 103 may be connected in parallel. Also, a plurality of outer coils 100 may be provided as in a first modified example shown in FIG. 15. In this case, the plurality of outer coils 100 may be connected in parallel. In this way, by connecting the outer coil 100 and the outer coil 103 in parallel, it is possible to increase the number of turns and suppress an increase in the wiring resistance value.

[0196] As shown in FIG. 16, in the transformer chip 70 of the second modified example, the inner coil 110 is disposed at the same position in the Z direction as the coil portion 103B of the outer coil 103. The configuration of the inner coil 110 can be changed arbitrarily. The position of the inner coil 110 in the Z direction can be changed arbitrarily. In one example, the inner coil 110 may be disposed at the same position in the Z direction as the outer coil 100. In one example, the inner coil 110 may be disposed at the same position in the Z direction as the coil portion 103A of the outer coil 103.

[0197] A first end 111 of the inner coil 110 is electrically connected to the second transformer pad 76A by a via 182. The second transformer pad 76A is disposed closer to the chip surface 70S than the inner coil 110 in the Z direction. In one example, the second transformer pad 76A is disposed in the same position as the outer coil 100.

[0198] (Third modified example) As shown in Fig. 18, the transformer chip 70 of the third modified example is different from the transformer chip 70 of the second modified example shown in Fig. 16 in that the coil portion 103B of the outer coil 103 is arranged so as not to overlap with both the outer coil 100 and the coil portion 103A in a plan view. By arranging the outer coil 100 and the coil portions 103A and 103B in this way, the facing area between the outer coil 100 and the coil portion 103A and the coil portion 103B in the Z direction is reduced. Therefore, the capacitance of the parasitic capacitor caused by this facing area can be reduced.

[0199] (Fourth modified example) 19, in the transformer chip 70 of the fourth modified example, the inner coil 110 may be disposed at a position different from that of the outer coil 100 in the Z direction. In the example shown in FIG. 19, the inner coil 110 is disposed closer to the third semiconductor substrate 71 than the outer coil 100 in the Z direction. With this configuration, the opposing area between the outer coil 100 and the inner coil 110 in the direction perpendicular to the Z direction is reduced. Therefore, the capacitance of the parasitic capacitor caused by this opposing area can be reduced.

[0200] In the transformer chip 70 of the fourth modified example, the outer coil 100 may be disposed closer to the third semiconductor substrate 71 than the inner coil 110 in the Z direction. In this case, the inner coil 110 is disposed, for example, in the uppermost insulator 72U of the insulating layer stack structure 72T of the third element insulating layer 72. The inner coil 110 may also be disposed, for example, in the insulator 72U immediately below the uppermost insulator 72U of the insulating layer stack structure 72T.

[0201] (Fifth modified example) The shapes of the outer coil 100 and the inner coil 110 in a plan view can be changed as desired. In one example, the outer coil 100 and the inner coil 110 may be formed in a rectangular shape in a plan view. In one example, the outer coil 100 and the inner coil 110 may be formed in a rectangular shape with rounded corners in a circular arc shape in a plan view. In one example, the outer coil 100 and the inner coil 110 may be formed in an elliptical shape in a plan view.

[0202] [Modification of the second embodiment] In the second embodiment, the configuration of the third element insulating layer 72 of the transformer chip 70 can be changed arbitrarily. In one example, as shown in FIG. 20, the first insulating film 72P of the specific insulator 72UA includes a plurality of recesses 72PC that open toward the cover insulating film 72UB. The plurality of recesses 72PC are arranged at a distance from each other in a direction perpendicular to the Z direction. In one example, each recess 72PC is formed in a ring shape in a plan view. In one example, the plurality of recesses 72PC are formed in a concentric shape in a plan view. In one example, the centers of the plurality of recesses 72PC are concentric with, for example, the center of the outer coil 100 and the center of the inner coil 110. The second insulating film 72Q of the specific insulator 72UA is embedded in the plurality of recesses 72PC. The cover insulating film 72UB includes a plurality of cover side recesses 72PD that open toward the first insulating film 72P of the specific insulator 72UA. The plurality of cover side recesses 72PD are arranged at a distance from each other in a surface direction perpendicular to the Z direction. In one example, the cover side recesses 72PD are formed concentrically in a plan view. The centers of the cover side recesses 72PD are concentric with the centers of the outer coil 100 and the inner coil 110, for example. The second insulating film 72Q of the specific insulator 72UA is embedded in the cover side recesses 72PD. This configuration provides the same effects as those of (2-1) and (2-2) of the second embodiment.

[0203] In the second embodiment, the number of isolation insulating films 78A and the number of cover-side isolation insulating films 78B can be changed arbitrarily. In one example, the number of isolation insulating films 78A may be one. In one example, the number of cover-side isolation insulating films 78B may be one. In another example, the number of isolation insulating films 78A may be different from the number of cover-side isolation insulating films 78B.

[0204] In the second embodiment, the multiple isolation insulating films 78A may be disposed at positions different from the multiple cover side isolation insulating films 78B. That is, in a plan view, the multiple isolation insulating films 78A may be disposed at positions not overlapping with the multiple cover side isolation insulating films 78B. In one example, in a plan view, the multiple isolation insulating films 78A may be disposed at positions partially overlapping with the multiple cover side isolation insulating films 78B.

[0205] In the second embodiment, it is sufficient that the isolation insulating film 78A penetrates the first insulating film 72P of the specific insulator 72UA in the Z direction, and the concave shape of the second insulating film 72Q may be omitted. In the second embodiment, the cover-side isolation insulating film 78B only needs to penetrate the cover insulating film 72UB in the Z direction, and the concave shape of the second insulating film 72Q of the specific insulator 72UA may be omitted.

[0206] [Modification of the third embodiment] In the third embodiment, the configuration of the transformer chip 70 can be arbitrarily modified. The transformer chip 70 may be modified, for example, as in the first to fifth modified examples shown in Figs. 21 to 27. Figs. 21, 22, 24, and 25 are schematic cross-sectional views of the transformer chip 70. The cross-sectional positions of Figs. 21, 22, 24, and 25 are the same as the cross-sectional position of the line F13-F13 in Fig. 12 of the third embodiment. Fig. 23 is a schematic exploded perspective view of a portion of the transformer chip 70. Figs. 26 and 27 are schematic planar views of the transformer chip 70. For convenience, the outer coil 130 and the inner coil 140 are shown by solid lines in Figs. 26 and 27.

[0207] (First modified example) As shown in FIG. 21, the transformer chip 70 of the first modified example includes two outer coils 130 arranged at a distance from each other in the Z direction, and vias 191 and 192 connecting the two outer coils 130. The two first outer coils 131 arranged at a distance from each other in the Z direction are connected in parallel by the vias 191. The two second outer coils 132 arranged at a distance from each other in the Z direction are connected in parallel by the vias 192. According to this configuration, the wiring resistance value of the outer coil 130 can be reduced by connecting the two first outer coils 131 in parallel and connecting the two second outer coils 132 in parallel. Note that three or more outer coils 130 may be provided at a distance from each other in the Z direction.

[0208] The inner coil 140 includes two inner coils 140 spaced apart from each other in the Z direction, and vias 193, 194 connecting the two inner coils 140. The first inner coils 141 spaced apart from each other in the Z direction are connected in parallel by the vias 193. The second inner coils 142 spaced apart from each other in the Z direction are connected in parallel by the vias 194. With this configuration, the two first inner coils 141 are connected in parallel, and the two second inner coils 142 are connected in parallel, thereby reducing the wiring resistance value of the inner coil 140. Note that three or more inner coils 140 may be provided spaced apart from each other in the Z direction.

[0209] (Second modified example) As shown in Figures 22 and 23, in the second modified example transformer chip 70, the outer coil 130 includes a first outer coil 131 and a second outer coil 132, a third outer coil 133 connected to the first outer coil 131, and a fourth outer coil 134 connected to the second outer coil 132.

[0210] The third outer coil 133 is disposed so as to overlap with the first outer coil 131 in a plan view. The third outer coil 133 includes coil portions 133A and 133B disposed spaced apart from each other in the Z direction. The coil portions 133A and 133B are connected in series between the first end 131A of the first outer coil 131 and the first wiring portion 160.

[0211] The fourth outer coil 134 is disposed so as to overlap with the second outer coil 132 in a plan view. The fourth outer coil 134 includes coil portions 134A and 134B disposed spaced apart from each other in the Z direction. The coil portions 134A and 134B are connected in series between the first end 132A of the second outer coil 132 and the second wiring portion 170.

[0212] In the transformer chip 70 of the second modification, the third outer coil 133 and the first outer coil 131 are connected in series between the first wiring section 160 and the second outer coil 132. In addition, the second outer coil 132 and the fourth outer coil 134 are connected in series between the first outer coil 131 and the second wiring section 170. Therefore, the number of turns of the outer coil 130 disposed on the outside of each of the first inner coil 141 and the second inner coil 142 can be increased. Therefore, the amount of magnetic flux generated by the outer coil 130 can be increased.

[0213] The third outer coil 133 (coil portions 133A, 133B) arranged at a distance from each other in the Z direction may be connected in parallel. Similarly, the fourth outer coil 134 (coil portions 134A, 134B) arranged at a distance from each other in the Z direction may be connected in parallel. In this way, by connecting the third outer coil 133 and the fourth outer coil 134 in parallel, the number of turns of the outer coil 130 can be increased and an increase in the wiring resistance value can be suppressed.

[0214] As shown in FIG. 22, in the transformer chip 70 of the second modification, the inner coil 140 is disposed at the same position in the Z direction as the coil portion 133B of the third outer coil 133 and the coil portion 134B of the fourth outer coil 134. The configuration of the inner coil 140 can be changed arbitrarily. The position of the inner coil 140 in the Z direction can be changed arbitrarily. In one example, the inner coil 140 may be disposed at the same position as the outer coil 130 in the Z direction. In one example, the inner coil 140 may be disposed at the same position in the Z direction as the coil portion 133A of the third outer coil 133 and the coil portion 134A of the fourth outer coil 134.

[0215] (Third modified example) The third modified example of the transformer chip 70 shown in Fig. 24 is different from the second modified example of the transformer chip 70 shown in Fig. 22 in that the coil portion 133B of the third outer coil 133 is arranged so as not to overlap the first outer coil 131, the second outer coil 132, and the coil portion 133A in a plan view. By arranging the first outer coil 131 and the third outer coil 133 in this manner, the facing area between the coil portion 133B and the first outer coil 131, the second outer coil 132, and the coil portion 133A in the Z direction is reduced. Therefore, the capacitance of the parasitic capacitor caused by this facing area can be reduced.

[0216] (Fourth modified example) In the transformer chip 70 of the fourth modification shown in FIG. 25, the first inner coil 141 and the second inner coil 142 of the inner coil 140 are disposed at positions different from the first outer coil 131 and the second outer coil 132 of the outer coil 130 in the Z direction. In one example, the first inner coil 141 and the second inner coil 142 are disposed closer to the third semiconductor substrate 71 than the first outer coil 131 and the second outer coil 132 in the Z direction. With this configuration, the opposing area between the inner coil 140 and the outer coil 130 in the direction perpendicular to the Z direction is reduced. Therefore, the capacitance of the parasitic capacitor caused by this opposing area can be reduced.

[0217] In the transformer chip 70 of the fourth modified example, the outer coil 130 may be disposed closer to the third semiconductor substrate 71 than the inner coil 140 in the Z direction. In this case, the inner coil 140 is disposed, for example, in the uppermost insulator 72U of the insulating layer stack structure 72T of the third element insulating layer 72. The inner coil 140 may also be disposed, for example, in the insulator 72U immediately below the uppermost insulator 72U of the insulating layer stack structure 72T.

[0218] (Fifth modified example) The shapes of the outer coil 130 and the inner coil 140 in plan view can be changed arbitrarily. In one example, as shown in FIG. 26, each of the outer coil 130 and the inner coil 140 may be formed in a rectangular shape in plan view. In another example, as shown in FIG. 27, each of the outer coil 130 and the inner coil 140 may be formed in a rectangular shape with rounded corners in a circular arc shape in plan view. Although not shown, each of the outer coil 130 and the inner coil 140 may be formed in an elliptical shape in plan view.

[0219] The positional relationship in the Z direction between the first outer coil 131 and the second outer coil 132 of the outer coil 130 can be changed arbitrarily. In one example, the first outer coil 131 and the second outer coil 132 may be disposed at different positions in the Z direction. In this case, the second end 131B of the first outer coil 131 and the second end 132B of the second outer coil 132 may be formed to overlap each other in a plan view. The second end 131B of the first outer coil 131 and the second end 132B of the second outer coil 132 may be directly electrically connected to each other.

[0220] The positional relationship in the Z direction between the first inner coil 141 and the second inner coil 142 of the inner coil 140 can be changed arbitrarily. In one example, the first inner coil 141 and the second inner coil 142 may be disposed at different positions from each other in the Z direction.

[0221] The first end 141A of the first inner coil 141 and the first end 142A of the second inner coil 142 of the inner coil 140 may be connected to the second chip 60. The second chip 60 may include a pad connected to the first end 141A of the first inner coil 141 of the inner coil 140 and a pad connected to the first end 142A of the second inner coil 142. The second circuit 30 of the second chip 60 may include a first receiving circuit that receives a signal transmitted by the first inner coil 141 and a second receiving circuit that receives a signal transmitted by the second inner coil 142.

[0222] A configuration in which the third embodiment is combined with the second embodiment will be described with reference to Fig. 28 and Fig. 29. Fig. 28 shows an enlarged cross-sectional structure of the first outer coil 131, the first inner coil 141, and the surrounding areas. Fig. 29 shows an enlarged cross-sectional structure of the second outer coil 132, the second inner coil 142, and the surrounding areas.

[0223] As shown in FIG. 28, a plurality of first grooves 72V1 are provided in a portion between the first inner coil 141 and the first outer coil 131 of the first insulating film 72P of the specific insulator 72UA in which the first inner coil 141, the second inner coil 142 (see FIG. 29), the first outer coil 131, and the second outer coil 132 (see FIG. 29) are provided. The plurality of first grooves 72V1 are provided at a distance from each other in a direction perpendicular to the Z direction. Each of the first grooves 72V1 is formed in an annular shape in a planar view. In one example, the plurality of first grooves 72V1 are formed in a concentric shape in a planar view. In one example, the centers of the plurality of first grooves 72V1 are concentric with the centers of the first outer coil 131 and the first inner coil 141. In this manner, by the multiple first grooves 72V1, the first insulating film 72P of the specific insulator 72UA is provided between the first outer coil 131 and the first inner coil 141, spaced apart in a direction perpendicular to the Z direction.

[0224] Each first groove 72V1 is a rectangular groove that penetrates the first insulating film 72P of the specific insulator 72UA in the Z direction and forms a concave shape in the second insulating film 72QA directly below the specific insulator 72UA. The second insulating film 72Q of the specific insulator 72UA enters each first groove 72V1. This forms a plurality of first isolation insulating films 78A1. In this way, the portion of the first insulating film 72P of the specific insulator 72UA between the first inner coil 141 and the first outer coil 131 includes a plurality of first isolation insulating films 78A1 that are spaced apart from each other in a direction perpendicular to the Z direction. That is, the first insulating film 72P between the first outer coil 131 and the first inner coil 141 is separated by the second insulating film 72Q (first isolation insulating film 78A1) that has a smaller dielectric constant than the first insulating film 72P. Since each first groove 72V1 is formed in an annular shape, each first isolation insulating film 78A1 provided in each first groove 72V1 is formed in an annular shape in a planar view. When a plurality of first grooves 72V1 are formed in a concentric shape in a planar view, the plurality of first isolation insulating films 78A1 are formed in a concentric shape in a planar view. In this manner, the first insulating film 72P and the second insulating film 72Q are alternately arranged between the first outer coil 131 and the first inner coil 141 in a direction perpendicular to the Z direction.

[0225] As shown in FIG. 29, a plurality of second grooves 72V2 are provided in a portion of the first insulating film 72P of the specific insulator 72UA between the second inner coil 142 and the second outer coil 132. The plurality of second grooves 72V2 are provided at a distance from each other in a direction perpendicular to the Z direction. Each of the second grooves 72V2 is formed in an annular shape in a plan view. In one example, the plurality of second grooves 72V2 are formed in a concentric shape in a plan view. In one example, the centers of the plurality of second grooves 72V2 are concentric with the centers of the second outer coil 132 and the second inner coil 142. In this way, the plurality of second grooves 72V2 allow the first insulating film 72P of the specific insulator 72UA to be provided at a distance from each other in a direction perpendicular to the Z direction between the second outer coil 132 and the second inner coil 142.

[0226] Each second groove 72V2 is a rectangular groove that penetrates the first insulating film 72P of the specific insulator 72UA in the Z direction and forms a concave shape in the second insulating film 72QA directly below the specific insulator 72UA. The second insulating film 72Q of the specific insulator 72UA enters each second groove 72V2. This forms a plurality of second isolation insulating films 78A2. In this way, the portion between the second inner coil 142 and the second outer coil 132 of the first insulating film 72P of the specific insulator 72UA includes a plurality of second isolation insulating films 78A2 that are spaced apart from each other in a direction perpendicular to the Z direction. That is, the first insulating film 72P between the second outer coil 132 and the second inner coil 142 is separated by the second insulating film 72Q (second isolation insulating film 78A2) that has a smaller dielectric constant than the first insulating film 72P. Since each second groove 72V2 is formed in an annular shape, each second isolation insulating film 78A2 provided in each second groove 72V2 is formed in an annular shape in a planar view. When a plurality of second grooves 72V2 are formed in a concentric shape in a planar view, the plurality of second isolation insulating films 78A2 are formed in a concentric shape in a planar view. In this manner, the first insulating film 72P and the second insulating film 72Q are alternately arranged between the second outer coil 132 and the second inner coil 142 in a direction perpendicular to the Z direction.

[0227] As shown in FIG. 28, a plurality of first grooves 72W1 are provided in a portion of the cover insulating film 72UB that contacts the second insulating film 72Q of the specific insulator 72UA between the first inner coil 141 and the first outer coil 131. The plurality of first grooves 72W1 are provided at a distance from each other in a direction perpendicular to the Z direction. Each of the first grooves 72W1 is formed in an annular shape in a plan view. In one example, the plurality of first grooves 72W1 are formed in a concentric shape in a plan view. In one example, the centers of the plurality of first grooves 72W1 are concentric with the centers of the first outer coil 131 and the first inner coil 141. In this way, the cover insulating film 72UB is provided at a distance from each other in a direction perpendicular to the Z direction between the first outer coil 131 and the first inner coil 141 by the plurality of first grooves 72W1.

[0228] Each first groove 72W1 is a rectangular groove penetrating the cover insulating film 72UB in the Z direction and formed in a concave shape in the second insulating film 72Q of the specific insulator 72UA. The second insulating film 72QB on the cover insulating film 72UB is inserted into each first groove 72W1. This constitutes a plurality of first cover side isolation insulating films 78B1. In this manner, the portion of the cover insulating film 72UB between the first inner coil 141 and the first outer coil 131 includes a plurality of first cover side isolation insulating films 78B1 provided at a distance from each other in a direction perpendicular to the Z direction. That is, the cover insulating film 72UB between the first outer coil 131 and the first inner coil 141 is separated by the second insulating film 72Q (first cover side isolation insulating film 78B1) having a smaller dielectric constant than the first insulating film 72P. Since each first groove 72W1 is formed in an annular shape, each first cover side isolation insulating film 78B1 provided in each first groove 72W1 is formed in an annular shape in a plan view. When the first grooves 72W1 are formed concentrically in a plan view, the first cover side isolation insulating films 78B1 are formed concentrically in a plan view. In this manner, the first insulating films 72P and the second insulating films 72Q are alternately arranged between the first outer coil 131 and the first inner coil 141 in a direction perpendicular to the Z direction.

[0229] As shown in FIG. 29, a plurality of second grooves 72W2 are provided in a portion between the second inner coil 142 and the second outer coil 132 of the cover insulating film 72UB in contact with the second insulating film 72Q of the specific insulator 72UA. The plurality of second grooves 72W2 are provided at a distance from each other in a direction perpendicular to the Z direction. Each of the second grooves 72W2 is formed in an annular shape in a plan view. In one example, the plurality of second grooves 72W2 are formed in a concentric shape in a plan view. In one example, the centers of the plurality of second grooves 72W2 are concentric with the centers of the second outer coil 132 and the second inner coil 142. In this way, the plurality of second grooves 72W2 provide the cover insulating film 72UB at a distance from each other in a direction perpendicular to the Z direction between the second outer coil 132 and the second inner coil 142.

[0230] Each second groove 72W2 is a rectangular groove penetrating the cover insulating film 72UB in the Z direction and formed in the second insulating film 72Q of the specific insulator 72UA in a concave shape. The second insulating film 72QB on the cover insulating film 72UB is inserted into each second groove 72W2. This constitutes a plurality of second cover side isolation insulating films 78B2. In this manner, the portion of the cover insulating film 72UB between the second inner coil 142 and the second outer coil 132 includes a plurality of second cover side isolation insulating films 78B2 provided at a distance from each other in a direction perpendicular to the Z direction. That is, the cover insulating film 72UB between the second outer coil 132 and the second inner coil 142 is separated by the second insulating film 72Q (second cover side isolation insulating film 78B2) having a smaller dielectric constant than the first insulating film 72P. Since each second groove 72W2 is formed in an annular shape, each second cover side isolation insulating film 78B2 provided in each second groove 72W2 is formed in an annular shape in a plan view. When the second grooves 72W2 are formed concentrically in a plan view, the second cover side isolation insulating films 78B2 are formed concentrically in a plan view. In this manner, the first insulating films 72P and the second insulating films 72Q are alternately arranged between the second outer coil 132 and the second inner coil 142 in a direction perpendicular to the Z direction.

[0231] In one example, the width dimension of each first groove 72W1 is equal to the width dimension of each first groove 72V1. Moreover, the width dimensions of the multiple first grooves 72W1 are equal to each other. Moreover, the width dimensions of the multiple first grooves 72V1 are equal to each other. In one example, the width dimension of each second groove 72W2 is equal to the width dimension of each second groove 72V2. Moreover, the width dimensions of the multiple second grooves 72W2 are equal to each other. Moreover, the width dimensions of the multiple second grooves 72V2 are equal to each other. Here, the width dimension of each first groove 72V1, 72W1 can be defined by the distance between the side surfaces constituting each first groove 72V1, 72W1 in a direction perpendicular to the Z direction. The width dimension of each second groove 72V2, 72W2 can be defined by the distance between the side surfaces constituting each second groove 72V2, 72W2 in a direction perpendicular to the Z direction.

[0232] When the width of each first groove 72W1 is equal to the width of each first groove 72V1, the width of each first cover side isolation insulating film 78B1 is equal to the width of each first isolation insulating film 78A1. When the widths of the first grooves 72W1 are equal to each other, the widths of the first cover side isolation insulating films 78B1 are equal to each other. When the widths of the first grooves 72V1 are equal to each other, the widths of the first isolation insulating films 78A1 are equal to each other. Here, the width of the first isolation insulating film 78A1 can be defined by the distance between the side surfaces of the first isolation insulating film 78A1 that contact the side surfaces constituting the first groove 72V1 in the direction perpendicular to the Z direction. The width of the first cover side isolation insulating film 78B1 can be defined by the distance between the side surfaces of the first cover side isolation insulating film 78B1 that contact the side surfaces constituting the first groove 72W1 in the direction perpendicular to the Z direction.

[0233] When the width of each second groove 72W2 is equal to the width of each second groove 72V2, the width of each second cover side isolation insulating film 78B2 is equal to the width of each second isolation insulating film 78A2. When the widths of the second grooves 72W2 are equal to each other, the widths of the second cover side isolation insulating films 78B2 are equal to each other. When the widths of the second grooves 72V2 are equal to each other, the widths of the second isolation insulating films 78A2 are equal to each other. Here, the width of the second isolation insulating film 78A2 can be defined by the distance between the side surfaces of the second isolation insulating film 78A2 that contact the side surfaces constituting the second groove 72V2 in the direction perpendicular to the Z direction. The width of the second cover side isolation insulating film 78B2 can be defined by the distance between the side surfaces of the second cover side isolation insulating film 78B2 that contact the side surfaces constituting the second groove 72W2 in the direction perpendicular to the Z direction.

[0234] According to this configuration, in the portion of the first insulating film 72P of the specific insulator 72UA between the first inner coil 141 and the first outer coil 131, the multiple first isolation insulating films 78A1 and the second insulating film 72Q are alternately arranged. Therefore, the interface distance between the first inner coil 141 and the first outer coil 131 can be made large. That is, the insulation distance between the first inner coil 141 and the first outer coil 131 can be made large. In the portion of the first insulating film 72P of the specific insulator 72UA between the second inner coil 142 and the second outer coil 132, the multiple second isolation insulating films 78A2 and the second insulating film 72Q are alternately arranged. Therefore, the interface distance between the second inner coil 142 and the second outer coil 132 can be made large. That is, the insulation distance between the second inner coil 142 and the second outer coil 132 can be made large.

[0235] In addition, in the portion of the cover insulating film 72UB between the first inner coil 141 and the first outer coil 131, a plurality of first cover side isolation insulating films 78B1 and the second insulating film 72Q are alternately arranged. Therefore, the interface distance between the first inner coil 141 and the first outer coil 131 can be made large. That is, the insulation distance between the first inner coil 141 and the first outer coil 131 can be made large. In the portion of the cover insulating film 72UB between the second inner coil 142 and the second outer coil 132, a plurality of second cover side isolation insulating films 78B2 and the second insulating film 72Q are alternately arranged. Therefore, the interface distance between the second inner coil 142 and the second outer coil 132 can be made large. That is, the insulation distance between the second inner coil 142 and the second outer coil 132 can be made large. Therefore, the dielectric strength of the semiconductor device 10 can be improved while suppressing the size of the transformer chip 70.

[0236] The number of the first grooves 72V1, 72W1 can be changed arbitrarily. In addition, in the modification shown in FIG. 28 and FIG. 29, the first grooves 72V1, 72W1 are arranged at positions where they overlap each other in a plan view, but this is not limited thereto. The first grooves 72V1, 72W1 may be arranged at positions different from each other in a plan view. In other words, the number of the first isolation insulating films 78A1 and the number of the first cover side isolation insulating films 78B1 can be changed arbitrarily. In addition, in the modification shown in FIG. 28 and FIG. 29, the first isolation insulating films 78A1 and the first cover side isolation insulating films 78B1 are arranged at positions where they overlap each other in a plan view, but this is not limited thereto. The first isolation insulating films 78A1 and the first cover side isolation insulating films 78B1 may be arranged at positions different from each other in a plan view.

[0237] The number of the second grooves 72V2, 72W2 can be changed arbitrarily. In the modification shown in FIG. 28 and FIG. 29, the second grooves 72V2, 72W2 are arranged at positions where they overlap each other in a plan view, but this is not limited thereto. The second grooves 72V2, 72W2 may be arranged at positions different from each other in a plan view. In other words, the number of the second isolation insulating films 78A2 and the number of the second cover side isolation insulating films 78B2 can be changed arbitrarily. In the modification shown in FIG. 28 and FIG. 29, the second isolation insulating films 78A2 and the second cover side isolation insulating films 78B2 are arranged at positions where they overlap each other in a plan view, but this is not limited thereto. The second isolation insulating films 78A2 and the second cover side isolation insulating films 78B2 may be arranged at positions different from each other in a plan view.

[0238] The widths of the first grooves 72V1 and 72W1 can be changed arbitrarily. In one example, the widths of the first grooves 72V1 and the first grooves 72W1 may be different from each other. That is, the widths of the first isolation insulating film 78A1 and the first cover-side isolation insulating film 78B1 may be different from each other. In one example, the width of at least one of the first grooves 72V1 may be different from the widths of the remaining first grooves 72V1. That is, the width of at least one of the first isolation insulating films 78A1 may be different from the widths of the remaining first isolation insulating films 78A1. In one example, the width of at least one of the first grooves 72W1 may be different from the widths of the remaining first grooves 72W1. That is, at least one of the first cover side isolation insulating films 78B1 may have a width dimension different from that of the remaining first cover side isolation insulating films 78B1. The shape of the first grooves 72V1 and 72W1 is not limited to a rectangular recessed shape and may be changed as desired. In one example, the first grooves 72V1 and 72W1 may be V-shaped.

[0239] The widths of the second grooves 72V2 and 72W2 can be changed arbitrarily. In one example, the widths of the second grooves 72V2 and 72W2 may be different from each other. That is, the widths of the second isolation insulating film 78A2 and the second cover-side isolation insulating film 78B2 may be different from each other. In one example, the width of at least one of the second grooves 72V2 may be different from the widths of the remaining second grooves 72V2. That is, the width of at least one of the second isolation insulating films 78A2 may be different from the widths of the remaining second isolation insulating films 78A2. In one example, the width of at least one of the second grooves 72W2 may be different from the widths of the remaining second grooves 72W2. That is, at least one of the second cover side isolation insulating films 78B2 may have a width dimension different from that of the remaining second cover side isolation insulating films 78B2. The shape of the second grooves 72V2 and 72W2 is not limited to a rectangular recessed shape and may be changed as desired. In one example, the second grooves 72V2 and 72W2 may be V-shaped.

[0240] The first isolation insulating film 78A1, the second isolation insulating film 78A2, the first cover side isolation insulating film 78B1, and the second cover side isolation insulating film 78B2 in the modified example shown in Figures 28 and 29 may be changed to the configurations shown in Figures 30 and 31. Figure 30 shows an enlarged cross-sectional structure of the first outer coil 131, the first inner coil 141, and the surrounding areas. Figure 31 shows an enlarged cross-sectional structure of the second outer coil 132, the second inner coil 142, and the surrounding areas.

[0241] As shown in FIG. 30, a portion of the first insulating film 72P of the specific insulator 72UA between the first inner coil 141 and the first outer coil 131 is provided with a plurality of first recesses 79A that open toward the cover insulating film 72UB. Each of the first recesses 79A is formed in an annular shape in a plan view. In one example, the plurality of first recesses 79A are formed in a concentric shape in a plan view. In one example, the centers of the plurality of first recesses 79A are concentric with the centers of the first inner coil 141 and the first outer coil 131. The second insulating film 72Q of the specific insulator 72UA is inserted into each of the first recesses 79A. As shown in FIG. 31, a portion of the first insulating film 72P of the specific insulator 72UA between the second inner coil 142 and the second outer coil 132 is provided with a plurality of second recesses 79B that open toward the cover insulating film 72UB. Each of the second recesses 79B is formed in an annular shape in a plan view. In one example, the plurality of second recesses 79B are formed in a concentric shape in a plan view. In one example, the centers of the multiple second recesses 79B are concentric with the center of the second inner coil 142 and the center of the second outer coil 132. The second insulating film 72Q of the specific insulator 72UA fills each of the second recesses 79B.

[0242] As shown in FIG. 30, a portion of the cover insulating film 72UB between the first inner coil 141 and the first outer coil 131 is provided with a plurality of first cover side recesses 79C that open toward the first insulating film 72P of the specific insulator 72UA. Each of the first cover side recesses 79C is formed in a ring shape in a plan view. In one example, the plurality of first cover side recesses 79C are formed in a concentric shape in a plan view. In one example, the centers of the plurality of first cover side recesses 79C are concentric with the centers of the first inner coil 141 and the first outer coil 131. The second insulating film 72Q of the specific insulator 72UA is inserted into each of the first cover side recesses 79C. As shown in FIG. 31, a portion of the cover insulating film 72UB between the second inner coil 142 and the second outer coil 132 is provided with a plurality of second cover side recesses 79D that open toward the first insulating film 72P of the specific insulator 72UA. Each of the second cover side recesses 79D is formed in a ring shape in a plan view. In one example, the second cover side recesses 79D are formed concentrically in a plan view. In one example, the centers of the second cover side recesses 79D are concentric with the centers of the second inner coil 142 and the second outer coil 132. The second insulating film 72Q of the specific insulator 72UA is inserted into each of the second cover side recesses 79D.

[0243] According to this configuration, similarly to the modified example shown in FIG. 28 and FIG. 29, the interface distance between the first inner coil 141 and the first outer coil 131 can be increased by the multiple first recesses 79A and the multiple first cover side recesses 79C. That is, the insulation distance between the first inner coil 141 and the first outer coil 131 can be increased. In addition, the interface distance between the second inner coil 142 and the second outer coil 132 can be increased by the multiple second recesses 79B and the multiple second cover side recesses 79D. That is, the insulation distance between the second inner coil 142 and the second outer coil 132 can be increased. Therefore, the dielectric strength of the semiconductor device 10 can be improved while suppressing the size increase of the transformer chip 70.

[0244] [Modifications common to the first to third embodiments] In each embodiment, the configuration of the third element insulating layer 72 of the transformer chip 70 can be changed as desired. In one example, the first insulating film 72P may be omitted from the third element insulating layer 72. In other words, the insulating layer stack structure 72T of the third element insulating layer 72 may be formed by stacking a plurality of second insulating films 72Q.

[0245] (Example of changing the submount chip) The configuration of the submount chip 120 can be changed arbitrarily. The submount chip 120 may be changed, for example, as in the first to fifth modified examples. For convenience, the sealing resin 200 (see FIG. 3) is omitted in FIGS. 32 to 34.

[0246] (First modified example) Fig. 32 shows a schematic cross-sectional structure of the first chip 50, the second chip 60, the transformer chip 70, the submount chip 120, and the surrounding areas in the first modified example. The cross-sectional position in Fig. 32 is the same as the cross-sectional position in Fig. 8 of the first embodiment.

[0247] As shown in FIG. 32, the thickness of the sub-mount chip 120 may be thicker than the thickness of the first chip 50. The thickness of the sub-mount chip 120 may be thicker than the thickness of the second chip 60. In one example, the thickness of the insulating layer 122 is increased to increase the thickness of the sub-mount chip 120. The thickness of the insulating layer 122 is thicker than the thickness of the first element insulating layer 52 of the first chip 50. The thickness of the insulating layer 122 is thicker than the thickness of the second element insulating layer 62 of the second chip 60. This increases the distance in the Z direction between the inner coil 110 and the conductive bonding material SD interposed between the sub-mount chip 120 and the first die pad 81, thereby improving the dielectric strength of the semiconductor device 10.

[0248] In the first modified example, the insulating layer 122 of the submount chip 120 may be configured in such a way that a plurality of first insulating films 122P and a plurality of second insulating films 122Q are alternately laminated one by one, as in the first embodiment. This can reduce warping of the submount chip 120. Therefore, the transformer chip 70 can be stably disposed on the submount chip 120.

[0249] (Second modified example) Fig. 33 is a schematic diagram showing a cross-sectional structure of the first chip 50, the second chip 60, the transformer chip 70, the submount chip 120, and the surrounding areas in the second modified example. The cross-sectional position in Fig. 33 is the same as the cross-sectional position in Fig. 8 of the first embodiment.

[0250] 33, the insulating layer 122 of the submount chip 120 may be configured with a plurality of second insulating films 122Q stacked on top of each other. That is, the first insulating film 122P may be omitted from the insulating layer 122. With this configuration, the first insulating film 122P, which has a higher dielectric constant than the second insulating film 122Q, is omitted, so that the dielectric strength of the submount chip 120 can be improved.

[0251] 33, the thickness of the sub-mount chip 120 is thinner than the thickness of the first chip 50. The thickness of the sub-mount chip 120 is thinner than the thickness of the second chip 60. However, since the dielectric strength of the sub-mount chip 120 is improved, even if the thickness of the sub-mount chip 120 is thinner than the thickness of the sub-mount chip 120 of the first embodiment, a decrease in the dielectric strength of the semiconductor device 10 can be suppressed. In addition, the thinner thickness of the sub-mount chip 120 allows the semiconductor device 10 to be made thinner.

[0252] 33, the dimension in the X direction of the submount chip 120 is smaller than the dimension in the X direction of the transformer chip 70. Although not shown, the dimension in the Y direction of the submount chip 120 may be smaller than the dimension in the Y direction of the transformer chip 70. With this configuration, the cost of the submount chip 120 can be reduced by reducing the size of the submount chip 120.

[0253] 33 can be changed arbitrarily. In one example, the X-direction dimension of the submount chip 120 may be equal to the X-direction dimension of the transformer chip 70. In addition, the Y-direction dimension of the submount chip 120 shown in FIG 33 can be changed arbitrarily. In one example, the Y-direction dimension of the submount chip 120 may be equal to the Y-direction dimension of the transformer chip 70.

[0254] (Third modified example) The dimensions in the X direction and the Y direction of the submount chip 120 can be changed arbitrarily. In one example, the dimension in the X direction of the submount chip 120 may be larger than the dimension in the X direction of the transformer chip 70. With this configuration, the transformer chip 70 can be stably arranged on the submount chip 120. In another example, the dimension in the Y direction of the submount chip 120 may be larger than the dimension in the Y direction of the transformer chip 70. With this configuration, the transformer chip 70 can be stably arranged on the submount chip 120.

[0255] (Fourth modified example) Fig. 34 is a schematic diagram showing a cross-sectional structure of the first chip 50, the transformer chip 70, the submount chip 120, and the surrounding areas in the fourth modified example. The cross-sectional position of Fig. 34 is the same as the cross-sectional position of Fig. 8 in the first embodiment.

[0256] 34, the submount chip 120 may be disposed on the first die pad 81 such that the fourth semiconductor substrate 121 is on the transformer chip 70 side with respect to the insulating layer 122. In this case, the transformer chip 70 is disposed on the fourth semiconductor substrate 121. More specifically, the third semiconductor substrate 71 of the transformer chip 70 is in contact with the fourth semiconductor substrate 121.

[0257] (Fifth modified example) At least one of the protective film 123 and the passivation film 124 may be omitted from the submount chip 120.

[0258] (Example of change in the arrangement of the submount chip and the transformer chip) The positional relationship between the submount chip 120 and the transformer chip 70 can be changed arbitrarily. This positional relationship may be changed, for example, as in the first to third modified examples. For convenience, the sealing resin 200 (see FIG. 3) is omitted in FIG. 35 and FIG. 36.

[0259] (First modified example) Fig. 35 shows a schematic cross-sectional structure of the first chip 50, the second chip 60, the transformer chip 70, the submount chip 120, and the surrounding areas in the first modified example. The cross-sectional position of Fig. 35 is the same as the cross-sectional position of Fig. 8 in the first embodiment.

[0260] 35, the transformer chip 70 may be disposed shifted toward the second chip 60 with respect to the submount chip 120. That is, in a plan view, the chip side surface 70B of the transformer chip 70 may be located closer to the second chip 60 than the chip side surface 120B of the submount chip 120. With this configuration, the length of the second intermediate wire WB can be shortened.

[0261] (Second modified example) Fig. 36 is a schematic diagram showing a cross-sectional structure of the first chip 50, the transformer chip 70, the submount chip 120, and the surrounding areas in the second modified example. The cross-sectional position of Fig. 36 is the same as the cross-sectional position of Fig. 8 in the first embodiment.

[0262] As shown in FIG. 36, the transformer chip 70 may be bonded onto the sub-mount chip 120 by an insulating bonding material SDA. That is, an insulating bonding material SDA may be interposed between the transformer chip 70 and the sub-mount chip 120 in the Z direction. According to this configuration, the distance DZ1 between the conductive bonding material SD interposed between the sub-mount chip 120 and the first die pad 81 and the inner coil 110 of the transformer chip 70 in the Z direction can be increased by the thickness of the insulating bonding material SDA. In addition, when an insulating bonding material is interposed between the sub-mount chip 120 and the first die pad 81, the distance DZ2 between the inner coil 110 and the first die pad 81 in the Z direction can be increased by the thickness of the insulating bonding material SDA. Therefore, the dielectric strength of the semiconductor device 10 can be improved.

[0263] (Third modified example) The arrangement of the transformer chip 70 on the submount chip 120 can be changed as desired. In one example, the transformer chip 70 may be arranged on the submount chip 120 such that the third semiconductor substrate 71 is located on the opposite side of the third element insulating layer 72 from the submount chip 120. In this case, the first transformer pads 75A, 75B and the second transformer pads 76A, 76B may be provided on the third semiconductor substrate 71.

[0264] (Example of transformer tip change) The third semiconductor substrate 71 may be omitted from the transformer chip 70. Both the inner coil 110 and the outer coil 100 may be disposed closer to the third semiconductor substrate 71 than the center of the third element insulating layer 72 in the Z direction.

[0265] (Modifications of the semiconductor device) The transformer chip 70 may be disposed on the second die pad 91. In this case, the sub-mount chip 120 is bonded to the second die pad 91 by a conductive bonding material or an insulating bonding material. The transformer chip 70 is disposed on the sub-mount chip 120.

[0266] A plurality of transformer chips 70 may be provided. In one example, as shown in FIG. 37, the transformer chip 70 includes a first transformer chip 70P arranged on the first die pad 81 and a second transformer chip 70Q arranged on the second die pad 91. The first transformer chip 70P includes a first transformer 40P. The second transformer chip 70Q includes a second transformer 40Q. The first transformer 40P and the second transformer 40Q have the same configuration as the transformer 40 of the first embodiment, for example. In this case, the sub-mount chip 120 includes a first sub-mount chip 120P bonded to the first die pad 81 by a conductive bonding material or an insulating bonding material, and a second sub-mount chip 120Q bonded to the second die pad 91 by a conductive bonding material or an insulating bonding material. The first transformer chip 70P is arranged on the first sub-mount chip 120P. The second transformer chip 70Q is arranged on the second sub-mount chip 120Q.

[0267] The second transformer pads 76A, 76B of the first transformer chip 70P and the second transformer pads 76A, 76B of the second transformer chip 70Q are individually connected by a wire WD. This electrically connects the inner coil 110 of the first transformer chip 70P and the inner coil 110 of the second transformer chip 70Q. The first transformer pads 75A, 75B of the second transformer chip 70Q are individually electrically connected to the second intermediate pad 66 of the second chip 60 by a second intermediate wire WB.

[0268] According to this configuration, a double insulation structure is formed by the first transformer 40P and the second transformer 40Q, which can improve the dielectric strength voltage of the semiconductor device 10. Note that the configurations of the first transformer 40P and the second transformer 40Q are not limited to the transformer 40 of the first embodiment, and may be the same as the transformer 40 of the third embodiment, for example.

[0269] The configuration of the transformer 40 provided in the third element insulating layer 72 of the transformer chip 70 can be changed arbitrarily. In one example, the transformer chip 70 may include a first coil 41 and a second coil 42 arranged opposite to each other in the Z direction in the third element insulating layer 72, as shown in FIG. 38, instead of the outer coil 100 (130) and the inner coil 110 (140). The first coil 41 is arranged closer to the third semiconductor substrate 71 than the second coil 42 in the Z direction. In other words, the first coil 41 is arranged closer to the submount chip 120 than the second coil 42 in the Z direction. The first coil 41 is electrically connected to the first transformer pads 75A and 75B. That is, the first coil 41 is electrically connected to the first circuit 20 via the first intermediate wire WA. The second coil 42 is electrically connected to the second transformer pads 76A and 76B. That is, the second coil 42 is electrically connected to the second circuit 30 via the second intermediate wire WB.

[0270] As shown in FIG. 39, the semiconductor device 10 may include a capacitor 210 instead of the transformer 40. In this case, the first circuit 20 and the second circuit 30 may be configured to transmit a signal or power via the capacitor 210. In the example shown in FIG. 39, the capacitor 210 includes a first electrode plate 211 and a second electrode plate 212. The first electrode plate 211 is electrically connected to the first circuit 20. The second electrode plate 212 is electrically connected to the second circuit 30. Here, the capacitor 210 is an example of an "insulating element".

[0271] 40, the semiconductor device 10 includes a capacitor chip 220 instead of the transformer chip 70. The capacitor chip 220 is disposed on the sub-mount chip 120. The sub-mount chip 120 is bonded to the first die pad 81 by, for example, a conductive bonding material SD. Here, the capacitor chip 220 is an example of an "insulating chip".

[0272] The capacitor chip 220 includes a fifth semiconductor substrate 221 and a fifth element insulating layer 222 formed on the fifth semiconductor substrate 221. In one example, the fifth semiconductor substrate 221 has the same configuration as the third semiconductor substrate 71 (see FIG. 5) of the transformer chip 70. In one example, the fifth element insulating layer 222 has the same configuration as the third element insulating layer 72 (see FIG. 5) of the transformer chip 70. The first electrode plate 211 and the second electrode plate 212 of the capacitor 210 are embedded in the fifth element insulating layer 222. The first electrode plate 211 and the second electrode plate 212 are disposed opposite to each other in the Z direction.

[0273] A part of the first electrode plate 211 constitutes the first transformer pad 75A. Therefore, the first electrode plate 211 is electrically connected to the first circuit 20 via the first intermediate wire WA. The second electrode plate 212 is electrically connected to the second transformer pad 76A. Therefore, the second electrode plate 212 is electrically connected to the second circuit 30 via the second intermediate wire WB. In the example shown in FIG. 40, the second electrode plate 212 is disposed closer to the fifth semiconductor substrate 221 than the first electrode plate 211. Note that the positions of the first electrode plate 211 and the second electrode plate 212 in the Z direction can be changed arbitrarily. In one example, the first electrode plate 211 may be disposed closer to the fifth semiconductor substrate 221 than the second electrode plate 212.

[0274] The semiconductor device 10 may include a plurality of first wirings and a plurality of second wirings instead of the first lead frame 80 and the second lead frame 90. That is, the semiconductor device 10 may include a first conductive member and a second conductive member. The first conductive member supports the first chip 50 and is electrically connected to the first chip 50. The first conductive member includes a plurality of first external terminals. The second conductive member supports the second chip 60 and is electrically connected to the second chip 60. The second conductive member includes a plurality of second external terminals. The transformer chip 70 is disposed on either the first conductive member or the second conductive member.

[0275] The semiconductor device 10 is not limited to being configured as a signal transmission device that transmits signals via the transformer 40, and may be configured as a power transmission device that transmits power via the transformer 40.

[0276] FIG. 41 shows an example of a circuit configuration of a power transmission device 300 as a modified example of the semiconductor device 10. The power transmission device 300 may include a control circuit 301, an oscillator 302, a transformer 40, diodes 303 to 306, and a smoothing capacitor 307. The control circuit 301 and the oscillator 302 may be included in the first circuit 20. The first circuit 20 may include the oscillator 302 and may not include the control circuit 301. The diodes 303 to 306 and the smoothing capacitor 307 may be included in the second circuit 30. The second circuit 30 may include the diodes 303 to 306 and may not include the smoothing capacitor 307. The number of diodes included in the second circuit 30 may be changed as appropriate depending on the configuration of the rectifier circuit. In one example, the first chip 50 including the control circuit 301 and the oscillator 302, the transformer chip 70 including the transformer 40, and the second chip 60 including the diodes 303 to 306 and the smoothing capacitor 307 are sealed with the sealing resin 200, similar to the semiconductor device 10 of the first embodiment.

[0277] A DC power supply 311 is connected to the control circuit 301. The oscillator 302 is controlled by the control circuit 301. The oscillator 302 outputs an AC signal. This AC signal is transmitted by the transformer 40. A DC voltage is supplied to the load 312 by the diodes 303-306 and the smoothing capacitor 307. In other words, the power transmission device 300 functions as a DC voltage conversion circuit (DC-DC converter) that converts the voltage of the DC power supply 311 into the operating voltage of the load 312.

[0278] The term "on" as used in this disclosure includes the meanings "on" and "above" unless the context clearly indicates otherwise. Thus, for example, the expression "a first element is disposed on a second element" is intended to mean that in some embodiments, the first element may be disposed directly on the second element in contact with the second element, while in other embodiments, the first element may be disposed above the second element without contacting the second element. In other words, the term "on" does not exclude a structure in which another element is formed between the first element and the second element.

[0279] The Z direction used in this disclosure does not necessarily have to be a vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" of the Z direction described in this specification being "up" and "down" of the vertical direction. For example, the X direction may be a vertical direction, or the Y direction may be a vertical direction.

[0280] <Additional Notes> The technical ideas that can be understood from this disclosure are described below. Note that, for the purpose of aiding understanding, not for the purpose of limitation, the components described in the appendices are given the reference numbers of the corresponding components in the above embodiment. The reference numbers are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numbers.

[0281] [Appendix 1] A first chip (50) including a first semiconductor substrate (51), a first circuit (20) formed on the first semiconductor substrate (51), and a first element insulating layer (52) formed on the first semiconductor substrate (51); a second chip (60) including a second semiconductor substrate (61), a second circuit (30) formed on the second semiconductor substrate (61), and a second element insulating layer (62) formed on the second semiconductor substrate (61), the second chip (60) being disposed apart from the first chip (50) in a first direction (X direction); a sub-mount chip (120) provided separately from the first chip (50) and the second chip (60); a transformer chip (70) including a transformer (40) disposed on the submount chip (120); the first circuit (20) and the second circuit (30) are configured to transmit a signal or power via the transformer (40); The transformer chip (70) is A third semiconductor substrate (71); a third element insulating layer (72) formed on the third semiconductor substrate (71); Including, The transformer (40) is embedded in the third element insulating layer (72), The submount chip (120) is A fourth semiconductor substrate (121); an insulating layer (122) formed on the fourth semiconductor substrate (121); Includes A semiconductor device (10).

[0282] [Appendix 2] The third element insulating layer (72) of the transformer chip (70) includes a structure in which a first insulating film (72P) containing silicon nitride and a second insulating film (72Q) containing silicon oxide are alternately laminated in a plurality of layers. 2. The semiconductor device according to claim 1.

[0283] [Appendix 3] The insulating layer (122) of the submount chip (70) includes a structure in which a first insulating film (122P) containing silicon nitride and a second insulating film (122Q) containing silicon oxide are alternately laminated in a plurality of layers. 3. The semiconductor device according to claim 1 or 2.

[0284] [Appendix 4] The insulating layer (122) of the submount chip (120) includes a structure in which a plurality of insulating films (122Q) containing silicon oxide are laminated. 3. The semiconductor device according to claim 1 or 2.

[0285] [Appendix 5] The thickness of the submount chip (120) is thinner than the thickness of the transformer chip (70). 5. The semiconductor device according to claim 1,

[0286] [Appendix 6] The thickness of the submount chip (120) is equal to or greater than the thickness of the transformer chip (70). 5. The semiconductor device according to claim 1,

[0287] [Appendix 7] The dimension of the submount chip (120) in the first direction (X direction) is smaller than the dimension of the transformer chip (70) in the first direction (X direction). 7. The semiconductor device according to claim 1,

[0288] [Appendix 8] The dimension of the submount chip (120) in the first direction (X direction) is equal to the dimension of the transformer chip (70) in the first direction (X direction). 7. The semiconductor device according to claim 1,

[0289] [Appendix 9] The dimension of the submount chip (120) in the first direction (X direction) is larger than the dimension of the transformer chip (70) in the first direction (X direction). 7. The semiconductor device according to claim 1,

[0290] [Appendix 10] The thickness of the submount chip (120) is equal to or greater than the thickness of the first chip (50) or the thickness of the second chip (60). 10. The semiconductor device according to any one of claims 1 to 9.

[0291] [Appendix 11] The thickness of the submount chip (120) is smaller than the thickness of the first chip (50) or the thickness of the second chip (60). 10. The semiconductor device according to any one of claims 1 to 9.

[0292] [Appendix 12] In a chip arrangement state in which the transformer chip (70) is arranged on the submount chip (120), the third semiconductor substrate (71) is interposed between the insulating layer (122) of the submount chip (120) and the third element insulating layer (72) of the transformer chip (70). 12. The semiconductor device according to claim 1.

[0293] [Appendix 13] The insulating layer (122) of the submount chip (120) includes protective layers (123, 124) formed on a surface side of the insulating layer (122), In the chip arrangement state, the third semiconductor substrate (71) is in contact with the protective layer (124). 13. The semiconductor device according to claim 12.

[0294] [Appendix 14] The transformer (40) includes an outer coil (100) and an inner coil (110) embedded in the third element insulating layer (72); When viewed from the thickness direction (Z direction) of the third element insulating layer (72), the inner coil (110) is disposed inside the outer coil (100) so as not to overlap with the outer coil (100). 14. The semiconductor device according to claim 1, wherein the first and second electrodes are arranged in a first direction.

[0295] [Appendix 15] Both the outer coil (100) and the inner coil (110) are disposed on the side farther from the third semiconductor substrate (71) than the center in the thickness direction (Z direction) of the third element insulating layer (72). 15. The semiconductor device according to claim 14.

[0296] [Appendix 16] The transformer (40) includes an outer coil (100) and an inner coil (110) embedded in the third element insulating layer (72); When viewed from the thickness direction (Z direction) of the third element insulating layer (72), the inner coil (110) is disposed inside the outer coil (100) so as not to overlap with the outer coil (100), The third element insulating layer (72) has a structure in which a plurality of insulators (72U) are stacked, the insulators including a first insulating film (72P) containing silicon nitride and a second insulating film (72Q) containing silicon oxide stacked on the first insulating film (72P), The inner coil (110) and the outer coil (100) are provided so as to penetrate a specific insulator (72UA) that is a specific one of the insulators, the third element insulating layer (72) is formed of the first insulating film (72P) and includes a cover insulating film (72UB) in contact with the second insulating film (72Q) of the specific insulator (72UA) so as to cover the inner coil (110) and the outer coil (100); A portion of the first insulating film (72P) of the specific insulator (72UA) between the inner coil (110) and the outer coil (100) includes a plurality of isolation insulating films (78A) spaced apart in a direction perpendicular to a thickness direction (Z direction) of the third element insulating layer (72), a portion of the cover insulating film (72UB) between the inner coil (110) and the outer coil (100) includes a plurality of cover-side isolation insulating films (78B) spaced apart in a direction perpendicular to the thickness direction (Z direction); Each of the plurality of isolation insulating films (78A) and the plurality of cover-side isolation insulating films (78B) is formed of the second insulating film (72Q). 14. The semiconductor device according to claim 1, wherein the first and second electrodes are arranged in a first direction.

[0297] [Appendix 17] Each of the plurality of isolation insulating films (78A) and the plurality of cover-side isolation insulating films (78B) is formed in an annular shape. 17. The semiconductor device according to claim 16.

[0298] [Appendix 18] The transformer (40) includes an outer coil (100) and an inner coil (110) disposed within the third element insulating layer (72); When viewed from the thickness direction (Z direction) of the third element insulating layer (72), the inner coil (110) is disposed inside the outer coil (100) so as not to overlap with the outer coil (100), The third element insulating layer (72) has a structure in which a plurality of insulators (72U) are stacked, the insulators including a first insulating film (72P) containing silicon nitride and a second insulating film (72Q) containing silicon oxide stacked on the first insulating film (72P), The inner coil (110) and the outer coil (100) are provided so as to penetrate a specific insulator (72UA) that is a specific one of the insulators, the third element insulating layer (72) is formed of the first insulating film (72P) and includes a cover insulating film (72UB) in contact with the second insulating film (72Q) of the specific insulator (72UA) so as to cover the inner coil (110) and the outer coil (100); a portion of the first insulating film (72P) of the specific insulator (72UA) between the inner coil (110) and the outer coil (100) includes a plurality of recesses (72PC) ​​spaced apart in a direction perpendicular to a thickness direction (Z direction) of the third element insulating layer (72) and opening toward the cover insulating film (72UB); A portion of the cover insulating film (72UB) between the inner coil (110) and the outer coil (100) includes a plurality of cover side recesses (72PD) that are spaced apart in a direction perpendicular to the thickness direction (Z direction) and open toward the first insulating film (72P) of the specific insulator (72UA), The second insulating film (72Q) is embedded in each of the plurality of recesses (72PC) ​​and the plurality of cover side recesses (72PD). 14. The semiconductor device according to claim 1, wherein the first and second electrodes are arranged in a first direction.

[0299] [Appendix 19] Each of the plurality of recesses (72PC) ​​and the plurality of cover side recesses (72PD) is formed in an annular shape. 19. The semiconductor device according to claim 18.

[0300] [Appendix 20] a first die pad (81) supporting the first chip (50); a second die pad (91) supporting the second chip (60); Including, The submount chip (120) and the transformer chip (70) are disposed on the first die pad (81) or the second die pad (91) between the first chip (50) and the second chip (60) in the first direction (X direction). 20. The semiconductor device according to any one of claims 1 to 19.

[0301] [Appendix 21] The inner coil (110) and the outer coil (100) are disposed at the same position in the thickness direction (Z direction). 20. The semiconductor device according to any one of claims 14 to 19.

[0302] [Appendix 22] The outer coil (130) includes a first outer coil (131) and a second outer coil (132) having first ends (131A, 132A) and second ends (131B, 132B), respectively; a second end (131B) of the first outer coil (131) and a second end (132B) of the second outer coil (132) are connected to each other, the first outer coil (131) and the second outer coil (132) are configured such that, when a current flows from a first end of one of the first outer coil (131) and the second outer coil (132) to a first end of the other outer coil, magnetic fluxes in opposite directions are generated; The inner coil (140) includes a first inner coil (141) and a second inner coil (142) having first ends (141A, 142A) and second ends (141B, 142B), respectively; When viewed from the thickness direction (Z direction) of the third element insulating layer (72), the first inner coil (141) is disposed inside the first outer coil (131) so as not to overlap with the first outer coil (131), and the second inner coil (142) is disposed inside the second outer coil (132) so as not to overlap with the second outer coil (132). 16. The semiconductor device according to claim 14 or 15.

[0303] [Appendix 23] The first inner coil (141), the second inner coil (142), the first outer coil (131), and the second outer coil (132) are disposed at the same positions as one another in the thickness direction (Z direction). 23. The semiconductor device according to claim 22.

[0304] [Appendix 24] The first inner coil (141) and the second inner coil (142) are connected by a coil connecting wire (WC) provided outside the transformer chip (70). 24. The semiconductor device according to claim 22 or 23.

[0305] [Appendix 25] The first outer coil (131) is electrically connected to the first chip (50) by a first chip connecting wire (WA1) provided outside the transformer chip (70), The second outer coil (132) is electrically connected to the first chip (50) by a second chip connecting wire (WA2) provided outside the transformer chip (70). 25. The semiconductor device according to any one of claims 22 to 24.

[0306] [Appendix 26] The first inner coil (141) is electrically connected to the second chip (60) by a third chip connecting wire (WB1) provided outside the transformer chip (70), The second inner coil (142) is electrically connected to the second chip (60) by a fourth chip connecting wire (WB2) provided outside the transformer chip (70). 26. The semiconductor device according to any one of claims 22 to 25.

[0307] [Appendix 27] The transformer (40) includes an outer coil (130) and an inner coil (140) disposed within the third element insulating layer (72); The outer coil (130) includes a first outer coil (131) and a second outer coil (132) having first ends (131A, 132A) and second ends (131B, 132B), respectively; a second end (131B) of the first outer coil (131) and a second end (132B) of the second outer coil (132) are connected to each other, the first outer coil (131) and the second outer coil (132) are configured such that, when a current flows from a first end of one of the first outer coil (131) and the second outer coil (132) to a first end of the other outer coil, magnetic fluxes in opposite directions are generated; The inner coil (140) includes a first inner coil (141) and a second inner coil (142) having first ends (141A, 142A) and second ends (141B, 142B), respectively; When viewed from the thickness direction (Z direction) of the third element insulating layer (72), the first inner coil (141) is arranged inside the first outer coil (131) so as not to overlap with the first outer coil (131), and the second inner coil (142) is arranged inside the second outer coil (132) so as not to overlap with the second outer coil (132), The third element insulating layer (72) has a structure in which a plurality of insulators (72U) are stacked, the insulators including a first insulating film (72P) containing silicon nitride and a second insulating film (72Q) containing silicon oxide stacked on the first insulating film (72P), the first inner coil (141), the second inner coil (142), the first outer coil (131), and the second outer coil (132) are arranged to penetrate a specific insulator (72UA), which is one specific insulator; the third element insulating layer (72) is composed of the first insulating film (72P), and includes a cover insulating film (72UB) in contact with the second insulating film (72Q) of the specific insulator (72UA) so as to cover the first inner coil (141), the second inner coil (142), the first outer coil (131), and the second outer coil (132); a portion of the first insulating film (72P) of the specific insulator (72UA) between the first inner coil (141) and the first outer coil (131) includes a plurality of first isolation insulating films (78A1) spaced apart in a direction perpendicular to the thickness direction (Z direction); a portion of the first insulating film (72P) of the specific insulator (72UA) between the second inner coil (142) and the second outer coil (132) includes a plurality of second isolation insulating films (78A2) spaced apart in a direction perpendicular to the thickness direction (Z direction); a portion of the cover insulating film (72UB) between the first inner coil (141) and the first outer coil (131) includes a plurality of first cover side isolation insulating films (78B1) spaced apart in a direction perpendicular to the thickness direction (Z direction), a portion of the cover insulating film (72UB) between the second inner coil (142) and the second outer coil (132) includes a plurality of second cover side isolation insulating films (78B2) spaced apart in a direction perpendicular to the thickness direction (Z direction), Each of the plurality of first isolation insulating films (78A1), the plurality of second isolation insulating films (78A2), the plurality of first cover side isolation insulating films (78B1), and the plurality of second cover side isolation insulating films (78B2) is composed of the second insulating film (72Q). 14. The semiconductor device according to claim 1, wherein the first and second electrodes are arranged in a first direction.

[0308] [Appendix 28] Each of the plurality of first isolation insulating films (78A1), the plurality of second isolation insulating films (78A2), the plurality of first cover side isolation insulating films (78B1), and the plurality of second cover side isolation insulating films (78B2) is formed in a ring shape. 28. The semiconductor device according to claim 27.

[0309] [Appendix 29] The transformer (40) includes an outer coil (130) and an inner coil (140) disposed within the third element insulating layer (72); The outer coil (130) includes a first outer coil (131) and a second outer coil (132) having first ends (131A, 132A) and second ends (131B, 132B), respectively; a second end (131B) of the first outer coil (131) and a second end (132B) of the second outer coil (132) are connected to each other, the first outer coil (131) and the second outer coil (132) are configured such that, when a current flows from a first end of one of the first outer coil (131) and the second outer coil (132) to a first end of the other outer coil, magnetic fluxes in opposite directions are generated; The inner coil (140) includes a first inner coil (141) and a second inner coil (142) having first ends (141A, 142A) and second ends (141B, 142B), respectively; When viewed from the thickness direction (Z direction) of the third element insulating layer (72), the first inner coil (141) is arranged inside the first outer coil (131) so as not to overlap with the first outer coil (131), and the second inner coil (142) is arranged inside the second outer coil (132) so as not to overlap with the second outer coil (132), The third element insulating layer (72) has a structure in which a plurality of insulators (72U) are stacked, the insulators including a first insulating film (72P) containing silicon nitride and a second insulating film (72Q) containing silicon oxide stacked on the first insulating film (72P), the first inner coil (141), the second inner coil (142), the first outer coil (131), and the second outer coil (132) are arranged to penetrate a specific insulator (72UA), which is one specific insulator; the third element insulating layer (72) is composed of the first insulating film (72P), and includes a cover insulating film (72UB) in contact with the second insulating film (72Q) of the specific insulator (72UA) so as to cover the first inner coil (141), the second inner coil (142), the first outer coil (131), and the second outer coil (132); a portion of the first insulating film (72P) of the specific insulator (72UA) between the first inner coil (141) and the first outer coil (131) includes a plurality of first recesses (79A) that are spaced apart in a direction perpendicular to the thickness direction (Z direction) and open toward the cover insulating film (72UB); a portion of the first insulating film (72P) of the specific insulator (72UA) between the second inner coil (142) and the second outer coil (132) includes a plurality of second recesses (79B) that are spaced apart in a direction perpendicular to the thickness direction (Z direction) and open toward the cover insulating film (72UB); a portion of the cover insulating film (72UB) between the first inner coil (141) and the first outer coil (131) includes a plurality of first cover side recesses (79C) that are spaced apart in a direction perpendicular to the thickness direction (Z direction) and open toward the first insulating film (72P) of the specific insulator (72UA); a portion of the cover insulating film (72UB) between the second inner coil (142) and the second outer coil (132) includes a plurality of second cover side recesses (79D) spaced apart in a direction perpendicular to the thickness direction (Z direction) and opening toward the first insulating film (72P) of the specific insulator (72UA); The second insulating film (72Q) is embedded in each of the plurality of first recesses (79A), the plurality of second recesses (79B), the plurality of first cover side recesses (79C), and the plurality of second cover side recesses (79D). 14. The semiconductor device according to claim 1, wherein the first and second electrodes are arranged in a first direction.

[0310] [Appendix 30] Each of the first recesses (79A), the second recesses (79B), the first cover side recesses (79C), and the second cover side recesses (79D) is formed in an annular shape. 30. The semiconductor device according to claim 29.

[0311] [Appendix 31] The transformer (40) includes a first coil (41) and a second coil (42) disposed in the third element insulating layer (72), The first coil (41) and the second coil (42) are disposed opposite each other in the thickness direction (Z direction) of the third element insulating layer (72). 14. The semiconductor device according to claim 1, wherein the first and second electrodes are arranged in a first direction.

[0312] [Appendix 32] An insulating adhesive (SDA) is interposed between the transformer chip (70) and the submount chip (120). 32. The semiconductor device according to any one of claims 1 to 31.

[0313] [Appendix 33] A first chip (50) including a first semiconductor substrate (51), a first circuit (20) formed on the first semiconductor substrate (51), and a first element insulating layer (52) formed on the first semiconductor substrate (51); a second chip (60) including a second semiconductor substrate (61), a second circuit (30) formed on the second semiconductor substrate (61), and a second element insulating layer (62) formed on the second semiconductor substrate (61), the second chip (60) being disposed apart from the first chip (50) in a first direction (X direction); a first sub-mount chip (120P) and a second sub-mount chip (120Q) provided separately from the first chip (50) and the second chip (60); a first transformer chip (70P) disposed on the first submount chip (120P) and including a first transformer (40P); a second transformer chip (70Q) disposed on the second submount chip (120Q) and including a second transformer (40Q); the first circuit (20) and the second circuit (30) are configured to transmit a signal or power via the first transformer (40P) and the second transformer (40Q); Both the first transformer chip (40P) and the second transformer chip (40Q) A third semiconductor substrate (71); a third element insulating layer (72) formed on the third semiconductor substrate (71); Including, the first transformer (40P) is embedded in the third element insulating layer (72) of the first transformer chip (70P), the second transformer (40Q) is embedded in the third element insulating layer (72) of the second transformer chip (70Q), Both the first submount chip (120P) and the second submount chip (120Q) A fourth semiconductor substrate (121); an insulating layer (122) formed on the fourth semiconductor substrate (121); Includes A semiconductor device (10).

[0314] [Appendix 34] a first die pad (81) supporting the first chip (50); a second die pad (91) supporting the second chip (60); Including, the first sub-mount chip (120P) is disposed on the first die pad (81) between the first chip (50) and the second chip (60) in the first direction (X direction); the first transformer chip (70P) is disposed on the first submount chip (120P); the second sub-mount chip (120Q) is disposed on the second die pad (91) between the first chip (50) and the second chip (60) in the first direction (X direction); The second transformer chip (70Q) is disposed on the second submount chip (120Q). 34. The semiconductor device of claim 33.

[0315] [Appendix 35] A first chip (50) including a first semiconductor substrate (51), a first circuit (20) formed on the first semiconductor substrate (51), and a first element insulating layer (52) formed on the first semiconductor substrate (51); a second chip (60) including a second semiconductor substrate (61), a second circuit (30) formed on the second semiconductor substrate (61), and a second element insulating layer (62) formed on the second semiconductor substrate (61), the second chip (60) being disposed apart from the first chip (50) in a first direction (X direction); a sub-mount chip (120) provided separately from the first chip (50) and the second chip (60); a capacitor chip (220) disposed on the submount chip (120) and including a capacitor (210); wherein the first circuit (20) and the second circuit (30) are configured to transmit a signal or power through the capacitor (210); The capacitor chip (220) A fifth semiconductor substrate (221); a fifth element insulating layer (222) formed on the fifth semiconductor substrate (221); Including, The capacitor (210) is embedded in the fifth element insulating layer (222); The submount chip (120) is A fourth semiconductor substrate (121); an insulating layer (122) formed on the fourth semiconductor substrate (121); Includes A semiconductor device (10).

[0316] [Appendix 36] a first chip (50) including a first circuit (20); a second chip (60) including a second circuit (30) and arranged apart from the first chip (50) in a first direction (X direction); a sub-mount chip (120) provided separately from the first chip (50) and the second chip (60); an insulating chip (70 / 220) disposed on the submount chip (120) and including an insulating element (40 / 210); wherein the first circuit (20) and the second circuit (30) are configured to transmit a signal or power through the insulating element (40 / 210); The insulating tip (70 / 220) is A semiconductor substrate (71 / 221); an element insulating layer (72 / 222) formed on the semiconductor substrate (71 / 221); Including, The insulating element (40 / 210) is embedded in the element insulating layer (72 / 222); The submount chip (120) is A submount semiconductor substrate (121); an insulating layer (122) formed on the submount semiconductor substrate (121); Includes A semiconductor device (10).

[0317] The above description is merely illustrative. Those skilled in the art may recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of describing the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and alterations that fall within the scope of the present disclosure, including the scope of the claims. [Explanation of symbols]

[0318] 10...Semiconductor device 20...1st circuit 21...Transmitting circuit 30…Second circuit 31...Receiver circuit 40...Trans 40P…First transformer 40Q…Second transformer 41…First coil 42…Second coil 43…Third coil 50…First tip 50S…Chip surface 50R…Chip back 51...first semiconductor substrate 52...first element insulating layer 53…First connection wire 54…Second connection wire 55…First pad 56…First intermediate pad 60…Second chip 60S…Chip surface 60R…Chip backside 61...second semiconductor substrate 62...Second element insulating layer 63…Third connection wire 64…4th connection wire 65…Second pad 66…Second intermediate pad 70...Trans chip 70S…Chip surface 70R…Chip backside 70A~70D: Chip side 70P…First transformer chip 70Q…Second transformer chip 71...Third semiconductor substrate 72...Third element insulating layer 72S…Third element surface 72R…3rd element back side 72P…First insulating film 72PC…Concave 72PD…Cover side recess 72Q, 72QA, 72QB...Second insulating film 72T…Insulating layer laminated structure 72U…Insulator 72UA…Specific insulator 72UB…Cover insulating film 72V,72W…Groove 72V1…1st groove 72V2…2nd groove 72W1…1st groove 72W2…Second groove 73...Protective film 74...Passivation film 75A, 75B…Pads for the first transformer 76A, 76B: Pads for the second transformer 77…Wiring section 77A…Connection wiring 77AA…1st end 77AB…2nd end 77B, 77C...Via 78A…Isolation insulating film 78A1...First isolation insulating film 78A2...Second isolation insulating film 78B…Cover side isolation insulating film 78B1...First cover side isolation insulating film 78B2...Second cover side isolation insulating film 79A…First recess 79B…Second recess 79C…First cover side recess 79D…Second cover side recess 80…First lead frame 81…First die pad 82…1st lead 90…2nd lead frame 91…Second die pad 92…2nd lead 100…Outer coil 100A…Outlet wire 101...1st end 102…Second end 103…Outer coil 103A, 103B... Coil section 104…Beer 110…Inner coil 111...1st end 112…Second end 120...Submount chip 120S…Chip surface 120R…Chip backside 120A~120D…Chip side 120P…First submount chip 120Q…Second submount chip 121...fourth semiconductor substrate 122...insulating layer 122S: Element surface 122R…Back side of element 122P…First insulating film 122Q…Second insulating film 122T…Insulating layer laminated structure 122U…Insulator 123...Protective film 124...Passivation film 130…Outer coil 131…First outer coil 131A…1st end 131B…Second end 132…Second outer coil 132A…1st end 132B…Second end 133…Third outer coil 133A, 133B... Coil section 134…4th outer coil 134A, 134B... Coil section 140…Inner coil 141…First inner coil 141A…1st end 141B…Second end 142…Second inner coil 142A…1st end 142B…Second end 151~156...Pads for transformers 1~6 160...1st wiring section 161…Connection wiring 161A…1st end 161B…Second end 162,163…Beer 170…Second wiring section 171…Connection wiring 171A…1st end 171B…Second terminal 172,173…Beer 181,182…Beer 191~194...Beer 200…Sealing resin 201~204…Sealing side 210…Capacitor 211...First electrode plate 212…Second electrode plate 220...Capacitor chip 221...fifth semiconductor substrate 222...fifth element insulating layer 300...Power transmission device 301...Control circuit 302…Oscillator 303~306...Diodes 307...Smoothing capacitor 311…DC power supply 312…Load SD: Conductive adhesive SDA: Insulating adhesive W1…First wire W2…Second wire WA, WA1, WA2...First intermediate wire WB, WB1, WB2: Second intermediate wire WC…Wire WD…Wire DZ1: Distance between the inner coil and the conductive bonding material DZ2: Distance between the inner coil and the first die pad

Claims

1. a first chip including a first semiconductor substrate, a first circuit formed on the first semiconductor substrate, and a first element insulating layer formed on the first semiconductor substrate; a second chip including a second semiconductor substrate, a second circuit formed on the second semiconductor substrate, and a second element insulating layer formed on the second semiconductor substrate, the second chip being spaced apart from the first chip in a first direction; a submount chip provided separately from the first chip and the second chip; a transformer chip disposed on the submount chip and including a transformer; the first circuit and the second circuit are configured to transmit a signal or power through the transformer; The transformer chip is A third semiconductor substrate; a third element insulating layer formed on the third semiconductor substrate; Including, the transformer is embedded in the third element insulating layer; The submount chip is A fourth semiconductor substrate; an insulating layer formed on the fourth semiconductor substrate; Includes Semiconductor device.

2. The third element insulating layer of the transformer chip includes a structure in which a first insulating film containing silicon nitride and a second insulating film containing silicon oxide are alternately stacked in a plurality of layers. The semiconductor device according to claim 1 .

3. The insulating layer of the submount chip includes a structure in which a first insulating film containing silicon nitride and a second insulating film containing silicon oxide are alternately laminated in a plurality of layers. The semiconductor device according to claim 1 .

4. The insulating layer of the submount chip includes a structure in which a plurality of insulating films containing silicon oxide are stacked. The semiconductor device according to claim 1 .

5. The thickness of the submount chip is smaller than the thickness of the transformer chip. The semiconductor device according to claim 1 .

6. The thickness of the submount chip is equal to or greater than the thickness of the transformer chip. The semiconductor device according to claim 1 .

7. A dimension of the submount chip in the first direction is smaller than a dimension of the transformer chip in the first direction. The semiconductor device according to claim 1 .

8. A dimension of the submount chip in the first direction is equal to a dimension of the transformer chip in the first direction. The semiconductor device according to claim 1 .

9. A dimension of the submount chip in the first direction is greater than a dimension of the transformer chip in the first direction. The semiconductor device according to claim 1 .

10. The thickness of the submount chip is equal to or greater than the thickness of the first chip or the thickness of the second chip. The semiconductor device according to claim 1 .

11. The thickness of the submount chip is smaller than the thickness of the first chip or the thickness of the second chip. The semiconductor device according to claim 1 .

12. In a chip arrangement state in which the transformer chip is arranged on the submount chip, the third semiconductor substrate is interposed between the insulating layer of the submount chip and the third element insulating layer of the transformer chip. The semiconductor device according to claim 1 .

13. the insulating layer of the submount chip includes a protective layer formed on a surface side of the insulating layer, In the chip arrangement state, the third semiconductor substrate is in contact with the protective layer. The semiconductor device according to claim 12.

14. the transformer includes an outer coil and an inner coil embedded in the third element insulation layer; When viewed from a thickness direction of the third element insulating layer, the inner coil is disposed inside the outer coil so as not to overlap with the outer coil. The semiconductor device according to claim 1 .

15. Both the outer coil and the inner coil are disposed on a side farther away from the third semiconductor substrate than the center in the thickness direction of the third element insulating layer. The semiconductor device according to claim 14.

16. the transformer includes an outer coil and an inner coil embedded in the third element insulation layer; When viewed from a thickness direction of the third element insulating layer, the inner coil is disposed inside the outer coil so as not to overlap with the outer coil, the third element insulating layer has a structure in which a plurality of insulators are stacked, the plurality of insulators including a first insulating film containing silicon nitride and a second insulating film containing silicon oxide stacked on the first insulating film; the inner coil and the outer coil are provided to penetrate a specific insulator, the third element insulating layer is made of the first insulating film and includes a cover insulating film in contact with the second insulating film of the specific insulator so as to cover the inner coil and the outer coil, a portion of the first insulating film of the specific insulator between the inner coil and the outer coil includes a plurality of isolation insulating films spaced apart in a direction perpendicular to a thickness direction of the third element insulating layer, a portion of the cover insulating film between the inner coil and the outer coil includes a plurality of cover-side isolation insulating films spaced apart in a direction perpendicular to the thickness direction, Each of the plurality of isolation insulating films and the plurality of cover-side isolation insulating films is made of the second insulating film. The semiconductor device according to claim 1 .

17. Each of the plurality of isolation insulating films and the plurality of cover-side isolation insulating films is formed in an annular shape. The semiconductor device according to claim 16.

18. the transformer includes an outer coil and an inner coil embedded in the third element insulation layer; When viewed from a thickness direction of the third element insulating layer, the inner coil is disposed inside the outer coil so as not to overlap with the outer coil, the third element insulating layer has a structure in which a plurality of insulators are stacked, the plurality of insulators including a first insulating film containing silicon nitride and a second insulating film containing silicon oxide stacked on the first insulating film; the inner coil and the outer coil are provided to penetrate a specific insulator, the third element insulating layer is made of the first insulating film and includes a cover insulating film in contact with the second insulating film of the specific insulator so as to cover the inner coil and the outer coil, a portion of the first insulating film of the specific insulator between the inner coil and the outer coil includes a plurality of recesses that are spaced apart in a direction perpendicular to a thickness direction of the third element insulating layer and open toward the cover insulating film, a portion of the cover insulating film between the inner coil and the outer coil includes a plurality of cover side recesses spaced apart in a direction perpendicular to the thickness direction and opening toward the first insulating film of the specific insulator, The second insulating film is embedded in each of the plurality of recesses and the plurality of cover-side recesses. The semiconductor device according to claim 1 .

19. Each of the plurality of recesses and the plurality of cover-side recesses is formed in an annular shape. The semiconductor device according to claim 18.

20. a first die pad supporting the first chip; a second die pad supporting the second chip; Including, The submount chip and the transformer chip are disposed on the first die pad or the second die pad between the first chip and the second chip in the first direction. The semiconductor device according to any one of claims 1 to 19.

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