Semiconductor device

Abstract

To provide a semiconductor device capable of restraining concentration of an electric field on an FP electrode.SOLUTION: A semiconductor device includes first to fourth electrodes, first to third semiconductor regions, and first and second insulating portions. The first semiconductor region is provided on the first electrode. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is selectively provided on the second semiconductor region. The second electrode is provided on the third semiconductor region. The third electrode is aligned with the second semiconductor region. The first insulating portion is provided between the second semiconductor region and the third electrode. The fourth electrode is aligned with the first and second semiconductor regions. The second insulating portion is provided between the first and second semiconductor regions and the fourth electrode. The second insulating portion has first and second insulating regions. The first insulating region surrounds the fourth electrode, and is in contact with the fourth electrode. The second insulating region surrounds the first insulating region, and is in contact with the first insulating region. The dielectric constant of the second insulating region is lower than the dielectric constant of the first insulating region.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] A semiconductor device equipped with dot-shaped field plate electrodes (hereinafter, referred to as "FP electrodes") is known to improve breakdown voltage or reduce on-resistance. For this semiconductor device, it is required to suppress the concentration of the electric field in the FP electrodes. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 9,722,036 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a semiconductor device capable of suppressing electric field concentration in an FP electrode. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a second electrode, a third electrode, a first insulating portion, a fourth electrode, and a second insulating portion. The first semiconductor region is provided on the first electrode. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is selectively provided on the second semiconductor region. The second electrode is provided on the third semiconductor region. The second electrode is electrically connected to the third semiconductor region. The third electrode is aligned with the second semiconductor region in a second direction and a third direction. The second direction is perpendicular to a first direction from the first semiconductor region to the second semiconductor region. The third direction is perpendicular to the first direction and intersects with the second direction. The first insulating portion is provided between the second semiconductor region and the third electrode in the second direction and the third direction. The fourth electrode is aligned with the first semiconductor region and the second semiconductor region in the second direction and the third direction. The second insulating portion is provided between the first semiconductor region and the fourth electrode and between the second semiconductor region and the fourth electrode in the second direction and the third direction. The second insulating portion has a first insulating region and a second insulating region. The first insulating region surrounds the fourth electrode and is in contact with the fourth electrode. The second insulating region surrounds the first insulating region and is in contact with the first insulating region. The dielectric constant of the first insulating region is lower than the dielectric constant of the second insulating region. [Brief description of the drawings]

[0006] [Figure 1] 1 is a plan view illustrating a semiconductor device according to an embodiment. [Diagram 2] 1 is a cross-sectional view illustrating a semiconductor device according to an embodiment. [Diagram 3] 11 is a graph illustrating characteristics of a semiconductor device of a reference example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Each embodiment will be described below with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as the actual ones. Even when the same part is shown, the dimensions and ratios of each part may be different depending on the drawing. Furthermore, in this specification and each drawing, elements similar to those explained with reference to the previous drawings are given the same reference numerals, and detailed explanations are omitted as appropriate.

[0008] For ease of understanding, the following description will use an XYZ Cartesian coordinate system to explain the arrangement and configuration of each part. The X-axis, Y-axis, and Z-axis are mutually perpendicular. The direction in which the X-axis extends is called the "X-direction," the direction in which the Y-axis extends is called the "Y-direction," and the direction in which the Z-axis extends is called the "Z-direction." For ease of understanding, the direction of the arrow in the Z-direction is called the upward direction, and the opposite direction is called the downward direction, but these directions are unrelated to the direction of gravity. Viewing from above is called "planar view."

[0009] In the following, the notations + and - indicate the relative level of the impurity concentration in each conductivity type. Specifically, a notation with "+" indicates a higher impurity concentration than a notation with neither "+" nor "-". A notation with "-" indicates a lower impurity concentration than a notation with neither "+" nor "-". Here, "impurity concentration" refers to the net impurity concentration after both donor and acceptor impurities are offset in the case where each region contains both donor and acceptor impurities.

[0010] FIG. 1 is a plan view illustrating a semiconductor device according to an embodiment. FIG. 2 is a cross-sectional view illustrating the semiconductor device according to the embodiment. FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. 1 and 2, the semiconductor device 100 according to the embodiment is, for example, a vertical MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The semiconductor device 100 is a MOSFET in which dot-shaped FP electrodes are provided and a trench-shaped gate electrode is provided between the FP electrodes.

[0011] The semiconductor device 100 includes a drain electrode 11 (first electrode), a source electrode 12 (second electrode), a gate electrode 13 (third electrode), an FP electrode 14 (fourth electrode), a gate pad 15, and a n - A p-type drift region 21 (first semiconductor region), a p-type base region 22 (second semiconductor region), + A source region 23 (third semiconductor region), n + The FP insulating portion 32 includes a drain region 24, a gate insulating portion 31 (first insulating portion), and an FP insulating portion 32 (second insulating portion). In this example, the first conductivity type is n-type, and the second conductivity type is p-type.

[0012] In the following, the direction from the first electrode 11 to the second electrode 12 is referred to as the first direction. The direction perpendicular to the first direction is referred to as the second direction. The direction perpendicular to the first direction and intersecting the second direction is referred to as the third direction. The first direction is, for example, the Z direction. The second direction is, for example, the X direction. The third direction is, for example, the Y direction.

[0013] A drain electrode 11 is provided on the bottom of the semiconductor device 100. On the drain electrode 11, + Through the drain region 24, - A drift region 21 is provided. - The drift region 21 is + The n-type drain region 24 is electrically connected to the drain electrode 11. - A p-type base region 22 is provided on the p-type drift region 21. An n-type + In this example, an n-type source region 23 is selectively provided on a portion of the p-type base region 22. +A p-type source region 23 is provided on another part of the p-type base region 22. + The source region 23 is not provided. + The p-type source region 23 is aligned with the p-type base region 22 in the X and Y directions. + A source electrode 12 is provided on the p-type source region 23. The source electrode 12 is connected to the p-type base region 22 and the n-type + The source electrode 12 is electrically connected to the source region 23. In FIG.

[0014] The gate electrode 13 is aligned with the p-type base region 22 in the X and Y directions. In this example, a part of the gate electrode 13 is aligned with the p-type base region 22 in the X and Y directions. - In this example, a portion of the gate electrode 13 is aligned with a portion of the n-type drift region 21 in the X direction and the Y direction. + It is aligned with a portion of the source region 23 .

[0015] The gate insulating portion 31 is provided between the gate electrode 13 and the p-type base region 22 in the X and Y directions. In this example, a part of the gate insulating portion 31 is disposed between the gate electrode 13 and the n-type base region 22 in the X and Y directions. - In this example, a part of the gate insulating portion 31 is disposed between the gate electrode 13 and the n-type drift region 21 in the X direction and the Y direction. + In this example, a part of the gate insulating portion 31 is disposed between the gate electrode 13 and the n-type source region 23 in the Z direction. - The gate electrode 13 is provided between the gate insulating portion 31 and the source electrode 12 in the Z direction. In this example, a part of the gate insulating portion 31 is provided between the gate electrode 13 and the source electrode 12 in the Z direction. In this manner, the gate electrode 13 is surrounded by the gate insulating portion 31. The gate electrode 13 is provided inside the gate insulating portion 31.

[0016] The gate electrode 13 is electrically connected to the gate pad 15. The gate pad 15 is electrically isolated from the source electrode 12. The gate electrode 13 may be electrically connected to the gate pad 15 via a gate wiring layer (not shown).

[0017] The FP electrode 14 has n - In this example, a portion of the FP electrode 14 is aligned with the n-type drift region 21 and the p-type base region 22 in the X and Y directions. + It is aligned with a portion of the source region 23 .

[0018] The FP insulating portion 32 is separated from the FP electrode 14 in the X direction and the Y direction by n - The FP insulating portion 32 is provided between the FP electrode 14 and the p-type drift region 21 and between the FP electrode 14 and the p-type base region 22 in the Z direction. - The FP electrode 14 is provided between the source electrode 12 and the FP drift region 21. In this manner, the FP electrode 14 is surrounded by the FP insulating portion 32. The FP electrode 14 is provided inside the FP insulating portion 32. The FP electrode 14 is electrically connected to the source electrode 12.

[0019] The FP insulating section 32 has a first insulating region 32a and a second insulating region 32b. The first insulating region 32a surrounds the FP electrode 14 in the XY plane. The first insulating region 32a contacts the FP electrode 14. The second insulating region 32b surrounds the first insulating region 32a in the XY plane. The second insulating region 32b contacts the first insulating region 32a. The first insulating region 32a is provided between the FP electrode 14 and the second insulating region 32b. The first insulating region 32a is provided inside the second insulating region 32b, and the FP electrode 14 is provided inside the first insulating region 32a.

[0020] The dielectric constant of the second insulating region 32b is lower than that of the first insulating region 32a. The ratio of the dielectric constant of the second insulating region 32b to that of the first insulating region 32a is, for example, 1 / 2 or more and 4 / 5 or less. The dielectric constant of the first insulating region 32a is, for example, constant within the first insulating region 32a. The dielectric constant of the second insulating region 32b is, for example, constant within the second insulating region 32b. In other words, the dielectric constant of the FP insulating portion 32 is, for example, a ratio of the dielectric constant of the first insulating region 32b to the dielectric constant of the first insulating region 32a. - The potential gradually decreases toward the p-type drift region 21 or the p-type base region 22.

[0021] The thickness of the first insulating region 32a and the thickness of the second insulating region 32b are, for example, greater than the thickness of a natural oxide film (for example, about 1 nm). The thickness of the second insulating region 32b is, for example, 0.1 to 10 times the thickness of the first insulating region 32a.

[0022] The thickness of the first insulating region 32a is expressed, for example, by the average value of the length of the first insulating region 32a in the X direction, the length of the first insulating region 32a in the Y direction, and the length of the first insulating region 32a in the Z direction. The length of the first insulating region 32a in the X direction, the length of the first insulating region 32a in the Y direction, and the length of the first insulating region 32a in the Z direction are, for example, the same. That is, the thickness of the first insulating region 32a is, for example, uniform.

[0023] The thickness of the second insulating region 32b is expressed, for example, as the average value of the length of the second insulating region 32b in the X direction, the length of the second insulating region 32b in the Y direction, and the length of the second insulating region 32b in the Z direction. The length of the second insulating region 32b in the X direction, the length of the second insulating region 32b in the Y direction, and the length of the second insulating region 32b in the Z direction are, for example, the same. That is, the thickness of the second insulating region 32b is, for example, uniform.

[0024] The FP insulating section 32 may further include another insulating region that surrounds the second insulating region 32b and is in contact with the second insulating region 32b. In this case, the dielectric constant of the other insulating region is preferably lower than that of the second insulating region 32b. The other insulating region may include multiple layers having different dielectric constants. In this case, the dielectric constant of the multiple layers may be different from that of the second insulating region 32b to n. - It is preferable that the concentration of the n-type ions decreases toward the p-type drift region 21 or the p-type base region 22.

[0025] The dielectric constant of the FP insulating portion 32 is n - The dielectric constant may be continuously decreased toward the p-type drift region 21 or the p-type base region 22. When the dielectric constant is continuously decreased, the inner region of the FP insulating portion 32 that contacts the FP electrode 14 is called the first insulating region 32a, - The outer region in contact with the p-type drift region 21 or the p-type base region 22 can be regarded as the second insulating region 32b. The thickness of the first insulating region 32ab is the same as the thickness of the second insulating region 32b. The dielectric constant at the center position in the thickness direction of the first insulating region 32a can be regarded as the dielectric constant of the first insulating region 32a. The dielectric constant at the center position in the thickness direction of the second insulating region 32b can be regarded as the dielectric constant of the second insulating region 32b. The dielectric constant of the FP insulating unit 32 is preferably set to be low so as to be inversely proportional to the distance from the FP electrode 14, for example. In addition, the rate of change of the dielectric constant in the FP insulating unit 32 is preferably set so that the strength of the electric field in the FP insulating unit 32 is constant, for example.

[0026] For example, the FP insulating portion 32 includes a first material and a second material having a lower dielectric constant than the first material, and the FP electrode 14 is - The ratio of the second material to the first material is increased toward the p-type drift region 21 or the p-type base region 22, so that the dielectric constant of the FP insulating portion 32 is increased from the FP electrode 14 to the n-type drift region 21 or the p-type base region 22. - The first material may be, for example, the same as the material of the first insulating region 32a described below, and the second material may be, for example, the same as the material of the second insulating region 32b described below.

[0027] The FP electrode 14 is surrounded by a first insulating region 32a in a plan view. The first insulating region 32a is surrounded by a second insulating region 32b in a plan view. The second insulating region 32b is surrounded by a p-type base region 22 in a plan view. The p-type base region 22 is surrounded by an n-type insulating region 32b in a plan view. + The source region 23 is surrounded by a + The source region 23 is surrounded by the gate insulating portion 31 in a plan view. The gate electrode 13 is provided along the gap between the gate insulating portions 31 in a plan view.

[0028] A plurality of FP electrodes 14 are provided in a plan view. In this example, the FP electrodes 14 are arranged in an equilateral triangular shape in a plan view. The FP electrodes 14 may be arranged in a quadrangular shape in a plan view, for example.

[0029] In this example, the shape of the FP electrode 14 and the FP insulating portion 32 in a plan view is circular. The shape of the FP electrode 14 and the FP insulating portion 32 in a plan view is not limited to this, and may be, for example, a polygon such as a triangle, a rectangle, or a hexagon. In this example, the shape of the gate insulating portion 31 and the n + The shape of the source region 23 is a hexagon. + The shape of the source region 23 is not limited to this, and may be, for example, a polygon such as a triangle or a rectangle, or may be a circle.

[0030] An example of the material of each component of the semiconductor device 100 will be described.

[0031] The drain electrode 11, the source electrode 12, and the gate pad 15 include a metal such as aluminum or copper. The gate electrode 13 and the FP electrode 14 include a conductive material such as polysilicon. Impurities may be added to the conductive material.

[0032] n - p-type drift region 21, p-type base region 22, n + shaped source region 23, and+ The semiconductor material of the drain region 24 includes silicon, silicon carbide, gallium nitride, or gallium arsenide. When silicon is used as the semiconductor material, the donor impurity may be arsenic, phosphorus, or antimony. The acceptor impurity may be boron.

[0033] The gate insulating section 31 and the FP insulating section 32 include insulating materials. The gate insulating section 31 includes, for example, silicon oxide (SiO). The first insulating region 32a of the FP insulating section 32 includes, for example, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and at least one of hafnium oxide (HfO), aluminum oxide (AlO), zirconium oxide (ZrO), and lanthanum oxide (LaO). The second insulating region 32b of the FP insulating section 32 includes, for example, at least one of carbon-containing silicon oxide (SiOC) and silicon oxide (SiO). The silicon oxide (SiO) included in the second insulating region 32b is preferably porous. The term "porous" here refers to a state in which the material has a structure with many fine pores, thereby reducing the inherent density and dielectric constant. When the first insulating region 32a includes silicon nitride (SiN) or silicon oxynitride (SiON), the second insulating region 32b preferably includes, for example, silicon oxide (SiO). When the first insulating region 32a includes silicon oxide (SiO), the second insulating region 32b preferably includes, for example, carbon-containing silicon oxide (SiOC).

[0034] The operation of the semiconductor device 100 will now be described. With a positive voltage applied to the drain electrode 11 relative to the source electrode 12, a voltage equal to or greater than the threshold is applied to the gate electrode 13. This forms a channel (inversion layer) in the p-type base region 22, turning the semiconductor device 100 on. Electrons flow from the source electrode 12 to the drain electrode 11 through the channel. When the voltage applied to the gate electrode 13 then becomes lower than the threshold, the channel in the p-type base region 22 disappears, turning the semiconductor device 100 off.

[0035] When the semiconductor device 100 is switched to the off state, the positive voltage applied to the drain electrode 11 with respect to the source electrode 12 increases. - The potential difference between the n-type drift region 21 and the FP electrode 14 increases. - From the interface with the drift region 21, - The depletion layer spreads toward the n-type drift region 21. This spread of the depletion layer can increase the breakdown voltage of the semiconductor device 100. Alternatively, the breakdown voltage of the semiconductor device 100 can be increased while maintaining the breakdown voltage of the n-type drift region 21. - By increasing the concentration of impurities that act as donors in the drift region 21, the on-resistance of the semiconductor device 100 can be reduced.

[0036] When the FP electrode 14 is provided, an electric field is concentrated at the FP electrode 14, which may increase the leakage current, and this may also reduce the reliability of the FP insulating section 32.

[0037] In contrast, in the semiconductor device 100 according to the embodiment, the FP insulating section 32 surrounding the FP electrode 14 has a multi-layer structure including a first insulating region 32a and a second insulating region 32b, and the dielectric constant of the second insulating region 32b located on the outside is made lower than the dielectric constant of the first insulating region 32a located on the inside. This reduces the strength of the electric field in the first insulating region 32a, and suppresses the concentration of the electric field in the FP electrode 14. This prevents the leakage current from increasing, and improves the reliability of the FP insulating section 32.

[0038] FIG. 3 is a graph illustrating the characteristics of the semiconductor device of the reference example. The horizontal axis of Fig. 3 represents the position on the XY plane, and the vertical axis of Fig. 3 represents the strength of the electric field. In FIG. 3, the electric field intensity of the semiconductor device of Reference Example 1 is represented by a solid line, the electric field intensity of the semiconductor device of Reference Example 2 is represented by a dashed line, and the electric field intensity of the semiconductor device of Reference Example 3 is represented by a dashed line.

[0039] The semiconductor device of Reference Example 1 has a first insulating region 32a at the position of insulating region A in FIG. 3, and a second insulating region 32b at the position of insulating region B in FIG. 3. The dielectric constant of the second insulating region 32b is lower than that of the first insulating region 32a. The first insulating region 32a of the semiconductor device of Reference Example 1 has a relative dielectric constant of 7.5. This corresponds to the relative dielectric constant when the first insulating region 32a contains silicon nitride (SiN). The second insulating region 32b of the semiconductor device of Reference Example 1 has a relative dielectric constant of 3.9. This corresponds to the relative dielectric constant when the second insulating region 32b contains silicon oxide (SiO).

[0040] The charge density of the semiconductor region is ρ, and the boundary position of the semiconductor region and the insulating region in the polar coordinate system is R. Si , the boundary position between the insulating region and the FP electrode in the polar coordinate system is R ox , the dielectric constant of the insulating region is ε 0x , the dielectric constant of the semiconductor region is ε Si If an arbitrary position in the polar coordinate system is r, the electric field strength E of the insulating region at position r is 0x and the electric field strength E in the semiconductor region Si is expressed by the following formula: The electric field intensity in Reference Example 1 follows this formula.

number

[0041] The semiconductor device of Reference Example 2 has a first insulating region 32a at the position of insulating region A in Fig. 3, and a second insulating region 32b at the position of insulating region B in Fig. 3. The dielectric constants of insulating region A and insulating region B are - The temperature gradient of the ion beam becomes continuously lower as the temperature approaches the drift region 21).

[0042] The semiconductor device of Reference Example 3 has first insulating regions 32a at the positions of insulating regions A and B in FIG. 3. That is, the semiconductor device of Reference Example 3 does not have second insulating regions 32b. The dielectric constant of the FP insulating portion 32 (first insulating region 32a) of the semiconductor device of Reference Example 3 is the same as the dielectric constant of the first insulating region 32a of the semiconductor device of Reference Example 1. The thickness of the FP insulating portion 32 (thickness of the first insulating region 32a) of the semiconductor device of Reference Example 3 is the same as the thickness of the FP insulating portion 32 (the sum of the thickness of the first insulating region 32a and the thickness of the second insulating region 32b) of the semiconductor device of Reference Examples 1 and 2.

[0043] As shown in FIG. 3, in the semiconductor devices of Reference Examples 1 and 2 having the second insulating region 32b, the electric field strength is greater at the position of insulating region B (i.e., the position where the second insulating region 32b is provided) than in the semiconductor device of Reference Example 3 not having the second insulating region 32b, and is smaller at the position of insulating region A (i.e., the position where the first insulating region 32a is provided) and the semiconductor region (n - The electric field intensity in the semiconductor region (n-shaped drift region 21) becomes smaller. This suggests that the concentration of the electric field in the FP electrode 14 can be suppressed by providing the second insulating region 32b. Furthermore, in the semiconductor device of Reference Example 2, the change in the electric field intensity in the positions of insulating region A and insulating region B becomes smaller (for example, becomes constant) compared to the semiconductor device of Reference Example 1. This suggests that the dielectric constant of the second insulating portion 32 can be reduced by changing the dielectric constant from the FP electrode 14 to the semiconductor region (n - It is suggested that the concentration of the electric field in the FP electrode 14 can be further suppressed by continuously lowering the temperature toward the axial drift region 21).

[0044] The thickness of the first insulating region 32a is d1, the thickness of the second insulating region 32b is d2, and the thickness of the semiconductor region (n - The thickness of the drift region 21) is d3, the relative dielectric constant of the first insulating region 32a is ε1, the relative dielectric constant of the second insulating region 32b is ε2, and the semiconductor region (n - When the relative dielectric constant of the semiconductor region (n) is ε3, the electric field strength E1 in the first insulating region 32a, the electric field strength E2 in the second insulating region 32b, and the -The electric field strength E3 in the drift region 21) is expressed by the following equation:

number

[0045] In this way, the FP insulating portion 32 surrounding the FP electrode 14 is made into a multi-layer structure including the first insulating region 32a and the second insulating region 32b, and the dielectric constant of the second insulating region 32b located on the outside is made lower than the dielectric constant of the first insulating region 32a located on the inside, thereby increasing the strength of the electric field in the second insulating region 32b and increasing the dielectric constant of the first insulating region 32a and the semiconductor region (n - The above equation suggests that the electric field strength in the axial drift region 21) can be reduced.

[0046] The FP insulating portion 32 and the FP electrode 14 of the semiconductor device 100 according to the embodiment can be formed, for example, by the following procedure. - A hole (via) is formed in the p-type drift region 21 and the p-type base region 22. Next, a second insulating region 32b is formed inside the hole by CVD (chemical vapor deposition), coating, ALD (atomic layer deposition), thermal oxidation, or the like. Next, a first insulating region 32a is formed inside the second insulating region 32b by CVD, coating, ALD, thermal oxidation, or the like. Next, an FP electrode 14 is formed inside the first insulating region 32a by CVD, coating, ALD, thermal oxidation, or the like. This allows the FP insulating unit 32 having the first insulating region 32a and the second insulating region 32b to be formed.

[0047] The embodiment may include the following features.

[0048] (Configuration 1) A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a third semiconductor region of the first conductivity type selectively provided on the second semiconductor region; a second electrode provided on the third semiconductor region and electrically connected to the third semiconductor region; a third electrode aligned with the second semiconductor region in a second direction perpendicular to a first direction from the first electrode toward the second electrode and in a third direction perpendicular to the first direction and intersecting the second direction; a first insulating portion provided between the second semiconductor region and the third electrode in the second direction and the third direction; a fourth electrode aligned with the first semiconductor region and the second semiconductor region in the second direction and the third direction; a second insulating portion provided between the first semiconductor region and the fourth electrode and between the second semiconductor region and the fourth electrode in the second direction and the third direction; Equipped with the second insulating portion has a first insulating region surrounding the fourth electrode and in contact with the fourth electrode, and a second insulating region surrounding the first insulating region and in contact with the first insulating region, A semiconductor device, wherein the dielectric constant of the second insulating region is lower than the dielectric constant of the first insulating region.

[0049] (Configuration 2) 2. The semiconductor device of claim 1, wherein the first insulating region includes at least one of silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, zirconium oxide, and lanthanum oxide.

[0050] (Configuration 3) 3. The semiconductor device according to claim 1, wherein the second insulating region includes at least one of carbon-containing silicon oxide and silicon oxide.

[0051] (Configuration 4) 4. The semiconductor device according to any one of configurations 1 to 3, wherein the second insulating region has a thickness that is 0.1 to 10 times the thickness of the first insulating region.

[0052] As described above, according to the embodiment, a semiconductor device capable of suppressing electric field concentration in the FP electrode is provided.

[0053] Although some embodiments of the present invention have been illustrated above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, modifications, etc. can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the scope of the invention and its equivalents described in the claims. In addition, the above-mentioned embodiments can be implemented in combination with each other. [Explanation of symbols]

[0054] 11: Drain electrode (first electrode) 12: Source electrode (second electrode) 13: Gate electrode (third electrode) 14:FP electrode (4th electrode) 15: Gate Pad 21:n - Drift region (first semiconductor region) 22: p-type base region (second semiconductor region) 23:n + Source region (third semiconductor region) 24:n + Drain region (fourth semiconductor region) 31: Gate insulation part (first insulation part) 32: FP insulation part (second insulation part) 32a: First insulating region 32b: Second insulating region 100: Semiconductor device

Claims

1. A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a third semiconductor region of the first conductivity type selectively provided on the second semiconductor region; a second electrode provided on the third semiconductor region and electrically connected to the third semiconductor region; a third electrode aligned with the second semiconductor region in a second direction perpendicular to a first direction from the first electrode toward the second electrode and in a third direction perpendicular to the first direction and intersecting the second direction; a first insulating portion provided between the second semiconductor region and the third electrode in the second direction and the third direction; a fourth electrode aligned with the first semiconductor region and the second semiconductor region in the second direction and the third direction; a second insulating portion provided between the first semiconductor region and the fourth electrode and between the second semiconductor region and the fourth electrode in the second direction and the third direction; Equipped with the second insulating portion has a first insulating region surrounding the fourth electrode and in contact with the fourth electrode, and a second insulating region surrounding the first insulating region and in contact with the first insulating region, A semiconductor device, wherein the dielectric constant of the second insulating region is lower than the dielectric constant of the first insulating region.

2. 2. The semiconductor device according to claim 1, wherein the first insulating region includes at least one of silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, zirconium oxide, and lanthanum oxide.

3. 3. The semiconductor device according to claim 1, wherein the second insulating region includes at least one of carbon-containing silicon oxide and silicon oxide.

4. 3. The semiconductor device according to claim 1, wherein the thickness of said second insulating region is 0.1 to 10 times the thickness of said first insulating region.

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