Insulated chip and signal transmission device

Abstract

To improve a dielectric voltage.SOLUTION: A trans-chip 50 comprises: a first unit 90 including a first element insulating layer 92 formed on a first substrate surface 91A of a first semiconductor substrate 91 and a first coil 21 provided in the first element insulating layer 92; a second element insulating layer 102 formed on a second substrate surface 101A of a second semiconductor substrate 101; a second coil 22 provided in the second element insulating layer 102; and an insulated glass layer 110 interposed between the first unit 90 and the second unit 100. In a unit bonded state in which the first unit 90 and the second unit 100 are bonded together with the insulated glass layer 110, the insulated glass layer 110 bonds both the first element insulating layer 92 and the second element insulating layer 102, and the first coil 21 and the second coil 22 are disposed facing each other.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present disclosure relates to insulating tips and signal transmission devices. [Background technology]

[0002] The transformer chip of Patent Document 1 includes, within an insulating layer laminated structure, an upper coil and a lower coil that are disposed opposite each other in the lamination direction of the insulating layer laminated structure. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2018-78169 A

[0004] [overview] In the above-mentioned transformer chip, there are cases where an improvement in the dielectric strength voltage is required. Note that this is not limited to the transformer chip including the upper coil and the lower coil, but also may be required in the capacitor chip including a capacitor instead of the upper coil and the lower coil.

[0005] An insulating chip according to one embodiment of the present disclosure includes a first unit including a first semiconductor substrate having a first substrate surface and a first substrate back surface opposite to the first substrate surface, a first element insulating layer formed on the first substrate surface and a first insulating element provided in the first element insulating layer, a second semiconductor substrate having a second substrate surface and a second substrate back surface opposite to the second substrate surface, a second element insulating layer formed on the second substrate surface and a second insulating element provided in the second element insulating layer, the second unit being disposed on the first unit, and an insulating glass layer interposed between the first unit and the second unit, wherein in a unit bonding state in which the first unit and the second unit are bonded by the insulating glass layer, the insulating glass layer bonds both the first element insulating layer and the second element insulating layer while being in contact with both the first element insulating layer and the second element insulating layer, and the first insulating element and the second insulating element are disposed opposite to each other. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a circuit diagram showing a schematic circuit configuration of a signal transmission device using an insulating chip according to one embodiment. [Diagram 2] FIG. 2 is a schematic plan view showing the configuration of the signal transmission device of FIG. [Diagram 3] FIG. 3 is a schematic plan view showing a configuration of an insulating chip in the signal transmission device of FIG. [Figure 4] FIG. 4 is a schematic cross-sectional view of the insulating chip taken along line F4-F4 in FIG. [Diagram 5] FIG. 5 is a schematic plan view showing a second unit of the insulating chip of FIG. [Figure 6] FIG. 6 is a schematic plan view showing a first unit of the insulating chip of FIG. [Figure 7] FIG. 7 is a schematic cross-sectional view showing an enlarged portion of the insulating chip in FIG. 4 including a first insulating element and a first pad. [Figure 8]FIG. 8 is a schematic cross-sectional view showing an enlarged portion of the insulating chip in FIG. 4 including the second insulating element and the second pad. [Figure 9] 9A to 9C are schematic cross-sectional views illustrating an exemplary manufacturing process for the insulating chip of FIG. [Figure 10] 10A to 10C are schematic cross-sectional views illustrating an exemplary manufacturing process for the insulating chip of FIG. [Figure 11] FIG. 11 is a schematic cross-sectional view showing an exemplary manufacturing process subsequent to FIG. [Figure 12] FIG. 12 is a schematic perspective view showing an exemplary manufacturing process subsequent to FIG. [Figure 13] FIG. 13 is a schematic plan view showing an exemplary manufacturing process subsequent to FIG. [Figure 14] FIG. 14 is a schematic cross-sectional view showing an exemplary manufacturing process subsequent to FIG. [Figure 15] FIG. 15 is a schematic cross-sectional view showing an exemplary manufacturing process subsequent to FIG. [Figure 16] FIG. 16 is a schematic perspective view showing an exemplary manufacturing process subsequent to FIG. [Figure 17] FIG. 17 is a schematic cross-sectional view showing an exemplary manufacturing step subsequent to FIG. [Figure 18] FIG. 18 is a circuit diagram showing a schematic circuit configuration of a signal transmission device using an insulating chip according to a first modified example. [Figure 19] FIG. 19 is a schematic cross-sectional view showing a structure of an insulating chip in the signal transmission device of FIG. [Figure 20] FIG. 20 is a schematic cross-sectional view showing the configuration of an insulating tip according to a second modified example. [Figure 21] FIG. 21 is a schematic cross-sectional view showing the configuration of an insulating tip according to a third modified example. [Figure 22] FIG. 22 is a schematic cross-sectional view showing the configuration of an insulating tip according to a fourth modified example. [Diagram 23] FIG. 23 is a schematic cross-sectional view showing the configuration of the insulating chip of FIG.

[0007] [Detailed Description] Hereinafter, an embodiment of an insulating chip and a signal transmission device according to the present disclosure will be described with reference to the accompanying drawings. Note that, for simplicity and clarity of description, the components shown in the drawings are not necessarily drawn to scale. Also, hatching lines may be omitted in cross-sectional views to facilitate understanding. The accompanying drawings are merely illustrative of embodiments of the present disclosure and should not be considered as limiting the present disclosure.

[0008] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0009] <Embodiment> [Circuit configuration of signal transmission device] The configuration of a signal transmission device 10 according to an embodiment will be described with reference to Fig. 1. Fig. 1 shows a schematic circuit configuration of the signal transmission device 10.

[0010] As shown in Fig. 1, the signal transmission device 10 is configured to transmit a pulse signal while electrically insulating between a primary side terminal 11 and a secondary side terminal 12. The signal transmission device 10 is, for example, a digital isolator. An example of a digital isolator is a DC / DC converter. The signal transmission device 10 of one embodiment includes a signal transmission circuit 10A having a primary side circuit 13 electrically connected to the primary side terminal 11, a secondary side circuit 14 electrically connected to the secondary side terminal 12, and a transformer 15 that electrically insulates the primary side circuit 13 and the secondary side circuit 14.

[0011] The primary circuit 13 is configured to operate when a first voltage V1 is applied to it. The primary circuit 13 is electrically connected to, for example, an external control device (not shown). The secondary circuit 14 is configured to operate when a second voltage V2 different from the first voltage V1 is applied to it. The first voltage V1 and the second voltage V2 are DC voltages. The secondary circuit 14 is electrically connected to, for example, a drive circuit (not shown) that is controlled by the control device. An example of the drive circuit is a switching circuit including a switching element. Examples of the switching element include a SiMOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), a SiCMOSFET, and an IGBT (Insulated Gate Bipolar Transistor). The secondary circuit 14 is electrically connected to a gate of the switching element. The secondary circuit 14 supplies a gate drive signal to the gate of the switching element. In the signal transmission circuit 10A, when a control signal from the control device is input to the primary side circuit 13 via the primary side terminal 11, the signal is transmitted from the primary side circuit 13 to the secondary side circuit 14 via the transformer 15. Then, the signal transmitted to the secondary side circuit 14 is output from the secondary side circuit 14 to the drive circuit via the secondary side terminal 12.

[0012] The signal transmitted from the primary circuit 13 to the secondary circuit 14, i.e., the signal output from the primary circuit 13, is, for example, a signal for driving a switching element. Examples of this signal include a set signal (SET) and a reset signal (RESET). The set signal is a signal that transmits the rising edge of a control signal from the control device, and the reset signal is a signal that transmits the falling edge of a control signal from the control device. The set signal and the reset signal can be said to be signals for generating a gate drive signal for a switching element.

[0013] The secondary side circuit 14 generates a gate drive signal for driving the switching element based on the set signal and reset signal received from the primary side circuit 13. Then, the secondary side circuit 14 supplies the gate drive signal to the gate of the switching element. In other words, it can be said that the secondary side circuit 14 generates a gate drive signal to be supplied to the gate of the switching element based on the first signal output from the primary side circuit 13. In this way, the signal transmission device 10 controls the on / off of the switching element.

[0014] As described above, the primary circuit 13 and the secondary circuit 14 are electrically insulated by the transformer 15. More specifically, the transformer 15 restricts the transmission of DC voltage between the primary circuit 13 and the secondary circuit 14, while allowing the transmission of various signals such as a set signal and a reset signal.

[0015] The withstand voltage of the signal transmission device 10 is, for example, 2500Vrms or more and 7500Vrms or less. In one example, the withstand voltage of the signal transmission device 10 is about 5000Vrms. However, the specific value of the withstand voltage of the signal transmission device 10 is not limited to this and can be changed arbitrarily. In the example shown in FIG. 1, the ground GND1 of the primary side circuit 13 and the ground GND2 of the secondary side circuit 14 are provided independently. Hereinafter, the potential of the ground GND1 of the primary side circuit 13 is defined as a first reference potential, and the potential of the ground GND2 of the secondary side circuit 14 is defined as a second reference potential. In this case, the first voltage V1 is a voltage from the first reference potential, and the second voltage V2 is a voltage from the second reference potential. The first voltage V1 is, for example, 4.5V or more and 5.5V or less, and the second voltage V2 is, for example, 9V or more and 24V or less.

[0016] The signal transmission device 10 includes two transformers 15 corresponding to the transmission of two types of signals, a set signal and a reset signal, from the primary side circuit 13 to the secondary side circuit 14. More specifically, the signal transmission device 10 includes a transformer 15 used to transmit a set signal from the primary side circuit 13 to the secondary side circuit 14, and a transformer 15 used to transmit a reset signal from the primary side circuit 13 to the secondary side circuit 14. Hereinafter, for convenience of explanation, the transformer 15 used to transmit the set signal will be referred to as "transformer 15A," and the transformer 15 used to transmit the reset signal will be referred to as "transformer 15B."

[0017] The signal transmission device 10 includes a primary signal line 16A that connects the primary circuit 13 and the transformer 15A, and a primary signal line 16B that connects the primary circuit 13 and the transformer 15B. Therefore, the primary signal line 16A transmits a set signal from the primary circuit 13 to the transformer 15A. The primary signal line 16B transmits a reset signal from the primary circuit 13 to the transformer 15B.

[0018] The signal transmission device 10 includes a secondary signal line 17A that connects the transformer 15A and the secondary circuit 14, and a secondary signal line 17B that connects the transformer 15B and the secondary circuit 14. Therefore, the secondary signal line 17A transmits a set signal from the transformer 15A to the secondary circuit 14. The secondary signal line 17B transmits a reset signal from the transformer 15B to the secondary circuit 14.

[0019] The transformer 15A is configured to electrically insulate the primary side circuit 13 from the secondary side circuit 14 while transmitting a set signal from the primary side circuit 13 to the secondary side circuit 14. The transformer 15B is configured to electrically insulate the primary side circuit 13 from the secondary side circuit 14 while transmitting a reset signal from the primary side circuit 13 to the secondary side circuit 14.

[0020] The transformers 15A and 15B include a first coil 21 and a second coil 22. The first coil 21 and the second coil 22 are electrically insulated from each other and configured to be magnetically coupled. Here, in the present disclosure, the first coil 21 is an example of a "first insulating element" and the second coil 22 is an example of a "second insulating element."

[0021] The first coils 21 of the transformers 15A and 15B are electrically connected to the primary circuit 13. In one example, a first end of the first coil 21 of the transformer 15A is electrically connected to the primary circuit 13 by a primary signal line 16A, and a second end of the first coil 21 of the transformer 15A is electrically connected to the ground GND1 of the primary circuit 13. A first end of the first coil 21 of the transformer 15B is electrically connected to the primary circuit 13 by a primary signal line 16B, and a second end of the first coil 21 of the transformer 15B is electrically connected to the ground GND1 of the primary circuit 13. Therefore, the potential of the second end of the first coil 21 of the transformers 15A and 15B becomes a first reference potential. The first reference potential is, for example, 0V.

[0022] The second coils 22 of the transformers 15A and 15B are electrically connected to the secondary circuit 14. In one example, a first end of the second coil 22 of the transformer 15A is electrically connected to the secondary circuit 14 by the secondary signal line 17A, and a second end of the second coil 22 of the transformer 15A is electrically connected to the ground GND2 of the secondary circuit 14. A first end of the second coil 22 of the transformer 15B is electrically connected to the secondary circuit 14 by the secondary signal line 17B, and a second end of the second coil 22 of the transformer 15B is electrically connected to the ground GND2 of the secondary circuit 14. Therefore, the potential of the second end of the second coil 22 of the transformers 15A and 15B becomes the second reference potential. The ground GND2 of the secondary circuit 14 is electrically connected to, for example, the source of a switching element in a switching circuit electrically connected to the secondary circuit 14.

[0023] [Internal structure of the signal transmission device] Next, an example of the internal structure of the signal transmission device 10 will be described with reference to Fig. 2. Fig. 2 shows a schematic plan view of the inside of the signal transmission device 10. Note that, since Fig. 1 shows a simplified circuit configuration of the signal transmission device 10, the number of external terminals (primary side terminals 11 and secondary side terminals 12) of the signal transmission device 10 in Fig. 2 is greater than the number of external terminals of the signal transmission device 10 in Fig. 1. In addition, the number of signal lines (the number of wires W1 to W4 described later) that transmit signals from the primary side circuit 13 to the secondary side circuit 14 in the signal transmission device 10 in Fig. 2 is greater than the number of signal lines in the signal transmission device 10 in Fig. 1.

[0024] As shown in FIG. 2, the signal transmission device 10 is a semiconductor device in which a plurality of semiconductor chips are packaged together. The signal transmission device 10 includes a first chip 30, a second chip 40, and a transformer chip 50 as semiconductor chips. The signal transmission device 10 also includes a first conductive member 60 on which the first chip 30 is arranged, a second conductive member 70 on which the second chip 40 is arranged, and a sealing resin 80 that seals a part of each of the chips 30, 40, 50 and each of the conductive members 60, 70. In one example, the conductive members 60, 70 are formed by the same lead frame. In this disclosure, the transformer chip 50 is an example of an "insulating chip". The package format of the signal transmission device 10 can be changed as desired. In FIG. 2, the sealing resin 80 is indicated by a two-dot chain line for the convenience of explaining the internal structure of the signal transmission device 10.

[0025] The sealing resin 80 is made of a material having electrical insulation properties. In one example, the sealing resin 80 is made of a resin containing, for example, epoxy resin. The sealing resin 80 is formed in a rectangular plate shape with the Z direction as the thickness direction. The sealing resin 80 has four resin side surfaces 81 to 84. The resin side surfaces 81 and 82 constitute both end faces of the sealing resin 80 in the X direction. The resin side surfaces 83 and 84 constitute both end faces of the sealing resin 80 in the Y direction. In the following description, the signal transmission device 10 and its components viewed from the Z direction will be referred to as a "planar view". The X direction and the Y direction are directions that intersect with the Z direction and are orthogonal to each other in a planar view. In one example, both the X direction and the Y direction are directions that are orthogonal to the Z direction. In the present disclosure, the X direction is an example of a "first direction".

[0026] Each of the first conductive member 60 and the second conductive member 70 is a conductor and is formed of a material containing, for example, Cu (copper), Fe (iron), etc. Each of the conductive members 60, 70 is provided across the inside and outside of the sealing resin 80.

[0027] The first conductive member 60 includes a first die pad 61 disposed within the sealing resin 80, and a plurality of first leads 62 disposed across the inside and outside of the sealing resin 80. Each of the first leads 62 constitutes a primary side terminal 11 (see FIG. 1).

[0028] 2, both the first chip 30 and the transformer chip 50 are disposed on the first die pad 61. In a plan view, the first die pad 61 is disposed such that its center in the X direction is closer to the resin side surface 81 than the center in the X direction of the sealing resin 80. In one example, the first die pad 61 is not exposed from the sealing resin 80. The first die pad 61 is formed in a rectangular flat plate shape with the thickness direction being the Z direction. The shape of the first die pad 61 in a plan view is a rectangle with the Y direction as the longitudinal direction and the X direction as the lateral direction.

[0029] The multiple first leads 62 are arranged spaced apart from each other in the Y direction. Of the multiple first leads 62, the first leads 62 arranged at both ends in the Y direction are each integrated with the first die pad 61. A portion of each first lead 62 protrudes from the resin side surface 81 toward the outside of the sealing resin 80.

[0030] The second conductive member 70 includes a second die pad 71 disposed within the sealing resin 80, and a plurality of second leads 72 disposed across the inside and outside of the sealing resin 80. Each of the second leads 72 constitutes a secondary side terminal 12 (see FIG. 1).

[0031] 2, the second chip 40 is disposed on the second die pad 71. In a plan view, the second die pad 71 is disposed closer to the resin side surface 82 than the first die pad 61 and is spaced apart from the first die pad 61 in the X direction. In this manner, the first die pad 61 and the second die pad 71 are arranged in the X direction, and therefore the X direction can be said to be the arrangement direction of the first die pad 61 and the second die pad 71.

[0032] In one example, the second die pad 71 is not exposed from the sealing resin 80. The second die pad 71 is formed in a rectangular flat plate shape with the thickness direction being the Z direction. The shape of the second die pad 71 in a plan view is a rectangle with the Y direction as the longitudinal direction and the X direction as the lateral direction. The dimensions in the X direction of the first die pad 61 and the second die pad 71 are set according to the size and number of the semiconductor chips to be arranged. For this reason, the dimension in the X direction of the first die pad 61 on which both the first chip 30 and the transformer chip 50 are arranged is larger than the dimension in the X direction of the second die pad 71 on which the second chip 40 is arranged.

[0033] The multiple second leads 72 are arranged spaced apart from each other in the Y direction. In the example shown in Fig. 2, a pair of the multiple second leads 72 are integrated with the second die pad 71. The pair of second leads 72 are second leads 72 adjacent in the Y direction to each of the second leads 72 arranged at both ends in the Y direction. A portion of each second lead 72 protrudes outward from the resin side surface 82 of the sealing resin 80.

[0034] 2, in a plan view, the multiple first leads 62 are arranged in a direction (Y direction) perpendicular to the arrangement direction (X direction) of the first die pad 61 and the second die pad 71. The multiple second leads 72 are also arranged in a direction (Y direction) perpendicular to the arrangement direction (X direction) of the first die pad 61 and the second die pad 71. Note that the number of the first leads 62 and the number of the second leads 72 can each be changed arbitrarily.

[0035] 2, the first die pad 61 is supported by a pair of first leads 62 that are integrated with the first die pad 61. The second die pad 71 is supported by a pair of second leads 72 that are integrated with the second die pad 71.

[0036] The first chip 30 and the transformer chip 50 are arranged on the first die pad 61 at a distance from each other in the X direction. The second chip 40 is arranged on the opposite side of the transformer chip 50 from the first chip 30 in the X direction. In this way, the first chip 30, the second chip 40, and the transformer chip 50 are arranged at a distance from each other in the X direction. It can be said that the first chip 30, the second chip 40, and the transformer chip 50 are arranged in the same direction as the arrangement direction of the first die pad 61 and the second die pad 71. In the X direction, the first chip 30, the transformer chip 50, and the second chip 40 are arranged in this order from the first lead 62 to the second lead 72. In other words, it can be said that the transformer chip 50 is arranged between the first chip 30 and the second chip 40 in the X direction.

[0037] The first chip 30 includes the primary side circuit 13 shown in Fig. 1. The first chip 30 is formed in a rectangular plate shape with the thickness direction being in the Z direction. The shape of the first chip 30 in a plan view is a rectangle with the short side direction being in the X direction and the long side direction being in the Y direction.

[0038] The back surface of the first chip 30 is bonded to the first die pad 61 by a conductive bonding material. The conductive bonding material may be, for example, a solder paste or an Ag (silver) paste.

[0039] A plurality of first pads 33, a plurality of second pads 34, and a plurality of third pads 35 are formed on a chip surface 31 of the first chip 30. The first pads 33, the second pads 34, and the third pads 35 are electrically connected to the primary side circuit 13.

[0040] The multiple first pads 33 are arranged on the chip surface 31 closer to the first lead 62 than the center of the chip surface 31 in the X direction. The multiple first pads 33 are arranged spaced apart from each other in the Y direction. The multiple second pads 34 are arranged at one end of the chip surface 31 in the X direction that is closer to the transformer chip 50. The multiple second pads 34 are arranged spaced apart from each other in the Y direction. The multiple third pads 35 are arranged separately at both ends of the chip surface 31 in the Y direction.

[0041] The second chip 40 includes the secondary side circuit 14 shown in Fig. 1. The second chip 40 is formed in a rectangular plate shape with the thickness direction being the Z direction. The back surface of the second chip 40 is joined to the second die pad 71 by a conductive bonding material such as solder paste or Ag paste.

[0042] A plurality of first pads 43, a plurality of second pads 44, and a plurality of third pads 45 are formed on a chip surface 41 of the second chip 40. The first pads 43, the second pads 44, and the third pads 45 are electrically connected to the secondary side circuit 14.

[0043] The multiple first pads 43 are formed on one of both ends in the X direction of the chip surface 41, which is closer to the transformer chip 50. The multiple first pads 43 are arranged spaced apart from each other in the Y direction. The multiple second pads 44 are formed on one of both ends in the X direction of the chip surface 41, which is closer to the second lead 72. The multiple second pads 44 are arranged spaced apart from each other in the Y direction. The multiple third pads 45 are arranged separately at both ends in the Y direction of the chip surface 41.

[0044] In this embodiment, the transformer chip 50 is a single chip including the transformers 15A and 15B shown in Fig. 1. In other words, the transformer chip 50 is a chip dedicated to the transformers 15A and 15B, which is provided separately from the first chip 30 and the second chip 40.

[0045] The transformer chip 50 has a first chip surface 51 and a second chip surface 52 that are located at different positions in the Z direction, and a chip back surface 53 (see FIG. 4) that faces the opposite side to the first chip surface 51 and the second chip surface 52. The second chip surface 52 is located on the opposite side to the first die pad 61 with respect to the first chip surface 51 in the Z direction. In other words, the first chip surface 51 is disposed closer to the first die pad 61 than the second chip surface 52 in the Z direction. The chip back surface 53 of the transformer chip 50 is bonded to the first die pad 61 by a conductive bonding material SD (see FIG. 4).

[0046] 2, the distance between the transformer chip 50 and the second chip 40 in the X direction in a plan view is greater than the distance between the transformer chip 50 and the first chip 30 in the X direction. On the other hand, the transformer chip 50 and the first chip 30 are disposed on the first die pad 61, and therefore may be disposed closer to each other. For this reason, it can be said that the transformer chip 50 is disposed closer to the first chip 30 than the second chip 40.

[0047] As shown in FIG. 2, a plurality of first pads 54 are formed on the first chip surface 51 of the transformer chip 50. The plurality of first pads 54 are formed on the end closer to the first chip 30 among both ends in the X direction of the first chip surface 51. The plurality of first pads 54 are arranged at a distance from each other in the Y direction. A plurality of second pads 55 are formed on the second chip surface 52 of the transformer chip 50. The plurality of second pads 55 are formed on the end closer to the second chip 40 among both ends in the X direction of the second chip surface 52. The plurality of second pads 55 are arranged at a distance from each other in the X direction and the Y direction. Here, in the present disclosure, the plurality of first pads 54 are an example of a "first pad", and the plurality of second pads 55 are an example of a "second pad".

[0048] A plurality of wires W1 to W4 are connected to each of the first chip 30, the transformer chip 50, and the second chip 40. Each of the wires W1 to W4 is a bonding wire formed by a wire bonding apparatus, and is made of a conductor including, for example, Au (gold), Al (aluminum), Cu, or the like.

[0049] The first chip 30 is electrically connected to the first conductive member 60 by the wire W1. More specifically, the first pads 33 and the third pads 35 of the first chip 30 are individually electrically connected to the first leads 62 by the wire W1. The third pads 35 are individually electrically connected to a pair of the first leads 62 that are integrated with the first die pad 61 among the first leads 62 by the wire W1. This electrically connects the primary circuit 13 to the first leads 62 (primary terminals 11). In the example shown in FIG. 2, the pair of first leads 62 that are integrated with the first die pad 61 constitute a ground terminal, and the primary circuit 13 and the first die pad 61 are electrically connected by the wire W1. Therefore, the first die pad 61 has the same potential as the ground GND1 of the primary circuit 13.

[0050] The second chip 40 is electrically connected to the second conductive member 70 by the wire W4. More specifically, the second pads 44 and the third pads 45 of the second chip 40 are individually electrically connected to the second leads 72 by the wire W4. The third pads 45 are individually electrically connected to a pair of second leads 72 that are integrated with the second die pad 71 among the second leads 72 by the wire W4. This electrically connects the secondary circuit 14 to the second leads 72 (secondary terminals 12). In the example shown in FIG. 2, the pair of second leads 72 that are integrated with the second die pad 71 constitute ground terminals, and the secondary circuit 14 and the second die pad 71 are electrically connected by the wire W4. Therefore, the second die pad 71 has the same potential as the ground GND2 of the secondary circuit 14.

[0051] The transformer chip 50 is electrically connected to the first chip 30 by wires W2. The transformer chip 50 is also electrically connected to the second chip 40 by wires W3. More specifically, the first pads 54 of the transformer chip 50 are individually electrically connected to the second pads 34 of the first chip 30 by wires W2. The second pads 55 of the transformer chip 50 are individually electrically connected to the first pads 33 of the second chip 40 by wires W3.

[0052] The first coil 21 of the transformers 15A and 15B is electrically connected to the ground GND1 (see FIG. 1) of the primary circuit 13 via the wire W2, the first chip 30, etc. The second coil 22 of the transformers 15A and 15B is electrically connected to the ground GND2 (see FIG. 1) of the secondary circuit 14 via the wire W3, the second chip 40, etc.

[0053] [Trans chip configuration] An example of the configuration of the transformer chip 50 will be described with reference to FIGS. FIG. 3 is a schematic diagram showing the planar structure of the transformer chip 50. FIG. 4 is a schematic diagram showing the cross-sectional structure of the transformer chip 50 taken along the line F4-F4 in FIG. 3. FIG. 5 is a schematic diagram showing the planar structure of the second unit 100 of the transformer chip 50 in FIG. 3. FIG. 6 is a schematic diagram showing the planar structure of the first unit 90 of the transformer chip 50. FIG. 7 is an enlarged view of the first coil 21, the second coil 22, and their surroundings of the transformer 15A in the cross-sectional structure of the transformer chip 50 in FIG. 4. FIG. 8 is an enlarged view of the second pad 55A and their surroundings in the cross-sectional structure of the transformer chip 50 in FIG. 4.

[0054] 3, the transformer chip 50 includes a first unit 90 and a second unit 100 joined onto the first unit 90. In the following, the configuration of the first unit 90 and the configuration of the second unit 100 will be described, and then the configuration of the transformer chip 50 combining the first unit 90 and the second unit 100 will be described. Note that the configurations of the first coil 21 and the second coil 22 of the transformer 15B are similar to the configurations of the first coil 21 and the second coil 22 of the transformer 15A, so in the following, the transformer 15A will be described, and a detailed description of the transformer 15B will be omitted.

[0055] (1st Unit) The configuration of the first unit 90 will be described with reference to FIGS. 4, the first unit 90 is a unit of the transformer chip 50 that is bonded to the first die pad 61. The first unit 90 includes a first semiconductor substrate 91 having a first substrate surface 91A and a first substrate back surface 91B opposite to the first substrate surface 91A, and a first element insulating layer 92 formed on the first substrate surface 91A.

[0056] A first substrate surface 91A of the first semiconductor substrate 91 faces the same side as the chip surface 51 of the transformer chip 50. A first substrate back surface 91B of the first semiconductor substrate 91 constitutes the chip back surface 53 of the transformer chip 50. The first semiconductor substrate 91 is formed in a rectangular plate shape with the thickness direction being the Z direction. The first semiconductor substrate 91 is formed of a material containing Si, for example. In this embodiment, the first semiconductor substrate 91 is a Si substrate. Note that a wide band gap semiconductor or a compound semiconductor may be used for the first semiconductor substrate 91. The wide band gap semiconductor is a semiconductor substrate having a band gap of 2.0 eV or more. The wide band gap semiconductor may be SiC (silicon carbide). The compound semiconductor may be a III-V group compound semiconductor. The compound semiconductor may include at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).

[0057] 6, the first element insulating layer 92 is formed in a rectangular shape with the X direction as the short side direction and the Y direction as the long side direction in a plan view. The first element insulating layer 92 includes four first element side surfaces 92C to 92F. The first element side surfaces 92C and 92D constitute both end surfaces of the first element insulating layer 92 in the X direction. The first element side surfaces 92E and 92F constitute both end surfaces of the first element insulating layer 92 in the Y direction. In the X direction, the first element side surface 92C is a side surface closer to the resin side surface 81 of the sealing resin 80 in FIG. 2, and the first element side surface 92D is a side surface closer to the resin side surface 82. In the Y direction, the first element side surface 92E is a side surface closer to the resin side surface 83 of the sealing resin 80, and the first element side surface 92F is a side surface closer to the resin side surface 84.

[0058] 7, the first element insulating layer 92 includes an insulator 92R composed of a plurality of first insulating films 92P and a plurality of second insulating films 92Q. The insulator 92R is formed by stacking the plurality of first insulating films 92P and the plurality of second insulating films 92Q alternately one by one in the Z direction. For this reason, the Z direction can also be said to be the thickness direction of the first element insulating layer 92.

[0059] The first insulating film 92P is an etching stopper film, and is formed of a material including at least one of, for example, SiN (silicon nitride), SiC, and SiCN (nitrogen-doped silicon carbide). The first insulating film 92P may have a function of preventing the diffusion of, for example, Cu. That is, the first insulating film 92P may be a film for preventing the diffusion of Cu.

[0060] The second insulating film 92Q is an interlayer insulating film, and is, for example, an oxide film formed of a material containing SiO2 (silicon oxide). The second insulating film 92Q has a thickness greater than that of the first insulating film 92P. The first insulating film 92P has a thickness of, for example, 50 nm or more and less than 1000 nm. The second insulating film 92Q has a thickness of, for example, 500 nm or more and 5000 nm or less. In this embodiment, the first insulating film 92P has a thickness of about 300 nm, and the second insulating film 92Q has a thickness of about 2000 nm. In order to easily understand the drawings, the ratio between the thickness of the first insulating film 92P and the thickness of the second insulating film 92Q in the drawings is different from the actual ratio between the thickness of the first insulating film 92P and the thickness of the second insulating film 92Q.

[0061] The first element insulating layer 92 has a first element front surface 92A and a first element back surface 92B facing opposite sides to each other in the Z direction. The first element front surface 92A faces the same side as the first chip front surface 51 and the second chip front surface 52 of the transformer chip 50. The first element front surface 92A constitutes, for example, the first chip front surface 51. The first element back surface 92B faces the same side as the chip back surface 53 of the transformer chip 50. The first element back surface 92B is in contact with the first semiconductor substrate 91. In one example, the first element back surface 92B is constituted by a second insulating film 92Q.

[0062] The first element insulating layer 92 includes a passivation layer 92G formed on the side of the first element surface 92A. The passivation layer 92G is a surface protective film for the first unit 90. The passivation layer 92G is formed on the insulator 92R. The passivation layer 92G is formed of a material including at least one of, for example, SiN and SiO2. In one example, the passivation layer 92G is formed of a material including SiO2. In one example, the passivation layer 92G is formed over the entire surface of the insulator 92R in a plan view. In one example, the passivation layer 92G may be formed of a laminated structure of multiple insulating films.

[0063] 6, first coils 21 of transformers 15A and 15B are provided in the first element insulating layer 92. These first coils 21 are arranged at the same position in the X direction and spaced apart from each other in the Y direction. The first coil 21 of transformer 15A is disposed closer to the first element side surface 92E than the first coil 21 of transformer 15B. Furthermore, these first coils 21 are disposed approximately in the center of the first element insulating layer 92 in the X direction.

[0064] 7, the first coil 21 is embedded in the first element insulating layer 92 at a position spaced apart from the first element front surface 92A of the first element insulating layer 92 in the Z direction. The first coil 21 is also disposed at a position spaced apart from the first element back surface 92B in the Z direction. In other words, the first coil 21 is not exposed from the first element insulating layer 92.

[0065] 6, the first coil 21 is formed in a spiral shape in a plan view. The number of turns of the first coil 21 can be arbitrarily changed according to the electrical characteristics of the transformer chip 50. The first coil 21 is made of a material including one or more appropriately selected from Ti (titanium), TiN (titanium nitride), Au, Ag, Cu, Al, and W (tungsten). In one example, the first coil 21 is made of a material including Cu.

[0066] An inner connection portion 21A and an outer connection portion 21B are electrically connected to the first coil 21. The inner connection portion 21A is disposed inward from the winding portion of the first coil 21 in a plan view. The inner connection portion 21A is connected to a wiring layer drawn out in the X direction from an inner end of the winding portion of the first coil 21. The outer connection portion 21B is disposed outward from the winding portion of the first coil 21 in a plan view.

[0067] The first unit 90 includes a plurality of first pads 54. The first pads 54 are disposed closer to the first element side surface 92C than the first coil 21 in the X direction. In the example shown in Fig. 3 and Fig. 5, three first pads 54 are provided. Hereinafter, for convenience, the three first pads 54 are referred to as "first pads 54A, 54B, 54C."

[0068] More specifically, the first pad 54A is provided in correspondence with the inner connection portion 21A of the first coil 21 of the transformer 15A. The first pad 54C is provided in correspondence with the inner connection portion 21A of the first coil 21 of the transformer 15B. The first pad 54B is provided in correspondence with the outer connection portion 21B connected to both the first coil 21 of the transformer 15A and the first coil 21 of the transformer 15B. The first pad 54B is electrically connected to the outer connection portion 21B. In one example, the outer connection portion 21B is a common connection portion of the first coil 21 of the transformer 15A and the first coil 21 of the transformer 15B. In other words, the second pad 55B constitutes a common pad for the first coil 21 of the transformer 15A and the first coil 21 of the transformer 15B.

[0069] The first pad 54A is disposed at a position overlapping the first coil 21 of the transformer 15A when viewed from the X direction. The first pad 54B is disposed between the first coil 21 of the transformer 15A and the first coil 21 of the transformer 15B in the Y direction. The first pad 54C is disposed at a position overlapping the first coil 21 of the transformer 15B when viewed from the X direction. The positions of the first pads 54A to 54C in the Y direction can be changed arbitrarily. The number of first pads 54 is not limited to the example shown in FIG. 6 and can be changed arbitrarily. In one example, two of each of the first pads 54A to 54C may be provided.

[0070] 7, the first pads 54A to 54C are provided on, for example, an insulator 92R and exposed from a passivation layer 92G. That is, the first pads 54A to 54C are provided on the first element insulating layer 92 so as to be exposed from a first element surface 92A of the first element insulating layer 92. Note that FIG. 7 shows the configuration of the first pad 54A.

[0071] 6 and 7, the first unit 90 includes a first connection portion 93 that electrically connects the inner connection portion 21A of the first coil 21 of the transformer 15A to the first pad 54A. The first connection portion 93 is embedded in the first element insulating layer 92. That is, the first coil 21 and the first pad 54A are electrically connected to each other in the first element insulating layer 92.

[0072] As shown in FIG. 7, the first connection portion 93 includes a first connection body 93A, a first connection wiring 93B, and a second connection body 93C. The first connection body 93A electrically connects the first connection wiring 93B and the first pad 54A. The first connection body 93A is disposed at a position overlapping both the first pad 54A of the first coil 21 and the first connection wiring 93B in a plan view. In the example shown in FIG. 7, the first connection body 93A is formed of a plurality of vias 93AA extending in the Z direction from the first connection wiring 93B as viewed from the Y direction, a conductive layer 93AB formed on the plurality of vias 93AA, and a plurality of vias 93AC formed on the conductive layer 93AB. The conductive layer 93AB is disposed at the same position as the first coil 21 in the Z direction. The plurality of vias 93AC are in contact with the first pad 54A. The configuration of the first connection body 93A can be changed arbitrarily, and for example, the first connection body 93A may be one via.

[0073] The first connection wiring 93B electrically connects the first connection body 93A and the second connection body 93C. The first connection wiring 93B includes an end 93BA overlapping the first connection body 93A and an end 93BB overlapping the inner connection portion 21A of the first coil 21 in a plan view. In one example, the end 93BB of the first connection wiring 93B may be the same size as the inner connection portion 21A of the first coil 21 in a plan view. In one example, the end 93BA of the first connection wiring 93B may be the same size as the conductive layer 93AB in a plan view. The first connection wiring 93B is disposed closer to the first element back surface 92B than the first coil 21 in the Z direction. The first connection wiring 93B is formed as a wiring layer extending in the X direction.

[0074] The second connection body 93C electrically connects the inner connection portion 21A of the first coil 21 and the end portion 93BB of the first connection wiring 93B. The second connection body 93C is disposed at a position overlapping both the inner connection portion 21A of the first coil 21 and the first connection wiring 93B in a plan view. The second connection body 93C is disposed closer to the first element back surface 92B than the first coil 21 in the Z direction. In the example shown in FIG. 7, the second connection body 93C is a via extending in the Z direction from the inner connection portion 21A of the first coil 21 when viewed from the Y direction.

[0075] The first connector 93A, the first connection wiring 93B, and the second connector 93C are made of a material including one or more appropriately selected from, for example, Ti, TiN, Au, Ag, Cu, Al, and W. In one example, the first connector 93A may be made of the same material as the first coil 21. In one example, the first connection wiring 93B and the second connector 93C may be made of a material different from that of the first coil 21.

[0076] As shown in FIG. 6, the first unit 90 includes a second connection portion 94 that electrically connects the outer connection portion 21B connected to both the first coil 21 of the transformer 15A and the first coil 21 of the transformer 15B to the first pad 54B. The second connection portion 94 is embedded in the first element insulating layer 92. That is, the first coils 21 and the first pad 54B of the transformers 15A and 15B are electrically connected to each other in the first element insulating layer 92. In a plan view, the second connection portion 94 is disposed at approximately the center in the Y direction of the second unit 100. Although not shown, the second connection portion 94 is disposed at the same position as the first connection portion 93 in the Z direction. The configuration of the second connection portion 94 is the same as that of the first connection portion 93.

[0077] The first unit 90 includes a first connection portion 95 that electrically connects the inner connection portion 21A of the first coil 21 of the transformer 15B and the first pad 54C. The configuration of the first connection portion 95 is the same as the configuration of the first connection portion 93.

[0078] As shown in FIG. 7, in this embodiment, the first element insulating layer 92 is composed of first to fifth insulating layers 921 to 925 that form an insulator 92R, and a passivation layer 92G.

[0079] The first insulating layer 921 is in contact with the first semiconductor substrate 91. That is, the first insulating layer 921 constitutes the insulating film of the lowest layer of the insulator 92R. The second insulating layer 922 is laminated on the first insulating layer 921. The second insulating layer 922 is provided with a first connection wiring 93B electrically connected to the first coil 21. The third insulating layer 923 is laminated on the second insulating layer 922. The third insulating layer 923 is provided with a plurality of vias 93AA of the first connector 93A and the second connector 93C. The fourth insulating layer 924 is laminated on the third insulating layer 923. The first coil 21, the inner connection portion 21A, and the conductive layer 93AB of the first connector 93A are provided on the fourth insulating layer 924. The third insulating layer 923 covers the first coil 21 from the first semiconductor substrate 91 side. The fifth insulating layer 925 is laminated on the fourth insulating layer 924. Therefore, the fifth insulating layer 925 covers the first coil 21. A plurality of vias 93AC of the first connector 93A are provided in the fifth insulating layer 925. On the fifth insulating layer 925, a first pad 54A is provided.

[0080] In this manner, it can be said that the first coil 21 is embedded in the third to fifth insulating layers 923-925. It can be said that the first connection portion 93 is embedded in the first to fifth insulating layers 921-925. The passivation layer 92G is laminated on the fifth insulating layer 925. The passivation layer 92G is formed, for example, over substantially the entire surface of the fifth insulating layer 925. On the other hand, the passivation layer 92G exposes the first pad 54A.

[0081] The first insulating layer 921, which is the lowest layer of the insulator 92R, is composed of a second insulating film 92Q containing SiO2. That is, the first insulating layer 921 does not include the first insulating film 92P containing SiN. On the other hand, each of the second to fifth insulating layers 922-925 on the first insulating layer 921 is composed of the first insulating film 92P and a second insulating film 92Q laminated on the first insulating film 92P.

[0082] (Unit 2) The configuration of second unit 100 will be described with reference to FIGS. As shown in FIG. 4, the second unit 100 is a unit that is arranged on the opposite side of the first die pad 61 with respect to the first unit 90 in the transformer chip 50 in the Z direction.

[0083] The second unit 100 includes a second semiconductor substrate 101 having a second substrate surface 101A and a second substrate back surface 101B opposite to the second substrate surface 101A, and a second element insulating layer 102 formed on the second substrate surface 101A.

[0084] The second semiconductor substrate 101 is formed in a rectangular plate shape with the thickness direction being in the Z direction. In one example, a protruding portion 101D protruding toward the sealing resin 80 is present on a side surface of the second semiconductor substrate 101 closer to a resin side surface 81 (see FIG. 2) of the sealing resin 80. The protruding portion 101D is formed over the entire second semiconductor substrate 101 in the Y direction, for example. The protruding portion 101D is formed due to a manufacturing method described later. In the example shown in FIG. 4, the front surface of the protruding portion 101D is a rectangular convex portion formed flush with the second substrate rear surface 101B, but the arrangement and shape of the protruding portion 101D are not limited thereto.

[0085] The second semiconductor substrate 101 is formed of, for example, a material containing Si. In this embodiment, the second semiconductor substrate 101 is a Si substrate. Note that, like the first semiconductor substrate 91, the second semiconductor substrate 101 may be made of a wide band gap semiconductor or a compound semiconductor. In this embodiment, the electrical resistivity of the second semiconductor substrate 101 is smaller than the electrical resistivity of the first semiconductor substrate 91. The impurity concentration of the second semiconductor substrate 101 is higher than the impurity concentration of the first semiconductor substrate 91. In one example, the thickness of the second semiconductor substrate 101 is smaller than the thickness of the first semiconductor substrate 91.

[0086] The second element insulating layer 102 is disposed on the first unit 90 side with respect to the second semiconductor substrate 101 in the Z direction. It can be said that the second element insulating layer 102 is disposed between the second semiconductor substrate 101 and the first unit 90 in the Z direction. Therefore, the second substrate back surface 101B of the second semiconductor substrate 101 constitutes the second chip front surface 52.

[0087] As shown in FIG. 5, the second element insulating layer 102 is formed in a rectangular shape with the X direction being the short side direction and the Y direction being the long side direction in a plan view. The second element insulating layer 102 includes four second element side surfaces 102C to 102F. The second element side surfaces 102C and 102D constitute both end faces in the X direction of the second element insulating layer 102. The second element side surfaces 102E and 102F constitute both end faces in the Y direction of the second element insulating layer 102. In the X direction, the second element side surface 102C is a side surface closer to the resin side surface 81 of the sealing resin 80 in FIG. 2, and the second element side surface 102D is a side surface closer to the resin side surface 82. In the Y direction, the second element side surface 102E is a side surface closer to the resin side surface 83 of the sealing resin 80, and the second element side surface 102F is a side surface closer to the resin side surface 84. In the example shown in FIGS. 3 and 4, second element side surface 102C is located closer to the first element side surface 92D than the first element side surface 92C.

[0088] 8, the second element insulating layer 102 includes an insulator 102R composed of a plurality of first insulating films 102P and a plurality of second insulating films 102Q. The insulator 102R is composed of a plurality of first insulating films 102P and a plurality of second insulating films 102Q alternately stacked one by one in the Z direction. For this reason, the Z direction can also be said to be the thickness direction of the second element insulating layer 102.

[0089] The first insulating film 102P is an etching stopper film, and is formed of a material containing at least one of, for example, SiN, SiC, and SiCN. The first insulating film 102P may have a function of preventing the diffusion of, for example, Cu. In other words, the first insulating film 102P may be a diffusion prevention film for Cu.

[0090] The second insulating film 102Q is an interlayer insulating film, and is, for example, an oxide film formed of a material containing SiO2. The second insulating film 102Q has a thickness greater than that of the first insulating film 102P. In one example, the second insulating film 102Q may have the same thickness as the second insulating film 92Q of the first element insulating layer 92. In one example, the first insulating film 102P may have the same thickness as the first insulating film 92P of the first element insulating layer 92. The first insulating film 102P has a thickness of, for example, 50 nm or more and less than 1000 nm. The second insulating film 102Q has a thickness of, for example, 500 nm or more and 5000 nm or less. In one embodiment, the first insulating film 102P has a thickness of about 300 nm, and the second insulating film 102Q has a thickness of about 2000 nm. In one example, the number of the first insulating films 102P may be the same as the number of the first insulating films 92P of the first element insulating layer 92. The number of second insulating films 102Q may be the same as the second insulating films 92Q of the first element insulating layer 92. In this manner, the thickness of the insulator 102R, which is a stack of the multiple first insulating films 102P and the multiple second insulating films 102Q, may be equal to the thickness of the insulator 92R. Note that, in order to facilitate understanding of the drawings, the ratio of the film thickness of the first insulating film 102P to the film thickness of the second insulating film 102Q in the drawings differs from the actual ratio of the film thickness of the first insulating film 102P to the film thickness of the second insulating film 102Q.

[0091] The second element insulating layer 102 has a second element front surface 102A and a second element back surface 102B facing opposite directions in the Z direction. The second element front surface 102A faces the first unit 90. The second element back surface 102B contacts the second semiconductor substrate 101. The second element insulating layer 102 includes a passivation layer 102G formed on the side of the second element front surface 102A. The passivation layer 102G constitutes the second element front surface 102A.

[0092] The passivation layer 102G is a surface protective film of the second unit 100. The passivation layer 102G is formed on the insulator 102R. The passivation layer 102G is formed of a material including at least one of SiN and SiO2. In one example, the passivation layer 102G is formed over the entire surface of the insulator 102R in a plan view. The passivation layer 102G may be formed of multiple laminated layers.

[0093] The second element insulating layer 102 includes a substrate-side insulating layer 102J interposed between the second semiconductor substrate 101 and the insulator 102R in the Z direction. The substrate-side insulating layer 102J is in contact with the second substrate surface 101A of the second semiconductor substrate 101. In other words, the substrate-side insulating layer 102J constitutes the second element rear surface 102B of the second element insulating layer 102. The substrate-side insulating layer 102J is formed of a material containing SiO2. In one example, the substrate-side insulating layer 102J is a thermal oxide film.

[0094] The second coils 22 of the transformers 15A and 15B are provided in the second element insulating layer 102. More specifically, the second coils 22 of the transformers 15A and 15B are provided in the insulator 102R. As shown in FIG. 5, the second coils 22 of the transformers 15A and 15B are arranged at the same position in the X direction and spaced apart from each other in the Y direction. The second coil 22 of the transformer 15A is disposed closer to the second element side surface 102E than the second coil 22 of the transformer 15B. Moreover, these second coils 22 are disposed closer to the second element side surface 102C than the center of the second element insulating layer 102 in the X direction. More specifically, the center of the second coil 22 in the X direction is located closer to the second element side surface 102C than the center of the second element insulating layer 102 in the X direction.

[0095] 8, the second coil 22 is embedded in the second element insulating layer 102 at a position spaced apart from the second element front surface 102A of the second element insulating layer 102 in the Z direction. The second coil 22 is also disposed at a position spaced apart from the second element back surface 102B in the Z direction. In other words, the second coil 22 is not exposed from the second element insulating layer 102. The second coils 22 of the transformers 15A and 15B are disposed at the same positions as each other in the Z direction.

[0096] As shown in FIG. 5, the second coil 22 is formed in a spiral shape in a plan view. The number of turns of the second coil 22 can be arbitrarily changed according to the electrical characteristics of the transformer chip 50. The second coil 22 is made of a material including one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W. In one example, the second coil 22 is made of a material including Cu. That is, the second coil 22 may be made of the same material as the first coil 21. The material constituting the second coil 22 can be arbitrarily changed. In one example, the second coil 22 may be made of a material different from that of the first coil 21.

[0097] The second coil 22 is electrically connected to an inner connection portion 22A and an outer connection portion 22B. The inner connection portion 22A is disposed inward from the winding portion of the second coil 22 in a plan view. The inner connection portion 22A is connected to a wiring layer drawn out in the X direction from an inner end of the winding portion of the second coil 22. The outer connection portion 22B is disposed outward from the winding portion of the second coil 22 in a plan view. Both the inner connection portion 22A and the outer connection portion 22B may be formed of, for example, the same material as the second coil 22.

[0098] The second unit 100 includes a plurality of second pads 55. The second pads 55 are disposed closer to the second element side surface 102D than the second coil 22 in the X direction. Three second pads 55 are provided corresponding to the first pads 54. Hereinafter, for convenience, the three second pads 55 are referred to as "second pads 55A, 55B, 55C."

[0099] More specifically, the second pad 55A is provided in correspondence with the inner connection portion 22A connected to the second coil 22 of the transformer 15A. The second pad 55A is electrically connected to the inner connection portion 22A connected to the second coil 22 of the transformer 15A. The second pad 55C is provided in correspondence with the inner connection portion 22A connected to the second coil 22 of the transformer 15B. The second pad 55C is electrically connected to the inner connection portion 22A connected to the second coil 22 of the transformer 15B. The second pad 55B is provided in correspondence with the outer connection portion 22B connected to both the second coil 22 of the transformer 15A and the second coil 22 of the transformer 15B. The second pad 55B is electrically connected to the outer connection portion 22B. In one example, the outer connection portion 22B is a common connection portion of the second coil 22 of the transformer 15A and the second coil 22 of the transformer 15B. In other words, the second pad 55B configures a common pad for the second coil 22 of the transformer 15A and the second coil 22 of the transformer 15B.

[0100] The second pad 55A is disposed at a position overlapping the second coil 22 of the transformer 15A when viewed from the X direction. The second pad 55B is disposed between the first coil 21 of the transformer 15A and the first coil 21 of the transformer 15B in the Y direction. The second pad 55C is disposed at a position overlapping the second coil 22 of the transformer 15B when viewed from the X direction. The positions of the second pads 55A to 55C in the Y direction can be changed arbitrarily. The number of the second pads 55 is not limited to the example shown in FIG. 5 and can be changed arbitrarily. In one example, two of each of the second pads 55A to 55C may be provided.

[0101] 8, the second unit 100 includes a first connection portion 103 that electrically connects the inner connection portion 22A connected to the second coil 22 of the transformer 15A to the second pad 55A. The first connection portion 103 is embedded in the second semiconductor substrate 101 and the second element insulating layer 102. In other words, the second coil 22 and the second pad 55A are electrically connected to each other within the second semiconductor substrate 101 and the second element insulating layer 102.

[0102] The first connection portion 103 includes a first connection body 103A, a first connection wiring 103B, and a second connection body 103C. The first connection body 103A penetrates the second semiconductor substrate 101 and is surrounded by an annular insulating layer 102JA in a plan view. The first connection body 103A is electrically insulated from other parts of the second semiconductor substrate 101 by the insulating layer 102JA. In one example, the first connection body 103A is formed of the same material as the second semiconductor substrate 101. In other words, the first connection body 103A is formed from the second semiconductor substrate 101. It can be said that the second semiconductor substrate 101 includes the first connection body 103A. It can be said that the first connection body 103A is separated from other parts of the second semiconductor substrate 101 by the annular insulating layer 102JA that penetrates the second semiconductor substrate 101 and surrounds the first connection body 103A in a plan view. The second pad 55A is disposed on the surface of the first connection body 103A. The second pad 55A is electrically connected to the first connection body 103A. The insulating layer 102JA may be formed integrally with the substrate-side insulating layer 102J. It can be said that the substrate-side insulating layer 102J includes a ring-shaped insulating layer 102JA. Here, the first connection body 103A is an example of a "connection body".

[0103] Moreover, the first connection body 103A is electrically connected to the first connection wiring 103B by at least one via 103D. In the example shown in FIG. 8, a plurality of vias 103D are provided between the first connection wiring 103B and the first connection body 103A in the Z direction. The plurality of vias 103D penetrate the substrate-side insulating layer 102J in the Z direction. Note that the number of vias 103D may be one. Moreover, the annular insulating layer 102JA is formed integrally with the substrate-side insulating layer 102J. In this case, it can be said that the substrate-side insulating layer 102J includes the annular insulating layer 102JA.

[0104] The first connection wiring 103B electrically connects the first connection body 103A and the second connection body 103C. The first connection wiring 103B includes an end 103BA overlapping the first connection body 103A in a plan view and an end 103BB overlapping the inner connection portion 22A of the second coil 22 in a plan view. In one example, the end 103BA of the first connection wiring 103B may have the same shape as the first connection body 103A in a plan view. In one example, the end 103BA of the first connection wiring 103B may be larger than the first connection body 103A in a plan view. In one example, the end 103BB of the first connection wiring 103B may be the same size as the inner connection portion 22A of the second coil 22 in a plan view. The first connection wiring 103B is disposed closer to the second element back surface 102B than the second coil 22 in the Z direction. The first connection wiring 103B is formed as a wiring layer extending in the X-direction. Here, the first connection wiring 103B is an example of a "second connection wiring".

[0105] The second connection body 103C electrically connects the inner connection portion 22A of the second coil 22 and the end portion 103BB of the first connection wiring 103B. The second connection body 103C is disposed at a position overlapping both the inner connection portion 22A connected to the second coil 22 and the first connection wiring 103B in a plan view. The second connection body 103C is disposed closer to the second element rear surface 102B than the second coil 22 in the Z direction. In the example shown in FIG. 8, the second connection body 103C is a via extending in the Z direction from the inner connection portion 22A connected to the second coil 22 when viewed from the Y direction.

[0106] As shown in FIG. 5, the second unit 100 includes a second connection portion 104 that electrically connects an outer connection portion 22B connected to both the second coil 22 of the transformer 15A and the second coil 22 of the transformer 15B to a second pad 55B.

[0107] The second connection portion 104 is provided so as to overlap both the outer connection portion 22B and the second pad 55B in a plan view. In one example, the configuration and arrangement in the thickness direction (Z direction) of the second connection portion 104 are the same as those of the first connection portion 103, although not shown.

[0108] The second unit 100 includes a first connection portion 105 that electrically connects the inner connection portion 22A of the second coil 22 of the transformer 15B and the second pad 55C. The first connection portion 105 is provided so as to overlap both the inner connection portion 22A of the second coil 22 of the transformer 15B and the second pad 55C in a plan view. In one example, the configuration of the first connection portion 105 and its arrangement in the thickness direction (Z direction) are the same as the configuration of the first connection portion 103.

[0109] As shown in FIG. 8, in this embodiment, the second element insulating layer 102 is composed of first to fourth insulating layers 1021 to 1024 that form an insulator 102R, and a passivation layer 102G.

[0110] The first insulating layer 1021 is in contact with the substrate-side insulating layer 102J. That is, the first insulating layer 1021 constitutes the insulating film of the lowest layer of the insulator 102R. The first insulating layer 1021 is provided with a first connection wiring 103B electrically connected to the second coil 22. The second insulating layer 1022 is laminated on the first insulating layer 1021. The second insulating layer 1022 is provided with a second connection body 103C electrically connected to the inner connection portion 22A. The third insulating layer 1023 is laminated on the second insulating layer 1022. The inner connection portion 22A and the second coil 22 are provided on the third insulating layer 1023. Therefore, the second insulating layer 1022 covers the second coil 22 from the second semiconductor substrate 101 side. The fourth insulating layer 1024 is laminated on the third insulating layer 1023. The fourth insulating layer 1024 covers the second coil 22. The fourth insulating layer 1024 constitutes the uppermost insulating film of the insulator 102R.

[0111] In this manner, the second coil 22 can be said to be embedded in the second to fourth insulating layers 1022 to 1024. The first connection portion 103 can be said to be embedded in the first to third insulating layers 1021 to 1023. The passivation layer 102G is laminated on the fourth insulating layer 1024. The passivation layer 102G is formed, for example, over the entire surface of the fourth insulating layer 1024. Each of the first to fourth insulating layers 1021 to 1024 is composed of a first insulating film 92P and a second insulating film 92Q laminated on the first insulating film 92P.

[0112] (Joint structure between the first and second units) The joining structure between the first unit 90 and the second unit 100 will be described with reference to FIGS.

[0113] As shown in Fig. 4, the transformer chip 50 includes an insulating glass layer 110 that is interposed between a first unit 90 and a second unit 100 disposed on the first unit 90 and that is in contact with both the first unit 90 and the second unit 100. The insulating glass layer 110 bonds the first unit 90 and the second unit 100 together. Hereinafter, the state in which the first unit 90 and the second unit 100 are bonded together by the insulating glass layer 110 will be referred to as a "unit bonded state." The insulating glass layer 110 bonds both the first element insulating layer 92 and the second element insulating layer 102 together.

[0114] An insulating glass layer 110 is formed in a region of the first element surface 92A of the first element insulating layer 92 where the second unit 100 is arranged. The insulating glass layer 110 is formed so as to entirely overlap the second unit 100 in a planar view. In one example, the insulating glass layer 110 is slightly smaller than the second unit 100 in a planar view. The size of the insulating glass layer 110 in a planar view can be changed arbitrarily. It is sufficient that the insulating glass layer 110 in a planar view is formed so as to entirely cover the portion where the first coil 21 and the second coil 22 face each other and to expose the first pad 54.

[0115] In this embodiment, the insulating glass layer 110 is formed of a paste material containing glass powder. The insulating glass layer 110 is formed by screen printing on the first element insulating layer 92 or the second element insulating layer 102. In one example, the difference in linear expansion coefficient between the insulating glass layer 110 and the first element insulating layer 92 and the second element insulating layer 102 is smaller than the difference in linear expansion coefficient between the insulating glass layer 110 and the second semiconductor substrate 101. In this embodiment, the linear expansion coefficient of the first element insulating layer 92 and the linear expansion coefficient of the second element insulating layer 102 are equal to each other. In one example, the linear expansion coefficient of the second semiconductor substrate 101 is larger than the linear expansion coefficient of the first element insulating layer 92 and the linear expansion coefficient of the second element insulating layer 102.

[0116] 3 and 4, the second unit 100 is smaller than the first unit 90 in a plan view. More specifically, the dimension of the second unit 100 in the X direction is smaller than the dimension of the first unit 90 in the X direction in a plan view. On the other hand, the dimension of the second unit 100 in the Y direction is equal to the dimension of the first unit 90 in the Y direction.

[0117] The second unit 100 is disposed such that the second element side surface 102D is at the same position in the X direction as the first element side surface 92D of the first unit 90, and the second element side surface 102E is at the same position in the X direction as the first element side surface 92E of the first unit 90. The second element side surface 102F is formed at the same position as the first element side surface 92F. Meanwhile, the second element side surface 102C is located closer to the first element side surface 92D than the first element side surface 92C. The position of the second unit 100 relative to the first unit 90 in a plan view can be arbitrarily changed.

[0118] As shown in FIG. 4, in the unit bonding state, the second unit 100 is placed on the insulating glass layer 110 with the second element insulating layer 102 positioned closer to the first unit 90 in the Z direction. Therefore, the second element insulating layer 102 is in contact with the insulating glass layer 110. That is, the insulating glass layer 110 bonds the second element insulating layer 102 and the first element insulating layer 92 together. In this manner, the insulating glass layer 110 is interposed between the second element insulating layer 102 and the first element insulating layer 92 in the Z direction. Therefore, the second element insulating layer 102 is disposed at a position spaced apart from the first element insulating layer 92 in the Z direction. That is, the second element insulating layer 102 is not directly bonded to the first element insulating layer 92.

[0119] Since insulating glass layer 110 is slightly smaller than second unit 100 in plan view, in the unit-bonded state, a recess that is recessed in a direction perpendicular to the Z direction is formed by second element side surfaces 102C-102F of second element insulating layer 102 of second unit 100, first element insulating layer 92 of first unit 90, and insulating glass layer 110. Although not shown, sealing resin 80 (see FIG. 2) fills the recess.

[0120] 3, in a plan view, the first pad 54 is disposed closer to the first element side surface 92C than the second unit 100. More specifically, in a plan view, the first pad 54 is provided at a position different from the second unit 100. In other words, the first pad 54 is formed in an exposed region 51A of the first element surface 92A that is exposed from the insulating glass layer 110 and the second unit 100.

[0121] As shown in FIG. 8, in the unit bonding state, the first coil 21 and the second coil 22 are arranged to face each other in the Z direction. In this embodiment, the ratio of the thickness DG of the insulating glass layer 110 to the thickness DA1 between the first coil 21 and the first element surface 92A included in the first element insulating layer 92 is equal to or greater than 1 and less than 4. Also, the ratio of the thickness DG of the insulating glass layer 110 to the thickness DA2 between the second coil 22 and the second element surface 102A included in the second element insulating layer 102 may be equal to or greater than 1 and less than 4. In one example, the ratio of the thickness DG of the insulating glass layer 110 to the thickness DA2 between the second coil 22 and the second element surface 102A included in the second element insulating layer 102 is equal to the ratio of the thickness DG of the insulating glass layer 110 to the thickness DA1 between the first element surface 92A. In the example shown in FIG. 8, the ratio of the thickness DG of the insulating glass layer 110 to the thickness DA1 between the first coil 21 and the first element surface 92A is greater than 1 and less than 2. Furthermore, the ratio of the thickness DG of the insulating glass layer 110 to the thickness DA2 between the second coil 22 and the second element surface 102A is greater than 1 and less than 2.

[0122] In one example, the thickness DA1 between the first coil 21 included in the first element insulating layer 92 and the first element surface 92A is about 5 μm. In one example, the thickness DG of the insulating glass layer 110 is 5 μm or more and 20 μm or less. The values ​​of the thickness DA1 between the first coil 21 included in the first element insulating layer 92 and the first element surface 92A and the thickness DG of the insulating glass layer 110 are not limited to these values. In addition, the distance between the first coil 21 and the second coil 22 in the Z direction may be changed by changing the thickness DG of the insulating glass layer 110. That is, in the transformer chip 50, the withstand voltage of the transformer chip 50 can be adjusted by adjusting the thickness DG of the insulating glass layer 110.

[0123] Also, although different from the example shown in FIG. 8, the thickness DG of the insulating glass layer 110 may be greater than or equal to the sum (DA1+DA2) of the thickness DA1 between the first coil 21 and the first element surface 92A and the thickness DA2 between the second coil 22 and the second element surface 102A.

[0124] [Transtip manufacturing method] An example of a method for manufacturing the transformer chip 50 will be described with reference to FIGS. Fig. 9 shows a schematic cross-sectional structure of a portion of the first wafer 800. The cross-sectional position of Fig. 9 is the same as the cross-sectional position of Fig. 4 in plan view.

[0125] As shown in FIG. 9, the method for manufacturing the transformer chip 50 includes preparing a first wafer 800. More specifically, first, a semiconductor wafer 801 is prepared, on which a plurality of first semiconductor substrates 91 are provided, each having a first substrate surface 91A and a first substrate back surface 91B opposite to the first substrate surface 91A. For example, a Si wafer can be used for this semiconductor wafer 801. Next, an element insulating layer 802 corresponding to a plurality of first element insulating layers 92 is formed on the surface of the semiconductor wafer 801 corresponding to the first substrate surface 91A. In the process of forming the element insulating layer 802, a first coil 21, first connecting portions 93, 95, and a second connecting portion 94 corresponding to each first element insulating layer 92 are formed. The first coil 21, the first connecting portions 93, 95, and the second connecting portion 94 can be formed by plating or sputtering. As a result, the first coil 21, the first connecting portions 93, 95, and the second connecting portion 94 are provided on each first element insulating layer 92. Next, the first pad 54 electrically connected to the first coil 21 via the first connecting portion 93, 95 or the second connecting portion 94 is provided so as to be exposed from the first element insulating layer 92 in the thickness direction (Z direction) of the first element insulating layer 92. The first pad 54 can be formed by plating or sputtering. Through the above steps, the first wafer 800 is manufactured. Therefore, the first wafer 800 includes a plurality of first units 90. Note that FIG. 9 shows a schematic cross-sectional structure of a portion of the first wafer 800 corresponding to one of the first units 90.

[0126] Figures 10 and 11 show a schematic cross-sectional structure of a portion of the second wafer 900. The cross-sectional positions of Figures 10 and 11 are the same as the cross-sectional position of Figure 9 in plan view. As shown in FIGS. 10 and 11, the method for manufacturing the transformer chip 50 includes preparing a second wafer 900.

[0127] As shown in Fig. 10, a semiconductor wafer 901 is prepared, which includes a plurality of second semiconductor substrates 101 each having a second substrate front surface 101A and a second substrate back surface 101B opposite to the second substrate front surface 101A. For example, a Si wafer can be used for this semiconductor wafer 901. For the semiconductor wafer 901, a semiconductor wafer having a lower electrical resistance than the semiconductor wafer 801 shown in Fig. 9 is used. In one example, the impurity concentration of the semiconductor wafer 901 is higher than the impurity concentration of the semiconductor wafer 801.

[0128] Next, in each second semiconductor substrate 101 of the semiconductor wafer 901, a trench 101C is formed that is recessed from the wafer surface corresponding to the second substrate surface 101A toward the wafer back surface corresponding to the second substrate back surface 101B. Each trench 101C can be formed, for example, by etching the semiconductor wafer 901. Each trench 101C is formed in an annular shape in a plan view. Next, an insulating layer 903 is formed so as to fill the entire trench 101C and cover the entire second substrate surface 101A. The insulating layer 903 is an insulating layer that corresponds to the multiple substrate-side insulating layers 102J. The insulating layer 903 is formed, for example, by thermally oxidizing the semiconductor wafer 901.

[0129] 11, element insulating layers 902 corresponding to the plurality of second element insulating layers 102 are formed on an insulating layer 903 formed on the wafer surface (second substrate surface 101A). In the process of forming the element insulating layer 902, second coils 22, first connecting portions 103, 105, and second connecting portions 104 corresponding to the respective second element insulating layers 102 are formed. The second coils 22, first connecting portions 103, 105, and second connecting portions 104 can be formed by plating or sputtering. As a result, the second coils 22, first connecting portions 103, 105, and second connecting portions 104 are provided on the respective second element insulating layers 102.

[0130] Next, a plurality of grooves 930 are formed by cutting through the element insulating layer 902 in its thickness direction and by cutting a part of the second semiconductor substrate 101 in the thickness direction (Z direction). The grooves 930 are provided in each of the second element insulating layers 102 of the element insulating layer 902. It can also be said that the grooves 930 are provided in each of the second units 100 of the second wafer 900. Each groove 930 is formed as a groove extending in the Y direction. In one example, each groove 930 may penetrate the second wafer 900 in the Y direction. In one example, the groove 930 is provided in a rectangular shape when viewed from the Y direction. The second wafer 900 is manufactured by the above steps. Therefore, the second wafer 900 includes a plurality of second units 100. Note that FIG. 10 and FIG. 11 show a schematic cross-sectional structure of a portion of the second wafer 900 corresponding to one of the second units 100.

[0131] Fig. 12 shows a schematic perspective structure for explaining the process of bonding the first wafer 800 and the second wafer 900. Fig. 13 shows a schematic planar structure for explaining the process of bonding the first wafer 800 and the second wafer 900. Fig. 14 shows a schematic cross-sectional structure of a part of the state in which the first wafer 800 and the second wafer 900 are bonded. Note that Fig. 13 shows a rectangular area corresponding to one of the first unit 90 and the second unit 100 of the first wafer 800 and the second wafer 900 shown in Fig. 12.

[0132] As shown in FIG. 12, the manufacturing method of the transformer chip 50 includes forming a plurality of intermediate insulating layers 110X on the element insulating layer 802 (see FIG. 13) of the first wafer 800. In this embodiment, each intermediate insulating layer 110X is formed by screen printing on each first element insulating layer 92 of the element insulating layer 802. The plurality of intermediate insulating layers 110X are arranged spaced apart from each other on the element insulating layer 802. Each intermediate insulating layer 110X is an insulating bonding material that bonds the first wafer 800 and the second wafer 900. In one example, the intermediate insulating layer 110X is a glass paste containing glass powder.

[0133] The material of the intermediate insulating layer 110X is not limited to glass paste, and may be other insulating materials including, for example, resin. In one example, the intermediate insulating layer 110X may include at least one of epoxy resin and bismaleimide resin instead of a paste material containing glass powder. The intermediate insulating layer 110X may be formed on each second element insulating layer of the second wafer 900.

[0134] 13, the intermediate insulating layer 110X is provided so as to cover, for example, the entire first coil 21 of the transformers 15A, 15B. In one example, the intermediate insulating layer 110X is provided on the first element insulating layer 92 at a position facing a portion of the second wafer 900 corresponding to the second unit 100. In one example, the area of ​​the intermediate insulating layer 110X in a plan view is smaller than the area of ​​the second unit 100 in a plan view.

[0135] 12 and 14, the manufacturing method of the transformer chip 50 includes bonding the first wafer 800 and the second wafer 900 together via the intermediate insulating layer 110X. In one example, the second wafer 900 is pressed against the intermediate insulating layer 110X arranged on the first wafer 800, and the intermediate insulating layer 110X is cured by heating while applying pressure. The second wafer 900 is bonded to the first wafer 800 via the intermediate insulating layer 110X by the curing of the intermediate insulating layer 110X.

[0136] 12, in a state where the first wafer 800 and the second wafer 900 are bonded together, intermediate insulating layers 110X are interposed between the first element insulating layers 92 and the second element insulating layers 102. The first wafer 800 and the second wafer 900 are bonded together by the intermediate insulating layers 110X. As shown in FIG 14, in a state where the first wafer 800 and the second wafer 900 are bonded together (hereinafter, the "wafer bonded state"), the first coil 21 and the second coil 22 are disposed opposite each other, and the groove 930 and the first pad 54 are disposed opposite each other.

[0137] 15, the manufacturing method of the transformer chip 50 includes grinding the second wafer 900 in a wafer-bonded state so that the thickness of each second semiconductor substrate 101 of the second wafer 900 is reduced. At this time, by grinding down to the bottom wall of each trench 101C, a plurality of substrate-side insulating layers 102J are formed from the insulating layer 903. In addition, a plurality of first connectors 103A are formed which penetrate each second semiconductor substrate 101 and are surrounded by insulating layers 102JA of the substrate-side insulating layers 102J.

[0138] Next, the manufacturing method of the transformer chip 50 includes forming the second pads 55 in contact with each of the first connecting bodies 103A. In this step, a second pad 55 is provided on each first connector 103A. Each second pad 55 is electrically connected to the second coil 22 via the first connector 103. The second pad 55 is provided so as to be exposed from the element insulating layer 802 in the thickness direction of the element insulating layer 802 (second element insulating layer 102). In one example, each second pad 55 is formed inside each insulating layer 102JA formed in a ring shape in a plan view.

[0139] Next, as shown in FIG. 16 and FIG. 17, in the wafer bonded state, both the first wafer 800 and the second wafer 900 are cut to be divided into individual pieces. In one example, both the first wafer 800 and the second wafer 900 in the wafer bonded state are cut along the cutting line CL by a dicing process. More specifically, the first wafer 800 and the second wafer 900 are placed on a dicing tape 910. Then, both the first wafer 800 and the second wafer 900 in the wafer bonded state are cut by a dicing blade to be divided into individual pieces. Through the above steps, a plurality of first units 90 are manufactured.

[0140] 15 is the same size as the first unit 90 in a plan view. That is, the first pad 54 of the first unit 90 is covered by the second unit 100. Thus, the second unit 100 includes an isolation region 940 in which the groove 930 is provided. The inner surface constituting the groove 930 includes the second element side surface 102C of the second element insulating layer 102. Therefore, the isolation region 940 is a region of the second unit 100 that is farther from the second coil 22 in the X direction than the second element side surface 102C.

[0141] As shown in FIGS. 15 to 17, the singulation in the manufacturing method of the transformer chip 50 includes removing a separation region 940 as a portion of the second wafer 900 (second unit 100) where the groove 930 is provided. In this step, the second semiconductor substrate 101 constituting the bottom surface of the groove 930 is cut in the Z direction by, for example, a dicing process. In the example shown in FIG. 17, a part of the separation region 940 overlapping with the groove 930 remains in the second semiconductor substrate 101. As a result, a protrusion 101D is formed in the second semiconductor substrate 101. Through the above steps, a plurality of transformer chips 50 are manufactured.

[0142] [Operation of the embodiment] The operation of this embodiment will now be described. In some cases, the transformer chip is required to have improved dielectric strength. As a countermeasure, it is possible to increase the distance between the first coil 21 and the second coil 22. In a configuration in which the first coil 21 and the second coil 22 are arranged opposite each other in the Z direction in one element insulating layer formed on one semiconductor substrate, it is necessary to increase the thickness of the element insulating layer in order to increase the distance between the first coil 21 and the second coil 22. However, if the thickness of the element insulating layer is increased, the semiconductor substrate is likely to warp during the manufacturing process of the transformer chip. For this reason, there is a limit to how thick the element insulating layer can be, and there is room for improvement.

[0143] In this respect, the transformer chip 50 of this embodiment includes a first unit 90 including a first element insulating layer 92 formed on a first semiconductor substrate 91 and a first coil 21 provided in the first element insulating layer 92, and a second unit 100 including a second element insulating layer 102 formed on a second semiconductor substrate 101 and a second coil 22 provided in the second element insulating layer 102. As a result, the first element insulating layer 92 formed on the first semiconductor substrate 91 and the second element insulating layer 102 formed on the second semiconductor substrate 101 are interposed between the first coil 21 and the second coil 22. Therefore, the thickness of each of the first element insulating layer 92 and the second element insulating layer 102 can be made thinner than the thickness of the element insulating layer formed on one semiconductor substrate in which the first coil 21 and the second coil 22 are embedded. For this reason, the first semiconductor substrate 91 and the second semiconductor substrate 101 are less likely to warp during the manufacturing process of the transformer chip 50.

[0144] In addition, an insulating glass layer 110 is interposed between the first element insulating layer 92 and the second element insulating layer 102. That is, the first element insulating layer 92, the second element insulating layer 102, and the insulating glass layer 110 are interposed between the first coil 21 and the second coil 22. Therefore, the distance between the first coil 21 and the second coil 22 can be made large. In addition, the thickness of the insulating glass layer 110 can be easily adjusted by changing the bonding conditions such as the viscosity of the glass paste and the pressing force during bonding. In this way, the distance between the first coil 21 and the second coil 22 can be adjusted by changing the thickness DG of the insulating glass layer 110. Therefore, it is possible to easily provide a transformer chip 50 having a different dielectric strength without changing the configuration of the first unit 90 and the second unit 100.

[0145] [Effects of the embodiment] According to the signal transmission device 10 of this embodiment, the following effects can be obtained. (1) The transformer chip 50 includes a first unit 90 including a first semiconductor substrate 91 having a first substrate surface 91A and a first substrate back surface 91B opposite to the first substrate surface 91A, a first element insulating layer 92 formed on the first substrate surface 91A, and a first coil 21 provided in the first element insulating layer 92, a second semiconductor substrate 101 having a second substrate surface 101A and a second substrate back surface 101B opposite to the second substrate surface 101A, a second element insulating layer 102 formed on the second substrate surface 101A, and a first coil 21 provided in the second element insulating layer 102. The unit includes a first unit 90 and a second unit 100 arranged on the first unit 90, and an insulating glass layer 110 interposed between the first unit 90 and the second unit 100 arranged on the first unit 90. In a unit bonded state in which the first unit 90 and the second unit 100 are bonded by the insulating glass layer 110, the insulating glass layer 110 bonds both the first element insulating layer 92 and the second element insulating layer 102 while being in contact with both, and the first coil 21 and the second coil 22 are arranged opposite each other.

[0146] According to this configuration, by interposing the insulating glass layer 110 between the first unit 90 and the second unit 100, it is possible to ensure a distance in the Z direction between the first coil 21 and the second coil 22 to ensure a dielectric strength voltage required for the transformer chip 50, without excessively thickening both the first element insulating layer 92 and the second element insulating layer 102. Therefore, the insulating glass layer 110 can improve the dielectric strength voltage of the transformer chip 50.

[0147] In addition, the distance between the first coil 21 and the second coil 22 in the Z direction can be adjusted by changing the thickness of the insulating glass layer 110 provided between the first element insulating layer 92 and the second element insulating layer 102, making it possible to easily manufacture multiple types of transformer chips 50 with different dielectric strength voltages.

[0148] (2) The difference in linear expansion coefficient between the insulating glass layer 110 and the first element insulating layer 92 and the second element insulating layer 102 is smaller than the difference in linear expansion coefficient between the insulating glass layer 110 and the second semiconductor substrate 101 .

[0149] This configuration reduces thermal stresses that occur in the first element insulating layer 92 and the second element insulating layer 102 due to differences in linear expansion coefficients between the insulating glass layer 110 and the first element insulating layer 92 and the second element insulating layer 102. Therefore, warping of the first element insulating layer 92 and the second element insulating layer 102 can be reduced.

[0150] (3) A second pad 55 electrically connected to the second coil 22 is provided on the second substrate back surface 101B. The electrical resistivity of the second semiconductor substrate 101 is smaller than the electrical resistivity of the first semiconductor substrate 91. The second semiconductor substrate 101 includes a first connector 103A electrically connected to the second pad 55, and the first connector 103A is separated from other portions of the second semiconductor substrate 101 by a ring-shaped insulating layer 102JA that penetrates the second semiconductor substrate 101 and surrounds the first connector 103A when viewed in the thickness direction of the second semiconductor substrate 101.

[0151] According to this configuration, because the electrical resistivity of the second semiconductor substrate 101 is low, it is possible to form a part of the electrical conduction path from the second coil 22 to the second pad 55 by isolating the first connector 103A from other parts of the second semiconductor substrate 101 by the insulating layer 102JA. Therefore, it is possible to form the electrical conduction path from the second coil 22 to the second pad 55 inside the second semiconductor substrate 101 without going through a process of embedding an electrically conductive member inside the second semiconductor substrate 101.

[0152] (4) The first unit 90 includes a first pad 54 that is exposed from the first element insulating layer 92 in the Z direction. The first pad 54 is disposed at a different position from the second unit 100 in a plan view.

[0153] According to this configuration, the first pads 54 are exposed in the Z direction on the first chip surface 51, and therefore the second units 100 are not present between the first pads 54 and the first chip 30. This makes it possible to prevent the second units 100 from interfering with the connection between the first pads 54 and the first chip 30.

[0154] (5) The first unit 90 includes a first pad 54 exposed from the first element insulating layer 92 in the Z direction. The first pad 54 and the second pad 55 are arranged separately on both sides in the X direction of the first coil 21 (second coil 22) in a plan view.

[0155] According to this configuration, the first pad 54 and the second pad 55 are arranged separately on both sides in the X direction, so that the first pad 54 is arranged closer to the first chip 30 than the second pad 55, and the second pad 55 is arranged closer to the second chip 40 than the first pad 54. This makes it possible to shorten the length of the wire W2 connecting the first pad 54 and the first chip 30 and the wire W3 connecting the second pad 55 and the second chip 40.

[0156] (6) A method for manufacturing the transformer chip 50 includes preparing a first wafer 800 including a first semiconductor substrate 91 having a first substrate surface 91A and a first substrate back surface 91B opposite to the first substrate surface 91A, a first element insulating layer 92 formed on the first substrate surface 91A, and a first coil 21 provided in the first element insulating layer 92; forming an intermediate insulating layer 110X on the first element insulating layer 92 or the second element insulating layer 102; bonding the first wafer 800 and the second wafer 900 together such that the intermediate insulating layer 110X is interposed between the first element insulating layer 92 and the second element insulating layer 102 and the first coil 21 and the second coil 22 are arranged opposite each other; and cutting both the first wafer 800 and the second wafer 900 together to separate them into individual pieces.

[0157] According to this configuration, by interposing the intermediate insulating layer 110X between the first wafer 800 and the second wafer 900, it is possible to ensure a distance in the Z direction between the first coil 21 and the second coil 22 to ensure a dielectric strength voltage required for the transformer chip 50, without excessively thickening both the first element insulating layer 92 and the second element insulating layer 102. Therefore, the intermediate insulating layer 110X can improve the dielectric strength voltage of the transformer chip 50.

[0158] In addition, after bonding the first wafer 800 and the second wafer 900, the first wafer 800 and the second wafer 900 are cut to separate them. Therefore, compared to a configuration in which the first wafer 800 and the second wafer 900 are separated into individual wafers and then bonded together, the process of bonding the separated wafers together can be eliminated, and the manufacturing process can be simplified.

[0159] (7) Preparing the first wafer 800 includes providing a first pad 54 electrically connected to the first coil 21 so as to be exposed from the first element insulating layer 92 in the Z direction. Preparing the second wafer 900 includes forming a groove 930 by penetrating the second element insulating layer 102 in its thickness direction and cutting a part of the second semiconductor substrate 101 in the thickness direction. The first wafer 800 and the second wafer 900 are bonded together, so that the groove 930 is disposed opposite the first pad 54. Singulating includes removing the part of the second wafer 900 where the groove 930 is provided.

[0160] According to this configuration, the first pad 54 electrically connected to the first coil 21 is provided so as to be exposed from the first element insulating layer 92 in the Z direction. Therefore, the first coil 21 can be connected to a circuit provided outside the transformer chip 50 via the first pad 54.

[0161] In addition, by bonding the first wafer 800 and the second wafer 900 together, the portion of the second wafer 900 in which the groove 930 is provided is removed with the groove 930 and the first pad 54 arranged opposite each other. Therefore, by removing the portion of the second wafer 900 arranged opposite the first pad 54, the first pad 54 can be exposed from the first element insulating layer 92 in the Z direction.

[0162] (8) Preparing the second wafer 900 includes forming a trench 101C recessed from the second substrate front surface 101A of the second semiconductor substrate 101 toward the second substrate back surface 101B, and forming a substrate-side insulating layer 102J on the second substrate front surface 101A to form an insulating layer 102JA embedded in the trench 101C. The trench 101C is formed in a ring shape in a plan view. Preparing the second wafer 900 further includes grinding the second semiconductor substrate 101 so that the thickness of the second semiconductor substrate 101 becomes thin in a state in which the first wafer 800 and the second wafer 900 are bonded together. In grinding the second semiconductor substrate 101, a first connection body 103A that penetrates the second semiconductor substrate 101 and is surrounded by the insulating layer 102JA is formed by grinding the second semiconductor substrate 101 to the bottom wall of the trench 101C. Preparing the second wafer 900 further includes forming second pads 55 on the second substrate backside 101B, the second pads 55 being electrically connected to the first connectors 103A.

[0163] According to this configuration, by forming the insulating layer 102JA that is annular in plan view and penetrates the second semiconductor substrate 101, the first connector 103A surrounded by the insulating layer 102JA can be separated from other regions of the second semiconductor substrate 101. Furthermore, by forming the second pad 55 that contacts the first connector 103A on the second substrate back surface 101B, it is possible to provide a conductive path that connects the second substrate front surface 101A and the second pad 55 exposed from the second substrate back surface 101B. In addition, by grinding the second semiconductor substrate 101 so as to reduce its thickness, the height of the transformer chip 50 can be reduced.

[0164] (9) The intermediate insulating layer 110X is formed on the first element insulating layer 92 or the second element insulating layer 102 by screen printing. With this configuration, the shape of intermediate insulating layer 110X in a plan view can be set arbitrarily by using a mask used during screen printing. This makes it possible to provide intermediate insulating layer 110X only in the portion where first unit 90 and second unit 100 are bonded on first element insulating layer 92 of first wafer 800 or second element insulating layer 102 of second wafer 900.

[0165] <Example of change> The above embodiment can be modified, for example, as follows. The above embodiment and the following modified examples can be combined with each other as long as no technical contradiction occurs. In the following modified examples, the same reference numerals as in the above embodiment are used for the parts common to the above embodiment, and the description thereof will be omitted.

[0166] (First modified example) A first modified example of the signal transmission device 10 will be described with reference to Fig. 18 and Fig. 19. Fig. 18 shows a schematic circuit configuration of the signal transmission device 10 of the first modified example. Fig. 19 shows a schematic cross-sectional structure of a capacitor chip 130 in the signal transmission device 10 of the first modified example.

[0167] As shown in FIG. 18, a signal transmission device 10 of the first modified example includes capacitors 120A and 120B instead of the transformers 15A and 15B. Capacitor 120A transmits a set signal from primary circuit 13 to secondary circuit 14, while electrically insulating primary circuit 13 from secondary circuit 14. Capacitor 120A has first electrode plate 121 and second electrode plate 122 that constitute electrodes of capacitor 120A. First electrode plate 121 of capacitor 120A is electrically connected to primary signal line 16A, and second electrode plate 122 is electrically connected to secondary signal line 17A.

[0168] Capacitor 120B transmits a reset signal from primary circuit 13 to secondary circuit 14, while electrically insulating primary circuit 13 from secondary circuit 14. Capacitor 120B has a first electrode plate 121 and a second electrode plate 122. First electrode plate 121 of capacitor 120B is electrically connected to primary signal line 16B, and second electrode plate 122 is electrically connected to secondary signal line 17B. Here, in the first modified example, first electrode plate 121 of capacitors 120A and 120B is an example of a "first insulating element", and second electrode plate 122 of capacitors 120A and 120B is an example of a "second insulating element".

[0169] The withstand voltage of the signal transmission device 10 is, for example, 2500 Vrms or more and 7500 Vrms or less. The withstand voltage of the signal transmission device 10 of the first modified example is about 5000 Vrms, similar to the above embodiment. However, the specific value of the withstand voltage of the signal transmission device 10 is not limited to this and can be changed arbitrarily.

[0170] The signal transmission device 10 of the first modified example includes a capacitor chip 130 instead of the transformer chip 50 (see FIG. 4). Below, the configuration of the capacitor 120A in the capacitor chip 130 will be described with reference to FIG. 19. Note that since the capacitor 120B has the same configuration as the capacitor 120A, a detailed description thereof will be omitted. Here, in the first modified example, the capacitor chip 130 is an example of an "insulating chip".

[0171] As described above, the capacitor chip 130 includes capacitors 120A and 120B instead of the transformers 15A and 15B of the transformer chip 50. For this reason, in the capacitor chip 130, the components common to the transformer chip 50 are given the same reference numerals as the components of the transformer chip 50, and the description thereof will be omitted.

[0172] The capacitor chip 130 includes a first unit 140, a second unit 150 formed on the first unit 140, and an insulating glass layer 110 interposed between the first unit 140 and the second unit 150, similar to the transformer chip 50. The first unit 140 is formed in a rectangular flat plate shape with the Z direction as the thickness direction. In a plan view, the first unit 140 is formed in a rectangular shape with the X direction as the short side direction and the Y direction as the long side direction. The second unit 150 is formed in a rectangular shape smaller in the X direction than the first unit 140. The arrangement of the first unit 140 and the second unit 150 may be the same as the first unit 90 and the second unit 100 of the embodiment. In other words, the capacitor chip 130 may have the same shape as the transformer chip 50.

[0173] The capacitor chip 130 has a first chip surface 131, a second chip surface 132, and a chip back surface 133 facing the opposite side to the chip surfaces 131, 132. Although not shown, the chip back surface 133 of the capacitor chip 130 is bonded to the first die pad 61 (both see FIG. 4) by a conductive bonding material SD.

[0174] A plurality of first pads 54 are formed on the first chip surface 131 of the capacitor chip 130. The first pads 54 are electrically connected to the capacitors 120A and 120B, similarly to the above embodiment. In one example, two first pads 54 are formed corresponding to the number of capacitors 120A and 120B. In one example, the first pads 54 are arranged at the same positions as each other in the X direction and spaced apart from each other in the Y direction.

[0175] A plurality of second pads 55 are formed on the second chip surface 132 of the capacitor chip 130. The plurality of second pads 55 are electrically connected to the capacitors 120A and 120B, similarly to the above embodiment. In one example, two second pads 55 are formed corresponding to the number of capacitors 120A and 120B. In one example, the plurality of second pads 55 are arranged at the same positions as each other in the X direction and spaced apart from each other in the Y direction.

[0176] The first unit 140 includes a first pad 54 , a first semiconductor substrate 91 , a first element insulating layer 92 , first electrode plates 121 of the capacitors 120A and 120B, and a first connection portion 141 . The first electrode plates 121 of the capacitors 120A and 120B are flat electrode plates whose thickness direction is in the Z direction. The shape of the first electrode plates 121 in a plan view is, for example, rectangular. These first electrode plates 121 are arranged at the same position in the X direction and spaced apart from each other in the Y direction.

[0177] The first electrode plate 121 is embedded in the first element insulating layer 92. More specifically, the first electrode plate 121 is disposed at a position spaced apart in the Z direction from the first element front surface 92A of the first element insulating layer 92. The first electrode plate 121 is disposed at a position spaced apart in the Z direction from the first element back surface 92B of the first element insulating layer 92. For this reason, the first electrode plate 121 is not exposed from the first element insulating layer 92. In one example, the position of the first electrode plate 121 in the Z direction is similar to that of the first coil 21 in the above embodiment.

[0178] The first electrode plate 121 is made of a material containing one or more appropriately selected from, for example, Ti, TiN, Au, Ag, Cu, Al, and W. In one example, the first electrode plate 121 is formed of a material containing Cu. Note that the shape of the first electrode plate 121 in a plan view can be changed arbitrarily.

[0179] The first connection portion 141 connects the first pad 54 and the first electrode plate 121. In one example, the arrangement and shape of the first connection portion 141 are the same as the first connection portion 93 (see FIG. 7) of the above embodiment. Note that the arrangement and shape of the first connection portion 141 can be changed as desired.

[0180] The second unit 150 includes the second semiconductor substrate 101, the second element insulating layer 102, the second electrode plates 122 of the capacitors 120A and 120B, and the second connection portion 151. The second electrode plates 122 of the capacitors 120A and 120B are flat electrode plates with the Z direction being the thickness direction. The shape of the second electrode plate 122 in a plan view is, for example, rectangular. In one example, the shape of the second electrode plate 122 in a plan view is rectangular with the X direction being the short side direction and the Y direction being the long side direction. In one example, the size of the second electrode plate 122 is the same as the size of the first electrode plate 121. That is, the dimensions of the second electrode plate 122 in the X direction, the Y direction, and the Z direction are equal to the dimensions of the first electrode plate 121 in the X direction, the Y direction, and the Z direction. These second electrode plates 122 are arranged at the same position in the X direction and spaced apart from each other in the Y direction. In FIG. 19, second electrode plate 122 of capacitor 120A is shown, but second electrode plate 122 of capacitor 120B is not shown.

[0181] The second electrode plate 122 is embedded in the second element insulating layer 102. More specifically, the second electrode plate 122 is disposed at a position spaced apart in the Z direction from the second element front surface 102A of the second element insulating layer 102. The second electrode plate 122 is disposed at a position spaced apart in the Z direction from the second element back surface 102B of the second element insulating layer 102. Therefore, the second electrode plate 122 is not exposed from the second element insulating layer 102. In one example, the arrangement position of the second electrode plate 122 in the Z direction is similar to that of the second coil 22 of the above embodiment.

[0182] The second electrode plate 122 is made of a material containing one or more appropriately selected from, for example, Ti, TiN, Au, Ag, Cu, Al, and W. In one example, the second electrode plate 122 is formed of a material containing Cu. Note that the shape of the second electrode plate 122 in a plan view can be changed arbitrarily.

[0183] The second connection portion 151 connects the second pad 55 and the second electrode plate 122. In one example, the arrangement and shape of the second connection portion 151 are similar to those of the first connection portion 103 (see FIG. 8) in the above embodiment. The arrangement and shape of the second connection portion 151 can be changed as desired. The manufacturing method of the capacitor chip 130 is similar to the manufacturing method of the transformer chip 50.

[0184] (Second modified example) The arrangement of the second pad 55 in plan view can be changed arbitrarily. In one example, as shown in FIG. 20, the second pad 55 may be arranged at a position overlapping the second coil 22 in plan view. In one example, the second pad 55 is arranged on the inside of the winding portion of the second coil 22 in plan view. In one example, the second pad 55 is arranged at a position overlapping the inner connection portion 22A in plan view. Note that the second pad 55 may be arranged at a position overlapping the second electrode plate 122 in plan view in the first modified example.

[0185] (Third modified example) The configuration of the first connection body 103A can be changed arbitrarily. In one example, as shown in FIG. 21, the first connection body 103A may be a conductive via 103D extending in the Z direction. More specifically, a through hole 101K is formed in the second semiconductor substrate 101. The via 103D is disposed in the through hole 101K. An insulating layer 102JA is formed between the via 103D and the inner surface constituting the through hole 101K. This insulates the via 103D from the second semiconductor substrate 101. A first pad 54A is formed on the via 103D. In this case, the second semiconductor substrate 101 does not need to be a substrate with low electrical resistivity as in the above embodiment. In one example, the second semiconductor substrate 101 may be the same semiconductor substrate as the first semiconductor substrate 91.

[0186] (Fourth modified example) As shown in FIG. 22, the second semiconductor substrate 101 may have an insulating layer 105R on the second substrate surface 101A. In the insulating layer 105R, for example, a plurality of contact holes 105S are formed penetrating the insulating layer 105R in the Z direction from the first connector 103A. A conductor 105T is embedded in each contact hole 105S. In one example, the conductor 105T embedded in the contact hole 105S is made of a material including one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W. A second pad 55 is formed on the insulating layer 105R. The second pad 55 is disposed at a position overlapping with the plurality of contact holes 105S in a plan view. The second pad 55 is electrically connected to the plurality of conductors 105T. Therefore, the second pad 55 and the first connector 103A are electrically connected via the conductor 105T. The size of the second pad 55 can be changed arbitrarily. It is only necessary that the second pads 55 are formed so as not to come into contact with adjacent second pads 55. In one example, the second pads 55 can be formed to a size that protrudes from the insulating layer 102JA in a plan view.

[0187] Fig. 23 shows a schematic cross-sectional structure for explaining an example of a manufacturing method of the transformer chip 50 of Fig. 22. In the manufacturing method of the transformer chip 50, the second semiconductor substrate 101 is ground to reduce its thickness, and then an insulating layer 105R is formed. Then, a plurality of contact holes 105S and conductors 105T are formed. Then, the second pads 55 are formed. Then, in a singulation process, the separation region 940 in which the grooves 930 are provided is removed.

[0188] (Other changes) In the above embodiment, the position of the first coil 21 in the Z direction is not limited to the example shown in Fig. 4 and can be changed as desired. For example, the first coil 21 may be located closer to the first element back surface 92B than to the edge element front surface 92A in the Z direction. The first coil 21 may also be disposed in the center of the first element insulating layer 92 in the Z direction.

[0189] In the above embodiment, the position of the second coil 22 in the Z direction is not limited to the example shown in Fig. 4 and can be changed as desired. The second coil 22 may be disposed closer to the second element back surface 102B than to the second element front surface 102A of the second element insulating layer 102 in the Z direction. The second coil 22 may also be disposed in the center of the second element insulating layer 102 in the Z direction.

[0190] In the above embodiment and each modified example, the outer connection portion 21B of the first coil 21 of the transformer 15A and the outer connection portion 21B of the first coil 21 of the transformer 15B may be provided separately. In this case, the first pad 54B may be provided one each corresponding to the outer connection portion 21B of the first coil 21 of the transformer 15A and the outer connection portion 21B of the first coil 21 of the transformer 15B. The outer connection portion 22B of the second coil 22 of the transformer 15A and the outer connection portion 22B of the second coil 22 of the transformer 15B may be provided separately. In this case, the second pad 55B may be provided one each corresponding to the outer connection portion 22B of the second coil 22 of the transformer 15A and the outer connection portion 22B of the second coil 22 of the transformer 15B.

[0191] In the first modified example, the number of capacitors 120A, 120B can be changed. Also, the number of first pads 54 and second pads 55 can be changed according to the number of capacitors 120A, 120B. Specifically, the number of first pads 54 is the same as the number of capacitors 120A, 120B. In one example, the total number of capacitors 120A, 120B may be four. In this case, the number of first pads 54 and second pads 55 is four each.

[0192] In the above embodiment, the thickness of the second semiconductor substrate 101 may be equal to the thickness of the first semiconductor substrate 91 . In the manufacturing method of the above embodiment, the order of the steps of forming the second pads 55 can be changed as desired. The second pads 55 may be formed after the first connectors 103A are formed.

[0193] In the above embodiment and each modified example, the protrusion 101D does not have to be formed. In one example, the manufacturing method of the above embodiment may include a step of removing the protrusion 101D. In the above embodiment, the transformer chip 50 may be disposed on the second die pad 71.

[0194] In the above embodiment, the configuration of the signal transmission device 10 can be changed arbitrarily. In one example, the first chip 30 may be omitted from the signal transmission device 10. In this case, the primary side circuit 13 may be included in, for example, the first unit 90 of the transformer chip 50. The multiple first pads 54 of the first unit 90 are electrically connected to the primary side circuit 13. In addition, the multiple first pads 54 may be individually connected to the multiple first leads 62 by wires W1.

[0195] In one example, the second chip 40 may be omitted from the signal transmission device 10. In this case, the secondary side circuit 14 may be included in, for example, the first unit 90 of the transformer chip 50. The transformer chip 50 may be disposed on the second die pad 71. The multiple second pads 55 may be individually connected to the multiple second leads 72 by wires W4.

[0196] In one example, the signal transmission device 10 may include a plurality of transformer chips 50. The plurality of transformer chips 50 may be arranged separately on the first die pad 61 and the second die pad 71. The transformers 15 of the plurality of transformer chips 50 are connected in series. This results in a double insulation structure. As a specific example, the plurality of second pads 55 of the transformer chip 50 arranged on the first die pad 61 are individually connected to the plurality of first pads 54 of the transformer chip 50 arranged on the second die pad 71 by a plurality of wires W3. The plurality of first pads 54 of the transformer chip 50 arranged on the first die pad 61 are individually connected to the plurality of second pads 34 of the first chip 30 by a plurality of wires W2. The plurality of second pads 55 of the transformer chip 50 arranged on the second die pad 71 are individually connected to the plurality of first pads 43 of the second chip 40 by the wires W3.

[0197] The terms "first", "second", "third", etc. in this disclosure are used merely to distinguish objects and do not rank the objects. In this specification, "at least one of A and B" should be understood to mean "A only, or B only, or both A and B."

[0198] The term "on" as used in this disclosure includes the meanings "on" and "above" unless the context clearly indicates otherwise. Thus, for example, the expression "a first element is disposed on a second element" is intended to mean that in some embodiments, the first element may be disposed directly on the second element in contact with the second element, while in other embodiments, the first element may be disposed above the second element without contacting the second element. In other words, the term "on" does not exclude a structure in which another element is formed between the first element and the second element.

[0199] The Z direction used in this disclosure does not necessarily have to be a vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" of the Z direction described in this specification being "up" and "down" of the vertical direction. For example, the X direction may be a vertical direction, or the Y direction may be a vertical direction.

[0200] <Additional Notes> The technical ideas that can be understood from this disclosure are described below. Note that, for the purpose of aiding understanding, not for the purpose of limitation, the components described in the appendices are given the reference numbers of the corresponding components in the above embodiment. The reference numbers are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numbers.

[0201] [Appendix A1] a first unit (90 / 140) including a first semiconductor substrate (91) having a first substrate surface (91A) and a first substrate back surface (91B) opposite to the first substrate surface (91A), a first element insulating layer (92) formed on the first substrate surface (91A), and a first insulating element (21 / 121) provided on the first element insulating layer (92); The semiconductor device includes a second semiconductor substrate (101) having a second substrate surface (101A) and a second substrate back surface (101B) opposite to the second substrate surface (101A), a second element insulating layer (102) formed on the second substrate surface (101A), and a second insulating element (22 / 122) provided on the second element insulating layer (102), an insulating glass layer (110) interposed between the first unit (90 / 140) and a second unit (100 / 150) disposed on the first unit (90 / 140); Equipped with In a unit bonding state in which the first unit (90 / 140) and the second unit (100 / 150) are bonded by the insulating glass layer (110), the insulating glass layer (110) bonds both the first element insulating layer (92) and the second element insulating layer (102) while being in contact with both of them, and the first insulating element (21 / 121) and the second insulating element (22 / 122) are disposed opposite each other. Insulated tip(50 / 130).

[0202] [Appendix A2] the first element insulating layer (92) includes a first element surface (92A) facing the same side as the first substrate surface (91A); The ratio of the thickness (DG) of the insulating glass layer (110) to the thickness (DA1) between the first insulating element (21 / 121) included in the first element insulating layer (92) and the first element surface (92A) is equal to or greater than 1 and less than 4. An insulating tip as described in Appendix A1.

[0203] [Appendix A3] The difference in linear expansion coefficient between the insulating glass layer (110) and the first element insulating layer (92) and the second element insulating layer (102) is smaller than the difference in linear expansion coefficient between the insulating glass layer (110) and the second semiconductor substrate (101). 1. An insulated tip as described in appendix A1 or A2.

[0204] [Appendix A4] A second pad (55) electrically connected to the second insulating element (22 / 122) is provided on the second substrate back surface (101B). An insulating chip according to any one of Appendices A1 to A3.

[0205] [Appendix A5] The electrical resistivity of the second semiconductor substrate (101) is smaller than the electrical resistivity of the first semiconductor substrate (91). Insulated tip as described in Appendix A4.

[0206] [Appendix A6] The impurity concentration of the second semiconductor substrate (101) is higher than the impurity concentration of the first semiconductor substrate (91). The insulating tip described in Appendix A5.

[0207] [Appendix A7] the second semiconductor substrate (101) includes a connector (103A) electrically connected to the second pad (55); The connector (103A) is separated from other parts of the second semiconductor substrate (101) by an annular insulating layer (102JA) that penetrates the second semiconductor substrate (101) and surrounds the connector (103A) when viewed in the thickness direction of the second semiconductor substrate (101). The insulating chip according to any one of Appendices A4 to A6.

[0208] [Appendix A8] a second connection wiring (103B) that electrically connects the second insulating element (22 / 122) and the connection body (103A); The second connection wiring (103B) is provided in the second element insulating layer (92). An insulating tip as described in Appendix A7.

[0209] [Appendix A9] The thickness of the second semiconductor substrate (101) is thinner than the thickness of the first semiconductor substrate (91). An insulating tip as described in Appendix A7.

[0210] [Appendix A10] an insulating layer (105R) formed on the second substrate back surface (101B) of the second semiconductor substrate (101) so as to cover at least the connector (103A); a conductor (105T) electrically connected to the connector (103A) and penetrating the insulating layer (105R); The second pad (55) is formed on the insulating layer (105R) and is electrically connected to the conductor (105T). An insulating tip as described in Appendix A7.

[0211] [Appendix A11] The first unit (90 / 140) includes a first pad (54) exposed from the first element insulating layer (92) in a thickness direction (Z direction) of the first element insulating layer (92), When viewed from the thickness direction (Z direction), the first pad (54) is disposed at a position different from that of the second unit (100 / 150). The insulating chip according to any one of Appendices A1 to A10.

[0212] [Appendix A12] The first unit (90 / 140) includes a first pad (54) exposed from the first element insulating layer (92) in a thickness direction (Z direction) of the first element insulating layer (92), The first pad (54) and the second pad (55) are arranged separately on both sides of the second insulating element (22 / 122) in the first direction (X direction) when viewed from the thickness direction (Z direction). The insulating chip according to any one of Appendices A4 to A10.

[0213] [Appendix A13] a first connection wiring (93B) that electrically connects the first insulating element (21 / 121) and the first pad (54); The first connection wiring (93B) is provided in the first element insulating layer (92). 1. An insulated tip as described in appendix A11 or A12.

[0214] [Appendix A14] Both the first insulating element (21) and the second insulating element (22) are coils. The insulating chip according to any one of Appendices A1 to A13.

[0215] [Appendix A15] Both the first insulating element (121) and the second insulating element (122) are electrode plates. The insulating chip according to any one of Appendices A1 to A13.

[0216] [Appendix A16] The first element insulating layer (92) is a first insulating layer (921) in contact with the first semiconductor substrate (91); a second insulating layer (922) provided with a wiring layer (93B) that is laminated on the first insulating layer (921) and electrically connected to the first insulating element (21 / 121); A third insulating layer (923) laminated on the second insulating layer (922); a fourth insulating layer (924) laminated on the third insulating layer (923) and provided with the first insulating element (21 / 121); a fifth insulating layer (925) laminated on the fourth insulating layer (924) and covering the first insulating element (21 / 121); a passivation layer (92G) laminated on the fifth insulating layer (925); It is made up of An insulating chip according to any one of Appendices A1 to A15.

[0217] [Appendix A17] Each of the second insulating layer (922), the third insulating layer (923), the fourth insulating layer (924), and the fifth insulating layer (925) is A first insulating film (92P) containing SiN; A second insulating film (92Q) containing SiO2 is laminated on the first insulating film (92P); It is made up of An insulating tip as described in Appendix A16.

[0218] [Appendix A18] An insulating tip (50) according to any one of appendices A1 to A17; A primary side circuit (13); a secondary circuit (14) connected to the primary circuit (13) via the insulating chip (50); Equipped with The primary circuit (13) and the secondary circuit (14) are configured to transmit signals via the insulating chip (50). Signal transmission device (10).

[0219] [Appendix A19] a first chip (30) including the primary side circuit (13); a second chip (40) including the secondary side circuit (14); a first die pad (61) supporting the first chip (30); a second die pad (71) supporting the second chip (40); Including, The insulating chip (50) is disposed on the first die pad (61) or the second die pad (71). 2. A signaling device as described in Appendix A18.

[0220] [Appendix A20] a first unit (90 / 140) including a first semiconductor substrate (91) having a first substrate surface (91A) and a first substrate back surface (91B) opposite to the first substrate surface (91A), a first element insulating layer (92) formed on the first substrate surface (91A), and a first insulating element (21 / 121) provided on the first element insulating layer (92); a second semiconductor substrate (101) having a second substrate surface (101A) and a second substrate back surface (101B) opposite to the second substrate surface (101A), a second element insulating layer (92) formed on the second substrate surface (101A), and a second insulating element (22 / 122) provided on the second element insulating layer (92), the second unit (100 / 150) being disposed on the first unit (90 / 140); an intermediate insulating layer (110) interposed between the first unit (90 / 140) and the second unit (100 / 150); Equipped with In a unit-joined state in which the first unit (90 / 140) and the second unit (100 / 150) are joined by the intermediate insulating layer (110), the intermediate insulating layer (110) is interposed between the first element insulating layer (92) and the second element insulating layer (92), and the first insulating element (21 / 121) and the second insulating element (22 / 122) are arranged opposite each other, The electrical resistivity of the second semiconductor substrate (101) is smaller than the electrical resistivity of the first semiconductor substrate (91). Insulated tip.

[0221] [Appendix A21] A second pad (55) electrically connected to the second insulating element (22 / 122) is provided on the second substrate back surface (101B). 2. The insulating tip described in Appendix A20.

[0222] [Appendix A22] the second semiconductor substrate (101) includes a connector (103A) electrically connected to the second pad (55); The connector (103A) is separated from other parts of the second semiconductor substrate (101) by an annular insulating layer (102JA) that penetrates the second semiconductor substrate (101) and surrounds the connector (103A) when viewed in the thickness direction (Z direction) of the second semiconductor substrate (101). 2. The insulating tip according to claim A21.

[0223] [Appendix A23] The second pad (55) is connected to a connection wiring (103B) electrically connected to a second insulating element (22 / 122) through conductive vias (103C, 103D). The insulating chip according to any one of Appendices A20 to A22.

[0224] [Appendix A24] an insulating layer (105R) formed on the second substrate back surface (101B) of the second semiconductor substrate (101) so as to cover at least the connector (103A); a conductor (105T) electrically connected to the connector (103A) and penetrating the insulating layer (105R); a second pad (55) formed on the insulating layer (105R) and electrically connected to the conductor (105T); Includes 2. The insulated tip described in Appendix A22.

[0225] [Appendix A25] Both the first insulating element (21) and the second insulating element (22) are coils. The insulating chip according to any one of Appendices A20 to A24.

[0226] [Appendix A26] Both the first insulating element (121) and the second insulating element (122) are electrode plates. The insulating chip according to any one of Appendices A20 to A24.

[0227] [Appendix A27] the second element insulating layer (102) includes a second element surface (102A) facing the same side as the second substrate surface (101A); The ratio of the thickness (DG) of the intermediate insulating layer (110) to the thickness (DA2) between the second insulating element (22 / 122) included in the second element insulating layer (102) and the second element surface (102A) is 1 or more and less than 4. The insulating chip according to any one of Appendices A20 to A26.

[0228] [Appendix A28] The second pad (55) is disposed directly above the second insulating element (22 / 122). The insulating chip according to any one of Appendices A4 to A10.

[0229] [Appendix A29] The first insulating element (21 / 121) is disposed closer to the first element back surface (92A) than the first pad (54) in the thickness direction (Z direction). 1. An insulated tip as described in appendix A11 or A12.

[0230] [Appendix A30] The thickness of the first element insulating layer (92) and the thickness of the second element insulating layer (102) are equal to each other. The insulating chip according to any one of Appendices A1 to A8.

[0231] [Appendix B1] preparing a first wafer (800) including a first semiconductor substrate (91) having a first substrate surface (91A) and a first substrate back surface (91B) opposite to the first substrate surface (91A), a first element insulating layer (92) formed on the first substrate surface (91A), and a first insulating element (21 / 121) provided on the first element insulating layer (92); preparing a second wafer (900) including a second semiconductor substrate (101) having a second substrate surface (101A) and a second substrate back surface (101B) opposite to the second substrate surface (101A), a second element insulating layer (102) formed on the second substrate surface (101A), and a second insulating element (22 / 122) provided on the second element insulating layer (102); forming an intermediate insulating layer (110X) on the first element insulating layer (92) or on the second element insulating layer (102); bonding the first wafer (800) and the second wafer (900) together such that the intermediate insulating layer (110X) is interposed between the first element insulating layer (92) and the second element insulating layer (102) and the first insulating element (21 / 121) and the second insulating element (22 / 122) are disposed opposite each other; cutting both the first wafer (800) and the second wafer (900) into individual pieces while the first wafer (800) and the second wafer (900) are bonded together; A method for producing an insulating tip comprising:

[0232] [Appendix B2] The intermediate insulating layer (110X) is formed of a paste material containing glass powder. A method for producing an insulating tip according to appendix B1.

[0233] [Appendix B3] Preparing the first wafer (800) includes providing a first pad (54) electrically connected to the first insulating element (21 / 121) so as to be exposed from the first element insulating layer (92) in a thickness direction of the first element insulating layer (92); Preparing the second wafer (900) includes forming a groove (930) by cutting a portion of the second semiconductor substrate (101) in a thickness direction (Z direction) while penetrating the second element insulating layer (102) in a thickness direction thereof; By bonding the first wafer (800) and the second wafer (900) together, the groove (930) is disposed opposite the first pad (54), The step of dividing the second wafer into individual pieces includes removing a portion (940) of the second wafer (900) in which the groove (930) is provided. A method for producing an insulating chip according to appendix B1 or B2.

[0234] [Appendix B4] Preparing the second wafer (900) includes: forming a trench (101C) recessed from the second semiconductor substrate (101) toward a back surface (101B) of the second substrate; filling the trench (101C) with an insulating layer (903); Including, The trench (101C) is formed in a ring shape when viewed in the thickness direction of the second semiconductor substrate (101). A method for producing an insulating chip according to any one of Appendix B1 to B3.

[0235] [Appendix B4] The method further includes grinding the second semiconductor substrate (101) so as to reduce its thickness while the first wafer (800) and the second wafer (900) are bonded together; By grinding the second semiconductor substrate (101), a connection body (103A) that penetrates the second semiconductor substrate (101) and is surrounded by the insulating layer (903) is formed by grinding down to the bottom wall of the trench (101C). A method for producing an insulating tip according to appendix B3.

[0236] [Appendix B5] The method further includes forming a second pad (55) in contact with the connection body (103A). A method for producing an insulating tip according to appendix B4.

[0237] [Appendix B6] The intermediate insulating layer (110X) is formed by screen printing on the first element insulating layer (92) or on the second element insulating layer (102). A method for producing an insulating chip according to any one of Appendix B1 to B5.

[0238] [Appendix B7] The intermediate insulating layer (110X) includes at least one of an epoxy resin and a bismaleimide resin. A method for producing an insulating tip according to appendix B1.

[0239] [Appendix B8] A ratio of a thickness (DG) of the intermediate insulating layer (110X) to a thickness (DA1) between the first insulating element (21 / 121) included in the first element insulating layer (92) and the first element surface (92A) is equal to or greater than 1 and less than 4. A method for producing an insulating chip according to any one of Appendix B1 to B7.

[0240] The above description is merely illustrative. Those skilled in the art may recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of describing the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and alterations that fall within the scope of the present disclosure, including the scope of the claims. [Explanation of symbols]

[0241] 10. Signal transmission device 10A…Signal transmission circuit 11…Primary side terminal 12…Secondary side terminal 13…Primary side circuit 14…Secondary side circuit 15, 15A, 15B...Transformer 16A,16B…Primary side signal line 17A,17B…Secondary side signal line 21…First coil 21A…Inner connection part 21B…Outer connection part 22…Second coil 22A…Inner connection part 22B…Outer connection part 30…First tip 31…Chip surface 33…First pad 34…Second pad 35…Third pad 40…Second chip 41…Chip surface 43…First pad 44…Second pad 45…3rd pad 50...Transformer tip (insulating tip) 51…First chip surface 51A…Exposed area 52…Second chip surface 53…Chip backside 54, 54A~54C…First pad 55,55A~55C...Second pad 60...First conductive member 61…First die pad 62…1st lead 70...Second conductive member 71…Second die pad 72…2nd lead 80…Sealing resin 81~84…Resin side 90…1st Unit 91...first semiconductor substrate 91A…First board surface 91B…Back side of first board 92...first element insulating layer 92A…First element surface 92B…Back side of first element 92C~92F…First element side 92G…passivation layer 92P…First insulating film 92Q…Second insulating film 92R…Insulator 93,95…First connection part 93A…First connector 93AA…Beer 93AB…Conductive layer 93AC…Beer 93B…First connection wire 93BA, 93BB...End 93C…Second connector 94…Second connection part 100…Second unit 101...second semiconductor substrate 101A…Second board surface 101B…Second board backside 101C…Trench 101D…Protrusion 101K...Through hole 102...second element insulating layer 102A…Second element surface 102B…Second element back side 102C~102F…Second element side 102G…passivation layer 102J…Insulating layer on board side 102JA…insulating layer 102P…First insulating film 102Q…Second insulating film 102R…Insulator 103, 105…First connection part 103A…First connector 103B…First connection wiring 103BA,103BB…end 103C...Second connector 103D…Via 104…Second connection part 105R…insulating layer 105S…Contact hole 105T…Conductor 110...insulating glass layer 110X: Intermediate insulation layer 120A, 120B... Capacitor 121...First electrode plate 122…Second electrode plate 130...Capacitor chip (insulating chip) 131…First chip surface 132…Second chip surface 133…Chip backside 140…1st Unit 141…First connection part 150…Second unit 151…Second connection part 800…1st wafer 801...Semiconductor wafer 802...element insulating layer 900…2nd wafer 901...Semiconductor wafer 902... Element insulating layer 903...Insulating layer 910...Dicing tape 921~925…1st~5th insulating layers 930...Groove 940…Separation area 1021~1024...1st~4th insulating layers W1~W4…Wire SD: Conductive adhesive DA1: Thickness between the first coil and the surface of the first element DA2: Thickness between the second coil and the surface of the second element DG: Thickness of insulating glass layer CL…cutting line

Claims

1. a first unit including a first semiconductor substrate having a first substrate surface and a first substrate back surface opposite to the first substrate surface, a first element insulating layer formed on the first substrate surface, and a first insulating element provided on the first element insulating layer; a second semiconductor substrate having a second substrate front surface and a second substrate back surface opposite to the second substrate front surface, a second element insulating layer formed on the second substrate front surface, and a second insulating element provided in the second element insulating layer; an insulating glass layer interposed between the first unit and a second unit disposed on the first unit; Equipped with In a unit bonded state in which the first unit and the second unit are bonded by the insulating glass layer, the insulating glass layer bonds both the first element insulating layer and the second element insulating layer in a state of contact with both the first element insulating layer and the second element insulating layer, and the first insulating element and the second insulating element are disposed opposite to each other. Insulated tip.

2. the first device insulation layer includes a first device surface facing the same side as the first substrate surface; a ratio of a thickness of the insulating glass layer to a thickness between the first insulating element included in the first element insulating layer and the first element surface is equal to or greater than 1 and less than 4; The insulating tip of claim 1 .

3. A difference in linear expansion coefficient between the insulating glass layer and the first element insulating layer and between the insulating glass layer and the second element insulating layer is smaller than a difference in linear expansion coefficient between the insulating glass layer and the second semiconductor substrate. The insulating tip of claim 1 .

4. A second pad electrically connected to the second insulating element is provided on the rear surface of the second substrate. The insulating tip of claim 1 .

5. The electrical resistivity of the second semiconductor substrate is smaller than the electrical resistivity of the first semiconductor substrate.

5. The insulating tip of claim 4.

6. The second semiconductor substrate has an impurity concentration higher than the impurity concentration of the first semiconductor substrate. The insulating tip of claim 5.

7. the second semiconductor substrate includes a connection body electrically connected to the second pad; The connection body is separated from other portions of the second semiconductor substrate by an annular insulating layer that penetrates the second semiconductor substrate and surrounds the connection body when viewed in a thickness direction of the second semiconductor substrate.

5. The insulating tip of claim 4.

8. a second connection wiring that electrically connects the second insulating element and the connection body; The second connection wiring is provided in the second element insulating layer.

8. The insulating tip of claim 7.

9. The thickness of the second semiconductor substrate is smaller than the thickness of the first semiconductor substrate.

8. The insulating tip of claim 7.

10. an insulating layer formed on a rear surface of the second semiconductor substrate so as to cover at least the connection body; a conductor electrically connected to the connector and penetrating the insulating layer; The second pad is formed on the insulating layer and is electrically connected to the conductor.

8. The insulating tip of claim 7.

11. the first unit includes a first pad exposed from the first element insulating layer in a thickness direction of the first element insulating layer, When viewed in the thickness direction, the first pad is disposed at a position different from that of the second unit. The insulating tip of claim 1 .

12. the first unit includes a first pad exposed from the first element insulating layer in a thickness direction of the first element insulating layer, The first pad and the second pad are arranged separately on both sides of the second insulating element in the first direction when viewed in the thickness direction.

5. The insulating tip of claim 4.

13. a first connection wiring electrically connecting the first insulating element and the first pad; The first connection wiring is provided in the first element insulating layer. The insulating tip of claim 11.

14. Both the first insulating element and the second insulating element are coils. The insulating tip of claim 1 .

15. Both the first insulating element and the second insulating element are electrode plates. The insulating tip of claim 1 .

16. The first element insulating layer is a first insulating layer in contact with the first semiconductor substrate; a second insulating layer provided with a wiring layer electrically connected to the first insulating element; a third insulating layer laminated on the second insulating layer; a fourth insulating layer laminated on the third insulating layer and having the first insulating element provided thereon; a fifth insulating layer laminated on the fourth insulating layer and covering the first insulating element; a passivation layer laminated on the fifth insulating layer; It is made up of The insulating tip of claim 1 .

17. Each of the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer is A first insulating film containing SiN; A SiO.sub.2 insulating film is laminated on the first insulating film. ２ A second insulating film comprising: It is made up of 17. The insulated tip of claim 16.

18. An insulating tip according to any one of claims 1 to 17, A primary side circuit; a secondary circuit connected to the primary circuit via the insulating chip; Equipped with The primary circuit and the secondary circuit are configured to transmit signals through the insulating chip. Signal transmission device.

19. A first chip including the primary side circuit; a second chip including the secondary side circuit; a first die pad supporting the first chip; a second die pad supporting the second chip; Including, The insulating chip is disposed on the first die pad or the second die pad.

20. The signal transmission device according to claim 18.

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