Communication interface circuit and operating method for the same

Abstract

To provide a communication interface circuit for supporting stable data transmission, and an operating method for the same.SOLUTION: A communication interface circuit of the present invention includes a protocol hierarchical circuit that generates packet data on the basis of input data, and a physical hierarchical circuit that encodes the packet data, outputs a transmission state, and drives a data lane including a plurality of three-phase wire links on the basis of the transmission state. The physical hierarchical circuit includes an encoder that calculates the transmission state on the basis of a preceding state output from the encoder in the previous unit interval, a symbol in which the packet data are mapped, and a control code. The control code instructs the encoding change on the basis of the coupling relation of the three-phase wire links.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a communication interface circuit and an operating method thereof, and more particularly to a communication interface circuit and an operating method thereof that support stable data transmission. [Background technology]

[0002] Components within electronic devices exchange data with each other through communication links. The components connect to the communications link through communications interface circuitry. The data to be transmitted is converted by the communications interface into a form suitable for transmission and transmitted over the communications link.

[0003] Standards exist for communicating data exchanged between components. For example, image sensing devices exchange data with other components using the Camera Serial Interface (CSI) and C-PHY defined by the Mobile Industry Processor Interface (MIPI) Alliance.

[0004] The amount of data exchanged between different components in electronic devices is increasing, and supporting stable data transmission of such data is becoming a challenge. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] U.S. Patent No. 11,641,294 Summary of the Invention [Problem to be solved by the invention]

[0006] The present invention has been made in consideration of the above-mentioned problems with the conventional communication interface circuits, and an object of the present invention is to provide a communication interface circuit and an operating method thereof that support stable data transmission. [Means for solving the problem]

[0007] In order to achieve the above object, a communication interface circuit according to the present invention includes a protocol layer circuit that generates packet data based on input data, and a physical layer circuit that encodes the packet data to output a transmission state and drives a data lane including a plurality of three-phase wire links based on the transmission state, wherein the physical layer circuit includes an encoder that calculates the transmission state based on a previous state output from an encoder in a previous unit interval, a symbol to which the packet data is mapped, and a control code, and the control code instructs an encoding change based on a coupling relationship of the plurality of three-phase wire links.

[0008] In order to achieve the above object, a communication interface circuit according to the present invention includes a physical layer circuit that generates a plurality of differential signals based on driving voltages of each of a plurality of three-phase wire links of a data lane and outputs a symbol based on the plurality of differential signals, and a protocol layer circuit that de-maps the symbol and outputs data, wherein the physical layer circuit includes a decoder that calculates the symbol based on a received differential signal based on the plurality of differential signals, a previous differential signal based on the plurality of differential signals in a previous unit interval, and a control code, and the control code indicates a decoding change based on a coupling relationship of the plurality of three-phase wire links.

[0009] In order to achieve the above object, a method for operating a communication interface circuit according to the present invention includes the steps of generating packet data based on input data, encoding the packet data to output a transmission state, and driving a data lane composed of a plurality of three-phase wire links based on the transmission state, wherein the step of encoding the packet data to output a transmission state includes the step of calculating the transmission state based on a previous state output in a previous unit interval, a symbol to which the packet data is mapped, and a control code, and the control code instructs an encoding change based on a coupling relationship of the plurality of three-phase wire links. Effect of the Invention

[0010] According to the communication interface circuit and the operating method thereof of the present invention, the physical layer circuit of the present invention performs appropriate encoding for the changed coupling relationship of the communication link based on a control code indicating a change in the coupling relationship of the communication link, thereby reducing degradation of the communication channel and enabling stable data transmission. [Brief description of the drawings]

[0011] [Figure 1] 1 is a block diagram showing a schematic configuration of a communication interface circuit according to an embodiment of the present invention; [Diagram 2] 2 is a block diagram showing a detailed configuration of a physical layer circuit of a communication interface circuit according to an embodiment of the present invention; FIG. [Diagram 3] FIG. 1 is a block diagram illustrating a communication interface circuit that supports communication link changes based on an analog multiplexer. [Figure 4] FIG. 2 is a block diagram showing a detailed configuration of an encoder of a communication interface circuit according to an embodiment of the present invention. [Diagram 5]1 is a diagram illustrating a state diagram according to encoding of a communication interface circuit according to an embodiment of the present invention; [Figure 6] 1 is a diagram illustrating a state diagram according to encoding of a communication interface circuit according to an embodiment of the present invention; [Figure 7] FIG. 2 is a diagram for explaining an embodiment of a communication link change of a communication interface circuit according to an embodiment of the present invention. [Figure 8] FIG. 2 is a diagram for explaining an embodiment of a communication link change of a communication interface circuit according to an embodiment of the present invention. [Figure 9] FIG. 2 is a diagram for explaining an embodiment of a communication link change of a communication interface circuit according to an embodiment of the present invention. [Figure 10] FIG. 2 is a diagram for explaining an embodiment of a communication link change of a communication interface circuit according to an embodiment of the present invention. [Figure 11] FIG. 2 is a diagram for explaining an embodiment of a communication link change of a communication interface circuit according to an embodiment of the present invention. [Figure 12] 1 is a block diagram showing a schematic configuration of a receiver communication interface circuit according to an embodiment of the present invention; [Figure 13] 2 is a block diagram showing a detailed configuration of a physical layer circuit of a communication interface circuit according to an embodiment of the present invention; FIG. [Figure 14] 2 is a block diagram showing a detailed configuration of a decoder of the communication interface circuit according to the embodiment of the present invention; FIG. [Figure 15] 2 is a diagram illustrating a decoder according to an embodiment of the present invention; [Figure 16] FIG. 2 is a diagram illustrating a symbol interpreter of a decoder according to an embodiment of the present invention. [Figure 17] 4 is a flowchart illustrating an operation method of a transmission side communication interface according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Next, a specific example of an embodiment for carrying out a communication interface circuit and an operating method thereof according to the present invention will be described with reference to the drawings. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following, the embodiments of the present invention will be described clearly and in detail to the extent that those skilled in the art can easily practice the present invention.

[0013] FIG. 1 is a block diagram showing a schematic configuration of a transmission-side communication interface circuit according to an embodiment of the present invention. For convenience, the transmitting communication interface circuit will be described as a transmit interface circuit, and the receiving communication interface circuit will be described as a receive interface circuit. The communications interface circuitry may be operable as either a transmit interface circuitry or a receive interface circuitry, or may be operable as both.

[0014] Referring to FIG. 1, a transmission interface circuit 100 according to an embodiment of the present invention includes a protocol layer circuit 110 and a physical layer circuit 120. The transmission interface circuit 100 may be a communication circuit for transmitting data between electronic devices, such as internal components of a mobile device, an automobile, and the like. The internal components may be an image sensing device, a display device. For example, the transmission interface circuit 100 may be used to couple components together in mobile computing devices such as smartphones, tablet computers, laptop computers, home appliance devices such as refrigerators and video cameras, wearable computing devices, and automobiles and similar devices. For example, the transmission interface circuit 100 may be arranged to couple an application processor of a mobile device with an image sensing device.

[0015] The transmission interface circuit 100 may be embodied as part of any one of the integrated circuits included in the component. For example, the transmission interface circuit 100 may be implemented as a partial circuit block of an image sensor of an image sensing device. Alternatively, the transmission interface circuit 100 may be implemented as a part of a circuit block of a display driver integrated circuit (DDI) of a display device. Alternatively, the transmission interface circuit 100 may be embodied in a separate communications chip that is connected to the components. For example, the transmission interface circuit 100 may be implemented as a communication semiconductor chip such as an Application Specific Integrated Circuit (ASIC) or a Field Programmable Gate Array (FPGA) for supporting data exchange between components.

[0016] The protocol layer circuit 110 receives data and generates transmission data (Tx_Data) in the form of packet data. The protocol layer circuit 110 generates a payload based on the input data, and inserts a header and a footer suitable for transmission before and after the payload, respectively, to generate transmission data (Tx_Data) in the form of packet data. In some embodiments, the protocol layer circuit 110 generates transmission data (Tx_Data) according to the Camera Serial Interface (CSI-2), Display Serial Interface (DSI), and DSI-2 defined by the Mobile Industry Processor Interface (MIPI) Alliance.

[0017] The transmission data (Tx_Data) is provided to the physical layer circuit 120, which encodes the transmission data (Tx_Data) to generate a driving signal. Each communication link is driven to a different signal level based on the drive signal. Data signals are transmitted through changes in signal levels on the communications link.

[0018] The physical layer circuit 120 transmits the data signal to the receiving interface circuit 200 on the receiving side through the data lane LANE. The physical layer circuitry 120 transmits data signals over at least one data lane LANE. For example, the physical layer circuitry 120 transmits data signals over a number of data lanes LANE. The physical layer circuitry 120 transmits data signals through data lanes LANE provided over a number of communication links. For example, a data lane LANE may be provided over multiple three-phase communication links. The communication link may be referred to as a wire link or a three-phase wire link. Each wire link transmits one of three mutually distinct levels of signals in a unit interval. For example, each wire link transmits a signal of one of a high level signal HIGH, a medium level signal MID, and a low level signal LOW in any one unit section.

[0019] The physical layer circuitry 120 is capable of driving multiple wire links in accordance with the C-PHY defined by the MIPI Alliance. For example, the physical layer circuitry 120 includes a number of line drivers configured to couple components to three three-phase wire links. The physical layer circuit 120 generates a driving signal by encoding transmission data (Tx_Data). The drive signal defines the signal level on each wire link. In any one unit section, the signal level state of each of the multiple wire links that provide one data lane LANE is defined as a wire state. Therefore, one wire state is transmitted to the receiving interface circuit 200 through one data lane LANE for each unit section.

[0020] In this specification, the wire state transmitted from the current unit section in the same data lane LANE is called a transmission state. A wire state transmitted in a unit interval immediately preceding the unit interval in which a transmission state is transmitted is called a preceding state. Therefore, the preceding state is transmitted through the data lane LANE, and the transmission state is transmitted through the data lane LANE in the next consecutive unit section.

[0021] The physical layer circuit 120 encodes the transmission data (Tx_Data) so that the same wire state is not continuously transmitted in consecutive unit intervals. The physical layer circuit 120 generates drive signals such that the signal levels of the three wire links that make up the wire state are all different from each other. For example, in a particular unit section, the signal levels of three wire links transmitting a wire state defined as +x are a high level signal HIGH, a low level signal LOW, and a middle level signal MID, respectively. Therefore, the physical layer circuit 120 calculates the transmission state by referring to the previous state. As a result, the physical layer circuit 120 does not output the same wire state consecutively. That is, the preceding state and the transmission state transmitted through the same data lane LANE are different from each other.

[0022] The physical layer circuitry 120 according to an embodiment of the present invention includes an encoder 125 . The encoder 125 computes a transmission state based on the previous state, the symbol, and the control code. The encoder of the physical layer circuit of a conventional communication interface circuit calculates the transmission state based only on the previous state and symbol. Differently, the encoder 125 of the physical layer circuit 120 according to the embodiment of the present invention calculates the transmission state further based on the control code (CONTROL_CODE). The control code (CONTROL_CODE) is a code that instructs an encoding change based on the coupling relationship of multiple three-phase wire links.

[0023] Referring to FIG. 1, a plurality of transmission pins (TXPIN_A, TXPIN_B, TXPIN_C) of a transmitting side transmission interface circuit 100 are each electrically coupled to one of a plurality of reception pins (RXPIN_A, RXPIN_B, RXPIN_C) of a reception interface circuit 200. For example, FIG. 1 shows that transmission pin A (TXPIN_A) is coupled to reception pin A (RXPIN_A), transmission pin B (TXPIN_B) is coupled to reception pin B (RXPIN_B), and transmission pin C (TXPIN_C) is coupled to reception pin C (RXPIN_C). In this case, based on the receiving pin, the wire link between transmission pin A (TXPIN_A) and receiving pin A (RXPIN_A) is called wire link A, the wire link between transmission pin B (TXPIN_B) and receiving pin B (RXPIN_B) is called wire link B, and the wire link between transmission pin C (TXPIN_C) and receiving pin C (RXPIN_C) is called wire link C.

[0024] According to the coupling settings between the components, the coupling relationship between the transmission pins (TXPIN_A, TXPIN_B, TXPIN_C) and the reception pins (RXPIN_A, RXPIN_B, RXPIN_C) changes. Although FIG. 1 exemplarily illustrates the transmit pins (TXPIN_A, TXPIN_B, TXPIN_C) being coupled to each of the receive pins (RXPIN_A, RXPIN_B, RXPIN_C) in sequence, the coupling relationship may be changed. For example, transmission pin A (TXPIN_A) may be coupled to reception pin C (RXPIN_C), transmission pin B (TXPIN_B) may be coupled to reception pin B (RXPIN_B), and transmission pin C (TXPIN_C) may be coupled to reception pin A (RXPIN_A). In this case, it can be seen that the A-wire link and the C-wire link are swapped with each other from the perspective of the transmitting side transmission interface circuit 100, and is referred to herein as A / C line swapping.

[0025] The transmission interface circuit 100 provides drive signals to each wire link of the data lane LANE based on the coupling relationship of the exchanged wire links. For example, the transmission interface circuit 100 drives the A wire link coupled to transmission pin A, the B wire link coupled to transmission pin B, and the C wire link coupled to transmission pin C with a high level signal HIGH, a low level signal LOW, and a middle level signal MID, respectively, to transmit a wire state defined as "+x." When the A-wire link and the C-wire link are swapped with each other, the transmit interface circuit 100 drives the C-wire link coupled to transmit pin A, the B-wire link coupled to transmit pin B, and the A-wire link coupled to transmit pin C with a middle level signal MID, a low level signal LOW, and a high level signal HIGH, respectively, to transmit a wire state defined as "+x."

[0026] The encoder 125 of the physical layer circuit 120 according to the embodiment of the present invention performs encoding differently according to swapping of any two wire links among the three three-phase wire links according to MIPI's C-PHY. For example, the encoder 125 may encode the same symbol into different wire states when the A-wire link is interchanged with the C-wire link, when the A-wire link is interchanged with the B-wire link, and when the B-wire link is interchanged with the C-wire link based on the provided control code.

[0027] Additionally, the encoder 125 of the physical layer circuitry 120 according to an embodiment of the present invention may perform encoding differently depending on the change of three wire links among the three three-phase wire links according to MIPI's C-PHY. For example, the encoder 125 may appropriately encode a coupling relationship in which the A wire link, the B wire link, and the C wire link are changed to the B wire link, the C wire link, and the A wire link, respectively, in sequence, based on the provided control code. Alternatively, the encoder 125 may appropriately encode the coupling relationship in which the A wire link, the B wire link, and the C wire link are changed to the C wire link, the A wire link, and the B wire link, respectively, in sequence, based on the provided control code. In the process of setting coupling of components, degradation of signal characteristics due to the communication link and degradation of signal characteristics due to the coupling pad characteristics can sometimes be solved by changing the communication link. Also, the coupling terminal arrangement between the components requires modification of the communication link.

[0028] Therefore, the physical layer circuit 120 according to the embodiment of the present invention performs appropriate encoding for the changed coupling relationship of the communication link based on the control code indicating the change in the coupling relationship of the communication link. As a result, degradation of the communication channel can be reduced, and data signals can be transmitted stably. In addition, the physical layer circuit 120 supports various interconnections between components through coupling terminal arrangements, thereby enabling stable transmission of data signals.

[0029] FIG. 2 is a block diagram showing a detailed configuration of the physical layer circuit 120 according to an embodiment of the present invention. Referring to FIG. 2, the physical layer circuit 120 includes a mapping circuit 121 , a parallel-to-serial converter 123 , an encoder 125 , a pre-driver control circuit 127 , and a driving driver 129 . Although FIG. 2 exemplarily illustrates the transmission pins (TXPIN_A, TXPIN_B, TXPIN_C) being coupled to the A wire link, the B wire link, and the C wire link in that order, the coupling relationship may be changed. For example, the physical layer circuitry according to the embodiment of FIG. 2 supports an A / C line switch with transmission pin A (TXPIN_A) coupled to a C-wire link and transmission pin C (TXPIN_C) coupled to an A-wire link. Other different forms of line switching of multiple wire links may also be supported.

[0030] The mapping circuit 121 maps the provided transmission data (Tx_Data) into symbols. Mapping circuit 121 receives 16 binary bit data and maps it into 7 symbols. The mapping circuit 121 maps the 16-bit data into seven symbols in accordance with the mapping standard defined by MIPI C-PHY. The seven symbols are provided to an encoder 125, one symbol each, through a parallel-to-serial converter 123.

[0031] The parallel-to-serial converter 123 provides to the encoder 125 three binary bits corresponding to each symbol among the seven symbols. Each symbol has one of five possible forms and is represented by 3 binary bits. Three binary bits in each symbol indicate the shape of the transition from a previous state to a transmission state based on the previous symbol. For example, the three binary bits include a flip bit (Tx_Flip), a rotation bit (Tx_Rotation), and a polarity change bit (Tx_Polarity). Each of the flip bit (Tx_Flip), rotation bit (Tx_Rotation), and polarity change bit (Tx_Polarity) indicates a transition shape between states. This will be explained in more detail below with reference to FIGS.

[0032] The encoder 125 according to the embodiment of the present invention encodes a symbol consisting of three binary bits provided based on the previous state and the control code (CONTROL_CODE) and outputs a transmission state (Pres_St). The transmission state (Pres_St) is a wire state that defines the signal levels of the three 3-phase wire links according to MIPI C-PHY. The control code (CONTROL_CODE) is stored in a register 320 outside the physical layer circuit 120 . Registers 320 store register values ​​for setting the component's environment. When the component is initially driven, the control circuit block (OUTIF) 310 reads the control code (CONTROL_CODE) from the register 320 and provides it to the encoder 125 . The control code (CONTROL_CODE) is stored in a register 320 as different values ​​according to different coupling relationships of a plurality of wire links. The encoder 125 appropriately encodes symbols for the coupling relationships of the multiple wire links based on a provided control code (CONTROL_CODE).

[0033] For example, the encoder outputs different transmission states (Pres_St) according to the coupling relationship of multiple wire links to transmit wire states "+x, -x, +y, -y, +z, -z" according to MIPI C-PHY. For example, if the provided control code indicates A / C line replacement, the encoder 125 outputs transmission states (Pres_St) of "-y, +y, -x, +x, -z, +z" to transmit wire states "+x, -x, +y, -y, +z, -z" according to MIPI C-PHY to the receiver. Similarly, if the provided control code indicates A / B line switching, the encoder 125 outputs transmission states (Pres_St) of "-x, +x, -z, +z, -y, +y" to transmit wire states "+x, -x, +y, -y, +z, -z" according to MIPI C-PHY to the receiver. In addition, if the provided control code indicates B / C line switching, the encoder 125 outputs transmission states (Pres_St) of "-z, +z, -y, +y, -x, +x" to transmit wire states "+x, -x, +y, -y, +z, -z" according to MIPI C-PHY to the receiver.

[0034] The pre-driver control circuit 127 provides driving signals (DrivingSignal_A, DrivingSignal_B, DrivingSignal_C) to a plurality of driving drivers 129 that respectively drive a plurality of wire links based on the provided transmission state (Pres_St). Each driver 129 drives the coupled wire link with one of a high level signal HIGH, a medium level signal MID, and a low level signal LOW based on each driving signal (DrivingSignal_A, DrivingSignal_B, DrivingSignal_C). Driving signals (DrivingSignal_A, DrivingSignal_B, DrivingSignal_C) of the pre-driver control circuit 127 according to an embodiment of the present invention are directly provided to each of the plurality of driving drivers 129. That is, regardless of changes in the coupling relationship of the multiple wire links, each of the multiple driving drivers 129 drives the coupled wire links based on the respective driving signals (DrivingSignal_A, DrivingSignal_B, DrivingSignal_C) provided directly from the pre-driver control circuit 127. This is because the encoder 125 according to the embodiment of the present invention calculates the transmission state (Pres_St) appropriately for the changed coupling relationship of the multiple wire links based on the control code (CONTROL_CODE).

[0035] Referring to FIG. 3, unlike the encoder 125 according to an embodiment of the present invention, the encoder ENC outputs a transmission state (State) based on the provided symbols (flip bit (Tx_Flip), rotation bit (Tx_Rotation), and polarity change bit (Tx_Polarity)) without taking into account the changed coupling relationship of multiple wire links. In this case, the plurality of driving drivers (Tx_Driver) of the driving driver circuit DRV cannot directly provide the driving signals (DS_A, DS_B, DS_C) provided by the pre-driver control circuit DCL. That is, the driving signals (DS_A, DS_B, DS_C) are appropriately selected by each of a plurality of analog multiplexers (MX1, MX2, MX3) based on the modified coupling relationship of the plurality of wire links and provided to each driving driver (Tx_Driver). In this case, there is a problem that the power consumption of the driver circuit DRV increases due to the analog multiplexers (MX1, MX2, MX3) and the area occupied by the driver circuit DRV increases. In addition, there is a problem that the wiring between the multiple analog multiplexers (MX1, MX2, MX3) and the pre-driver control circuit DCL becomes very complicated. As a result, in reality, a communication interface circuit using the encoder ENC of FIG. 3 cannot support various changes in the wire links, but can only support some changes in the wire links.

[0036] In contrast, the encoder 125 according to the embodiment of the present invention calculates a transmission state (Pres_St) appropriately for the changed coupling relationship of the multiple wire links based on the control code (CONTROL_CODE). The pre-driver control circuit 127 can directly provide a plurality of driving signals (DrivingSignal_A, DrivingSignal_B, DrivingSignal_C) generated based on the transmission state (Pres_St) to each of the driving drivers 129.

[0037] FIG. 4 is a block diagram showing a detailed configuration of the encoder 125 according to the embodiment of FIG. Referring to FIG. 4, the encoder 125 includes a symbol encoder (125_1) and a flip-flop circuit (125_2). Although FIG. 4 exemplarily illustrates that the transmission pins (TXPIN_A, TXPIN_B, TXPIN_C) are coupled to the reception pins (RXPIN_A, RXPIN_B, RXPIN_C) in sequence, the coupling relationship may be changed.

[0038] The symbol encoder (125_1) receives a symbol made up of three binary bits. The three binary bits of the symbol include a flip bit (Tx_Flip), a rotation bit (Tx_Rotation), and a polarity change bit (Tx_Polarity). Each binary bit of the symbol indicates the shape of a state transition from a previous state (Prev_St) to a transmission state (Pres_St). The symbol encoder 125_1 according to the embodiment of the present invention encodes a symbol based on a previous state Prev_St and a control code CONTROL_CODE, and outputs a transmission state Pres_St.

[0039] The control code (CONTROL_CODE) instructs encoding change based on the coupling relationship of multiple wire links provided by the data lane LANE. For example, the control code (CONTROL_CODE) may indicate encoding based on A / C line switching, B / C line switching, or A / B line switching. The control code (CONTROL_CODE) indicates encoding based on B / C / A line changes of A / B / C lines, or C / A / B line changes of A / B / C lines. The transmission states (Pres_St[0], Pres_St[1], Pres_St[2]) output by the symbol encoder (125_1) are provided to a flip-flop circuit (125_2) and a pre-driver control circuit 127.

[0040] The flip-flop circuit (125_2) and the pre-driver control circuit 127 operate based on the same clock signal (Symbol_Clk). The flip-flop circuit 125_2 stores the transmission states (Pres_St[0], Pres_St[1], Pres_St[2]) provided in the first unit interval. The flip-flop circuit (125_2) provides the transmission states (Pres_St[0], Pres_St[1], Pres_St[2]) provided in the first unit interval to the symbol encoder (125_1) as preceding states (Prev_St[0], Prev_St[1], Prev_St[2]) in the second unit interval, which is the next unit interval following the first unit interval. According to an embodiment of the present invention, the pre-driver control circuit 127 directly provides a plurality of driving signals (DrivingSignal_A, DrivingSignal_B, DrivingSignal_C) generated based on the provided transmission states (Pres_St[0], Pres_St[1], Pres_St[2]) to each of a plurality of driving drivers 129.

[0041] The drive voltage level of each wire link driven based on the transmission state (Pres_St[0], Pres_St[1], Pres_St[2]) is the same as shown in Table 1 below according to the transmitted wire state. The drive voltage levels for each wire link in Table 1 assume no swapping or changing of the A / B / C lines. [Table 1]

[0042] The high level signal HIGH, the intermediate level signal MID, and the low level signal LOW are signals having voltages (4 / 3, 1 / 2, and 1 / 4) of the reference voltage, respectively. The encoder (125_1) according to an embodiment of the present invention includes encoding logic (ENC_LOGIC). The encoding logic (ENC_LOGIC) encodes a symbol based on the previous state (Prev_St) and the control code (CONTROL_CODE) and outputs a transmission state (Pres_St). The encoding logic (ENC_LOGIC) performs encoding based on the state diagram shown in FIG. 5 when the control code (CONTROL_CODE) indicates that there is no exchange or change of the A / B / C lines.

[0043] Referring to FIG. 5, transitions between six wire states are shown by a symbol (FRP Symbol) represented by three binary bits. For example, the wire state "-y" is transitioned to the wire state "-x" by the symbol "000". Therefore, the encoding logic (ENC_LOGIC) outputs the transmission state (Pres_St) to '-x' if the control code (CONTROL_CODE) indicates no exchange or change of the A / B / C lines, the previous state (Prev_St) is '-y', and the provided symbol is '000'.

[0044] Referring to FIG. 5, when the control code (CONTROL_CODE) indicates that there is no exchange or change of the A / B / C lines, the encoding logic (ENC_LOGIC) outputs a transmission state (Pres_St) that maintains the previous state (Prev_St) and polarity based on the symbol “000” represented by 3 binary bits and reduces the character by one step. The increase in the number of wire state letters describes the alphabet in increasing order. Therefore, in the state diagram of FIG. 5, the symbol "000" transitions by rotating counterclockwise in the preceding state (Prev_St).

[0045] The encoding logic (ENC_LOGIC) changes the polarity in the preceding state (Prev_St) based on the symbol "001" and outputs a transmission state (Pres_St) in which the character is reduced by one level. The encoding logic (ENC_LOGIC) maintains the polarity in the preceding state (Prev_St) based on the symbol "010" and outputs a transmission state (Pres_St) in which the character is increased by one step. The encoding logic (ENC_LOGIC) changes the polarity in the preceding state (Prev_St) based on the symbol "011" and outputs a transmission state (Pres_St) in which the character is increased by one step.

[0046] That is, in the state diagram of FIG. 5, when the rotation bit (Tx_Rotation) of the symbol (FRP Symbol) expressed by 3 binary bits is '0', the encoding logic (ENC_LOGIC) rotates in a direction decreasing the character from the previous state (Prev_St) to calculate the transmission state (Pres_St), and when the rotation bit (Tx_Rotation) is '1', it rotates in a direction increasing the character from the previous state (Prev_St) to calculate the transmission state (Pres_St).

[0047] In the state diagram of FIG. 5, the operation of the encoding logic (ENC_LOGIC) according to the flip bit (Tx_Flip), rotation bit (Tx_Rotation), and polarity change bit (Tx_Polarity) of the symbol (FRP Symbol) represented by 3 binary bits is performed according to Table 2 below. [Table 2]

[0048] The encoding logic (ENC_LOGIC) according to the embodiment of the present invention calculates the transmission state (Pres_St) according to the state diagram of FIG. 6 when the control code (CONTROL_CODE) instructs the exchange of any two lines among the A / B / C lines. For example, the encoding logic (ENC_LOGIC) maintains the polarity in the preceding state (Prev_St) based on the symbol "000" and outputs a transmission state (Pres_St) in which the character is increased by one step. The encoding logic (ENC_LOGIC) changes the polarity in the preceding state (Prev_St) based on the symbol "001" and outputs a transmission state (Pres_St) in which the character is increased by one step. The encoding logic (ENC_LOGIC) maintains the polarity in the preceding state (Prev_St) based on the symbol "010" and outputs a transmission state (Pres_St) in which the character is reduced by one step. The encoding logic (ENC_LOGIC) changes the polarity in the preceding state (Prev_St) based on the symbol "011" and outputs a transmission state (Pres_St) in which the character is reduced by one level.

[0049] That is, in the state diagram of FIG. 6, when the rotation bit (Tx_Rotation) of the symbol (FRP Symbol) expressed by 3 binary bits is '0', the encoding logic (ENC_LOGIC) rotates in a direction to increase the character from the previous state (Prev_St) and calculates the transmission state (Pres_St), and when the rotation bit (Tx_Rotation) is '1', it rotates in a direction to decrease the character from the previous state (Prev_St) and calculates the transmission state (Pres_St).

[0050] In the state diagram of FIG. 6, the operation of the encoding logic (ENC_LOGIC) according to the flip bit (Tx_Flip), rotation bit (Tx_Rotation), and polarity change bit (Tx_Polarity) of the symbol (FRP Symbol) represented by 3 binary bits is performed according to Table 3 below. [Table 3]

[0051] FIG. 7 is a diagram for explaining the operation of the transmission interface circuit 100 according to the embodiment of the present invention following A / C line exchange. Detailed description of portions that overlap with or are similar to the description made with reference to FIGS. 1 to 6 will be omitted. Referring to FIG. 7, the transmission interface circuit 100 includes an encoder 125 , a pre-driver control circuit 127 , and a driving driver 129 . The encoder 125, the pre-driver control circuit 127, and the driving driver 129 are the same as those in FIGS.

[0052] The transmission pins (TXPIN_A, TXPIN_B, TXPIN_C) of the transmission interface circuit 100 are each coupled to the reception pins (RXPIN_C, RXPIN_B, RXPIN_A) of the reception interface circuit 200 in sequence. That is, the A and C lines on the multiple wire links that provide the data lane LANE are swapped and coupled. The encoding logic (ENC_LOGIC) of the encoder 125 according to an embodiment of the present invention receives a control code (CONTROL_CODE) that directs encoding based on the A / C line exchange.

[0053] The encoding logic (ENC_LOGIC) encodes symbols based on the control code (CONTROL_CODE) to output transmission states of "-y, +y, -x, +x, -z, +z" in response to reception of wire states (Rx Wire States) "+x, -x, +y, -y, +z, -z" based on the MIPI C-PHY of the receiving interface circuit 200. The transmission interface circuit 100 according to the embodiment of FIG. 7 calculates the transmission state (Tx Wire State) based on the state diagram described with reference to FIG. The pre-driver control circuit 127 generates a plurality of driving signals (DrivingSignal_A, DrivingSignal_B, DrivingSignal_C) based on the transmission state (Tx Wire State) output by the encoder 125, and directly provides the driving signals to each of the plurality of driving drivers 129.

[0054] The drive voltage level of each wire link driven based on the transmission state (Tx Wire State) is the same as shown in [Table 4] below according to the transmitted wire state. [Table 4]

[0055] For example, based on a control code (CONTROL_CODE) that instructs encoding based on the A / C line switching, the encoder 125 encodes the symbol and outputs a transmission state (Tx Wire State) "-y". A medium level signal MID, a low level signal LOW, and a high level signal HIGH are driven to the wire links respectively coupled to the transmission pins (TXPIN_A, TXPIN_B, TXPIN_C), in turn. By A / C line switching, the receive interface circuit 200 receives a high level signal HIGH, a low level signal LOW, and a medium level signal MID from the A line, B line, and C line, respectively, and decodes them as a receive wire state (Rx Wire State) "+x".

[0056] FIG. 8 is a diagram for explaining the operation of the transmission interface circuit 100 according to the embodiment of the present invention in response to A / B line exchange. Detailed description of portions that overlap with or are similar to the description made with reference to FIGS. 1 to 7 will be omitted. Referring to FIG. 8, the transmission interface circuit 100 includes an encoder 125 , a pre-driver control circuit 127 , and a driving driver 129 . The encoder 125, the pre-driver control circuit 127, and the driving driver 129 are the same as those in FIGS.

[0057] The transmission pins (TXPIN_A, TXPIN_B, TXPIN_C) of the transmission interface circuit 100 are each coupled to the reception pins (RXPIN_B, RXPIN_A, RXPIN_C) of the reception interface circuit 200 in sequence. That is, the A and B lines on the multiple wire links that provide the data lane LANE are swapped and coupled. The encoding logic (ENC_LOGIC) of the encoder 125 according to an embodiment of the present invention receives a control code (CONTROL_CODE) that directs encoding based on the A / B line exchange. The encoding logic (ENC_LOGIC) encodes symbols based on the control code (CONTROL_CODE) to output transmission states of "-x, +x, -z, +z, -y, +y" in response to reception of wire states (Rx Wire States) "+x, -x, +y, -y, +z, -z" based on the MIPI C-PHY of the receiving interface circuit 200. The transmission interface circuit 100 according to the embodiment of FIG. 8 calculates the transmission state (Tx Wire State) based on the state diagram described with reference to FIG.

[0058] The driving voltage level of each wire link driven based on the transmission state (Tx Wire State) is the same as that shown in Table 5 below according to the transmitted wire state. [Table 5]

[0059] For example, based on a control code (CONTROL_CODE) that instructs encoding based on the A / B line exchange, the encoder 125 encodes a symbol and outputs a transmission state (Tx Wire State) of "-x". A low level signal LOW, a high level signal HIGH, and a medium level signal MID are driven to the wire links respectively coupled to the transmission pins (TXPIN_A, TXPIN_B, TXPIN_C), in sequence. By the A / B line exchange, the receiving interface circuit 200 receives a high level signal HIGH, a low level signal LOW, and a medium level signal MID from the A line, B line, and C line, respectively, and decodes them as a receiving wire state (Rx Wire State) "+x".

[0060] FIG. 9 is a diagram for explaining the operation of the transmission interface circuit 100 according to the embodiment of the present invention in accordance with the B / C line exchange. Detailed description of portions that overlap with or are similar to the description made with reference to FIGS. 1 to 8 will be omitted. Referring to FIG. 9, the transmission interface circuit 100 includes an encoder 125, a pre-driver control circuit 127, and a driving driver 129. The encoder 125, the pre-driver control circuit 127, and the driving driver 129 are the same as those in FIGS.

[0061] The transmission pins (TXPIN_A, TXPIN_B, TXPIN_C) of the transmission interface circuit 100 are each coupled to the reception pins (RXPIN_A, RXPIN_C, RXPIN_B) of the reception interface circuit 200 in sequence. That is, the B and C lines on the multiple wire links providing the data lane LANE are swapped and coupled. The encoding logic (ENC_LOGIC) of the encoder 125 according to an embodiment of the present invention receives a control code (CONTROL_CODE) that directs encoding based on the B / C line exchange. The encoding logic (ENC_LOGIC) encodes symbols based on the control code (CONTROL_CODE) to output transmission states of "-z, +z, -y, +y, -x, +x" in response to reception of wire states (Rx wire states) "+x, -x, +y, -y, +z, -z" based on the MIPI C-PHY of the receiving interface circuit 200. The transmission interface circuit 100 according to the embodiment of FIG. 9 calculates the transmission state (Tx Wire State) based on the state diagram described with reference to FIG.

[0062] The drive voltage level of each wire link driven based on the transmission state (Tx Wire State) is the same as shown in Table 6 below according to the transmitted wire state. [Table 6]

[0063] For example, based on a control code (CONTROL_CODE) that instructs encoding based on the B / C line exchange, the encoder 125 encodes a symbol and outputs a transmission state (Tx Wire State) "-z". A high level signal HIGH, a medium level signal MID, and a low level signal LOW are driven to the wire links respectively coupled to the transmission pins TXPIN_A, TXPIN_B, and TXPIN_C in sequence. By the B / C line exchange, the receiving interface circuit 200 receives a high level signal HIGH, a low level signal LOW, and a medium level signal MID from the A line, B line, and C line, respectively, and decodes them as a receiving wire state (Rx Wire State) "+x".

[0064] FIG. 10 is a diagram for explaining an operation of the transmission interface circuit 100 according to the embodiment of the present invention in accordance with a change from line A, line B, and line C to line B, line C, and line A, respectively. Detailed description of portions that overlap with or are similar to the description made with reference to FIGS. 1 to 9 will be omitted. The transmission pins (TXPIN_A, TXPIN_B, TXPIN_C) of the transmission interface circuit 100 are each coupled to the reception pins (RXPIN_C, RXPIN_A, RXPIN_B) of the reception interface circuit 200 in sequence. That is, the A lines, B lines, and C lines on the multiple wire links providing the data lane LANE are changed and coupled to B lines, C lines, and A lines, respectively.

[0065] The encoding logic (ENC_LOGIC) of the encoder 125 according to an embodiment of the present invention receives a control code (CONTROL_CODE) that instructs encoding based on the fact that the A line, B line, and C line have been changed to the B line, C line, and A line, respectively, in sequence. The encoding logic (ENC_LOGIC) encodes symbols based on the control code (CONTROL_CODE) to output transmission states of "+y, -y, +z, -z, +x, -x" in response to reception of wire states (Rx Wire States) "+x, -x, +y, -y, +z, -z" based on the MIPI C-PHY of the receiving interface circuit 200. The transmission interface circuit 100 according to the embodiment of FIG. 10 calculates the transmission state (Tx Wire State) based on the state diagram described with reference to FIG. That is, the wire state transition patterns when the A line, B line, and C line are changed, respectively, are different from the wire state transition patterns when any two of the A line, B line, and C line are exchanged.

[0066] The drive voltage level of each wire link driven based on the transmission state (Tx Wire State) is the same as shown in Table 7 below according to the transmitted wire state. [Table 7]

[0067] For example, based on a control code (CONTROL_CODE) that instructs encoding of the A line, B line, and C line based on the B line, C line, and A line changes, respectively, the encoder 125 encodes a symbol and outputs a transmission state (Tx Wire State) "+y". A medium level signal MID, a high level signal HIGH, and a low level signal LOW are driven to the wire links respectively coupled to the transmission pins (TXPIN_A, TXPIN_B, TXPIN_C), in sequence. By changing the A line, B line, and C line in the order of B line, C line, and A line, respectively, the receiving interface circuit 200 receives a high level signal HIGH, a low level signal LOW, and a medium level signal MID from the A line, B line, and C line, respectively, and decodes them as a receiving wire state (Rx Wire State) "+x".

[0068] FIG. 11 is a diagram for explaining an operation of the transmission interface circuit 100 according to the embodiment of the present invention in accordance with a change from line A, line B, and line C to line C, line A, and line B, respectively. Detailed description of portions that overlap with or are similar to the description made with reference to FIGS. 1 to 10 will be omitted. The transmission pins (TXPIN_A, TXPIN_B, TXPIN_C) of the transmission interface circuit 100 are each coupled to the reception pins (RXPIN_B, RXPIN_C, RXPIN_A) of the reception interface circuit 200 in sequence. That is, the A lines, B lines, and C lines on the multiple wire links providing the data lane LANE are changed and coupled to C lines, A lines, and B lines, respectively.

[0069] The encoding logic (ENC_LOGIC) of the encoder 125 according to an embodiment of the present invention receives a control code (CONTROL_CODE) instructing encoding based on the fact that the A line, B line, and C line have been changed to the C line, A line, and B line, respectively, in sequence. The encoding logic (ENC_LOGIC) encodes symbols based on the control code (CONTROL_CODE) to output transmission states of "+z, -z, +x, -x, +y, -y" in response to the reception of wire states (Rx Wire States) "+x, -x, +y, -y, +z, -z" based on the MIPI C-PHY of the receiving interface circuit 200. The transmission interface circuit 100 according to the embodiment of FIG. 10 calculates the transmission state (Tx Wire State) based on the state diagram described with reference to FIG. That is, the wire state transition patterns when the A line, B line, and C line are changed, respectively, the C line, A line, and B line are changed, and are different from the wire state transition patterns when any two of the A line, B line, and C line are exchanged.

[0070] The drive voltage level of each wire link driven based on the transmission state (Tx Wire State) is the same as shown in Table 8 below according to the transmitted wire state. [Table 8]

[0071] For example, based on a control code (CONTROL_CODE) that instructs encoding of the A line, B line, and C line based on the C line, A line, and B line changes, respectively, the encoder 125 encodes a symbol and outputs a transmission state (Tx Wire State) "+z". A low level signal LOW, a medium level signal MID, and a high level signal HIGH are driven to the wire links respectively coupled to the transmission pins (TXPIN_A, TXPIN_B, TXPIN_C), in sequence. By changing the A line, B line, and C line, respectively, the C line, A line, and B line, the receiving interface circuit 200 receives a high level signal HIGH, a low level signal LOW, and a medium level signal MID from the A line, B line, and C line, respectively, and decodes them as a receiving wire state (Rx Wire State) "+x".

[0072] FIG. 12 is a block diagram showing a schematic configuration of a receiver communication interface circuit according to an embodiment of the present invention. Detailed description of portions that overlap with or are similar to the description made with reference to FIGS. 1 to 11 will be omitted. Referring to FIG. 12, the receiving interface circuit ( 200 _ 2 ) includes a physical layer circuit 210 and a protocol layer circuit 220 .

[0073] The physical layer circuit 210 receives a data signal from the transmission interface circuit 100 on the transmission side through the data lane LANE. The physical layer circuitry 210 receives data signals over at least one data lane LANE. For example, the physical layer circuitry 210 receives data signals over a number of data lanes LANE. For reference, FIG. 1 is explained assuming one data lane LANE. The physical layer circuit 210 receives receive states over data lanes LANE that are provided for multiple wire links according to C-PHY defined by the MIPI Alliance.

[0074] The physical layer circuitry 210 according to an embodiment of the present invention includes a decoder 213 . The decoder 213 computes symbols based on the preceding differential signal, the received differential signal, and the control code. A decoder in a physical layer circuit of a conventional receiving interface circuit computes symbols based only on the preceding differential signal and the received differential signal. Differently from this, the encoder 213 of the physical layer circuit 210 of the receiving interface circuit (200_2) according to the embodiment of the present invention calculates a symbol further based on a control code (CONTROL_CODE). The control code is a code that directs a decoding change based on the coupling relationship of a plurality of three-phase wire links.

[0075] That is, the receive interface circuit (100_2) supports the replacement or modification of wire links in the same manner as the transmit interface circuit 100 of FIG. If the receiving interface circuit (100_2) supports the replacement or change of the wire link, the receiving interface circuit (100_2) transmits the data signal to the data lane LANE without considering the replacement or change of the wire link. The physical layer circuit 210 demaps the calculated symbols into bit codes of the received data (Rx_Data). The received data (Rx_Data) output by the physical layer circuit 210 is data in the form of packet data. The protocol layer circuit 110 receives packet data (Rx_Data), extracts a payload based on the header and footer, and generates data.

[0076] The coupling relationship between the transmission pins (TXPIN_A, TXPIN_B, TXPIN_C) and the reception pins (RXPIN_A, RXPIN_B, RXPIN_C) can be changed according to the coupling settings between the components. Although FIG. 12 exemplarily illustrates the transmit pins (TXPIN_A, TXPIN_B, TXPIN_C) being coupled to the receive pins (RXPIN_A, RXPIN_B, RXPIN_C) in sequence, the coupling relationship may be changed. The receiving interface circuit (200_2) according to an embodiment of the present invention can change the decoding of the received differential signal based on a change in the coupling relationship between the transmission pins (TXPIN_A, TXPIN_B, TXPIN_C) and the receiving pins (RXPIN_A, RXPIN_B, RXPIN_C).

[0077] FIG. 13 is a block diagram showing a detailed configuration of a physical layer circuit according to an embodiment of the present invention. Referring to FIG. 13, the physical layer circuit 210 includes a receiver 211 , a decoder 213 , a serial-to-parallel converter 215 , and a demapper 217 . Although FIG. 13 exemplarily illustrates the transmission pins (TXPIN_A, TXPIN_B, TXPIN_C) being coupled to the A wire link, the B wire link, and the C wire link in that order, the coupling relationship may be changed. For example, the physical layer circuitry according to the embodiment of FIG. 13 may support an A / C line switch with transmission pin A (TXPIN_A) coupled to a C-wire link and transmission pin C (TXPIN_C) coupled to an A-wire link. Other forms of line replacement or modification of multiple wire links may also be supported.

[0078] The receiver 211 outputs a differential signal (Rx_AB, Rx_BC, Rx_CA) based on the difference between the drive signals of each wire link based on the received receive state. The decoder 213 according to the embodiment of the present invention calculates a symbol consisting of 3 binary bits based on the differential signals (Rx_AB, Rx_BC, Rx_CA) and the control code (CONTROL_CODE). The three binary bits include a flip bit (Tx_Flip), a rotation bit (Tx_Rotation), and a polarity change bit (Tx_Polarity). Each binary bit of a symbol dictates the shape of a transition in a preceding differential signal to a received differential signal. The transmit differential signal and receive differential signal each correspond to a wire state that defines the signal levels of three 3-phase wire links according to MIPI C-PHY.

[0079] The control code (CONTROL_CODE) indicates a decoding change based on the coupling relationship of multiple wire links. For example, the control code (CONTROL_CODE) may indicate decoding based on A / C line switching, B / C line switching, or A / B line switching. The control code (CONTROL_CODE) directs decoding based on the B / C / A line changes of the A / B / C lines or the C / A / B line changes of the A / B / C lines. The control code (CONTROL_CODE) is stored in a register outside the physical layer circuit.

[0080] Upon initial activation of the component, a control code (CONTROL_CODE) is provided to the decoder 213 . The control code (CONTROL_CODE) is stored in a register with different values ​​according to different coupling relationships of a plurality of wire links. Each symbol output by decoder 213 is provided to a serial-to-parallel converter 215 , which illustratively provides seven symbols to a demapper 217 . The demapper 217 demaps the seven symbols into 16 binary bit data and outputs received data (Rx_Data).

[0081] FIG. 14 is a block diagram showing a detailed configuration of the decoder 213 according to the embodiment of FIG. Referring to FIG. 14, the decoder 213 includes a flip-flop circuit (213_1) and a symbol decoder (213_2). FIG. 14 exemplarily illustrates that the transmission pins (TXPIN_A, TXPIN_B, TXPIN_C) are coupled to the reception pins (RXPIN_A, RXPIN_B, RXPIN_C) in sequence, but the coupling relationship may be changed. The receiver 211 outputs a differential signal (Rx_AB, Rx_BC, Rx_CA) based on the receiving state.

[0082] The differential signals (Rx_AB, Rx_BC, Rx_CA) are determined based on the receiving state as shown in Table 9 below. [Table 9]

[0083] The differential signals (Rx_AB, Rx_BC, Rx_CA) output by the receiver 211 are provided to a flip-flop circuit (213_1). The flip-flop circuit (213_1) operates based on a clock signal (Symbol_Clk). The flip-flop circuit (213_1) stores the differential signals (Rx_AB, Rx_BC, Rx_CA) received in the first unit interval in the preceding differential signals (Prev_AB, Prev_BC, Prev_CA). The flip-flop circuit 213_1 provides the differential signals (Rx_AB, Rx_BC, Rx_CA) provided in the first unit interval to the symbol decoder 213_2 as the preceding differential signals (Prev_AB, Prev_BC, Prev_CA) in the second unit interval, which is the next unit interval following the first unit interval.

[0084] The symbol decoder 213_2 according to the embodiment of the present invention receives the preceding differential signals Prev_AB, Prev_BC, Prev_CA, the received differential signals Pres_AB, Pres_BC, Pres_CA, and the control code CONTROL_CODE. The symbol decoder 213_2 decodes the received differential signals Pres_AB, Pres_BC, and Pres_CA based on the preceding differential signals Prev_AB, Prev_BC, and Pres_CA and the control code CONTROL_CODE, and outputs a symbol consisting of 3 binary bits. The three binary bits of the symbol include a flip bit (Tx_Flip), a rotation bit (Tx_Rotation), and a polarity change bit (Tx_Polarity). Each binary bit of the symbol indicates the shape of a transition in a preceding differential signal (Prev_AB, Prev_BC, Prev_CA) to a received differential signal (Pres_AB, Pres_BC, Pres_CA).

[0085] The symbol decoder 213_2 decodes the received differential signals Pres_AB, Pres_BC, and Pres_CA appropriately for the coupling relationship of the multiple wire links based on the provided control code CONTROL_CODE. The encoder decodes the received states differently according to the coupling relationship of the wire links, and outputs symbols each composed of 3 binary bits. For example, if the provided control code (CONTROL_CODE) indicates A / C line switching, the symbol decoder (213_2) decodes each of the wire states "-y, +y, -x, +x, -z, +z" according to MIPI C-PHY into symbols corresponding to "+x, -x, +y, -y, +z, -z", based on the state diagram of FIG. 6.

[0086] When the receiving interface circuit receives a receiving state "-y" and the control code (CONTROL_CODE) indicates an A / C line exchange, the receiving state "-y" causes the flip-flop circuit (213_1) to output "101" as the receiving differential signal (Pres_AB, Pres_BC, Pres_CA) based on [Table 9]. For example, if the preceding differential signals (Prev_AB, Prev_BC, Prev_CA) are "100" corresponding to the wire state "+x," the symbol decoder (213_2) outputs "001," which corresponds to the transition from the wire state "+x" in the state diagram of FIG. 6 to the wire state "-y," as a symbol composed of three binary bits. Each state in the state diagram of FIG. 6 is replaced with a bit corresponding to the differential signal in Table 9 and used in the symbol decoder 213_2.

[0087] That is, the received antecedent state "+x" and received state "-y" due to the A / C line switch correspond to the wire antecedent state "-y" and received state "+x", respectively, in the absence of the line switch. If there is no line exchange, the symbol decoder 213_2 decodes the preceding state "-y" and the receiving state "+x" based on the state diagram of FIG. 5, and outputs the symbol "001". Therefore, when the control code (CONTROL_CODE) indicates an A / C line replacement, it is the same as the symbol "001" output in response to the transition from wire state "+x" to wire state "-y" in the state diagram of 6. Therefore, when the control code (CONTROL_CODE) instructs decoding based on A / C line switching, B / C line switching, or A / B line switching, the symbol decoder (213_2) performs decoding based on the state diagram of FIG. 6. When the control code (CONTROL_CODE) instructs decoding based on a change in each of the B / C / A lines of the A / B / C lines or a change in each of the C / A / B lines of the A / B / C lines, the symbol decoder 213_2 performs decoding based on the state diagram of FIG. 7.

[0088] FIG. 15 is a block diagram showing a schematic configuration of the decoder 213 according to another embodiment of FIG. Referring to FIG. 15, the decoder 213 includes a symbol decoder (213_3). The symbol decoder 213 receives the received differential signals (Pres_AB, Pres_BC, Pres_CA) and the preceding differential signals (Prev_AB, Prev_BC, Prev_CA) from the same receiver 211 and flip-flop circuit (213_1) as in FIG. In addition, the symbol interpreter (213_4) receives a control code (CONTROL_CODE).

[0089] The symbol decoder (213_3) according to the embodiment of the present invention includes a symbol interpreter (213_4). The symbol interpreter 213_4 converts the received differential signals (Pres_AB, Pres_BC, Pres_CA) and the preceding differential signals (Prev_AB, Prev_BC, Prev_CA) based on the control code (CONTROL_CODE) and outputs the converted signals to a first output line IN1 and a second output line IN2, respectively. For example, if the control code (CONTROL_CODE) indicates decoding based on A / C line switching, the symbol interpreter (213_4) converts each of the received differential signals (Pres_AB, Pres_BC, Pres_CA) and the preceding differential signals (Prev_AB, Prev_BC, Prev_CA) as shown in FIG. 15.

[0090] Referring to Table 10 below, which shows the symbol conversion relationship based on the A / C line exchange, when the received differential signal (Pres_AB, Pres_BC, Pres_CA) is “101” generated based on the receiving state “-y”, the symbol interpreter (213_4) converts it to “100” corresponding to the receiving state “+x” and outputs it to the first output line IN1. The decoding logic (DEC_LOGIC) calculates symbols (Rx_Flip, Rx_Rotation, Rx_Polarity) based on the current differential signals (Pres_AB, Pres_BC, Pres_CA) from which the line exchange has been restored and the previous differential signals (Prev_AB, Prev_BC, Prev_CA) based on the state diagram of Figure 5. Therefore, the decoding logic (DEC_LOGIC) of FIG. 15 differs from the decoding logic (DEC_LOGIC) of FIG. [Table 10]

[0091] The symbol interpreter (213_3) converts the received differential signals (Pres_AB, Pres_BC, Pres_CA) and the preceding differential signals (Prev_AB, Prev_BC, Prev_CA) by referring to FIG. 16 when the control code (CONTROL_CODE) indicates decoding based on A / C line swapping (A / C SWAP), when it indicates decoding based on A / B line swapping (A / B SWAP), or when it indicates decoding based on B / C line swapping (B / C SWAP). The symbol interpreter (213_4) converts the received differential signals (Pres_AB, Pres_BC, Pres_CA) and the preceding differential signals (Prev_AB, Prev_BC, Prev_CA) by referring to FIG. 16 when the control code (CONTROL_CODE) instructs decoding based on changes of the A line, B line, and C line to the B line, C line, and A line, respectively (A→B, B→C, C→A TRANSITION) and when the A line, B line, and C line instruct decoding based on changes of the A line, B line, and C line to the C line, A line, and B line, respectively (A→C, B→A, C→B TRANSITION). The symbol interpreters 213_3 and 213_4 can be implemented in various ways, such as a plurality of multiplexers or a table-type memory device.

[0092] FIG. 17 is a flowchart illustrating an operation method of a transmission-side communication interface circuit according to an embodiment of the present invention. The communications interface circuitry transmits data signals over data lanes provided on a plurality of three-phase wire links. In some embodiments, the data lanes are driven based on MIPI's C-PHY.

[0093] In step S110, the communication interface circuit processes input data into a packet data format. The communication interface circuit generates a payload based on input data, and inserts a header and a footer suitable for transmission before and after the payload, respectively, to generate transmission data in the form of packet data. In some embodiments, the communication interface circuit generates transmission data according to (CSI-2, DSI, DSI-2) as defined by the MIPI Alliance.

[0094] In step S120, the communication interface circuit encodes transmission data, which is packet data, and outputs a transmission state. The communication interface circuit calculates a transmission state based on the symbol to which the transmission data is mapped, the previous state, and the control code. The communication interface circuit maps the 16 binary bit data of the transmission data into seven symbols and then performs encoding. Each symbol includes a flip bit (Tx_Flip), a rotation bit (Tx_Rotation), and a polarity change bit (Tx_Polarity) that indicate the type of transition from a previous state to a transmit state based on the previous symbol. A symbol is therefore represented by 3 binary bits. The transmission states are wire states that define the signal levels of the three 3-phase wire links according to MIPI's C-PHY. The control code is a code that instructs an encoding change based on the coupling relationship of a plurality of three-phase wire links.

[0095] According to an embodiment, the communication interface circuit performs encoding differently according to the interchange of any two of the three three-phase wire links (A wire link, B wire link, C wire link) according to MIPI C-PHY based on the control code. For example, based on a provided control code, the same symbol is encoded into different wire states when the A-wire link and the C-wire link are interchanged, when the A-wire link and the B-wire link are interchanged, and when the B-wire link and the C-wire link are interchanged. In some embodiments, the communication interface circuit performs encoding differently according to changes in all wire links among the three 3-phase wire links according to MIPI C-PHY based on the control code.

[0096] The communication interface circuitry performs appropriate encoding of the changed coupling relationship of the communication link based on the control code indicating the coupling relationship change of the communication link. As a result, degradation of the communication channel can be reduced, and data signals can be transmitted stably. In addition, the communication interface circuit supports various interconnections between components through coupling terminal arrangements, thereby enabling stable transmission of data signals.

[0097] The communication interface circuit performs encoding according to state diagram 5 if the control code indicates that there is no exchange or change of the A / B / C lines. When the control code instructs the exchange of any two of the A / B / C lines, the communication interface circuit performs encoding based on the state diagram of FIG.

[0098] The communications interface circuitry encodes the symbols based on a control code that dictates the encoding based on the A / C line exchange. That is, the communications interface circuit encodes symbols to output transmission states of "-y, +y, -x, +x, -z, +z" in response to the receiving wire states "+x, -x, +y, -y, +z, -z" respectively. The communications interface circuitry encodes the symbols based on a control code that dictates the encoding based on the A / B line exchange. That is, the communications interface circuit encodes symbols to output transmission states of "-x, +x, -z, +z, -y, +y" in response to the receiving wire states "+x, -x, +y, -y, +z, -z" respectively. The communications interface circuitry encodes the symbols based on a control code that dictates the encoding based on the B / C line exchange. That is, the communications interface circuit encodes symbols to output transmission states of "-z, +z, -y, +y, -x, +x" in response to the receiving wire states of "+x, -x, +y, -y, +z, -z" respectively.

[0099] The communications interface circuitry encodes symbols on the A-lines, B-lines, and C-lines in that order based on control codes that direct encoding based on modifications to the B-lines, C-lines, and A-lines, respectively. That is, the communications interface circuit encodes symbols to output transmission states of "+y, -y, +z, -z, +x, -x" in response to the receiving wire states "+x, -x, +y, -y, +z, -z" respectively. The communications interface circuitry encodes symbols on the A-line, B-line, and C-line in that order based on control codes that direct encoding based on modifications to the C-line, A-line, and B-line, respectively. That is, the communications interface circuit encodes symbols to output transmission states of "+z, -z, +x, -x, +y, -y" in response to the receiving wire states of "+x, -x, +y, -y, +z, -z" respectively.

[0100] In step S130, the communication interface circuit drives the multiple three-phase wire links based on the transmission state to transmit data signals to data lanes provided on the three-phase wire links. The communication interface circuit generates a plurality of drive signals for driving three 3-phase wire links based on the MIPI C-PHY based on the transmission state. The communication interface circuit drives the multiple wire links based on the generated respective drive signals, regardless of changes in the coupling relationship of the multiple wire links. That is, in step S130, a transmission state is calculated appropriately for the changed coupling relationship of the plurality of wire links based on the control code, and the driving signals generated based on the transmission state directly drive each of the plurality of wire links based on their respective driving signals.

[0101] Meanwhile, what has been described above is a specific embodiment for carrying out the present invention. In addition to the above-described embodiments, the present invention also includes embodiments that can be simply modified or easily altered. In addition, the present invention includes techniques that can be easily modified and implemented using the embodiments. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined not only by the claims below, but also by equivalents to the claims of the present invention.

[0102] Any of the functional blocks shown in the figures and described above may be embodied in hardware including logic circuits, a hardware / software combination such as a processor executing software, or a processing circuit such as a combination of both. For example, the processing circuit may be, more specifically, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, an FPGA (Field Programmable Gate Array), an SoC (System on a Chip), a programmable logic device, a microprocessor, an ASIC (Custom Integrated Circuit), or the like.

[0103] The exemplary embodiments have been described above according to method steps illustrating the performance of and relationships between specified functions. The boundaries and sequences of such functional building blocks and method steps have been defined herein for convenience of explanation. Thus, alternative boundaries and sequences may be defined so long as the specified functions and relationships are appropriately performed. Accordingly, such alternate boundaries or sequences are within the scope and spirit of the claims.

[0104] Various exemplary embodiments herein may reference a variety of circuit elements including, but not limited to, capacitors, resistors, inductors, switches, amplifiers, comparators, filters, flip-flops, drivers, and transistors. Various other types of digital, analog, active, and / or manual components may be used to implement the exemplary embodiments. Various other transistor types may be used depending on, for example, the implementation, whether positive or negative logic is used, the manufacturing process used, etc. Additionally, unless specifically stated otherwise herein, various types of filters, comparators, switches, etc. may be included that may be used to implement example embodiments. [Explanation of symbols]

[0105] 100, 100_2 Transmission interface circuit 110 Protocol Hierarchy Circuit 120 Physical layer circuit 121 Mapping Circuit 123 Parallel-to-Serial Converter 125 Encoder 125_1 Symbol Encoder 125_2 Flip-flop circuit 127 Pre-driver control circuit 129 Driving Driver 200, 200_2 Receive interface circuit 310 Control circuit block (OUTIF) 320 Register

Claims

1. A protocol layer circuit for generating packet data based on input data; a physical layer circuit for encoding the packet data to output a transmission state and driving a data lane including a plurality of three-phase wire links based on the transmission state; the physical layer circuit includes an encoder for calculating the transmission state based on a previous state output from an encoder in a previous unit interval, a symbol to which the packet data is mapped, and a control code; The control code indicates an encoding change based on a coupling relationship of the plurality of three-phase wire links.

2. The physical layer circuit includes: a mapping circuit for mapping the packet data to the symbols; the encoder for calculating the transmission state based on the preceding state, the symbol, and the control code; A pre-driver control circuit that controls a plurality of driving drivers based on the transmission state; 2. The communication interface circuit according to claim 1, further comprising: a plurality of driving drivers for driving the plurality of three-phase wire links, respectively, under the control of the pre-driver control circuit.

3. 3. The communication interface circuit of claim 2, wherein an output of the pre-driver control circuit is provided directly to the plurality of driving drivers.

4. 2. The communication interface circuit according to claim 1, wherein the encoder receives the control code stored in an external register.

5. 2. The communication interface circuit according to claim 1, wherein the physical layer circuit is based on C-PHY of MIPI (Mobile Industry Processor Interface).

6. the plurality of three-phase wire links includes a first wire link, a second wire link, and a third wire link; the control code indicates an encoding change based on a swapping relationship between the first wire link and the third wire link; 6. The communication interface circuit of claim 5, wherein the encoder outputs the transmission states "-y, +y, -x, +x, -z, +z" in response to reception of wire states "+x, -x, +y, -y, +z, -z" based on the MIPI C-PHY at the receiving end.

7. the plurality of three phase wire links includes three three phase wire links, a first three phase wire link, a second three phase wire link, and a third three phase wire link; the control code indicates an encoding change based on a swapping relationship of any two of the three three-phase wire links; 6. The communication interface circuit of claim 5, wherein the encoder outputs the transmission state in which a letter is increased from the previous state and the polarity of the previous state is maintained in response to the symbol being a bit code "000".

8. the plurality of wire links includes three three phase wire links, a first three phase wire link, a second three phase wire link, and a third three phase wire link; the control code indicates an encoding change based on a swapping relationship of any two of the three three-phase wire links; 6. The communication interface circuit according to claim 5, wherein the encoder outputs the transmission state in which a letter is increased from the previous state and the polarity of the previous state is changed in response to the symbol being a bit code "001".

9. the plurality of wire links includes three three phase wire links, a first three phase wire link, a second three phase wire link, and a third three phase wire link; the control code indicates an encoding change based on a swapping relationship of any two of the three three-phase wire links; 6. The communication interface circuit of claim 5, wherein the encoder outputs the transmission state in which a letter is decreased from the previous state and the polarity of the previous state is maintained in response to the symbol being a bit code "010".

10. the plurality of wire links includes three three phase wire links, a first three phase wire link, a second three phase wire link, and a third three phase wire link; the control code indicates an encoding change based on a swapping relationship of any two of the three three-phase wire links; 6. The communication interface circuit according to claim 5, wherein the encoder outputs the transmission state in which a letter is decreased from the previous state and the polarity of the previous state is changed in response to the symbol being a bit code "011".

11. the plurality of wire links includes three three phase wire links, a first three phase wire link, a second three phase wire link, and a third three phase wire link; the control code indicates an encoding change based on a relationship of changing the first three-phase wire link to a second wire link of the three phases, changing the second three-phase wire link to the third three-phase wire link, and changing the third three-phase wire link to the first three-phase wire link; 6. The communication interface circuit of claim 5, wherein the encoder outputs the transmission states "+y, -y, +z, -z, +x, -x" in response to reception of wire states "+x, -x, +y, -y, +z, -z" based on the MIPI C-PHY at the receiving end.

12. the plurality of wire links includes three three phase wire links, a first three phase wire link, a second three phase wire link, and a third three phase wire link; the control code indicates an encoding change based on a relationship of changing the first three phase wire link to the third three phase wire link, changing the second three phase wire link to the first three phase wire link, and changing the third three phase wire link to the second three phase wire link; 6. The communication interface circuit of claim 5, wherein the encoder outputs the transmission states "+z, -z, +x, -x, +y, -y" in response to reception of wire states "+x, -x, +y, -y, +z, -z" based on the MIPI C-PHY at the receiving end.

13. the plurality of three phase wire links includes a first three phase wire link, a second three phase wire link, and a third three phase wire link; 6. The communication interface circuit of claim 5, wherein the encoder outputs different transmission states based on different control codes corresponding to the same wire states received at the receiving end based on the MIPI C-PHY.

14. a physical layer circuit that generates a plurality of differential signals based on a driving voltage of each of a plurality of three-phase wire links of a data lane, and outputs a symbol based on the plurality of differential signals; A protocol layer circuit for de-mapping the symbols and outputting data; the physical layer circuit includes a decoder that calculates the symbol based on a received differential signal based on the plurality of differential signals, a previous differential signal based on the plurality of differential signals of a previous unit interval, and a control code; 11. A communications interface circuit comprising: a first control code for controlling a first input of said first phase wire link and a second control code for controlling a second input of said first phase wire link;

15. 15. The communication interface circuit according to claim 14, wherein the physical layer circuit is based on C-PHY of the Mobile Industry Processor Interface (MIPI).

16. the plurality of three phase wire links includes a first three phase wire link, a second three phase wire link, and a third three phase wire link; the control code directs a decoding change based on a swapping relationship between the first three-phase wire link and a third three-phase wire link; 16. The communications interface circuit of claim 15, wherein the decoder includes a symbol interpreter that converts a plurality of differential signals corresponding to each of the received wire states "-y, +y, -x, +x, -z, +z" based on the MIPI C-PHY into a plurality of differential signals corresponding to each of the wire states "+x, -x, +y, -y, +z, -z."

17. generating packet data based on the input data; encoding the packet data to output a transmission state; and driving a data lane composed of a plurality of three-phase wire links based on the transmission state; The step of encoding the packet data and outputting a transmission state includes the step of computing the transmission state based on a previous state output in a previous unit interval, a symbol to which the packet data is mapped, and a control code; 11. A method of operating a communications interface circuit, comprising: the control code instructing an encoding change based on a coupling relationship of the plurality of three-phase wire links.

18. the plurality of three phase wire links includes a first three phase wire link, a second three phase wire link, and a third three phase wire link; 20. The method of claim 17, wherein the step of encoding the packet data and outputting the transmission states comprises the step of outputting different transmission states based on different control codes corresponding to a plurality of identical wire states received at a receiving end based on MIPI C-PHY.

19. Driving the data lanes comprises: generating a plurality of drive signals for driving a plurality of driving drivers based on the transmission states; and providing the plurality of drive signals directly to the plurality of drive drivers.

20. The data lanes are driven based on the C-PHY standard of the Mobile Industry Processor Interface (MIPI); the plurality of three-phase wire links includes three three-phase wire links; The symbol is made up of 3 binary bits, The step of encoding the packet data and outputting the transmission state includes: in response to the control code instructing an encoding change based on a swapping relationship between any two of the three three-phase wire links, If the intermediate bit of the symbol is "0", output the transmission state in which the character of the preceding state is increased; 20. The method of claim 17, further comprising the step of outputting the transmission state in which the character of the preceding state is reduced when the intermediate bit of the symbol is "1".

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