Semiconductor device

Abstract

To provide a transistor that uses an oxide semiconductor and that has good operating characteristics, and to provide a semiconductor device that has improved operating characteristics by using the transistor.SOLUTION: The transistor has such a configuration that one of a source electrode and a drain electrode of the transistor is surrounded by an annular gate electrode in a plan view. Alternatively, the transistor has such a configuration that one of the source electrode and the drain electrode of the transistor is surrounded by a channel formation region in a plan view. Thereby, the source electrode and the drain electrode are not electrically connected with each other via a parasitic channel generated at an end part of an island-like oxide semiconductor layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This generally refers to electro-optical devices, light-emitting display devices, semiconductor circuits, and electronic devices, all of which are semiconductor devices. be. [Background technology]

[0003] In recent years, metal oxide semiconductors that exhibit semiconducting properties have been used as materials for transistors. Metal oxides are used for various purposes. For example, Indium is used as a material for pixel electrodes in displays such as liquid crystal displays and EL displays. It is used in this way.

[0004] In addition, a transistor (thin film transistor) is formed using a semiconductor thin film formed on a substrate having an insulating surface. The technology of constructing thin film transistors (also called thin film transistors (TFTs)) is attracting attention. It is widely applied in electronic devices such as circuits (ICs) and image display devices (display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors. As another material, oxide semiconductors have been attracting attention.

[0005] Examples of metal oxides that exhibit semiconducting properties include tungsten oxide, tin oxide, and indium oxide. The channels are formed in metal oxides that exhibit semiconducting properties, such as aluminum and zinc oxide. For example, a transistor using indium as an active layer is already known. Amorphous oxide transistors containing In, Ga, and Zn Sta has been disclosed. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2006-165528 A [Patent Document 2] JP 2007-96055 A [Patent Document 3] JP 2007-123861 A Summary of the Invention [Problem to be solved by the invention]

[0007] It is known that oxygen vacancies in oxide semiconductors act as donors, and When an oxide semiconductor is used for the panel formation region, an oxide semiconductor layer with as few oxygen vacancies as possible should be used. However, it is preferable to use an oxide semiconductor having an island shape for forming a transistor. In the conductor layer, oxygen is easily released from its end portion.

[0008] In addition, in the process of forming the oxide semiconductor layer into an island shape, components of the etching gas (chlorine, fluorine, etc.) The oxide semiconductor layer is mixed with silicon, boron, hydrogen, or the like from its edge and becomes a donor in the oxide semiconductor layer. Therefore, in the island-shaped oxide semiconductor layer, a low-resistance region is formed at the edge and in the vicinity thereof. A parasitic channel of a transistor is easily formed in the low-resistance region. .

[0009] When a parasitic channel is generated at an end of the island-shaped oxide semiconductor layer, the transistor The source and drain of the transistor are connected, and an unintended current ("leakage") flows between the source and drain. Also, the off-state current of the transistor increases. This causes an increase in power consumption.

[0010] Thus, the parasitic channel causes the deterioration of the electrical characteristics of the transistor. For example, Normally-on transistors, increased threshold voltage variation, and stress-induced This can cause defects such as a shift in the threshold voltage.

[0011] In the transistor, the oxide semiconductor layer in a region overlapping with the gate A channel (the first The first channel is called the parasitic channel (also called the second channel). A channel can be formed.

[0012] In a transistor in which two types of channels can be formed independently, The connection relationship of the rain is as shown in the circuit in FIG. In the circuit, a variable resistor 1201 is connected in parallel between the source (S) and the drain (D). and resistor 1202. Here, variable resistor 1201 corresponds to the first channel. , the resistor 1202 corresponds to the second channel. The variable resistor 1201 and resistor 1202 are connected in series between the source (S) and drain (D). 02A, resistor 1202B is present.

[0013] For example, in digital circuits, transistors are often used as switches. Specifically, the formation of the first channel is determined by controlling the voltage between the gate and source. By selecting the input, the transistor is used as a switch. In the transistor in which the first channel is formed, whether the first channel is formed or not depends on Regardless, the source and drain may be electrically connected via a parasitic channel. In such a transistor, intentional switching control becomes difficult.

[0014] In addition to the region where the first channel is formed, the region where the second channel is formed In a transistor with overlapping gate electrodes, the gate and the source where the channels are formed are The threshold voltages between the two sources are often different. Typically, the former is formed before the channel is formed. The threshold voltage at which the latter channel is formed is higher than the threshold voltage at which the former channel is formed. The current drive capability of the first channel is higher than that of the second channel. When the voltage between the gate and source of the transistor in question is increased, The current between the drains changes in two stages. Specifically, a second channel is formed. The first step (increase in the current between the source and drain) occurs near the threshold voltage where It is confirmed that the second stage occurs in the vicinity of the threshold voltage at which the first channel is formed. A change (an increase in the current between the source and drain) is observed.

[0015] When such a transistor is used as a switch in a digital circuit, the switch The switch may undergo two-step changes, making it difficult to control the switching intentionally. .

[0016] In view of this, one embodiment of the present invention provides a transistor whose switching can be easily controlled. One of the challenges is to

[0017] One embodiment of the present invention is to provide a semiconductor device capable of suppressing the occurrence of a parasitic channel. Another object of the present invention is to provide a semiconductor device having good electrical characteristics. Another object of the present invention is to provide a highly reliable semiconductor device. [Means for solving the problem]

[0018] A transistor according to one embodiment of the disclosed invention includes an oxide semiconductor layer. The outer edge of the semiconductor device is covered with a first electrode, which is either a source electrode or a drain electrode. As a result, oxygen desorption from the outer edge of the oxide semiconductor layer is prevented, and generation of a parasitic channel is suppressed. It is possible.

[0019] Further, a gate insulating layer having a ring-shaped planar shape is provided over the oxide semiconductor layer. The second electrode, which is the other of the source electrode and the drain electrode, is formed on the It is surrounded by an annular gate electrode.

[0020] The channel formation region of a transistor is the region between the source electrode and the drain electrode. The oxide semiconductor layer is formed in a region overlapping with the gate electrode with a gate insulating layer interposed therebetween. The outer edge is covered by a first electrode, which is either a source electrode or a drain electrode. In other words, the channel formation region is not provided on the outer edge of the oxide semiconductor layer.

[0021] As described above, in one embodiment of the disclosed invention, the outer edge of the oxide semiconductor layer is The oxide semiconductor layer is covered with the drain electrode. In addition, the oxide semiconductor layer can be formed by the oxide semiconductor layer. By covering the edge with either the source electrode or the drain electrode, the oxygen on the outer edge of the oxide semiconductor layer is Not only that, but it also prevents the internal oxygen from escaping through the outer edge, forming a parasitic channel. The production of can be suppressed.

[0022] In one embodiment of the disclosed invention, the use of the transistor can improve operation characteristics. It is possible to provide a semiconductor device in which the improvement is achieved.

[0023] In one embodiment of the disclosed invention, a base insulating layer and an oxide film provided on the base insulating layer A semiconductor layer and a source electrode or a drain electrode covering at least a part of the outer edge of the oxide semiconductor layer. one of the source electrode and the drain electrode, the other of the source electrode and the drain electrode, the oxide semiconductor layer, a gate insulating layer covering one and the other of the source electrode or the drain electrode; a dielectric layer provided on the oxide semiconductor layer via an insulating layer, A gate electrode is provided so as to surround the other of the source electrode and the drain electrode. One of the electrodes is characterized in that it is provided so as to surround the gate electrode.

[0024] In one embodiment of the disclosed invention, a first insulating layer covering the gate insulating layer and the gate electrode a second insulating layer on the first insulating layer; and a source electrode or and an electrode electrically connected to the other of the drain electrodes.

[0025] In one embodiment of the disclosed invention, the oxide semiconductor layer has a rectangular planar shape. It is characterized by:

[0026] In one embodiment of the disclosed invention, the gate electrode has a planar shape that is annular. Let us assume that.

[0027] In one embodiment of the disclosed invention, a semiconductor device is provided on the base insulating layer, a first electrode having a material similar to that of the drain electrode; a gate insulating layer; and a gate electrode provided on the gate insulating layer and having a material similar to that of the gate electrode. The semiconductor device is characterized by having a capacitor element having a second electrode.

[0028] In plan view, one of the source electrode or the drain electrode of the transistor is surrounded by a gate electrode. By using the structure including the source electrode and the drain electrode, an end portion of the island-shaped oxide semiconductor layer can be formed. This configuration does not include this.

[0029] In addition, when viewed from above, one of the source electrode and the drain electrode of the transistor is a channel By surrounding the oxide semiconductor layer with the formation region, the end of the island-shaped oxide semiconductor layer is The structure is such that the electrode does not reach the

[0030] With this structure, the end portion of the island-shaped oxide semiconductor layer, in which a parasitic channel is likely to occur, Therefore, the island-shaped A parasitic channel formed at the edge of the oxide semiconductor layer causes the source and drain electrodes to be unintentionally connected. This can prevent the electrical connection from occurring without any problem.

[0031] In addition, by covering the edge of the island-shaped oxide semiconductor layer with a metal layer, This can reduce oxygen desorption from the oxide semiconductor layer, thereby suppressing a decrease in the resistance of the oxide semiconductor layer.

[0032] The planar shape of the island-shaped oxide semiconductor layer is not particularly limited, and may be a polygon, a circle, or a curved line. The gate electrode, source electrode, drain electrode, and so on may be formed in a shape that is intersected by a line or a shape that combines straight lines and curves. The planar shape of the inner electrode is similar.

[0033] In plan view, one of the source electrode or the drain electrode of the transistor is surrounded by a gate electrode. In the case of a configuration including the gate electrode, the gate electrode will be annular, but the annular shape is not limited to a circular or rectangular shape.

[0034] One embodiment of the present invention is a semiconductor device having a source electrode and a drain electrode over an island-shaped oxide semiconductor layer. an insulating layer on the oxide semiconductor layer, a source electrode, and a drain electrode; In a plan view, one of the source electrode and the drain electrode is surrounded by a gate electrode. It is characterized by being contained in

[0035] One embodiment of the present invention is a semiconductor device having a source electrode and a drain electrode over an island-shaped oxide semiconductor layer. an insulating layer on the oxide semiconductor layer, a source electrode, and a drain electrode; The island-shaped oxide semiconductor layer has a channel formation region in a region overlapping with the gate electrode. In a plan view, one of the source electrode and the drain electrode is surrounded by a channel forming region. It is characterized by being contained in

[0036] One embodiment of the present invention is a semiconductor device having a first insulating layer on a first wiring, and an island-shaped oxide film on the first insulating layer. a source electrode and a drain electrode on the island-shaped oxide semiconductor layer; One of the gate electrode and drain electrode is formed in an opening formed in the island-shaped oxide semiconductor layer and the first insulating layer. The insulating layer is electrically connected to the first wiring through the hole, and includes an island-shaped oxide semiconductor layer, a source electrode, and a drain electrode. A second insulating layer is provided on the drain electrode, and a gate electrode is provided on the second insulating layer. and one of the source electrode and the drain electrode is surrounded by a gate electrode. Let us assume that.

[0037] One embodiment of the present invention is a semiconductor device having a first insulating layer on a first wiring, and an island-shaped oxide film on the first insulating layer. a source electrode and a drain electrode on the island-shaped oxide semiconductor layer; One of the gate electrode and drain electrode is formed in an opening formed in the island-shaped oxide semiconductor layer and the first insulating layer. The insulating layer is electrically connected to the first wiring through the hole, and includes an island-shaped oxide semiconductor layer, a source electrode, and a drain electrode. A gate electrode is formed on the second insulating layer. The semiconductor layer has a channel formation region in a region overlapping with the gate electrode, and One of the source electrode and the drain electrode is surrounded by a channel forming region. do.

[0038] The gate electrode is formed so as to overlap at least one of the source electrode and the drain electrode. This is also fine.

[0039] One embodiment of the present invention disclosed in this specification is a semiconductor device having a ring-shaped gate electrode and a source electrode or a drain electrode. The present invention relates to a semiconductor device in which one of the in-electrodes is surrounded by the gate electrode.

[0040] One aspect of the present invention disclosed herein is a semiconductor device comprising a first electrode embedded in a first insulating layer and a first One surface of the island-shaped oxide semiconductor layer is in contact with an electrode, and the other surface of the island-shaped oxide semiconductor layer is in contact with an end portion of the island-shaped oxide semiconductor layer. A second electrode and a second insulating film formed to cover the island-shaped oxide semiconductor layer and the second electrode. a third electrode having an annular upper surface formed on the second insulating layer, the first electrode being the second electrode is formed on the outside of the third electrode, and the third electrode is formed on the inside of the first electrode. The semiconductor device is characterized by the above.

[0041] Note that the end portion of the island-shaped oxide semiconductor layer in this specification refers to an end portion of the island-shaped oxide semiconductor layer viewed from above. It means the outer edge of a conductor layer, and the same applies to side and end faces.

[0042] In the oxide semiconductor layer, a region that does not overlap with the second electrode and the third electrode is The low-resistance region of the oxide semiconductor layer is preferably a region to which impurities are added. The element is different from the component, and functions as a donor when added to the oxide semiconductor layer. It refers to the element that

[0043] Another aspect of the present invention disclosed in this specification is a first electrode embedded in a first insulating layer. an island-shaped oxide semiconductor layer having one surface in contact with the first electrode; a second electrode in contact with the insulating layer, and a second electrode formed to cover the island-shaped oxide semiconductor layer and the second electrode. a second insulating layer formed on the second insulating layer, and a third electrode having a ring-shaped upper surface formed on the second insulating layer; The third electrode overlaps with the first electrode and the second electrode. be.

[0044] It is preferable that the surface of the first insulating layer and the surface of the first electrode are continuous flat surfaces. stomach.

[0045] The first electrode has a semiconductor layer having a different band gap from that of the oxide semiconductor layer. By electrically connecting the semiconductor device, a highly functional semiconductor device can be formed.

[0046] An insulating layer containing aluminum oxide is formed on the second insulating layer and the third electrode. It is preferable that the above is done.

[0047] Another aspect of the present invention is an oxide semiconductor device having a first surface and a second surface that is a reverse surface of the first surface. A conductor layer, an insulating layer in contact with the oxide semiconductor layer on the first surface, and an oxide semiconductor layer formed on the insulating layer. a first conductive layer having a ring-shaped portion overlapping the conductor layer and the oxide semiconductor layer; a second conductive layer in contact with the oxide semiconductor layer on a first surface in a region inside the annular portion; a third conductive layer in contact with the oxide semiconductor layer on the second surface in the region outside the annular portion; and , the first conductive layer functions as a gate, and the second conductive layer functions as one of a source and a drain. a second conductive layer serving as the other of the source and drain of a transistor; It is.

[0048] In this specification, "annular" refers to a round shape like a ring (with a circular inner circumference and a circular outer circumference). However, the term "annular" includes any shape of a single object having an opening. For example, a polygon with circular or elliptical openings (with the inner circumference being circular or elliptical and the outer circumference being multi-sided) Circular or elliptical with a polygonal opening (with a polygonal inner periphery and a circular or elliptical outer periphery) elliptical), or polygonal with polygonal openings (inner circumference is polygonal, outer circumference is polygonal) ) or part of the inner circumference is curved and the rest is a broken line, and part of the outer circumference is curved and the rest is a broken line All of these shapes are included in the "annular" shape. Effect of the Invention

[0049] According to one embodiment of the present invention, a transistor capable of suppressing the occurrence of a parasitic channel can be obtained. do.

[0050] According to one embodiment of the present invention, a transistor that is less susceptible to the influence of a parasitic channel can be obtained. do.

[0051] According to one embodiment of the present invention, a transistor whose switching can be easily controlled can be provided. .

[0052] According to one embodiment of the present invention, a transistor with favorable operating characteristics (electrical characteristics) can be provided. Furthermore, by using the transistor, a semiconductor device having improved operating characteristics can be obtained. can be provided.

[0053] According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. [Brief description of the drawings]

[0054] [Figure 1] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Diagram 2] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Diagram 3] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 4] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Diagram 5] 1A to 1C are top views illustrating a manufacturing process of a semiconductor device. [Figure 6] 1A to 1C are top views illustrating a manufacturing process of a semiconductor device. [Figure 7] 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 8] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 9] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 10] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 11] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 12] 1A to 1C are top views illustrating a method for manufacturing a semiconductor device. [Figure 13] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 14] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 15] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 16] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 17] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 18] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 19] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 20] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 21] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 22] FIG. 1 is a top view illustrating one embodiment of a semiconductor device. [Diagram 23] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 24] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Diagram 25] 1A to 1C are diagrams illustrating an electrode structure of a semiconductor device. [Figure 26] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 27] 1A and 1B are a top view and a cross-sectional view illustrating a manufacturing process of a semiconductor device. [Figure 28] 1A and 1B are a top view and a cross-sectional view illustrating a manufacturing process of a semiconductor device. [Figure 29] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Diagram 30] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Diagram 31] 1A to 1C are a top view, a cross-sectional view, and a circuit diagram illustrating one embodiment of a semiconductor device. [Diagram 32] FIG. 1 is a perspective view illustrating one embodiment of a semiconductor device. [Diagram 33] 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Diagram 34] 1A to 1C are a top view, a cross-sectional view, and a circuit diagram illustrating one embodiment of a semiconductor device. [Diagram 35] 1A and 1B are a circuit diagram and a perspective view illustrating one embodiment of a semiconductor device. [Diagram 36] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 37] 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 38] 1A and 1B are a cross-sectional view and a circuit diagram illustrating one embodiment of a semiconductor device. [Figure 39] 1A and 1B are a circuit diagram and a perspective view illustrating one embodiment of a semiconductor device. [Diagram 40] 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Diagram 41] 1A and 1B are a circuit diagram and a perspective view illustrating one embodiment of a semiconductor device. [Diagram 42] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Diagram 43] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Diagram 44] FIG. 1 is a circuit diagram illustrating one embodiment of a semiconductor device. [Diagram 45] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 46] FIG. 1 is a block diagram illustrating one embodiment of a semiconductor device. [Figure 47] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 48] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 49] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 50] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 51] 1A to 1C are diagrams illustrating examples of electronic devices. [Figure 52] 1A to 1C are diagrams illustrating examples of electronic devices. [Figure 53] 1A to 1C are diagrams illustrating examples of electronic devices. [Figure 54] FIG. 1 is a circuit diagram showing the connection relationship between a source and a drain. [Figure 55] 1A and 1B are a top view and a cross-sectional view illustrating a conventional example. [Figure 56] Model diagram used to calculate the transfer of excess oxygen. [Figure 57] Calculation results for the model diagram in Figure 56. [Figure 58] A model used to calculate the movement of oxygen vacancies. [Figure 59] Calculation results for the model diagram in Figure 58. [Figure 60] 1A and 1B are a top view and a cross-sectional view illustrating the structure of an analytical sample. [Figure 61] FIG. 1 shows the results of TDS analysis. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0055] The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention is not limited to the above embodiment, and various changes and modifications may be made in the form and details without departing from the spirit and scope of the present invention. It will be easily understood by those skilled in the art that the above-mentioned invention can be obtained by the following embodiments. The present invention should not be construed as being limited to the contents described below. The same reference numerals are used in different drawings to indicate the same parts or parts having similar functions. A repeated explanation will be omitted.

[0056] In this specification, the end portion of the island-shaped oxide semiconductor layer refers to a plane of the island-shaped oxide semiconductor layer. It means the outer edge from the perspective, and the same applies to sides and end faces.

[0057] In addition, ordinal numbers such as "first," "second," and "third" in this specification are intended to avoid confusion of components. The numbers are added to avoid confusion and are not intended to be limiting.

[0058] In addition, the position, size, range, etc. of each component shown in the drawings are not necessarily the same as in the actual embodiment, for ease of understanding. Therefore, the disclosed invention may not necessarily represent the actual position, size, range, etc. The present invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0059] In addition, the functions of the "source" and "drain" of a transistor are different for transistors of different polarities. When a current flow direction is changed during circuit operation, the circuit is switched. For this reason, in this specification, terms including "source" and "drain" are used They can be used interchangeably.

[0060] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wire." In addition, the term "electrode" or "wiring" may be used to refer to the plural "electrodes" or "wirings". This also includes cases where the "line" is formed as a single unit.

[0061] In order to make the drawings easier to understand, some components may be omitted from the top view. There is a match.

[0062] First, the configuration of a conventional transistor 9910 will be described with reference to FIG. 55(B) is a plan view (top view) of a conventional transistor 9910. 55(A) is a cross-sectional view of a portion indicated by a chain line T1-T2 in FIG. FIG. 55(C) is a cross-sectional view of the portion indicated by the chain line T3-T4 in FIG. 55(A). 55C illustrates a cross section along an end portion of the oxide semiconductor layer 9904.

[0063] A conventional transistor 9910 shown in FIG. 55 has an insulating layer 9903 formed on a substrate 9901. An oxide semiconductor layer 9904 is formed over the insulating layer 9903. A source electrode 9905 and a drain electrode 9906 are formed on the oxide semiconductor layer 9904 , An insulating layer 9907 is formed on the source electrode 9905 and the drain electrode 9906. A gate electrode 9908 is formed at a position overlapping with an oxide semiconductor layer 9904 on the gate electrode 9907. The oxide semiconductor layer 9904 has a channel formation region 9904a and a low resistance The oxide semiconductor layer 9904 has a low resistance region 9904b and a low resistance region 9904c. The region overlapping with the gate electrode 9908 becomes a channel forming region 9904a.

[0064] 55(B) and 55(C) are diagrams showing the structure of a conventional transistor 9910 along the channel length direction. FIG. 55(B) shows a cross section of a conventional transistor 9910 near its center. FIG. 55(C) shows a conventional transistor 9910 with a source electrode 9905 and a drain electrode 9906. 9 shows a cross section of an end portion of an oxide semiconductor layer 9904 that reaches an inner electrode 9906.

[0065] When the transistor 9910 is in an off state, a channel is formed in the channel formation region 9904a. Therefore, the source electrode 9905 and the drain electrode 9906 are electrically isolated. However, if a parasitic channel due to oxygen vacancies occurs at an end of the oxide semiconductor layer 9904, As shown in FIG. 55(C), the source electrode 9905 and the drain electrode 9906 are connected to each other through a parasitic channel. 906 are electrically connected, and a leakage current is generated between the source electrode 9905 and the drain electrode 9906. The flow of 9911 will flow.

[0066] Leakage current 9911 causes problems such as increased power consumption and a negative shift in threshold voltage. This causes the electrical characteristics of the transistor to deteriorate. The size of the parasitic channel also varies depending on the degree of oxygen vacancy. This causes the electrical characteristics of the transistor to vary. The oxygen vacancies occurring at the edge of the oxide semiconductor layer 9904 are a cause of deterioration in the reliability of the transistor. It can also be a cause.

[0067] (Embodiment 1) An example of a structure of a semiconductor device according to this embodiment will be described with reference to the drawings. 1A is a top view of a transistor 110 and a capacitor 111 according to an embodiment of the present invention; FIG. 1(C) is a cross-sectional view taken along line A1-A2 in the top view shown in FIG. 1(A). FIG. 1(D) is a cross-sectional view taken along line B1-B2 in the top view shown in FIG. 1(A). FIG. 2 is a cross-sectional view taken along line C1-C2 in the top view.

[0068] The transistor 110 illustrated in FIGS. 1A, 1B, and 1C includes a base insulating layer 10. 1, an oxide semiconductor layer 102 is formed on the oxide semiconductor layer 102, and a source electrode or a drain electrode is formed on the oxide semiconductor layer 102. Electrode 104 functions as one of the source and drain electrodes, The transistor 110 has an oxide semiconductor layer 102, an electrode 108, and a A gate insulating layer 103 is provided over the transistor 104 and the electrode 108. 110 is a gate electrode 105 on the oxide semiconductor layer 102 via a gate insulating layer 103. A first insulating layer 107 is formed to cover the gate insulating layer 103 and the gate electrode 105. and a second insulating layer 109 are laminated on the second insulating layer 109. Through an opening provided in the insulating layer 109, the first insulating layer 107, and the gate insulating layer 103, An electrode 106 is formed which is electrically connected to the electrode 108 .

[0069] As shown in FIG. 1A, in the transistor 110, The edge is covered with an electrode 104 which functions as either a source or drain electrode. Further, a gate insulating layer 103 is provided over the oxide semiconductor layer 102, and a gate insulating layer 103 is provided between the gate insulating layer 103 and the oxide semiconductor layer 102. A gate electrode 105 is formed on the surface of the semiconductor substrate 101. The other of the source electrode and the drain electrode, electrode 102, is formed on the semiconductor substrate 101. The outside of the electrode 108 is surrounded by a ring-shaped gate electrode 105. The gate electrode 105 is annular, and the outside of the gate electrode 105 is connected to one of the source electrode and the drain electrode. It is surrounded by an electrode 104 which acts as a counter electrode.

[0070] The channel forming region of the transistor 110 is connected to the electrodes 10 which are the source electrode and the drain electrode. 4 and the electrode 108, the gate electrode 105 is disposed with the gate insulating layer 103 therebetween. The outer edge of the oxide semiconductor layer 102 is formed in a region overlapping with a source electrode or a drain electrode. Since the channel forming region is covered by the electrode 104, which is one of the electrodes, the oxide semiconductor It is not provided on the outer edge of the conductor layer 102 .

[0071] Therefore, in this embodiment, the source By covering either the drain or the gate electrode, the occurrence of a parasitic channel can be suppressed. Therefore, a transistor capable of being used can be obtained.

[0072] The capacitor 111 shown in FIG. 1A, FIG. 1B, and FIG. The electrodes 104 and 108 are made of the same material and in the same process as the electrodes 114 and 116. The capacitor 111 has a gate insulating layer 103 provided on the electrode 114. The gate insulating layer 103 is sandwiched between the electrode 115 and the gate insulating layer 103. The electrode 115 is The electrodes 114 and 115 are formed of the same material and in the same process as the gate electrode 105. The gate insulating layer 103 functions as a dielectric. A first insulating layer 107 and a second insulating layer 108 are formed over the gate insulating layer 103 and the electrode 115. An edge layer 109 is deposited.

[0073] As described above, the electrode 114, which is one of a pair of electrodes of the capacitor 111, is The capacitor element 111 is formed of the same material and in the same process as the electrode 108. The other electrode 115 of the capacitor 111 is a thin insulating layer 103. The gate electrode 105 is formed of the same material and in the same process as the gate electrode 105. The transistor 110 and the capacitor element 111 can be fabricated on the same plane. By forming the capacitor element 111 on the same plane, the number of steps for manufacturing the semiconductor device can be reduced. This makes it possible to increase productivity.

[0074] Note that in this embodiment, the planar shape of the oxide semiconductor layer 102 as shown in FIG. The planar shape of the oxide semiconductor layer 102 is rectangular, but the shape is not limited thereto. The shape may be a polygon other than a rectangle (for example, a triangle) or a circle. This also includes the shape.

[0075] In addition, in the oxide semiconductor layer 102, a layer functioning as one of a source electrode and a drain electrode The region overlapping the pole 104 functions as either a source region or a drain region. The oxide semiconductor layer 102 includes an electrode 1 functioning as the other of the source electrode and the drain electrode. The region overlapping with 08 functions as the other of the source region and the drain region.

[0076] In a manufacturing process described later, the oxide semiconductor layer 102 is provided with a material for changing the conductivity of the oxide semiconductor. In the case where the impurity element is not added, the region between the source region and the channel forming region and An offset region is provided between the drain region and the channel forming region. The channel formation region, source region, drain region, and offset region are formed by self-alignment. By providing an offset region, the parasitic capacitance between the gate electrode and the source electrode is reduced. It is also possible to reduce the amount of parasitic capacitance between the gate electrode and the drain electrode. The length of the channel forming region, which is the distance that carriers flow (channel The length (also referred to as the thickness) is preferably less than 60 nm.

[0077] In addition, the channel formation region is formed by self-alignment, which allows for miniaturization of transistors. It is easy to make a semiconductor, has high on-characteristics (e.g., on-current and field-effect mobility), and enables high-speed operation. do.

[0078] On the other hand, in a manufacturing process described later, the oxide semiconductor layer 102 is masked with a gate electrode 105. When an impurity element that changes the conductivity of an oxide semiconductor is added, between the drain region and the channel forming region, and between the drain region and the channel forming region. When the low resistance region is formed, the transistor 110 This reduces the on-resistance and improves the operating speed.

[0079] Also, as in the transistor 112 shown in FIG. 2, the gate electrode 135 is a source electrode and a drain electrode. When the electrodes 104 and 108 overlap, an offset region is not formed. In addition, in the transistor 112 shown in FIG. and between the drain region and the channel forming region. Since it is not possible to add it, a low resistance region is not formed.

[0080] Note that FIG. 2A is a top view of the transistor 112 and the capacitor 111 of this embodiment. FIG. 2B is a cross-sectional view taken along line A3-A4 in the top view shown in FIG. FIG. 2(C) is a cross-sectional view taken along line B3-B4 in the top view shown in FIG. 2(A). FIG. 2(D) is a cross-sectional view taken along line C3-C4 in the top view shown in FIG. For ease of understanding, some components are omitted in FIG. 2(A).

[0081] Although not shown in the present embodiment, a transistor 110 is provided below the base insulating layer 101. A semiconductor device having a different semiconductor device, for example, a semiconductor layer having a different band gap from an oxide semiconductor layer The semiconductor device may include a transistor.

[0082] The insulating underlayer 101 is formed by stacking a first insulating underlayer 101 and a second insulating underlayer 102 in the order from the side farthest from the oxide semiconductor layer 102. The first insulating underlayer 101a and the second insulating underlayer 101b are laminated together. 1a is a layer in which an element contained in a semiconductor device provided below the base insulating layer 101 is formed later. The insulating film 104 is provided to prevent the oxide semiconductor layer 102 from being mixed with the oxide semiconductor layer 102 .

[0083] The first base insulating layer 101a has a blocking effect that suppresses release of oxygen from the oxide semiconductor layer 102. It functions as a coating layer.

[0084] In particular, the first insulating underlayer 101a is free of impurities such as hydrogen, moisture, hydrides, or hydroxides. It is preferable to use a material having a barrier property against oxygen or a material having a barrier property against the first insulating underlayer 1. By applying a material with barrier properties to 01a, it is possible to prevent the intrusion of impurities from the outside. Furthermore, release of oxygen from the oxide semiconductor layer 102 can be prevented.

[0085] The first insulating underlayer 101a is a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a nitride film, or the like. Silicon oxide, aluminum oxide, aluminum nitride, aluminum oxide nitride, oxynitride Select from films containing aluminum, hafnium oxide, gallium oxide, or a mixture of these materials. The laminate may be of single layer or laminate construction.

[0086] Silicon oxynitride is a material whose composition contains more oxygen than nitrogen. The concentration ranges are 55-65 atomic % for oxygen, 1-20 atomic % for nitrogen, and 25- 35 atomic %, hydrogen in the range of 0.1 to 10 atomic %, so that the total is 100 atomic % The term "silicon nitride oxide film" refers to a film containing each element at a given concentration. , the nitrogen content is higher than the oxygen content, with the oxygen concentration ranging from 15 to 30 atomic %; Nitrogen is in the range of 20 to 35 atomic %, Si is in the range of 25 to 35 atomic %, and hydrogen is in the range of 15 to 25 atomic %. It refers to a material that contains each element at any concentration so that the total amount is 100 atomic %.

[0087] The second insulating underlayer 101b may be made of the same material as the first insulating underlayer 101a. The second insulating underlayer 101b is a region containing oxygen exceeding the stoichiometric composition (hereinafter, referred to as an oxygen excess region). The second base insulating layer 101b has oxygen exceeding the stoichiometric composition. If the second insulating underlayer 101b contains excess oxygen, the oxide film formed later may be formed. This is preferable because it can compensate for oxygen deficiencies in the organic semiconductor layer 102. In the case where the layer 101b has a stacked structure, at least a layer in contact with the oxide semiconductor layer 102 is an oxide semiconductor layer. In order to provide the second insulating underlayer 101b with an oxygen excess region, For example, the second base insulating layer 101b may be formed in an oxygen atmosphere. The second insulating underlayer 101b after the deposition is doped with oxygen (at least oxygen radicals, oxygen atoms, oxygen The oxygen excess region may be formed by implanting oxygen ions. These include ion implantation, ion doping, plasma immersion ion implantation, etc. For example, deposition method, plasma treatment, etc. can be used.

[0088] The oxide semiconductor layer 102 may have a single-layer structure or a stacked-layer structure. The oxide semiconductor layer 102 may have either an amorphous structure or a crystalline structure. In the case where the oxide semiconductor layer 102 has an amorphous structure, The oxide semiconductor layer may be subjected to heat treatment to become a crystalline oxide semiconductor layer. The temperature of the heat treatment for crystallizing the oxide semiconductor layer is 250° C. or higher and 700° C. or lower, preferably. is 400°C or higher, more preferably 500°C or higher, and further preferably 550°C or higher. Note that this heat treatment may also serve as another heat treatment in the manufacturing process.

[0089] The oxide semiconductor layer 102 is formed by depositing an oxide semiconductor film over the base insulating layer 101 and then depositing a The oxide semiconductor film may be processed into a predetermined shape.

[0090] The oxide semiconductor film is formed by a sputtering method, MBE (Molecular Beam Epitaxy), or the like. eam epitaxy) method, CVD method, pulsed laser deposition method, ALD (Atomic In addition, the oxide may be formed by a method such as a layer deposition method. The semiconductor film is formed by setting multiple substrate surfaces roughly perpendicular to the sputtering target surface. Alternatively, the film may be formed by using a sputtering apparatus that performs film formation in a state where the film is heated.

[0091] When the oxide semiconductor film is formed, the hydrogen concentration in the oxide semiconductor film is reduced as much as possible. In order to reduce the hydrogen concentration, for example, a sputtering method is used. When forming a film, hydrogen is used as the atmospheric gas supplied to the film forming chamber of the sputtering device. A high-purity rare gas (typically Al) from which impurities such as water, hydroxyl groups, or hydrides have been removed. Gases such as argon, oxygen, and mixtures of rare gases and oxygen are appropriately used.

[0092] In addition, the residual moisture in the film formation chamber is removed and a sputtering gas from which hydrogen and moisture have been removed is introduced. By forming the oxide semiconductor film in this manner, the hydrogen concentration in the formed oxide semiconductor film can be reduced. In order to remove the residual moisture in the deposition chamber, an adsorption type vacuum pump, for example, a cryopump, is used. It is preferable to use a pump, an ion pump, or a titanium sublimation pump. A cryopump may be a molecular pump with a cold trap added. For example, hydrogen molecules, water (H2O) and other compounds containing hydrogen atoms (preferably compounds containing carbon atoms) Since the pumping capacity of the cryopump is high, the film is formed in the deposition chamber evacuated by the cryopump. In addition, the concentration of impurities contained in the oxide semiconductor film can be reduced.

[0093] In addition, when the oxide semiconductor film is formed by a sputtering method, a metal oxide The relative density (filling rate) of the target is 90% or more and 100% or less, preferably 95% or more and 99% or less. The relative density of the metal oxide target is high, so the film is The oxide semiconductor film can be a dense film.

[0094] If possible, the oxide semiconductor film is formed while the base insulating layer 101 is kept at a high temperature. This is also effective in reducing the concentration of impurities that may be contained in the oxide semiconductor film. The temperature to which the base insulating layer 101 is heated may be set to 150° C. or more and 450° C. or less. Preferably, the heating temperature is set to 200° C. or more and 350° C. or less. By heating 101 at a high temperature, a crystalline oxide semiconductor film can be formed.

[0095] The oxide semiconductor used for the oxide semiconductor film is at least indium (In). It is preferable that the alloy contains In and zinc (Zn). It is particularly preferable that the alloy contains In and Zn. A stabilizer for reducing variations in electrical characteristics of a transistor using the oxide semiconductor In addition to these, it is preferable to have gallium (Ga) as a stabilizer. It is preferable to use tin (Sn) as the stabilizer. It is preferable to use aluminum (Al) as a stabilizer. It is preferable that the stabilizer contains zirconium (Zr). is preferred.

[0096] Other stabilizers include the lanthanides lanthanum (La) and cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Ho, Erbium, Thulium, Ytterbium, Ru The element may contain one or more of the elements tetraethynyl (Te) and tetraethynyl (Lu).

[0097] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and oxides of binary metals. In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, ternary metal oxides In-Ga-Zn oxide (also written as IGZO), In-Al-Zn oxide Oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides oxides, Sn-Al-Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides In-Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides , In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide, I n-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In -Lu-Zn ​​oxides, In-Sn-Ga-Zn oxides, which are oxides of quaternary metals, I n-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al- Zn-based oxide, In-Sn-Hf-Zn-based oxide, In-Hf-Al-Zn-based oxide are used. There can be.

[0098] Here, for example, the In-Ga-Zn oxide is an oxide of indium (In), gallium (Ga ), and zinc (Zn) are included in the oxide. The ratio of In, Ga, and Zn does not matter. Moreover, metal elements other than In, Ga, and Zn may be contained.

[0099] The oxide semiconductor film has the chemical formula InMO3(ZnO) m A thin film expressed as (m>0) Here, M is selected from Sn, Zn, Ga, Al, Mn and Co. The metal element or elements are also shown. In2SnO 5(ZnO) n Materials expressed as (n>0) may also be used.

[0100] For example, the atomic number of In:Ga:Zn=1:1:1 or In:Ga:Zn=2:2:1 In-Ga-Zn oxides having the same composition or oxides having a similar composition can be used. is In:Sn:Zn=1:1:1, In:Sn:Zn=2:1:3 or In:Sn In-Sn-Zn oxides with an atomic ratio of In:Zn=2:1:5 and oxides with similar compositions It is recommended to use.

[0101] However, the present invention is not limited to these, and may be applied to any desired transistor electrical characteristics (field effect mobility, threshold voltage, etc.). The appropriate composition should be used according to the required voltage, voltage variation, etc. In order to obtain the electrical properties, the carrier concentration, impurity concentration, defect density, atomic ratio of metal elements to oxygen, It is preferable that the interatomic distance, density, etc. are appropriate.

[0102] For example, it is relatively easy to obtain high field effect mobility in In-Sn-Zn oxides. However, in the case of In-Ga-Zn oxides, the electrical conductivity can be improved by reducing the defect density in the bulk. The field effect can increase mobility.

[0103] For example, the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c(a+b+ c=1) and oxides with an atomic ratio of In:Ga:Zn=A:B:C (A+B+C=1) The oxide compositions are close to each other if a, b, and c are (a-A) 2 +(b-B) 2 +(c-C) 2 ≦r 2 The above condition is satisfied, and r can be set to, for example, 0.05. The same is true for other oxides. .

[0104] Note that the oxide semiconductor film is formed under conditions in which a large amount of oxygen is contained (for example, 100% oxygen). The film is formed by sputtering in an atmosphere containing 00% oxygen. (Preferably, the oxide semiconductor has an oxygen content of 100% or less with respect to the stoichiometric composition in a crystalline state.) It is preferable to use a membrane having an excess area.

[0105] The oxide semiconductor film is formed using a sputtering gas that contains hydrogen, water, or a hydroxyl group. Alternatively, it is preferable to use a high-purity gas from which impurities such as hydrides have been removed.

[0106] Note that the oxide semiconductor film may be a single crystal, a polycrystalline (also referred to as polycrystal), a microcrystalline, or a The material can be in a state such as amorphous or non-crystalline.

[0107] Since it is relatively easy to obtain a flat surface for an amorphous oxide semiconductor, Transistors using this material can reduce interface scattering during operation, and can be manufactured relatively easily and High field effect mobility can be obtained.

[0108] In addition, in a crystalline oxide semiconductor, defects in the bulk can be further reduced, and the surface By improving the flatness of the oxide semiconductor film, the transistor using the crystalline oxide semiconductor can be formed into an amorphous It is possible to obtain a field-effect mobility higher than that of a transistor using an oxide semiconductor in a base state. In order to improve the flatness of the surface, it is preferable to form an oxide semiconductor on a flat surface. Specifically, the average surface roughness (Ra) is 0.15 nm or less, preferably 0.1 nm or less. It is preferable to form it on the surface.

[0109] Note that Ra is defined in JIS B0601:2001 (ISO4287:1997). This is a three-dimensional extension of the arithmetic mean roughness, which is currently used, so that it can be applied to curved surfaces. It can be expressed as "the average of the absolute values ​​of the deviation from the specified surface to the surface" and is defined by the following formula (1). can be.

[0110]

number

[0111] Here, the specified surface is the surface to be measured for roughness, and has coordinates (x1, y1, f(x1, y 1)),(x1,y2,f(x1,y2)),(x2,y1,f(x2,y1)),(x The specified surface is the quadrangular area represented by the four points (x2, y2, f(x2, y2)) and the specified surface is the xy plane. The area of ​​the projected rectangle is S0, and the height of the reference plane (the average height of the specified plane) is Z0. was measured using an atomic force microscope (AFM). It is possible to determine

[0112] In addition, when an In-Zn oxide material is used as the oxide semiconductor, the atomic ratio is In / Zn=0.5 or more and 50 or less, preferably In / Zn=1 or more and 20 or less, and more preferably The atomic ratio of In / Zn is set to 1.5 or more and 15 or less. The field effect mobility of the transistor can be improved by the number of atoms of the compound. When the ratio is In:Zn:O=X:Y:Z, Z>1.5X+Y.

[0113] The oxide semiconductor film may have, for example, a non-single crystal structure. Axis Aligned Crystal), polycrystalline, microcrystalline, and amorphous. Crystalline crystals have a higher defect level density than microcrystalline and CAAC. The density of defect states is high. xis Aligned Crystalline Oxide Semiconductor It is called tor.

[0114] The oxide semiconductor film may include, for example, a CAAC-OS. The c-axis is oriented, and the a-axis and / or b-axis are not macroscopically aligned.

[0115] The oxide semiconductor film may have, for example, microcrystals. The microcrystalline oxide semiconductor film has a thickness of, for example, 1 nm to 10 nm. The film contains microcrystals (also called nanocrystals) of about 100 nm in size. Alternatively, the film contains microcrystalline oxide semiconductor. The film is, for example, an oxide having a crystalline-amorphous mixed phase structure with a crystalline portion of 1 nm or more and less than 10 nm. It has a semiconductor.

[0116] The oxide semiconductor film may be, for example, amorphous. The amorphous oxide semiconductor film has, for example, a disordered atomic arrangement. Alternatively, the amorphous oxide semiconductor film is, for example, completely amorphous. The oxide semiconductor has no crystal parts.

[0117] Note that the oxide semiconductor film may be a CAAC-OS film, a microcrystalline oxide semiconductor film, or an amorphous oxide semiconductor film. The mixed film may be a film having, for example, an amorphous oxide semiconductor region and a microcrystalline oxide semiconductor region. The mixed film has a semiconductor region and a CAAC-OS region. A stack of an oxide semiconductor region, a microcrystalline oxide semiconductor region, and a CAAC-OS region. The structure may be

[0118] Note that the oxide semiconductor film may be, for example, single crystal.

[0119] The oxide semiconductor film has a plurality of crystal parts, and the c-axes of the crystal parts are aligned along a normal vector of a surface on which the crystal parts are formed. It is preferable that the crystal orientation of the crystals is parallel to the normal vector of the surface. The directions of the a-axis and the b-axis may be different between the oxide semiconductor films. An example is a CAAC-OS film.

[0120] The CAAC-OS film is not completely amorphous. For example, the CAAC-OS film has crystalline and The oxide semiconductor has a crystalline-amorphous mixed phase structure including an amorphous portion. The size of the electrodes is often within a cube with one side less than 100 nm. Transmission Electron Microscope (TEM) In the image of e), the boundary between the amorphous and crystalline parts in the CAAC-OS film and the crystalline part are clearly visible. The boundary between the crystal and the grains is not clear. Therefore, the CAAC-OS film has no grain boundary. In this way, the decrease in electron mobility caused by grain boundaries is suppressed.

[0121] The crystal parts included in the CAAC-OS film have, for example, a c-axis that is perpendicular to the normal to the surface on which the CAAC-OS film is formed. Aligned in a direction parallel to the line vector or the surface normal vector and perpendicular to the ab plane When viewed from the normal direction, the metal atoms are arranged in a triangular or hexagonal shape, and when viewed from the direction perpendicular to the c-axis, Metal atoms are arranged in layers, or metal atoms and oxygen atoms are arranged in layers. The directions of the a-axis and the b-axis may be different between the two. When describing it as straight, it is also in the range of 80° to 100°, preferably 85° to 95°. In addition, when simply describing it as parallel, it is -10° or more and 10° or less, and preferably This also includes the range of -5° to 5°.

[0122] In the CAAC-OS film, the distribution of the crystal parts may not be uniform. In the process of forming the C-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, The proportion of crystalline parts may be higher near the surface than near the growth surface. By adding impurities to the AC-OS film, the crystalline part becomes amorphous in the impurity-added region. It may also be pawned.

[0123] The c-axis of the crystal part in the CAAC-OS film is the normal vector of the surface on which the CAAC-OS film is formed. The shape of the CAAC-OS film is Depending on the shape (cross-sectional shape of the surface to be formed or cross-sectional shape of the surface), The c-axis of the crystal is the normal vector of the surface on which the CAAC-OS film is formed. The crystals are aligned parallel to the normal vector of the crystal or surface. or by subjecting the film to a crystallization treatment such as a heat treatment after the film is formed. .

[0124] The electrical characteristics of transistors using CAAC-OS films change when exposed to visible or ultraviolet light. Therefore, the transistor has high reliability.

[0125] Note that part of oxygen contained in the oxide semiconductor may be replaced with nitrogen.

[0126] Even if a planarization treatment is performed on the surface of the oxide semiconductor film before the oxide semiconductor film is formed, The planarization process is not particularly limited, but may be a polishing process (e.g., chemical mechanical polishing). ), dry etching treatment, or plasma treatment can be used.

[0127] The plasma treatment may be, for example, a reverse sputtering treatment in which argon gas is introduced to generate plasma. Reverse sputtering is a process in which RF is applied to the substrate side in an argon atmosphere. This method involves applying voltage using a power supply to generate plasma in the vicinity of the substrate to modify the surface. Instead of the argon atmosphere, nitrogen, helium, oxygen, etc. may be used. When the oxide semiconductor film is formed, powdery substances (particles, It is possible to remove the debris (also called trash).

[0128] As the planarization process, the polishing process, the dry etching process, and the plasma process may be performed multiple times. In addition, when performing the steps in combination, the order of the steps is not particularly limited. The thickness is not limited to a specific value and may be appropriately set depending on the unevenness of the surface of the oxide semiconductor film on which the oxide semiconductor film is formed.

[0129] In addition, the oxide semiconductor film is formed by removing excess hydrogen (water or a hydroxyl group) from the oxide semiconductor film. It is preferable to carry out a heat treatment to remove (dehydrate or dehydrogenate) the hydrogen atoms contained in the hydrogen atoms. The temperature is 300°C to 700°C, or lower than the distortion point of the substrate. The reaction can be carried out in a nitrogen atmosphere or the like.

[0130] This heat treatment can remove hydrogen, which is an n-type impurity, from the oxide semiconductor. For example, when the hydrogen concentration in the oxide semiconductor film after the dehydration or dehydrogenation treatment is 5×10 1 9 / cm 3 Less than or equal to 5×10 18 / cm 3 It can be as follows:

[0131] Note that the heat treatment for dehydration or dehydrogenation can be performed after the formation of the oxide semiconductor film. This may be performed at any time during the process of manufacturing the transistor 110. When an aluminum oxide film is used as the layer 103 or the first insulating layer 107, the oxide It is preferable to carry out the dehydration or dehydrogenation before forming the aluminum film. The treatment may be carried out multiple times, or may be combined with other heat treatments.

[0132] In heat treatment, nitrogen or rare gases such as helium, neon, and argon are mixed with water, hydrogen, etc. It is preferable that the nitrogen or helium introduced into the heat treatment device is not included. The purity of rare gases such as neon and argon should be 6N (99.9999%) or higher, preferably 7N ( 99.99999%) or more (i.e., impurity concentration is 1 ppm or less, preferably 0.1 ppm or less) It is preferable to use the following:

[0133] After the oxide semiconductor film is heated by the heat treatment, the heating temperature is maintained or the heating temperature is changed. While slowly cooling from the beginning, high purity oxygen gas, high purity dinitrogen monoxide gas, or ultra-dry air was added to the same furnace. The dew point was measured using a CRDS (Cavity Ring Down Laser Spectroscopy) type dew point meter. In this case, the moisture content is 20 ppm or less (-55°C in terms of dew point), preferably 1 ppm or less, more preferably Air (preferably 10 ppb or less) may be introduced. Oxygen gas or nitrous oxide gas It is preferable that the oxygen gas introduced into the heat treatment device does not contain water, hydrogen, etc. Alternatively, the purity of the dinitrogen monoxide gas is set to 6N or more, preferably 7N or more (i.e., oxygen gas or The impurity concentration in the nitrous oxide gas is kept below 1 ppm, preferably below 0.1 ppm. It is preferable that the dehydration or dehydrogenation is performed by the action of oxygen gas or nitrous oxide gas. The main components of the oxide semiconductor that were reduced at the same time as the impurity removal process By supplying oxygen, which is a component material, the oxide semiconductor film is highly purified and turned into an i-type ( It is possible to make it true.

[0134] In addition, oxygen (at least oxygen radiative) may be added to the oxide semiconductor film that has been subjected to the dehydration or dehydrogenation treatment. Oxygen may be supplied to the film by introducing oxygen into the film. stomach.

[0135] Oxygen is introduced into an oxide semiconductor film that has been subjected to dehydration or dehydrogenation treatment to supply oxygen into the film. By this, the oxide semiconductor film can be highly purified and made to be i-type (intrinsic). A transistor having a highly purified i-type (intrinsic) oxide semiconductor film has a low electrical characteristic fluctuation. is suppressed and the material is electrically stable.

[0136] In the oxygen introduction step, oxygen may be directly introduced into the oxide semiconductor film. The insulating layer 103 and the first insulating layer 107 are formed on the insulating layer 102. Oxygen may be introduced into the oxide semiconductor layer. When oxygen is introduced through another film, the ions Ion implantation, ion doping, plasma immersion ion implantation, etc. However, when oxygen is directly introduced into the exposed oxide semiconductor film, the above method is used. In addition to the above method, plasma treatment or the like can also be used.

[0137] Oxygen may be introduced into the oxide semiconductor film after dehydration or dehydrogenation treatment. In addition, the oxide semiconductor layer that has been subjected to the dehydration or dehydrogenation treatment may be The introduction of oxygen may be carried out multiple times. In addition, the dehydration or dehydrogenation treatment and the introduction of oxygen may be carried out in the following manner: This may be repeated multiple times.

[0138] Note that oxygen may be introduced into the oxide semiconductor film before it is processed into a predetermined shape, or after it is processed into a predetermined shape. This may be carried out after processing into a specific shape.

[0139] In this way, impurities such as water and hydrogen are removed, and the oxide, which is a constituent element of the oxide semiconductor, is also removed. By supplying an element, the i-type can be realized. In this respect, the doping of impurity elements, such as silicon, It can be said that this is not merely an i-type change, but rather contains a technological concept that has never been seen before.

[0140] Note that the oxide semiconductor film may be a single crystal oxide semiconductor, a polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, or a In addition to single layers of amorphous oxide semiconductors, amorphous oxide semiconductors, and CAAC-OS films, In addition, the stack of oxide semiconductors may be formed by stacking at least two layers selected from the following: The layer may be a stack of layers having the same crystallinity, or a stack of layers having different crystallinity.

[0141] Next, a method for manufacturing the transistor 110 and the capacitor 111 will be described with reference to cross-sectional views shown in FIGS. The following description will be given with reference to the side view of FIG. 5 and the top view of FIG. 6. Note that the transistor 112 is also , can be fabricated in a similar manner to the transistor 110.

[0142] First, the oxide semiconductor film is processed into a predetermined shape to form an oxide semiconductor layer on the base insulating layer 101. A layer 102 is formed (see FIG. 3(A), FIG. 4(A), FIG. 4(B), and FIG. 5(A)).

[0143] Next, a first conductive film 116 is formed to cover the base insulating layer 101 and the oxide semiconductor layer 102. (See FIG. 3(B), FIG. 4(C), FIG. 4(D), and FIG. 5(B)).

[0144] The first conductive film 116 is made of a material that can withstand the subsequent heat treatment. For example, aluminum (Al), Chromium (Cr), Copper (Cu), Tantalum (Ta), Titanium (Ti), Molybdenum (Mo) Mo, Tungsten (W), Neodymium (Nd), Scandium (Sc), etc. Metal films containing the above elements, or metal nitride films containing the above elements (titanium nitride film, Molybdenum nitride film, tungsten nitride film, etc. can be used. Titanium (T) is placed on either or both of the upper and lower sides of a low-resistance metal film such as Al (Al) or Cu (Copper). i) High melting point metal films such as molybdenum (Mo), tungsten (W), and tantalum (Ta) or their metal nitride films (titanium nitride film, molybdenum nitride film, tungsten nitride film) A high melting point metal film may be placed on either or both of the lower and upper sides of the low resistance metal film. When metal films or metal nitride films are laminated, the metal in the low-resistance metal film moves (diffusion) That is, the first conductive film 116 is preferably a first conductive layer, The first conductive layer is a metal film, and the second conductive layer is a low-resistance conductive layer. At least one of the first conductive layer and the third conductive layer is made of a metal of the second conductive layer. The third conductive layer on the second conductive layer is made of a material capable of preventing the movement of the second conductive layer. By covering the end of the second conductive layer, migration of metal from the end of the second conductive layer can be suppressed. This is preferable because it can be done.

[0145] For example, the first conductive film 116 is formed by stacking tungsten (W), copper (Cu), and tantalum nitride. The low-resistance copper (Cu) is layered with tungsten (W) and The first conductive film 116 may be made of a conductive metal oxide. Conductive metal oxides include indium oxide (In2O3), tin oxide ( SnO2), zinc oxide (ZnO), indium oxide tin oxide (In2O3-SnO2, I TO), indium oxide zinc oxide (In2O3-ZnO) or these metals An oxide material containing silicon oxide can be used.

[0146] A resist mask is formed over the first conductive film 116, and the first conductive film 116 is A part of the conductive film 116 is selectively removed to form a source electrode covering the outer edge of the oxide semiconductor layer 102. Electrode 104, which is one of the source and drain electrodes, and electrode 105, which is the other of the source and drain electrodes. The electrode 108 and the electrode 114 which functions as one of a pair of electrodes of the capacitor 111 are formed. (See FIG. 3(C), FIG. 4(E), FIG. 4(F), and FIG. 5(C)).

[0147] As shown in FIG. 5C, the other of the source and drain electrodes, 108 is arranged to be surrounded by an electrode 104 which is either a source electrode or a drain electrode. can be.

[0148] The first conductive film 116 is etched by a dry etching method or a wet etching method. The first conductive film 116 can be etched by a dry etching method. The first conductive film 116 may be formed by a combination of the wet etching method and the etch method. The resist mask is formed by appropriately using a photolithography method, a printing method, an inkjet method, or the like. If the resist mask is formed by the inkjet method, it is possible to use a photomask. This reduces manufacturing costs.

[0149] When the first conductive film 116 is etched by dry etching, the etching gas is A gas containing a halogen element can be used as the halogen gas. The following are examples of chloride (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4) or tetrachloride: Chlorine gases such as carbon chloride (CCl4), carbon tetrafluoride (CF4), and hexafluoride Sulfur (SF6), nitrogen trifluoride (NF3), or trifluoromethane (CHF3), etc. Fluorine-based gases such as hydrogen bromide (HBr) or oxygen can be used as appropriate. In addition, an inert gas may be added to the etching gas used. Reactive ion etching (RIE) is one of the methods g) method can be used.

[0150] In addition, a capacitively coupled plasma (CCP) was used as the plasma source. Inductively Coupled Plasma (ICP) Coupled Plasma, Electron Cyclotron Resonance (ECR) Cyclotron Resonance plasma, Helicon wave excited plasma (HW P: Helicon Wave Plasma, Microwave Excited Surface Wave Plasma (SW P: Surface Wave Plasma) can be used. In particular, IC P, ECR, HWP, and SWP can generate high density plasma. The etching method (hereinafter also referred to as "dry etching process") is The etching conditions (power applied to the coil-shaped electrode) were adjusted so that the processed shape could be etched. The amount of heat generated, the amount of power applied to the electrode on the substrate side, the temperature of the electrode on the substrate side, etc. are appropriately adjusted.

[0151] The ends of the formed electrodes 104, 108, and 114 are tapered. This is preferable because it improves the coverage of the insulating layer and conductive layer that are laminated later.

[0152] Specifically, the cross-sectional shapes of the electrodes 104, 108, and 114 are trapezoidal or triangular. In order to achieve this, the ends of the electrodes 104, 108, and 114 are tapered. Here, the taper angle θ of the ends of the electrodes 104, 108, and 114 is set to 60° or less. The taper angle θ is preferably 45° or less, and more preferably 30° or less. When a layer having a tapered shape is viewed from a direction perpendicular to its cross section (a plane perpendicular to the surface of the substrate), The taper angle is less than 90°. When the taper angle is 90° or more, it is called a forward taper. In addition, not only the electrodes 104, 108, and 114, but also the ends of each layer may be tapered. This prevents the layer formed on top from being interrupted (step discontinuity) and improves coverage. It can be raised.

[0153] The ends of the electrodes 104, 108, and 114 may be formed in a stepped shape. The ends of the electrodes 104, 108, and 114 are stepped, so that the layers formed thereon can be It is possible to prevent breakage and improve the coverage. By forming the end of each layer, not limited to the electrode 114, into a forward tapered shape or a stepped shape, This prevents the layer from being broken (step breaks) and improves the coating properties. can.

[0154] The surface of the oxide semiconductor layer 102 exposed by the formation of the electrodes 104 and 108 is The elements constituting the electrodes 104 and 108, the elements present in the film formation chamber, and the elements Elements constituting the etching gas used may adhere as impurities.

[0155] The adhesion of impurities can increase the off-state current of a transistor or degrade the electrical characteristics of the transistor. In addition, a parasitic channel is likely to be generated in the oxide semiconductor layer 102. Therefore, the electrodes that should be electrically separated from each other are easily electrically connected via the oxide semiconductor layer 102. become.

[0156] Therefore, after the etching for forming the electrodes 104 and 108 is completed, the oxide semiconductor A cleaning process (impurity removal process) is performed to remove impurities adhering to the surface and side surfaces of the conductor layer 102. ) may also be performed.

[0157] The impurity removal treatment can be performed by plasma treatment or treatment with a solution. As the plasma treatment, oxygen plasma treatment or nitrous oxide plasma treatment can be used. Alternatively, a rare gas (typically, argon) may be used for the plasma treatment.

[0158] In addition, cleaning with solutions includes alkaline solutions such as TMAH solution, phosphoric acid and dilute This can be done using an acidic solution such as hydrofluoric acid, water, etc. For example, dilute water fluoride When using hydrofluoric acid, mix 50wt% hydrofluoric acid with 1 / 10 water. 5 ~1 / 10 2 degree, good Preferably 1 / 10 5 ~1 / 10 3 Use dilute hydrofluoric acid diluted to about 100%. , with a concentration of 0.5% by weight to 5×10 -4 % by weight of dilute hydrofluoric acid, preferably 5×10 - 2 Weight% to 5×10 -4 It is preferable to use dilute hydrofluoric acid of about 100% by weight for the cleaning process. The impurities attached to the exposed surface of the oxide semiconductor layer 102 are removed by the cleaning treatment. It is possible.

[0159] In addition, when impurity removal treatment is performed using a dilute hydrofluoric acid solution, the exposed oxide semiconductor layer 1 That is, the surface of the oxide semiconductor layer 102 can be etched. Impurities attached to the surface or mixed in the vicinity of the surface of the oxide semiconductor layer 102 are oxidized. This can be removed together with a part of the semiconductor layer 102. The thickness of the region overlapping with the electrode 108 is greater than the thickness of the region not overlapping with the electrode 104 and the electrode 108. It becomes bigger.

[0160] By removing impurities, secondary ion mass spectrometry (SIMS) Concentration peaks obtained by analysis using Ion Mass Spectrometry The chlorine concentration on the surface of the oxide semiconductor layer is 1×10 19 / cm 3 Below (preferably is 5 x 10 18 / cm 3 Less than 1×10, more preferably 18 / cm 3 (below) In addition, the boron concentration can be increased to 1×10 19 / cm 3 Less than or equal to 5×10 18 / c m 3 Less than 1×10, more preferably 18 / cm 3 (See below). Aluminum concentration 1×10 19 / cm 3 Less than or equal to 5×10 18 / cm 3 Below, More preferably, 1×10 18 / cm 3 (see below).

[0161] By removing impurities, we have achieved a highly reliable transistor with stable electrical characteristics. 0 can be achieved.

[0162] Next, a gate insulating layer is formed over the oxide semiconductor layer 102, the electrode 104, the electrode 108, and the electrode 114. A layer 103 is formed.

[0163] Gate insulating layer 103 (a product of first gate insulating layer 103a and second gate insulating layer 103b) The thickness of the layer is 1 nm to 20 nm, and the method is sputtering, MBE, CVD, or pas The gate insulating layer can be formed by appropriately using a laser deposition method, an ALD method, or the like. 103 is a plate having a plurality of substrate surfaces set approximately perpendicular to the sputtering target surface. Alternatively, the film may be formed using a sputtering apparatus that performs film formation in a heated state.

[0164] The material of the gate insulating layer 103 may be silicon oxide, gallium oxide, aluminum oxide, Silicon nitride, silicon oxynitride, aluminum oxynitride, silicon nitride oxide, etc. are used. In the gate insulating layer 103, a first gate insulating layer in contact with the oxide semiconductor layer 102 may be formed. The base insulating layer 103a preferably contains oxygen. Similarly, it is preferable that a region in contact with the oxide semiconductor layer 102 has an oxygen excess region. In particular, the first gate insulating layer 103a has at least a stoichiometric composition in the film (bulk). For example, the first gate insulating layer 103a preferably contains oxygen in an amount exceeding 100%. When silicon oxide is used, SiO 2+α (However, it is preferable to set α>0.) In this embodiment, the gate insulating layer 103 is made of SiO 2+α (where α>0) The silicon oxide is used as the gate insulating layer 103. In this case, oxygen can be supplied to the oxide semiconductor layer 102, so that the characteristics of the oxide semiconductor layer 102 can be improved. Furthermore, the gate insulating layer 103 is formed according to the size of the transistor to be manufactured and the thickness of the gate insulating layer 103. It is preferable to form the insulating layer while taking into consideration step coverage.

[0165] In addition, the second portion of the gate insulating layer 103 that is in contact with the gate electrode 105 to be formed in a later step is The gate insulating layer 103b is formed by absorbing an element contained in the gate electrode 105 into the oxide semiconductor layer 102. and a blocking function for suppressing release of oxygen from the oxide semiconductor layer 102. It functions as a blocking layer.

[0166] The material of the gate insulating layer 103 is hafnium oxide, yttrium oxide, hafnium Silicate (HfSi x O y x>0, y>0), nitrogen-doped hafnium silicate (HfSiO x N y (x>0, y>0)), hafnium aluminate (HfAl x O y (x>0, y>0)), and the use of high-k materials such as lanthanum oxide allows the gate Furthermore, the first gate insulating layer 103a and the second gate insulating layer 10 Each of 3b may have a single layer structure or a laminated structure.

[0167] Next, a gate electrode 105 is formed on the oxide semiconductor layer 102 via the gate insulating layer 103. First, a second conductive film 117 is formed on the gate insulating layer 103 (FIG. 3(D) and FIG. 4 (G), Figure 4(H), and Figure 6(A).

[0168] The second conductive film 117 is formed by a gate insulating film by a plasma CVD method, a sputtering method, or the like. It is deposited on layer 103 .

[0169] The material of the second conductive film 117 is molybdenum (Mo), titanium (Ti), tantalum ( Ta), tungsten (W), aluminum (Al), copper (Cu), chromium (Cr), nickel A metal film containing an element selected from Nd, Sc, or the above-mentioned Metal nitride films containing elements (titanium nitride film, molybdenum nitride film, tungsten nitride film) ) can be used. In addition, similarly to the first conductive film 116, aluminum (Al), Titanium (Ti), molybdenum (Mo), or other low-resistance metal film is placed on either or both of the upper and lower sides of the metal film. High melting point metal film such as molybdenum (Mo), tungsten (W), tantalum (Ta) or the like By stacking these metal nitride films, the migration (diffusion) of the metal in the low-resistance metal film can be inhibited. That is, like the first conductive film 116, the second conductive film 117 is preferably The second conductive layer is a low-coating layer, and the third conductive layer is a metal film. A highly resistive conductive layer is used. At least one of the first conductive layer and the third conductive layer is provided with a second conductive layer. The third conductive layer on the second conductive layer is made of a material capable of preventing the migration of metal in the layer. By covering the end of the second conductive layer, migration of metal from the end of the second conductive layer is suppressed. This is preferable because it is possible to

[0170] For example, the second conductive film 117 is formed by stacking tungsten (W), copper (Cu), and tantalum nitride. The low-resistance copper (Cu) is layered with tungsten (W) and The second conductive film 117 may be formed by doping with an impurity element such as phosphorus. Semiconductors such as etched polycrystalline silicon and silicides such as nickel silicide The second conductive film 117 may have a single layer structure or a multilayer structure. .

[0171] The second conductive film 117 may be made of a material containing indium tin oxide or tungsten oxide. Indium oxide, indium zinc oxide with tungsten oxide, indium zinc oxide with titanium oxide Indium oxide, indium tin oxide with titanium oxide, indium zinc oxide, cerium oxide Conductive materials such as indium-tin oxide doped with indium can also be used. A laminated structure of a conductive material and the above-mentioned metal material may also be used.

[0172] In addition, a layer of the second conductive film 117 in contact with the gate insulating layer 103 is made of a metal oxide containing nitrogen. oxides, specifically, In-Ga-Zn oxides containing nitrogen and In-Sn oxides containing nitrogen. oxides containing nitrogen, In-Ga oxides containing nitrogen, In-Zn oxides containing nitrogen, Sn-based oxides containing nitrogen, In-based oxides containing nitrogen, and metal nitride films (InN, SnN, etc.) are used. These films have an energy of 5 eV (electron volts) or more, preferably 5.5 eV (electron volts). When used as a gate electrode, it has a work function of 1000V or more, and the threshold voltage of a transistor is This makes it possible to realize a so-called normally-off switching element. .

[0173] The gate electrode 105 and the electrode 115 are formed on a second conductive layer provided on the gate insulating layer 103. The conductive film 117 can be formed by processing using a resist mask. The resist mask used in the processing is a resist formed by a photolithography method or the like. Slimming processing is performed on the resist mask to create a mask with finer patterns. is preferred.

[0174] The slimming process is, for example, an ablation process using oxygen in a radical state (oxygen radicals) or the like. However, the slimming process is a photolithography process. If a process could be used to process masks formed by such methods into finer patterns, It is not necessary to limit the process to slimming. The channel length (L) of the transistor is determined by the slimming process. For this purpose, a process with good controllability can be applied.

[0175] As a result of the slimming process, the resist mask formed by photolithography etc. The line width is preferably 1 / 2 or less, more preferably 1 / 3 or less, of the resolution limit of the exposure device. For example, the line width is preferably 30 nm or more and 2000 nm or less. Alternatively, the thickness can be set to 50 nm or more and 350 nm or less. It is possible to achieve finer grains.

[0176] As described above, by selectively removing a portion of the second conductive film 117, a ring-shaped gate The electrode 105 and the other electrode 115 of the pair of electrodes of the capacitor 111 are formed. (See FIG. 3(E), FIG. 4(I), FIG. 4(J), and FIG. 6(B)).

[0177] As shown in FIG. 6B, the annular gate electrode 105 serves as a source electrode or a drain electrode. The electrode 108 is provided on the outside of the other electrode 108 so as to surround the periphery of the electrode 108. The electrode 104, which is either a source electrode or a drain electrode, is disposed outside the annular gate electrode 105. The gate electrode 105 is disposed on the side of the semiconductor substrate 101 so as to surround the periphery of the annular gate electrode 105 .

[0178] If the ends of the gate electrode 105 and the electrode 115 are tapered, This is preferable because it improves the coverage of the insulating layer and conductive layer to be laminated.

[0179] After the gate electrode 105 is formed, an impurity element that changes the conductivity of the oxide semiconductor is added to the gate electrode 105. When the oxide semiconductor layer 102 is doped using the gate electrode 105 as a mask, the source region and the Self-alignment between the drain region and the channel forming region, and between the drain region and the channel forming region. When the low resistance region is formed, the on-resistance of the transistor 110 is reduced. This reduces the on-resistance and improves the operating speed.

[0180] The impurity elements are added by ion implantation, ion doping, plasma immersion ion implantation, etc. This can be done by using an on-implantation method or the like.

[0181] The impurity element is an impurity that changes the electrical conductivity of the oxide semiconductor layer. The elements included in the study were group 15 elements (typically nitrogen (N), phosphorus (P), arsenic (As), and and antimony (Sb), boron (B), aluminum (Al), argon (Ar), Lithium (He), Neon (Ne), Indium (In), Fluorine (F), Chlorine (Cl), One or more selected from titanium (Ti) and zinc (Zn) can be used. Cut.

[0182] In addition, when the impurity element is not added to the oxide semiconductor layer 102, A self-aligned structure is formed between the drain region and the channel region, and between the drain region and the channel region. By providing the offset region, the gate electrode and the source The parasitic capacitance between the gate electrode and the drain electrode can be reduced. This can reduce the parasitic capacitance that occurs in the

[0183] The shape of the gate electrode 135 of the transistor 112 is the same as that of the gate electrode 105. The electrode 105 is formed by modifying the electrode 104 and the electrode 108 so that the electrode 105 partially overlaps the electrode 104 and the electrode 108. It is possible.

[0184] Also, like the transistor 112, a part of the gate electrode 135 and the source and drain electrodes When the electrodes 104 and 108 overlap, the offset region is formed as described above. In addition, in the transistor 112, as described above, the source region and the channel region are not formed. A self-aligned structure is formed between the drain region and the channel region, and between the drain region and the channel region. Since impurity elements cannot be added to the semiconductor layer, a low resistance region is not formed.

[0185] Next, a first insulating layer is formed over the gate insulating layer 103, the gate electrode 105, and the electrode 115. A layer 107 is formed.

[0186] The first insulating layer 107 is formed by a plasma CVD method, a sputtering method, a vapor deposition method, or the like. The first insulating layer 107 is typically made of silicon oxide or silicon oxynitride. Inorganic insulating materials such as aluminum oxide nitride, gallium oxide, etc. can be used. can.

[0187] The first insulating layer 107 may be made of aluminum oxide, hafnium oxide, magnesium oxide, or the like. zirconium oxide, lanthanum oxide, barium oxide, or metal nitrides (e.g., nitride Aluminum) can also be used.

[0188] The first insulating layer 107 may be a single layer or a multilayer, for example, silicon oxide and aluminum oxide. Aluminum oxide is a material that can absorb impurities such as hydrogen and moisture, and also acids. It has a high blocking effect that prevents both oxygen and water from passing through the membrane, and is effective during the manufacturing process and operation. After the manufacturing process, impurities such as hydrogen and moisture, which are factors of fluctuation, are mixed into the oxide semiconductor layer 102. and release of oxygen, which is a main component material constituting the oxide semiconductor, from the oxide semiconductor layer 102. This is preferable because it functions as a blocking layer that suppresses

[0189] In addition, when aluminum oxide is used as the first insulating layer 107, for example, aluminum The aluminum oxide film is formed by forming a film of aluminum and doping the aluminum with oxygen. Um may also be used.

[0190] The above-mentioned "oxygen doping treatment" refers to a treatment in which oxygen (at least oxygen radicals, oxygen atoms, oxygen elementary molecules, ozone, oxygen ions (oxygen molecular ions), and / or oxygen cluster ions. The term "bulk" refers to the introduction of oxygen into the bulk. The term "acid" is used to clarify that the additive is added not only to the surface of the thin film but also to the inside of the thin film. The "raw doping process" involves the addition of oxygen plasma to the bulk. The oxygen doping process includes heat treatment in an oxygen atmosphere, ion implantation, and ion Doping method, plasma immersion ion implantation method, performed in an oxygen atmosphere For example, plasma treatment in an atmosphere containing oxygen can be used. When performing the Zuma treatment, an ashing device can be used. Alternatively, a gas cluster ion beam may be used.

[0191] The supply gas in the oxygen doping process is oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, etc. Gases containing oxygen, such as nitrogen and carbon monoxide, can be used. A rare gas may be added to the gas.

[0192] In addition, the oxygen doping process may be performed on the entire surface of the film into which oxygen is to be introduced at once. For example, Alternatively, a linear ion beam may be used. When a linear ion beam is used, oxygen is introduced. At least one of the film and the ion beam is moved (scanned) relative to one another. In this case, oxygen can be introduced onto the entire surface of the layer into which oxygen is to be introduced.

[0193] The first insulating layer 107 is formed by sputtering or the like to add impurities such as water and hydrogen to the first insulating layer 107. It is preferable to form the film by a suitable method that does not involve contamination.

[0194] In the same manner as in the formation of the oxide semiconductor film, moisture remaining in the deposition chamber for the first insulating layer 107 is removed. For this purpose, it is preferable to use an adsorption type vacuum pump (such as a cryopump). The concentration of impurities contained in the first insulating layer 107 formed in a deposition chamber evacuated using an opto-pump In addition, the exhaust method for removing residual moisture in the deposition chamber for the first insulating layer 107 can be reduced. The stage may be a turbomolecular pump plus a cold trap.

[0195] In this embodiment, the first insulating layer 107 is formed by sequentially depositing a thin film of a SiO 2 film on the oxide semiconductor layer 102. A laminated structure of silicon oxide and aluminum oxide is used for the insulating layer. Aluminum is applied at high density (film density 3.2g / cm 3 More than 3.6 g / cm, preferably 3.6 g / cm 3 (End) By this, stable electrical characteristics can be imparted to the transistor 110. The density was measured by Rutherford Backscattering (RBS). ring spectrometry, X-ray reflectometry (XRR), It can be measured by the reflection.

[0196] Next, a second insulating layer 109 is formed on the first insulating layer 107. The second insulating layer 109 is It is preferable that the insulating film functions as a planarizing insulating film that reduces surface irregularities caused by transistors. The material of the second insulating layer 109 is appropriately selected from the above-mentioned materials used for the first insulating layer 107. In addition to the above materials, the second insulating layer 109 can be made of polyimide. Organic materials such as acrylic resins and benzocyclobutene-based resins can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials) and the like can be used. A planarizing insulating film may be formed by stacking a plurality of insulating films made of these materials. In addition, the second insulating layer 109 may not be provided, and only the first insulating layer 107 may be provided. good.

[0197] As described above, a sufficient amount of oxygen is supplied to the oxide semiconductor layer 102 so that the oxide semiconductor layer 102 is in a supersaturated state. In order to achieve this, an insulating layer containing excess oxygen is provided to surround the oxide semiconductor layer 102. As described above, the second base insulating layer 10 in contact with the oxide semiconductor layer 102 is preferably 1b and the first gate insulating layer 103a, an insulating layer containing excess oxygen or an oxide semiconductor layer 10 An insulating layer including an oxygen excess region is used in the region in contact with 2.

[0198] Furthermore, it is placed on the outside of the insulating layer containing excess oxygen to prevent the infiltration of impurities from the outside. In addition, a blocking layer that suppresses release of oxygen from the oxide semiconductor layer 102 is preferably provided. In this embodiment, the first base insulating layer 101a, the second gate insulating layer 103b, And the first insulating layer 107 functions as a blocking layer.

[0199] An insulating layer containing excess oxygen and a blocking layer for suppressing release of oxygen are provided above and below the oxide semiconductor layer 102. By providing the insulating layer, the oxide semiconductor layer 102 has a substantially stoichiometric composition. The oxygen concentration can be increased by 100% or by 150%. For example, when the stoichiometric composition of the oxide semiconductor layer 102 is In:Ga:Zn:O=1:1:1: In the case where the atomic ratio of oxygen contained in the oxide semiconductor layer 102 is 4 or more, It is possible.

[0200] Next, a mask (not shown) is formed on the second insulating layer 109, and the first The second insulating layer 109, the first insulating layer 107, and the gate insulating layer 103 are each partially removed. The second insulating layer 109 is removed to form an opening that reaches the electrode 108. etch the first insulating layer 107 and the gate insulating layer 103 to reach the electrode 108. An opening is formed.

[0201] Next, a third conductive layer which will become the electrode 106 is formed on the second insulating layer 109 so as to fill the opening. The third conductive film is partially removed by etching or the like, and the electrode 108 is provided with an electrically conductive film. An electrode 106 that is electrically connected to the third conductive film is formed (see FIGS. 1(A) to 1(D)). The same material as that of the first conductive film 116 or the second conductive film 117 can be used for the conductive film 114. Similarly to the first conductive film 116 and the second conductive film 117, aluminum (Al), copper (Cu), Titanium (Ti), molybdenum (Mo), etc. are placed on either or both of the upper and lower sides of a low-resistance metal film such as Cu. High melting point metal films such as butanol (Mo), tungsten (W), tantalum (Ta), etc. The metal nitride film is preferably laminated because it can inhibit the migration (diffusion) of the metal in the low-resistance metal film. For example, the third conductive film may be made of tungsten (W), copper (Cu), or tantalum nitride. The low-resistance copper (Cu) is layered on the barrier metal tungsten (W) and That is, the third conductive film may be sandwiched between the first conductive film 116 and the tantalum nitride film. A first conductive layer, a metal film as a second conductive layer, and a third conductive layer are laminated together. A low-resistance conductive layer is used as the layer. At least one of the first conductive layer and the third conductive layer is A material capable of preventing the migration of the metal of the second conductive layer is used. When the conductive layer is configured to cover the end of the second conductive layer, the metal from the end of the second conductive layer is prevented from flowing out of the conductive layer. This is preferable since it is possible to suppress the movement.

[0202] If the end of the formed electrode 106 is tapered, the insulating layer and the conductive layer to be laminated later may be damaged. This is preferable because it improves the coverage of the layer.

[0203] Here, the first conductive film 116 is made up of a first conductive layer, a metal film which is a second conductive layer, and The first conductive layer and the second conductive layer are laminated to form a laminate of three conductive layers. The second conductive layer is a low-resistance conductive layer. The third conductive layer is made of a material capable of inhibiting the migration of metal in the second conductive layer, and the electrodes 104 and 105 are made of a material capable of inhibiting the migration of metal in the second conductive layer. FIG. 7A shows a cross-sectional view of a semiconductor device in which the transistor 108 and the electrode 114 are formed.

[0204] The electrode 104 shown in FIG. 7A includes a first electrode 104a, a second electrode 104b, and a third electrode 104b. The electrode 104c is a laminated electrode. The electrode 108 is made up of a first electrode 108a, a second electrode 108b, and a The first electrode 108b and the third electrode 108c are laminated together. 1. An electrode in which a first electrode 114a, a second electrode 114b, and a third electrode 114c are stacked. It is.

[0205] In FIG. 7A, the second electrode 104 of each of the electrodes 104, 108, and 114 is The material of the first electrode 108b, the second electrode 114b is, for example, copper. In addition, the first electrode 104a, the first electrode 104b, the first electrode 104c, and the first electrode 114c of each of the electrodes 104, 108, and 114 are The material of the first electrode 108a and the first electrode 114a is, for example, a material that suppresses the movement (diffusion) of copper. In addition, the electrodes 104, 108, and 114 are each made of tungsten (W). The materials of the third electrodes 104c, 108c, and 114c are For example, tantalum nitride is used. In the electrode structure shown in FIG. 7(A), a fluorine-based tantalum nitride is used to encapsulate the copper. Although the number of photolithography and etching steps increases, the material of the second electrode is The effect of suppressing copper diffusion by the above-mentioned method is extremely high, and the reliability of the semiconductor device can be improved.

[0206] In addition, the semiconductor device is configured such that the third electrode on the second electrode covers the end of the second electrode. A cross-sectional view of the third electrode 104c is shown in FIG. The electrode 108c and the third electrode 114c are connected to the second electrode 104b and the second electrode When the end portions of the first electrode 108b and the second electrode 114b are covered, the gold of the second electrode This is preferable because it further enhances the effect of suppressing the migration of metals, such as copper. The pole structure requires additional photolithography and etching steps to seal in the copper However, it is highly effective in suppressing the diffusion of copper, which is the material of the second electrode, and is therefore suitable for semiconductor devices. This can improve the reliability of the device.

[0207] Note that the oxide semiconductor layer 102 may have a structure in which a plurality of oxide semiconductor layers are stacked. For example, the oxide semiconductor layer 102 may be a stack of a first oxide semiconductor layer and a second oxide semiconductor layer. As a result, the first oxide semiconductor layer and the second oxide semiconductor layer are formed using metal oxides having different compositions. For example, a ternary metal oxide may be used for the first oxide semiconductor layer, and a second oxide semiconductor may be used for the second oxide semiconductor layer. The conductor layer may be made of an oxide of a binary metal. The two oxide semiconductor layers may each be an oxide of a ternary metal.

[0208] In addition, the first oxide semiconductor layer and the second oxide semiconductor layer are made of the same elements, and the composition of both layers is For example, the atomic ratio of the first oxide semiconductor layer may be set to In:Ga:Zn=1. The atomic ratio of the second oxide semiconductor layer is In:Ga:Zn=3:1:2. The atomic ratio of the first oxide semiconductor layer may be In:Ga:Zn=1:3:2, The atomic ratio of the second oxide semiconductor layer may be In:Ga:Zn=2:1:3. The atomic ratio of the first oxide semiconductor layer or the second oxide semiconductor layer is In:Ga:Zn=1. :6:4, In:Ga:Zn=1:9:6, or In:Ga:Zn=1:9:0 Good too.

[0209] At this time, the side of the first oxide semiconductor layer or the second oxide semiconductor layer closer to the gate electrode (the The In and Ga contents of the oxide semiconductor layer on the channel side are preferably In>Ga. The In and Ga contents of the oxide semiconductor layer on the side farther from the back electrode (the back channel side) are set to In≦ It is better to call it Ga.

[0210] In oxide semiconductors, the s orbitals of heavy metals mainly contribute to carrier conduction, and the In content Increasing the number of s orbitals tends to increase the overlap, so In>Ga The oxide having the composition In≦Ga has a higher mobility than the oxide having the composition In≦Ga. Ga has a higher oxygen vacancy formation energy than In, so oxygen vacancies are less likely to occur. Oxides with a composition of In≦Ga have more stable characteristics than oxides with a composition of In>Ga. Equipped with.

[0211] An oxide semiconductor with a composition of In>Ga is applied to the channel side, and In≦ By using an oxide semiconductor containing Ga, the mobility and reliability of a transistor can be improved. It will be possible to further increase

[0212] In addition, the first oxide semiconductor film and the second oxide semiconductor film may be oxide semiconductor films having different crystallinity. That is, a single crystal oxide semiconductor film, a polycrystalline oxide semiconductor film, a microcrystalline oxide semiconductor film, A structure in which a suitable combination of a carbide semiconductor film, an amorphous oxide semiconductor film, or a CAAC-OS film is used. In addition, at least one of the first oxide semiconductor film and the second oxide semiconductor film may be When an amorphous oxide semiconductor is used for either one of the two layers, the internal stress of the oxide semiconductor layer 102 and the external stress are reduced. This reduces the stress on the transistors, reducing the variation in their characteristics and improving the reliability of the transistors. It is possible to further increase the

[0213] On the other hand, amorphous oxide semiconductors are prone to absorbing impurities that act as donors, such as hydrogen, and are also prone to oxidation. Therefore, the oxide semiconductor film on the channel side is easily made n-type because of the electron vacancies. It is preferable to use a crystalline oxide semiconductor such as CAAC-OS.

[0214] In addition, the oxide semiconductor layer 102 has a stacked structure of three or more layers, and A structure in which an amorphous oxide semiconductor layer is sandwiched between semiconductor layers may be used. A structure in which semiconductor layers and amorphous oxide semiconductor layers are alternately stacked may be used.

[0215] In the case where the oxide semiconductor layer 102 has a stacked structure of a plurality of layers, the above structure is a stacked structure of a plurality of layers. They can be used in combination.

[0216] In addition, the oxide semiconductor layer 102 has a stacked structure of a plurality of layers. The introduction of oxygen may be performed by a heat treatment in an oxygen atmosphere, an ion implantation method, an ion Doping method, plasma immersion ion implantation method, oxygen-containing atmosphere For example, a plasma treatment as described below can be used.

[0217] By introducing oxygen every time an oxide semiconductor layer is formed, oxygen vacancies in the oxide semiconductor are reduced. This can increase the effectiveness of the system.

[0218] In addition, in the transistor described in this embodiment, the oxide semiconductor layer 102 is a CAAC-OS The oxide semiconductor layer formed of CAAC-OS is particularly useful when This is because oxygen is easily desorbed from the end surface. This will be explained in detail below.

[0219] As described above, according to the present embodiment, a transistor capable of suppressing the occurrence of a parasitic channel is provided. In addition, the use of the transistor improves the operating characteristics. It is possible to provide a semiconductor device having the above structure.

[0220] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0221] (Embodiment 2) In this embodiment, a transistor having a structure different from that disclosed in the above embodiment is The following describes the transistor.

[0222] The transistor and the capacitor of this embodiment are shown in FIG. 8. The transistor 120 shown in FIG. The transistor has a structure similar to that of the transistor 110 shown in FIG. The electrode 124 (electrode 124a and electrode 124b) functioning as one of the electrodes is made of an oxide semiconductor. It differs from transistor 110 in that it does not cover the entire outer edge of conductor layer 102 .

[0223] FIG. 8A is a top view of a transistor 120 and a capacitor 111 of this embodiment. FIG. 8(B) is a cross-sectional view taken along line A5-A6 in the top view shown in FIG. FIG. 8(C) is a cross-sectional view taken along line B5-B6 in the top view shown in FIG. 8(A). 8(B) is a cross-sectional view taken along line C5-C6 in the top view shown in FIG. 8(A).

[0224] An electrode 124a serving as one of a source electrode and a drain electrode of the transistor 120 and The same potential is applied to electrode 124b and electrode 124c, and therefore they function electrically as the same electrode. The electrode 124a and the electrode 124b each cover a part of the outer edge of the oxide semiconductor layer 102. The configuration will be as follows.

[0225] By using the structure shown in the transistor 120, the area occupied by the transistor can be reduced. In addition, the outer edge of the oxide semiconductor layer 102 of the transistor 120 is a source electrode. or the electrode 124 (electrode 124a and electrode 124b) functioning as one of the drain electrodes. Since the electrode 10 functions as the other of the source electrode and the drain electrode, The oxide semiconductor 8 and the electrode 124 are not electrically connected to each other through a parasitic channel. By configuring the outer edge of the layer 102 so that it does not reach from the source electrode to the drain electrode, a parasitic It is possible to obtain a transistor capable of suppressing the occurrence of a discharge.

[0226] As shown in FIG. 9, the gate electrode 125 extends beyond the outer edge of the oxide semiconductor layer 102. In the extended transistor 121, the gate electrode 125 extends from the oxide semiconductor layer 1 However, there is a risk of low resistance regions being formed at the outer edges of the transistor 120. Similarly, the outer edge of the oxide semiconductor layer 102 functions as one of a source electrode and a drain electrode. Since the electrode 124 is in contact only with the corresponding electrodes 124 (electrodes 124a and 124b), the parasitic No channel occurs and the electrical characteristics of the transistor 121 are not degraded.

[0227] Note that FIG. 9A is a top view of the transistor 120 and the capacitor 111 of this embodiment. 9(B) is a cross-sectional view taken along line A7-A8 in the top view shown in FIG. 9(A). FIG. 9(C) is a cross-sectional view taken along line B7-B8 in the top view shown in FIG. 9D) is a cross-sectional view taken along line C7-C8 in the top view shown in FIG. 9A.

[0228] In FIG. 9, the gate electrode 125 is covered with the electrodes 124a and 124b. However, the present invention is not limited to this. The gate electrode 125 extends beyond both the outer edge that is not covered by the electrode 124a and the electrode 124b. Even if the transistor 121 is extended, no parasitic channel is generated, and the electrical characteristics of the transistor 121 are low. Don't lower it.

[0229] As described above, according to the present embodiment, a transistor capable of suppressing the occurrence of a parasitic channel is provided. In addition, the use of the transistor improves the operating characteristics. It is possible to provide a semiconductor device having the above structure.

[0230] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0231] (Embodiment 3) In this embodiment, a transistor having a different structure from the transistors disclosed in the above embodiment will be described. The structure and manufacturing method of the capacitor element that can be manufactured simultaneously with the transistor 250 We will explain about this.

[0232] FIG. 10A is a top view of the transistor 250, and FIG. 10A is a top view of the capacitor 2 10(B1) is a top view of the X1-X2 chain line in FIG. FIG. 10(B2) is a cross-sectional view of the portion shown in FIG. 10(A2) along the dashed line Y1-Y2. FIG.

[0233] The structure of the transistor 250 will be described with reference to FIGS. 10A1 and 10B1. In the top view of FIG. 10A1, the transistor 250 has a ring-shaped gate electrode. A source electrode 205 is formed on the inside of the ring-shaped gate electrode 208, and a drain electrode 206 is formed on the outside of the ring-shaped gate electrode 208. For convenience, the source electrode 205 is used in the present specification. The names of the parts corresponding to the drain electrode 206 are fixed, but in actual circuit operation In this case, the source and drain may be interchanged. Thus, the transistor 250 is Either the source electrode 205 or the drain electrode 206 is formed inside the ring-shaped gate electrode 208. The source electrode 205 or the drain electrode 206 is formed on the outside of the annular gate electrode 208. In other words, the transistor 25 has a structure in which the other is formed. 0 is a gate electrode that is connected to either the source electrode 205 or the drain electrode 206 in a plan view. It has a configuration surrounded by 208.

[0234] In addition, a region of the oxide semiconductor layer 204 that overlaps with the ring-shaped gate electrode 208 is a channel-shaped Since the channel forming region 204a is annular, the channel forming region 204a is also annular. 0 is a source electrode 205 or a drain electrode 206 inside the ring-shaped channel forming region 204a. 06 is formed, and a source electrode 205 or In other words, the other of the drain electrodes 206 is formed. That is, in a plan view, the transistor 250 has a source electrode 205 or a drain electrode 206. 06 is surrounded on one side by a channel formation region 204a.

[0235] In FIG. 10B1, a wiring 202 is formed on a substrate 201. An insulating layer 203 is formed. An oxide semiconductor layer 204 is formed over the insulating layer 203. A source electrode 205 and a drain electrode 206 are formed on the oxide semiconductor layer 204. The oxide semiconductor layer 204 includes a channel formation region 204a, a low-resistance region 204b, and a low The source electrode 205 or the drain electrode 204c is disposed in the oxide semiconductor layer. By providing a low resistance region between the region where 206 contacts and the channel formation region, a transistor This can increase the on-state current of the transistor and enhance the field-effect mobility of the transistor.

[0236] The source electrode 205 is connected to the wiring 202 through an opening 213 formed in the insulating layer 203. The oxide semiconductor layer 204, the source electrode 205, and the drain electrode 206 are electrically connected to each other. An insulating layer 207 is formed on the electrode 206, and a gate electrode 208 is formed on the insulating layer 207. In addition, an insulating layer 209 is formed on the gate electrode 208, and a planarized An insulating layer 210 is formed. The insulating layer 207 can function as a gate insulating layer. do.

[0237] The insulating layer 203, the insulating layer 207, and the insulating layer 209 may be a single layer or a laminate of multiple layers. In particular, when the insulating layer 203 and the insulating layer 207 are formed by stacking a plurality of layers, the oxide semiconductor layer It is preferable to use a layer containing a large amount of oxygen as the layer in contact with 204.

[0238] In addition, the end of the oxide semiconductor layer 204 is covered with the drain electrode 206. This reduces oxygen desorption from the end of the 204 and suppresses the generation of parasitic channels. The transistor 250 includes at least a gate electrode 208, a source electrode 205, a drain electrode 20 6, an insulating layer 207, and an oxide semiconductor layer 204. The transistor 250 is a type of transistor with a top gate structure.

[0239] The configuration of the capacitor 255 will be described with reference to FIG. 10(A2) and FIG. 10(B2). The capacitance element 255 is formed by sandwiching an insulating layer 207 between a capacitance electrode 221 and a capacitance electrode 222. In FIG. 10B2, an insulating layer 203 is formed on a substrate 201. A capacitance electrode 221 is formed on the edge layer 203. The capacitance electrode 221 is connected to the source electrode 205. The capacitance electrode 22 can be formed using the same layer as the drain electrode 206. An insulating layer 207 is formed on the capacitor 1, and a capacitor electrode 222 is formed on the insulating layer 207. The capacitance electrode 222 can be formed using the same layer as the gate electrode 208. An insulating layer 209 is formed on the electrode 222, and a planarizing insulating layer 210 is formed on the insulating layer 209. It is being done.

[0240] The transistor 250 and the capacitor 255 can be formed on the same plane.

[0241] Next, referring to FIG. 11, a transistor 260 having a different configuration from the transistor 250 will be described. FIG. 11A shows a semiconductor device in which an oxide semiconductor is used for a semiconductor layer in which a channel is formed. 11B is a top view of a transistor 260, and FIG. 11B is a top view of the V1-V2 transistor in FIG. FIG. 11(C) is a cross-sectional view of the portion indicated by the dashed line. FIG. 11(A) is a cross-sectional view of the portion indicated by the dashed line. 1 is a cross-sectional view of a portion indicated by a dashed line in FIG.

[0242] The transistor 260 and the transistor 250 have different configurations of the drain electrode 206. The transistor 250 has a structure in which the entire periphery of the end of the oxide semiconductor layer 204 is covered with the drain electrode 206. However, in the transistor 260, a part of an edge of the oxide semiconductor layer 204 is used as a drain electrode. In addition, the source electrode 205 or the drain electrode 206 is not covered with the The structure in which one side of the gate electrode 206 is surrounded by the gate electrode 208 or the channel forming region 204a is It is the same as transistor 250.

[0243] By using the structure shown in the transistor 260, the area occupied by the transistor can be reduced. In addition, the transistor 260 also has an end portion of the oxide semiconductor layer 204 that is a drain electrode. Since the source electrode 205 and the drain electrode 206 are in contact with each other, the source electrode 205 and the drain electrode 206 are not parasitic transistors. The end of the oxide semiconductor layer 204 is not electrically connected to the source By configuring the electrode 205 so that it does not reach the drain electrode 206, the power consumption is reduced. Therefore, a transistor having good thermal characteristics can be realized.

[0244] Next, an example of a method for manufacturing the transistor 250 and the capacitor 255 will be described with reference to FIGS. 12 is a top view illustrating a method for manufacturing a transistor 250. 13 and 14 are cross-sectional views illustrating a method for manufacturing a transistor 250 and a capacitor 255. It is.

[0245] First, wiring 202 is formed on a substrate 201, and an insulating layer 203 is formed on the wiring 202. 12(A) and 13(A). There is no significant restriction on the substrate that can be used for the substrate 201. Although there is no particular limitation, it is necessary that the material has at least a heat resistance sufficient to withstand subsequent heat treatment. For example, glass substrates, ceramic substrates, single crystal semiconductors such as silicon and silicon carbide, Solid substrates, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI substrates In addition, a plastic substrate or the like that has heat resistance sufficient to withstand the processing temperature of this manufacturing process is used. In addition, the substrate on which the semiconductor element is provided is called the substrate 201. It may also be used as such.

[0246] The glass substrate may be, for example, barium borosilicate glass, aluminoborosilicate glass, or Alternatively, a non-alkali glass substrate such as an aluminosilicate glass substrate may be used. A sapphire substrate or the like can be used. In addition, the substrate 201 can be a flexible substrate (a flexible substrate). When a flexible substrate is used, a transistor is formed on the flexible substrate. The transistor 250 may be directly fabricated, or may be fabricated on another fabrication substrate and then After the formation, the semiconductor device may be peeled off and transferred to a flexible substrate. In order to prevent this, a separation layer is preferably provided between the formation substrate and the transistor. The substrate 201 is made of aluminoborosilicate glass.

[0247] A conductive layer that will later become wiring 202 is formed on a substrate 201 by sputtering, vacuum deposition, or The conductive layer is formed by plating. (Cu), Tantalum (Ta), Titanium (Ti), Molybdenum (Mo), Tungsten (W ), neodymium (Nd), scandium (Sc), the above-mentioned metallic elements The insulating layer 10 can be formed by using an alloy material containing the above-mentioned metal elements, a nitride material of the above-mentioned metal elements, etc. In addition, manganese (Mn), magnesium (Mg), zirconium (Zr), beryllium (Brylium), Materials containing one or more metal elements selected from the group consisting of fluorine (Al), fluorine (Be), and fluorine (Br) may also be used. In addition, semiconductors such as polycrystalline silicon containing impurity elements such as phosphorus, nickel silicon Silicide such as silicide may also be used.

[0248] The conductive layer to be the wiring 202 may have a single-layer structure or a stacked structure of two or more layers. For example, a single layer structure using aluminum containing silicon, or a titanium layer on aluminum A two-layer structure with titanium on titanium nitride, a two-layer structure with tungsten on titanium nitride, Two-layer structure with tungsten laminated on tantalum nitride, two-layer structure with tungsten laminated on tantalum nitride, Cu-Mg-A l Two-layer structure with copper laminated on alloy, copper laminated on titanium nitride, and tungsten on top of that The three-layer structure that forms the tantalum nitride is layered on top of the tungsten. By using copper for the conductive layer that becomes the wiring 202, the wiring 2 The wiring resistance of 02 can be reduced. In addition, copper can be replaced with tungsten, molybdenum, or tungsten. By laminating with high melting point metals such as tantalum or their nitrides, it is possible to prevent copper from diffusing into other layers. can.

[0249] The conductive layer to be the wiring 202 is made of indium tin oxide or indium containing tungsten oxide. Indium oxide, indium zinc oxide with tungsten oxide, indium zinc oxide with titanium oxide Indium tin oxide, titanium oxide, indium zinc oxide, silicon oxide A light-transmitting conductive material such as doped indium tin oxide can also be used. In addition, the conductive material having the light transmitting property and the material containing the metal element may be laminated. It is also possible.

[0250] In this embodiment, a conductive layer that becomes the wiring 202 is formed by sputtering to a thickness of 100 nm of tungsten.

[0251] Next, a portion of the conductive layer that will become the wiring 202 is selectively etched to form the wiring 202 ( A portion of the conductive layer is selectively etched to form a wiring (including other wiring formed in the same layer). In this case, a resist mask is formed on the conductive layer, and a dry etching method or a wet etching method is used. The unnecessary portion of the conductive layer may be removed by etching the conductive layer. Alternatively, both the hot etching method and the wet etching method may be combined. The resist mask is formed by appropriately using a photolithography method, a printing method, an inkjet method, or the like. If the resist mask is formed by the inkjet method, a photomask can be used. This reduces the manufacturing cost.

[0252] When the conductive layer is etched by dry etching, a halogen gas is used as the etching gas. A gas containing a halogen element can be used. An example of a gas containing a halogen element is chlorine ( Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4) or carbon tetrachloride (C Chlorine gases such as Cl4, carbon tetrafluoride (CF4), sulfur hexafluoride (SF6 ), nitrogen trifluoride (NF3) or trifluoromethane (CHF3) are typical examples. Fluorine-based gas, hydrogen bromide (HBr) or oxygen can be used as appropriate. An inert gas may be added to the etching gas. Using the reactive ion etching (RIE) method It is possible.

[0253] In addition, a capacitively coupled plasma (CCP) was used as the plasma source. Inductively Coupled Plasma (ICP) Coupled Plasma, Electron Cyclotron Resonance (ECR) Cyclotron Resonance plasma, Helicon wave excited plasma (HW P: Helicon Wave Plasma, Microwave Excited Surface Wave Plasma (SW P: Surface Wave Plasma) can be used. In particular, IC P, ECR, HWP, and SWP can generate high density plasma. The etching method (hereinafter also referred to as "dry etching process") is The etching conditions (power applied to the coil-shaped electrode) were adjusted so that the processed shape could be etched. The amount of heat generated, the amount of power applied to the electrode on the substrate side, the temperature of the electrode on the substrate side, etc. are appropriately adjusted.

[0254] Note that a resist mask of any shape is formed on the conductive layer or the insulating layer by photolithography. The process of forming the resist mask is called the photolithography process. In many cases, a step of etching and a step of removing the resist mask are performed. The photolithography process includes a resist mask forming process and an etching process for a conductive layer or an insulating layer. The process may include an etching step and a resist mask stripping step.

[0255] Next, an insulating layer 203 is formed over the wiring 202 (see FIG. 13A).

[0256] The insulating layer 203 is formed by a sputtering method, an MBE method, a CVD method, a pulsed laser deposition method, or an ALD method. The method can be appropriately used to form the ferroelectric thin film. The insulating layer 203 may be formed by a high density plasma CVD method. This is done by setting multiple substrate surfaces roughly perpendicular to the sputtering target surface. Alternatively, the film may be formed by using a sputtering device.

[0257] The material of the insulating layer 203 is aluminum nitride, aluminum oxide, aluminum oxynitride, etc. Aluminum, aluminum oxide nitride, gallium oxide, silicon nitride, silicon oxide, silicon nitride oxide A material selected from silicon or silicon oxynitride is formed in a single layer or in a multilayer structure. can be done.

[0258] The insulating layer 203 contains oxygen in a portion that is in contact with the oxide semiconductor layer 204 to be formed later. Furthermore, the insulating layer 203 in contact with the oxide semiconductor layer 204 is preferably It is preferred that oxygen is present in at least an amount exceeding the stoichiometric composition in the stoichiometric composition. For example, When silicon oxide is used as the insulating layer 203, SiO 2+α (where α>0) In this embodiment, the insulating layer 203 is made of SiO 2+α (However, α>0) When the silicon oxide is in contact with the oxide semiconductor layer 204, the oxide This allows oxygen to be supplied to the oxide semiconductor layer 204, improving the electrical characteristics of the transistor. It is possible.

[0259] The insulating layer 203 is made of the insulating layer containing excess oxygen as described above, silicon nitride or aluminum oxide. Impurities such as hydrogen, water, hydrides, or hydroxides, and barriers to oxygen, such as nium Alternatively, a lamination of insulating layers (hereinafter also referred to as barrier layers) formed of a material having adhesive properties may be used. By forming the film from a material with barrier properties, it is possible to prevent the above-mentioned impurities from entering from the substrate side. In this way, it is possible to prevent oxygen contained in the insulating layer that contains an excess of oxygen from diffusing toward the substrate side.

[0260] In this embodiment, a 200 mm thick insulating layer 203 is formed on a substrate 201 by plasma CVD. The insulating layer 203 is formed at a temperature of 1000 nm. The higher the temperature, the higher the temperature is preferably within the temperature that the substrate 201 and the wiring 202 can withstand. The insulating layer 203 is formed by heating the insulating layer 203 to a temperature of 350° C. or more and 450° C. or less. It is preferable that the temperature during the formation of the insulating layer 203 is constant. The plate is heated to 350°C.

[0261] After the insulating layer 203 is formed, the insulating layer 203 is dried under reduced pressure, a nitrogen atmosphere, a rare gas atmosphere, or an ultra-dry atmosphere. Heat treatment may be performed under a nitrogen atmosphere. The concentration of hydrogen, water, hydrides, hydroxides, etc. that are present in the gas can be reduced. The temperature is preferably higher than the temperature that the substrate 201 and the wiring 202 can withstand. Specifically, the heating is preferably performed at a temperature equal to or higher than the film-forming temperature of the insulating layer 203 and lower than the distortion point of the substrate 201. preferable.

[0262] After the insulating layer 203 is formed, the insulating layer 203 is subjected to oxygen doping treatment. Note that the oxygen doping treatment for the insulating layer 203 may be performed after the heat treatment. The above-mentioned heat treatment and oxygen doping treatment may be repeated several times. . The heat treatment and the oxygen doping treatment may be alternately repeated several times.

[0263] Next, an oxide semiconductor layer 214 (which will later become the oxide semiconductor layer 204) (as shown in FIG. 1) is formed on the insulating layer 203. The layer (not shown) is formed by sputtering.

[0264] Note that the oxide semiconductor layer 214 is formed using the same material as the oxide semiconductor disclosed in the above embodiment. The present invention can be formed by the above-mentioned method and method.

[0265] Note that the oxide semiconductor layer 214 is formed under conditions in which a large amount of oxygen is contained. or in a state where oxygen is supersaturated (preferably in a stoichiometric state where the oxide semiconductor is in a crystalline state). It is preferable that the composition contains a region having an excessive amount of oxygen.

[0266] For example, in the case where an oxide semiconductor layer is formed by a sputtering method, a sputtering gas It is preferable to carry out the sputtering under conditions where the proportion of oxygen is high, and the sputtering gas is oxygen gas 1 It is preferable to use a sputtering gas with a concentration of oxygen of 0.001%. When the film is formed under certain conditions, particularly when the film is formed using 100% oxygen gas, the film is not formed even if the film formation temperature is set to 300°C or higher. This suppresses the release of Zn from the nitride semiconductor layer.

[0267] In addition, prior to the formation of the oxide semiconductor layer 214, the oxide semiconductor layer 214 of the insulating layer 203 is bonded to the insulating layer 203. A planarization process may be performed on the region formed by the above process.

[0268] The oxide semiconductor layer 214 contains almost no impurities such as copper, aluminum, or chlorine. It is desirable to use highly purified materials that are not subject to the effects of chemical reactions during the manufacturing process of transistors. It is necessary to appropriately select a process in which there is no risk of these impurities being mixed in or adhering to the surface of the oxide semiconductor layer. Specifically, the copper concentration in the oxide semiconductor layer is preferably 1×10 18 atoms / cm 3 Less than or equal to 1×10 17 atoms / cm 3 In addition, the oxide semiconductor layer The aluminum concentration in 18 atoms / cm 3 The following applies. In addition, oxide semiconductors The chlorine concentration in the body layer is 2 x 10 18 atoms / cm 3 The following applies.

[0269] In addition, sodium (Na), lithium (Li), and potassium (K ) The concentration of alkali metals such as Na is 5×10 16 atoms / cm 3 The following is preferably is 1×10 16 atoms / cm 3 Less than 1×10, more preferably 15 atoms / c m 3 In the following, Li is 5×10 15 atoms / cm 3 Less than or equal to 1×10 15 ato ms / cm 3 In the following, K is 5×10 15 atoms / cm 3 Less than or equal to 1×10 15 atoms / cm 3 The following applies.

[0270] In this embodiment, the oxide semiconductor layer 214 is formed by a sputtering device having an AC power supply. A 35 nm thick In-Ga-Zn oxide was deposited by sputtering using a ring device. The target for fabricating the film by sputtering has the following composition: A metal oxide target with an atomic ratio of In:Ga:Zn=1:1:1 is used.

[0271] First, the substrate 201 is held in a film-forming chamber that is maintained in a reduced pressure state. While removing moisture, a sputtering gas from which hydrogen and moisture have been removed is introduced, and the above target is used. The oxide semiconductor layer 214 is formed over the insulating layer 203. For this purpose, adsorption type vacuum pumps, such as cryopumps, ion pumps, titanium sublimation pumps, etc. It is preferable to use a displacement pump as the exhaust means. A cold trap may be added to the vacuum chamber. The chamber may be filled with, for example, hydrogen atoms, water (HO) or other compounds containing hydrogen atoms (more preferably carbon Since the oxide semiconductor layer 214 formed in the deposition chamber is exhausted, The concentration of impurities contained in the material can be reduced.

[0272] Alternatively, the insulating layer 203 and the oxide semiconductor layer 214 may be formed in succession without being exposed to the air. When the insulating layer 203 and the oxide semiconductor layer 214 are successively formed without exposure to air, This makes it possible to prevent impurities such as hydrogen and water from adhering to the surface of the layer 203 .

[0273] Next, a part of the oxide semiconductor layer 214 is selectively etched by a photolithography process. An island-shaped oxide semiconductor layer 204 is formed (see FIG. 12B and FIG. 13B). A resist mask for forming the oxide semiconductor layer 204 is formed by an ink-jet method. If the resist mask is formed by the inkjet method, a photomask is not required. This reduces manufacturing costs.

[0274] Note that the oxide semiconductor layer 214 can be etched by either dry etching or wet etching. The oxide semiconductor layer 21 may be removed by a wet etching method or a wet etching method. When etching step 4, the etching solution is a mixture of phosphoric acid, acetic acid, and nitric acid, A solution containing oxalic acid can be used. ITO-07N (manufactured by Kanto Chemical Co., Ltd.) In addition, when the oxide semiconductor layer is etched by a dry etching method, For example, a dry etching method using a high-density plasma source such as ECR or ICP is used. In addition, dry etching is a method that can easily achieve uniform discharge over a wide area. As a method, ECCP (Enhanced Capacitively Coupled There is a dry etching method using the plasma mode. For example, it can also be used for 10th generation substrates over 3m in size. It is possible.

[0275] In addition, after the oxide semiconductor layer 204 is formed, excess hydrogen (water or hydroxide) in the oxide semiconductor layer 204 is removed. Heat treatment may be performed to remove (dehydrate or dehydrogenate) the aryl groups (including the aryl groups). The temperature of the heat treatment should be between 300°C and 700°C, or below the distortion point of the substrate. The heating can be performed under pressure or in a nitrogen atmosphere. The substrate is placed in a furnace, and the oxide semiconductor layer 204 is heated in a nitrogen atmosphere at 450° C. for 1 hour. The heat treatment is carried out.

[0276] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heating element such as a resistance heating element. A device that heats the workpiece by radiation may be used. For example, a GRTA (Gas Reactor Transformer) apid Thermal Anneal) equipment, LRTA (Lamp Rapid T RTA (Rapid Thermal Anneal) equipment, etc. al) equipment can be used. The LRTA equipment can be a halogen lamp, a metal halide lamp, lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure mercury lamp This is a device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp or other light source. The GRTA device is a device that uses high-temperature gas to perform heat treatment. Inert gases such as argon or nitrogen that do not react with the workpiece during heat treatment An active gas is used.

[0277] For example, the substrate is placed in an inert gas heated to a high temperature of 650°C to 700°C as a heat treatment. After heating for several minutes, GRTA may be performed in which the substrate is taken out of the inert gas.

[0278] In the heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen or hydrogen introduced into the heat treatment device is not included. The purity of rare gases such as sodium, neon, and argon is preferably 6N (99.9999%) or higher. is 7N (99.99999%) or more (i.e. impurity concentration is 1 ppm or less, preferably 0.1 It is preferable to set the concentration to less than ppm.

[0279] After the oxide semiconductor layer 204 is heated by heat treatment, high-purity oxygen gas, High purity nitrous oxide gas or ultra-dry air (Cavity Ring Down Spectroscopy (CRDS) A dew point meter using Cavity Ring-Down Spectroscopy (Cavity Ring-Down Spectroscopy) was used. The moisture content measured at 20 ppm (-55°C in terms of dew point) or less, preferably 1 ppm m or less, more preferably 10 ppb or less of air) may be introduced. It is preferable that the dinitrogen gas does not contain water, hydrogen, etc. The purity of the oxygen gas or nitrous oxide gas to be used is 6N or more, preferably 7N or more (i.e., The impurity concentration in the nitrogen gas or dinitrogen monoxide gas is 1 ppm or less, preferably 0.1 ppm. It is preferable to use the following method. The action of oxygen gas or nitrous oxide gas causes dehydration or The oxide semiconductor that was reduced during the dehydrogenation process was By supplying oxygen, which is the main component of the oxide semiconductor, oxygen vacancies in the oxide semiconductor are reduced. Thus, the oxide semiconductor layer 204 can be made i-type (intrinsic) or substantially i-type.

[0280] The heat treatment for dehydration or dehydrogenation can be performed after the formation of the oxide semiconductor layer. This may be performed before or after the formation of the organic semiconductor layer 204. The heat treatment for hydrogenation may be carried out multiple times, or may be carried out in combination with another heat treatment.

[0281] In addition, oxygen, which is a main component material of an oxide semiconductor, can be removed by the dehydration or dehydrogenation treatment. In the oxide semiconductor layer, oxygen is released and the amount of oxygen is reduced. At these locations, oxygen vacancies exist, and these oxygen vacancies cause fluctuations in the electrical characteristics of the transistor. This results in a level of noise.

[0282] For this reason, the oxide semiconductor layer 204 that has been subjected to the dehydration or dehydrogenation treatment is subjected to oxygen doping treatment. In this case, oxygen may be supplied to the oxide semiconductor layer 204.

[0283] Oxygen is introduced into the oxide semiconductor layer 204 that has been subjected to dehydration or dehydrogenation treatment. By supplying the product, the impurity removal process by dehydration or dehydrogenation treatment can be performed. In addition, oxygen vacancies in the oxide semiconductor are reduced, and the oxide semiconductor layer 204 becomes i-type (intrinsic). The transistor having the i-type (intrinsic) oxide semiconductor layer 204 has the following electrical characteristics: Fluctuations are suppressed and the device is electrically stable.

[0284] In the case where oxygen is introduced into the oxide semiconductor layer 204, oxygen doping treatment is performed directly on the oxide semiconductor layer 204. The bonding may be performed directly or via another layer.

[0285] In addition, the oxygen doping treatment reduces the bonds between the elements constituting the oxide semiconductor layer 204 and hydrogen, Alternatively, the bond between the element and the hydroxyl group is broken and the hydrogen or hydroxyl group is replaced by oxygen. Therefore, when heat treatment is performed after oxygen doping, water is generated by reacting with Therefore, hydrogen or a hydroxyl group is easily released as water. After the oxygen is introduced, heat treatment may be performed. Alternatively, oxygen may be introduced into the oxide semiconductor layer 204 to make the oxide semiconductor layer 204 have an excess of oxygen. The oxygen doping treatment and the heat treatment of the layer 204 may be alternately performed multiple times. Alternatively, the heat treatment and the oxygen doping treatment may be carried out simultaneously.

[0286] In this manner, impurities such as hydrogen are sufficiently removed from the oxide semiconductor layer 204, and thus the oxide semiconductor layer 204 has a high thermal conductivity. The oxide semiconductor layer 204 is purified and a sufficient amount of oxygen is supplied thereto, so that oxygen vacancies in the oxide semiconductor layer 204 are reduced. It is preferable that the material is i-type (intrinsic) or substantially i-type (intrinsic) by the above-mentioned method. I wish.

[0287] Highly purified oxide with reduced impurities such as water or hydrogen, which act as electron donors The purified OS then supplies oxygen to the oxide semiconductor to oxidize it. By reducing oxygen vacancies in the semiconductor, it is possible to obtain an i-type (intrinsic) oxide semiconductor or an i-type In this case, the oxide semiconductor is substantially i-type. A transistor using an i-type or substantially i-type oxide semiconductor for a semiconductor layer is It has the characteristic of having an extremely low leakage current.

[0288] Specifically, the hydrogen concentration in the highly purified oxide semiconductor layer was measured by SIMS. The value is 5 x 10 19 atoms / cm 3 Less than or equal to 5×10 18 atoms / cm 3 Less than or equal to 5×10 17 atoms / cm 3 The following applies. In addition, oxide semiconductors In order to supply sufficient oxygen to the oxide semiconductor layer 204 so that the oxide semiconductor layer 204 is in a supersaturated state, It is preferable to sandwich 04 in contact with an insulating layer containing a large amount of oxygen.

[0289] In addition, the hydrogen concentration in the insulating layer, which contains a lot of oxygen, is also important because it affects the characteristics of the transistor. The hydrogen concentration in the oxygen-rich insulating layer is 7.2×10 20 atoms / cm 3 That's it In some cases, the variation in the initial characteristics of the transistor increases, the L length dependency increases, and the B The hydrogen concentration in the insulating layer, which contains a lot of oxygen, is 7. 2×10 20 atoms / cm 3 That is, the hydrogen concentration in the oxide semiconductor layer is set to be less than 5×1 0 19 atoms / cm 3 The hydrogen concentration in the insulating layer containing a large amount of oxygen is 7.2×1 0 20 atoms / cm 3 It is preferable that the amount is less than 100 μm.

[0290] Here, we will discuss SIMS analysis of hydrogen concentration. It is difficult to obtain accurate data near the surface of the material or near the interface between layers of different materials. It is known that the hydrogen concentration distribution in the layer in the thickness direction was analyzed by SIMS. When doing so, the value should not fluctuate dramatically within the range in which the target layer exists, and should be approximately constant. The average value in the region where the hydrogen concentration is obtained is adopted as the hydrogen concentration. When the thickness of is small, it is affected by the hydrogen concentration in the adjacent layers and obtains a nearly constant value. In this case, the hydrogen concentration in the region where the layer exists may not be found. The maximum or minimum value is adopted as the hydrogen concentration in the layer. In the region, there is no mountain-shaped peak having a maximum value and no valley-shaped peak having a minimum value. In this case, the value at the inflection point is adopted as the hydrogen concentration.

[0291] Next, the oxide semiconductor layer 204 and the Then, a part of the insulating layer 203 is selectively etched to form an opening 213 reaching the wiring 202. (See FIG. 12(C) and FIG. 13(C)). In addition, a resist mask for forming the opening 213 is The resist mask may be formed by an ink-jet method. In this case, a photomask is not used, and therefore manufacturing costs can be reduced. The etching of the insulating layer 203 may be performed by either dry etching or wet etching. , or both may be used.

[0292] Next, a source electrode 205 and a source electrode 206 are formed on the oxide semiconductor layer 204 by a photolithography process. The drain electrode 206 and the capacitance electrode 221 (not shown in FIG. 12) are formed in the same layer. A source electrode 205 and a drain electrode 206 are formed (including wiring) (see FIG. 12(D) and FIG. 13(D)). The drain electrode 206 and the capacitance electrode 221 are formed using the same material and method as the wiring 202. It is possible.

[0293] In this embodiment, a source electrode 205, a drain electrode 206, and a capacitance electrode 221 are formed. A 200 nm thick titanium layer is formed by sputtering to serve as a conductive layer for this purpose. The conductive layer is etched using, for example, an etching gas (BCl3:Cl2=750 sccm: 150sccm), bias power is 1500W, ICP power supply power is 0W, This can be performed by ICP etching at a pressure of 2.0 Pa.

[0294] Furthermore, etching for forming the source electrode 205 and the drain electrode 206 is completed. Then, a cleaning treatment (impurity removal) is performed to remove impurities attached to the surface of the oxide semiconductor layer 204. It is preferable to carry out a removal treatment.

[0295] By carrying out impurity removal processing, highly reliable transistors with stable electrical characteristics can be realized. It can be realized.

[0296] Next, a source electrode 205 and a drain electrode 206 are formed in contact with a part of the oxide semiconductor layer 204. An insulating layer 207 is formed on the insulating layer 203 (see FIG. 13(E)). The insulating layer 207 can be formed by the same material and method as the gate of the transistor 250. It also functions as a dielectric of the capacitor element 255.

[0297] A capacitance element has a structure in which a dielectric is sandwiched between two opposing electrodes. The thinner the dielectric, the (The shorter the distance between the two opposing electrodes, the greater the dielectric constant of the dielectric material.) However, if the dielectric is made thinner to increase the capacitance of the capacitive element, the This increases the leakage current between the capacitor and the dielectric strength of the capacitor element. do.

[0298] The overlapping portion of the gate electrode, gate insulating layer, and semiconductor layer of the transistor serves as a capacitance element. The gate capacitance of the semiconductor layer is A channel is formed in the region overlapping the gate electrode. The formation region functions as two electrodes of the capacitance element, and the gate insulating layer functions as the dielectric of the capacitance element. It is preferable to have a large gate capacitance, but to increase the capacitance, If the insulating layer is made thinner, problems such as the increase in leakage current and the decrease in dielectric strength may occur. water.

[0299] Therefore, the insulating layer 207 is made of hafnium silicate (HfSi x O y (x>0, y>0 )), nitrogen-doped hafnium silicate (HfSi x O y N z(x>0, y>0, z>0), nitrogen-doped hafnium aluminate (HfAl x O y N z (x>0, y>0, z>0) (hafnium oxide, yttrium oxide, etc.) Therefore, even if the insulating layer 207 is made thick, the capacitance value between the gate electrode 208 and the oxide semiconductor layer 204 is It will be possible to ensure sufficient

[0300] For example, if a high-k material with a large dielectric constant is used as the insulating layer 207, the insulating layer 207 Even if the thickness is increased, the same capacitance value as that in the case where silicon oxide is used for the insulating layer 207 can be realized. Therefore, leakage current occurring between the gate electrode 208 and the oxide semiconductor layer 204 can be reduced. This can reduce the leakage current occurring between the capacitance electrode 222 and the capacitance electrode 221. The wiring formed using the same layer as the pole 208 and another wiring overlapping the wiring The leakage current can be reduced. The insulating layer 207 is made of a high-k material and another insulating material. A laminated structure may also be used.

[0301] Note that the insulating layer 207 preferably contains oxygen in a portion in contact with the oxide semiconductor layer 204. In this embodiment, the insulating layer 207 in contact with the oxide semiconductor layer 204 is preferably It is preferred that there is at least a stoichiometric excess of oxygen (in the bulk). For example, when silicon oxide is used as the insulating layer 207, SiO 2+α (however, In this embodiment, the insulating layer 207 is made of SiO 2+α (However, α> 0) is used as the insulating layer 207. In this case, oxygen can be supplied to the oxide semiconductor layer 204, so that the characteristics of the oxide semiconductor layer 204 can be improved.

[0302] The insulating layer 207 is made of the insulating layer containing excess oxygen as described above, silicon nitride, aluminum oxide, etc. Impurities such as hydrogen, water, hydrides, or hydroxides, and barriers to oxygen, such as nium It is preferable that the oxide semiconductor layer 20 be a laminate of insulating layers made of a material having an oxidizing property. An insulating layer containing excess oxygen is formed in contact with 4, and the insulating layer containing excess oxygen has a barrier property. By stacking the insulating layer, impurities can be prevented from entering the oxide semiconductor layer 204 and the oxide semiconductor layer 204 can be prevented from being oxidized. In this way, oxygen contained in the insulating layer containing excess oxygen can be effectively supplied to the oxide semiconductor layer 204. can.

[0303] In addition, before forming the insulating layer 207, oxygen, nitrous oxide, or a rare gas (typically The plasma treatment using argon etc. removes moisture and organic matter from the surface of the substrate. It is preferable to remove any impurities.

[0304] After the insulating layer 207 is formed, the insulating layer 207 is subjected to oxygen doping treatment. Alternatively, after the insulating layer 207 is formed and before the oxygen doping process, the pressure may be reduced. Heat treatment under nitrogen, rare gas, or ultra-dry air nitrogen atmosphere The hydrogen, water, hydride, or water contained in the insulating layer 207 may be removed by heat treatment. The concentration of oxides and the like can be reduced. The heat treatment temperature is set to a temperature that the substrate 201 can withstand. It is preferable to perform the process at a temperature higher than the deposition temperature of the insulating layer 207. , preferably below the strain point of the substrate 201.

[0305] In addition, the insulating layer 207 containing a large amount (excessive amount) of oxygen, which serves as an oxygen supply source, is formed on the oxide semiconductor layer 20 4, and then the heat treatment is performed to convert the insulating layer 207 into an oxide semiconductor layer. Oxygen can be supplied to 204.

[0306] By supplying oxygen to the oxide semiconductor layer 204, oxygen vacancies in the oxide semiconductor layer 204 are reduced. The thickness of the insulating layer 207 is preferably 1 nm or more and 50 nm or less. The thickness of the insulating layer 207 depends on the size of the transistor to be manufactured, the source electrode 205, the drain electrode It may be determined taking into consideration the step coverage of the electrode 206 and the capacitance electrode 221.

[0307] Next, the gate electrode 208 and the capacitor electrode 222 are formed (other electrodes formed in the same layer). (including wiring) (see FIG. 12(E) and FIG. 14(A)). The gate electrode 208 and the capacitance electrode 22 2 is the same as the wiring 202, the source electrode 205, the drain electrode 206, and the capacitance electrode 221. The material and method can be used to form the above-mentioned insulating film.

[0308] In this embodiment, a tungsten film having a thickness of 100 nm is used to form the gate electrode 208 and the capacitor. A quantity electrode 222 is formed.

[0309] Next, a dopant 231 is introduced into the oxide semiconductor layer 204 using the gate electrode 208 as a mask. Then, low resistance regions 204b and 204c are formed (FIG. 12(F), FIG. 14(B)). reference).

[0310] The dopant 231 is an impurity element that changes the electrical conductivity of the oxide semiconductor layer 204. As the arsenic 231, group 15 elements (typically phosphorus (P), arsenic (As), and Antimony (Sb), Boron (B), Aluminum (Al), Tungsten (W), Molybdenum (Mo) Butan (Mo), Nitrogen (N), Argon (Ar), Helium (He), Neon (Ne), Indium (In), Gallium (Ga), Fluorine (F), Chlorine (Cl), Titanium (Ti) and zinc (Zn).

[0311] The method of introducing the dopant 231 includes ion implantation, ion doping, plasma ion implantation, etc. In this case, the dopants are implanted in the cavity. It is preferable to use the elemental ion of PANT 231 or fluoride or chloride ions.

[0312] In this embodiment, the dopant 231 is oxidized through the insulating layer 207 by ion implantation. The dopant 231 is introduced into the semiconductor layer 204. The introduction step of the dopant 231 is carried out in consideration of the thickness of the layer through which the dopant passes. In this embodiment, the accelerating voltage and the dose amount are appropriately set. Phosphorus is used as the dopant 31, and phosphorus ions are implanted by ion implantation. The dose of 31 is 1×10 13 ions / cm 2 5×10 or more 16 ions / cm 2 below This can be done as follows.

[0313] The concentration of dopant 231 in the low resistance region is 5×10 18 / cm 3 More than 1×10 22 / cm 3 It is preferable that:

[0314] Furthermore, the dopant 231 may be introduced while the substrate 201 is being heated.

[0315] Note that the treatment of introducing the dopant 231 into the oxide semiconductor layer 204 may be performed multiple times. A plurality of types of dopants 231 may be used.

[0316] After the dopant 231 is introduced, a heat treatment may be performed. The temperature is 300°C to 700°C, preferably 300°C to 450°C, for 1 hour in an oxygen atmosphere. It is preferable to carry out the heating under nitrogen atmosphere, reduced pressure, or air (ultra-dry air). Processing may be carried out.

[0317] In this embodiment, phosphorus (P) ions are implanted into the oxide semiconductor layer 204 by ion implantation. The phosphorus (P) ion implantation conditions were an acceleration voltage of 30 kV and a dose of 1.0×1. 0 15 ions / cm 2 Let us assume that.

[0318] Note that when a crystalline oxide semiconductor is used for the oxide semiconductor layer 204, the dopant 23 The introduction of 1 may cause some of the material to become amorphous.

[0319] By introducing the dopant 231, a low resistance region 204b is formed on both sides of the channel forming region 204a. Thus, an oxide semiconductor layer 204 including a low-resistance region 204c is formed.

[0320] Next, an insulating layer 209 is formed on the insulating layer 207, the gate electrode 208, and the capacitance electrode 222. The insulating layer 209 is formed in the same manner as the insulating layer 203 or the insulating layer 207 (see FIG. 14C). For example, the insulating layer 209 can be formed of silicon oxide or The insulating film 11 can be formed by sputtering or CVD using a material such as silicon oxynitride. Alternatively, the insulating layer 209 may be subjected to oxygen doping treatment to become an insulating layer containing excess oxygen.

[0321] In addition, the insulating layer 209 is formed to be resistant to both impurities such as hydrogen and water and oxygen in the transistor. It is made of a material with high barrier properties that prevents the passage of The insulating layer 209 may be a layer formed by arranging the insulating layer 209 in a manner similar to that described above. and a barrier layer may be laminated.

[0322] The barrier layer forms a metal layer that becomes a metal oxide when oxygen is introduced, for example. It is also possible to form the metal oxide layer by performing oxygen doping treatment on the metal layer. Metal materials include aluminum, magnesium-added aluminum, and titanium. The aluminum doped with ruthenium, the aluminum in contact with the insulating layer 207, and the aluminum A laminate of magnesium or aluminum on the insulating layer 207 and Abutting titanium laminations, etc. may be used.

[0323] After the insulating layer 209 is formed, heat treatment may be performed. The temperature of the heat treatment is, for example, 250° C. or higher. The heating temperature can be set to 600°C or lower, preferably 300°C or higher and 600°C or lower.

[0324] Through the above steps, the transistor 250 is formed. In this embodiment, a flat insulating layer is formed on the transistor 260. An example of forming a photo-insulating layer 210 is shown (see FIG. 14(D)).

[0325] The planarization insulating layer 210 may be, for example, polyimide, acrylic resin, or benzocyclobutene resin. Heat-resistant organic insulating materials such as grease, polyamide, and epoxy resin can be used. In addition to the above organic insulating materials, low-k materials, siloxane resins, Use a single layer or multilayer of PSG (phosphorus glass), BPSG (borophosphorus glass), etc. can be done.

[0326] In addition, the planarization insulating layer 210 is formed by chemical mechanical polishing (CMP) after the insulating layer is formed. Alternatively, the insulating layer 14 may be formed by a planarization process such as a metal polishing process.

[0327] Note that in the transistor described in this embodiment, the oxide semiconductor layer 204 is a CAAC-OS This is particularly useful when using a CAAC-OS film. etc.

[0328] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0329] (Embodiment 4) In this embodiment, the transistor 250 and the transistor 260 disclosed in the third embodiment are A transistor having a different structure will be described with reference to FIGS. 15 and 16. 5 (A1) is a transistor 27 using an oxide semiconductor for a semiconductor layer in which a channel is formed. 15(B1) is a plan view (top view) of FIG. 15(A1) showing the W1-W FIG. 15(A2) is a cross-sectional view of the area indicated by the dashed line in FIG. 1 shows a plan view of a transistor 280 using an oxide semiconductor for a semiconductor layer in which a channel is formed. FIG. 15(B2) is a top view of the Z1-Z2 chain line shown in FIG. 15(A2). FIG. 15( In FIG. 15(A1) and FIG. 15(A2), some components are omitted.

[0330] The transistor 270 has a configuration in which the shape of the gate electrode 208 is different from that of the transistor 250. In addition, the transistor 280 differs from the transistor 260 in the shape of the gate electrode 208. Specifically, the transistor 270 and the transistor 280 have a gate An electrode 208 is formed so as to overlap the source electrode 205 and the drain electrode 206. In addition, when viewed from above, one of the source electrode 205 and the drain electrode 206 is a channel electrode. The configuration surrounded by the configuration region 204 a is the same as that of the transistor 250 and the transistor 260 .

[0331] With this structure, the source electrode 205 in the oxide semiconductor layer 204 is in contact with The region from the drain electrode 206 to the drain electrode 207 can be used as a channel forming region. Therefore, the process for forming the low resistance region 204b and the low resistance region 204c can be omitted. This makes it possible to improve the productivity of semiconductor devices.

[0332] The gate electrode 208 is overlapped with either the source electrode 205 or the drain electrode 206. 205 or 206 and the gate electrode 208. An offset region may be formed in the oxide semiconductor layer 204. By this, the gate electrode 208 and the other of the source electrode 205 or the drain electrode 206 are This can reduce electric field concentration between the gates and improve the reliability of the transistor.

[0333] Note that in the transistor 280, the gate electrode 208 is disposed at an end of the oxide semiconductor layer 204. It is not necessary to cover the entire circumference.

[0334] FIG. 16A illustrates a transistor 2 in which an oxide semiconductor is used for a semiconductor layer in which a channel is formed. 16(B) is a plan view (top view) of 90, and FIG. 16(A) shows Q1-Q2 1 is a cross-sectional view of a portion indicated by a dashed line in FIG. Therefore, some of the components are omitted in FIG.

[0335] The transistor 290 has a configuration different from the transistor 250 in plan view. The transistor 290 has a gate electrode 208, a source electrode 205, and a drain electrode 206, which are circular in shape. The gate electrode 208, the source electrode 205, and the drain electrode 206 are By arranging them in a circular shape, the distance from the source electrode 205 to the drain electrode 206 is Therefore, a current can be efficiently passed through the oxide semiconductor layer 204. Therefore, it is possible to realize a transistor with better electrical characteristics.

[0336] In addition, in FIG. 16, the source electrode 205 is divided into a source electrode 205a, a source electrode 205b, and a source The drain electrode 206 is a laminate of the drain electrode 206a, the drain electrode 206b, and the drain electrode 206c. In the example shown, the electrode 206b and the drain electrode 206c are laminated. The source electrode 205a and the drain electrode 206a are formed by a 50 nm thick tongue electrode. A stainless steel film was formed to a thickness of 400 nm as the source electrode 205b and the drain electrode 206b. A copper film having a thickness of 100 nm is formed as the source electrode 205c and the drain electrode 206c. A tantalum nitride film is formed.

[0337] By using copper for the source electrode 205 and the drain electrode 206, the wiring resistance is reduced. The source electrode 205a and the drain electrode 206a can be formed of tungsten. The source electrode 205b and the drain electrode 206b are made of copper. The source electrode 205c and the drain electrode 206b are made of tantalum nitride. By covering the electrode 206c, the copper used for the source electrode 205 and the drain electrode 206 is removed from the other layers. In addition, for example, the source electrode 205a and the drain electrode 205b can be prevented from diffusing into the The electrode 206a may be a tungsten nitride film or a laminate of tungsten and tungsten nitride. Good too.

[0338] Moreover, the wiring 202 and the gate electrode 208 may be formed as a laminated structure as described above.

[0339] In addition, in a plan view, one of the source electrode 205 and the drain electrode 206 is a channel type. The transistors 270, 280, and The transistor 290 is the same as the transistor 250 and the transistor 260. The end of the oxide semiconductor layer 204 does not reach from the source electrode 205 to the drain electrode 206. The configuration is also the same.

[0340] Therefore, the transistors 270, 280, and 290 are also transistors. Similar to the transistor 250 and the transistor 260, the source electrode 205 and the drain electrode 206 are Since there is no electrical connection through a parasitic channel, power consumption is low and electrical characteristics are However, it is possible to realize a transistor having a good characteristic.

[0341] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0342] (Embodiment 5) In this embodiment, a transistor having a different structure from the transistors disclosed in the above embodiment will be described. The structure and manufacturing method of a capacitor that can be manufactured simultaneously with a transistor are described. do.

[0343] FIG. 17A is a top view of a transistor 310 according to one embodiment of the present invention. 17(B) is a cross-sectional view taken along line E1-E2 in FIG. 17(A), and FIG. 17(C) is a cross-sectional view taken along line E1-E2 in FIG. 4 is a cross-sectional view taken along line E3-E4 shown in FIG.

[0344] The transistors shown in FIGS. 17A, 17B, and 17C are embedded in a first insulating layer 311. A first electrode 312, an oxide semiconductor layer 313 in contact with the first electrode, a second electrode 314 in contact with the oxide semiconductor layer; and a second insulating layer covering the oxide semiconductor layer and the second electrode. 315, and a third electrode 316 formed on the second insulating layer. A third insulating layer 317 is preferably provided as a protective film on the layer and the third electrode. Furthermore, a planarizing film 318 may be provided as necessary.

[0345] The transistors shown in FIGS. 17A, 17B, and 17C are field-effect transistors. The first electrode 312 is a source electrode, the second electrode 314 is a drain electrode, and the third electrode 316 is The second insulating layer 315 functions as a gate insulating layer, and the third insulating layer 316 functions as a gate electrode. The insulating layer 317 is formed by desorption of oxygen from the oxide semiconductor layer 313 and by absorbing hydrogen and other impurities from the oxide semiconductor layer. It functions as a protective film to prevent moisture from entering.

[0346] The first electrode 312 is embedded in the first insulating layer 311, and the first electrode 312 is One end of the transistor 312 is electrically connected to a wiring such as a power supply line or a signal line, or to another transistor. The other end of the first electrode 312 can be connected to the surface of the first insulating layer 311. The oxide semiconductor layer 313 is planarized so as to be continuous with the first surface of the oxide semiconductor layer 313. and is electrically connected to

[0347] The oxide semiconductor layer 313 is processed into an island shape, and a second electrode 314 is formed to cover the edge of the island. By covering the end of the oxide semiconductor layer 313 with the second electrode 314, This can provide the effect of suppressing the release of oxygen from the part.

[0348] The third electrode 316 is formed on the oxide semiconductor layer 313 via the second insulating layer 315. The third electrode has an annular top surface, the first electrode 312 is located inside the third electrode, and the outer A second electrode 314 is located on the side.

[0349] Here, in the oxide semiconductor layer 313, the third electrode 316 and the second electrode 314 overlap. The non-convoluted region has high resistance, and impurities are added to suppress the decrease in the on-current of the transistor. Therefore, the oxide semiconductor layer 313 is preferably formed by adding impurities. There are an undoped high resistance region 313a and an impurity-doped low resistance region 313b. do.

[0350] In the above transistor structure, the oxide semiconductor layer 313, which is likely to become the parasitic channel, Since the end of the oxide semiconductor layer 31 does not overlap with the third electrode 316 which is a gate electrode, The parasitic channel effect of the end of the MOSFET 3 can be suppressed, and the electrical characteristics and and reliability can be improved.

[0351] Note that the transistor of one embodiment of the present invention has the structure illustrated in FIGS. As shown in FIGS. 18A, 18B, and 18C, the second electrode 314 may be an oxide semiconductor. 18A shows a configuration in which the layer 313 is covered with a part of an end portion of the layer 313. 18(B) is a top view of a transistor 320 in FIG. 18(A). FIG. 18(C) is a cross-sectional view taken along line F3-F4 in FIG. 18(A). 18A, 18B, and 18C show only one portion of the rectangular oxide semiconductor layer 313. The second electrode 314 covering the side and the opposing side is illustrated, but the present invention is not limited to this. Any part of the end portion of the semiconductor layer 313 may be covered with the second electrode 314 .

[0352] As shown in FIGS. 19A, 19B, and 19C, a part of an end portion of the oxide semiconductor layer 313 The third electrode 316 may cover the first electrode 316. 19(B) is a top view of the transistor 330, and FIG. 19(B) is a top view of the transistor 330 along the line G1-G 19(C) is a cross-sectional view taken along line G3-G4 in FIG. 19(A). 19A, 19B, and 19C, one side of the rectangular oxide semiconductor layer 313 is The third electrode 316 covering the opposite side of the first electrode 312 is shown as an example, but the present invention is not limited to this. Any part of the end portion of the body layer 313 may be covered with the third electrode 316.

[0353] As shown in FIGS. 20A, 20B, and 20C, the third electrode 316 is connected to the first electrode 31 2 and a part of the second electrode 314. The third oxide semiconductor layer 313 is disposed between the first electrode 312 and the second electrode 314. Since the entire region overlapping with the electrode 316 becomes a channel formation region, the oxide semiconductor layer FIG. 20(A) shows a step of adding an impurity to the semiconductor device 313 according to one embodiment of the present invention. 20B is a top view of the transistor 340, and FIG. 20B is a top view of the transistor 340 along the line H1-H 20(C) is a cross-sectional view taken along line H3-H4 in FIG. 20(A). It is.

[0354] In a manufacturing process of a transistor according to one embodiment of the present invention, The capacitor element 350 can be fabricated on the same surface at the same time. The capacitor 350 can be used as a charge storage element. FIG. 21B is a cross-sectional view taken along line J1-J2 shown in FIG.

[0355] In addition, in Figs. 17(A), (B), (C) to 20(A), (B), (C), The oxide semiconductor layer 313, the first electrode 312, and the second electrode 313 each having a substantially rectangular outer periphery are The electrode 314 and the third electrode 316 are shown as examples, but are not limited thereto. As shown in FIG. 1, the upper surface shape may be a circle or a polygon. The electrode 316 and the wiring electrically connected thereto can be connected at any position. The location is not limited.

[0356] Next, a transistor 310 according to one embodiment of the present invention shown in FIGS. An example of the method will be described with reference to Figs. 23 and 24. The figure on the left is a top view, and the figure on the right is a cross-sectional view.

[0357] As described above, one end of the first electrode 312 (not shown) is connected to a power line, a signal line, etc. The first transistor can be electrically connected to any wiring or other transistors. The electrode 312 is electrically connected to wiring such as a power supply line or a signal line or to other transistors. A contact plug or a conductive layer electrically connected to the contact plug is used. It is possible.

[0358] First, a power supply line, a signal line, or an interlayer insulating film is formed on a substrate, and the interlayer insulating film is formed on the power supply line, a signal line, or another transistor. Thus, a first insulating layer 311 is formed.

[0359] The first insulating layer 311 is formed by depositing silicon oxide, oxide film, or the like by plasma CVD or sputtering. Silicon oxide nitride, aluminum oxide, aluminum oxide nitride, hafnium oxide, gallium oxide Silicon nitride, silicon oxynitride, aluminum nitride, oxide nitride, etc. The insulating film can be formed of a nitride insulating film such as aluminum nitride, or a mixture of these materials. Alternatively, a stack of the above materials may be used. The upper layer is formed of a material containing oxygen that can be a source of oxygen to the oxide semiconductor layer 313. is preferred.

[0360] Next, contact holes leading to wiring such as power lines and signal lines, or electrodes of other transistors, The contact holes may be formed by using a photolithography process. stomach.

[0361] Next, a conductive film is formed by sputtering or the like so as to fill the contact holes. Conductive films include aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten. An element selected from the group consisting of tin, etc., or an alloy containing the above-mentioned elements, or The conductive film may be a single layer or a laminate of two or more layers. For example, the upper side or the lower side of a metal film such as aluminum or copper may be used. Both the substrate and the substrate are coated with a high melting point metal film such as chromium, tantalum, titanium, molybdenum, or tungsten. A conductive nitride film made of manganese, magnesium, Zirconium, beryllium, neodymium, scandium, or a combination of these A combination of materials may also be used.

[0362] Then, the unnecessary conductive film on the surface is removed by planarizing the surface using CMP or the like. A contact plug is formed to fill the contact hole. The contact plug is as shown in FIG. It can be used as the first electrode 312 which becomes the source electrode of the transistor shown in FIG. Cut.

[0363] In addition, a conductive film is formed on the contact plug, and the conductive film is processed into an island shape. An insulating film is formed to cover the film, and then planarization is performed again using the CMP method, etc. to form a contact plate. A method for obtaining a first electrode 312 having a different shape from the lug may be performed. The same material as the conductive film can be used.

[0364] In addition to the planarization process by CMP, etc., dry etching and plasma processing are also performed. The plasma treatment may be performed by, for example, introducing argon gas to generate plasma. Reverse sputtering is a process in which RF is applied to the substrate side in an argon atmosphere. This is a method of modifying the surface by applying voltage using a power supply to generate plasma near the substrate. Instead of argon, nitrogen, helium, oxygen, etc. may be used. Powdery substances (also called particles or dust) attached to the film formation surface of the oxide semiconductor layer are removed. can be removed.

[0365] Next, an oxide semiconductor film is formed over the first insulating layer 311 and the first electrode 312. The oxide semiconductor layer 313 is formed into an island shape by using lithography and etching. (See FIG. 23(B)).

[0366] Note that the oxide semiconductor for forming the oxide semiconductor layer 313 is the same as that disclosed in the above embodiment. The insulating film can be formed using the same materials and methods as those used for the oxide semiconductor.

[0367] After the oxide semiconductor film is formed, excess hydrogen (including water and a hydroxyl group) contained in the oxide semiconductor film is removed. It is preferable to carry out a heat treatment to reduce or remove (dehydrate or dehydrogenate) the hydrogen atoms. The heat treatment temperature is between 300 and 700°C, or a glass substrate is used. In this case, the temperature should be below the distortion point of the substrate. Heat treatment can be performed under reduced pressure or in a nitrogen atmosphere. preferable.

[0368] This heat treatment reduces hydrogen, which is an impurity that imparts n-type conductivity, from the oxide semiconductor film. In addition, an insulating layer containing oxygen can be used as the first insulating layer 311. When the first insulating layer 311 is used, oxygen contained in the first insulating layer 311 is transferred to the oxide semiconductor film by the heat treatment. The oxide semiconductor film can be supplied with an acid that is released simultaneously with the dehydration or dehydrogenation treatment. By supplying oxygen from the first insulating layer 311, oxygen vacancies in the oxide semiconductor film are filled. It is possible.

[0369] Note that the heat treatment for dehydration or dehydrogenation is performed after the island-shaped oxide semiconductor layer 313 is formed or after the island-shaped oxide semiconductor layer 313 is formed. This heat treatment may be used together with other heat treatments in the manufacturing process of a transistor.

[0370] In the above heat treatment, nitrogen or a rare gas such as helium, neon, or argon is mixed with water, It is preferable that the nitrogen or helium introduced into the heat treatment device is not included. The purity of rare gases such as fluorine, neon, and argon should be 6N (99.9999%) or higher, preferably 7N. N (99.99999%) or more (i.e., impurity concentration is 1 ppm or less, preferably 0.1 ppm m or less).

[0371] In addition, after the oxide semiconductor film is heated by the heat treatment, the heating temperature is maintained or is increased from the heating temperature. While slowly cooling, high purity oxygen gas, high purity dinitrogen monoxide gas, or ultra-dry air are added to the same furnace. (When measured using a CRDS (Cavity Ring Down Laser Spectroscopy) type dew point meter In the case of the above, the moisture content is 20 ppm or less (-55°C in terms of dew point), preferably 1 ppm or less, more preferably Preferably, air at a concentration of 10 ppb or less may be introduced. It is preferable that the gas does not contain water, hydrogen, etc. The purity of the oxygen gas or nitrous oxide gas should be 6N or more, preferably 7N or more (i.e., oxygen gas or nitrous oxide). The impurity concentration in the nitrous oxide gas should be kept below 1 ppm, preferably below 0.1 ppm. It is preferable that the dehydration or dehydrogenation process is carried out by the action of oxygen gas or nitrous oxide gas. The main components of the oxide semiconductor film that were simultaneously reduced by the process of removing impurities by the By supplying oxygen, which is a component material, the oxide semiconductor film is highly purified and i-type (true It is possible to make it more sexual.

[0372] In addition, ion implantation, ion doping, plasma immersion ion implantation, A method for supplying oxygen to the oxide semiconductor film by a deposition method, a plasma treatment method, or the like is used. In this case, oxygen may be supplied directly to the oxide semiconductor film, or a second insulating film formed later may be used. Oxygen may be supplied through edge layer 315 .

[0373] The introduction of oxygen into the oxide semiconductor film can be performed after the dehydration or dehydrogenation treatment. In addition, the amount of oxygen added to the oxide semiconductor film that has been subjected to the dehydration or dehydrogenation treatment is not limited to the above. The introduction of oxygen may be carried out several times. In addition, the dehydration or dehydrogenation treatment and the introduction of oxygen may be carried out alternately. This may be repeated multiple times.

[0374] Next, a second electrode 314 (a wiring formed from the same layer as this) is formed on an end of the oxide semiconductor layer 313. The conductive film is formed to become a conductive layer (including a wire, etc.). The conductive film is formed using the same material as the first electrode 312. Then, the transistor can be formed by photolithography and etching. A second electrode 314 which serves as a drain electrode of the transistor is formed (see FIG. 23(C)).

[0375] Note that the oxide semiconductor layer 313 exposed by the formation of the second electrode 314 (drain electrode) The surface contains elements constituting the second electrode 314, elements present in the film formation chamber, and elements that are removed by etching. Elements constituting the etching gas used may adhere as impurities.

[0376] Therefore, after the etching for forming the second electrode 314 is completed, the oxide semiconductor layer 3 A cleaning process (impurity removal process) can be performed to remove impurities adhering to the surface of 13. preferable.

[0377] Next, a second insulating layer 315 is formed so as to cover the oxide semiconductor layer 313 and the second electrode 314. is formed by a plasma CVD method, a sputtering method or the like.

[0378] The second insulating layer 315 is a gate insulating layer, and is made of a material such as a silicon oxide film or a gallium oxide film. aluminum film, aluminum oxide film, silicon nitride film, silicon oxynitride film, aluminum oxynitride film The insulating film can be formed using a silicon nitride oxide film or a silicon nitride oxide film.

[0379] The second insulating layer 315 may be made of hafnium oxide, yttrium oxide, or hafnium. Silicate (HfSi x O y (x>0, y>0)), nitrogen-doped hafnium silicate Hafnium aluminate (HfAl x O y (x>0, y>0)), lanthanum oxide By using high-k materials, the gate leakage current can be reduced. The border layer 315 may be a single layer structure or a laminate structure.

[0380] Note that the second insulating layer 315 is an insulating layer in contact with the oxide semiconductor layer 313 and therefore does not absorb oxygen. It is preferable that the insulating layer contains as little impurities as possible, such as water and hydrogen. However, in the plasma CVD method, the hydrogen concentration in the film is higher than that in the sputtering method. Therefore, it is difficult to reduce the amount of the second insulating layer 315 by the plasma CVD method. When forming a film, a heat treatment (dehydration or It is preferable to carry out a dehydrogenation treatment.

[0381] The temperature of the heat treatment is 250° C. or more and 650° C. or less, preferably 450° C. or more and 600° C. or less. If a glass substrate is used, the temperature must be below the distortion point of the glass substrate. The substrate is introduced into an electric furnace, which is one of the devices, and the second insulating layer 315 is placed in a vacuum (reduced pressure) atmosphere. Heat treatment is carried out at 650°C under atmospheric pressure for 1 hour.

[0382] The heat treatment can dehydrate or dehydrogenate the second insulating layer 315, The second insulating layer 3 is free of impurities such as hydrogen or water that cause the transistor characteristics to fluctuate. 15 can be formed.

[0383] In the heat treatment for dehydration or dehydrogenation, the surface of the second insulating layer 315 is dehydrated or dehydrogenated. The condition is such that the release of water, etc. is hindered (for example, a membrane that does not allow hydrogen or water to pass through is provided). It is preferable that the surface of second insulating layer 315 is exposed, without being covered with a metal layer (eg, covered with a metal layer).

[0384] The heat treatment for dehydration or dehydrogenation may be carried out multiple times, or may be carried out in combination with other heat treatments. This is also fine.

[0385] In addition, the dehydrated or dehydrogenated second insulating layer 315 is subjected to an oxygen doping process. In this treatment, oxygen may be supplied to the oxide semiconductor layer 313 at the same time.

[0386] Next, a conductive film is formed on the second insulating layer 315 by a sputtering method or the like, and then a photolithography method and Then, a third electrode 316 having a ring-shaped upper surface is formed by etching (see FIG. 24(A)). The third electrode 316 is the gate electrode of the transistor and is connected to the first electrode 316 as shown. By forming the first electrode 312 and the second electrode 314 at a position where they do not overlap, the parasitic capacitance is reduced. However, a part of the wiring connected to the third electrode 316 is connected to the second electrode Overlaps with 314.

[0387] The third electrode 316 is formed using the same material and method as the gate electrode shown in the above embodiment. It is possible.

[0388] For example, as shown in FIG. 25, a copper layer 352 is formed in the middle layer, and a copper diffusion prevention layer is formed in either the upper or lower layer. The conductive layer has a three-layer structure with tungsten nitride 351 on one side and tantalum nitride 353 on the other side. The third electrode 316 can be used as the first electrode 312 and the second electrode 313. The three-layered conductive layer can also be applied to the electrode 314. In the electrode structure shown in FIG. Although the photolithography process is increased to seal in the copper, the diffusion of copper is suppressed. The effect is very high, and the reliability of the transistor can be improved.

[0389] After the third electrode 316 is formed, a heat treatment may be performed. For example, a GRTA apparatus may be used to heat the third electrode 316 at 65 Heat treatment can be performed at 500°C for 30 to 15 minutes in an electric furnace. Heat treatment may be carried out for a period of time.

[0390] Next, the oxide semiconductor layer 313 is overlapped with the second electrode 314 and the third electrode 316. In order to reduce the resistance of the region that is not to be exposed, impurities are added to the region to form a low resistance region 313b. (See FIG. 24(B)).

[0391] The impurities that improve the electrical conductivity of the oxide semiconductor layer 313 include, for example, phosphorus (P) and arsenic. (As), antimony (Sb), boron (B), aluminum (Al), nitrogen (N ), Argon (Ar), Helium (He), Neon (Ne), Indium (In), Fluorine (Fluor) is selected from the group consisting of fluorine (F), chlorine (Cl), titanium (Ti), and zinc (Zn). One or more of the above may be used.

[0392] The impurities pass through the second insulating film by using the third electrode 316 as a mask, and are absorbed into the oxide semiconductor. The impurity can be locally added to the conductor layer 313. The method for adding the impurity is ion implantation. implantation method, ion doping method, plasma immersion ion implantation method, etc. In this case, the impurity may be dissolved in water to obtain a solution containing the impurity as a simple substance, a fluoride, or a chloride ion. It is preferable to use

[0393] The impurity doping process is carried out under various conditions, such as the acceleration voltage, the dose amount, and the thickness of the film through which the impurities are to be passed. For example, the impurity added to the oxide semiconductor layer 313 may be When phosphorus is used, the impurity concentration in the region where the impurity is added is 5×10 18 / cm 3 End 1×10 22 / cm 3 It is preferable that:

[0394] Note that the impurity may be added while the substrate is heated. The impurity doping treatment may be carried out multiple times, and multiple types of impurities may be used.

[0395] In addition, a heat treatment may be performed after the impurity addition treatment. For example, The heating may be performed at a temperature of 00° C. to 700° C., preferably 300° C. to 450° C., for one hour. The heat treatment may also be carried out in a nitrogen atmosphere, under reduced pressure, or in the air (ultra-dry air).

[0396] Next, a third insulating layer 317 is formed as a protective film on the second insulating layer 315 and the third electrode 316. As the third insulating layer 317, for example, a silicon oxide film, an oxide film, or the like is preferably formed. gallium oxide film, aluminum oxide film, silicon nitride film, silicon oxynitride film, aluminum oxynitride film An insulating film such as an aluminum film or a silicon nitride oxide film can be used.

[0397] Note that the third insulating layer 317 is more preferably an aluminum oxide film. The aluminum oxide membrane is permeable to both impurities such as hydrogen and moisture, and oxygen. Therefore, the aluminum oxide film has a high blocking effect. During and after the formation of the oxide semiconductor layer, impurities such as hydrogen and moisture, which are factors of fluctuation, The oxide semiconductor layer is mainly composed of oxygen, and oxygen is released from the oxide semiconductor layer. The aluminum oxide film functions as a protective film to prevent the aluminum oxide film from leaking out. A film is formed directly by sputtering, or an aluminum (Al) film is formed by sputtering, etc. Later, oxygen plasma treatment, oxygen ion implantation, oxygen ion doping, etc. will be performed. Thus, it can be formed.

[0398] The third insulating layer 317 may be a silicon oxide film, a gallium oxide film, a silicon nitride film, or an oxide One or more of a silicon nitride film, an aluminum oxynitride film, and a silicon nitride oxide film The insulating film and the aluminum oxide film may be laminated together.

[0399] Alternatively, oxygen addition treatment may be performed on the third insulating layer 317. For example, an ion implantation method may be used. , ion doping method, plasma immersion ion implantation method, plasma Oxygen can be provided to the third insulating layer 317, such as by a treatment method.

[0400] After the third insulating layer 317 is formed, a heat treatment at 100° C. to 400° C. may be performed. This heat treatment may be performed by holding the temperature constant or by heating from room temperature to 100°C or higher. The temperature was increased to 400°C or less and then decreased to room temperature several times. The heat treatment may be carried out under reduced pressure. When the heat treatment is carried out under reduced pressure, The heating time can be shortened. This heat treatment converts the oxygen contained in each insulating layer into oxide. Since the semiconductor layer 313 can be supplied with the semiconductor material, the reliability of the transistor can be improved.

[0401] Next, if necessary, a planarization film 318 is formed on the third insulating layer 317. Examples of the insulating film that can be used as the third insulating layer 317 include polyimide resin, Acrylic resin, polyimide amide resin, benzocyclobutene resin, polyamide resin Heat-resistant organic materials such as grease and epoxy resins can be used. In addition to the materials, low-k materials, siloxane resins, and PSG (phosphorus glass) are also available. ), BPSG (borophosphorus glass), etc. can be used. Alternatively, a planarizing insulating layer may be formed by stacking a plurality of insulating films.

[0402] For example, the flattening film 318 may be an acrylic resin film having a thickness of 1500 nm. The acrylic resin film is applied by coating and then baked (for example, in a nitrogen atmosphere at 250°C for 1 hour). ) can be formed.

[0403] In addition, the structures shown in FIGS. 18(A), (B), (C) to 20(A), (B), (C) The transistor is formed by the above-mentioned method for manufacturing the transistor 310, except that the second electrode 314 and It can be formed by appropriately changing the shape of the third electrode 316. In the transistors having the structures shown in (a), (b), and (c), a low resistance region 313b is formed. This makes it possible to omit the step of adding impurities to achieve this.

[0404] The capacitor illustrated in FIG. 21 is manufactured by the photolithography method for the above-described transistor 310. In the lithography process, a mask having a different shape from the components of the transistor 310 is used. This allows the transistor 310 to be formed at the same time without increasing the number of steps. .

[0405] Through the above steps, a transistor in which generation of a parasitic channel is suppressed, which is one embodiment of the present invention, can be formed. It is possible.

[0406] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0407] (Embodiment 6) In this embodiment, a transistor having a different structure from the transistors disclosed in the above embodiment will be described. The structure and manufacturing method of a capacitor that can be manufactured simultaneously with a transistor are described. do.

[0408] FIG. 26 illustrates a structural example of a transistor 410 according to one embodiment of the present invention. FIG. 26A is a top view of the transistor, and FIG. 26B is a top view of the transistor. 26(C) is a cross-sectional view taken along the line K1-K2 shown in FIG. 26(A), and FIG. 26(C) is a cross-sectional view taken along the line K3- This is a cross-sectional view taken along line K4.

[0409] The transistor 410 illustrated in FIG. 26 includes an oxide semiconductor layer 401 and a The insulating layer 402 overlaps with the oxide semiconductor layer 401 with the insulating layer 402 interposed therebetween and is A conductive layer 403 having a ring-shaped portion overlapping the semiconductor layer 401, and an inner side of the ring-shaped portion the conductive layer 404 in contact with the oxide semiconductor layer 401 in the region outside the ring-shaped portion; 26, a conductive layer 405 is provided in contact with the oxide semiconductor layer 401. In the transistor 410, the conductive layer 403 functions as a gate, and the conductive layer 404 functions as a transistor. The conductive layer 405 serves as the other of the source and drain. In addition, in the transistor 410 shown in FIG. The oxide semiconductor layer 403 and the conductive layer 404 are provided on the top surface of the oxide semiconductor layer 401, and the conductive layer 405 is an oxide semiconductor layer. The insulating layer 404 is provided on the lower surface side of the compound semiconductor layer 401 .

[0410] Note that the conductive layer 405 illustrated in FIG. 26 has a ring-shaped portion in contact with the oxide semiconductor layer 401. The conductive layer 405 is arranged so that the upper surface thereof is substantially flush with the upper surface of the insulating layer 406. The upper surface of the insulating film 402 is in contact with the oxide semiconductor layer 401. The transistor 410 shown in FIG. 4 includes an insulating layer 407 and a conductive layer extending over the insulating layer 407. The conductive layer 408 is provided between the insulating layer 402 and the insulating layer 407. The conductive layer 404 is in contact with the conductive layer 404 at an opening 411 provided in the conductive layer 404 .

[0411] In the transistor 410 shown in FIG. 26, the conductive layer 404 (one of the source and drain When the end of the oxide semiconductor layer 401 is electrically connected to the insulating layer 402, at least a conductive layer is provided between the insulating layer 401 and the oxide semiconductor layer 401. The oxide semiconductor layer 401 overlaps with the gate 403. The region overlapping with the conductive layer 403 (gate) of the transistor 410 Depending on the voltage between the conductive layer 404 or conductive layer 405 (source), the channel (intrinsic In the transistor 410, the oxide semiconductor Regardless of whether the end of the conductor layer 401 has a low resistance or not, whether an inherent channel is formed or not. The conductive layer 404 and the conductive layer 405 (source and drain) are electrically connected based on As a result, in transistor 410, a switch This makes it possible to easily control the switching.

[0412] Note that the oxide semiconductor for forming the oxide semiconductor layer 401 may be any of the oxide semiconductors disclosed in the above embodiment. The insulating film can be formed using the same materials and methods as those used for the oxide semiconductor.

[0413] The insulating layer 402 may be made of silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide. Inorganic insulating materials such as gallium oxide, aluminum oxide nitride, or aluminum oxide are used. It is also possible to apply a laminate of these materials. Aluminum acts as a barrier to both impurities such as hydrogen and oxygen. Therefore, a layer containing aluminum oxide is used as the insulating layer 402. In this manner, oxygen is prevented from being released from the oxide semiconductor layer 401. This can prevent impurities such as hydrogen from being mixed into the layer 401 .

[0414] The insulating layer 402 may be made of hafnium oxide, yttrium oxide, or hafnium silicate. (HfSi x O y (x>0, y>0)), nitrogen doped hafnium silicate, haf HfAl x O y (x>0, y>0)), or lanthanum oxide ( A film containing a so-called high-k material can also be used. This makes it possible to reduce the gate leakage current.

[0415] The conductive layer 403 may be made of aluminum, copper, titanium, tantalum, tungsten, or molybdenum. , chromium, neodymium, scandium or alloys containing these elements In addition, a film made of a metal oxide containing nitrogen can be used as the conductive layer 403. Specifically, nitrogen-containing In-Ga-Zn oxides, nitrogen-containing In-Sn oxides, In-Ga oxide containing nitrogen, In-Zn oxide containing nitrogen, Sn oxide containing nitrogen It is also possible to use In-based oxides containing nitrogen or metal nitrides (InN, SnN, etc.). These nitride films have an energy of 5 eV (electron volts) or more, preferably 5.5 eV (electron volts). When used as a gate, it can increase the threshold voltage of a transistor by 100%. This makes it possible to realize a so-called normally-off switching element. A laminate of these films may also be applied.

[0416] The conductive layers 404 and 405 may be formed of aluminum, copper, titanium, tantalum, or tungsten. Elements selected from tenon, molybdenum, chromium, neodymium, and scandium, A film made of an alloy containing these elements or a nitride containing these elements can be applied. Moreover, a laminate of these films may also be applied.

[0417] The insulating layer 406 may be made of silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide. Inorganic insulating materials such as gallium oxide, aluminum oxide nitride, or aluminum oxide are used. It is also possible to apply a laminate of these materials. Aluminum acts as a barrier to both impurities such as hydrogen and oxygen. Therefore, a material containing aluminum oxide is preferably used as the insulating layer 402. By using the above-mentioned insulating layer, it is possible to prevent oxygen from being released from the oxide semiconductor layer 401 and to prevent the oxide semiconductor layer This can prevent impurities such as hydrogen from entering the layer 401 .

[0418] The insulating layer 407 may be made of silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide. Inorganic insulating materials such as gallium oxide, aluminum oxide nitride, or aluminum oxide are used. In addition, organic insulating materials such as polyimide and acrylic can also be used. Also, a laminate of these materials can be applied.

[0419] The conductive layer 408 may be made of aluminum, copper, titanium, tantalum, tungsten, or molybdenum. , an element selected from chromium, neodymium, and scandium, or an alloy containing these elements; Alternatively, a material made of a nitride containing these elements can be applied. A layer may also be applied.

[0420] 27 and 28 are diagrams illustrating an example of a manufacturing process of the transistor 410 illustrated in FIG. Specifically, FIGS. 27(A1) to (C1) and 28(A1) to (C1) show transistor 410. 27(A2) to (C2) and FIG. 28(A2) to (C2) are top views showing the manufacturing process of the is a line K1-K2 shown in Figs. 28(A1) to (C1) and 28(A1) to (C1). Cross-sectional view.

[0421] First, the insulating layer 406 is formed. The method for forming the insulating layer 406 may be a plasma CVD method, a sintered silicon carbide method, or the like. In addition, after the insulating film is formed, the water or hydrogen content is reduced. For example, a heat treatment may be performed under reduced pressure or in an inert atmosphere. Heat treatment at 300°C to 700°C for 1 hour or less is sufficient. In this way, it is possible to prevent hydrogen from being mixed into the oxide semiconductor layer 401. When the substrate includes an aluminum oxide film, the aluminum oxide film may be directly formed or can be formed by forming an aluminum film and then oxidizing it. The oxidation treatment may be an oxygen plasma treatment or an oxygen doping treatment.

[0422] Next, an opening 412 is formed in the insulating layer 406. For example, by using a photolithography method, A mask is formed on the insulating layer 406, and the insulating layer 406 is partially etched to form an opening 4. Form 12.

[0423] Next, a conductive film is formed. The method for forming the conductive film includes a sputtering method. Can be obtained.

[0424] Next, the conductive film provided on the insulating layer 406 is cut (grinded, polished) to form The cutting method may be the CMP method. An edge layer 406 and a conductive layer 405, the upper surface of which forms a substantially flush surface with the insulating layer 406, are formed. .

[0425] Next, an oxide semiconductor film is formed by a sputtering method. Further, the oxide semiconductor film is formed under the following conditions: the oxide semiconductor film contains a large amount of oxygen. For example, sputtering in an atmosphere of 95% to 100% oxygen In this way, the oxide semiconductor film is preferably formed by The amount of element is increased (preferably, the amount of element is increased relative to the stoichiometric composition in the oxide semiconductor in a crystalline state). It may contain areas with excess oxygen.

[0426] As described in the above embodiment, after the oxide semiconductor film is formed or after the oxide semiconductor layer is formed, After the formation of the insulating layer 401, a heat treatment may be performed. By this heat treatment, oxygen contained in the insulating layer 406 is converted into Therefore, the oxide semiconductor film or the oxide layer 401 can be heated by the heat treatment. Even if oxygen deficiency occurs in the oxide semiconductor layer 401, the oxide semiconductor layer 401 can be easily oxidized by the supply of oxygen from the insulating layer 406. This makes it possible to compensate for the oxygen deficiency.

[0427] Next, the oxide semiconductor film is partially removed. For example, A mask is formed over the oxide semiconductor film, and the oxide semiconductor film is partially etched. As a result, the oxide semiconductor layer 401 is formed.

[0428] Next, a conductive film is formed. The method for forming the conductive film includes a sputtering method. After the conductive film is formed or after the conductive layer 404 is formed, a heat treatment may be performed. For example, a GRTA device that uses high-temperature gas for heat treatment can be used to heat the material at 650°C for 1 to 5 minutes. The high-temperature gas in the GRTA may be a rare gas such as argon or Inert gas such as nitrogen is used. In addition, it is heated at 500℃ for 30 minutes to 1 hour in an electric furnace. Processing may be carried out.

[0429] Next, the conductive film is partially removed. For example, the conductive film is partially removed by using a photolithography method. A mask is formed on the conductive film, and the conductive film is partially etched and removed. As a result, a conductive layer 404 is formed.

[0430] Next, the insulating layer 402 is formed. The method for forming the insulating layer 402 may be a plasma CVD method, a sputtering method, or the like. Examples include the tarring method.

[0431] Furthermore, when the insulating layer 402 contains aluminum oxide, the aluminum oxide is directly The aluminum film can be formed by depositing the aluminum on the aluminum substrate or by performing oxidation treatment after depositing the aluminum film. The oxidation treatment may be an oxygen plasma treatment or an oxygen doping treatment. Some examples include:

[0432] Next, a conductive film is formed. The method for forming the conductive film includes a sputtering method. After the conductive film is formed or after the conductive layer 403 is formed, heat treatment may be performed. For example, a GRTA device that uses high-temperature gas for heat treatment can be used to heat the material at 650°C for 1 to 5 minutes. In addition, the high-temperature gas in the GRTA is a rare earth gas such as argon. Use an inert gas such as gas or nitrogen. Also, use an electric furnace at 500℃ for 30 minutes to 1 hour. Heat treatment may be carried out during this time.

[0433] Next, the conductive film is partially removed. For example, the conductive film is partially removed by using a photolithography method. A mask is formed on the conductive film, and the conductive film is partially etched and removed. As a result, a conductive layer 403 is formed.

[0434] Next, the insulating layer 407 is formed. The method for forming the insulating layer 407 may be a plasma CVD method, a sputtering method, or the like. Examples of the method include a deposition method and a coating method.

[0435] Next, an opening 411 is formed in the insulating layer 407 and the insulating layer 402. For example, A mask is formed on the insulating layer 407 by a lithography method, and the insulating layer 407 and the insulating layer 402 are partially An opening 411 is formed by partial etching.

[0436] Next, a conductive film is formed. The method for forming the conductive film includes a sputtering method. Can be obtained.

[0437] Next, the conductive film is partially removed. For example, the conductive film is partially removed by using a photolithography method. A mask is formed on the conductive film, and the conductive film is partially etched and removed. As a result, a conductive layer 408 is formed.

[0438] The structure of a transistor according to one embodiment of the present invention is not limited to the above. The modified structure of the transistor of the embodiment is shown as a transistor 420 and a transistor 430. A transistor 420 and a transistor 430 having the structure shown in FIG. This is one aspect of clarity.

[0439] FIG. 29A is a top view of a transistor 420, and FIG. 29B is a top view of the transistor 420 shown in FIG. FIG. 29(C) is a top view of the transistor 430. FIG. 29(D) is a cross-sectional view taken along line N1-N2 shown in FIG. 29(C).

[0440] The transistor 420 shown in FIGS. 29A and 29B is the same as the transistor 410 shown in FIG. The conductive layer 405 (the other of the source and drain) is connected to the conductive portions 405A and 405B and the connection portion 4 The conductive portion 405A and the conductive portion 405B are made of an oxide semiconductor. The connection portion 405C is a conductive layer that contacts the conductor layer 401, and the connection portion 405B is a conductive layer that contacts the insulating layer 402 and the insulating layer 407. The conductive layer 405A and the conductive layer 405B are in contact with each other through an opening 413 provided in the conductive layer 405A. In the transistor 420 shown in FIGS. 29A and 29B, The other of the source and drain and the gate (conductive layer 403) or source It is possible to reduce the parasitic capacitance between the drain and the conductive layer 404. On the other hand, in the transistor 410 shown in FIG. 26, Compared with the transistor 420, the current driving capability can be increased (the on-current can be increased). Specifically, the transistor 410 shown in FIG. In comparison with the transistor 420 shown in FIG. Therefore, in the transistor 410 shown in FIG. Compared with the transistor 420 shown in FIG. 1B, the current drive when the conductive layer 405 serves as the source It is possible to increase the capacity.

[0441] Note that a transistor obtained by modifying a part of the structure of the transistor 420 shown in FIGS. A transistor is also an embodiment of the present invention. Each of the first and second insulating layers 401 is in contact with the oxide semiconductor layer 401 and is electrically connected to the oxide semiconductor layer 401. A transistor having a conductive portion is also a transistor of one embodiment of the present invention.

[0442] The transistor 430 shown in FIGS. 29C and 29D is the same as the transistor 410 shown in FIG. In comparison, the difference is that a part of the conductive layer 403 and a part of the conductive layer 405 overlap each other. 26.) and (D) of the transistor 430 shown in FIG. Specifically, the transistor shown in FIG. In the gate 410, the oxide semiconductor layer 401 in a region not overlapping with the conductive layer 403 (gate) is highly In contrast, the transistors shown in Figs. 29(C) and (D) In the transistor 430, the conductive layer 403 (gate) and There are few non-overlapping areas. Therefore, in Figs. 29(A) and (B), In comparison with the transistor shown in the transistor 410, the current driving capability can be increased. On the other hand, in the transistor 410 shown in FIG. 26, The parasitic capacitance between the conductive layer 403 and the conductive layer 405 is reduced compared to the transistor 430. It is possible to do so.

[0443] The manufacturing process of the transistor of one embodiment of the present invention is not limited to the above-described process. For example, A manufacturing process of a transistor described below is also one embodiment of the present invention.

[0444] After the steps shown in Figs. 27(C1) and (C2), the steps shown in Figs. 28(A1) and (A2) In order to remove impurities attached to the surface of the oxide semiconductor layer 401, By the cleaning treatment, the oxide semiconductor layer 40 may be cleaned. It is possible to suppress the region near the surface of 1 from becoming low in resistance due to the presence of the impurity. Cut.

[0445] FIG. 30 illustrates an example of a process for fabricating a modified transistor of one embodiment of the present invention. In the process for manufacturing a transistor described with reference to FIGS. 27 and 28, the oxide semiconductor layer 4 30(A) and (B) show a manufacturing process in which a process for forming a low-resistance region is added to the process in 01. This will be described with reference to the following.

[0446] After the steps shown in Figs. 28(A1) and (A2), the steps shown in Figs. 28(B1) and (B2) Before the above, an impurity may be implanted into the oxide semiconductor layer 401 to reduce the resistance of the oxide semiconductor layer 401. The conductive layer 403 and the conductive layer 404 serve as a mask. The impurities are helium, boron, , nitrogen, fluorine, neon, aluminum, phosphorus, argon, arsenic, krypton, indium The elements include one or more elements selected from the group consisting of aluminum, tin, antimony and xenon. The method includes ion implantation and ion doping. It is preferable to use the method.

[0447] The region to which the impurity is added has a low resistance. As a result, the oxide semiconductor layer 401 has a low resistance in the region 40 1A and a region 401B having a lower resistance than the region 401A are formed.

[0448] By adding the process shown in FIG. 30 to the transistor manufacturing process shown in FIG. Therefore, it is possible to increase the current driving capability of the transistor formed. When the steps shown in FIG. 1 are not performed, the number of steps for manufacturing a transistor can be reduced. .

[0449] As shown in FIG. 30B, The transistor having the above structure is also a transistor according to one embodiment of the present invention.

[0450] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0451] (Embodiment 7) In this embodiment, the transistor shown in this specification is used, and even in a situation where power is not supplied, An example of a semiconductor device that can retain memory contents and has no limit to the number of times it can be written is shown in FIG. This will be explained using:

[0452] FIG. 31 shows an example of the structure of a semiconductor device. FIG. 31(A) shows a cross-sectional view of the semiconductor device. FIG. 31B shows a top view of the semiconductor device, and FIG. 31C shows a circuit diagram of the semiconductor device. Here, FIG. 31(A) is a cross section taken along lines P1-P2 and P3-P4 in FIG. 31(B). Equivalent.

[0453] The semiconductor device shown in FIG. 31(A) and FIG. 31(B) has a transistor using a first semiconductor material in the lower part. The transistor 560 has a transistor 110 made of a second semiconductor material on top. The transistor 110 shown in FIG. 31 is the same as the transistor described in the first embodiment. In place of the transistor 110, a transistor having a different configuration from the transistor 110 is used. A transistor having the following structure may be used.

[0454] Here, the first semiconductor material and the second semiconductor material may be materials having different forbidden band widths. For example, the first semiconductor material may be a semiconductor material other than an oxide semiconductor (such as silicon). The second semiconductor material can be an oxide semiconductor. The transistors used in this study can easily operate at high speed. The characteristics of the charge storage capacitor enable it to retain electric charge for a long period of time.

[0455] It should be noted that the above transistors are all n-channel transistors. However, it goes without saying that a p-channel transistor can be used. Other than the use of transistors as exemplified in the fine print (materials used in memory devices and memory device The specific configuration of the component (e.g., structure) is not limited to the configuration disclosed in this specification.

[0456] The transistor 560 in FIG. 31A includes a semiconductor material (e.g., silicon, etc.). A channel forming region 516 is provided in a substrate 500 including a channel forming region 516 and a The impurity region 520 and the intermetallic compound region 524 in contact with the impurity region 520 are formed as shown in FIG. a gate insulating layer 508 provided on the channel forming region 516; and a gate electrode 510 provided on the gate electrode 510. In some cases, the transistor does not have a gate electrode or drain electrode. In this case, the source is sometimes used to explain the connection relationship of the transistor. The source and drain regions are sometimes referred to as the source electrode and drain electrode. In this specification, the term "source electrode" may include a source region.

[0457] An element isolation insulating layer 506 is provided on the substrate 500 so as to surround the transistor 560. An insulating layer 528 and an insulating layer 530 are provided to cover the transistor 560 . In the transistor 560, a sidewall insulating layer is formed on the side surface of the gate electrode 510. A metal insulating layer may be provided to form the impurity region 520 including regions with different impurity concentrations. The element isolation insulating layer 506 is formed by LOCOS (Local Oxidation of Silicon). silicon) and STI (Shallow Trench Isolation), etc. The element isolation technique can be used.

[0458] The transistor 560 using a single crystal semiconductor substrate can operate at high speed. By using this transistor as a read transistor, data can be read at high speed. The insulating layer 528 and the insulating layer 530 are formed to cover the transistor 560. As a process prior to the formation of the transistor 110 and the capacitor 564, the insulating layer 52 CMP is performed on the insulating layer 530 and the transistor 1. This improves the flatness of the surface on which the gate electrode 10 is formed, and at the same time exposes the upper surface of the gate electrode 510 .

[0459] The insulating layer 528 and the insulating layer 530 are typically a silicon oxide film, a silicon oxynitride film, an oxide film, or a silicon nitride film. aluminum oxide film, aluminum nitride film, silicon nitride film, aluminum nitride film, Inorganic insulating films such as silicon oxide film and aluminum oxide nitride film can be used. The edge layer 528 and the insulating layer 530 are formed by using a plasma CVD method, a sputtering method, or the like. It is possible.

[0460] In addition, organic materials such as polyimide, acrylic resin, and benzocyclobutene resin can be used. In addition to the above organic materials, low-dielectric constant materials (low-k materials) can also be used. When using organic materials, the insulating layer can be formed by wet methods such as spin coating and printing. 528 and insulating layer 530 may be formed.

[0461] In this embodiment, the insulating layer 528 is a silicon nitride film, and the insulating layer 530 is a silicon nitride film. A silicon oxide film is used.

[0462] Between the transistor 560 and the transistor 110, a first base insulating layer 101a and The first insulating base layer 101a is a layer for forming a second insulating base layer 101b of the transistor. 560 from entering the oxide semiconductor layer 102; The second insulating layer 102 functions as a blocking layer for suppressing the release of oxygen from the second insulating layer 102. The base insulating layer 101b contains excess oxygen for supplying oxygen to the oxide semiconductor layer 102. As a result, the oxide semiconductor layer 102 of the transistor 110 is By supplying oxygen from the insulating layer 101b, the oxide semiconductor layer 102 This can compensate for the oxygen deficiency.

[0463] In FIG. 31, the insulating layer 528, the insulating layer 530, the first base insulating layer 101a, and the second The insulating layer 528 is formed on the first insulating base layer 101b. In the case where the insulating layer 530 functions as a blocking layer like the insulating layer 1 in a, In the case where the oxide semiconductor layer 102 has a function of supplying oxygen thereto, similarly to the case of 01b, It is possible to provide a configuration in which the ground insulating layer 101a and the second base insulating layer 101b are not provided. .

[0464] The transistor 110 illustrated in FIG. 31A is an oxide semiconductor as described in Embodiment 1. The transistor 110 includes a semiconductor device having a channel forming region. The oxide semiconductor layer 102 to be used is preferably highly purified. By using an oxide semiconductor, the transistor 110 can have excellent off-state characteristics. can be done.

[0465] Since the off-state current of the transistor 110 is small, the use of the transistor 110 enables long-term recording. The contents of the memory can be retained, i.e., no refresh operation is required, or Therefore, it is possible to realize a semiconductor memory device in which the frequency of refresh operations is extremely low. Power consumption can be reduced sufficiently.

[0466] In this embodiment, the electrode 108, which is the other of the source electrode and the drain electrode, is the electrode 106. The transistor 560 is electrically connected to the gate electrode 510 through the In order to form an opening reaching the gate electrode 510 of the gate electrode 560, the first gate insulating layer 1 103a, the second gate insulating layer 103b, the first insulating layer 107, and the second insulating layer 109. When etching is performed to form an opening that reaches the electrode 108, the first gate insulating layer 103a , the second gate insulating layer 103b, the first insulating layer 107, and the second insulating layer 109. An opening is formed in a region above the gate electrode 510 of the transistor 560 .

[0467] Next, a third conductive layer which will become the electrode 106 is formed on the second insulating layer 109 so as to fill the opening. The third conductive film is partially removed by etching or the like to leave the electrode 108 and the The electrode 106 electrically connected to the gate electrode 510 of the transistor 560 may be formed. .

[0468] On the transistor 110, a first insulating layer 107, a second insulating layer 109, and an insulating layer 55 are provided. In this embodiment, the insulating layer 550 is formed of an oxidized aluminum. The aluminum oxide film is made of high density aluminum oxide (film density 3.2 g / cm 3 That's all good Preferably 3.6g / cm 3 By setting the transistor 110 to Characteristics can be given.

[0469] In addition, a conductive layer 553 is provided in a region overlapping with the electrode 106 with the insulating layer 550 interposed therebetween. The electrode 106, the insulating layer 550, and the conductive layer 553 constitute a capacitor element 564. The electrode 106 is the other of the source electrode or the drain electrode of the transistor 110. Since the source electrode or drain electrode of the transistor 110 is electrically connected to the electrode 108, The electrode 108, which is the other of the input electrodes, can be said to function as one electrode of the capacitor 564. The conductive layer 553 functions as the other electrode of the capacitor 564. If necessary, the capacitor 564 may be omitted. 4 may be provided separately above the transistor 110. Furthermore, as shown in FIG. , may be provided on the same plane as transistor 110.

[0470] An insulating layer 552 is provided over the transistor 110 and the capacitor 564. A wiring 556 is provided on the insulating layer 552. The wiring 556 is connected to the transistor 110. It is provided to connect other transistors. The wire 556 is connected to the insulating layer 550 through an electrode formed in an opening formed in the insulating layer 552. Electrode 104 or electrode 108, or electrode 10 electrically connected to electrode 108 6, where the electrode is electrically connected to at least the oxide semiconductor layer of the transistor 110. It is preferable that the conductive layer 102 is provided so as to overlap with a part of the conductive layer 102 .

[0471] In FIG. 31(A) and FIG. 31(B), a transistor 560 and a transistor 110 are provided so as to overlap at least partially, and the source region of the transistor 560 Alternatively, the drain region and the oxide semiconductor layer 102 may be provided so as to partly overlap each other. In addition, the transistor 110 and the capacitor 564 are preferably For example, the conductive layer 553 of the capacitor 564 is , at least partially overlapping with the gate electrode 510 of the transistor 560 . By adopting such a planar layout, it is possible to reduce the area occupied by the semiconductor device. This allows for high integration.

[0472] The electrode 106 and the wiring 556 are electrically connected to each other by directly contacting the electrode 106 and the wiring 556. Alternatively, an electrode may be provided on the insulating film between the electrode 106 and the wiring 556, and the electrode The electrode may be interposed between the electrodes.

[0473] Next, an example of a circuit configuration corresponding to FIGS. 31(A) and 31(B) is shown in FIG. 31(C).

[0474] In FIG. 31C, the first wiring (1st Line) and the source of the transistor 560 The electrode is electrically connected to the second wiring (2nd Line) and the transistor 560. The drain electrode is electrically connected. Also, the third wiring (3rd Line) The fourth transistor 110 is electrically connected to one of the source electrode and the drain electrode of the fourth transistor 110. The wiring (4th Line) and the gate electrode of the transistor 110 are electrically connected. The gate electrode of the transistor 560 and the source voltage of the transistor 110 are connected to each other. The other of the electrode or drain electrode is electrically connected to the other electrode of the capacitor 564. The wiring (5th Line) and the other electrode of the capacitor 564 are electrically connected to each other.

[0475] In the semiconductor device shown in FIG. 31C, the potential of the gate electrode of the transistor 560 can be held. By taking advantage of this feature, it is possible to write, retain, and read information as follows: .

[0476] The writing and holding of data will be described. First, the potential of the fourth wiring is set to The transistor 110 is turned on by applying a potential to the transistor 110. The potential of the third wiring is applied to the gate electrode of the transistor 560 and one side of the capacitor 564. That is, the node 555 is provided with a predetermined charge. is given (write). Here, the charges that give two different potential levels (Lo Then, either the w-level charge or the high-level charge is given. The potential of the fourth wiring is set to a potential at which the transistor 110 is turned off. By turning off 110, the charge applied to the gate electrode of transistor 560 is retained (retained).

[0477] Since the off-state current of the transistor 110 is extremely small, the gate electrode of the transistor 560 The charge is retained for a long period of time.

[0478] Next, the reading of information will be explained. A state in which a predetermined potential (constant potential) is applied to the first wiring When an appropriate potential (read potential) is applied to the fifth wiring, the potential held in the node 555 Depending on the load, the second wire takes on different potentials. In the case of a transistor 560, a high-level charge is applied to the gate electrode of the transistor 560. Apparent threshold V th_H The gate electrode of the transistor 560 is at a low level. Apparent threshold V for a given charge th_L This is because the The apparent threshold voltage is the voltage required to turn on transistor 560. This refers to the potential of the fifth wiring. Therefore, the potential of the fifth wiring is V th_H and V t h_L By setting the potential V0 between For example, if a high-level charge is applied during writing, In this case, the potential of the fifth wire is V0 (> V th_H ), transistor 560 is "ON" When a low-level charge is applied, the potential of the fifth wire is V0 ( <V th_L ), transistor 560 remains in the "off state." Therefore, by monitoring the potential of the second wiring, the stored data can be read out.

[0479] When memory cells are arranged in an array, only the information in a desired memory cell can be read. If the information is not read out, the state of the gate electrode is Regardless of the potential at which transistor 560 is in the “off state,” i.e., V th_H Yo Alternatively, the transistor may be turned on regardless of the state of the gate electrode. The potential at which the transistor 560 is in the "on" state, i.e., V th_L A larger potential Just give it to the fifth wire.

[0480] In the semiconductor device described in this embodiment, an off-state current is low when an oxide semiconductor is used for a channel formation region. By using extremely small transistors, memory contents can be retained for an extremely long period of time. In other words, the refresh operation is unnecessary or the refresh operation is possible. This allows the frequency of operation to be reduced significantly, resulting in a significant reduction in power consumption. In addition, when there is no power supply (however, it is preferable that the potential is fixed), However, it is possible to retain the stored contents for a long period of time.

[0481] In addition, the semiconductor device described in this embodiment does not require a high voltage for writing data. There is no problem with degradation of the capacitance. For example, unlike conventional non-volatile memory, the floating gate Since there is no need to inject electrons into the floating gate or extract electrons from the floating gate, The problem of deterioration of the gate insulating layer does not occur at all. The device does not have the limit on the number of times it can be rewritten, which is a problem with conventional non-volatile memory, and is reliable. Furthermore, the on and off states of transistors allow the Since writing is performed, high speed operation can be easily achieved.

[0482] As described above, according to the present embodiment, a transistor capable of suppressing the occurrence of a parasitic channel is provided. You can get the data.

[0483] In addition, according to this embodiment mode, the operation characteristics can be improved by using the transistor. It is possible to provide a semiconductor device having such a structure.

[0484] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0485] (Embodiment 8) In this embodiment, a transistor shown in this specification is used, and when power is not supplied, A semiconductor device that can retain memory contents even under certain conditions and has no limit on the number of times it can be written to. The configuration different from that shown in the seventh embodiment will be described below.

[0486] Fig. 32 is a perspective view of a semiconductor device. The semiconductor device shown in Fig. 32 has a memory circuit on the upper portion. A memory cell array including a plurality of memory cells (memory cell arrays 3400a to The memory cell array 3400n (where n is an integer of 2 or more) is provided in a plurality of layers. Logic circuits 300 required to operate the memory cell arrays 3400a to 3400n Has 4.

[0487] 33 is a partially enlarged view of the semiconductor device shown in FIG. 32. In FIG. 33, a logic circuit 300 4. The memory cell array 3400a and the memory cell array 3400b are shown. A plurality of memory cells included in the rechargeable cell array 3400a or the memory cell array 3400b Among them, memory cell 3170a and memory cell 3170b are shown as representatives. The memory cell 3170a and the memory cell 3170b may be, for example, the circuit configuration described in the seventh embodiment. It is also possible to adopt a configuration similar to that described above.

[0488] The transistor included in the memory cell 3170a is designated as a transistor 3171a. The transistor included in the memory cell 3170b is shown as a transistor 3171b. The transistor 3171a and the transistor 3171b have an oxide semiconductor layer having a channel. A transistor having a channel formation region in an oxide semiconductor layer. The configuration is the same as that described in the above embodiment, so the description will be omitted. .

[0489] In FIG. 33, the transistors 3171a and 3171b are Although the transistor 110 described in the first embodiment is illustrated, a transistor other than the transistor 110 may be used. A transistor may also be used.

[0490] In addition, the logic circuit 3004 uses a semiconductor material other than an oxide semiconductor for a channel formation region. The transistor 3001 is connected to the gate of the transistor 3002.

[0491] Here, the semiconductor material other than the oxide semiconductor is the second semiconductor material as described in the above embodiment. A first semiconductor material (such as silicon) that has a different band gap from that of an oxide semiconductor, which is a conductive material. ) The transistor using the first semiconductor material can easily operate at high speed. A transistor using an oxide semiconductor, which is the second semiconductor material, can be used for a long time due to its characteristics. This allows charge retention between the electrodes.

[0492] The transistor 3001 is fabricated on a substrate 3000 that includes a semiconductor material (such as silicon). A device isolation insulating layer 3116 is provided, and a channel forming region is formed in the region surrounded by the device isolation insulating layer 3116. A transistor can be obtained by forming a region that will become a region. The transistor 3001 is a semiconductor film such as a silicon film formed on an insulating surface, or a SOI substrate. The transistor may be a transistor in which a channel forming region is formed in the silicon film of the plate. The configuration of the star 3001 can be a known configuration, so the description is omitted. do.

[0493] Between a layer in which the transistor 3171a is formed and a layer in which the transistor 3001 is formed The wiring 3100a and the wiring 3100b are formed on the transistor. Between the layer on which the sta 3001 is formed, an insulating layer 3140a is provided, and the wiring 3100a An insulating layer 3141a is provided between the wiring 3100b and the transistor. An insulating layer 3142a is provided between the layer on which the star 3171a is formed.

[0494] Similarly, a layer in which the transistor 3171b is formed and a layer in which the transistor 3171a is formed Between the layers, a wiring 3100c and a wiring 3100d are formed. An insulating layer 3140b is provided between the layer in which the transistor 3171a is formed and the An insulating layer 3141b is provided between the line 3100c and the wiring 3100d. An insulating layer 3142b is provided between the layer in which the transistor 3171b is formed and the layer in which the transistor 3171b is formed. There are.

[0495] Insulating layer 3140a, insulating layer 3141a, insulating layer 3142a, insulating layer 3140b, insulating layer 3 The insulating layer 3142b functions as an interlayer insulating film and has a flattened surface. It can be said that:

[0496] The wiring 3100a, the wiring 3100b, the wiring 3100c, and the wiring 3100d form a memory cell. The electrical connection between the logic circuit 3004 and the memory cell can be performed. do.

[0497] The electrode 3303 included in the logic circuit 3004 is electrically connected to the circuit provided above. It is possible.

[0498] For example, as shown in FIG. 33, the electrode 3505 connects the electrode 3303 to the wiring 3100a. The wiring 3100a can be electrically connected to the wiring 310 by the electrode 3503a. The wiring 3100b can be electrically connected to the source of the transistor 3171a. The electrode 3501a is electrically connected to one of the source electrode and the drain electrode. In this way, the wiring 3100a and the electrode 3303 can be connected to the transistor 31 The electrode 3501a can be electrically connected to the source or drain of the transistor 71a. Pole 3503b allows electrical connection to be made with wiring 3100c.

[0499] In FIG. 33, two memory cells (memory cell 3170a and memory cell 3170b) are ) is stacked as an example, but the number of stacked memory cells is not limited to this. .

[0500] In FIG. 33, the electrode 3303 and the transistor 3171a are electrically connected to each other through a wiring 3100a. However, this is not limited to the above example. The electrical connection with the wiring 3100a may be made via the wiring 3100b, or the wiring 3100a and the wiring 3100b may be made via the wiring 3100c. Alternatively, the signal may be transmitted through both the wiring 3100a and the wiring 3100b. Alternatively, the measurement may be performed using other electrodes without using any electrodes.

[0501] In addition, in FIG. 33, a layer in which the transistor 3171a is formed and a layer in which the transistor 3001 is formed are Between the formed layer, two wirings, wiring 3100a and wiring 3100b, are provided. However, the present invention is not limited to this. A single wiring may be provided between the layer on which the transistor 3001 is formed, or three wirings may be provided between the layer on which the transistor 3001 is formed, More than one wiring may be provided.

[0502] In addition, in FIG. 33, a layer in which the transistor 3171b is formed and a layer in which the transistor 3171a is formed are Between the layer on which the wiring 3100 is formed, two wirings, wiring 3100c and wiring 3100d, are provided. However, the present invention is not limited to this. A wiring may be provided between the layer in which the transistor 3171a is formed and the , three or more wirings may be provided.

[0503] As described in this embodiment, a semiconductor having a band gap different from that of an oxide semiconductor which is a second semiconductor material is A transistor using a first semiconductor material having the above structure is stacked with a second semiconductor material, an oxide A plurality of transistors using a semiconductor layer are provided. The panel formation region is formed in a different region of the single oxide semiconductor layer. On a plurality of transistors each having a channel formation region in a different region of a single oxide semiconductor layer Furthermore, a channel formation region is formed in a different region of another single oxide semiconductor layer through an insulating layer. There may be provided a number of other transistors, each of which may be configured in accordance with the present invention. As shown in the first to third embodiments.

[0504] As described above, according to the present embodiment, a transistor capable of suppressing the occurrence of a parasitic channel is provided. You can get the data.

[0505] In addition, according to this embodiment mode, the operation characteristics can be improved by using the transistor. It is possible to provide a semiconductor device having such a structure.

[0506] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0507] (Embodiment 9) In this embodiment, the transistor shown in this specification is used, and even in a situation where power is not supplied, An example of a semiconductor device that can retain memory contents and has no limit to the number of times it can be written is shown in FIG. This will be explained using:

[0508] FIG. 34 shows an example of the structure of a semiconductor device. FIG. 34(A) shows a cross-sectional view of the semiconductor device. FIG. 34(B) shows a top view of the semiconductor device, and FIG. 34(C) shows a circuit diagram of the semiconductor device. Here, FIG. 34(A) is a cross section taken along lines Q1-Q2 and Q3-Q4 in FIG. 34(B). In addition, in FIG. 34B, a part of the configuration of the semiconductor device shown in FIG. The description of the elements is omitted.

[0509] The semiconductor device shown in FIG. 34(A) and FIG. 34(B) has a transistor using a first semiconductor material in the lower part. A transistor 669 is formed on the upper portion of the semiconductor substrate 662 using a second semiconductor material. In this embodiment, the transistor 662 is the transistor disclosed in the third embodiment. An example using a transistor 250 is shown.

[0510] Here, the first semiconductor material and the second semiconductor material may be materials having different forbidden band widths. For example, the first semiconductor material may be a semiconductor material other than an oxide semiconductor (such as silicon). The second semiconductor material can be an oxide semiconductor. The transistors used in this study can easily operate at high speed. The characteristics of the charge storage capacitor enable it to retain electric charge for a long period of time.

[0511] It should be noted that the above transistors are all n-channel transistors. However, it goes without saying that a p-channel transistor can be used. Other than the use of transistors as exemplified in the fine print (materials used in memory devices and memory devices The specific configuration of the above-mentioned structure is not limited to the configuration disclosed in this specification.

[0512] The transistor 669 in FIG. 34A includes a semiconductor material (e.g., silicon). A channel forming region 616 is provided in a substrate 600 including a semiconductor layer 614 and a semiconductor layer 615 is provided so as to sandwich the channel forming region 616. The impurity region 620 and the intermetallic compound region 624 in contact with the impurity region 620 are formed as shown in FIG. a gate insulating layer 608 provided on the channel forming region 616; A gate electrode 610 is provided on the gate electrode 610. In some cases, the transistor does not have a gate electrode or drain electrode. In this case, the source is sometimes used to explain the connection relationship of the transistor. The source and drain regions are sometimes referred to as the source electrode and drain electrode. In this specification, the term "source electrode" may include a source region.

[0513] An element isolation insulating layer 606 is provided on the substrate 600 so as to surround the transistor 669. An insulating layer 628 and an insulating layer 630 are provided to cover the transistor 669. In the transistor 669, a sidewall insulating layer (sidewall A thin insulating layer (insulating film) may be provided to form an impurity region 620 including regions with different impurity concentrations. The element isolation insulating layer 606 is formed using an element isolation technique such as LOCOS or STI. It is possible.

[0514] The transistor 669 using a single crystal semiconductor substrate can operate at high speed. By using this transistor as a read transistor, data can be read at high speed. Two insulating layers are formed to cover the transistor 669. As a process before forming the capacitor 662 and the capacitance element 664, the two insulating layers are subjected to CMP processing. Then, planarized insulating layers 628 and 630 are formed, and the upper surface of the gate electrode 610 is exposed at the same time. Make them give it to you.

[0515] The insulating layer 628 and the insulating layer 630 are typically made of silicon oxide, silicon oxynitride, or aluminum oxide. Minium, Aluminum Oxynitride, Silicon Nitride, Aluminum Nitride, Silicon Oxynitride An inorganic insulating material such as aluminum oxide nitride can be used. The layer 630 can be formed by using a plasma CVD method, a sputtering method, or the like.

[0516] In addition, organic materials such as polyimide, acrylic resin, and benzocyclobutene resin can be used. In addition to the above organic materials, low-dielectric constant materials (low-k materials) can also be used. When using organic materials, the insulating layer can be formed by wet methods such as spin coating and printing. 628, an insulating layer 630 may be formed.

[0517] In this embodiment, the insulating layer 628 is a silicon nitride film, and the insulating layer 630 is a silicon nitride film. A silicon oxide film is used.

[0518] A planarization treatment is performed on the surface of the insulating layer 630 in a region where the oxide semiconductor layer 644 is to be formed. In this embodiment, the surface is sufficiently planarized by a polishing process (e.g., a CMP process). Preferably, the average surface roughness of the insulating layer 630 is 0.15 nm or less. A semiconductor layer 644 is formed.

[0519] A transistor 662 illustrated in FIG. 34A has a channel formation region formed using an oxide semiconductor. The transistor 662 includes an oxide semiconductor layer 644 and a ring-shaped gate electrode 6 38, a source electrode 636, a ring-shaped drain electrode 637, and an insulating layer acting as a gate insulating layer. Here, the oxide semiconductor layer 644 included in the transistor 662 is a The channel formation region 644a is formed using an i-type or substantially i-type oxide semiconductor. By using an i-type oxide semiconductor for the channel formation region 644a, A transistor 662 with extremely excellent off characteristics can be obtained.

[0520] Since the off-state current of the transistor 662 is small, the use of this transistor allows for long-term recording. The contents of the memory can be retained, i.e., no refresh operation is required, or Since it is possible to realize a semiconductor device in which the frequency of refresh operations is extremely low, power consumption can be reduced. The power consumption can be reduced significantly.

[0521] An insulating layer 635 and an insulating layer 668 are provided over the transistor 662 as a single layer or a stacked layer. In this embodiment, aluminum oxide is used for the insulating layer 668. High density (density 3.2g / cm 3 More than 3.6 g / cm, preferably 3.6 g / cm 3 (or more) This allows the transistor 662 to have stable electrical characteristics.

[0522] In addition, a wiring 647 formed in the same layer as the drain electrode 637 and a wiring 648 formed in the same layer as the gate electrode 638 are An electrode 646 formed of a layer overlaps with an insulating layer 661 therebetween to form a capacitor element 664. That is, the transistor 662 and the capacitor element 664 can be formed on the same plane. The wiring 647 functions as one electrode of the capacitor 664, and the electrode 646 functions as one electrode of the capacitor 664. It should be noted that if no capacitance is required, a capacitor element 664 is provided. It is also possible to adopt a configuration in which no

[0523] The wiring 663 and the wiring 665 can be formed on the insulating layer 635 at the same time in the same process. In addition, the electrode 646 and the source electrode 636 are connected to the insulating layer 635 and the insulating The layer 668 is electrically connected to the insulating layer 661 through an opening formed in the insulating layer 661. , and the drain electrode is connected through another opening formed in the insulating layer 635, the insulating layer 668, and the insulating layer 661. It is electrically connected to electrode 637 .

[0524] In addition, an insulating layer 652 is provided over the transistor 662 and the capacitor 664 . In addition, a wiring 667 may be provided over the insulating layer 652 as necessary. However, the wiring 667 is electrically connected to the wiring 663 through an opening provided in the insulating layer 652. Here, the electrode may be formed by at least the oxide semiconductor layer 644 of the transistor 662. It is preferable that the second insulating film 10 is provided so as to overlap a part of the first insulating film 10.

[0525] The wiring 667 is connected to the gate electrode 638, the source electrode 636, or the drain electrode 637. The wiring 667, the gate electrode 638, and the source electrode 63 The electrical connection of the gate electrode 638, the source electrode 636 or the drain electrode 637 is This may be done by directly contacting the drain electrode 637 with the wiring 667, or by contacting the gate electrode 638 An electrode is provided on the insulating layer between the source electrode 636 or the drain electrode 637 and the wiring 667. The electrode may be disposed between the electrodes.

[0526] The source electrode 636 of the transistor 662 is connected to the insulating layer 632 through an opening. The wiring 633 is electrically connected to the gate of the transistor 669. That is, the source electrode 636 is electrically connected to the gate electrode 610. The transistor 669 and the transistor 662 are electrically connected to each other. The source electrode 636 of the transistor 669 and the The gate electrode 610 may be directly connected without using the wiring 633. By overlapping the transistor 662 with the transistor 69, the area occupied by the semiconductor device can be reduced. This allows for high integration.

[0527] Next, an example of a circuit configuration corresponding to FIGS. 34(A) and 34(B) is shown in FIG. 34(C).

[0528] In FIG. 34C, the first wiring (1st Line) and the source of the transistor 669 The electrode is electrically connected to the second wiring (2nd Line) and the transistor 669. The drain electrode is electrically connected. Also, the third wiring (3rd Line) The transistor 662 is electrically connected to one of a source electrode and a drain electrode of the first The fourth line and the gate electrode of the transistor 662 are electrically connected. The gate electrode of the transistor 669 and the source The other of the electrode and the drain electrode is electrically connected to one of the electrodes of the capacitor 664. The fifth line and the other electrode of the capacitor element 664 are electrically connected. do.

[0529] In the semiconductor device shown in FIG. 34C, the potential of the gate electrode of the transistor 669 can be held. By taking advantage of this feature, it is possible to write, retain, and read information as follows: .

[0530] The writing and holding of data will be described. First, the potential of the fourth wiring is set to the transistor 6 The transistor 662 is turned on by applying a potential to the transistor 662. The potential of the third wiring is applied to the gate electrode of the transistor 669 and the capacitor 664. That is, a predetermined charge is applied to the gate electrode of the transistor 669 (write Here, we consider charges that give two different potential levels (hereinafter, low-level charge and high-level charge). Then, the potential of the fourth wire is set to The transistor 662 is turned off by applying a potential to the transistor 662. As a result, the charge applied to the gate electrode of the transistor 669 is held (retained). .

[0531] Since the off-state current of the transistor 662 is extremely small, the gate electrode of the transistor 669 The charge is retained for a long period of time.

[0532] Next, the reading of information will be explained. A state in which a predetermined potential (constant potential) is applied to the first wiring When an appropriate potential (read potential) is applied to the fifth wiring, the gate of the transistor 669 Depending on the amount of charge held in the electrode, the second wire takes on a different potential. If the transistor 669 is an n-channel type, a high level voltage is applied to the gate electrode of the transistor 669. Apparent threshold voltage V under load th_H The gate of transistor 669 The apparent threshold voltage V when a low-level charge is applied to the gate electrode th_L Yo Here, the apparent threshold voltage is the voltage at which the transistor 669 is turned on. The term "potential of the fifth wiring" refers to the potential of the fifth wiring required to make the fifth wiring "on state." The potential of the line is V th_H and V th_L By setting the potential V0 between For example, in writing, the charge applied to the gate electrode of the high level If a Bell charge is applied, the potential of the fifth wire is V0 (>V th_H ) Then When a low-level charge is applied, the transistor 669 is in the "on state." The potential of the fifth wire is V0( <V th_L ), the transistor 669 is "off" Therefore, by observing the potential of the second wiring, the stored information It can be read out.

[0533] When memory cells are arranged in an array, only the information in a desired memory cell can be read. If the information is not read out, the state of the gate electrode is Regardless of the potential, transistor 669 is in the "off" state, i.e., V th_H Yo Alternatively, the transistor may be turned on regardless of the state of the gate electrode. The potential at which the transistor 669 is in the "on" state, that is, V th_L A larger potential Just give it to the fifth wire.

[0534] In the semiconductor device described in this embodiment, an off-state current is low when an oxide semiconductor is used for a channel formation region. By using extremely small transistors, memory contents can be retained for an extremely long period of time. In other words, the refresh operation is unnecessary or the refresh operation is possible. This allows the frequency of operation to be reduced significantly, resulting in a significant reduction in power consumption. In addition, when there is no power supply (however, it is preferable that the potential is fixed), However, it is possible to retain the stored contents for a long period of time.

[0535] In this way, a nonvolatile random access memory (RAM) can be realized by using a transistor including an oxide semiconductor. It is possible to realize this.

[0536] In addition, the semiconductor device described in this embodiment does not require a high voltage for writing data. There is no problem with degradation of the capacitance. For example, unlike conventional non-volatile memory, the floating gate Since there is no need to inject electrons into the floating gate or extract electrons from the floating gate, The problem of deterioration of the gate insulating layer does not occur at all. The device does not have the limit on the number of times it can be rewritten, which is a problem with conventional non-volatile memory, and is reliable. Furthermore, the on and off states of transistors allow the Since writing is performed, high speed operation can be easily achieved.

[0537] As described above, a semiconductor device that realizes miniaturization and high integration and is endowed with high electrical characteristics is provided. Locations can be provided.

[0538] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0539] (Embodiment 10) In this embodiment mode, the transistor described in the above embodiment mode is used, and A semiconductor device that can retain memory contents even under certain conditions and has no limit on the number of times it can be written to. The configuration different from that shown in the ninth embodiment will be described with reference to FIGS. 35 and 36. cormorant.

[0540] FIG. 35(A) shows an example of a circuit configuration of a semiconductor device, and FIG. 35(B) shows an example of a semiconductor device. First, the semiconductor device shown in FIG. The semiconductor device shown in FIG. 35B will be described.

[0541] In the semiconductor device shown in FIG. 35A, the bit line BL and the source voltage of the transistor 662 are The gate or drain electrode of the transistor 662 is electrically connected to the word line WL. The electrode is electrically connected to the source electrode or drain electrode of the transistor 662 and the capacitor. The first terminal of terminal 654 is electrically connected to the first terminal of terminal 654 .

[0542] Next, data is written and stored in the semiconductor device (memory cell 650) shown in FIG. The case where the above is performed will be explained.

[0543] First, the potential of the word line WL is set to a potential at which the transistor 662 is turned on. The transistor 662 is turned on. This causes the potential of the bit line BL to change to the potential of the capacitor 654. The potential of the word line WL is then applied to the first terminal (write). By setting the transistor 662 to an off state as a potential at which the transistor 662 is turned off, The potential of the first terminal of the quantum element 654 is held (held).

[0544] The transistor 662 including an oxide semiconductor has an extremely low off-state current. For this reason, when the transistor 662 is turned off, the first The potential of the terminal (or the charge stored in the capacitance element 654) is kept constant for an extremely long period of time. It is possible to retain it.

[0545] Next, the reading of information will be described. When the transistor 662 is turned on, The bit line BL and the capacitance element 654 are electrically connected to each other. As a result, the potential of the bit line BL changes. The amount of change in the potential is determined by the potential of the first terminal of the capacitance element 654 (or the potential stored in the capacitance element 654). It takes on different values ​​depending on the charge.

[0546] For example, the potential of the first terminal of the capacitance element 654 is V, the capacitance of the capacitance element 654 is C, and the bit line The capacitance component of BL (hereinafter also referred to as bit line capacitance) is CB, If the potential of the bit line BL is VB0, the potential of the bit line BL after the charge is redistributed is (CB×VB0+C×V) / (CB+C). Therefore, the state of memory cell 650 is In this case, the potential of the first terminal of the capacitance element 654 is assumed to be in two states, V1 and V0 (V1>V0). Then, the potential of the bit line BL when the potential V1 is held is (=(CB×VB0+C×V1 ) / (CB+C)) is the potential of the bit line BL when the potential V0 is held (=(CB × VB0+C×V0) / (CB+C)).

[0547] Then, by comparing the potential of the bit line BL with a predetermined potential, information can be read out. do.

[0548] In this manner, in the semiconductor device shown in FIG. 35A, the off-state current of the transistor 662 is extremely low. Because of its small size, the charge stored in the capacitance element 654 can be held for a long time. In other words, refresh operations are not required or the frequency of refresh operations can be reduced. Since it is possible to reduce the power consumption to an extremely low level, the power consumption can be reduced sufficiently. In addition, even if there is no power supply, the memory contents can be retained for a long period of time. be.

[0549] Next, the semiconductor device shown in FIG. 35B will be described.

[0550] The semiconductor device shown in FIG. 35B has the memory cell shown in FIG. 35A as a memory circuit in the upper portion. The memory cell arrays 651a and 651b each have a plurality of memory cells 650. The frequency required to operate the memory cell array 651 (memory cell arrays 651a and 651b) is The peripheral circuit 653 is electrically connected to the memory cell array 651. This is being continued.

[0551] By using the configuration shown in FIG. 35B, the peripheral circuit 653 is connected to the memory cell array 651. Since the insulating film can be provided directly below the semiconductor device, the semiconductor device can be made smaller.

[0552] The transistors provided in the peripheral circuit 653 are made of a different semiconductor material from the transistor 662. It is more preferable to use silicon, germanium, silicon germanium, etc. Silicon carbide, gallium arsenide, or the like can be used, and a single crystal semiconductor can be used. In addition, organic semiconductor materials may be used. The transistor is capable of sufficiently high speed operation. It is possible to realize various circuits (logic circuits, driver circuits, etc.) that require operation in an optimal manner. do.

[0553] In the semiconductor device shown in FIG. 35(B), two memory cell arrays 651 (memory cell In the illustrated example, a stacked memory cell array 651a and a stacked memory cell array 651b are used. The number of memory cell arrays to be stacked is not limited to this. It may also be configured as follows.

[0554] Next, a specific configuration of the memory cell 650 shown in FIG. 35(A) will be described with reference to FIG. Make a statement.

[0555] 36 is an example of the configuration of a memory cell 650. FIG. 36(B) shows a cross-sectional view of the memory cell 650, and FIG. 36(B) shows a top view of the memory cell 650. A) corresponds to the cross section at R1-R2 and R3-R4 in FIG. In order to make the diagram easier to understand, some components are omitted in FIG.

[0556] The transistor 662 shown in FIGS. 36A and 36B has the structure described in the above embodiment. The configuration may be the same as that of the conventional one.

[0557] A wiring 633 is formed on an insulating layer 680, and an insulating layer 632 is formed on the wiring 633. The transistor 662 provided over the insulating layer 632 is formed with an insulating layer 668 and an insulating layer 652. Also, the source electrode 636 of the transistor 662 is covered with the insulating layer 632. A wiring 633 is provided in the overlapping region. The source electrode 636 and the wiring 633 are insulated from each other. The electrical connection is made through an opening formed in the edge layer 632 .

[0558] In a region overlapping with the drain electrode 637 of the transistor 662, an insulating layer 645 is interposed. A line 656 is provided. The drain electrode 637, the insulating layer 645, and the wiring 656 A capacitance element 654 is formed. That is, the drain electrode 637 is The wiring 656 serves as the other electrode of the capacitor 654, and the insulating layer 645 acts as a dielectric.

[0559] A wiring 660 is provided over the insulating layer 652 that covers the transistor 662 and the capacitor 654. The wiring 660 is provided to connect the memory cell 650 to the adjacent memory cell 650. Although not shown, the wiring 660 is inserted through an opening provided in the insulating layer 652 and the insulating layer 668. The wiring 660 may be electrically connected to the gate electrode 638 through an insulating layer 652. The source electrode 662 of the transistor 662 is connected to the insulating layer 668 through an opening provided in the insulating layer 661. 36 or the drain electrode 637. The wiring 660 corresponds to the bit line BL in the circuit diagram of FIG.

[0560] In FIG. 36A and FIG. 36B, the wiring 633 is included in an adjacent memory cell. The transistor may be electrically connected to the source electrode 636. By adopting this, the area occupied by the semiconductor device can be reduced, and therefore high integration can be achieved. It is possible to achieve this.

[0561] By adopting the planar layout shown in FIG. 36(B), the area occupied by the semiconductor device can be reduced. Therefore, the semiconductor device can be highly integrated.

[0562] FIG. 37 is a cross-sectional view showing an example of a stacked structure of the semiconductor device shown in FIG. In FIG. 7, a peripheral circuit 653, a memory cell array 651a, and a memory cell array 651b are FIG. 37 illustrates a stacked structure of the memory cell array 651a. One of the resells 650 is shown as a memory cell 650a. One of the memory cells 650 included in the memory cell array 51b is shown as memory cell 650b. In addition, the transistor 662 included in the memory cell 650a is shown as a transistor 662a. The transistor 662 in the memory cell 650b is shown as a transistor 662b. There are.

[0563] The transistor 681 included in the peripheral circuit 653 is made of a material other than an oxide semiconductor (for example, a silicon The transistor 681 is provided on a substrate 670 formed of a material such as a capacitor. A region to be a channel forming region is formed in the region surrounded by the insulating layer 685. The transistor 681 can be formed on an insulating surface. A channel formation region is formed in a semiconductor layer such as silicon formed on a silicon substrate or in a silicon layer of an SOI substrate. The transistor 681 may have a known structure. Since it is possible to use it, the explanation will be omitted.

[0564] The memory cell array 651b is formed on the peripheral circuit 653 via an insulating layer 671. The memory cell array 651a is formed on the memory cell array 651b via an insulating layer 672. The memory cell array 651a is electrically connected to other circuits via wiring 660a. It can be connected.

[0565] Moreover, the insulating layers 671 and 672 function as interlayer insulating layers, and their surfaces are flattened. The configuration can be as follows.

[0566] The peripheral circuit 653, the memory cell array 651a, and the memory cell array 651b are connected to the wiring 67. 3, electrically connected by wiring 674, wiring 675, and wiring 660b.

[0567] The transistors 662a and 662b are transistors using an oxide semiconductor. A transistor using an oxide semiconductor has a low off-state current. Therefore, by using this, it is possible to retain memory contents for a long period of time. This allows the frequency of refresh operations to be reduced significantly, resulting in sufficient power consumption. can be reduced.

[0568] In addition, a transistor using a material other than an oxide semiconductor (in other words, a transistor capable of operating at sufficiently high speed) The peripheral circuits are made of transistors that can be used for semiconductors (or transistors that can be used for semiconductors in a broader sense). In order to realize the above, a memory circuit using a transistor having a sufficiently low off-state current is integrated in the semiconductor device. This makes it possible to realize a semiconductor device having unprecedented features. By forming the memory circuit in a stacked structure, the integration of the semiconductor device can be promoted.

[0569] As described above, a semiconductor device that realizes miniaturization and high integration and is endowed with high electrical characteristics is provided. In addition, the present invention provides a semiconductor device having a smaller number of defects than the conventional semiconductor device. Since it is possible to fabricate semiconductor devices using a lithography process, it is possible to produce semiconductor devices at low cost. It is possible to provide a semiconductor device with high productivity.

[0570] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0571] (Embodiment 11) In this embodiment, a transistor according to one embodiment of the present invention is used, and a transistor is A semiconductor device (memory device) that can retain memory contents even under certain conditions and has no limit on the number of times it can be written to. An example of the device will be described with reference to the drawings.

[0572] FIG. 38 shows an example of the structure of a semiconductor device. FIG. 38A shows a cross-sectional view of the semiconductor device. 38(B) shows a circuit diagram of the semiconductor device.

[0573] The semiconductor device shown in FIG. 38(A) and FIG. 38(B) uses a first semiconductor material in the lower part. A transistor 3200 is provided, and a transistor 3202 and a transistor 3203 are provided on the upper portion of the transistor 3200. and a capacitor element 3204.

[0574] In this embodiment, the transistor 3202 and the capacitor 3204 are 13 shows an example in which the transistor 310 and the capacitor 350 disclosed in Embodiment 5 are used.

[0575] Here, the first semiconductor material and the second semiconductor material may be materials having different forbidden band widths. For example, the first semiconductor material may be a semiconductor material other than an oxide semiconductor (such as silicon). The second semiconductor material can be an oxide semiconductor. The transistors used in this study can easily operate at high speed. The characteristics of the charge storage capacitor enable it to retain electric charge for a long period of time.

[0576] It should be noted that the above transistors are all n-channel transistors. However, it goes without saying that a p-channel transistor can be used. Other than the application of the transistors exemplified in the fine print (materials used in memory devices and memory devices) The specific configuration of the device (e.g., the structure of the device) is not limited to the configuration disclosed in this specification.

[0577] The transistor 3200 in FIG. 38A is made of a semiconductor material (e.g., silicon). A channel forming region is provided on a substrate 3000 including a channel forming region and a The impurity region is provided on the channel forming region, and the intermetallic compound region is provided on the channel forming region. The gate electrode is provided on the gate insulating layer. In the drawings, the source electrode and the drain electrode may not be explicitly shown. In some cases, the term "transistor" includes such a state. In order to explain the connection relationship, the source and drain regions are also included. In other words, in this specification, the term "source electrode" refers to a source It may include areas.

[0578] An element isolation insulating layer 3116 is provided on the substrate 3000 so as to surround the transistor 3200. An insulating layer 3220 is provided to cover the transistor 3200. The element isolation insulating layer 3116 is formed using an element isolation technique such as LOCOS or STI. It is possible.

[0579] For example, the transistor 3200 using a crystalline silicon substrate can operate at high speed. Therefore, by using the transistor as a read transistor, it is possible to read information. The formation of the transistor 3202 and the capacitor element 3204 can be performed at high speed. As a pre-processing step, the insulating layer 3220 covering the transistor 3200 is subjected to a CMP process to form an insulating The edge layer 3220 is planarized to simultaneously expose the top surface of the gate electrode of the transistor 3200. do.

[0580] A connection wiring 3 is provided on the gate electrode of the transistor 3200 to electrically connect the gate electrode. 210 and an insulating layer 3222 are provided.

[0581] In addition, a plurality of contact holes are formed in the insulating layer 3222. The contact plug 3215 electrically connects to the transistor 3202 and the capacitor A contact plug 3216 is formed to electrically connect to one electrode of the element 3204. As described in the fifth embodiment, the contact plug 3215 is It acts as the source electrode of 3202.

[0582] The capacitor is formed by connecting the wiring 3210, the insulating layer 3222, and the transistor 3202. A conductive layer (for example, a contact layer for the capacitance element 3204) that can be formed at the same time as the drain electrode. In this case, the contact plug 3216 may be formed of a non-contact layer. It is essential.

[0583] The transistor 3202 illustrated in FIG. 38A has a channel formed in an oxide semiconductor layer. The transistor 3202 is a top-gate transistor. By using this, it is possible to retain memory contents for a long period of time. Semiconductor memory that does not require a refresh operation or that requires a very infrequent refresh operation Since it is possible to use the memory device as a storage device, power consumption can be reduced sufficiently.

[0584] As shown in FIG. 38A, the transistor 3200 and the transistor 3202 are arranged so as to overlap each other. Therefore, the area occupied by the semiconductor device can be reduced. The integration density of semiconductor devices can be increased.

[0585] Next, an example of a circuit configuration corresponding to FIG. 38(A) is shown in FIG. 38(B).

[0586] In FIG. 38B, the first wiring (1st Line) and the source of the transistor 3200 The second line and the transistor 320 are electrically connected to each other. The drain electrode of the third wiring (3rd Line ) is electrically connected to one of the source electrode and the drain electrode of the transistor 3202. The fourth line and the gate electrode of the transistor 3202 are electrically connected to each other. The gate electrode of the transistor 3200 and the gate electrode of the transistor 32 One of the source electrode or the drain electrode of 02 is electrically connected to the other electrode of the capacitor element 3204. , and the fifth wiring (5th Line) and the other electrode of the capacitor element 3204 are electrically connected to are connected to the network.

[0587] In the semiconductor device shown in FIG. 38B, the potential of the gate electrode of the transistor 3200 can be held. By taking advantage of this feature, it is possible to write, store, and read information as follows: do.

[0588] The writing and holding of data will be described. First, the potential of the fourth wiring is set to The potential is set to a level at which the transistor 3202 is turned on, thereby turning on the transistor 3202. As a result, the potential of the third wiring is applied to the gate electrode of the transistor 3200 and the capacitor 320 That is, a predetermined charge is applied to the gate electrode of the transistor 3200. Here, the charge that gives two different potential levels (hereafter, Low level) is Then, a fourth charge (called a low-level charge or a high-level charge) is applied. The potential of the wiring is set to a potential at which the transistor 3202 is turned off, By turning off the transistor 3202, the charge applied to the gate electrode of the transistor 3200 is retained (retained).

[0589] Since the off-state current of the transistor 3202 is extremely small, the gate voltage of the transistor 3200 The charge on the pole is retained for a long period of time.

[0590] Next, the reading of information will be explained. A state in which a predetermined potential (constant potential) is applied to the first wiring When an appropriate potential (read potential) is applied to the fifth wiring, the gate of the transistor 3200 Depending on the amount of charge held in the transistor electrode, the second wiring has a different potential. If the transistor 3200 is an n-channel type, a high level is applied to the gate electrode of the transistor 3200. Apparent threshold V for a given Bell charge th_H is a transistor 3200 The apparent threshold voltage V when a low-level charge is applied to the gate electrode of th_LYo Here, the apparent threshold voltage is the voltage at which the transistor 3200 is The term "fifth wiring" refers to the potential of the fifth wiring required to turn the fifth wiring "on." The potential of the wiring is V th_H and V th_L By setting the potential V0 between The charge applied to the gate electrode of 200 can be distinguished. For example, in writing, When the h-level charge is applied, the potential of the fifth wire is V0 (>V th_H ) If a low-level charge is applied, the transistor 3200 is in the "on state." In this case, the potential of the fifth wire is V0( <V th_L ) even if the transistor is 3200 Therefore, by determining the potential of the second wiring, The information stored in the memory can be read out.

[0591] When memory cells are arranged in an array, only the information in a desired memory cell can be read. If the information is not read out, the state of the gate electrode is Regardless of the potential, transistor 3200 is in the “off state”, i.e., V th_H Alternatively, the potential of the gate electrode may be changed regardless of the state of the gate electrode. The potential at which the transistor 3200 is in the "on" state, that is, V th_L Larger current Just give the digits to the fifth wire.

[0592] In the semiconductor device described in this embodiment, an off-state current is low when an oxide semiconductor is used for a channel formation region. By using extremely small transistors, memory contents can be retained for an extremely long period of time. In other words, the refresh operation is unnecessary or the refresh operation is possible. This allows the frequency of operation to be reduced significantly, resulting in a significant reduction in power consumption. In addition, when there is no power supply (however, it is preferable that the potential is fixed), However, it is possible to retain the stored contents for a long period of time.

[0593] In addition, the semiconductor device described in this embodiment does not require a high voltage for writing data. There is no problem with degradation of the capacitance. For example, unlike conventional non-volatile memory, the floating gate Since there is no need to inject electrons into the floating gate or extract electrons from the floating gate, The problem of deterioration of the gate insulating layer does not occur at all. The device does not have the limit on the number of times it can be rewritten, which is a problem with conventional non-volatile memory, and is reliable. Furthermore, the on and off states of transistors allow the Since writing is performed, high speed operation can be easily achieved.

[0594] As described above, a semiconductor device that realizes miniaturization and high integration and has excellent electrical characteristics is developed. It is possible to provide a semiconductor device and a method for manufacturing the semiconductor device.

[0595] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0596] (Embodiment 12) In this embodiment mode, the transistor described in Embodiment 5 is used, and the transistor is used in a case where power is not supplied. However, regarding semiconductor devices that can retain memory contents and have no limit on the number of times they can be written, A semiconductor device having a configuration different from that shown in the eleventh embodiment will be described.

[0597] FIG. 39(A) shows an example of a circuit configuration of a semiconductor device, and FIG. 39(B) shows an example of a semiconductor device. 4162 and a capacitor included in the semiconductor device. The element 4254 is a transistor and a capacitor described in Embodiment 5. This can be done.

[0598] In the semiconductor device shown in FIG. 39A, the bit line BL and the source of the transistor 4162 The word line WL and the gate electrode of the transistor 4162 are electrically connected. The drain electrode of the transistor 4162 and one terminal of the capacitor 4254 are connected in series. are electrically connected.

[0599] Next, data is written to the semiconductor device (memory cell 4250) shown in FIG. The case where holding is performed will be described.

[0600] First, the potential of the word line WL is set to a potential at which the transistor 4162 is turned on. This causes the potential of the bit line BL to change to the potential of the capacitance element 42 The potential of the word line WL is then applied to one terminal of the transistor 54 (write). The transistor 4162 is turned off by using the potential at which the transistor 4162 is turned off. Thus, the potential of one terminal of the capacitor 4254 is held (retained).

[0601] The transistor 4162 including an oxide semiconductor has an extremely low off-state current. For this reason, when the transistor 4162 is turned off, the capacitor 4254 The potential of the first terminal (or the charge stored in the capacitor 4254) is kept constant for a very long time. It is possible to hold the signal for a long time.

[0602] Next, the reading of information will be described. When the transistor 4162 is turned on, The bit line BL in the free state and the capacitance element 4254 are electrically connected, and the bit line BL and the capacitance element 42 54. As a result, the potential of the bit line BL changes. The change in the potential of L is determined by the potential of the first terminal of the capacitance element 4254 (or the capacitance element 4254 It takes on different values ​​depending on the charge stored in the

[0603] For example, the potential of the first terminal of the capacitor 4254 is V, the capacitance of the capacitor 4254 is C, The capacitance component of the bit line BL (hereinafter also referred to as the bit line capacitance) is CB. If the previous potential of the bit line BL is VB0, then the potential of the bit line BL after the charge is redistributed is is (CB×VB0+C×V) / (CB+C). Therefore, the memory cell 4250 In this state, the potential of the first terminal of the capacitor 4254 is in two states of V1 and V0 (V1>V0). In this case, the potential of the bit line BL when the potential V1 is held is (=(CB×VB 0+C×V1) / (CB+C)) is the potential of the bit line BL when the potential V0 is held It can be seen that this is higher than (=CB×VB0+C×V0) / (CB+C)).

[0604] Then, by comparing the potential of the bit line BL with a predetermined potential, information can be read out. do.

[0605] In this manner, in the semiconductor device shown in FIG. 39A, the off-state current of the transistor 4162 is extremely small. Since the capacitance is small, the charge stored in the capacitor 4254 can be held for a long time. That is, the refresh operation is not required or the refresh operation can be performed This makes it possible to reduce the frequency of the power consumption significantly. In addition, even if there is no power supply, the memory contents can be retained for a long period of time. It is Noh.

[0606] Next, the semiconductor device shown in FIG. 39B will be described.

[0607] The semiconductor device shown in FIG. 39B has the memory cell shown in FIG. 39A as a memory circuit in the upper portion. A memory cell array 4251 having a plurality of memory cells 4250 (memory cell arrays 4251a and 4251b), and at the bottom, peripherals necessary for operating the memory cell array 4251 The peripheral circuit 4253 is electrically connected to the memory cell array 4251. is connected to

[0608] By using the configuration shown in FIG. 39B, the peripheral circuit 4253 is connected to the memory cell array 42 Since it can be provided directly below 51, the semiconductor device can be made smaller.

[0609] The transistor provided in the peripheral circuit 4253 is a semiconductor different from the transistor 4162. It is preferable to use materials such as silicon, germanium, and silicon germanium. , silicon carbide, gallium arsenide, etc., and a single crystal semiconductor is used. It is more preferable to use an organic semiconductor material. The transistor can operate at a sufficiently high speed. It is possible to realize various circuits (logic circuits, driver circuits, etc.) that require high speed operation. It is Noh.

[0610] In the semiconductor device shown in FIG. 39B, the memory cell array 4251 In the above example, a configuration in which the memory cell array 4251a and the memory cell array 4251b are stacked is illustrated. The number of memory cell arrays is not limited to this. A structure in which three or more memory cell arrays are stacked is also possible. It may be a single layer or a multilayer structure.

[0611] Next, a specific configuration of the memory cell 4250 shown in FIG. 39(A) will be described with reference to FIG. Provide an explanation.

[0612] FIG. 40 is a cross-sectional view of an example of the configuration of a memory cell 4250 formed on a substrate 4000. In FIG. 40, the source electrode of the transistor 4162 and the wiring 4222 (bit line BL) is electrically connected to the drain electrode of the transistor 4162 and one of the capacitor elements 4254. The gate electrode of the transistor 4162 (the third The electrode 316) is electrically connected to the wiring 4223 (word line WL) in a region not shown. Connected.

[0613] Note that the drain electrode of the transistor 4162 and one electrode of the capacitor 4254 are in the same layer. However, they may be electrically connected by other connection wiring or the like. In addition, the wiring 4222 is illustrated as a bit line BL, but the wiring may be formed through a contact plug or the like. Another wiring electrically connected to 4222 may be used as a bit line BL.

[0614] In addition, the substrate 4000 is replaced with a substrate including a peripheral circuit for driving the memory cell 4250. By electrically connecting the configuration of the memory cell 4250 and the peripheral circuit, the memory cell 4250 shown in FIG. As described above, the semiconductor device shown in FIG. The number of stacked layers 251 is not limited, and the peripheral circuits are arranged so that each memory cell array can be driven. It is sufficient that the input terminal 11 is electrically connected to the input terminal 11.

[0615] The transistor 4162 is formed using an oxide semiconductor. Since transistors have a low off-state current, they can retain stored data for a long period of time. In other words, the frequency of refresh operations can be reduced significantly, resulting in reduced power consumption. The force can be significantly reduced.

[0616] In addition, a transistor using a material other than an oxide semiconductor (in other words, a transistor capable of operating at sufficiently high speed) The peripheral circuits are made of transistors that can be used for semiconductors (or transistors that can be used for semiconductors in a broader sense). In order to realize the above, a memory circuit using a transistor having a sufficiently low off-state current is integrated in the semiconductor device. This makes it possible to realize a semiconductor device having unprecedented features. By forming the memory circuit in a stacked structure, the integration of the semiconductor device can be promoted.

[0617] As described above, a semiconductor device that realizes miniaturization and high integration and has excellent electrical characteristics is developed. An apparatus can be provided.

[0618] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0619] (Embodiment 13) In this embodiment, a transistor according to one embodiment of the present invention is used, and a transistor is A semiconductor device (memory device) that can retain memory contents even under certain conditions and has no limit on the number of times it can be written to. An example of the above-mentioned device will be described with reference to FIGS. 41 and 42.

[0620] FIG. 41A shows an example of a circuit configuration of a memory cell included in a memory device, and FIG. FIG. 41 is a conceptual diagram showing an example of a memory device. First, in the memory cell of the memory device shown in FIG. First, the memory device shown in FIG. 41(B) will be described.

[0621] In the memory cell shown in FIG. The word line WL and the gate of the transistor 701 are electrically connected. The source or drain of the transistor 701 and one electrode of the capacitor 702 are electrically connected to each other. In the memory device shown in FIG. As 01, the above-mentioned transistor is applied.

[0622] Next, a case where information is written and held in the memory cell shown in FIG. Reveal.

[0623] First, writing of information will be described.

[0624] The potential of the word line WL is set to a potential at which the transistor 701 is turned on. As a result, the potential of the bit line BL is set to one of the capacitor elements 702. Then, the potential of the word line WL is applied to the transistor 701. The transistor 701 is turned off by the potential for turning off the capacitor. The potential of one electrode of the element 702 is maintained (maintained).

[0625] The transistor 701 in which a channel is formed in an oxide semiconductor layer has an extremely low off-state current. Therefore, when the transistor 701 is turned off, The potential (accumulated charge) of one electrode of element 702 is maintained for an extremely long period of time. It is possible.

[0626] Next, the reading of information will be described.

[0627] The bit line BL is set in a floating state. Then, the potential of the word line WL is set to 0 by the transistor 701. The transistor 701 is turned on by applying a potential to the transistor 701 to turn it on. The bit line BL in this state and one electrode of the capacitor 702 are electrically connected to each other. The charge is redistributed between the bit line 702 and the bit line BL. As a result, the potential of the bit line BL changes. The amount of change in the potential of the line BL is determined by the potential (accumulated charge) of one electrode of the capacitor 702. Therefore, the values ​​are different.

[0628] For example, the potential of one electrode of the c...

Claims

[Claim 1] A first insulating layer is provided on the first wiring; an island-shaped oxide semiconductor layer on the first insulating layer; a source electrode and a drain electrode on the island-shaped oxide semiconductor layer, one of the source electrode and the drain electrode is electrically connected to the first wiring through an opening formed in the island-shaped oxide semiconductor layer and the first insulating layer; a second insulating layer on the island-shaped oxide semiconductor layer, the source electrode, and the drain electrode; a gate electrode on the second insulating layer, wherein one of the source electrode and the drain electrode is surrounded by the gate electrode in a plan view.

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