Display device

Abstract

To provide a semiconductor device, which is typified by a display device, including an oxide semiconductor layer, which can deal with the increase in size and definition of a screen, has excellent display quality, operates stably, and has high reliability.SOLUTION: By the use of a conductive layer containing Cu for a wire with long leading distance, the increase in wiring resistance can be suppressed. The conductive layer containing Cu does not overlap with an oxide semiconductor layer where a channel region in the TFT is formed and is covered with an insulating layer containing silicon nitride. Thus, the diffusion of Cu can be prevented and the semiconductor device with high reliability can be manufactured. In particular, even if a display device, which is one aspect of the semiconductor device, is increased in size and definition, the display quality can be high and the operation can be stable.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] Semiconductor device having a thin film transistor (hereinafter also referred to as a TFT) using an oxide semiconductor film And the present invention relates to a method for producing the same.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Generally speaking, electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices. [Background technology]

[0003] In recent years, semiconductor thin films (thicknesses between several nm and several hundred nm) formed on substrates with insulating surfaces have become popular. The technology of constructing thin film transistors (TFTs) using a thin film transistor (TFT) is attracting attention. Transistors are widely used in electronic devices such as ICs and electro-optical devices, especially in image display devices. Development of these materials as switching elements is being rushed. There are many different types of metal oxides and they have many applications. For example, indium oxide is a well-known material used in liquid crystal displays. It is used as a transparent electrode material required in industries such as automobiles.

[0004] Some metal oxides exhibit semiconducting properties. Metal oxides that exhibit semiconducting properties include Examples of such oxides include tungsten oxide, tin oxide, indium oxide, and zinc oxide. Thin film transistors that use metal oxides with such semiconducting properties as the channel formation region are already known. (Patent Document 1 and Patent Document 2).

[0005] In addition, in an active matrix type semiconductor device such as a liquid crystal display device, the screen size There is a trend for TVs to become larger, with diagonal sizes of 60 inches or more, and even 120 inches or more. The development is also taking into consideration the screen size. In addition, the screen resolution is also high definition. Image quality (HD, 1366 x 768), Full HD image quality (FHD, 1920 x 1080 ) and the trend is toward higher definition, with resolutions of 3840 x 2048 or 4096 x 2180. The development of so-called 4K digital cinema display devices is also underway.

[0006] The increase in screen size and resolution tends to increase the wiring resistance within the display. Increased resistance can cause delays in signal transmission to the end of the signal line and voltage drops in the power line. As a result, display quality may deteriorate, resulting in uneven display and poor gradation, and power consumption may increase. cormorant.

[0007] In order to suppress the increase in wiring resistance, a technology is being developed to form a low-resistance wiring layer using copper (Cu). This has been investigated (see, for example, Patent Documents 3 and 4). [Prior art documents] [Patent documents]

[0008] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A [Patent Document 3] JP 2004-133422 A [Patent Document 4] JP 2004-163901 A Summary of the Invention [Problem to be solved by the invention]

[0009] In order to prevent the increase in wiring resistance, technology is being investigated to form a low-resistance wiring layer using copper (Cu). However, Cu easily diffuses into semiconductors and silicon oxide, and This can cause unstable operation and a significant drop in yield.

[0010] One embodiment of the present invention is a method for preventing the influence of a voltage drop due to wiring resistance, a signal writing failure to a pixel, and a gray scale error. and to provide a semiconductor device, such as a display device, having a higher display quality. This is one of the challenges.

[0011] Another object of one embodiment of the present invention is to achieve high-speed operation of a semiconductor device.

[0012] Another object of one embodiment of the present invention is to achieve power saving in a semiconductor device.

[0013] Another object of one embodiment of the present invention is to achieve high-definition semiconductor devices.

[0014] Another embodiment of the present invention is a thin film transistor which includes an oxide semiconductor film and operates stably. It is another object of the present invention to provide a semiconductor device using the same. [Means for solving the problem]

[0015] That is, one embodiment of the present invention disclosed in this specification is a method for forming a first insulating layer containing silicon nitride on a substrate. a first conductive layer including Cu on the first insulating layer; a second insulating layer including silicon nitride on the second conductive layer; a third insulating layer including silicon oxide on the insulating layer; and a third conductive layer serving as a source electrode and a drain electrode over the oxide semiconductor layer; a fourth insulating layer including silicon oxide on the third conductive layer; and a silicon nitride layer on the fourth insulating layer. The fifth insulating layer includes a silicon substrate, and the fourth insulating layer and the fifth insulating layer are provided with an opening through which the silicon substrate is exposed. The third conductive layer functions as either a source electrode or a drain electrode. a fourth conductive layer connected to the first conductive layer, and a fifth conductive layer including Cu overlapping the fourth conductive layer; A sixth insulating layer including silicon nitride covering the fifth conductive layer is provided. and the sixth insulating layer is provided with an opening through which the other of the source electrode and the drain electrode is provided. a sixth conductive layer electrically connected to the third conductive layer, the sixth conductive layer being electrically connected to the first conductive layer and the fifth conductive layer; The semiconductor device is characterized in that the conductive layer does not overlap with the oxide semiconductor layer.

[0016] The first conductive layer or the fifth conductive layer is made of W, Ta, Mo, Ti, Cr, Zr, or Ca. It is preferable that at least one element selected from the above is included. In addition, the second conductive layer is preferably made of an element having a melting point higher than that of Cu.

[0017] In addition, one embodiment of the present invention disclosed in this specification is a semiconductor device including a semiconductor device having a first insulating layer including silicon nitride formed on a substrate. forming a first conductive layer containing Cu on the first insulating layer; and forming a first conductive film on the first conductive layer. forming a second conductive layer covering the layer; and forming a second insulating layer including silicon nitride on the second conductive layer. forming a third insulating layer containing silicon oxide on the second insulating layer; forming island-shaped oxide layers on the third insulating layer; A semiconductor layer is formed on the island-shaped oxide semiconductor layer, and the semiconductor layer functions as a source electrode and a drain electrode. forming a third conductive layer including a first insulating layer and a fourth insulating layer including silicon oxide on the third conductive layer; A fifth insulating layer containing silicon nitride is formed on the fourth insulating layer, and a fourth insulating layer and a fifth insulating layer are formed on the fourth insulating layer. Through the opening, a semiconductor device that functions as either a source electrode or a drain electrode is A fourth conductive layer is formed to electrically connect to the third conductive layer, and Cu is disposed on the fourth conductive layer. forming a fifth conductive layer including silicon nitride, and forming a sixth insulating layer including silicon nitride covering the fifth conductive layer; A source electrode is provided through an opening provided in the fourth insulating layer, the fifth insulating layer, and the sixth insulating layer. or a sixth conductive layer electrically connected to the third conductive layer functioning as the other of the drain electrodes. After the oxide semiconductor layer is formed, first heat treatment is performed to dehydrate the oxide semiconductor layer. The first conductive layer and the fifth conductive layer are not overlapped with the oxide semiconductor layer. The present invention relates to a method for manufacturing a semiconductor device.

[0018] The first heat treatment is performed by using the RTA method at a temperature of 400° C. or higher and lower than 750° C., using a rare gas or It is preferable that the first heat treatment is performed under a nitrogen atmosphere after the fourth insulating layer is formed. It is preferable to carry out the second heat treatment at a temperature lower than that of the first heat treatment.

[0019] Further, one embodiment of the present invention disclosed in this specification is a semiconductor device having a base insulating layer containing silicon nitride over a substrate. A conductive layer containing Cu on an insulating base layer and a conductive layer containing a high melting point metal covering the conductive layer containing Cu. The gate wiring is formed by laminating the insulating layer containing silicon nitride and the insulating layer containing silicon oxide on the gate wiring. a gate insulating layer including a stack of insulating layers each including an oxide semiconductor island on the gate insulating layer; A semiconductor layer has a source electrode and a drain electrode on the island-shaped semiconductor layer, An interlayer insulating layer consisting of a laminate of an insulating layer containing silicon oxide and an insulating layer containing silicon nitride is formed on the in-electrode. a barrier layer having conductivity on the interlayer insulating layer and a laminate of a conductive layer containing Cu on the barrier layer; The source wiring is formed by connecting the source wiring to an opening provided in the interlayer insulating layer. A passivation layer containing silicon nitride is electrically connected to the source electrode and is provided on the source wiring. On the passivation layer, through an opening provided in the passivation layer and the interlayer insulating layer, In this case, the conductive layer is electrically connected to the drain electrode, and the conductive layer containing Cu in the gate wiring is The conductive layer containing Cu in the source wiring is a semiconductor in which the channel of the thin film transistor is formed. The semiconductor device is characterized in that it does not overlap with any other layer.

[0020] In addition, one embodiment of the present invention disclosed in this specification is a semiconductor device having an active matrix circuit and a drive circuit on a substrate. The active matrix circuit has a drive circuit and a protection circuit. The current carrying wiring and power supply lines have a wiring layer containing Cu. The wiring layer containing Cu is The semiconductor layer of the thin film transistor in the driver circuit and the protection circuit does not overlap with the semiconductor layer of the thin film transistor in the switch circuit. The connection of the thin film transistor in the semiconductor device is formed without using a wiring layer containing Cu, and the connection of the thin film transistor in the semiconductor device is formed without using a wiring layer containing Cu. is a semiconductor device characterized in that it has a structure in which a gate electrode is sandwiched between insulating layers containing silicon nitride.

[0021] The semiconductor layer is InMO3(ZnO) m (m>0 and m is a non-natural number) A semiconductor material can be used. M is selected from Ga, Fe, Ni, Mn, and Co. It refers to one or more metallic elements in a compound. For example, In-Ga-Zn-O system, In -Sn-Zn-O, In-Al-Zn-O, Sn-Ga-Zn-O, Al-Ga- Zn-O series, Sn-Al-Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Z An nO-based, In-O-based, Sn-O-based, or Zn-O-based oxide semiconductor film is used.

[0022] In the active matrix circuit, the source wiring that transmits the video signal to each pixel TFT, Gate wiring, storage capacitance lines, power supply lines, and driver circuits that control the on / off state of pixel TFTs Power lines, common potential lines, and lead-in lines from terminals that input and output signals to and from the outside. By using a conductive layer containing Cu for wiring with long wiring distances, the increase in wiring resistance can be suppressed. can be done.

[0023] The conductive layer containing Cu is arranged so as not to overlap with the semiconductor layer in which the channel region of the TFT is formed. By doing so, the influence of Cu diffusion can be prevented.

[0024] The insulating layers located above and below the conductive layer containing Cu are insulating layers containing silicon nitride, By sandwiching or wrapping the conductive layer containing Cu between layers, it is possible to prevent the diffusion of Cu.

[0025] In this specification, the term "gate" refers to a gate electrode and a part or the whole of a gate wiring. The gate wiring is a wiring that connects at least one gate electrode of a transistor to another electrode or This refers to a wiring for electrically connecting to another wiring, and is used, for example, as a scanning The lines are also included in the gate wiring.

[0026] The source refers to a source region, a source electrode, and a part or all of a source wiring. The source region is a region of the semiconductor layer whose resistivity is equal to or lower than a certain value. The source wiring is defined as at least a conductive layer connected to a source region. A transistor for electrically connecting a source electrode of a transistor to another electrode or another wiring. For example, when a signal line in a display device is electrically connected to a source electrode, In this case, the source wiring also includes the signal line.

[0027] The drain refers to the drain region, drain electrode, and part or all of the drain wiring. The drain region is a region of the semiconductor layer whose resistivity is equal to or lower than a certain value. The drain electrode is the conductive layer that is connected to the drain region. The drain electrode of at least one transistor is electrically connected to another electrode or another wiring. For example, a signal line in a display device is connected to a drain electrode. When electrically connected, the drain wiring also includes the signal line.

[0028] In addition, in this document (specification, claims, drawings, etc.), The source and drain are interchangeable depending on the transistor structure and operating conditions. It is difficult to determine whether one is the source or the drain. In the specification, claims, drawings, etc., either the source or the drain One of the terminals is arbitrarily selected and referred to as the source and drain, and the other terminal is referred to as the source and drain. It is referred to as the other side of Rain.

[0029] In this specification, the term "light-emitting device" refers to an image display device, a light-emitting device, or a light Also, the light emitting device is connected to a connector, such as FPC (Flexib le printed circuit) or TAB (Tape Automate d Bonding) tape or TCP (Tape Carrier Packag e) is attached to the module, the printed wiring board is attached to the end of the TAB tape or TCP. A module with a COG (Chip On Glass) s) All modules in which an IC (integrated circuit) is directly mounted using this method are included in the light-emitting device. Let us assume that. Effect of the Invention

[0030] A thin film transistor using an oxide semiconductor film and having good electrical characteristics and high reliability, and a thin film transistor using a Cu-containing By using a source wiring and a gate wiring made of a conductive layer including the In semiconductor devices, the area of ​​the pixel portion is increased and a good display is realized even when the screen is enlarged. Since the resistance of the wiring in the pixel section can be significantly reduced, The embodiment of the present invention can also be used for large screens with a diagonal of 60 inches or 120 inches. It can also be used for high-definition screens such as full HD and 4K digital cinema. [Brief description of the drawings]

[0031] [Figure 1] 1A and 1B are a plan view and a circuit diagram illustrating one embodiment of the present invention. [Diagram 2] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of the present invention. [Diagram 3] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 4] 1A to 1C are cross-sectional process views illustrating one embodiment of the present invention. [Diagram 5] 1A to 1C are cross-sectional process views illustrating one embodiment of the present invention. [Figure 6] FIG. 4 is a diagram for explaining a multi-tone mask. [Figure 7] 1A to 1C are cross-sectional process views illustrating one embodiment of the present invention. [Figure 8] 1A to 1C are a plan view, a cross-sectional view, and a circuit diagram illustrating one embodiment of the present invention. [Figure 9] 1A and 1B are a circuit diagram and a plan view illustrating one embodiment of the present invention. [Figure 10] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 11] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of the present invention. [Figure 12] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of the present invention. [Figure 13] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of the present invention. [Figure 14] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 15] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 16] 1A and 1B are diagrams illustrating a pixel equivalent circuit of a semiconductor device. [Figure 17] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 18] FIG. 1 is a block diagram illustrating a display device. [Figure 19] 1A and 1B are a diagram illustrating a configuration of a signal line driver circuit and a timing chart illustrating the operation of the signal line driver circuit. [Figure 20] FIG. 1 is a circuit diagram showing a configuration of a shift register. [Figure 21] 1A and 1B are a circuit diagram and a timing chart illustrating the operation of a shift register; [Figure 22] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 23] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 24] 1A and 1B are diagrams illustrating examples of usage of electronic paper. [Diagram 25] FIG. 1 is an external view showing an example of an electronic book. [Figure 26] FIG. 1 is an external view showing an example of a television device and a digital photo frame. [Figure 27] FIG. 1 is an external view showing an example of a gaming machine. [Figure 28] FIG. 1 is an external view showing an example of a portable computer and a mobile phone. [Figure 29] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 30] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 31] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 32] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 33] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 34] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 35] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 36] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 37] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 38] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 39] 1A and 1B are a cross-sectional view and a circuit diagram illustrating one embodiment of the present invention. [Diagram 40] A diagram showing the crystal structure of metal and oxygen in IGZO. [Diagram 41] 1A and 1B are diagrams illustrating a structural model of a metal atom and an oxygen atom in the vicinity of an interface between a tungsten film and an oxide semiconductor film. [Diagram 42] 1A and 1B are diagrams showing a structural model of a metal atom and an oxygen atom in the vicinity of an interface between a molybdenum film and an oxide semiconductor film. [Diagram 43] 1A and 1B are diagrams showing a structural model of a metal atom and an oxygen atom in the vicinity of an interface between a titanium film and an oxide semiconductor film. [Diagram 44] FIG. 1 is a diagram showing the crystal structure of titanium dioxide having a rutile structure. [Diagram 45] Density of states diagram of titanium dioxide having a rutile structure. [Figure 46] Density of states diagram of oxygen-deficient titanium dioxide. [Figure 47] Density of states diagram of titanium monoxide. [Figure 48] FIG. 1 is a band diagram illustrating one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0032] The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention is not limited to the above embodiment, and various changes and modifications may be made in the form and details without departing from the spirit and scope of the present invention. It will be easily understood by those skilled in the art that the above-mentioned invention can be obtained by the following embodiments. The present invention should not be construed as being limited to the contents described below. The same reference numerals are used in different drawings to indicate the same parts or parts having similar functions. A repeated explanation thereof will be omitted.

[0033] (Embodiment 1) In this embodiment, a display device in which a semiconductor element using an oxide semiconductor is formed in a pixel portion and its periphery is One embodiment of the display device will be described with reference to FIG. 1(A) and FIG. 1(B).

[0034] The structure of a display device 30 is shown in FIG. and a source terminal portion 8. The display device 30 also includes a gate line 20_1 and a gate Gate wiring (20_1 to 20_n (n is a natural number)) including the wiring 20_2, and The source wirings (60_1 to 60_m (however, In addition, the pixel region 94 of the display device 30 includes a pixel 93. Each pixel 93 is connected to at least one pair of gate wiring and source wiring. The NI PXIe-8110 is connected to the power wiring.

[0035] The display device 30 also includes a common wiring 44, a common wiring 45, a common wiring 46, and a common wiring 65. In addition, for example, the common wiring 45 is connected to the common wiring 65 via a connection portion 95, The common wirings are electrically connected to each other and have the same potential.

[0036] The common wiring 44, the common wiring 45, the common wiring 46 and the common wiring 65 are connected to a terminal 71, a terminal 75, terminal 81, and terminal 85. The common wiring is also connected to the opposing substrate. It has a common connection portion 96 that can be electrically connected to the plate.

[0037] In addition, the gate signal line terminals (70_1 to 70_i (where i is a natural number)) of the gate terminal section 7 are The gate driver circuit 91 (hereinafter, also referred to as a scanning line driver circuit) is connected to the gate driver circuit 91 via a protection circuit 97. The terminal 74 is connected to the gate drive circuit 91. This connects an external power supply (not shown) to the gate drive circuit 91. 20_1 to 20_n (where n is a natural number) are connected to the common wiring 65 via a protection circuit 97. It is being done.

[0038] In addition, the source signal line terminals (80_1 to 80_k (where k is a natural number)) of the source terminal section 8 are The signal line driver circuit 92 is connected to the source driver circuit 92 (hereinafter, also referred to as a signal line driver circuit) and is connected to the source driver circuit 92 via a protection circuit 97. The terminal 84 is connected to the source driver circuit 92. This connects an external power supply (not shown) to the source driver circuit 92. 60_1 to 60_m (where m is a natural number) are connected to the common wiring 45 via a protection circuit 97. It is being done.

[0039] The gate driver circuit and the source driver circuit use the thin film transistor disclosed in this specification, The gate driver circuit and the source driver circuit can be formed simultaneously with the pixel. Either or both of them are formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate. The chip may be mounted by using a COG method, a wire bonding method, a TAB method, or the like.

[0040] An example of an equivalent circuit applicable to the pixel 93 is shown in FIG. The circuit is an example in which a liquid crystal element is used as a display element in the pixel 93 .

[0041] Next, an example of the configuration of a pixel of the display device shown in FIG. 1 will be described with reference to FIG. 2B and 2C are plan views showing the layered structure of the pixel. In addition, A1-A2, B1-B2, and C1-C2 in FIG. The dashed lines correspond to the sections A1-A2, B1-B2, and C1-C2 in FIG. 2(B). The dashed line D1-D2 in FIG. 2(A) corresponds to the cross section D1-D2 in FIG. 2(C). Correct.

[0042] The cross sections A1-A2 and D1-D2 are cross sections of the thin film transistor 250 used in the pixel portion. The layer structure is shown. The thin film transistor 250 is an embodiment of a bottom gate structure.

[0043] In the cross sections A1-A2 and D1-D2, an insulating layer 201 provided on a substrate 200 and A gate wiring 202 is provided on the insulating layer 201, and a gate insulating film 203 is provided on the gate wiring 202. A gate wiring 203, an insulating layer 204 provided on the gate wiring 203, and a A semiconductor layer 205 is provided, and a pair of electrodes 207a and an electrode 207b are provided on the semiconductor layer 205. The electrode 207b and an insulating layer provided on the electrode 207a, the electrode 207b, and the semiconductor layer 205. 208, and the source wiring 2 contacting the electrode 207a through an opening provided in the insulating layer 208. 09, a source wiring 210 provided on the source wiring 209, and The insulating layer 211 is connected to the insulating layer 208 through an opening provided in the insulating layer 211 and the insulating layer 208. and an electrode 212 in contact with the electrode 207b.

[0044] Also, the cross section B1-B2 shows the laminated structure of a storage capacitor (also called a Cs capacitor). In B1-B2, an insulating layer 201 is formed on a substrate 200, and a storage capacitor wiring 2 is formed on the insulating layer 201. 13, a storage capacitor wiring 214 on the storage capacitor wiring 213, and an insulating layer 214 on the storage capacitor wiring 214. 204, an electrode 207b on the insulating layer 204, an insulating layer 208 on the electrode 207b, and an insulating layer 208, and an insulating layer 211 and an electrode 212 on the insulating layer 211. It is preferable to use an oxide semiconductor for the layer 205. For details of the oxide semiconductor, the description in Embodiment 2 can be referred to.

[0045] Also, the cross section C1-C2 shows the laminated structure at the wiring intersection between the gate wiring and the source wiring. In the cross section C1-C2, an insulating layer 201 is formed on a substrate 200, and a gate insulating layer 202 is formed on the insulating layer 201. A gate wiring 202, a gate wiring 203 on the gate wiring 202, and an insulating film on the gate wiring 203. An edge layer 204, an insulating layer 208 on the insulating layer 204, and a source wiring 209 on the insulating layer 208. A source wiring 210 is formed on the source wiring 209, and an insulating layer 211 is formed on the source wiring 210. Yes.

[0046] For details on the materials of each part, etc., please refer to embodiment 2.

[0047] In addition, a structure in which a semiconductor layer is formed between the insulating layer 204 and the insulating layer 208 at the wiring intersection portion is used. By adopting such a structure, the distance between the gate wiring and the source wiring in the film thickness direction can be reduced. Since the spacing can be increased, the parasitic capacitance at the wiring intersection can be reduced.

[0048] One embodiment of the present invention is not limited to the pixel configuration shown in FIG. The elemental structure is illustrated in Fig. 3. The thin film transistor 251 illustrated in Fig. 3 has a bottom gate structure. This is one mode of a thin film transistor and can be called a channel protective type.

[0049] The thin film transistor 251 includes an insulating layer 201 provided on a substrate 200 and a A gate wiring 202 is provided on the gate electrode 201, and a gate wiring 203 is provided on the gate wiring 202. 2, an insulating layer 204 provided on the gate wiring 203, and a semiconductor A channel protection layer 225 provided on the semiconductor layer 205 and a channel protection layer 2 25 and a pair of electrodes 207a and 207b provided on the semiconductor layer 205; 207a, the electrode 207b, and an insulating layer 208 provided on the semiconductor layer 205; A source wiring 209 contacting the electrode 207a through an opening provided in the source wiring 208; A source wiring 210 is provided on the insulating layer 21. 1 and contacts the electrode 207b through an opening provided in the insulating layer 211 and the insulating layer 208. and an electrode 212.

[0050] The storage capacitor of the pixel exemplified in this embodiment is a storage capacitor wiring formed in the same layer as the gate wiring. An insulating layer 204 is formed between the electrode 207b and the storage capacitor wiring 213 and the storage capacitor wiring 214. Compared to the electrode 212 or the source line 210, the electrode 207b is Since it is adjacent to the storage capacitor wiring 214 in the thickness direction, it is suitable for forming a storage capacitor.

[0051] The gate wiring 202 and the source wiring 210 are formed of a conductive material containing Cu. The increase in resistance can be prevented. In addition, the gate wiring 203 is made of W, Ta, Mo, Ti, C A conductive material containing an element having a melting point higher than that of Cu, such as r, is used to contact the gate wiring 202 and By forming the gate wiring 202 so as to cover the entire surface of the semiconductor device, migration of the gate wiring 202 is suppressed. In addition, the upper and lower sides of the gate wiring 202 containing Cu can be formed on the upper and lower sides of the gate wiring 202. The insulating layer located on the side of the gate electrode 20 is an insulating layer containing silicon nitride, and the insulating layer is a gate wiring 20 containing Cu. By sandwiching or wrapping the gate wiring 202, the diffusion of Cu contained in the gate wiring 202 is prevented. It is possible to do so.

[0052] Also, the gate wiring 202 is overlapped with the semiconductor layer 205 in which the channel of the thin film transistor is formed. The gate wiring 203 is arranged so as not to be folded, and a part of the gate wiring 203 that contacts the gate wiring 202 is extended. The semiconductor layer 205 is overlapped with the gate electrode. The Cu contained in the gate wiring 202 is a thin film transistor having a semiconductor layer containing an oxide semiconductor. This can further reduce the effect on the resistor.

[0053] In addition, at least an insulating layer 204 and an insulating layer 205 are provided between the gate wiring and the source wiring at the wiring intersection. By sandwiching the layer 208, the distance between the wirings in the film thickness direction can be greatly increased. As a result, the parasitic capacitance at the wiring intersection can be reduced.

[0054] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0055] (Embodiment 2) In this embodiment mode, a manufacturing process of a pixel portion of the display device described in the first embodiment mode will be described with reference to FIG. 4 and 5. Note that the cross sections A1-A2 and B1- The cross sections A1-A2, B1-B2, C1-C2, and D1-D2 in FIG. 11A and 11B are cross-sectional views of the areas indicated by the dashed lines of B2, C1-C2, and D1-D2.

[0056] First, an insulating layer 201 containing silicon nitride is formed as an underlying insulating layer on a substrate 200 to a thickness of 50 nm or more and 30 nm or more. The substrate 200 is formed to a thickness of 0 nm or less, preferably 100 nm or more and 200 nm or less. In addition to glass and ceramic substrates, any substrate that has sufficient heat resistance to withstand the processing temperatures of this manufacturing process is also available. In addition, when the substrate does not need to be transparent, Alternatively, a metal substrate such as a stainless steel alloy substrate having an insulating film formed on its surface may be used. The plate may be made of, for example, barium borosilicate glass, aluminoborosilicate glass, or alumina. It is recommended to use a non-alkali glass substrate such as luminosilicate glass. The substrate 200 may be a third generation (550 mm× 650mm), 3.5th generation (600mm x 720mm, or 620mm x 750mm ), 4th generation (680mm x 880mm, or 730mm x 920mm), 5th generation ( 1100mm x 1300mm), 6th generation (1500mm x 1850mm), 7th generation ( 1870mm x 2200mm), 8th generation (2200mm x 2400mm), 9th generation ( 2400mm x 2800mm, 2450mm x 3050mm, 10th generation (2950m A glass substrate having a size of 3400 mm×3,400 mm or the like can be used. In this embodiment, the substrate 20 Aluminoborosilicate glass is used for 0.

[0057] The insulating layer 201 can be formed by a single layer or a stack of a silicon nitride film or a silicon nitride oxide film. In this specification, silicon nitride oxide refers to a material having a composition containing more nitrogen than oxygen. The content of oxygen is high, and preferably, it is characterized by Rutherford backscattering spectrometry (RBS) and When measured using hydrogen forward scattering spectrometry (HFS), the composition range was 5 to 3 oxygen. 0 atomic %, nitrogen 20-55 atomic %, silicon 25-35 atomic %, hydrogen 10-30 atomic % The insulating layer 201 is formed by a method such as a sputtering method, a CVD method, a coating method, In this embodiment, the insulating layer 201 is formed to a thickness of 100 nm. A silicon nitride film with a thickness of 100 nm is formed. The film is doped with phosphorus (P) and boron (B). That's fine.

[0058] Next, a 1000 nm thick film is formed on the insulating layer 201 by using a sputtering method, a vacuum deposition method, or a plating method. Cu is deposited to a thickness of 00 nm or more and 500 nm or less, preferably 200 nm or more and 300 nm or less. A conductive film containing the compound is formed on the conductive film by a photolithography method, an ink-jet method, or the like. A mask is formed, and the conductive film is etched using the mask to form the gate wiring 202 and the protective film. A capacitance line 213 can be formed.

[0059] In order to improve the adhesion of the gate line 202, between the insulating layer 201 and the gate line 202, Metal layers using W, Ta, Mo, Ti, Cr, etc., or alloy layers combining these Alternatively, a nitride or oxide of these may be formed.

[0060] In addition, the formation of Cu by the sputtering method can be achieved using not only pure Cu material as the target material. Cu with W, Ta, Mo, Ti, Cr, Al, Zr, Ca, or other elements A Cu alloy material containing 10 wt% or less, preferably 2 wt% or less of the element is used. By using Cu alloy materials, it is possible to improve the adhesion of Cu wiring and prevent malformations such as hillocks. The migration resistance can be improved.

[0061] In addition, a rare gas such as Ar can be used as the sputtering gas. By using a sputtering gas containing oxygen, a Cu oxide is formed at the interface with the substrate. In this case, the tantalum alloy containing elements that are more easily oxidized than Cu is used. By using a get material, the adhesion can be improved. Since the resistance is higher than that of u, sputtering with oxygen added to rare gas only at the beginning of sputtering It is advisable to use a rare gas and then perform sputtering using only a rare gas.

[0062] In addition, when the resist mask is formed by the inkjet method, a photomask is not used. This reduces manufacturing costs. In addition, the conductive nanopaste such as copper is applied by the inkjet method. The gate wiring 202 and the storage capacitor wiring 213 are formed inexpensively by discharging the material onto a plate and baking it. It is possible.

[0063] In this embodiment, a Cu film having a thickness of 250 nm is formed on the insulating layer 201 by sputtering. A film is formed, and a Cu film is formed using the resist mask formed in the first photolithography process. Selective etching is performed to form the gate wiring 202 and the storage capacitor wiring 213 (FIG. 4 (See (A)).

[0064] Next, W, Ta, or the like is deposited on the gate wiring 202 by sputtering, vacuum deposition, or the like. Elements with higher melting points than Cu, such as Mo, Ti, and Cr, or combinations of the above elements The conductive film is made of an alloy or the like, and has a thickness of 5 nm to 200 nm, preferably 10 nm to 100 nm. The conductive film is not limited to a single layer containing the above-mentioned elements, but may be a laminate of two or more layers. In this embodiment, a tungsten single layer structure having a thickness of 200 nm can be used. A conductive film is formed. Note that the conductive film is formed after at least the first heat treatment and the second heat treatment. It is preferable that the material has heat resistance sufficient to withstand heat treatment.

[0065] Alternatively, the conductive film is a transparent conductive oxide containing any one of indium, tin, and zinc. For example, indium oxide (In2O3) or an indium oxide tin oxide alloy may be used. It is preferable to use In2O3-SnO2 (abbreviated as ITO). A material in which an insulating oxide such as silicon oxide is added to the oxide may be used. By using the material as a conductive film, the aperture ratio of a display device can be improved.

[0066] Next, a mask is formed on the conductive film by photolithography, inkjet printing, or the like. The conductive film is then etched using the mask to form the gate wiring 203 and the storage capacitor wiring 204. In this embodiment, the second photolithography process can form the first insulating film 14. The conductive film is selectively etched using a resist mask to form the gate wiring 203 and the storage capacitor. A quantity wiring 214 is formed (see FIG. 4(B)).

[0067] The gate wiring and storage capacitor wiring are made of a conductive material containing elements with a higher melting point than Cu. By applying such a structure, the migration of the layer containing Cu is prevented. In particular, the bottom gate The gate wiring in a thin-film transistor is subject to the effects of heat loads in post-processing and stresses in the laminated film. Therefore, by making the structure resistant to these influences, the reliability of the semiconductor device can be improved. It is possible to do so.

[0068] Next, an insulating layer 204 functioning as a gate insulating layer is formed on the gate wiring 203 to a thickness of 50 nm or less. The thickness of the insulating film is preferably 800 nm or less, more preferably 100 nm or more and 600 nm or less. In this embodiment, the insulating layer 204 is formed by laminating the insulating layer 204b on the insulating layer 204a. The edge layer 204a is a silicon nitride layer (SiN y (y>0) The insulating layer 204b is a silicon oxide layer (SiO x (x>0) on the insulating layer 204a These are laminated to form an insulating layer 204 having a thickness of 100 nm.

[0069] The insulating layer 204 also functions as a protective layer. The upper insulating layer is an insulating layer 201 and an insulating layer 204a, which are insulating films containing silicon nitride. The gate wiring 202 containing Cu is sandwiched or wrapped in the insulating layer. This can prevent the diffusion of Cu contained in the port wiring 202 .

[0070] Next, a semiconductor layer 205 is formed on the insulating layer 204. Conductive films are In-Ga-Zn-O, In-Sn-Zn-O, and In-Al-Zn-O. , Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In- Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-O series, Sn-O series, Zn-O In addition, the oxide semiconductor film is formed by emitting a rare gas (typically, argon) In the atmosphere, in the oxygen atmosphere, or in the mixed atmosphere of rare gas (typically argon) and oxygen, The insulating layer 11 can be formed by a sputtering method.

[0071] In addition, when using the sputtering method, the silicon oxide (SiO2) content is 2% by weight or more and 10% by weight or less. The oxide semiconductor film is deposited using a target containing SiO x (X>0 ) may be included.

[0072] Here, a target for forming an oxide semiconductor film containing In, Ga, and Zn (composition ratio: In2O3:Ga2O3:ZnO=1:1:1[mol%], In:Ga:Zn=1:1 :0.5[at.%]) was used, the distance between the substrate and the target was 100 mm, and the pressure was 0. Deposition was performed under an atmosphere of 6 Pa, direct current (DC) power supply of 0.5 kW, and oxygen (oxygen flow rate of 100%). In addition, when a pulsed direct current (DC) power supply is used, the powdery substances (particles) generated during film formation are This is preferable because it can reduce the amount of dust and dirt that accumulates on the surface of the substrate and also makes the film thickness distribution uniform. The oxide semiconductor film was formed using an In-Ga-Zn-O oxide semiconductor film formation target. Then, an In-Ga-Zn-O based film is formed by sputtering.

[0073] The filling rate of the oxide semiconductor film forming target is 90% or more and 100% or less, preferably 9 The filling rate is 5% or more and 99.9%. By using a target for oxide semiconductor film formation with a high filling rate, As a result, the formed oxide semiconductor film becomes a dense film.

[0074] Note that the thickness of the oxide semiconductor film is preferably from 5 nm to 30 nm. The appropriate thickness varies depending on the solid semiconductor material, and the thickness may be appropriately selected depending on the material.

[0075] In addition, it is preferable to form an oxide semiconductor film successively over the insulating layer 204. The chamber type sputtering equipment uses a silicon or silicon oxide (artificial quartz) target. and a target for forming an oxide semiconductor film. The film forming chamber has at least a cryopump as an exhaust means. Instead of the ion pump, a turbo molecular pump is used, and moisture is placed on the intake port of the turbo molecular pump. A cold trap may be provided to adsorb the above.

[0076] The deposition chamber evacuated using a cryopump contains hydrogen atoms, H2O, and other hydrogen atoms. Compounds containing oxygen and compounds containing carbon atoms are exhausted, so the oxide film formed in the film formation chamber is The concentration of impurities contained in the semiconductor film can be reduced.

[0077] The oxide semiconductor film may be formed while the substrate is heated. The temperature is set to 200°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. By forming the oxide semiconductor film, the concentration of impurities in the oxide semiconductor film can be reduced. do.

[0078] The sputtering method uses a high-frequency power supply as the sputtering power source, while the RF sputtering method uses a DC power supply. There are two types of sputtering: DC sputtering and pulsed DC sputtering, which uses a pulsed bias. The sputtering method is mainly used to deposit insulating films, while the DC sputtering method is mainly used to deposit metal conductive films. It is used when forming a film.

[0079] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The equipment can deposit layers of different materials in the same chamber, or multiple types of films in the same chamber. It is also possible to deposit a single film by simultaneously introducing a material of the same type and discharging it.

[0080] Also, a sputtering apparatus using a magnetron sputtering method equipped with a magnet mechanism inside the chamber and ECR sputtering using plasma generated by microwaves without glow discharge. There is a sputtering apparatus that uses this method.

[0081] In addition, in a film formation method using a sputtering method, a target material and a sputtering gas component are mixed during film formation. Reactive sputtering is a method of forming thin films of compounds by chemically reacting them with each other, and There is also a bias sputtering method in which a voltage is also applied to the substrate.

[0082] Before the oxide semiconductor film was formed by a sputtering method, argon gas was introduced to the plasma In order to remove the dust adhering to the surface of the insulating layer 204, a reverse sputtering process is performed to generate dust. In the reverse sputtering, a voltage is applied to the substrate using an RF power source in an argon atmosphere. This method generates plasma near the substrate by ionizing it, and modifies the surface. Alternatively, nitrogen, helium, oxygen, etc. may be used.

[0083] Next, a mask is applied to the oxide semiconductor film by photolithography, an ink-jet method, or the like. The oxide semiconductor film is selectively etched using the mask to form an island-shaped semiconductor layer 2 In this embodiment, a resist mask is formed by a third photolithography process. The oxide semiconductor film is selectively etched using a etchant to form an island-shaped semiconductor layer 205. (See FIG. 4(C)). Here, the end of the semiconductor layer 205 is etched to have a tapered shape. This prevents the wiring from being cut off due to the step shape. Acid or organic acids such as oxalic acid can be used as the etchant.

[0084] Next, the semiconductor layer 205 is dehydrated or dehydrogenated. The temperature of the heat treatment in step 1 is 400° C. or more and less than 750° C. For example, At 700°C or less, for 1 to 10 minutes, preferably 650°C, for 3 to 6 minutes This can be done with the following RTA (Rapid Thermal Anneal) processing: The RTA method allows dehydration or dehydrogenation in a short time, which reduces distortion of the glass substrate. It is also possible to process at temperatures above this point.

[0085] When using the RTA method, the heat treatment device is, for example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid Therm) RTA (Rapid Thermal Anneal) equipment such as The LRTA device can be used with halogen lamps, metal halide lamps, and Senon arc lamps, carbon arc lamps, high pressure sodium lamps, high pressure mercury lamps, etc. This is a device that heats the workpiece by radiating light (electromagnetic waves) emitted from the lamp. The TA device uses the heat radiation from the light emitted from the lamp and the gas This is a device that heats the object to be treated by heat conduction from the heated gas. The gas used is a rare gas such as argon or nitrogen, which does not react with the object to be treated by heat treatment. In addition, the LRTA and GRTA devices use not only lamps but also A device for heating an object to be treated by heat conduction or heat radiation from a heating element such as a resistance heating element. The device may include:

[0086] In addition, when the first heat treatment is performed using an electric furnace or the like, the heat treatment time is 425° C. or higher. The heat treatment time may be less than 1 hour, but if the temperature is less than 425℃, the heat treatment time should be longer than 1 hour. In the first heat treatment, the substrate is introduced into an electric furnace, which is one type of heat treatment device, and oxidized. The oxide semiconductor layer is then subjected to a heat treatment in a nitrogen atmosphere. From the heating temperature T at which hydration or dehydrogenation occurs, to a temperature that is sufficient to prevent water from re-entering the system, Using a furnace, slowly cool the material in a nitrogen atmosphere until the temperature drops by 100°C or more below the heating temperature T. In addition, the atmosphere is not limited to nitrogen, and it can be a rare gas atmosphere (helium, neon, argon, etc.). Dehydration or dehydrogenation can be performed in the oxide semiconductor without exposure to air. By preventing water or hydrogen from re-entering the layer, an oxide semiconductor layer containing a low concentration of hydrogen is obtained.

[0087] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain water, hydrogen, etc. Or the purity of rare gases such as helium, neon, and argon must be 6N (99.9999%) or higher. Preferably, the concentration of impurities is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, It is preferable to keep the concentration of the ion exchange resin at 0.1 ppm or less.

[0088] At this time, needle-like ions having a c-axis oriented in the direction perpendicular to the film surface are formed on the surface of the semiconductor layer 205. By using an oxide semiconductor layer having such a structure, The surface layer has a dense crystalline region composed of fine crystals of needle-shaped crystals. This prevents the deterioration of electrical characteristics due to re-intrusion of moisture from the semiconductor and N-type formation caused by desorption of oxygen. In addition, the surface layer of the oxide semiconductor layer is on the back channel side, and the prevention of N-type is due to the parasitic transistor. It is also effective in suppressing channel noise.

[0089] In addition, the temperature is lowered from the heating temperature T at which the oxide semiconductor layer is dehydrated or dehydrogenated. When dehydrating or dehydrogenating, water or hydrogen is added without exposing it to the air in the same furnace where dehydration or dehydrogenation was performed. It is important not to mix them again. Dehydration or dehydrogenation is performed to make I-type and high resistance. When a thin film transistor is manufactured using the oxide semiconductor layer, The threshold voltage can be set to positive, making the switching element have a so-called normally-off characteristic. This can be achieved by setting the gate voltage of the thin film transistor to a positive threshold voltage as close as possible to 0V. It is desirable for the display device to have a channel formed.

[0090] In addition, the gas atmosphere when lowering the temperature from the heating temperature T is the same as the gas atmosphere heated to the heating temperature T. For example, the same gas atmosphere as that used for dehydration or dehydrogenation may be used. The furnace is not exposed to the atmosphere, and the inside of the furnace is filled with high-purity oxygen gas or N2O gas, ultra-dry air, Cooling may be performed by filling the tank with water (dew point of -40°C or less, preferably -60°C or less).

[0091] As described above, the first heat treatment is performed to form the semiconductor layer 20 made of an oxide semiconductor film. 5 by reducing impurities (HO, H, OH, etc.) contained in the oxide semiconductor This allows the production of highly reliable thin film transistors with excellent electrical properties. A gistar can be formed.

[0092] In addition, the first heat treatment of the oxide semiconductor layer is performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer. In this case, the substrate is removed from the heating device after the first heat treatment. It is then taken out and subjected to a third photolithography step.

[0093] Next, although not shown in FIGS. 2 to 5, a gate wiring 203 and an electrode 20 (to be described later) are An opening (also called a contact hole) for connecting the electrode 7a or the electrode 207b is formed in the insulating layer 204. The insulating layer 204 is formed by photolithography, inkjet printing, or the like. A mask is formed by selectively etching the insulating layer 204 using the mask to form a contact. Here, a hole is formed in the resist formed by the fourth photolithography process. The insulating layer 204 is selectively etched using a mask to form contact holes.

[0094] The formation of the contact holes by the fourth photolithography process is performed after the insulating layer 204 is formed. Alternatively, the step may be performed after the formation of the silicon oxide film 204 and before the formation of the semiconductor layer 205.

[0095] Next, W, Ta, M are deposited on the semiconductor layer 205 by sputtering, vacuum deposition, or the like. Conductive films of O, Ti, Cr, etc., or alloys combining the above elements, etc. The thickness of the film is 100 nm or more and 500 nm or less, preferably 200 nm or more and 300 nm or less. The conductive film is not limited to a single layer containing the above-mentioned elements, and may be a laminate of two or more layers. The conductive film has a resistance to at least a degree sufficient to withstand the second heat treatment to be performed later. It is preferable that the composition has thermal properties.

[0096] The conductive film may be a transparent conductive oxide containing indium, tin or zinc. For example, indium oxide (In2O3) or an indium tin oxide alloy ( It is preferable to use In2O3-SnO2 (abbreviated as ITO). An insulating oxide such as silicon oxide may be added to the oxide. By using the same as above, the aperture ratio of the display device can be improved.

[0097] The conductive film in contact with the semiconductor layer 205 made of an oxide semiconductor film contains a metal having a high oxygen affinity. It is preferable to use materials.

[0098] Metals with high oxygen affinity include titanium (Ti), manganese (Mn), and magnesium (M g), zirconium (Zr), beryllium (Be), or thorium (Th) In this embodiment, a titanium film is used.

[0099] When an oxide semiconductor layer is formed in contact with a conductive film having high oxygen affinity, the carrier density near the interface The resistance of the oxide semiconductor layer is increased, a low-resistance region is formed, and the contact resistance between the oxide semiconductor layer and the conductive film is reduced. This is because the conductive film with high oxygen affinity extracts oxygen from the oxide semiconductor layer. At the interface between the oxide semiconductor layer and the conductive film, a layer containing excess metal in the oxide semiconductor layer (also called a composite layer) is formed. This is called the formation of a conductive film or an oxidized conductive film, or both. For example, in a structure in which an In-Ga-Zn-O oxide semiconductor layer is in contact with a titanium film, A layer containing an excess of indium and a titanium oxide film are formed near the interface between the oxide semiconductor layer and the titanium film. Alternatively, a layer may be generated near the interface between the oxide semiconductor layer and the titanium film. Either an indium-rich layer or a titanium oxide layer may be produced. The layer with excess indium, which is oxygen-depleted from the a-Zn-O oxide semiconductor layer, has low electrical conductivity. Since the contact resistance between the oxide semiconductor layer and the conductive film is high, the contact resistance between the oxide semiconductor layer and the conductive film can be reduced.

[0100] Note that a conductive titanium oxide film may be used as the conductive film in contact with the oxide semiconductor layer. In this case, in a structure in which an In-Ga-Zn-O-based oxide semiconductor layer is in contact with a titanium oxide film, In the case of the titanium oxide film, a layer containing excess indium is formed near the interface between the oxide semiconductor layer and the titanium oxide film. It may be generated.

[0101] The In-Ga-Zn-O oxide semiconductor layer is used as the active layer of a thin film transistor. In the thin film transistor used, a metal layer used as a source electrode or a drain electrode In the vicinity of the interface with the In-Ga-Zn-O-based oxide semiconductor layer, the concentration of indium is The layer higher than the region (In-rich layer) and the titanium oxide film (TiO X ) is formed This will be explained in detail in the fourteenth embodiment.

[0102] The conductive film can be formed by arc discharge ion plating or spraying. Also, silver, gold, copper, etc. may be used by using a screen printing method, an inkjet method, etc. Alternatively, the conductive nanopaste may be discharged and baked.

[0103] Next, a mask is formed on the conductive film by photolithography, inkjet printing, or the like. The conductive film is then etched using the mask to form an electrode 207 that functions as a source electrode. In this embodiment, the electrode 207b serving as a drain electrode can be formed. First, a 200 nm thick Ti film was formed as a conductive film by sputtering, and the fifth photolithography was performed. Using a resist mask formed in the lithography process, wet etching or dry etching is performed. The conductive film is selectively etched by an etching method to form electrodes 207a and 207b. do.

[0104] In the fifth photolithography step, only the conductive film in contact with the oxide semiconductor layer is Only the conductive film in contact with the oxide semiconductor layer is selectively removed. In order to achieve this, an alkaline etchant was used, which is ammonia hydrogen peroxide (weight ratio of composition: 31% by weight). When a mixture of hydrogen peroxide (28% by weight), ammonia (5:2:2 by weight), etc. is used, a metal conductive film is selectively removed, leaving an oxide semiconductor layer made of an In-Ga-Zn-O-based oxide semiconductor. It can be done.

[0105] In addition, depending on the etching conditions, the oxide semiconductor layer In this case, the exposed areas of the source and drain electrode layers may be etched. The thickness of the oxide semiconductor layer in the sandwiched region (region sandwiched between 207a and 207b) is The thickness of the oxide semiconductor layer in a region where the source electrode layer overlaps with the wiring 203 or the thickness of the drain electrode layer The thickness of the oxide semiconductor layer in the overlapping region is thinner than that in the oxide semiconductor layer in the overlapping region (see FIG. 4D).

[0106] Next, the insulating layer 208 is formed on the insulating layer 204 and the semiconductor layer 205. The insulating layer 208 is Molecular weight, hydrogen ions, and OH - It does not contain impurities such as these, and prevents them from entering from the outside. The insulating layer 208 is formed using an inorganic insulating film. Therefore, the insulating film is formed using an inorganic insulating film that suppresses migration of the Cu-containing layer. In this embodiment, the insulating layer 208 is formed by stacking an insulating layer 208b over an insulating layer 208a.

[0107] The insulating layer 208a in contact with the semiconductor layer 205 is formed using an oxide insulating film. The oxide insulating film is formed to a thickness of at least 1 nm by a sputtering method or the like. The film can be formed by using a method that does not mix impurities such as silicon oxide. A silicon nitride oxide film, an aluminum oxide film, an aluminum oxynitride film, or the like is used. It is formed in a layer or laminate.

[0108] The substrate temperature during the formation of the insulating layer 208a may be set to a temperature between room temperature and 300° C. in this embodiment. The temperature is set to 100°C in the sputtering method for forming a silicon oxide film. In an atmosphere of rare gas (typically argon), oxygen, or a mixture of rare gas (typically argon) and oxygen, The oxide insulating film formed by the sputtering method can be formed in a suitable atmosphere. It is dense and can be used as a protective film to suppress the diffusion of impurities into adjacent layers, even in a single layer. In addition, phosphorus (P) or boron (B) doped targets can be used to Phosphorus (P) or boron (B) can also be added to the oxide insulating film.

[0109] In addition, a silicon oxide target or a silicon target can be used as the target. In particular, a silicon target is preferred. Using a silicon target, the reaction is carried out under an oxygen and rare gas atmosphere. The silicon oxide film formed by the sputtering method has dangling bonds between silicon and oxygen atoms (datum). It contains a lot of mercury-containing bonds.

[0110] Since the insulating layer 208a contains many dangling bonds, the impurities contained in the semiconductor layer 205 The diffusion of the oxygen atoms into the insulating layer 208a is facilitated through the interface between the layer 205 and the insulating layer 208a. Specifically, hydrogen atoms contained in the semiconductor layer 205, compounds containing hydrogen atoms such as H2O, Compounds containing carbon atoms are easily diffused and moved to the insulating layer 208a, and are fixed to the insulating layer 208a. It will be turned into.

[0111] In this embodiment, the purity of the sputtering gas is 6N, and the columnar polycrystalline B-doped silicon target is The distance between the substrate and the target (TS distance) was 89 mm, pressure 0.4 Pa, direct current (DC) power supply 6 kW, oxygen (oxygen flow rate 100%) The insulating layer 208a is formed by pulse DC sputtering in a 300 nm atmosphere. do.

[0112] At this stage, the region where the semiconductor layer 205 and the insulating layer 208a are in contact with each other is formed. 03 and is sandwiched between the insulating layer 204 and the insulating layer 208a. This serves as a channel formation region. The insulating layer 208a also functions as a channel protection layer.

[0113] The insulating layer 208b formed on the insulating layer 208a is an insulating film containing nitrogen. 08b is at least 1 nm thick, and the insulating film is coated with water or hydrogen by a method such as sputtering. The film is formed by using a method that does not mix impurities such as silicon nitride and oxynitride. A silicon film or aluminum nitride film is used. In this embodiment, RF sputtering is used. Then, the insulating layer 208b of the silicon nitride film is formed.

[0114] In this embodiment, a silicon nitride film having a thickness of 400 nm is formed as the insulating layer 208b.

[0115] Next, a second heat treatment (preferably at 200° C. or higher and 400° C. or lower, for example at 250° C. or higher and 3 50℃ or less) in an inert gas atmosphere or nitrogen gas atmosphere. The treatment is preferably carried out at a lower temperature than the first heat treatment.

[0116] For example, the second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. When the semiconductor layer 205 is heated, a part of the semiconductor layer 205 is in contact with the insulating layer 208a. Another part of 205 is heated while being in contact with electrodes 207a and 207b.

[0117] When the second heat treatment is performed while the semiconductor layer 205 is in contact with the insulating layer 208a, the insulating layer 2 As a result, the region where the insulating layer 208a contacts the semiconductor layer 205 becomes oxygen-excessive. From the region where a contacts the semiconductor layer 205, the region becomes I-type (has high resistance) in the depth direction of the semiconductor layer 205.

[0118] Specifically, from the interface between the semiconductor layer 205 and the insulating layer 208a to the insulating layer 204, A semiconductor layer 205 having an I-type (high resistance) region is formed.

[0119] The thin film transistor manufactured in this embodiment has an I-type (high resistance) channel formation region. Since the oxide semiconductor layer is formed, the threshold voltage is a positive value, and the enhancement effect is Indicates the behavior of the type.

[0120] The electrodes 207a and 207b are made of a metal conductive film having a high affinity for oxygen, and the semiconductor layer When the second heat treatment is performed on the region in contact with 205, oxygen is easily transferred to the metal conductive film side. Therefore, the oxide semiconductor layer in the region in contact with the metal conductive film, which has a strong affinity for oxygen, becomes N-type. An example of a metal that has a strong affinity with elements is Ti.

[0121] By performing the second heat treatment, the insulator layer 205 made of an oxide semiconductor is removed. Impurities (such as HO, H, and OH) can be reduced, and the oxide semiconductor film can be highly purified. This makes it possible to form a thin film transistor having good electrical characteristics and high reliability.

[0122] The timing of the second heat treatment is not limited to immediately after the formation of the insulating layer 208. There are no particular limitations as long as it is a process subsequent to the formation of the layer 208.

[0123] Next, an opening (contact hole) for connecting the electrode 207a and the source wiring 209 is formed. A thin film (also referred to as a thin-film transistor) 216 is formed on the insulating layer 208. A mask is formed by an ink-jet method or the like, and the insulating layer 208 is selectively In this embodiment, the sixth photolithography is performed to form a contact hole. The insulating layer 208 is selectively etched using the resist mask formed in the etching process. Form a contact hole.

[0124] Next, in order to form the source wiring 209, a sputtering method, a vacuum deposition method, or the like is used. Conductive films with higher melting points than Cu, such as W, Ta, Mo, Ti, and Cr, or the above elements The combined alloy is made into a conductive film having a thickness of 5 nm to 200 nm, preferably 10 nm or more. The thickness is 100 nm or less. In addition, tantalum nitride and nitride are deposited by reactive sputtering. Titanium oxide may also be formed.

[0125] Next, a conductive film containing Cu is deposited on the substrate by sputtering, vacuum deposition, or plating. The thickness of the insulating film is 00 nm or more and 500 nm or less, preferably 200 nm or more and 300 nm or less. forming a mask on the conductive film by a photolithography method, an ink-jet method, or the like; The mask is used to etch the conductive film containing Cu and the conductive film for forming the source wiring 209. By performing the above-mentioned process, the source wiring 209 and the source wiring 210 containing Cu can be formed.

[0126] In this embodiment, the conductive film for forming the source wiring 209 is made of titanium nitride having a thickness of 50 nm. A conductive film for forming the source wiring 210 is made of Cu having a thickness of 250 nm. The conductive film is selectively etched using the resist mask formed in the photolithography process. Then, a source wiring 209 and a source wiring 210 are formed (see FIG. 5(A)).

[0127] The source wiring 209 also functions as a barrier layer to prevent Cu diffusion. By laminating a layer containing Cu and a layer containing an element with a higher melting point than Cu, the layer containing Cu This makes it possible to suppress migration of the metal oxide and improve the reliability of the semiconductor device. A layer containing an element having a melting point higher than that of Cu is also provided on the source wiring 210, and the layer containing Cu is The semiconductor device may be sandwiched between layers containing an element having a melting point higher than that of u. Depending on the conditions of use, the source wiring may be a single layer containing Cu. The layer can be formed using the same structure and method as the gate wiring 202 .

[0128] Next, the insulating layer 211 is formed to a thickness of 50 nm to 300 nm, preferably 100 nm to 200 nm. The insulating layer 211 is formed to a thickness of 100 nm or less. The insulating layer 211 is formed in the same manner as the insulating layer 201. The insulating layer 211 prevents external contaminants from affecting the thin film transistor. In the present embodiment, the insulating layer 211 is a 1 mm thick film. A silicon nitride film having a thickness of 0 nm is formed. The insulating layer 211 also functions as a protective layer. The insulating layers located above and below the source wiring 210 are made of silicon nitride. The source wiring 210 containing Cu is sandwiched or wrapped between the insulating layers. This makes it possible to prevent the diffusion of Cu contained in the wire 210 (see FIG. 5(B)).

[0129] Next, a contact for connecting the electrode 207b to the electrode 212 that functions as a pixel electrode is Holes are formed in the insulating layer 211 and the insulating layer 208. A mask is formed by a dye method, an ink jet method, or the like, and the insulating layer 211 and The insulating layer 208 is selectively etched to form contact holes. The insulating layer 211 and the The insulating layer 208 is selectively etched to form a contact hole (opening 217). .

[0130] Next, a transparent conductive film is formed to a thickness of 30 nm by using a sputtering method, a vacuum deposition method, or the like. The conductive film is formed to a thickness of 50 nm or more and 200 nm or less, preferably 50 nm or more and 100 nm or less. A mask is formed on the substrate by photolithography or inkjet printing, and the mask is The conductive film can be etched using the above-mentioned method to form an electrode 212 that functions as a pixel electrode. Cut.

[0131] Examples of the light-transmitting conductive film include indium oxide containing tungsten oxide, tungsten oxide, and the like. Indium zinc oxide containing tin, indium oxide containing titanium oxide, titanium oxide Indium tin oxide (ITO) and indium zinc oxide Conductive materials with light transmission such as lead oxide and indium tin oxide with added silicon oxide are used. It can be used.

[0132] In addition, the light-transmitting conductive film is formed by using a conductive material containing a conductive polymer (also called a conductive polymer). The pixel electrode formed by using the conductive composition can be formed by a sheet. Resistance is 10000Ω / □ or less, and light transmittance at a wavelength of 550nm is 70% or more. It is also preferable that the resistivity of the conductive polymer contained in the conductive composition is 0.1 Ω cm or less. It is preferable that:

[0133] In this embodiment, an ITO film having a thickness of 80 nm is formed as a conductive film having a light-transmitting property. A conductive film having a light-transmitting property is selected using a resist mask formed in the photolithography process. Selective etching is performed to form an electrode 212 that functions as a pixel electrode (see FIG. 5(C)). ).

[0134] In this embodiment, when the insulating layer 204 and the semiconductor layer 205 are not formed in succession, Layer 204 is then heated under an inert gas atmosphere (nitrogen, helium, neon, argon, etc.) It is preferable to perform a heat treatment (at 400° C. or higher and below the distortion point of the substrate). By this, impurities such as hydrogen and water contained in the insulating layer 204 are removed before the oxide semiconductor film is formed. can be removed.

[0135] The silicon oxide layer, the silicon nitride layer, the silicon oxynitride layer, or the silicon nitride oxide layer may be formed by sputtering. In addition to the above method, the film may be formed by plasma CVD. For example, the film may be formed using SiH4, The silicon oxynitride layer may be formed by plasma CVD using oxygen and nitrogen. The thickness of the film 204 is 100 nm or more and 500 nm or less. In the case of a laminated film, for example, a first gate insulating layer having a thickness of 5 nm or more and a thickness of 200 nm or less on the first gate insulating layer; A second gate insulating layer of 300 nm or less is laminated. Note that this is done using a plasma CVD method or the like. If the formed film contains impurities such as hydrogen and water, the above heat treatment is performed to remove the impurities. It is preferable that an oxide semiconductor film be formed after the above-mentioned process.

[0136] In this embodiment, the gate insulating layer is selectively formed by the fourth photolithography process. A contact hole is formed by etching to reach a gate wiring layer (not shown). This method is not limited to the above. For example, after the insulating layer 204 is formed, a resist is formed on the insulating layer 204. A contact mask may be formed to form a contact hole reaching the gate wiring layer.

[0137] In this embodiment, a photolithography process using a multi-tone mask is applied. Regarding the photolithography process using a multi-tone mask, FIG. 6 and FIG. I will use this to explain.

[0138] A multi-tone mask has three exposure levels for the exposed, intermediate and unexposed parts. This is an exposure mask that allows multiple exposures, and the transmitted light has multiple intensities. A resist mask having multiple (typically two) thickness regions formed by the light and development process Therefore, by using a multi-tone mask, the number of exposure masks can be reduced. It is possible to reduce the number.

[0139] A typical example of a multi-tone mask is a gray-tone mask 801a as shown in FIG. There is a half-tone mask 801b as shown in FIG. 6(C).

[0140] As shown in FIG. 6A, the gray-tone mask 801a is made of a light-transmitting substrate 802 and a The light shielding portion 803 is formed on the substrate 801 and a diffraction grating 804. On the other hand, the diffraction grating 804 has a light transmittance of 0%. By setting the spacing between the transparent parts to be equal to or less than the resolution limit of the light used for exposure, the light transmittance The diffraction grating 804 can be formed by periodically arranging slits, dots, meshes, etc. Either periodic or non-periodic slits, dots, or meshes can be used.

[0141] The light-transmitting substrate 802 may be a light-transmitting substrate made of quartz or the like. The diffraction grating 804 is formed using a light-shielding material that absorbs light, such as chromium or chromium oxide. This can be done.

[0142] When the gray-tone mask 801a is irradiated with exposure light, as shown in FIG. In 803, the light transmittance 805 is 0%, and the light shielding portion 803 and the diffraction grating 804 are In the area where the diffraction grating 804 is not provided, the light transmittance 805 is 100%. In this case, the light transmittance can be adjusted in the range of 10 to 70%. The light transmittance can be adjusted by adjusting the spacing and pitch of the slits, dots, or mesh of the diffraction grating. This is possible by adjusting the switch.

[0143] As shown in FIG. 6C, the halftone mask 801b is made of a light-transmitting substrate 802 and a The semi-transmitting portion 807 is made of Mo. SiN, MoSi, MoSiO, MoSiON, CrSi, etc. can be used. The light portion 806 can be formed using a light-shielding material that absorbs light, such as chromium or chromium oxide. Cut.

[0144] When the halftone mask 801b is irradiated with exposure light, as shown in FIG. In 806, the light transmittance 808 is 0%, and the light shielding portion 806 and the semi-transmitting portion 807 are both In the region where the semi-transparent portion 807 is not provided, the light transmittance 808 is 100%. In the semi-transparent portion 807, the light transmittance can be adjusted in the range of 10 to 70%. The light transmittance can be adjusted by adjusting the material of the semi-transmitting portion 807 .

[0145] Next, the third photolithography step and the fifth photolithography step will be described with reference to FIG. Here is an example of replacing the lithography process with a single multi-tone mask photolithography process. He explains.

[0146] In the third photolithography process of the present embodiment, a semiconductor In the above embodiment, the layer 205 is formed and both layers are made into island-shaped semiconductor layers. However, in this embodiment, the layer 205 is not made into island-shaped semiconductor layers. Then, an electrode layer 207 is formed on the semiconductor layer 205. Then, a multi-layer structure is formed on the electrode layer 207. A resist mask 231 having a concave or convex portion is formed using a lithographic mask (FIG. 7(A)). reference).

[0147] The resist mask 231 is a resist having a plurality of regions (two regions in this example) with different thicknesses. In the resist mask 231, the thick areas are made of resist. The thin areas are called convex portions of the resist mask 231, and the thin areas are called concave portions of the resist mask 231. .

[0148] In the resist mask 231, an electrode 207a which functions as a source electrode to be formed later is A protrusion is formed in the portion where the electrode 207b functioning as the drain electrode is to be formed. A recess is formed in the portion sandwiched between the portion where the pole 207a and the electrode 207b are formed. .

[0149] Next, the electrode layer 207 and the semiconductor layer 205 are selectively removed using a resist mask 231. At the same time, etching is performed to form island-shaped semiconductor layers 205 (see FIG. 7(B)).

[0150] Next, the resist mask 231 is retracted (reduced) to form a resist mask 231a, A resist mask 231b is formed. In order to make the resist mask recede (shrink), oxygen plasmon By making the resist mask retreat (shrink), The electrode layer 207 in the portion sandwiched between the resist mask 231a and the resist mask 231b is It is exposed (see Figure 7(C)).

[0151] Next, the electrode layer 2 in the portion sandwiched between the resist mask 231a and the resist mask 231b is 07 is selectively etched using the resist mask 231a and the resist mask 231b. By this, the electrodes 207a and 207b are formed. There are cases where only a portion of 205 is etched, resulting in a semiconductor layer having a groove (concave portion). In addition, the ends of the semiconductor layer 205 protrude outward beyond the ends of the electrodes 207a and 207b. (See FIG. 7D.) Next, the resist mask 231a and the resist mask Then, the ridge 231b is removed (see FIG. 7(E)).

[0152] By using a multi-tone mask, multiple photolithography steps can be performed in a single photolithography step. Since it is possible to replace the process with the conventional process, the productivity of the semiconductor device can be improved. .

[0153] In this embodiment, the electrode 207a and the solder are formed in the sixth photolithography process. When forming a contact hole for connecting the source wiring 209, the thin film transistor Openings are formed in the insulating layers 204b, 208a, and 208b so as to surround the insulating layer. The thin film transistor 252 is structured such that the layer 211 contacts the insulating layer 204a through the opening. A cross-sectional view of the thin film transistor 252 is shown in FIG.

[0154] The thin film transistor 252 illustrated in FIG. 38 is a channel transistor, similar to the thin film transistor 250. The transistor is a thin film transistor of a reflective etch type. A gate wiring 202 provided on the layer 201 and a gate wiring 203 provided on the gate wiring 202 203, an insulating layer 204a provided on the gate wiring 203, and a The insulating layer 204b is formed on the insulating layer 204b, the semiconductor layer 205 is formed on the insulating layer 204b, and the semiconductor layer 2 A pair of electrodes 207a and 207b are provided on the substrate 205, and the electrodes 207a and 207 b, an insulating layer 208a provided on the semiconductor layer 205, and a The insulating layer 208a is electrically connected to the insulating layer 208b through an opening provided in the insulating layer 208a and the insulating layer 208b. A source wiring 209 in contact with the electrode 207a and a source wiring 209 provided on the source wiring 2 10, an insulating layer 211 provided on the source wiring 210, and the insulating layer 211 and the insulating layer 208 a and an electrode 212 in contact with the electrode 207b through an opening provided in the insulating layer 208b; Although the gate wiring 202 is not shown in FIG. The gate wiring 202 of the thin film transistor 250 shown in FIG. It is set up as follows.

[0155] Here, the insulating layer 204b, the insulating layer 208a, and the insulating layer 208b are formed by a sixth photolithography. In the ?lm, an opening is selectively formed so that the insulating layer 204a is exposed, and the insulating layer 21 1 covers the upper surface and side surfaces of the insulating layer 208b, the insulating layer 208a, and the side surfaces of the insulating layer 204b. , and comes into contact with the insulating layer 204a through the opening.

[0156] Here, the insulating layer 211 and the insulating layer 204a are made of an insulating film containing nitrogen, and are resistant to moisture and hydrogen ions. Nya, OH ― It does not contain impurities such as chlorine and is an inorganic material that blocks the intrusion of these substances from the outside. It is an insulating film.

[0157] Therefore, by using the structure shown in FIG. 38, the insulating layer 211 made of an insulating film containing nitrogen and the insulating Layer 204a can encapsulate thin film transistor 252, so that insulating layer 21 In the manufacturing process after the formation of the insulating film 1, the intrusion of moisture from the outside can be prevented. Even after a display device, such as a liquid crystal display device, is completed, it is difficult to protect the device from water for a long period of time. This can prevent the intrusion of foreign matter and improve the long-term reliability of the device.

[0158] In this embodiment, a structure in which one thin film transistor is surrounded by an insulating film containing nitrogen is shown. However, there is no particular limitation, and a configuration in which a plurality of thin film transistors are surrounded by an insulating film containing nitrogen may also be used. In addition, a plurality of thin film transistors in a pixel portion may be surrounded by an insulating film containing nitrogen. The insulating layer 211 is formed so as to surround at least the periphery of the pixel portion of the active matrix substrate. It is only necessary to provide a region in contact with the edge layer 204a.

[0159] In addition, a thin film transistor having a light-transmitting property can be provided. The display device according to the second embodiment further includes a thin film transistor provided in a pixel portion of the display device. The semiconductor layer 205 and the conductive film having light transmitting properties are connected to the gate wiring 203, the electrode 207a, and the A case where the electrode 207b is applied will be described.

[0160] When applied to a thin film transistor included in the pixel configuration shown in FIG. The insulating layer 201 is formed on the insulating layer 201, and the gate wiring 202 is formed on the insulating layer 201. A light-transmitting gate wiring 203 is provided on the gate electrode 202. An insulating layer 204 is provided on the insulating layer 204, a semiconductor layer 205 is provided on the semiconductor layer 205, A pair of light-transmitting electrodes 207a and 207b are provided. 207b, an insulating layer 208 provided on the semiconductor layer 205, and a A source wiring 209 is in contact with the electrode 207a through the opening, and a A source wiring 210 is provided, an insulating layer 211 is provided on the source wiring 210, and an insulating layer 2 11 and an electrode 212 that contacts the electrode 207b through an opening provided in the insulating layer 208; It is possible to provide a light-transmitting thin film transistor having the above structure.

[0161] In addition, a thin film transistor having a bottom gate structure and having a channel protection layer as shown in FIG. Specifically, an insulating layer 201 is provided on a substrate 200, and a thin film is provided on the insulating layer 201. A gate wiring 202 is provided on the gate electrode 201, and a light-transmitting gate wiring 203 is provided on the gate wiring 202. A wiring 203 having a light-transmitting property, an insulating layer 204 provided on the gate wiring 203, and an insulating layer 2 A semiconductor layer 205 is provided on the semiconductor layer 204, and a channel protection layer 2 is provided on the semiconductor layer 205. 25, and a pair of electrodes 207a and an electrode 207b having light transmitting properties provided on the channel protection layer 225. The electrode 207b and an insulating layer provided on the electrode 207a, the electrode 207b, and the semiconductor layer 205. 208, and the source wiring 2 contacting the electrode 207a through an opening provided in the insulating layer 208. 09, a source wiring 210 provided on the source wiring 209, and The insulating layer 211 is connected to the insulating layer 208 through an opening provided in the insulating layer 211 and the insulating layer 208. and an electrode 212 in contact with the electrode 207b. do.

[0162] Many of the oxide semiconductors which can be used for the oxide semiconductor layer 205 described in Embodiment 2 are visible It transmits light. In addition, a conductive material having light transmission properties, such as an insulator containing tungsten oxide, Indium oxide, indium zinc oxide with tungsten oxide, indium zinc oxide with titanium oxide Indium tin oxide, titanium oxide, indium tin oxide (hereinafter referred to as ITO ), indium zinc oxide, indium tin oxide doped with silicon oxide, In- Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Z nO system, Sn-Al-Zn-O system, Sn-Zn-O system, Al-Zn-O system, In-O system , Sn-O-based, Zn-O-based oxide semiconductors, etc. are formed into films using a sputtering method, etc. This can be applied to the gate wiring 203, the electrode 207a, and the electrode 207b.

[0163] The light-transmitting oxide semiconductor layer 205 and the light-transmitting conductive film are formed on the gate wiring 203. Since the thin film transistors used for the electrodes 207a and 207b have a light-transmitting property, Therefore, the aperture ratio of the pixel portion is not impaired.

[0164] Note that the light-transmitting conductive oxide serves as an n+ layer in a region in contact with the oxide semiconductor layer. This allows the creation of thin-film transistors with low contact resistance and low parasitic resistance. We can provide it.

[0165] The above process suppresses the increase in wiring resistance and allows the production of semiconductors, such as display devices, with high display quality. The present invention also provides a device comprising insulating layers disposed above and below the conductive layer including Cu. The insulating layer contains silicon nitride, and the insulating layer sandwiches or encases a conductive layer containing Cu. This prevents the diffusion of Cu contained in the conductive layer, thereby providing a highly reliable semiconductor device. This can be done.

[0166] Further, by performing heat treatment for dehydration or dehydrogenation, the oxide semiconductor layer It is possible to reduce impurities (H2O, H, OH, etc.) contained in the oxide semiconductor layer and to highly purify the oxide semiconductor layer. As described above, by suppressing the concentration of impurities in the oxide semiconductor layer, the electrical characteristics can be improved. Thus, a thin film transistor having good properties and high reliability can be formed.

[0167] The oxide semiconductor layer in which the impurity concentration is suppressed, which is manufactured by the method exemplified in this embodiment, By applying this technique, it is possible to provide highly reliable semiconductor devices. In addition, a thin film transistor using an oxide semiconductor having a high operating speed can be provided. A thin-film transistor using an oxide semiconductor is relatively simple to manufacture and has sufficient reliability. We can provide you with a gyroscope.

[0168] In addition, the present embodiment allows the threshold voltage to be controlled, the operating speed to be high, and the manufacturing process to be relatively simple. A method for manufacturing a thin film transistor using an oxide semiconductor, which is simple and has sufficient reliability can be provided.

[0169] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0170] (Embodiment 3) In this embodiment, the display device 30 shown in FIG. 1 in the first embodiment is gate-driven. 9 shows an example of the configuration of a thin film transistor used in the source driving circuit 91 or the source driving circuit 92. .

[0171] The driver circuit for driving the pixel section is composed of an inverter circuit, a capacitor, a resistor, etc. In this embodiment, two thin film transistors are used in the driving circuit. The configuration of an inverter circuit consisting of two n-channel TFTs is explained. When combining them to form an inverter circuit, they are formed with enhancement type TFTs. In the case of EEMOS circuit, the enhancement type transistor and the depletion type transistor are In some cases, a transistor is formed by combining it with an EDMOS transistor (hereafter referred to as an EDMOS circuit). When the threshold voltage of the n-channel TFT is positive, the When the threshold voltage of the n-channel TFT is negative, it is called a depletion-type transistor. This definition is used throughout the specification.

[0172] The cross-sectional structure of the inverter circuit of the driver circuit is shown in FIG. A plan view of the circuit is shown in FIG. 8(C). In FIG. 8(C), a cross section taken along the dashed line Z1-Z2 is shown. 8(A). Note that the first thin film transistor 430a and the second thin film transistor The thin film transistor 430b is an inverted staggered thin film transistor with a bottom gate structure.

[0173] The first thin film transistor 430a shown in FIG. 8A has an insulating layer 410 formed on the surface. A first gate wiring 401a is provided on a substrate 400, and an insulating film is provided on the first gate wiring 401a. An insulating layer 411 and an insulating layer 412 are provided, and a first semiconductor layer 403a is provided on the insulating layer 412. An electrode 405a and an electrode 405b are provided on the first semiconductor layer 403a. Similarly, the second thin film transistor 430b is also formed on the substrate 40 having the insulating layer 410 formed on the surface thereof. A second gate wiring 401b is provided on the first gate electrode 400, and an insulating layer 41 is provided on the second gate wiring 401b. a second semiconductor layer 403b is provided on the insulating layer 412; An electrode 405b and an electrode 405c are provided on the second semiconductor layer 403b. The electrode 405c is formed through a contact hole 404 formed in the insulating layer 411 and the insulating layer 412. The electrode 405a, the electrode 405b, and the second gate wiring 401b are directly connected to each other through the electrode 405a. An insulating layer 413, an insulating layer 414, and an insulating layer 415 are formed on the electrode 405c. The electrodes 405a, 405b, and 405c are stretched as shown in FIG. The insulating film also functions as a wiring that electrically connects the thin film transistors in the driver circuit.

[0174] Here, the first gate wiring 401a and the second gate wiring 401b are the same as those in the first embodiment. The gate wiring 203 is formed by using the same material and the same method as the gate wiring 203 shown in the second embodiment. In addition, the first semiconductor layer 403a and the second semiconductor layer 403b may be formed in the same manner as in the embodiment. The semiconductor layer 205 shown in the first or second embodiment is formed using the same material and the same method. The electrodes 405a, 405b, and 405c can be formed as described in the first embodiment. Alternatively, the same material as the pair of electrodes 207a and 207b shown in the second embodiment may be used. The insulating layers 410 to 415 can be formed by using a method according to the embodiment. The insulating layer 201, the insulating layer 204, the insulating layer 208 and the insulating layer 209 shown in the first embodiment or the second embodiment are It can be formed using the same materials and methods as those for layer 211.

[0175] The contact hole 404 is formed by the fourth photolithography process shown in the second embodiment. In the process, a mask is formed on the insulating layer 412, and the insulating layer 412 and the insulating layer 4 11 is selectively etched. By directly connecting the electrode 405c and the second gate wiring 401b, good contact is achieved. In addition, the contact between the electrode 405c and the second When the gate wiring 401b is connected via another conductive film, for example, a conductive film having light transmitting properties Compared with the conventional method, the number of contact holes can be reduced, which makes it possible to reduce the number of thin-film transistors. This reduces the area occupied by the thin film transistors and shortens the distance between the thin film transistors in the driver circuit. can.

[0176] As described above, the distance between thin film transistors in the drive circuit can be shortened, and the wiring resistance can be reduced. Since the amount of the ZnO can be sufficiently reduced, it is possible to use the ZnO as wiring for electrically connecting each thin film transistor. It is not necessary to use a conductive layer containing Cu. This allows the thin-film transistors in the driver circuit to be Since a sufficient distance can be provided between the thin film transistor and the wiring made of a conductive layer containing Cu, This prevents Cu from diffusing into the oxide semiconductor layer of the transistor. Power lines that supply power to transistors and common wiring that have relatively long wiring distances Since the wire is relatively susceptible to the influence of wiring resistance, use wiring made of a conductive layer containing Cu. It is preferable.

[0177] As described in the first embodiment, the gate driving circuit 91 is connected to the gate wirings (20_1 to 20_1). _n (where n is a natural number)), and the source driver circuit 92 is connected to the source wirings (60_1 to 60_m( where m is a natural number) and are connected to gate wiring (20_1 to 20_n (where n is a natural number). The source wiring (60_1 to 60_m (where m is a natural number)) is a conductive layer containing Cu. Therefore, even in the display area where the wiring is long, the wiring resistance is sufficiently low. It can be reduced.

[0178] The electrode 405a is a power supply line of a ground potential (ground power supply line). The electrode 405c may be a power supply line (negative power supply line) to which a voltage VDL of It is electrically connected to the power supply line (positive power supply line) to which VDD is applied.

[0179] The equivalent circuit of the EEMOS circuit is shown in FIG. 8(B). The circuit connection corresponds to the equivalent circuit shown in FIG. 8B. The second thin film transistor 430b is an enhancement type n-channel transistor. This is an example.

[0180] Here, by providing gate electrodes above and below the oxide semiconductor layer to control the threshold voltage, The first thin film transistor 430a and the second thin film transistor 430b are enhancement Alternatively, a n-channel transistor of a GaN type may be used.

[0181] In addition to the EEMOS circuit, the first thin film transistor 430a is also an enhancement The second thin film transistor 430b is a depletion type n-channel transistor. By using an n-channel transistor, an EDMOS circuit can be created. In that case, instead of connecting the electrode 405c to the second gate wiring 401b, the electrode 405b and the second gate wiring 401b are connected.

[0182] Enhancement type n-channel transistor and depletion type n-channel transistor are placed on the same substrate. The method for fabricating the first and second channel transistors is, for example, The conductor layer 403b is formed using a material different from that of the oxide semiconductor layer 403a and a film forming condition different from that of the oxide semiconductor layer 403b. A gate electrode for threshold control is provided on the upper side of the layer to control the threshold. Apply a voltage to the gate electrode for threshold control so that the other TFT is on. The EDMOS circuit may be configured so that the transistor is normally off.

[0183] Note that the structure shown in this embodiment mode may be used in appropriate combination with structures shown in other embodiment modes. It is possible to do so.

[0184] (Embodiment 4) In this embodiment, a protection circuit using a semiconductor element in which an oxide semiconductor film is applied to a semiconductor layer is 9 and 10 will be used to explain this. The configuration of the connection portion that connects the wires together will be described with reference to FIG.

[0185] An example of a circuit that can be used as the protection circuit 97 is shown in FIG. The nonlinear elements 170a and 170b are made up of die It is composed of a two-terminal element such as an electrode or a three-terminal element such as a transistor. For example, It can be formed in the same process as the transistor in the pixel portion. For example, By connecting the drain terminal to the MOSFET, it can have characteristics similar to a diode.

[0186] The first terminal (gate) and the third terminal (drain) of the nonlinear element 170a are connected to the common wiring 45. The second terminal (source) is connected to the source wiring 60_1. The first terminal (gate) and the third terminal (drain) of 70b are connected to the source wiring 60_1, The second terminal (source) is connected to the common wiring 45. That is, the protection circuit shown in FIG. The circuit consists of two transistors, each with its rectifying direction opposite to each other, connected to a common wire 4. 5 and the source wiring 60_1. In other words, the common wiring 45 and the source wiring Between the lines 60_1, a transistor whose rectification direction is from the common wiring 45 to the source wiring 60_1 is provided. A transistor having a rectification direction from the source wiring 60_1 toward the common wiring 45 is connected to the This is the configuration.

[0187] When the source line 60_1 is positively or negatively charged due to static electricity or the like, the protection circuit A current flows in a direction that cancels the charge. For example, when the source wiring 60_1 is positively charged, Then, a current flows in a direction that dissipates the positive charge to the common wiring 45. Electrostatic breakdown or threshold voltage shift of the pixel transistor connected to the source wiring 60_1 In addition, the source wiring 60_1 and the charged source wiring 60_2 are prevented from crossing each other through an insulating layer. This can prevent dielectric breakdown of the insulating layer between the wiring and other wirings.

[0188] The protection circuit is not limited to the above configuration. For example, the rectification direction may be from the common wiring 45 to the source wiring 46. A plurality of transistors each having a rectification direction common to the source wiring 60_1 and a rectification direction common to the source wiring 60_1. A configuration in which a plurality of transistors are connected to the common wiring 45 may be used. The source wiring 60_1 is connected with a plurality of nonlinear elements to prevent a surge voltage from being applied to the source wiring 60_1. Not only when a voltage is applied, but also when the common wiring 45 is charged with static electricity or the like, This can prevent the electric charge from flowing directly into the source wiring 60_1. In addition, the protection circuit can be configured using an odd number of nonlinear elements.

[0189] In FIG. 9A, the protective circuit is provided on the source wiring 60_1 and the common wiring 45. The same configuration can be applied to the protection circuits of other parts. The semiconductor element according to the embodiment can be applied to the nonlinear element 170a and the nonlinear element 170b. Cut.

[0190] Next, an example of manufacturing a protection circuit over a substrate using a semiconductor element of one embodiment of the present invention is shown in FIG. 9B is a plan view of the wiring and the connection between the wiring. FIG. 10 shows an example of a cross section of the Q1-Q2 cut line, the Q3-Q4 cut line, and the Q 5-Q6 is a cross-sectional view corresponding to the cutting line.

[0191] In the configuration shown in FIG. 9B, the common line 45 and the source line 60_1 are connected to the nonlinear element 170a and 13 is a plan view of a portion connected by a nonlinear element 170b, which is an example of a protection circuit 97. FIG.

[0192] The nonlinear element 170a has a gate wiring 111a, which is connected to the common wiring 45. Either the source electrode or the drain electrode of the nonlinear element 170a is connected to the source wiring. 60_1, and the other is a first electrode 115a. a is connected to the common wiring 45 .

[0193] The nonlinear element 170b has a gate wiring 111b. The gate wiring 111b is connected to a contact hole. The source wiring 60 is connected to the source electrode 126, the second electrode 115b, and the contact hole 125. The source electrode and the drain electrode of the nonlinear element 170b are connected to the first electrode 11. The nonlinear element 170b is made up of a semiconductor layer 113 and a second electrode 115a. Yes.

[0194] Next, the configuration of the common wiring 45, the source wiring 60_1, and the nonlinear element 170b will be described with reference to FIG. This will be explained using 10.

[0195] The common wiring 45 is formed in the same wiring layer as the gate wiring. The gate wiring 45a and the gate wiring 45b are formed by laminating them on the insulating film 101. An insulating layer 102 is formed on the gate wiring 45b, and an insulating layer 117 is formed on the insulating layer 102. An insulating layer 118 is formed on the insulating layer 117 .

[0196] The source wiring 60_1 is formed on the insulating layer 118. The source wiring 60_1b is formed by stacking on the source wiring 60_1a. An insulating layer 119 is formed on 60_1.

[0197] The nonlinear element 170b has a gate wiring 111b on an insulating film 101 provided on a substrate 100. The insulating layer 102 is disposed on the gate wiring 111b. The semiconductor layer 113 is disposed on the line 111b, and the semiconductor layer 113 is disposed so as to overlap the end of the gate wiring 111b. 13. The gate wiring 111b is overlapped with the electrode 115a and the electrode 115b. An insulating layer 117 is provided in contact with the semiconductor layer 113 sandwiched between the ends of the electrodes 115a and 115b. An insulating layer 118 is formed on the insulating layer 117. It is constructed by laminating an edge layer 102a and an insulating layer 102b.

[0198] The electrode 115b is connected to the gate wiring via a contact hole 125 provided in the insulating layer 102. The electrode 115b is directly connected to the semiconductor substrate 111b via a contact hole 126. The insulating layer 118 and the source wiring 60_1 are connected to each other. A layer 119 is formed.

[0199] The conductive film that becomes the electrodes 115a and 115b may be made of Ti, Mo, W, Cr, Cu, T a. An element selected from the above, or an alloy containing the above elements, or a combination of the above elements The conductive film is not limited to a single layer containing the above-mentioned elements, but may be a laminate of two or more layers. A layer may be used.

[0200] In particular, the conductive film in contact with the semiconductor layer 113 is preferably made of a metal having a high oxygen affinity. A junction is formed between a metal with high oxygen affinity and an oxide semiconductor. Titanium is particularly favorable among metals with high oxygen affinity. Alternatively, a titanium nitride film may be used in place of the titanium film.

[0201] Such a junction structure is formed between the semiconductor layer 113 and the electrode 115a, and between the semiconductor layer 113 and the electrode 115. b, the operation of the nonlinear element 170a and the nonlinear element 170b becomes stable. That is, the thermal stability is increased, and stable operation is possible. This improves the circuit's functionality and stabilizes its operation. It also reduces junction leakage and reduces nonlinearity. The parasitic resistance and the variation thereof of the element 170a and the nonlinear element 170b can be reduced.

[0202] The nonlinear elements 170a and 170b have the same configuration in the main part. The nonlinear element 170b is the same as the thin film transistor of the pixel portion described in the first embodiment. Therefore, in this embodiment, the nonlinear element 170a and the nonlinear A detailed description of the thin film element 170b will be omitted. It can be made using the same process.

[0203] An example of a connection between common wirings will be described with reference to FIG. 11. Note that FIG. 11(A) shows the wiring and the wiring FIG. 11(B) is a plan view of a connection portion between the , R3-R4 cross-sectional view corresponding to the cutting line.

[0204] As already explained, the common wiring 45 is formed by stacking the gate wiring 45b on the gate wiring 45a. The common wiring 65 has the same configuration as the source wiring 60_1. That is, the common wiring 65 has a configuration in which a source wiring 65b is laminated on a source wiring 65a. The source wiring 65a is formed of the same conductive film as the source wiring 60_1a, and the source wiring 65b is The wiring 60_1b is formed of the same conductive film.

[0205] At the connection portion 95, the common wiring 45 and the common wiring 65 are electrically connected. The common wiring 45 and the common wiring 65 are formed by insulating layers 102 and 65a. The contact is made through a contact hole 127 formed in the edge layer 117 and the insulating layer 118. .

[0206] In the connection portion 95, the gate wiring 45b and the solder joint are made of a conductive material containing an element having a melting point higher than that of Cu. The base wiring 65a is connected to the base wiring 65a, realizing a highly reliable connection. The gate wiring 45a and the source wiring 65b made of this material suppress the wiring resistance.

[0207] The common connection portion 96 is provided in the outer region of the pixel portion, and is made of conductive particles (plastic particles). The substrate has a connection part arranged opposite to the surface of the substrate through a gold-plated particle (e.g., a gold-plated particle on the surface) and is electrically connected to the substrate. As an example of the common connection portion 96, a gate wiring 45a is connected to the gate wiring 45b. A structure in which 45b is formed on the laminated conductive layers will be described with reference to FIG.

[0208] The common connection portion 96 is electrically connected to the common wiring 45. The gate electrode 94 is disposed on the gate wiring 45a. An electrode 1 is formed on the conductive layer on which the wiring 45b is laminated, via an insulating layer 102a and an insulating layer 102b. The electrode 115c is formed on the insulating layer 102a and the insulating layer 102b. The electrode 115c is electrically connected to the conductive layer through a contact hole 128. A conductive layer 66 having the same structure as the common line 65 is laminated on the common line 65, and further functions as a pixel electrode. The conductive layer 129 is formed using a light-transmitting conductive film similar to the electrode 212 .

[0209] The gate wiring 45a and the source wiring 60 connected to the protection circuit exemplified in this embodiment The wiring 1b is made of a conductive material containing Cu and has low wiring resistance.

[0210] The gate wiring 45b is made of an element having a higher melting point than Cu, such as W, Ta, Mo, Ti, or Cr. The gate wiring 45a is formed by using a conductive material containing silicon so as to contact and cover the gate wiring 45a. Therefore, migration in the port wiring 45a can be suppressed, and the reliability of the semiconductor device can be improved. In addition, the insulating layers located above and below the gate wiring 45a containing Cu are made of silicon nitride. The insulating layer is made of a material containing Cu, and the gate wiring 45a containing Cu is sandwiched or wrapped by the insulating layer. This can prevent diffusion of Cu contained in the gate wiring 45a.

[0211] In addition, in the protection circuit exemplified in this embodiment, the first terminal (gate) of the nonlinear element is connected to the second terminal It is directly connected to the first terminal (source) or the third terminal (drain) through a contact hole. As a result, the interface and the contact hole formed by one connection are one This is smaller than the case where the connection is made via another wiring layer.

[0212] In addition, the electrical resistance can be reduced by reducing the number of interfaces required for connection. If the number of contact holes is small, the area occupied by the connection portion can be reduced.

[0213] Therefore, the protection circuit exemplified in this embodiment can reduce the connection resistance. This ensures stable operation of the protection circuit. In addition, only one contact hole is required for connection. The area occupied by the protection circuit can be reduced, thereby making it possible to miniaturize the display device.

[0214] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0215] (Embodiment 5) In this embodiment, the gate terminal portion of the display device shown in FIG. 7 and the source signal line terminal of the source terminal section 8. FIG.

[0216] FIG. 12(A1) and FIG. 12(A2) are a cross-sectional view and a plan view, respectively, of a gate signal line terminal. FIG. 12(A1) corresponds to a cross-sectional view taken along line C1-C2 in FIG. 12(A2). As shown in FIG. 12(A1), the gate signal line terminal is formed by forming an insulating layer 360 on a substrate 300. A gate wiring 351a is formed on the insulating layer 360, and at least the gate wiring 35 A gate wiring 351b is formed so as to cover the end of 1a, and an insulating layer is formed on the gate wiring 351b. 361, insulating layer 362, insulating layer 363, insulating layer 364, and insulating layer 365 are formed. A transparent conductive layer 355 is formed on the gate wiring 351b. The wiring 351a and the gate wiring 351b are collectively called the gate wiring 351. The insulating layer 361 to the insulating layer 1b function as a first terminal of the gate signal line terminal. The edge of the edge layer 365 is patterned, the edge of the gate wiring 351b is exposed, and the transparent conductive layer The first terminal is in direct contact with the end of the gate wiring 351b. The conductive layer 355 is a terminal electrode for connection that functions as an input terminal. 351a, the gate wiring 351b and the transparent conductive layer 355 are the same as those in the first and second embodiments. The gate wiring 202, the gate wiring 203, and the electrode 212 shown in FIG. The insulating layers 360 to 365 can be formed by the method described in Embodiment 1. The insulating layer 201, the insulating layer 204, the insulating layer 208 and the insulating layer 2 It can be formed using the same material and method as in 11.

[0217] The gate wiring 351a is made of a conductive material containing Cu, so that the gate signal line terminal and Also, the wiring resistance in the lead-in wiring from the gate signal line terminal can be reduced. The gate wiring 351b is made of an element having a melting point higher than that of Cu, such as W, Ta, Mo, Ti, or Cr. The gate wiring 351a is formed by using a conductive material containing Therefore, migration in the port wiring 351a can be suppressed, and the reliability of the semiconductor device can be improved. In addition, the insulating layers located above and below the gate wiring 351a containing Cu can be formed of silicon nitride. The insulating layers 360 and 361 are insulating layers containing Cu. By sandwiching or wrapping the wiring 351a, the C It can prevent the spread of u.

[0218] FIG. 12(B1) and FIG. 12(B2) are a cross-sectional view and a plan view of a source signal line terminal, respectively. FIG. 12(B1) is a cross-sectional view taken along line D1-D2 in FIG. 12(B2). The source signal line terminal is formed by forming an insulating layer 3 on a substrate 300 as shown in FIG. 60, an insulating layer 361 and an insulating layer 362 are formed, and an electrode 352 is formed on the insulating layer 362. An insulating layer 363 and an insulating layer 364 are formed on the electrode 352, and a source electrode 365 is formed on the insulating layer 364. A wiring 354a is formed, a source wiring 354b is formed on the source wiring 354a, and a source An insulating layer 365 is formed on the wiring 354b, and a transparent conductive layer is formed on the insulating layer 365 and the electrode 352. Here, the source wiring 354a and the source wiring 354b are joined together. The insulating layers 363 to 365 are patterned at their ends. The end of the electrode 352 is exposed and in direct contact with the transparent conductive layer 355. A contact hole is formed in the insulating layer 364 and the second source signal line end. The electrode 352 functioning as a terminal is connected to the source wiring 354. The transparent conductive layer 355 in direct contact with the end of a certain electrode 352 is a connection terminal that functions as an input terminal. Here, the electrode 352, the source wiring 354a, the source wiring 354b, and The transparent conductive layer 355 is a pair of electrodes 207a and 207b shown in the first and second embodiments. The electrode 207b, the source wiring 209, the source wiring 210, and the electrode 212 are made of the same material. The insulating layers 360 to 365 can be formed by the method described above. The insulating layer 201, the insulating layer 204, the insulating layer 208 and the insulating layer 209 shown in the first embodiment and the second embodiment are It can be formed using the same materials and methods as those for layer 211.

[0219] The source wiring 354b is made of a conductive material containing Cu, so that the source signal line terminal and Also, the wiring resistance in the lead-in wiring from the source signal line terminal can be reduced. The source wiring 354a is made of an element having a melting point higher than that of Cu, such as W, Ta, Mo, Ti, or Cr. Conductive materials containing, or alloys of the above elements, or tantalum nitride, titanium nitride, By forming the insulating layer 354b in contact with the source wiring 354b using tungsten, molybdenum nitride, etc., To suppress migration in the source wiring 354b and improve the reliability of the semiconductor device In addition, the insulating layers located above and below the source wiring 354b containing Cu can be nitrided. The insulating layers 364 and 365 are insulating layers containing silicon, and the insulating layers are made of a solenoid containing Cu. By sandwiching or wrapping the source wiring 354b, The diffusion of Cu can be prevented.

[0220] In this embodiment, the gate wiring 351 having a laminated structure is a first terminal of the gate wiring 3 In the above example, the transparent conductive layer 355 functions as an input terminal. The form of the is not limited to this. As shown in FIG. 13(A1) and FIG. 13(A2), The first terminal is composed of only the gate wiring 351a, and the gate wiring 351a is connected to the transparent conductive layer 3 55 may be directly in contact with the substrate 55. This corresponds to a cross-sectional view taken along line C1-C2.

[0221] In this embodiment, the source wiring 354 is connected to the input terminal 352 via the electrode 352, which is the second terminal. In the above example, the transparent conductive layer 355 functions as an input terminal. As shown in FIG. 13(B1) and FIG. 13(B2), the second terminal In the source wiring 354 that functions as a transparent conductive layer, the source wiring 354b is directly connected to the transparent conductive layer 355. Here, FIG. 13(B1) is D1-D2 in FIG. 13(B2). It corresponds to a cross-sectional view taken along the line.

[0222] A plurality of gate lines, source lines, and capacitance lines are provided according to the pixel density. In addition, in the terminal section, a first terminal has the same potential as the gate wiring, a second terminal has the same potential as the source wiring, The terminal 2 and the third terminal of the same potential as the capacitance wiring are arranged in a row. The number of terminals may be any number and may be determined appropriately by the implementer.

[0223] Note that the structure described in this embodiment mode may be appropriately combined with structures described in other embodiments. It is possible to do so.

[0224] (Embodiment 6) In this embodiment, at least a part of the driver circuit and a thin film transistor to be disposed in the pixel portion are formed on the same substrate. An example of fabricating a transistor will be described below.

[0225] The thin film transistor disposed in the pixel portion is formed according to any one of the first to fourth embodiments. The thin film transistors described in any of the embodiments 1 to 4 are n-channel TFTs. Therefore, some of the driver circuits can be configured with n-channel TFTs. The thin film transistors in the pixel portion are formed on the same substrate.

[0226] An example of a block diagram of an active matrix display device is shown in FIG. A pixel portion 5301, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, and a third scanning line driver circuit 5304 are provided on a substrate 5300. A signal line driver circuit 5303 and a signal line driver circuit 5304 are provided in the pixel portion 5301. A signal line is arranged extending from a signal line driver circuit 5304, and a plurality of scanning lines are arranged in a first scanning line driver circuit 5305. The scanning line driver circuit 5302 and the second scanning line driver circuit 5303 are arranged to extend from each other. At the intersections of the scan lines and the signal lines, pixels each having a display element are arranged in a matrix. The display device substrate 5300 is made of a flexible printed circuit board (FPC). A timing control circuit 5305 (controller, control circuit) and other connecting parts are connected to the timing control circuit 5305. The power supply is connected to the power supply IC (also called the control IC).

[0227] A first scanning line driver circuit 5302, a second scanning line driver circuit 5303, The signal line driver circuit 5304 is formed over the same substrate 5300 as the pixel portion 5301. Therefore, the number of externally provided parts such as drive circuits can be reduced, leading to cost reduction. In addition, the number of connections (such as FPCs) between the substrate 5300 and the external drive circuit can be reduced. Therefore, it is possible to improve the reliability or the yield.

[0228] The timing control circuit 5305 is, for example, A first scanning line driving circuit start signal (GSP1), a scanning line driving circuit clock signal (GCK1). The timing control circuit 5305 also supplies the second scanning line driving circuit For example, the second scanning line driver circuit start signal (GSP2) (start The signal line supplies the clock signal (GCK2) for the scanning line driver circuit. A start signal (SSP) for the signal line driver circuit and a clock for the signal line driver circuit are input to the driver circuit 5304. Clock signal (SCK), data for video signal (DATA) (also simply called video signal), Each clock signal is a multiple of the clock signal (LAT) with different periods. It may be a clock signal or may be supplied together with an inverted clock signal (CKB). The first scanning line driver circuit 5302 and the second scanning line driver circuit 53 It is possible to omit either 03 or 04.

[0229] In FIG. 18B, a circuit with a low driving frequency (for example, the first scanning line driving circuit 5302, The second scanning line driver circuit 5303) is formed on the same substrate 5300 as the pixel portion 5301, and the signal line driver The configuration in which the driving circuit 5304 is formed on a substrate different from that of the pixel portion 5301 is shown. Due to its structure, the field effect mobility is smaller than that of a transistor using a single crystal semiconductor. The driving circuit formed on the substrate 5300 can be configured by the thin film transistor. Therefore, it is possible to increase the size of the display device, reduce the number of steps, reduce costs, or improve yields. It is possible to plan this.

[0230] The thin film transistors described in any of the embodiments 1 to 4 are n-channel TFTs. In FIG. 19(A) and FIG. 19(B), a signal line driver circuit configured with an n-channel TFT is shown. An example of the configuration and operation will be described.

[0231] The signal line driver circuit includes a shift register 5601 and a switching circuit 5602 . The switching circuit 5602 includes switching circuits 5602_1 to 5602_N (N is a natural number). The switching circuits 5602_1 to 5602_N each have a A plurality of thin film transistors 5603_1 to 5603_k (k is a natural number) are provided. The thin film transistors 5603_1 to 5603_k are n-channel TFTs. An example will be explained.

[0232] The connection relationship of the signal line driver circuit will be described using the switching circuit 5602_1 as an example. The first terminals of the thin film transistors 5603_1 to 5603_k are respectively connected to the wiring 5604_1 The second terminals of the thin film transistors 5603_1 to 5603_k are connected to are connected to the signal lines S1 to Sk, respectively. The gate of k is connected to the wiring 5605_1.

[0233] The shift register 5601 sequentially outputs H level (H signal) to the wirings 5605_1 to 5605_N. , or high power supply potential level), and the switching circuits 5602_1 to 56 It has the function of selecting 02_N in sequence.

[0234] For example, the switching circuit 5602_1 includes wirings 5604_1 to 5604_k and a signal line S 1 to Sk (conduction between the first terminal and the second terminal), that is, the function of controlling the conduction state between the wiring 5 The function of controlling whether or not the potential of 604_1 to 604_k is supplied to the signal lines S1 to Sk is In this way, the switching circuit 5602_1 has a function as a selector. The thin film transistors 5603_1 to 5603_k are connected to wirings 5604_1 to 5604_k, respectively. A function of controlling the conduction state between the wirings 5604_1 to 5604_k and the signal lines S1 to Sk, that is, 04_k to the signal lines S1 to Sk. Each of the switches 5603_1 to 5603_k functions as a switch.

[0235] In addition, the wirings 5604_1 to 5604_k each carry video signal data (DATA). The video signal data (DATA) is an analog signal corresponding to the image information or image signal. This is often a signal that

[0236] Next, the operation of the signal line driver circuit of FIG. 19(A) will be described with reference to the timing chart of FIG. 19(B). FIG. 19B shows signals Sout_1 to Sout_N and An example of Vdata_1 to Vdata_k is shown. These are examples of output signals of the shift register 5601, and signals Vdata_1 to Vdata _k are examples of signals input to the wirings 5604_1 to 5604_k, respectively. One operation period of the signal line driving circuit corresponds to one gate selection period in the display device. The selection period is divided into periods T1 to TN, for example. This is a period for writing video signal data (DATA) to the pixels belonging to the selected row. be.

[0237] In the drawings of the present embodiment, the signal waveforms of the components are not rounded for clarity. Therefore, the scale may not necessarily be limited to the actual scale. It should be noted that

[0238] During the period T1 to the period TN, the shift register 5601 outputs an H-level signal to the wiring 560 For example, in the period T1, the shift registers 5 601 outputs a high-level signal to the wiring 5605_1. Since 5603_1 to 5603_k are turned on, wiring 5604_1 to 5604_k and signal At this time, the wirings 5604_1 to 5604_k are in a conductive state. Data(S1)~Data(Sk) are input. Data(S1)~Data(Sk ) belong to a selected row via thin film transistors 5603_1 to 5603_k. In this way, during the periods T1 to TN, Then, the video signal data (DATA) is sent to the pixels in the selected row in order of k columns. It will be written.

[0239] As described above, video signal data (DATA) is written to the pixels in multiple columns. This makes it possible to reduce the number of video signal data (DATA) or the number of wirings. This reduces the number of connections to external circuits. A) is written to the pixels in multiple columns at a time, which allows the writing time to be extended. This makes it possible to prevent insufficient writing of video signal data (DATA).

[0240] The shift register 5601 and the switching circuit 5602 may be the same as those described in the third embodiment. In this case, a circuit including a thin film transistor shown in FIG. The polarity of all the transistors in the resistor 5601 is either N-channel or P-channel. It can be configured with only one polarity.

[0241] Regarding one form of a shift register used as a part of a scanning line driver circuit and / or a signal line driver circuit, This will be described with reference to FIG. 20 and FIG.

[0242] The scanning line driving circuit has a shift register. In some cases, it may also have a level shifter or a buffer. In the scanning line driver circuit, a clock signal is input to the shift register. The selection signal is generated by inputting the clock signal (CK) and the start pulse signal (SP). The generated selection signal is buffered and amplified in a buffer and then supplied to the corresponding scan line. The gate electrodes of the transistors of the pixels for one line are connected to the scanning line. Since the transistors of the pixels in one line must be turned on simultaneously, The capacitor used is capable of carrying a large current.

[0243] The shift register includes a first pulse output circuit 10_1 to an N-th pulse output circuit 10_N ( N is a natural number of 3 or more (see FIG. 20(A)). The first pulse output circuit 10_1 to the N-th pulse output circuit 10_N of the register are A first clock signal CK1 is transmitted from a wiring 11, and a second clock signal CK2 is transmitted from a second wiring 12. , a third clock signal CK3 is output from a third wiring 13, and a fourth clock signal CK4 is output from a fourth wiring 14. In the first pulse output circuit 10_1, a signal CK4 is supplied from the fifth wiring 15. A start pulse SP1 (first start pulse) is input. In the pulse output circuit 10_n (n is a natural number between 2 and N), the pulse output A signal from the circuit (called the previous signal OUT(n-1)) (n is a natural number greater than or equal to 2) is input. In addition, in the first pulse output circuit 10_1, the third pulse output circuit 10_3, which is two stages behind, Similarly, in the n-th pulse output circuit 10_n in the second stage or later, a signal from The signal from the (n+2)th pulse output circuit 10_(n+2) in the subsequent stage (subsequent stage signal OUT( Therefore, the pulse output circuit of each stage outputs the following stage and / or The first output signal (OUT(1)(SR)~ OUT(N)(SR)), the second output signal (OUT(1)~OU T(N)) is output. As shown in FIG. 20(A), The latter stage signal OUT(n+2) is not input to the two stages. A second start pulse SP2 is sent from the wiring 16, and a third start pulse S Alternatively, the shift register can be configured to input P1, P2, and P3. For example, the (N+1)th pulse signal that does not contribute to the pulse output to the pixel unit may be Luth output circuit 10 (N+1) , the (N+2)th pulse output circuit 10 (N+2) (Da The dummy stage also receives a second start pulse (SP2) and a third start pulse (SP3). Alternatively, a configuration may be adopted in which a signal equivalent to the first pulse (SP3) is generated.

[0244] The clock signal (CK) goes between H and L levels (L signal, low power supply potential) at regular intervals. Here, the first clock signal (CK1) to the second clock signal (CK2) are The fourth clock signal (CK4) is delayed by 1 / 4 cycle in sequence. The first clock signal (CK1) to the fourth clock signal (CK4) are used to generate a pulse output circuit. The clock signal is GCK depending on the input drive circuit. It is sometimes called SCK, but here we will use CK for explanation.

[0245] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are connected to the first wiring 11 to It is electrically connected to any one of the fourth wirings 14. For example, in FIG. The first pulse output circuit 10_1 has a first input terminal 21 electrically connected to the first wiring 11. The second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal 23 is The second pulse output circuit 10_2 is electrically connected to the third wiring 13. The first input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 is electrically connected to the third wiring 13. The third input terminal 23 is electrically connected to the fourth wiring 14. There are.

[0246] Each of the first pulse output circuit 10_1 to the N-th pulse output circuit 10_N has a first input terminal a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal The input terminal 25, the first output terminal 26, and the second output terminal 27 (see FIG. 20(B)). In the first pulse output circuit 10_1, a first clock signal is input to a first input terminal 21. A first clock signal CK1 is input to the first input terminal 22, a second clock signal CK2 is input to the third input terminal 23, and a third clock signal CK3 is input to the second input terminal 24. A third clock signal CK3 is input to the input terminal 23 of the second clock CLK1, and a start signal CK4 is input to the fourth input terminal 24 of the third clock CLK2. A pulse is input, the next stage signal OUT(3) is input to the fifth input terminal 25, and the first output A first output signal OUT(1)(SR) is output from a terminal 26, and a second output signal OUT(1)(SR) is output from a second output terminal 27. The second output signal OUT(1) is output.

[0247] Next, an example of a specific circuit configuration of the pulse output circuit shown in FIG. 19(A) will be described with reference to FIG. Explain using (C).

[0248] The pulse output circuit shown in FIG. 20C includes a first transistor 31 to an eleventh transistor The first input terminal 21 to the fifth input terminal 25 and the first In addition to the first output terminal 26 and the second output terminal 27, a power supply to which a first high power supply potential VDD is supplied A power supply line 51 is connected to a power supply line 52 to which a second high power supply potential VCC is supplied, and a power supply line 53 is connected to which a low power supply potential VSS is supplied. A signal is supplied from the power supply line 53 to the first transistor 31 to the eleventh transistor 41. The power supply potential is supplied. The magnitude relationship of the power supply potential of each power supply line in FIG. 20(C) is as follows: The first high power supply potential VDD is set to a potential equal to or higher than the second high power supply potential VCC, and the second power supply potential VC C is a potential higher than the low power supply potential VSS. The fourth clock signal (CK4) is a signal that alternates between H and L levels at regular intervals. When the voltage is H level, it is VDD, and when the voltage is L level, it is VSS. By making VCC lower than the potential VDD of the power supply line 51, the operation is not affected. Therefore, the potential applied to the gate electrode of the transistor can be kept low. This reduces the shift in the threshold voltage and suppresses degradation.

[0249] In FIG. 20C, the first transistor 31 has a first terminal electrically connected to a power supply line 51. a second terminal electrically connected to a first terminal of a ninth transistor 39; is electrically connected to the fourth input terminal 24. The second transistor 32 is is electrically connected to the power supply line 53, and the second terminal is electrically connected to the first terminal of the ninth transistor 39. a gate electrode electrically connected to the gate electrode of the fourth transistor 34; The third transistor 33 has a first terminal electrically connected to the first input terminal 21, The second terminal is electrically connected to the first output terminal 26. The fourth transistor 34 is The first terminal is electrically connected to the power supply line 53, and the second terminal is electrically connected to the first output terminal 26. The fifth transistor 35 has a first terminal electrically connected to the power supply line 53, The second terminal is connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34. The gate electrode is electrically connected to the fourth input terminal 24. The transistor 36 of No. 6 has a first terminal electrically connected to the power supply line 52 and a second terminal electrically connected to the second Electrically connected to the gate electrode of the transistor 32 and the gate electrode of the fourth transistor 34 The seventh transistor has a gate electrode electrically connected to the fifth input terminal 25. The eighth transistor 37 has a first terminal electrically connected to the power supply line 52 and a second terminal electrically connected to the eighth transistor 38. and a gate electrode electrically connected to a third input terminal 23. The eighth transistor 38 has a first terminal connected to the gate electrode of the second transistor 32 and The fourth transistor 34 is electrically connected to a gate electrode thereof, the gate electrode of which is connected to the second input terminal The ninth transistor 39 has a first terminal electrically connected to the first transistor 22. The second terminal is electrically connected to the second terminal of the second transistor 31 and the second terminal of the second transistor 32. The gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 40 are connected to The tenth transistor is electrically connected to the power supply line 52, and the gate electrode is electrically connected to the power supply line 52. The resistor 40 has a first terminal electrically connected to the first input terminal 21 and a second terminal electrically connected to the second output terminal 22. a gate electrode electrically connected to the second terminal of the ninth transistor 39; The eleventh transistor 41 has a first terminal electrically connected to the power supply line 53. the second terminal is electrically connected to the second output terminal 27, and the gate electrode is The gate electrode of the fourth transistor 32 and the gate electrode of the fourth transistor 34 are electrically connected to each other. There are.

[0250] In FIG. 20C, the gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 4 The connection point of the gate electrode of transistor 0 and the second terminal of transistor 939 is referred to as node A. In addition, the gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, the second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, the second terminal of the eighth transistor The connection point of the first terminal of the transistor 38 and the gate electrode of the eleventh transistor 41 is node B. (See FIG. 21(A)).

[0251] A thin film transistor is defined as a transistor having at least three elements including a gate, a drain, and a source. A semiconductor device has a terminal and a channel region formed in a region overlapping with a gate. By controlling the gate potential, the drain and source are connected via the channel region. The current flowing between the source and drain can be controlled by the thin film transistor. Which is the source or drain depends on the transistor structure and operating conditions, etc. Therefore, the regions that function as the source and drain are In some cases, the term "source" or "drain" is not used. In such cases, for example, They may be referred to as terminal or second terminal.

[0252] Here, the timing of the shift register having a plurality of pulse output circuits shown in FIG. A shift register is a scanning line driver circuit. In this case, the period 61 in FIG. 21B corresponds to a vertical blanking period, and the period 62 corresponds to a gate selection period. do.

[0253] As shown in FIG. 21A, the ninth transistor has a gate to which the second power supply potential VCC is applied. By providing the transistor 39, the following can be achieved before and after the bootstrap operation: There are such advantages.

[0254] In the absence of the ninth transistor 39, the gate electrode of which is applied with the second power supply potential VCC, When the potential of the node A rises due to the base strap operation, the second transistor 31 The potential of the source terminal rises and becomes higher than the first power supply potential VDD. Then, the source of the first transistor 31 is switched to the first terminal side, that is, the power supply line 51 side. Therefore, in the first transistor 31, between the gate and the source, between the gate and the drain In both cases, a large voltage is applied, which causes a large stress and can lead to deterioration of the transistor. Therefore, the ninth transistor, whose gate electrode is applied with the second power supply potential VCC, By providing a resistor 39, the potential of node A rises due to the bootstrap operation. However, the potential of the second terminal of the first transistor 31 is not increased. That is, by providing the ninth transistor 39, the first transistor 3 The negative voltage applied between the gate and source of 1 can be reduced. By using the circuit configuration of this embodiment, the gate and source of the first transistor 31 Since the negative voltage applied between the first transistor 31 and the second transistor 32 can be reduced, the stress-induced breakdown of the first transistor 31 can be reduced. Deterioration can be suppressed.

[0255] The ninth transistor 39 is provided at a position corresponding to the second gate of the first transistor 31. A terminal is connected between the terminal and the gate of the third transistor 33 via a first terminal and a second terminal. In addition, in the present embodiment, a system having a plurality of pulse output circuits may be provided. In the case of a soft register, the signal line driver circuit has more stages than the scan line driver circuit. The resistor 39 may be omitted, which has the advantage of reducing the number of transistors.

[0256] Note that the semiconductor layers of the first to eleventh transistors 31 to 41 are made of oxide semiconductor. By using a conductor, the off-current of the thin film transistor is reduced, and the on-current and Because it is possible to increase the field effect mobility and reduce the degree of degradation. In addition, a transistor including an oxide semiconductor can be Compared to transistors using amorphous silicon, a high potential is applied to the gate electrode. Therefore, the degree of deterioration of the transistor due to the second power supply potential VCC is small. The same operation can be obtained by supplying the first power supply potential VDD to the power supply line. Since the number of power lines to be routed can be reduced, the circuit can be made more compact.

[0257] The gate electrode of the seventh transistor 37 is connected to the third input terminal 23. A lock signal is supplied by the second input terminal 22 to the gate electrode of the eighth transistor 38. The clock signal to be generated is input to the gate electrode of the seventh transistor 37 by the second input terminal 22. a clock signal provided by the third input terminal 23 to the gate electrode of the eighth transistor 38; The same effect can be obtained by swapping the wiring so that the clock signal is supplied by At this time, in the shift register shown in FIG. The seventh transistor 37 is turned off, and the eighth transistor 38 is turned on. The first transistor 38 is on, then the seventh transistor 37 is off, and the eighth transistor By turning off the resistor 38, the second input terminal 22 and the third input terminal 2 The voltage drop at node B caused by the voltage drop at node 3 is applied to the gate of the seventh transistor 37. This is due to a drop in the potential of the gate electrode of the eighth transistor 38 and a drop in the potential of the gate electrode of the eighth transistor 39. On the other hand, in the shift register shown in FIG. The seventh transistor 37 and the eighth transistor 38 are both in an on state. 37 is on, the eighth transistor 38 is off, then the seventh transistor 37 is By turning off the eighth transistor 38, the second input terminal 22 and The drop in the potential of the node B caused by the drop in the potential of the third input terminal 23 is The number of times the potential of the gate electrode of the transistor 38 is lowered can be reduced to one. The clock signal CK3 is input to the gate electrode of the seventh transistor 37 from the third input terminal 23. The gate electrode of the eighth transistor 38 receives the clock signal from the second input terminal 22. It is preferable to have a wiring relationship in which CK2 is supplied. This is because the fluctuation of the potential of node B This is because the number of times is reduced and noise can be reduced.

[0258] In this manner, the potentials of the first output terminal 26 and the second output terminal 27 are maintained at the L level. By configuring the node B to periodically receive a high-level signal during the period, the pulse output This makes it possible to suppress malfunction of the power circuit.

[0259] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0260] (Embodiment 7) A thin film transistor is manufactured, and the thin film transistor is used in a pixel portion and further in a driver circuit. A semiconductor device (also called a display device) having a display function can be manufactured. The transistors and part or the entire driver circuit are integrated on the same substrate as the pixel section, An on-panel can be formed.

[0261] The display device includes a display element. The display element may be a liquid crystal element (also called a liquid crystal display element), a light-emitting A light-emitting element (also called a light-emitting display element) can be used. A light-emitting element is a light-emitting element that emits light by applying a current or a voltage. This category includes elements whose brightness is controlled by a specific factor, such as inorganic EL (Electroluminescent) devices. Also, electronic ink, etc. A display medium in which the contrast changes due to thermal effects can also be used.

[0262] The display device includes a panel in which a display element is sealed, and a controller for the panel. and a module in which an IC or the like including the above is mounted. In the process, the element substrate corresponds to one form before the display element is completed, and the element substrate is The element substrate is provided with a means for supplying a current to the display element in each of the plurality of pixels. The display element may be in a state where only the pixel electrodes of the display element are formed, or a conductive film that becomes the pixel electrodes may be formed. may be in a state after the formation of a film and before etching to form a pixel electrode, All forms apply.

[0263] In this specification, the term "display device" refers to an image display device, a display device, or an optical Also refers to connectors, such as FPC (Flexible Printed Circuit). inted circuit) or TAB (Tape Automated Bon ding tape or TCP (Tape Carrier Package) is used. Modules with printed wiring boards attached to the ends of TAB tape or TCP or the display element is mounted with an IC (integrated circuit) by the COG (Chip On Glass) method. The display device also includes all modules in which a display circuit (or other circuit) is directly mounted.

[0264] The appearance and cross section of a liquid crystal display panel, which is one mode of a semiconductor device, will be described with reference to FIG. 14(A1) and 14(A2) show thin film transistors 4010 and 4011 and a liquid crystal display. A panel in which an element 4013 is sealed between a second substrate 4006 and a sealing material 4005. FIG. 14(B) is a plan view of the same, and FIG. 14(B) corresponds to a cross-sectional view taken along line MN in FIG. 14(A1) and (A2). Correct.

[0265] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In this manner, a sealant 4005 is provided. A second substrate 4006 is provided on the path 4004. The line driver circuit 4004 is made up of a first substrate 4001, a sealant 4005, and a second substrate 4006. The liquid crystal layer 4008 is sealed together with the first substrate 4001. In a region different from the region surrounded by the material 4005, a single crystal is formed on a separately prepared substrate. A signal line driver circuit 4003 formed of a semiconductor film or a polycrystalline semiconductor film is mounted.

[0266] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG method, a wire The ear bonding method, the TAB method, etc. can be used. This is an example of mounting a signal line driver circuit 4003 by the OG method. FIG. 14(A2) shows a signal line driver circuit 4003 mounted by the TAB method. In this example, the signal line driver circuit 4003 is implemented by the above.

[0267] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In FIG. 14B, the thin film transistor included in the pixel portion 4002 A transistor 4010 and a thin film transistor 4011 included in the scanning line driver circuit 4004 Insulating layers 4041 and 402 are formed on the thin film transistors 4010 and 4011. 4001, 4042, and 4021 are provided on the first substrate 4001. 43 is provided on the gate electrode layer of the thin film transistor, and an insulating layer 4044 and an insulating layer 404 5 is provided on the insulating layer 4020. A source wiring 4046 is provided on the insulating layer 4020. Through contact holes formed in the insulating layer 4020 and the insulating layer 4041, It is connected to the source electrode or the drain electrode of the transistor 4010 .

[0268] The thin film transistors 4010 and 4011 are made of the oxide semiconductor layer shown in any one of Embodiments 1 to 4. A highly reliable thin film transistor including a semiconductor layer can be applied. In this embodiment, the thin film transistors 4010 and 4011 are n-channel thin film transistors.

[0269] The oxide semiconductor layer of the thin film transistor 4011 for the driver circuit is A conductive layer 4040 is provided in a position overlapping with the channel formation region. By providing the gate insulating film at a position overlapping the channel formation region of the nitride semiconductor layer, In addition, the amount of change in the threshold voltage of the thin film transistor 4011 can be reduced. The conductive layer 4040 may have the same potential as the gate electrode layer of the thin film transistor 4011. The conductive layer may be different from the first gate electrode layer and may function as the second gate electrode layer. The potential of 4040 may be GND, 0V, or may be in a floating state.

[0270] The thin film transistor manufactured according to the process described in the second embodiment is highly purified. For example, impurities (hydrogen atoms, H In order to prevent contamination by compounds containing hydrogen atoms such as 2O and compounds containing carbon atoms, The oxide is removed by an ion pump or the like after the film is formed for dehydration or dehydrogenation. The semiconductor layer is heat-treated, and a so-called back channel of the thin film transistor is formed. By forming an oxide insulating film in contact with the region, impurities are transported from the oxide semiconductor layer to the oxide Diffusion into the insulating film.

[0271] In addition, a conductive layer 4040 is provided in a position overlapping with the channel forming region, By shielding the thin film transistor from static electricity, The amount of electrically induced carriers can be reduced.

[0272] The oxide semiconductor layer is highly purified and shielded from static electricity, so that the oxide semiconductor layer The carrier density is reduced. For example, the carrier density of the oxide semiconductor layer is 1×10 14 / cm 3 The oxide semiconductor layer with the carrier density suppressed in this way is a thin film transistor. By using it as a transistor, the off-current (I off ) can provide a thin-film transistor with a small In addition, the off-current (I off ) is suppressed, the thin film transistor is applied to a display device. As a result, a display device with low power consumption can be provided.

[0273] In addition, a pixel electrode layer 4030 of the liquid crystal element 4013 is connected to the thin film transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is electrically connected to the second substrate 40. 06. A pixel electrode layer 4030, a counter electrode layer 4031, and a liquid crystal layer 4008 are formed. The overlapping portion corresponds to the liquid crystal element 4013. The electrode layer 4031 is provided with insulating layers 4032 and 4033 which function as alignment films. A liquid crystal layer 4008 is sandwiched between edge layers 4032 and 4033 .

[0274] The first substrate 4001 and the second substrate 4006 may be light-transmitting substrates. Glass, ceramics, and plastics can be used. , FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film, or acrylic resin film A film can be used.

[0275] The spacer 4035 is a columnar spacer obtained by selectively etching an insulating film. The distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031 is controlled. The spacer 4035 is provided to control the amount of light emitted from the spacer 4035. A spherical spacer may be used as the spacer 4035. In addition, the counter electrode layer 4031 is provided over the same substrate as the thin film transistor 4010. The common connection portion is electrically connected to the common potential line. The counter electrode layer 4031 and the common potential line can be electrically connected via the conductive particles. The conductive particles are contained in the sealing material 4005 .

[0276] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so it is necessary to improve the temperature range. In order to achieve this, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal layer 4008. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed of 1 msec. Since the liquid crystal display is optically isotropic, no alignment treatment is required, and the viewing angle dependency is small.

[0277] In addition to the transmission type liquid crystal display device, the present invention can also be applied to a semi-transmission type liquid crystal display device.

[0278] In addition, in liquid crystal display devices, a polarizing plate is provided on the outer side (the viewing side) of the substrate, and a colored layer (color In this example, the polarizing plate is placed on the inner side of the substrate. The laminated structure of the polarizing plate and the colored layer is not limited to the embodiment, and the polarizing plate may be provided in the same manner. The thickness may be appropriately set depending on the material of the colored layer and the manufacturing process conditions.

[0279] The thin film transistor 4011 is in contact with a semiconductor layer including a channel formation region as a protective insulating film. The insulating layer 4041 is formed by the insulating layer 4041 as described in the first embodiment and the second embodiment, for example. The insulating layer 208 may be formed using the same material and method as the insulating layer 208 shown in the second embodiment. As the 4041, silicon oxide is deposited by sputtering in the same manner as in the first and second embodiments. A bare film is formed.

[0280] In addition, in order to reduce surface irregularities caused by the thin film transistor, a planarizing insulating film is formed on the insulating layer 4020. An insulating layer 4021 is formed to function as a film. The insulating layer 4021 is made of a material such as polyimide, aluminum, or the like. Acrylic resin, benzocyclobutene resin, polyamide, epoxy resin, etc. In addition to the above organic materials, low-k materials can be used. materials), siloxane resin, PSG (phosphorus glass), BPSG (borophosphorus glass), etc. In addition, by stacking a plurality of insulating films made of these materials, An insulating layer 4021 may be formed.

[0281] Siloxane-based resin is a type of Si-OS formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. Alternatively, the organic group may have a fluoro group. That's fine.

[0282] The method for forming the insulating layer 4021 is not particularly limited, and may be a sputtering method, an SOG method, or the like, depending on the material. , spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife The baking process of the insulating layer 4021 and the annealing of the semiconductor layer can be performed by using a fcoater or the like. By using both, a semiconductor device can be manufactured efficiently.

[0283] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide. , indium zinc oxide with tungsten oxide, indium oxide with titanium oxide, Indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), Conductive materials with translucency such as indium zinc oxide and indium tin oxide doped with silicon oxide Conductive materials can be used.

[0284] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of a conductive polymer. The conductive composition may be used to form the conductive film. The pixel electrode thus fabricated has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 550 nm. It is preferable that the resistance of the conductive polymer contained in the conductive composition is 70% or more. It is preferable that the electrical conductivity be 0.1 Ω·cm or less.

[0285] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0286] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel section 4 Various signals and potentials are applied to 002 via FPC4018.

[0287] The connection terminal electrode 4015 is made of the same conductive film as the pixel electrode layer 4030 of the liquid crystal element 4013. The terminal electrode 4016 is formed from the source electrode layers of the thin film transistors 4010 and 4011. The drain electrode layer is formed of the same conductive film as the drain electrode layer.

[0288] The connection terminal electrode 4015 is connected to a terminal of the FPC 4018 via an anisotropic conductive film 4019. The electrodes are electrically connected to each other.

[0289] In FIG. 14, a signal line driver circuit 4003 is formed separately and mounted on a first substrate 4001. The embodiment is not limited to this configuration. Alternatively, only a part of the signal line driver circuit or a part of the scanning line driver circuit may be separately formed. It may be implemented.

[0290] FIG. 23 shows a semiconductor device using a TFT substrate 2600 produced by the production method disclosed in this specification. 1 shows an example in which a liquid crystal display module is configured as a semiconductor device.

[0291] FIG. 23 shows an example of a liquid crystal display module, in which a TFT substrate 2600 and an opposing substrate 2601 are connected. The substrate 2602 is fixed to the substrate 2601 by a bonding material 2602, and a pixel portion 2603 including a TFT and the like and a liquid crystal layer are disposed between the substrate 2601 and the substrate 2602. A display element 2604 and a colored layer 2605 are provided to form a display area. 5 is necessary for color display, and in the case of the RGB method, it corresponds to each color of red, green, and blue. A colored layer is provided for each pixel. A polarizing plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are disposed on the outside of the light source. The display is composed of a cold cathode fluorescent lamp 2610 and a reflector 2611, and the circuit board 2612 is a flexible A wiring board 2609 is connected to the wiring circuit section 2608 of the TFT substrate 2600, and the control External circuits such as roll circuits and power circuits are built in. Also, between the polarizer and the liquid crystal layer The layers may be laminated together with a retardation plate therebetween.

[0292] The LCD module is available in TN (Twisted Nematic) mode, IPS (In-plane Switching) mode, n-Plane-Switching mode, FFS (Fringe Field Switching) switching mode, MVA (Multi-domain Vertical A alignment) mode, PVA(Patterned Vertical Alignment) mode nment) mode, ASM(Axially Symmetric aligned Micro-cell mode, OCB (Optically Compensated Birefringence mode, FLC (Ferroelectric Liquid uid Crystal) mode, AFLC(AntiFerroelectric L iquid Crystal mode etc. can be used.

[0293] By the above steps, a highly reliable liquid crystal display panel can be manufactured as a semiconductor device. do.

[0294] The liquid crystal display device is manufactured using the display device described in any of Embodiments 1 to 5. This allows the gate wiring and source wiring to be formed from a conductive material containing Cu, It is possible to prevent an increase in wiring resistance, thereby enabling the liquid crystal display device to operate at a high speed and with low power consumption. Therefore, it is possible to provide a liquid crystal display device that can accommodate a large screen and a high-definition screen. This can be done.

[0295] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0296] (Embodiment 8) An example of electronic paper will be shown as one mode of a semiconductor device.

[0297] The thin film transistor of the first embodiment uses an element electrically connected to a switching element. The present invention may be used for electronic paper that drives electronic ink by electrophoretic display. The device (electrophoretic display) is also called "electrophoretic display" and has the same readability as paper and is superior to other display devices. It has the advantages of low power consumption and the ability to have a thin, lightweight shape.

[0298] Electrophoretic displays can take a variety of forms, but the first particle has a positive charge. A microcapsule containing a negatively charged second particle and a negatively charged second particle is immersed in a solvent or solute. By applying an electric field to the microcapsules, The particles in the tube are moved in opposite directions to each other, and only the color of the particles that have gathered on one side is displayed. In addition, the first particles or the second particles contain a dye, and they do not migrate in the absence of an electric field. The color of the first particle and the color of the second particle are different (including colorless). )

[0299] Thus, electrophoretic displays operate in such a way that materials with high dielectric constants migrate to areas of high electric field. This is a display that utilizes the so-called dielectrophoretic effect.

[0300] The microcapsules dispersed in a solvent are called electronic ink. The electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. A color display is also possible by using a color filter or particles having a pigment.

[0301] In addition, the above microphone is appropriately placed on the active matrix substrate so as to be sandwiched between two electrodes. By arranging multiple microcapsules, an active matrix display device is completed. If an electric field is applied to the cell, a display can be performed. For example, the thin film transistor of the first embodiment An active matrix substrate obtained by a laser diode can be used.

[0302] The first particles and the second particles in the microcapsules are made of a conductive material, an insulating material, Semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, A material selected from the group consisting of magnetochromic material, magnetophoretic material, and a composite material thereof. Just use it.

[0303] FIG. 22 shows an active matrix type electronic paper as an example of a semiconductor device. The thin film transistor 581 used in the device may be the thin film transistor shown in Embodiments 1 and 2. It can be fabricated in the same way as a thin-film transistor that contains an oxide semiconductor layer, and is a highly reliable thin-film transistor. It is Sta.

[0304] The electronic paper in FIG. 22 is an example of a display device that uses the twisting ball display method. The spherical display method is an electrode layer that uses spherical particles painted in black and white as display elements. The first electrode layer 587 and the second electrode layer 588 are disposed between the first electrode layer 587 and the second electrode layer 589. This is a method of displaying by controlling the orientation of spherical particles by creating a potential difference between 88. do.

[0305] The thin film transistor 581 formed on the substrate 580 is a bottom-gate thin film transistor. The substrate 580 is covered with an insulating layer 583 that is in contact with the semiconductor layer. An insulating layer 592 and an insulating layer 593 are formed on the gate electrode of the thin film transistor. 82 is formed, and insulating layers 597 and 598 are formed on the insulating layer 583. On the insulating layer 583, a source wiring 599a and a source wiring 599b are formed. The thin film transistor 5 is connected to the insulating layer 597 through a contact hole formed in the insulating layer 597. The source electrode layer or the drain electrode layer of the thin film transistor 581 is connected to the source electrode layer or the drain electrode layer of the thin film transistor 581. The source electrode layer or the drain electrode layer is formed by a first electrode layer 587 and an opening formed in the insulating layer 585. The first electrode layer 587 and the substrate 596 are in contact with each other and electrically connected. Between the second electrode layer 588 and the black area 590a and the white area 590b, A spherical particle 589 is provided that includes a cavity 594 that is filled with a liquid, the spherical particle The periphery of the electrode 589 is filled with a filler 595 such as resin (see FIG. 22). The layer 587 corresponds to a pixel electrode, and the second electrode layer 588 corresponds to a common electrode. 588 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 581. The common connection portion is used to connect the second electrode to the conductive particles disposed between the pair of substrates. Layer 588 may be electrically connected to a common potential line.

[0306] Also, instead of the twist ball, an electrophoretic element can be used. and a 10μm to 20μm diameter nanoparticle that contains positively charged white nanoparticles and negatively charged black nanoparticles. Microcapsules with a diameter of about 0 μm are used. When an electric field is applied to the microcapsules by the first and second electrode layers, the microcapsules emit white light. White particles and black particles move in opposite directions to display either black or white. The display element that applies this principle is the electrophoretic display element, and the device that uses the electrophoretic display element The electrophoretic display element is generally called electronic paper. Since all of them have high reflectivity, auxiliary lights are not required, and they consume little power, so they can be used in dimly lit places. Even if the power is not supplied to the display unit, Since it is possible to hold an image once it has been displayed, it is possible to transfer the image from the radio wave source to a semiconductor device with a display function. When a display device (also referred to simply as a display device or a semiconductor device equipped with a display device) is cut, Even if there is a problem, it is possible to store the displayed image.

[0307] Through the above steps, electronic paper having high reliability as a semiconductor device can be manufactured. .

[0308] The above electronic page can be manufactured by using the manufacturing method of the thin film transistor described in any of Embodiments 1 to 5. By fabricating a thin film transistor for each pixel, It is possible to suppress display unevenness caused by variations in the threshold voltage.

[0309] The electronic paper can be manufactured using the display device described in any of the embodiments 1 to 3. This allows the gate wiring and source wiring to be formed from a conductive material containing Cu, It is possible to prevent an increase in wiring resistance, thereby enabling the electronic paper to operate at a higher speed and with less power consumption. This allows for a large-screen, high-resolution electronic paper to be provided. This can be done.

[0310] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0311] (Embodiment 9) An example of a light-emitting display device is shown as a semiconductor device. is shown using a light-emitting element that uses electroluminescence. The light-emitting element that uses the light-emitting material is classified into two types according to whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element and the latter an inorganic EL element.

[0312] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into layers containing light-emitting organic compounds, causing a current to flow. The rears (electrons and holes) recombine to form an excited state in the light-emitting organic compound. When the excited state returns to the ground state, light is emitted. Such a light-emitting element is called a current-excitation type light-emitting element.

[0313] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements according to their element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor reaction that utilizes the donor and acceptor levels. Thin-film inorganic EL elements are made by sandwiching a light-emitting layer between dielectric layers. The structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0314] FIG. 16 shows an example of a pixel configuration to which digital time gray scale driving can be applied as an example of a semiconductor device. This is a diagram.

[0315] The configuration of a pixel to which digital time gray scale driving can be applied and the operation of the pixel will be described. The figure shows an n-channel transistor that uses an oxide semiconductor layer as a channel formation region in one pixel. Here is an example of using two of them.

[0316] The pixel 6400 includes a switching transistor 6401, a driving transistor 6402, The switching transistor 64 has a light emitting element 6404 and a capacitor element 6403. 01 has a gate connected to a scanning line 6406 and a first electrode (one of the source and drain electrodes) The first electrode (the other of the source electrode and the drain electrode) is connected to a signal line 6405, and the second electrode (the other of the source electrode and the drain electrode) is connected to a drive The driving transistor 6402 is connected to the gate of the driving transistor 6402. The gate is connected to a power supply line 6407 via a capacitor element 6403, and the first electrode is connected to a power supply line 640 7, and the second electrode is connected to the first electrode (pixel electrode) of the light emitting element 6404. The second electrode of the light emitting element 6404 corresponds to a common electrode 6408. It is electrically connected to a common potential line formed on the substrate.

[0317] A low power supply potential is set to the second electrode (common electrode 6408) of the light emitting element 6404. Note that the low power supply potential is a low power supply potential with respect to the high power supply potential set to the power supply line 6407. Potential < High power supply potential. For example, GND, 0V, etc. are set as low power supply potential. The potential difference between the high power supply potential and the low power supply potential is applied to the light emitting element 6404. In order to make the light emitting element 6404 emit light by passing a current through the light emitting element 6404, a high power supply potential and the low power supply potential is set to be equal to or higher than the forward threshold voltage of the light emitting element 6404. Each potential is set.

[0318] The capacitor 6403 is omitted by substituting the gate capacitance of the driving transistor 6402. It is also possible to set the gate capacitance of the driving transistor 6402 as follows: A capacitance may be formed between the gate electrode and the second electrode.

[0319] In the case of a voltage input voltage driving method, the gate of the driving transistor 6402 is The driving transistor 6402 is either fully on or fully off. In other words, the driving transistor 6402 operates in a linear region. In order to operate the driving transistor 6402 in a linear region, the power supply line 6407 A voltage higher than the voltage applied to the gate of the driving transistor 6402 is applied to the gate of the signal line 6403. A voltage equal to or higher than (power supply line voltage+Vth of driving transistor 6402) is applied to 05.

[0320] In addition, when analog gray scale driving is performed instead of digital time gray scale driving, the input of the signal is different. By doing so, the same pixel configuration as in FIG. 16 can be used.

[0321] In the case of performing analog gradation driving, a light emitting element 6404 is connected to the gate of a driving transistor 6402. A voltage equal to or higher than the forward voltage of the light emitting element 6401 and the Vth of the driving transistor 6402 is applied. The forward voltage in 04 refers to the voltage required to achieve the desired brightness, and should be at least 100% forward voltage. The driving transistor 6402 is set to operate in the saturation region. By inputting a suitable video signal, a current can be passed through the light emitting element 6404. In order to operate the transistor 6402 in the saturation region, the potential of the power supply line 6407 is set to the driving transistor 6402. The gate potential of the transistor 6402 is set higher than that of the transistor 6403. Analog gradation drive can be performed by passing a current according to a video signal through the optical element 6404. .

[0322] Note that the pixel configuration shown in FIG. 16 is not limited to this. For example, A switch, a resistive element, a capacitive element, a transistor, a logic circuit, or the like may be added.

[0323] Next, the configuration of the light emitting element will be described with reference to FIG. 17. Here, the driving TFT is The cross-sectional structure of a pixel will be described using the example of the type shown in Figure 17(A), (B), and (C). The driving TFTs used in the semiconductor device, TFTs 7001, 7011, and 7021, are The thin film transistor can be manufactured in the same manner as in the first and second embodiments. The present invention relates to a highly reliable thin film transistor including a

[0324] The light emitting element only needs to have at least one of the anode and cathode transparent in order to extract light. Then, a thin film transistor and a light emitting element are formed on the substrate, and light is taken from the surface opposite to the substrate. Top emission, bottom emission, and side emission. There are light-emitting elements with a double-sided emission structure that emits light from the side of the pixel. The present invention can also be applied to optical elements.

[0325] A light emitting element having a bottom emission structure will be described with reference to FIG.

[0326] The driving TFT 7011 is an n-type TFT, and light emitted from the light emitting element 7012 is incident on the cathode 7013 side. FIG. 17(A) shows a cross-sectional view of a pixel when emitting light. A cathode 7013 of a light-emitting element 7012 is formed on a light-transmitting conductive film 7017 that is electrically connected to the light-transmitting conductive film 7017. An EL layer 7014 and an anode 7015 are laminated in this order on a cathode 7013. In addition, an insulating layer 7031 is formed on the substrate, and a gate electrode of the driving TFT 7011 is formed on the insulating layer 7031. Insulating layers 7032 and 7036 are formed, and the source electrode and Insulating layers 7037, 7038, and 7039 are formed on the drain electrodes. On 7038, a source wiring 7018a and a source wiring 7018b are formed. The driving TFT 70 is connected to the insulating layer 7037 through a contact hole formed in the insulating layer 7038. The light-transmitting conductive film 7017 is connected to the source electrode of the insulating layer 7 Through contact holes formed in the TFTs 7037, 7038, and 7039, the driving TFT 701 The drain electrode of the first transistor is electrically connected to the drain electrode of the first transistor.

[0327] The light-transmitting conductive film 7017 can be formed of indium oxide containing tungsten oxide, oxide Indium zinc oxide with tungsten oxide, indium oxide with titanium oxide, Indium tin oxide containing titanium, indium tin oxide (hereinafter referred to as ITO), Conductive materials with optical transparency such as indium zinc oxide and indium tin oxide doped with silicon oxide A membrane may be used.

[0328] In addition, the cathode 7013 can be made of various materials, but a material with a relatively small work function is preferable. Specifically, for example, alkali metals such as Li and Cs, and aluminum metals such as Mg, Ca, and Sr. In addition to potassium earth metals and alloys containing them (Mg:Ag, Al:Li, etc.), Yb and E In FIG. 17(A), the thickness of the cathode 7013 is set to a thickness that transmits light. For example, the thickness of the 20 nm thick film is set to a value of about 5 nm to 30 nm. An aluminum film is used as the cathode 7013 .

[0329] After a light-transmitting conductive film and an aluminum film are laminated, the film is selectively etched. In this case, the conductive film 7017 and the cathode 7013 may be formed on the same substrate. It is preferable to use a etchant.

[0330] The periphery of the cathode 7013 is covered with a partition wall 7019. The partition wall 7019 is made of polyimide, alumina, Organic resin films such as acrylic resin, polyamide, and epoxy resin, inorganic insulating films, and organic polysiloxanes The partition wall 7019 is formed by using a photosensitive resin material, and the cathode 7013 is formed by using a photosensitive resin material. An opening is formed on the top, and the side wall of the opening becomes an inclined surface formed with a continuous curvature. In the case where a photosensitive resin material is used for the partition wall 7019, The step of forming a resist mask can be omitted.

[0331] The EL layer 7014 formed on the cathode 7013 and the partition wall 7019 is composed of a single layer. The EL layer 70 may be formed by laminating a plurality of layers. When the cathode 7013 is composed of a plurality of layers, an electron injection layer, an electron transport layer, a light emitting layer, and a The layer, the hole transport layer, and the hole injection layer are laminated in this order. There is no need to set

[0332] The stacking order is not limited to the above, and may be a hole injection layer, a hole transport layer, a light emitting layer, etc., on the cathode 7013. However, when comparing power consumption, the cathode may be used in the same manner as the cathode. An electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer are stacked on the electrode 7013 in this order. Layering is preferred because it consumes less power.

[0333] In addition, various materials can be used for the anode 7015 formed on the EL layer 7014. However, materials with large work functions, such as titanium nitride, ZrN, Ti, W, Ni, Pt, Cr, etc., and transparent conductive materials such as ITO, IZO (indium zinc oxide), and ZnO. It is preferable to provide a shielding film 7016 on the anode 7015. For example, the shielding film 7016 may be made of a metal that blocks light or a material that reflects light. In this embodiment, an ITO film is used as the anode 7015, and a shielding film 7 A Ti film is used as 016.

[0334] The region where the EL layer 7014 is sandwiched between the cathode 7013 and the anode 7015 is the light emitting element 7012. In the case of the element structure shown in FIG. 17A, the light emitted from the light emitting element 7012 is is emitted toward the cathode 7013 as indicated by the arrow.

[0335] In addition, FIG. 17A shows an example in which a light-transmitting conductive film is used as a gate electrode. The light emitted from the light emitting element 7012 passes through the color filter layer 7033 and is emitted. do.

[0336] The color filter layer 7033 is formed by a droplet discharge method such as an inkjet method, a printing method, or a photolithography method. Each is formed by an etching method using lithography technology.

[0337] The color filter layer 7033 is covered with an overcoat layer 7034, which is a protective insulating layer. In FIG. 17A, the overcoat layer 7034 is thin. As shown in FIG. 7, the overcoat layer 7034 has irregularities caused by the color filter layer 7033. It has the function of flattening the surface.

[0338] In addition, a protective insulating layer 7035, an overcoat layer 7034, and insulating layers 7037 and 7038, The contact hole formed in the partition wall 7039 and reaching the drain electrode is In FIG. 17(A), a contact hole that reaches the drain electrode and By adopting a layout in which the partition wall 7019 and the insulating film 7020 overlap, the aperture ratio can be improved.

[0339] Next, a light emitting element having a dual emission structure will be described with reference to FIG.

[0340] In FIG. 17B, a conductive film 7 having a light transmitting property is electrically connected to a driving TFT 7021. A cathode 7023 of a light-emitting element 7022 is formed on the cathode 7023. A layer 7024 and an anode 7025 are laminated in this order. In addition, an insulating layer 7041 is formed on the substrate. An insulating layer 7042 and an insulating layer 7046 are formed on the gate electrode of the driving TFT 7021. An insulating layer 7047 is formed on the source electrode and the drain electrode of the driving TFT 7021. 7048 and 7049 are formed on the insulating layer 7048. A source wiring 7028b is formed on the insulating layer 7047 and a source wiring 7028c is formed on the insulating layer 7048. The source electrode of the driving TFT 7021 is connected to the source electrode of the driving TFT 7021 through a contact hole. The light-transmitting conductive film 7027 is formed on insulating layers 7047, 7048, and 7049. It is electrically connected to the drain electrode of the driving TFT7021 through a contact hole. do.

[0341] The light-transmitting conductive film 7027 can be formed using indium oxide containing tungsten oxide, Indium zinc oxide with tungsten oxide, indium oxide with titanium oxide, Indium tin oxide containing titanium, indium tin oxide (hereinafter referred to as ITO), Conductive materials with optical transparency such as indium zinc oxide and indium tin oxide doped with silicon oxide A membrane may be used.

[0342] In addition, the cathode 7023 can be made of various materials, but a material with a relatively small work function is preferable. Specifically, for example, alkali metals such as Li and Cs, and aluminum metals such as Mg, Ca, and Sr. In addition to potassium earth metals and alloys containing them (Mg:Ag, Al:Li, etc.), Yb and E In this embodiment, the thickness of the cathode 7023 is set to a thickness that is light-transmitting. For example, the thickness of the 20 nm thick film is set to a value of about 5 nm to 30 nm. An aluminum film is used as the cathode 7023 .

[0343] After a light-transmitting conductive film and an aluminum film are laminated, the film is selectively etched. In this case, the conductive film 7027 and the cathode 7023 may be formed on the same substrate. It is preferable to use a etchant.

[0344] The periphery of the cathode 7023 is covered with a partition 7029. The partition 7029 is made of polyimide, alumina, Organic resin films such as acrylic resin, polyamide, and epoxy resin, inorganic insulating films, and organic polysiloxanes The partition wall 7029 is formed by using a photosensitive resin material, and the cathode 7023 is formed by using a photosensitive resin material. An opening is formed on the top, and the side wall of the opening becomes an inclined surface formed with a continuous curvature. In the case where a photosensitive resin material is used for the partition wall 7029, The step of forming a resist mask can be omitted.

[0345] The EL layer 7024 formed on the cathode 7023 and the partition wall 7029 is composed of a single layer. The EL layer 70 may be formed by laminating a plurality of layers. When the cathode 7023 is composed of a plurality of layers, an electron injection layer, an electron transport layer, a light emitting layer, and a The layer, the hole transport layer, and the hole injection layer are laminated in this order. There is no need to set

[0346] The stacking order is not limited to the above, and may be a hole injection layer, a hole transport layer, a light emitting layer, etc., on the cathode 7023. However, when comparing power consumption, the cathode may be used in the same manner as the cathode. An electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer are stacked on the electrode 7023 in this order. Layering is preferred because it consumes less power.

[0347] In addition, various materials can be used for the anode 7025 formed on the EL layer 7024. However, materials with relatively large work functions, such as transparent conductive materials such as ITO, IZO, and ZnO, are used. In this embodiment, an ITO film containing silicon oxide is used as the anode 7025. There are.

[0348] The region where the EL layer 7024 is sandwiched between the cathode 7023 and the anode 7025 is the light emitting element 7022. In the case of the element structure shown in FIG. 17B, the light emitted from the light emitting element 7022 is is emitted toward both the anode 7025 side and the cathode 7023 side as indicated by the arrows.

[0349] In addition, FIG. 17B shows an example in which a light-transmitting conductive film is used as a gate electrode. The light emitted from the light emitting element 7022 to the cathode 7023 passes through the color filter layer 7043. Pass it through and eject it.

[0350] The color filter layer 7043 is formed by a droplet discharge method such as an inkjet method, a printing method, or a photolithography method. Each is formed by an etching method using lithography technology.

[0351] The color filter layer 7043 is covered with an overcoat layer 7044, which is a protective insulating layer. Covered by layer 7045 .

[0352] In addition, a protective insulating layer 7045, an overcoat layer 7044, and insulating layers 7047 and 7048, The contact hole formed in the partition wall 7029 and reaching the drain electrode is The contact hole reaching the drain electrode and the partition wall 7029 are arranged in an overlapping position. By adopting this layout, the aperture ratio on the anode 7025 side and the cathode 7023 side are almost the same. It can be made one.

[0353] However, when using a light-emitting element with a dual-side emission structure and making both display surfaces full color display, Since the light from the anode 7025 side does not pass through the color filter layer 7043, a separate color filter is required. It is preferable to provide a sealing substrate having a filter layer above the anode 7025.

[0354] Next, a light emitting element having a top emission structure will be described with reference to FIG.

[0355] In FIG. 17C, a TFT 7001 which is a driving TFT is an n-type TFT, and a light emitting element 7002 emits light. FIG. 17C shows a cross-sectional view of a pixel in the case where the light incident thereon exits to the anode 7005 side. A cathode 7003 of a light emitting element 7002 electrically connected to a driving TFT 7001 is formed. An EL layer 7004 and an anode 7005 are laminated in this order on a cathode 7003. An insulating layer 7051 is formed on the substrate, and an insulating layer is formed on the gate electrode of the driving TFT 7001. 7052 and an insulating layer 7056 are formed, and the source electrode and drain electrode of the driving TFT 7001 are formed. Insulating layers 7057, 7058, and 7059 are formed on the electrodes. A source wiring 7008a and a source wiring 7008b are formed on the insulating layer 705. 7 and the insulating layer 7058 are connected to the driver TFT 7001 through contact holes formed therein. The cathode 7003 is connected to the ground electrode. 9, the drain electrode of the driving TFT 7001 is electrically connected to the drain electrode of the driving TFT 7001 through a contact hole formed in the is connected to

[0356] In addition, various materials can be used for the cathode 7003, but a material with a relatively small work function is preferable. Materials, specifically, alkali metals such as Li and Cs, and arsenic such as Mg, Ca, and Sr. In addition to alkaline earth metals and alloys containing them (Mg:Ag, Al:Li, etc.), Yb and Rare earth metals such as Er are preferred.

[0357] The periphery of the cathode 7003 is covered with a partition 7009. The partition 7009 is made of polyimide, alumina, Organic resin films such as acrylic resin, polyamide, and epoxy resin, inorganic insulating films, and organic polysiloxanes The partition wall 7009 is formed by using a photosensitive resin material, and the cathode 7003 is formed by using a photosensitive resin material. An opening is formed on the top, and the side wall of the opening becomes an inclined surface formed with a continuous curvature. In the case where a photosensitive resin material is used for the partition wall 7009, The step of forming a resist mask can be omitted.

[0358] In addition, the EL layer 7004 formed on the cathode 7003 and the partition wall 7009 is composed of a single layer. The EL layer 70 may be formed by laminating a plurality of layers. When the cathode 7003 is composed of multiple layers, an electron injection layer, an electron transport layer, a light emitting layer, and a The layer, the hole transport layer, and the hole injection layer are laminated in this order. There is no need to set

[0359] The stacking order is not limited to the above, and a hole injection layer, a hole transport layer, and a light emitting layer may be stacked on the cathode 7003. The cathode 700 may be laminated in this order, the electron transport layer, and the electron injection layer. 3 will function as the anode.

[0360] In FIG. 17(C), a hole injection was performed on a laminated film in which a Ti film, an aluminum film, and a Ti film were laminated in this order. The dopant layer, hole transport layer, light emitting layer, electron transport layer, and electron injection layer are laminated in that order, and Mg:A A laminate of a g-alloy thin film and an ITO film is formed.

[0361] However, when comparing power consumption, the cathode 7003 is provided with an electron injection layer, an electron transport layer, a light emitting layer, It is preferable to laminate the hole transport layer and the hole injection layer in this order, since this reduces power consumption.

[0362] The anode 7005 is formed using a conductive material that transmits light, such as titanium oxide. Indium oxide with tungsten oxide, indium zinc oxide with tungsten oxide, Indium oxide containing titanium, indium tin oxide containing titanium oxide, indium stannate Indium tin oxide with added silicon oxide, indium zinc oxide, A conductive film having such a structure may be used.

[0363] The region where the EL layer 7004 is sandwiched between the cathode 7003 and the anode 7005 constitutes the light emitting element 7002. In the case of the pixel shown in FIG. 17C, the light emitted from the light emitting element 7002 is The light is emitted toward the anode 7005 as indicated by the mark.

[0364] In FIG. 17C, the drain electrode of the TFT 7001 is formed by insulating layers 7057 and 70 58, 7059 are electrically connected to the cathode 7003 through contact holes formed therein. The planarization insulating layer 7053 is made of polyimide, acrylic resin, benzocyclobutene resin, poly Resin materials such as polyamide and epoxy resins can be used. Low dielectric constant materials (low-k materials), siloxane resins, PSG (phosphorus glass), BPSG (phosphorus boron glass) and the like can be used. Note that insulating films formed from these materials can be used. The planarization insulating layer 7053 may be formed by stacking a plurality of the planarization insulating layers 705. The method for forming the layer 3 is not particularly limited, and may be a sputtering method, a SOG method, a spin coating method, or the like, depending on the material. Dipping, spray coating, droplet ejection method (inkjet method, screen printing, offset printing Printing, etc.), doctor knife, roll coater, curtain coater, knife coater, etc. In addition, an insulating layer 7055 can be provided over the planarization insulating layer 7053. preferable.

[0365] In addition, a partition wall 7009 is provided to insulate the cathode 7003 from the cathode of an adjacent pixel. The partition wall 7009 is made of an organic resin film such as polyimide, acrylic resin, polyamide, or epoxy resin. The partition wall 7009 is formed using an inorganic insulating film or an organic polysiloxane. An opening is formed on the cathode 7003 using the resin material, and the side wall of the opening has a continuous curvature. It is preferable to form the partition wall 7009 so as to have an inclined surface having a slope. When a photosensitive resin material is used, the step of forming a resist mask can be omitted.

[0366] In the structure of FIG. 17C, when a full-color display is performed, for example, the light-emitting element 70 02 is a green light emitting element, one adjacent light emitting element is a red light emitting element, and the other The light-emitting element is a blue light-emitting element. In addition to the three types of light-emitting elements, a white element is also added, making a total of four. A light-emitting display device capable of full-color display may be manufactured using a variety of light-emitting elements.

[0367] In the structure of FIG. 17(C), all the light emitting elements are white light emitting elements. A sealing substrate having a color filter or the like is disposed above the light emitting element 7002. A light-emitting display device capable of full color display may be manufactured. By forming a material and combining it with a color filter and a color conversion layer, a full color display is achieved. It is possible.

[0368] Of course, a single-color display may be used. For example, a lighting device may be formed using white light. Alternatively, monochromatic light may be used to form an area color type light emitting device.

[0369] If necessary, an optical film such as a polarizing film, eg, a circular polarizing plate, may be provided.

[0370] Although the organic EL element has been described as the light-emitting element here, inorganic EL elements can also be used as the light-emitting element. It is also possible to provide an L element.

[0371] In addition, the thin film transistor (driving TFT) that controls the driving of the light-emitting element and the light-emitting element are electrically However, a current control TFT is connected between the driving TFT and the light emitting element. The configuration may be such that the input / output terminals are connected to each other.

[0372] In addition, the present invention can be applied to a liquid crystal display device as long as the device does not include a light emitting element and a partition wall. The case of a liquid crystal display device is shown in FIG.

[0373] The case where the driving TFT 7061 is an n-type is shown. A light-transmitting conductive film 7067 is provided on the substrate. An insulating layer 7071 is formed on the gate electrode of the driving TFT 7061, and an insulating layer 7072 is formed on the gate electrode of the driving TFT 7061. An insulating layer 7076 is formed on the source electrode and the drain electrode of the driving TFT 7061. Insulating layers 7077, 7078, and 7079 are formed on the insulating layers 7077, 707 On the insulating layer 708, a source wiring 7068a and a source wiring 7068b are formed. 78 and the insulating layer 7077 through contact holes formed in the driving TFT 7061. The light-transmitting conductive film 7067 is connected to the source electrode. 78, 7079 are connected to the drain of the driving TFT 7061 through contact holes formed therein. It is electrically connected to the electrode.

[0374] The light-transmitting conductive film 7067 can be formed using indium oxide containing tungsten oxide, Indium zinc oxide with tungsten oxide, indium oxide with titanium oxide, Indium tin oxide containing titanium, indium tin oxide (hereinafter referred to as ITO), Conductive materials with optical transparency such as indium zinc oxide and indium tin oxide doped with silicon oxide A membrane may be used.

[0375] In FIG. 37, the light emitted from the backlight passes through the color filter layer 7063. The color filter layer 7063 is formed by a droplet discharge method such as an ink-jet method. They are formed by a printing method, an etching method using photolithography technology, or the like.

[0376] The color filter layer 7063 is covered with an overcoat layer 7064, which is a protective insulating layer. In FIG. 37, the overcoat layer 7064 is thin. As shown in the figure, the overcoat layer 7064 covers the unevenness caused by the color filter layer 7063. It has a flattening function.

[0377] Furthermore, by providing a liquid crystal layer over the conductive film 7067 having a light-transmitting property, can also be applied.

[0378] Next, the appearance and structure of a light-emitting display panel (also called a light-emitting panel) which corresponds to one embodiment of a semiconductor device will be described. The cross section will be described with reference to FIG. 15. FIG. 15(A) shows a thin film formed on a first substrate. A panel in which the film transistor and the light emitting element are sealed between the second substrate and the film transistor and the light emitting element by a sealant. 15(B) is a plan view of the above-mentioned embodiment, and FIG. 15(B) is a cross-sectional view taken along line HI of FIG. 15(A).

[0379] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504 are provided on a first substrate 4501. A sealant 4505 is formed to surround the gate driver circuits 4504a and 4504b. In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 45 4504a and 4504b are a first substrate 4501, a sealant 4505, and a second substrate 4506. The filling material 4507 is sealed with the sealing material 4507. Highly sealed protective film with little outgassing (lamination film, UV curable resin film) It is preferable to package (enclose) the package in a material such as a film or a cover material.

[0380] A pixel portion 4502, a signal line driver circuit 4503a, and a fourth 503b and the scanning line driver circuits 4504a and 4504b each have a plurality of thin film transistors. In FIG. 15B, a thin film transistor 4510 included in a pixel portion 4502 and a signal A thin film transistor 4509 included in the signal line driver circuit 4503a is illustrated. Insulating layers 4541, 4542, and 4543 are provided on the transistors 4509 and 4510. In addition, an insulating layer 4544 is provided over the thin film transistor 4510. An insulating layer 4545 is provided over a first substrate 4501, and a gate electrode layer of a thin film transistor An insulating layer 4546 and an insulating layer 4547 are provided on the insulating layer 4542. A source wiring 4548 is provided, and a thin film formed in the insulating layer 4541 and the insulating layer 4542 is formed. A source electrode layer or a drain electrode layer of the thin film transistor 4510 is connected through a contact hole. It is connected to the polar layer.

[0381] The thin film transistors 4509 and 4510 are made of the oxide semiconductor layer described in any of Embodiments 1 to 3. A highly reliable thin film transistor including a semiconductor layer can be applied. In this embodiment, the thin film transistors 4509 and 4510 are n-channel thin film transistors.

[0382] The oxide semiconductor layer of the thin film transistor 4509 for the driver circuit is A conductive layer 4540 is provided in a position overlapping with the channel formation region. By providing the gate insulating film at a position overlapping the channel formation region of the nitride semiconductor layer, In addition, the amount of change in the threshold voltage of the thin film transistor 4509 can be reduced. The conductive layer 4540 may have the same potential as the gate electrode layer of the thin film transistor 4509. The conductive layer may be different from the first gate electrode layer and may function as the second gate electrode layer. The potential of 4540 may be GND, 0V, or may be in a floating state.

[0383] The thin film transistors 4509 and 4510 are semiconductor transistors including a channel formation region as a protective insulating film. An insulating layer 4541 is formed in contact with the body layer. The insulating layer 208 may be formed using the same material and method as the insulating layer 208. In order to reduce surface unevenness, the thin film transistor is formed with the insulating layer 4544, which functions as a planarizing insulating film. Here, the insulating layer 4541 is formed by covering the insulating layer 4510. Similarly to the insulating layer 208, a silicon oxide film is formed by sputtering.

[0384] In addition, an insulating layer 4544 is formed as a planarization insulating film. The insulating layer 4021 may be formed using the same material and method as the insulating layer 4021 described in the seventh embodiment. The layer 4544 is made of acrylic resin.

[0385] In addition, 4511 corresponds to a light-emitting element, and a first electrode which is a pixel electrode of the light-emitting element 4511 is The layer 4517 is electrically connected to the source electrode or the drain electrode of the thin film transistor 4510. The light emitting element 4511 is configured with a first electrode layer 4517, an electroluminescent layer 45 12, the second electrode layer 4513 has a stacked structure, but is not limited to the structure shown in this embodiment mode. The configuration of the light emitting element 4511 is determined according to the direction of the light to be extracted from the light emitting element 4511. can be changed appropriately.

[0386] The partition 4520 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. In particular, a photosensitive material is used to form an opening on the first electrode layer 4517, and the sidewall of the opening It is preferable that the inclined surface is formed so as to have a continuous curvature.

[0387] The electroluminescent layer 4512 may be composed of a single layer or a plurality of layers may be laminated. It doesn't matter whether it is done or not.

[0388] In order to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4511, the second electrode layer A protective film may be formed on the partition wall 4513 and the partition wall 4520. The protective film may be a silicon nitride film, A silicon oxynitride film, DLC film, etc. can be formed.

[0389] In addition, signal line driver circuits 4503a and 4503b, scanning line driver circuits 4504a and 4504b Various signals and potentials applied to the pixel portion 4502 are It is supplied by b.

[0390] The connection terminal electrode 4515 is formed of the same conductive film as the first electrode layer 4517 of the light-emitting element 4511. The terminal electrode 4516 is formed from the source of the thin film transistors 4509 and 4510. The source electrode and the drain electrode are formed from the same conductive film.

[0391] The connection terminal electrode 4515 is connected to the terminal of the FPC 4518a via the anisotropic conductive film 4519. The electrodes are electrically connected to each other.

[0392] The second substrate located in the direction in which light is extracted from the light emitting element 4511 must be transparent. In that case, use a glass plate, a plastic plate, a polyester film or an acrylic plate. A light-transmitting material such as a film is used.

[0393] In addition, filler 4507 can be inert gas such as nitrogen or argon, or ultraviolet-curing resin. It can be made of resin or thermosetting resin, and is suitable for PVC (polyvinyl chloride), acrylic resin, etc. Epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (copolymer of ethylene and vinyl acetate) can be used. For example, filler Nitrogen may be used as the oxygen source.

[0394] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, the polarizing plate or the circular polarizing plate may be provided with an anti-reflection film. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0395] The signal line driver circuits 4503a and 4503b and the scanning line driver circuits 4504a and 4504b are A driving circuit formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate is Also, only the signal line driver circuit, or a part of it, or the scanning line driver circuit may be mounted. Only the operating circuit or only a part of it may be separately formed and mounted, and the configuration is not limited to that of FIG. I can't.

[0396] Through the above steps, a highly reliable light-emitting display device (display panel) can be manufactured as a semiconductor device. It is possible.

[0397] The light-emitting display device is manufactured using the display device described in any of Embodiments 1 to 5. This allows the gate wiring and source wiring to be formed from a conductive material containing Cu, It is possible to prevent an increase in wiring resistance, thereby enabling the light emitting display device to operate at a high speed and with low power consumption. Therefore, it is possible to provide a light-emitting display device that can accommodate a large screen and a high-definition screen. This can be done.

[0398] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0399] (Embodiment 10) The semiconductor device disclosed in this specification can be applied as electronic paper. Par can be used in any electronic device that displays information. For example, electronic paper can be used for electronic books, posters, train rides, etc. It can be used for in-car advertising, display on various cards such as credit cards, etc. An example of the electronic device is shown in Fig. 24 and Fig. 25.

[0400] FIG. 24(A) shows a poster 2631 made of electronic paper. When the advertisements are printed on paper, they are replaced manually. You can change the display of your ad in a short time. Also, the display is stable and the image does not collapse. The poster may be configured to transmit and receive information wirelessly.

[0401] A poster 2631 is manufactured using the display device described in any of the embodiments 1 to 5. This allows the gate wiring and source wiring to be formed from a conductive material containing Cu, It is possible to prevent an increase in wiring resistance, thereby enabling the display device to operate at a high speed and with low power consumption. Therefore, it is possible to provide a poster 2631 that can be used on a large screen and a high-definition screen. This can be done.

[0402] FIG. 24B shows an advertisement 2632 on a train or other vehicle. When using printed paper, advertisements are replaced manually, but with electronic paper, This allows you to change the display of your ads in a short time without a lot of manual labor. The in-car advertisement system is structured to transmit and receive information wirelessly. It is also possible to use the following.

[0403] An in-vehicle advertisement 2632 can be produced using the display device shown in any one of the first to fifth embodiments. This allows the gate wiring and source wiring to be formed from a conductive material containing Cu, It is possible to prevent an increase in wiring resistance, thereby enabling the display device to operate at a high speed and with low power consumption. Therefore, it is possible to provide an in-car advertisement 2632 that can be used on a large screen and a high-definition screen. This can be done.

[0404] FIG. 25 shows an example of an electronic book. For example, an electronic book 2700 includes a housing 2701 and The housing 2701 and the housing 2703 are The device is integrated with an axis portion 2711, and can be opened and closed with the axis portion 2711 as an axis. This configuration makes it possible to operate like a paper book.

[0405] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a text is displayed on the right display (display 2705 in FIG. 25) and An image can be displayed on the display unit 2707 in FIG.

[0406] FIG. 25 shows an example in which the housing 2701 is provided with an operation unit. 701, a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. The configuration may include a display board, a pointing device, etc. On the front side, there is a terminal for external connection (earphone terminal, USB terminal, or AC adapter and USB cable). A terminal that can be connected to various cables such as a USB cable, a recording medium insertion section, etc. Furthermore, the electronic book 2700 may be configured to have a function as an electronic dictionary. Good too.

[0407] The electronic book 2700 may be configured to transmit and receive information wirelessly. The desired book data can be purchased and downloaded from the electronic book server. is also possible.

[0408] (Embodiment 11) The semiconductor device disclosed in this specification can be applied to various electronic devices (including game machines). The electronic device can be, for example, a television device (television or television receivers), computer monitors, digital cameras and digital video cameras cameras, digital photo frames, mobile phones (also called mobile phones or mobile phone devices), (c) Portable game machines, personal digital assistants, audio playback devices, large game machines such as pachinko machines, etc. Some examples include:

[0409] FIG. 26A shows an example of a television device. The television device 9600 includes: A display unit 9603 is incorporated in a housing 9601. The display unit 9603 displays images. In this embodiment, the housing 9601 is supported by a stand 9605. The figure shows a configuration in which

[0410] The television device 9600 can be operated using an operation switch provided on the housing 9601 or a separate remote control. This can be done by the remote control operation device 9610. The channel and volume can be controlled by the 9609, and the display 9603 shows In addition, the remote control unit 9610 can control the video. A display portion 9607 for displaying information output from 9610 may be provided.

[0411] The television device 9600 includes a receiver and a modem. It can receive more general television broadcasts, and can also be connected to a modem via wired or wireless connection. By connecting to a network, communication can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0412] A television set 9600 is manufactured using the display device described in any of Embodiments 1 to 5. By doing so, the gate wiring and the source wiring can be formed of a conductive material containing Cu. Therefore, an increase in wiring resistance can be prevented. Since it is possible to use electricity, it is possible to make a television device 96 that can accommodate a large screen and a high-definition screen. 00 can be provided.

[0413] FIG. 26B shows an example of a digital photo frame. In the frame 9700, a display unit 9703 is incorporated in a housing 9701. 3 is capable of displaying various images, for example images taken with a digital camera. By displaying data, it can function just like a normal photo frame.

[0414] The Digital Photo Frame 9700 is equipped with an operation unit, external connection terminals (USB terminal, US A terminal that can be connected to various cables such as B cable, etc., and a recording medium insertion section, etc. These components may be installed on the same surface as the display unit, but they may be installed on the side or back. It is preferable to have a digital photo frame with a built-in memory card because it improves the design. A memory that stores image data taken with a digital camera is inserted into the body insertion section. The captured image data can be displayed on the display portion 9703 .

[0415] The digital photo frame 9700 may also be configured to transmit and receive information wirelessly. It is also possible to wirelessly import and display desired image data.

[0416] FIG. 27(A) shows a portable gaming machine, which is composed of two housings, a housing 9881 and a housing 9891. The housing 9881 is connected to a connector 9893 so as to be openable and closable. A display unit 9883 is incorporated in the housing 9891. The portable gaming machine shown in FIG. 27(A) also includes a speaker unit 9884 and a recording medium insertion unit 988. 6, LED lamp 9890, input means (operation keys 9885, connection terminals 9887, sensors 9 888 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, Chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration 9889) equipped with a microphone, etc. Of course, the configuration of the portable gaming machine is not limited to the above, and may be at least as described in the present specification. The present invention is not limited to the above, and may be applied to any configuration having the semiconductor device disclosed in the above and other auxiliary equipment. The portable game machine shown in FIG. 27(A) can be used to play a game recorded on a recording medium. The function of reading out the program or data and displaying it on the display unit, and wireless communication with other portable gaming machines The portable gaming machine shown in FIG. 27(A) has the following functions: The functions are not limited to these, and various functions can be provided.

[0417] FIG. 27(B) shows an example of a slot machine, which is a large gaming machine. Slot Machine 9 The slot machine 900 includes a display unit 9903 built into a housing 9901. 900 also includes other operating means such as a start lever and stop switch, a coin slot, Of course, the configuration of the slot machine 9900 is not limited to the above. However, the present invention is not limited to the above, and may be configured to include at least the semiconductor device disclosed in the present specification. The configuration may include appropriate auxiliary equipment.

[0418] FIG. 28A is a perspective view showing an example of a portable computer.

[0419] The portable computer of FIG. 28(A) has an upper housing 9301 and a lower housing 9302 connected to each other. The hinge unit is closed to form an upper housing 9301 having a display unit 9303 and a keyboard. The lower housing 9302 having the base 9304 can be stacked on top of each other, making it easy to carry. This is convenient, and when the user wants to type on the keyboard, the hinge unit needs to be opened. The user can perform input operations by looking at the display portion 9303.

[0420] The lower housing 9302 also includes a keyboard 9304 and a pointing device for inputting data. If the display portion 9303 is a touch input panel, Input operations can be performed by touching the touch panel. The lower housing 9302 has a computing function unit such as a hard disk. It has an external connection port 9305 into which a communication cable conforming to the USB communication standard is inserted. There are.

[0421] The upper housing 9301 further includes a display unit 93 that can be slid and stored inside the upper housing 9301. 07, it is possible to realize a wide display screen. The orientation of the screen of the 9307 can be adjusted by the user. If it is a panel, input operations can be performed by touching a part of the retractable display unit.

[0422] The display unit 9303 or the foldable display unit 9307 may be a liquid crystal display panel, an organic light emitting element, or The display device uses an image display device such as a light-emitting display panel using inorganic light-emitting elements.

[0423] The portable computer shown in FIG. 28A is configured with a receiver and the like, and is also a television. It is possible to receive broadcasts and display images on the display unit. The display unit 9307 is slid while the hinge unit connecting the display unit 9302 to the display body 9302 is kept in the closed state. By adjusting the screen angle, the user can watch TV broadcasts. In this case, the hinge unit is opened to prevent the display unit 9303 from displaying anything. Since the system only activates the circuits that display the TV broadcast, power consumption is kept to a minimum. This is useful in portable computers where battery capacity is limited.

[0424] FIG. 28(B) shows a portable electronic device that can be worn on the user's arm like a wristwatch. FIG. 13 is a perspective view showing an example of a story.

[0425] This mobile phone is a main body having at least a communication device having a telephone function and a battery. A band part 9204 for attaching the body to the arm, and a fastening state of the band part 9204 to the arm are adjusted. The device is made up of an adjustment unit 9205 for adjusting the temperature, a display unit 9201, a speaker 9207, and a microphone 9208. It has been made.

[0426] The main body also has an operation switch 9203, which serves as a power input switch and a display switching switch. In addition to the camera switch and the camera start switch, there are also other buttons, such as a button that starts an Internet program. Each function can be associated with a specific function, such as being started.

[0427] Input operations of this mobile phone are performed by touching the display portion 9201 with a finger or an input pen, or by operating the mobile phone. This is done by operating a switch 9203 or by inputting voice into a microphone 9208. 28(B) shows a display button 9202 displayed on a display unit 9201. Input can be made by touching the screen with a finger or other object.

[0428] The main body also includes an imaging device that converts the subject image formed through the photographic lens into an electronic image signal. The camera unit 9206 has a step. Note that the camera unit does not necessarily have to be provided.

[0429] The mobile phone shown in FIG. 28(B) is configured with a television broadcast receiver, etc. It can receive TV broadcasts and display the images on the display unit 9201, and can also store data in a memory or the like. As a configuration equipped with a storage device, television broadcasts can be recorded in the memory. The mobile phone shown in FIG. 2 may have a function for collecting location information such as GPS.

[0430] The display unit 9201 is a light-emitting display panel such as a liquid crystal display panel, an organic light-emitting element, or an inorganic light-emitting element. The mobile phone shown in FIG. 28(B) is small and lightweight. Therefore, the battery capacity is limited, and the display device used for the display portion 9201 is a low-power display device. It is preferable to use a force actuable panel.

[0431] Although FIG. 28B illustrates an electronic device that is worn on the arm, the electronic device is not limited to this. It is sufficient that the device has a shape that can be carried around.

[0432] (Embodiment 12) In this embodiment mode, the thin film transistor described in Embodiment 1 is used as one mode of a semiconductor device. An example of a display device having a display element will be described with reference to FIGS. An example of a liquid crystal display device using a liquid crystal element will now be described with reference to FIGS. The TFTs 628 and 629 used in the liquid crystal display device of FIG. The thin film transistor shown in the embodiment 2 can be applied, and the process shown in the embodiment 2 can be performed in the same manner. It is a thin-film transistor with excellent electrical characteristics and high reliability that can be fabricated. Reference numeral 629 denotes a thin film transistor in which an oxide semiconductor layer is used as a channel formation region. In FIG. 32, the thin film transistor shown in FIG. 1 is used as an example of the thin film transistor. However, the present invention is not limited to this.

[0433] This section describes a VA (Vertical Alignment) type liquid crystal display device. A liquid crystal display device is a type of device that controls the alignment of liquid crystal molecules in a liquid crystal display panel. In A-type liquid crystal display devices, the liquid crystal molecules are aligned perpendicular to the panel surface when no voltage is applied. In this embodiment, pixels are divided into several regions. The device is designed to split the molecules into small pixels (subpixels) and tilt them in different directions. This is called domainization or multi-domain design. In the following explanation, multi-domain design is The liquid crystal display device under consideration will now be described.

[0434] 30 and 31 show a pixel electrode and a counter electrode, respectively. FIG. 2 is a plan view of the substrate side on which electrodes are formed, showing a cross-sectional structure corresponding to a cutting line EF shown in the figure. FIG. 29 shows the same. FIG. 31 shows a plan view of the substrate on which the counter electrode is formed. The following description will be given with reference to these figures.

[0435] FIG. 29 shows a TFT 628, a pixel electrode layer 624 connected thereto, and a storage capacitor 630. The substrate 600 on which the counter electrode layer 640 and the like are formed is laminated on the counter substrate 601. 4 shows the state in which liquid crystal has been injected.

[0436] A colored film 636 and a counter electrode layer 640 are formed on the counter substrate 601. A protrusion 644 for controlling the alignment of the liquid crystal is formed on the counter electrode layer 640. The height of the upper protrusion 644 and the height of the spacer (not shown) are different. An alignment film 648 is formed on the counter electrode layer 640, and an alignment film 646 is formed on the counter electrode layer 640. A liquid crystal layer 650 is formed between them.

[0437] The spacers may be columnar spacers or bead spacers. The spacers may be formed on a pixel electrode layer 624 formed on a substrate 600 .

[0438] On the substrate 600 on which the insulating layer 661 is formed, a TFT 628 and a pixel electrode layer connected thereto are The pixel electrode layer 624 includes a TFT 628, a storage capacitor 630, and a An insulating layer 664 covers the wiring 616 and the storage capacitor 630, and an insulating layer 66 on the insulating layer 664 5. The insulating layer 666 on the insulating layer 665 and the insulating layer 622 on the insulating layer 666 are respectively penetrated. The source is connected to the wiring 618 through a contact hole 623. A source wiring 616 is formed by laminating a wiring 616a and a source wiring 616b. Through contact holes formed in the insulating layer 665 and the insulating layer 664, The TFT 628 is connected to the source electrode layer or the drain electrode layer. The thin film transistor shown in embodiment 1 can be used appropriately.

[0439] The storage capacitor 630 is a first capacitor formed at the same time as the gate wiring 602 of the TFT 628. A capacitance wiring 604 which is a capacitance wiring, an insulating layer 662 and an insulating layer 663 on the gate wiring 602, The second capacitance wiring 617 is formed at the same time as the wiring 618. The gate wiring 602 is a laminate of gate wirings 602a and 602b. The line 604 and the line 60b function as a gate electrode layer of the TFT 628. It is a stack of 4a and 604b.

[0440] The pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640 are overlapped to form a liquid crystal element. It has been made.

[0441] FIG. 30 shows a structure on a substrate 600. The pixel electrode layer 624 is made of the material shown in the embodiment mode 1. The pixel electrode layer 624 is provided with a slit 625. is for controlling the alignment of the liquid crystal.

[0442] The TFT 629 and the pixel electrode layer 626 and the storage capacitor 631 connected thereto shown in FIG. The TFT 628, the pixel electrode layer 624, and the storage capacitor portion 630 can be formed in the same manner. In addition, the capacitance wiring 605 forming the storage capacitance portion 631 can be formed in the same manner as the capacitance wiring 604. The capacitor wirings 605a and 605b are stacked. The source wiring 616 and the gate wiring 602 are connected to the pixels of this liquid crystal display panel. The pixel is composed of a pixel electrode layer 624 and a pixel electrode layer 626. 24 and the pixel electrode layer 626 are sub-pixels.

[0443] The structure on the opposing substrate side is shown in FIG. 31. The opposing electrode layer 640 is made of the same material as the pixel electrode layer 624. On the counter electrode layer 640, protrusions 6 for controlling the alignment of liquid crystal are preferably formed. 44 has been formed.

[0444] The equivalent circuit of this pixel structure is shown in Figure 32. TFT628 and TFT629 both have gate The line 602 is connected to the source line 616. In this case, the capacitance line 604 and the capacitance line 60 By making the potentials of the liquid crystal elements 651 and 652 different from each other, the operation of the liquid crystal elements 651 and 652 can be made different from each other. That is, by individually controlling the potentials of the capacitance wiring 604 and the capacitance wiring 605, The orientation of the liquid crystal is precisely controlled to widen the viewing angle.

[0445] When a voltage is applied to the pixel electrode layer 624 having the slit 625, The slit 625 and the protrusion on the opposing substrate 601 side cause distortion of the electric field (diagonal electric field). By arranging the 644 in an alternating pattern, a diagonal electric field is effectively generated, and the liquid crystal By controlling the orientation, the direction in which the liquid crystal is oriented can be made to differ depending on the location. The viewing angle of the LCD panel is expanded by creating a multi-domain structure.

[0446] Next, a VA type liquid crystal display device different from the above will be described with reference to FIGS. 33 to 36. In the configuration of the invention described below, the same parts as those of the above-mentioned VA type liquid crystal display device are used. Or, the same reference numerals are used in different drawings for parts having similar functions, and the repetition of such reference numerals will not be used in the drawings. The explanation of this will be omitted.

[0447] 33 and 34 show the pixel structure of a VA type liquid crystal display panel. FIG. 33 shows a cross-sectional structure corresponding to the cutting line YZ shown in the figure. The following description will refer to both figures.

[0448] In this pixel structure, one pixel has multiple pixel electrodes, each of which is connected to a TFT. Each TFT is configured to be driven by a different gate signal. That is, in a pixel with a multi-domain design, the signals applied to each pixel electrode are independent. The device has a configuration for controlling the above.

[0449] The pixel electrode layer 624 is connected to the TFT 628 through the contact hole 623 by the wiring 618. The pixel electrode layer 626 is connected to the wiring 619 through the contact hole 627. The gate wiring 602 of the TFT 628 and the gate The gate wiring 603 is separated so that different gate signals can be applied. On the other hand, the source wiring 616 functioning as a data line is formed in the insulating layer 664 and the insulating layer 665. The source electrode layers of the TFT628 and the TFT629 are connected through the contact holes. , which is commonly used in the TFT628 and TFT629. The thin film transistor described in the embodiment mode 1 can be used as appropriate. In addition, as in the pixel structure of the above-mentioned VA type liquid crystal display panel, the gate wiring 602 is a stack of gate wirings 602a and 602b, and gate wiring 603 is a gate wiring 6 The source wiring 616 is a stack of source wirings 616a and 616b. The insulating layer 6 is a laminate of the capacitance wiring 690a and the capacitance wiring 690b. The insulating layer 61 to the insulating layer 666 are also formed in the same manner as the pixel structure of the above-mentioned VA type liquid crystal display panel.

[0450] The pixel electrode layer 624 and the pixel electrode layer 626 have different shapes and are separated by a slit 625. The pixel electrode layer 626 is arranged so as to surround the outside of the pixel electrode layer 624 that spreads in a V shape. The timing of applying voltages to the pixel electrode layer 624 and the pixel electrode layer 626 is set as follows: The alignment of the liquid crystal is controlled by varying the TFT 628 and the TFT 629. The equivalent circuit of this pixel structure is shown in FIG. T629 is connected to the gate wiring 603. The gate wiring 602 and the gate wiring 603 are different. By applying different gate signals, the operation timing of TFT628 and TFT629 can be made different. It is possible to do so.

[0451] A colored film 636 and a counter electrode layer 640 are formed on the counter substrate 601. A flattening film 637 is formed between the electrode layer 636 and the counter electrode layer 640 to prevent the alignment of the liquid crystal from being disturbed. FIG. 35 shows the structure of the opposing substrate side. The opposing electrode layer 640 is shared between different pixels. The electrode is connected to the pixel electrode, but a slit 641 is formed therein. The polar layer 624 and the slits 625 on the pixel electrode layer 626 side are arranged so as to interdigitate with each other. This makes it possible to effectively generate an oblique electric field and control the alignment of the liquid crystal. The orientation direction of the liquid crystal can be made to vary depending on the location, thereby widening the viewing angle.

[0452] The pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640 shown in FIG. A liquid crystal element 651 shown in FIG. 36 is formed. In addition, the pixel electrode layer 626 shown in FIG. The liquid crystal layer 650 and the counter electrode layer 640 are overlapped to form a liquid crystal element 652 as shown in FIG. In addition, a multi-domain liquid crystal display device is formed in which a liquid crystal element 651 and a liquid crystal element 652 are provided in one pixel. It is an in-structure.

[0453] By using the display device shown in any one of the first to fifth embodiments, the above-mentioned liquid crystal display It is possible to fabricate a display device using VA (Vertical Alignment) Although the liquid crystal display device of the type has been described, the present embodiment is not limited to this. For example, a liquid crystal is driven by applying an electric field horizontally to the liquid crystal molecules in the cell to express gradation. In-plane switching type liquid crystal display devices (such as IPS type liquid crystal display devices) and TN type liquid crystal display devices It may also be a device.

[0454] The liquid crystal display device is manufactured using the display device described in any of Embodiments 1 to 5. This allows the gate wiring and source wiring to be formed from a conductive material containing Cu, It is possible to prevent an increase in wiring resistance, thereby achieving high speed and low power consumption of the display device. Therefore, it is possible to provide a liquid crystal display device that can accommodate a large screen and a high-definition screen. do.

[0455] (Embodiment 13) In this embodiment, a first substrate having a thin film transistor and a second substrate serving as an opposing substrate are An example of manufacturing a display panel in which the above is bonded together will be described below.

[0456] In the production process of LCD panels and EL display panels, static electricity can affect electronic circuits and cause electrical Static electricity can also cause dust to adhere to the product. There are some problems that become easier.

[0457] In particular, when an insulating substrate is used, it is easy to become charged with static electricity. It is made of a soft material such as glass or resin.

[0458] Static electricity occurs when two objects are rubbed, touched, or separated, causing one object to become positively charged and the other This refers to the charge in which one object is negatively charged. When electrons move between two objects due to friction, etc. The phenomenon in which electric charges are generated is called electrification. When electrification occurs, if the material of the object is an insulator, The generated charge does not flow and accumulates as static electricity.

[0459] In addition, a thin film transistor using an oxide semiconductor layer is susceptible to static electricity. There is a risk that the electrical characteristics of the capacitor will fluctuate and deviate from the design range.

[0460] Therefore, a first substrate having a thin film transistor and a second substrate serving as an opposing substrate are bonded together. After the thin film transistor is grounded, the static electricity stored in the thin film transistor is discharged to the ground side, and the amount of charge is gradually attenuated. The heat treatment is carried out in such a state that the odor is easily eliminated. At least one of the heating processes performed during panel production serves as the heat treatment. This makes it possible to reduce the amount of static electricity without increasing the number of steps.

[0461] The manufacturing method of a liquid crystal display panel will be described below with reference to FIG.

[0462] First, a thin film transistor 710 having an oxide semiconductor layer and a pixel A first substrate 701 having an electrode 730 formed thereon is prepared. The driver circuit is mounted on the same substrate, and the TFT711 in the driver circuit is also a thin-film transistor. The TFT 711 of the driving circuit is fabricated in the same process as the TFT 710. The conductive layer 740 is formed of the same material as the pixel electrode 730. It has been made.

[0463] After the pixel electrodes are formed, they are washed and dried at 150°C for 2 minutes. Then, an alignment film is formed. The alignment film is formed by applying a liquid horizontal alignment film by offset printing or screen printing. A film-forming material (or a vertical alignment film-forming material), such as polyimide, is selectively applied and baked. After pre-baking on a hot plate at 80℃ for 2 minutes, Baked in an oven at 230℃ for 40 minutes. After baking, rubbed and then washed. Then dry at 150°C for 2 minutes.

[0464] In addition, a color filter, an alignment film, a sealant, etc. are formed on the second substrate 706 which is the opposing substrate. The process for carrying out the above is shown below.

[0465] First, a black resin layer pattern that will become a black matrix is ​​formed on the second substrate 706. Then, a green resin layer pattern, a blue resin layer pattern, and a red resin layer pattern are formed. The green resin layer pattern, the blue resin layer pattern, and the red resin layer pattern are color filters. Then, an overcoat layer is formed to cover these resin layer patterns.

[0466] Next, a silicon oxide doped indium tin oxide film was sputtered onto the overcoat layer. In order to reduce the resistance of the counter electrode 731, the counter electrode 731 is heated at 250° C. for 1 Heat for an hour.

[0467] Next, a columnar spacer 735 is formed on the counter electrode 731. The columnar spacer 735 is , which is obtained by selectively etching an organic resin film such as an acrylic resin film.

[0468] Then, the film is washed and dried at 150° C. for 2 minutes. Then, the film is oriented on the spacer 735. The alignment film is formed by printing a liquid film using offset printing or screen printing. A horizontal alignment film forming material (or a vertical alignment film forming material), such as polyimide, is selectively applied. After pre-baking for 2 minutes at 80°C on a hot plate, The film is baked in a clean oven at 230°C for 40 minutes. After baking, the film is rubbed. After that, it is washed and dried at 150℃ for 2 minutes.

[0469] The sheet is then printed using a screen printing method, an inkjet device, or a dispensing device. The sealing material may be an acrylic photocurable resin. The material contains filler (diameter 6μm~24μm) and has a viscosity of 40~400 Pa·s. It is preferable to select a sealing material that will not dissolve in the liquid crystal that will come into contact with it later. The sealant forms a closed loop and surrounds the display area.

[0470] Also, the counter electrode 731 and the common connection portion 702 provided on the first substrate are electrically connected. Therefore, the sealing material 704 containing conductive particles is also applied by an inkjet device or a dispenser. The common connection portion 702 is a shield for bonding the first substrate and the second substrate. The conductive particles contained in the sealing material are used to electrically connect the opposing electrode to the sealing material. Or, the common area is connected to the area that does not overlap with the sealing material (excluding the pixel area). A connection portion is provided, and a paste containing conductive particles is provided so as to overlap the common connection portion, and a counter electrode The common connection portion 702 is electrically connected to the pixel electrode 730 and the conductive layer 74. It is made of the same material and in the same process as 0.

[0471] Until the sealing material is formed, the second substrate 706 is protected from elements such as thin film transistors even if it is charged with static electricity. This is not a problem because no sub-layers are formed, but it will be bonded to the first substrate in a later process. It is preferable to reduce the amount of charge on the second substrate 706 before alignment. The amount of charge on the second substrate 706 may be reduced by using a laser or the like, and the counter electrode 731 may be set to a fixed potential. For example, the above-mentioned heat treatment such as sintering may be carried out while electrically connected to a ground potential.

[0472] Next, liquid crystal is dropped onto the alignment film of the second substrate 706. The liquid crystal material is dropped using a liquid crystal display or a dispenser. Not specified, TN LCD, OCB LCD, STN LCD, VA LCD, ECB type LCD, GH LCD, high Molecular dispersion liquid crystal, discotic liquid crystal, etc. can be used.

[0473] Next, the pair of substrates are bonded together under reduced pressure. Then, a first substrate 701 having a thin film transistor 710 is attached to the first substrate 701. Immediately after bonding, the sealant 705 is irradiated with ultraviolet light.

[0474] Next, in order to further harden the sealant 705, the sealant is heated at 80° C. to 200° C. for 0.5 hours. The heat treatment is performed for at least 10 hours and not more than 10 hours. The bonded pair of substrates are then placed in a furnace 780 of a heating device. The furnace 780 was placed on a stainless steel floor electrically connected to the ground potential. Then, a common connection terminal 715 electrically connects to the common connection portion 702. Heating is performed while the external terminal 716, which is connected to the ground potential, is connected. The electrical potential of the connection part 702 is not limited to the ground potential (also called GND), and may be a fixed This heat treatment hardens the sealant 705 and removes the charged At the same time, static electricity can be suitably removed.

[0475] In this embodiment, heating is performed at 120° C. for 1 hour.

[0476] In addition, an enlarged cross-sectional view of the display area during heat treatment while connected to the ground potential is shown in FIG. As shown in FIG. 39(B), a counter electrode 731 electrically connected to a ground potential, A liquid crystal layer 708 is disposed between the thin film transistor 710 and the pixel electrode 730 electrically connected thereto. However, by heating the liquid crystal layer 708, the thin film transistor 710 is charged. The static electricity 790 is discharged to the ground side through the liquid crystal layer 708. The schematic diagram using an equivalent circuit is shown in FIG. 39(C). A path 791 through which static electricity 790 charged in the transistor 710 escapes to the ground side through the liquid crystal layer The static electricity generated by the heat treatment gradually escapes to the ground via a path 791. This makes it easier for the noise to be attenuated and resolved.

[0477] By performing heat treatment with the opposing electrode at ground potential, a normally-off thin-film transistor is produced. This allows stable production of LCD panels, improving the yield of LCD panels. Cut.

[0478] In addition, when producing multiple panels from one substrate, after bonding a pair of substrates, The first substrate is cut using a cutting device such as a scriber, a breaker, or a roll cutter. Or both substrates can be cut. In this way, multiple panels can be made from one substrate. can.

[0479] Next, a heat treatment for aligning the liquid crystal, i.e., a realignment treatment (for example, 80°C to 200°C, 10 The heating is carried out at 100° C. to 170° C. for 10 minutes to 1 hour, preferably at 100° C. to 170° C. for 10 minutes to 1 hour.

[0480] In this embodiment, the realignment treatment is performed at 120° C. for 1 hour. Alternatively, as shown in FIG. 39(A), the heat treatment may be performed with the opposing electrode at ground potential. In this embodiment, the heat treatment for hardening the sealant and the heat treatment for aligning the liquid crystal are performed. Although the above-mentioned example shows that the heat treatment is performed separately, the heat treatment may be performed in the same step.

[0481] Through the above steps, a liquid crystal display panel can be formed.

[0482] In addition, the present invention is not limited to a liquid crystal display device, and may be applied to an electronic pen that drives the electronic ink shown in the eighth embodiment. A heat treatment can be performed on display panels such as LCDs to reduce static electricity. In a state where an electrode provided on a second substrate for sealing the electronic ink is electrically connected to a ground potential, A sealant for fixing the second substrate to the first substrate on which the thin film transistor is provided is hardened. The heat treatment is performed in a state where the electrode provided on the second substrate is at a ground potential. This makes it possible to stably fabricate normally-off thin film transistors, This can improve the yield of active matrix type electronic paper.

[0483] In addition, the present invention is not limited to liquid crystal display devices, and the electroluminescence display panel shown in the ninth embodiment may also be susceptible to static electricity. A heat treatment can be performed to reduce the electrical charge.

[0484] In the case of manufacturing an EL display panel, an oxide semiconductor is formed on a first substrate according to the second embodiment. a first electrode electrically connected to the thin film transistor having a layer covering a periphery of the first electrode; After the partition wall is formed, heating is performed. This heating is performed at 200°C for 1 hour in a nitrogen atmosphere. Then, a heat treatment was performed in a vacuum at 150° C. for 1 hour to form a ferroelectric thin film on the first electrode of the first substrate. A layer containing an organic compound is deposited.

[0485] Next, a second electrode is formed on the layer containing an organic compound by evaporation or sputtering. The second electrode is provided above the thin film transistor in the display area so as to overlap it. The second electrode can also be provided above the thin film transistor of the driving circuit so as to overlap it. When the second electrode is set to a common potential, the second electrode is electrically connected to the ground potential in the subsequent heat treatment. It is preferable to connect the

[0486] Next, a second substrate having a recess in which a desiccant is fixed is fixed to the first substrate with a sealant. In the case of an EL display panel, the temperature must be higher than 80℃. If the heating temperature is too high, the light-emitting element may deteriorate. Therefore, the temperature should be kept at 80℃ for 0.5 hours or more and 10 hours or more. Heat treatment is performed for the following period.

[0487] By performing heat treatment with the second electrode at ground potential, a normally-off thin-film transistor is formed. This allows for stable production of EL display panels, improving the yield rate. can.

[0488] In addition, when sealing the light-emitting element using a thin stainless steel substrate as the second substrate, When adhesive (such as epoxy resin) used to fix stainless steel substrates hardens, The heat treatment is performed while electrically connecting the substrate to the ground potential. In addition to the thin-film transistors in the display area, the thin-film transistors in the driver circuits are formed on the same substrate. All thin-film transistors, including the MOS transistor, are overlapped by a stainless steel substrate, which is a conductive material. Heat treatment is performed with the stainless steel substrate overlapping the transistor at a fixed potential, e.g., ground potential. By doing this, it is possible to stably manufacture a normally-off thin film transistor. The yield of flexible EL display panels can be improved.

[0489] Heat treatment is performed with the electrode overlapping the thin film transistor at a fixed potential, for example, at ground potential. This makes it possible to effectively remove static electricity that has built up on the substrate during the manufacturing process of the semiconductor device. can be done.

[0490] (Embodiment 14) In this embodiment, the In-Ga-Zn-O-based oxide semiconductor film described in Embodiment 2 is In a thin-film transistor with a channel etch structure used as the active layer of the thin-film transistor A metal film used as a source electrode or a drain electrode, and an In-Ga-Zn-O oxide A layer with a higher indium concentration (In-rich layer) near the interface with the semiconductor film. layer) and titanium oxide film (TiO X ) formation phenomenon was verified using computational science. .

[0491] First, the indium, gallium, and zinc that make up the In-Ga-Zn-O oxide semiconductor The energy required for each oxide to form an oxygen vacancy (vacancy formation energy GeeE def ) and determine which metal oxides are more likely to form oxygen vacancies. We conducted a study on this issue.

[0492] The defect formation energy E def The definition of is expressed by the following formula 1. A is Indium alone, gallium alone, zinc alone, or indium, gallium, and zinc Note that E(O) is half the energy of an oxygen atom, and E(A m O n-1 ) is an acid Oxide A with an electron deficiency m O n-1 represents the energy of

[0493]

number

[0494] Concentration of vacancies n and vacancy formation energy E def The relationship is approximately expressed by the following formula 2. where N is the number of oxygen positions when no defects are formed, and k B Bolt Mann's constant, T, represents temperature.

[0495]

number

[0496] The calculation was performed using the density functional theory program CASTEP. The plane wave basis pseudopotential method was used, and the functional was GGA-PBE. The energy used was 500 eV. The number of grid points was 3 × 3 × 1 for IGZO and 1 for I 2x2x2 for n2O3, 2x3x2 for Ga2O3, 4 for ZnO The ratio was ×4×1.

[0497] The crystal structure of IGZO crystal is symmetric R-3 (international code: 148) structure. For the 84-atom structure with doubled a-axis and b-axis, Ga and Zn are the lowest energy structures. For In2O3, a bixbyite structure with 80 atoms was used. structure, β-Gallia structure of 80 atoms for Ga2O3, and 8 The wurtzite structure with 0 atoms was used.

[0498] From equation 2, the defect formation energy E def As increases, the concentration of oxygen vacancies, n, i.e. It can be seen that the amount of oxygen vacancy is small. In the following Table 1, A is indium alone, , vacancy formation energy for gallium alone, zinc alone, indium, gallium and zinc E def Indicates the value of.

[0499] In IGZO (Model 1), oxygen is adjacent to three indium atoms and one zinc atom in the crystal. The defect formation energy E def The structure is shown in Figure 40(A).

[0500] In addition, IGZO (Model 2) has three indium atoms and one gallium atom adjacent in the crystal. The vacancy formation energy E of the adjacent oxygen def The structure is shown in Figure 40(B). .

[0501] In addition, IGZO (Model 3) has two zinc atoms and two gallium atoms adjacent to each other in the crystal. Oxygen vacancy formation energy E def The structure is shown in Figure 40(C).

[0502] [Table 1]

[0503] Defect formation energy E def The larger the value of is, the easier it is to form an oxygen vacancy. Energy is required, which means that the bond with oxygen tends to be stronger. The vacancy formation energy E def From the value of It is clear that the oxygen is easily lost near the indium.

[0504] The formation of oxygen vacancies in the In-Ga-Zn-O oxide semiconductor is caused by the formation of oxygen vacancies in the source electrode or The metal used as the drain electrode extracts oxygen from the oxide semiconductor. It is believed that the electrical conductivity of oxide semiconductors increases when oxygen vacancies are formed. Therefore, if the above-mentioned oxygen extraction occurs, the oxide semiconductor film near the interface with the metal film It is expected that electrical conductivity will increase.

[0505] Next, we confirm whether the metal is extracting oxygen from the oxide semiconductor. To achieve this, quantum molecular Dynamics (QMD) calculations were performed.

[0506] The structure to be calculated was created as follows. First, a structure was created using the classical molecular dynamics (CMD) method. The amorphous In-Ga-Zn-O oxide semiconductor (a-IGZO) was 4 atoms of In 12 Ga 12 Zinc 12 O 48 Extract the unit cell containing We performed molecular dynamics (QMD) calculations and first-principles structure optimization. The a-IGZO layer was obtained by cutting the IGZO into small pieces, and then crystallization of metal atoms (W, Mo, Ti) was performed on the a-IGZO layer. Then, the structure was optimized. As a starting point, calculations were performed at 623.0 K using the quantum molecular dynamics (QMD) method. In order to estimate only the interface interaction, the bottom edge of the a-IGZO layer and the top edge of the metal layer are fixed. did.

[0507] The calculation conditions for the classical molecular dynamics calculation are shown below. The calculation program is Materials Explorer was used. a-IGZO was fabricated under the following conditions. Calculation cell with a side length of 1 nm A total of 84 atoms are randomly arranged in the In:Ga:Zn:O=1:1:1:4 ratio and the density is 5.9g / cm 3 The temperature was gradually decreased from 5500K to 1K in the NVT ensemble. After that, the structural relaxation was performed at 1K for 10ns. The time step was 0.1fs, and the total calculation time was 10n The potential is the Born-Mayer-Hu potential between the metal and oxygen, and between the oxygen and oxygen. The ggins type is applied to the metal-metal interface, and the Lennard Jones type is applied to the metal-metal interface. The charge is I n: +3, Ga: +3, Zn: +2, O: -2.

[0508] The calculation conditions for the QMD calculation are shown below. The calculation program was the first-principles calculation software CASTE P was used. GGA-PBE was used for the functional, and Ultrasoft was used for the pseudopotential. The cutoff energy was 260 eV, and the number of k-points was 1 × 1 × 1. The calculation was performed in the NVT ensemble with a temperature of 623 K. The total calculation time was 2.0 ps with a time step of The width is 1.0 fs.

[0509] The results of the above calculation are shown in Figures 41 to 43. In Figures 41 to 43, white circles indicate W, Mo, The black circles represent oxygen atoms. FIG. 41(A) shows the structure when a metal layer is used, and FIG. 41(B) shows the structure before QMD calculation. The structure after QMD calculation is shown in Figure 42. The structure when a metal layer made of Mo is used is shown in Figure 43. FIG. 42(A) shows the structure before the QMD calculation, and FIG. 42(B) shows the structure after the QMD calculation. FIG. 43 shows a structure in which a metal layer made of Ti is used. FIG. 43(A) shows the QMD Figure 43(B) shows the structure before and after the QMD calculation.

[0510] From Fig. 42(A) and Fig. 43(A), in the case of Mo and Ti, the metal is already in the state of being ... Oxygen that has moved to the metal layer can be seen. And, in Figure 41(B), Figure 42(B), and Figure 43(B), From the comparison, it was found that the most oxygen transfer was observed in the case of Ti. It is believed that Ti is the most suitable electrode for creating oxygen vacancies in IGZO.

[0511] It is believed that titanium oxide is formed when the oxygen extracted by titanium reacts with the titanium. Therefore, the titanium oxide film formed between the oxide semiconductor film and the titanium film has electrical conductivity. We verified whether it has it or not.

[0512] Titanium dioxide has a rutile structure (high-temperature tetragonal crystal), anatase structure (low-temperature tetragonal crystal), It has several crystal structures, including the brookite structure (orthorhombic). When the titanium dioxide is heated, it changes to the rutile type, which is the most stable structure. The crystal structure of titanium dioxide having the rutile structure is shown in Figure 44. The rutile structure is tetragonal and the space group that indicates the symmetry of the crystal is P42 / mnm. .

[0513] For the titanium dioxide structure above, the density functional method using the GGA-PBE functional was used to obtain The density of states was calculated. The structure was optimized, including the cell structure, while maintaining symmetry. The density of states was calculated using the density functional theory introduced in the CASTEP code. The pseudopotential method was used, and the cutoff energy was set to 380 eV.

[0514] FIG. 45 shows a density of states diagram for titanium dioxide with the rutile structure. Titanium dioxide with a lattice structure has a band gap and has a density of states similar to that of an insulator or a semiconductor. It can be seen that the band gap tends to be estimated as small in density functional theory. The actual band gap of titanium dioxide is about 3.0 eV, as shown in the density of states diagram in Figure 45. 1. The band gap is larger than that shown in FIG.

[0515] Next, FIG. 46 shows the density of states of titanium dioxide with a rutile structure when there is an oxygen deficiency. Specifically, the calculation involves the calculation of the TiO2 and O48 atoms in titanium oxide. Titanium oxide with one Ti24 atom and one O47 atom was used as a model. In the density of states diagram shown in 6, the Fermi level is shifted to the inside of the conduction band, making it metallic, and oxygen vacancy is present. It can be seen that titanium dioxide exhibits n-type conductivity when

[0516] Next, FIG. 47 shows the density of states of titanium monoxide (TiO). It can be seen that tungsten has a metallic density of states.

[0517] Therefore, the density of states of titanium dioxide shown in FIG. 45 and the density of states of titanium dioxide having oxygen vacancies shown in FIG. From the density of states diagram of titanium oxide shown in FIG. 47 and the density of states diagram of titanium monoxide shown in FIG. 48, it is found that the Titanium dioxide (TiO 2-δ ) has n-type conductivity over the range 0<δ<1 Therefore, it is expected that the composition of the titanium oxide film is titanium monoxide, oxygen vacancy, Even if the titanium dioxide film contains any of the In-Ga-Zn It is believed that the flow of current between the -O-based oxide semiconductor film and the titanium film is unlikely to be obstructed.

[0518] FIG. 48 shows the energy distribution between the source and drain electrodes of a thin film transistor. In FIG. 48, an In-Ga-Zn- Using an O-based film (IGZO), the oxide semiconductor film is placed between the source electrode and the oxide semiconductor film. Between the drain electrode and TiO xHowever, TiO x The thickness of the oxide semiconductor film is 0.1 nm or more and 10 nm or less. In, Ga, Zn, etc.), and the above pair of TiO x Each of the membranes is in contact with The In-Ga-Zn-O film (IGZO) in the area other than the composite layer The electron affinity of TiO is 4.3 eV. x The film was placed at 4.3 eV and connected to the source or drain electrode. The Ti layer is shown as 4.1 eV and the composite layer as 4.5 eV. The band position changes so that the Fermi level of the material is aligned. When IGZO is not oxidized, the Fermi level is in the middle of the band gap because of the small number of carriers. In the TiOx film and composite layer, the Fermi level is not propagated due to the large number of carriers. Therefore, in Figure 48, the position of the conduction band of each material is determined by the above electron affinity. As shown in Figure 48, the composite layers have almost no difference in electron affinity. Therefore, between the oxide semiconductor film and the source electrode, and between the oxide semiconductor film and the drain electrode, A good connection structure can be achieved. [Explanation of symbols]

[0519] 7 Gate terminal 8 Source terminal 20 Gate wiring 21 Terminal 22 Terminals 23 Terminal 24 terminals 25 Terminals 26 Terminals 27 Terminal 30 Display device 44 Common Wiring 45 Common Wiring 45a Gate wiring 45b Gate wiring 46 Common Wiring 60 Source wiring 65 Common Wiring 65a Source wiring 65b Source wiring 71 Terminal 74 Terminals 75 Terminals 81 Terminal 84 terminals 85 Terminals 91 Gate drive circuit 92 Source driver circuit 93 pixels 94 pixel area 95 Connection 96 Common Connection 97 Protection circuit 100 Substrates 101 Insulating film 102 Insulating layer 102a Insulating layer 102b Insulating layer 111a Gate wiring 111b Gate wiring 113 Semiconductor layer 115a electrode 115b electrode 115c electrode 117 Insulating Layer 118 Insulating Layer 119 Insulating Layer 125 Contact Hole 126 Contact Hole 127 Contact Hole 128 Contact Hole 170a Nonlinear element 170b Nonlinear element 200 boards 201 Insulating layer 202 Gate wiring 203 Gate wiring 204 Insulating layer 204a Insulating layer 204b Insulating layer 205 Semiconductor layer 207 Electrode layer 207a Electrode 207b Electrode 208 Insulating layer 208a Insulating layer 208b Insulating layer 209 Source wiring 210 Source wiring 211 Insulating layer 212 Electrode 213 Holding capacitor wiring 214 Holding capacitor wiring 216 Opening 217 Opening 225 Channel Protection Layer 250 Thin Film Transistors 251 Thin-film transistor 252 Thin-film transistor 300 Substrates 351 Gate wiring 351a Gate wiring 351b Gate wiring 352 Electrode 354 Source Wiring 354a Source wiring 354b Source wiring 355 Transparent conductive layer 360 Insulation layer 361 Insulating Layer 362 Insulating Layer 363 Insulating Layer 364 Insulating Layer 365 Insulation Layer 400 Substrates 401a Gate wiring 401b Gate wiring 403a Semiconductor layer 403b Semiconductor layer 404 Contact Hole 405a electrode 405b electrode 405c electrode 410 Insulating layer 411 Insulating layer 412 Insulating layer 413 Insulating layer 414 Insulating layer 415 Insulating layer 430a Thin film transistor 430b Thin film transistor 580 Substrate 581 Thin Film Transistor 582 Insulating layer 583 Insulating Layer 585 Insulation Layer 587 Electrode layer 588 Electrode layer 589 Spherical particles 590a black area 590b White area 591 Insulating Layer 592 Insulating layer 594 Cavity 595 Filling material 596 Board 597 Insulating Layer 598 Insulating Layer 599a Source wiring 599b Source wiring 600 Substrates 601 Opposing substrate 602 Gate wiring 602a Gate wiring 602b Gate wiring 603 Gate wiring 603a Gate wiring 603b Gate wiring 604 Capacitance wiring 604a Capacitive wiring 604b Capacitive wiring 605 Capacitance wiring 605a Capacitive wiring 605b Capacitive wiring 607 Pixel electrode 616 Source wiring 616a Source wiring 616b Source wiring 617 Capacitance wiring 618 Wiring 619 Wiring 622 Insulating layer 623 Contact Hole 624 Pixel electrode layer 625 Slit 626 Pixel electrode layer 627 Contact Hole 628 TFT 629 TFT 630 Holding capacity section 631 Holding capacity section 636 Colored film 637 Planarization film 640 Counter electrode layer 641 Slit 644 Protrusion 646 Orientation Film 648 Orientation Film 650 Liquid crystal layer 651 Liquid crystal element 652 Liquid crystal element 661 Insulating Layer 662 Insulating layer 663 Insulating Layer 664 Insulating layer 665 Insulating Layer 666 Insulating Layer 690 Capacitance wiring 690a Capacitive wiring 690b capacitor wiring 701 Substrate 702 Common connection part 704 Sealing material 705 Sealing material 706 Substrate 708 Liquid crystal layer 710 Thin Film Transistor 711 Thin Film Transistor 715 Common connection terminal 716 External terminal 730 Pixel electrode 731 Counter Electrode 735 Spacer 740 Conductive Layer 742 Interlayer insulating film 780 Furnace 790 Static Electricity 791 Routes 801a Gray Tone Mask 801b Halftone Mask 802 Transparent substrate 803 Shading part 804 Diffraction Grating 805 Light transmittance 806 Shading part 807 Semi-transparent part 808 Light transmittance 2600 TFT substrate 2601 Opposing substrate 2602 Sealing material 2603 Pixel section 2604 Display element 2605 Colored layer 2606 Polarizing plate 2607 Polarizing plate 2608 Wiring circuit section 2609 Flexible wiring board 2610 cold cathode tube 2611 Reflector 2612 Circuit Board 2613 Diffuser 2700 e-books 2701 Case 2703 Case 2705 ​​Display section 2707 Display section 2711 Shaft 2721 Power supply 2723 Operation key 2725 Speaker 4001 Substrate 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 Substrate 4008 Liquid crystal layer 4010 Thin film transistor 4011 Thin film transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive film 4020 Insulation layer 4021 Insulation layer 4030 Pixel electrode layer 4031 Counter electrode layer 4032 Insulation layer 4035 Spacer 4040 Conductive layer 4041 Insulation layer 4042 Insulation layer 4043 Insulation layer 4044 Insulation layer 4045 Insulation layer 4046 Source Wiring 4501 Board 4502 Pixel section 4503a Signal line driver circuit 4503b Signal line driver circuit 4504a Scanning line driver circuit 4504b Scanning line driver circuit 4505 Sealing material 4506 Board 4507 Filling material 4509 Thin-film transistor 4510 Thin-film transistor 4511 Light emitting element 4512 Electroluminescent layer 4513 Electrode layer 4515 Connection terminal electrode 4516 Terminal electrode 4517 Electrode layer 4518a FPC 4518b FPC 4519 Anisotropic conductive film 4520 Bulkhead 4540 Conductive layer 4541 Insulation layer 4542 Insulation layer 4543 Insulation layer 4544 Insulation layer 4545 Insulation layer 4546 Insulation layer 4547 Insulation layer 4548 Source Wiring 5300 Board 5301 Pixel unit 5302 Scanning line driver circuit 5303 Scanning line driver circuit 5304 Signal line driver circuit 5305 Timing Control Circuit 5601 Shift Register 5602 Switching Circuit 5603 Thin Film Transistor 5604 Wiring 5605 Wiring 6400 pixels 6401 Switching transistor 6402 Driving transistor 6403 Capacitor 6404 Light emitting element 6405 Signal Line 6406 scan lines 6407 Power line 6408 Common electrode 7001 TFT 7002 Light emitting element 7003 Cathode 7004 EL layer 7005 Anode 7008a Source wiring 7008b Source wiring 7009 Bulkhead 7011 Driving TFT 7012 Light emitting element 7013 Cathode 7014 EL layer 7015 Anode 7016 Shielding membrane 7017 Conductive film 7018a Source wiring 7018b Source wiring 7019 Bulkhead 7021 Driving TFT 7022 Light emitting element 7023 Cathode 7024 EL layer 7025 Anode 7027 Conductive film 7028a Source wiring 7028b Source wiring 7029 Bulkhead 7031 Insulation layer 7032 Insulation layer 7033 Color filter layer 7034 Overcoat layer 7035 Protective insulation layer 7036 Insulation layer 7037 Insulation layer 7038 Insulation layer 7039 Insulation layer 7041 Insulation layer 7042 Insulation layer 7043 Color filter layer 7044 Overcoat layer 7045 Protective insulation layer 7046 Insulation layer 7047 Insulation layer 7048 Insulation layer 7049 Insulation layer 7051 Insulation layer 7052 Insulation layer 7053 Planarizing insulating layer 7055 Insulation layer 7056 Insulation layer 7057 Insulation layer 7058 Insulation layer 7059 Insulation layer 7061 Driving TFT 7063 Color filter layer 7064 Overcoat layer 7065 Protective insulation layer 7067 Conductive film 7068a Source wiring 7068b Source wiring 7071 Insulation layer 7072 Insulation layer 7076 Insulation layer 7077 Insulation layer 7078 Insulation layer 7079 Insulation layer 9201 Display section 9202 Display button 9203 Operation switch 9204 Band 9205 Adjustment section 9206 Camera Department 9207 Speaker 9208 Mike 9301 Upper housing 9302 Lower housing 9303 Display section 9304 Keyboard 9305 External connection port 9306 Pointing Device 9307 Display section 9600 Television Equipment 9601 Case 9603 Display section 9605 Stand 9607 Display section 9609 Operation key 9610 Remote control device 9700 Digital Photo Frame 9701 Case 9703 Display section 9881 Case 9882 Display section 9883 Display section 9884 Speaker section 9885 Operation key 9886 Recording medium insertion section 9887 Connection terminal 9888 Sensor 9889 Microphone 9890 LED Lamp 9891 Case 9893 Connection section 9900 Slot Machine 9901 Case 9903 Display section

Claims

1. a first conductive layer having a function as a gate electrode of a transistor; a first insulating layer having a region overlying the first conductive layer; an oxide semiconductor layer having a region located over the first insulating layer and including a channel formation region of the transistor; a second conductive layer having a region in contact with a top surface of the oxide semiconductor layer, a region in contact with a side surface of the oxide semiconductor layer, and a region in contact with a top surface of the first insulating layer, and functioning as one of a source electrode and a drain electrode of the transistor; a third conductive layer having a region in contact with a top surface of the oxide semiconductor layer, a region in contact with a side surface of the oxide semiconductor layer, and a region in contact with a top surface of the first insulating layer, and serving as the other of the source electrode and drain electrode of the transistor; a second insulating layer having a region in contact with an upper surface of the second conductive layer, a region in contact with an upper surface of the third conductive layer, and a region in contact with an upper surface of the oxide semiconductor layer; a fourth conductive layer having a region located above the second insulating layer and functioning as wiring; a fifth conductive layer having a region located above the second insulating layer and functioning as a pixel electrode; the second insulating layer has a first opening and a second opening; the fourth conductive layer is electrically connected to the second conductive layer in the first opening; the fifth conductive layer is electrically connected to the third conductive layer in the second opening; the fourth conductive layer has a laminated structure, a thickness of the second conductive layer is smaller than a thickness of the fourth conductive layer; the oxide semiconductor layer does not overlap with the first opening and does not overlap with the second opening; The first conductive layer does not overlap with the first opening and does not overlap with the second opening.

2. a first conductive layer having a function as a gate electrode of a transistor; a first insulating layer having a region overlying the first conductive layer; an oxide semiconductor layer having a region located over the first insulating layer and including a channel formation region of the transistor; a second conductive layer having a region in contact with a top surface of the oxide semiconductor layer, a region in contact with a side surface of the oxide semiconductor layer, and a region in contact with a top surface of the first insulating layer, and functioning as one of a source electrode and a drain electrode of the transistor; a third conductive layer having a region in contact with a top surface of the oxide semiconductor layer, a region in contact with a side surface of the oxide semiconductor layer, and a region in contact with a top surface of the first insulating layer, and serving as the other of the source electrode and drain electrode of the transistor; a second insulating layer having a region in contact with an upper surface of the second conductive layer, a region in contact with an upper surface of the third conductive layer, and a region in contact with an upper surface of the oxide semiconductor layer; a fourth conductive layer having a region located above the second insulating layer and functioning as wiring; a fifth conductive layer having a region located above the second insulating layer and functioning as a pixel electrode; the second insulating layer has a first opening and a second opening; the fourth conductive layer is electrically connected to the second conductive layer in the first opening; the fifth conductive layer is electrically connected to the third conductive layer in the second opening; the fourth conductive layer has a laminated structure, a thickness of the second conductive layer is smaller than a thickness of the fourth conductive layer; the oxide semiconductor layer does not overlap with the first opening and does not overlap with the second opening; the first conductive layer does not overlap with the first opening and does not overlap with the second opening; a first conductive layer disposed on the first insulating film and configured to electrically connect the first conductive layer to the oxide semiconductor layer;

3. a first conductive layer having a function as a gate electrode of a transistor; a first insulating layer having a region overlying the first conductive layer; an oxide semiconductor layer having a region located over the first insulating layer and including a channel formation region of the transistor; a second conductive layer having a region in contact with a top surface of the oxide semiconductor layer, a region in contact with a side surface of the oxide semiconductor layer, and a region in contact with a top surface of the first insulating layer, and functioning as one of a source electrode and a drain electrode of the transistor; a third conductive layer having a region in contact with a top surface of the oxide semiconductor layer, a region in contact with a side surface of the oxide semiconductor layer, and a region in contact with a top surface of the first insulating layer, and serving as the other of the source electrode and drain electrode of the transistor; a second insulating layer having a region in contact with an upper surface of the second conductive layer, a region in contact with an upper surface of the third conductive layer, and a region in contact with an upper surface of the oxide semiconductor layer; a fourth conductive layer having a region located above the second insulating layer and functioning as wiring; a fifth conductive layer having a region located above the second insulating layer and functioning as a pixel electrode; the second insulating layer has a first opening and a second opening; the fourth conductive layer is electrically connected to the second conductive layer in the first opening; the fifth conductive layer is electrically connected to the third conductive layer in the second opening; the fourth conductive layer has a laminated structure, a thickness of the second conductive layer is smaller than a thickness of the fourth conductive layer; the oxide semiconductor layer does not overlap with the first opening and does not overlap with the second opening; the first conductive layer does not overlap with the first opening and does not overlap with the second opening; In a plan view, the fourth conductive layer has a region extending in a first direction, A display device, wherein, in a plan view, the third conductive layer has a region that extends in a direction parallel or approximately parallel to the first direction.

4. a first conductive layer having a function as a gate electrode of a transistor; a first insulating layer having a region overlying the first conductive layer; an oxide semiconductor layer having a region located over the first insulating layer and including a channel formation region of the transistor; a second conductive layer having a region in contact with a top surface of the oxide semiconductor layer, a region in contact with a side surface of the oxide semiconductor layer, and a region in contact with a top surface of the first insulating layer, and functioning as one of a source electrode and a drain electrode of the transistor; a third conductive layer having a region in contact with a top surface of the oxide semiconductor layer, a region in contact with a side surface of the oxide semiconductor layer, and a region in contact with a top surface of the first insulating layer, and serving as the other of the source electrode and drain electrode of the transistor; a second insulating layer having a region in contact with an upper surface of the second conductive layer, a region in contact with an upper surface of the third conductive layer, and a region in contact with an upper surface of the oxide semiconductor layer; a fourth conductive layer having a region located above the second insulating layer and functioning as wiring; a fifth conductive layer having a region located above the second insulating layer and functioning as a pixel electrode; the second insulating layer has a first opening and a second opening; the fourth conductive layer is electrically connected to the second conductive layer in the first opening; the fifth conductive layer is electrically connected to the third conductive layer in the second opening; the fourth conductive layer has a laminated structure, a thickness of the second conductive layer is smaller than a thickness of the fourth conductive layer; the oxide semiconductor layer does not overlap with the first opening and does not overlap with the second opening; the first conductive layer does not overlap with the first opening and does not overlap with the second opening; an entire surface of the oxide semiconductor layer overlaps with the first conductive layer in a plan view; In a plan view, the fourth conductive layer has a region extending in a first direction, A display device, wherein, in a plan view, the third conductive layer has a region that extends in a direction parallel or approximately parallel to the first direction.

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