Electronic apparatus, data generation method, circuit generation method, and circuit generation program

Abstract

To provide a circuit generation apparatus which can automatically generate a circuit by combining cells.SOLUTION: A circuit generating apparatus 100 according to the present invention has searching means for allocating a cell as a unit as an element of a circuit having a specific function to a node of each hierarchy of a Monte Carlo tree structure and searching for a route in the Monte Carlo tree structure, and generation means for generating a target circuit by synthesizing a plurality of cells based on the searched route.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a circuit generation device, a data generation method, a circuit generation method, and a circuit design program for generating a semiconductor integrated circuit, and more particularly to a design technique for generating a circuit by Monte Carlo search. [Background technology]

[0002] As an example of a circuit design device for semiconductor integrated circuits, Patent Document 1 discloses a method for generating circuit cells using a versatile template to shorten the design time of a target circuit. The template includes design method information for determining transistor parameters from topology information having a plurality of transistors, process information, and transistor specification information, and a user inputs the process information and transistor specification information using the template. The circuit design device determines transistor parameters according to the input process information and transistor specification information according to the design method information, and automatically generates circuit cells corresponding to the topology based on the determined parameters. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6568980 Summary of the Invention [Problem to be solved by the invention]

[0004] In cell-based circuit design, a circuit is divided into individual functional blocks (cells), and the entire circuit is constructed by combining these cells. A cell is a small unit of a circuit that has a specific function, and is composed of circuit elements such as transistors and resistors that realize the specific function.

[0005] The cells registered in the library can be reused, and a circuit designer selects appropriate cells from the library and combines them to generate a target circuit. Reusing the cells in the library can increase the productivity and reliability of circuit design.

[0006] Cell-based circuit design is primarily used in the design of digital circuits, but it can also be used in the design of analog circuits and mixed-signal circuits that include analog and digital components. For example, the present applicant has disclosed a method for generating cells for analog circuits under the name AnaCell in Patent Document 1. AnaCell also has a guaranteed validity of the meaning of the circuit, and can be an ideal building block for generating a target circuit.

[0007] In such cell-based circuit design, an experienced designer can design a target circuit by combining a limited number of cells based on experience, but a designer without experience or skills must select cells from an enormous number of cell combinations and repeatedly try out the combinations of the selected cells to design the target circuit.There is a demand for a design method that reduces the effort and time required for design by experienced designers and designers without skills or experience, and is also highly reliable.

[0008] The present invention is devised to solve such conventional problems, and aims to provide an electronic device, a data generation method, a circuit generation method, and a circuit generation program that can automatically generate a target circuit by synthesizing cells. [Means for solving the problem]

[0009] The electronic device according to the present invention has a circuit generation function and comprises a search means for assigning cells, which are building blocks of a circuit and have specific functions, to nodes at each level of a Monte Carlo tree structure and for searching for a root in the Monte Carlo tree structure, and a generation means for generating a target circuit by combining a plurality of cells based on the searched route.

[0010] In one embodiment, each node of the Monte Carlo tree structure holds a w cumulative value and an n number of trials, and the search means selects a node based on the w cumulative value and the n number of trials, and searches for a route from the root node to a leaf node. In one embodiment, when the search means has searched for a route from the root node to a leaf node, it executes a test bench for evaluating the performance of the generated target circuit, and updates the w cumulative value of each node according to the test bench result. In one embodiment, the search means determines whether or not a measured value of the performance of the target circuit obtained by the test bench satisfies an operational specification of the target circuit input by a user, and when the measured value satisfies the operational specification, it adds points to the w cumulative value, and when the operational specification is not satisfied, it does not add points to the w cumulative value or subtracts points. In one embodiment, when the search means has searched for a route from the root node to a leaf node, it adds points to the n number of trials of each node on the route. In one embodiment, each node of the Monte Carlo tree structure further holds a cumulative maximum value of measured values ​​of performance of the target circuit obtained by a test bench, and the search means searches for a route based on the cumulative maximum value. In one embodiment, the search means assigns cells registered in a library to each node of the Monte Carlo tree structure. In one embodiment, the library includes cells of analog circuits, cells of digital circuits, and cells indicating connections of multiple elements.

[0011] A circuit generation method for an electronic device according to the present invention includes a step of assigning cells, which are building blocks of a circuit and have specific functions, to nodes at each level of a Monte Carlo tree structure, searching for a root in the Monte Carlo tree structure, and a step of generating a target circuit by synthesizing a plurality of cells based on the searched route.

[0012] The circuit generation program executed by the electronic device according to the present invention includes a step of assigning cells, which are building blocks of a circuit and have specific functions, to nodes at each level of a Monte Carlo tree structure and searching for a root in the Monte Carlo tree structure, and a step of generating a target circuit by synthesizing a plurality of cells based on the searched route. Effect of the Invention

[0013] According to the present invention, a Monte Carlo tree structure is used to search for optimal cell combinations, and the searched cells are synthesized to generate a target circuit, thereby making it possible to significantly improve design efficiency, and even experienced designers or designers with no experience or skills can easily design the target circuit. [Brief description of the drawings]

[0014] [Figure 1] 1 is a block diagram showing a configuration of a circuit generating device according to an embodiment of the present invention; [Diagram 2] FIG. 4 is a diagram showing a generation flow of a target circuit according to an embodiment of the present invention. [Diagram 3] FIG. 2 is a diagram for explaining a data structure of a Monte Carlo tree structure according to an embodiment of the present invention. [Figure 4] FIG. 2 is a diagram showing an example of an AnaCell registered in a library. [Diagram 5] FIG. 2 is a diagram showing an example of a Monte Carlo tree structure of an operational amplifier according to an embodiment of the present invention. [Figure 6] FIG. 11 is a diagram showing an example of target values ​​stored in each node according to another embodiment of the present invention. [Figure 7] FIG. 1 is a block diagram showing the configuration of a SAR ADC. [Figure 8] FIG. 8 is a diagram illustrating an example of the configuration of the internal logic of the SAR ADC illustrated in FIG. 7. [Figure 9] FIG. 11 is a diagram illustrating an example of a Monte Carlo tree structure of a SAR ADC according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] The present invention uses Monte Carlo Search (MCTS) in cell-based circuit design. Monte Carlo Search is essentially an algorithm for efficiently solving search problems, and this algorithm can be used to solve optimization problems of cell combinations.

[0016] AnaCell / LogiCell units can be almost ideal building blocks for circuits in terms of selection and combination, and a large number of these cells are registered in the library. For example, an op-amp or other circuit can be generated by synthesizing AnaCells or LogiCells, and a Monte Carlo search is used to synthesize the cells.

[0017] The design method of this invention, for example, transforms analog circuit design from a method in which LW parameter tuning is the main skill to a design method that involves topology architecture consideration + library (cell) preparation, which enables significant design efficiency improvement and new topology generation. Furthermore, by registering logic blocks, analog circuits, etc. as assets in this scheme, it becomes possible to significantly increase reusability in future new designs. EXAMPLES

[0018] Next, an embodiment of the present invention will be described with reference to the drawings. Fig. 1 is a block diagram showing a schematic configuration of a circuit generating device of this embodiment. The circuit generating device 100 is realized by using hardware and software using an electronic device such as a computer or a server connected to a network.

[0019] In one embodiment, the circuit generation device 100 is configured to include an input unit 110 that receives instructions from a user or an external device, an output unit 120 that outputs information regarding circuit generation in the form of images and / or sounds, a communication unit 130 that enables communication with the outside world via wireless or wired connections, a ROM / RAM 140, a memory unit 150 that stores data, programs, software applications, etc. necessary for circuit generation, and a controller 160 that controls each unit.

[0020] The input unit 110 includes, but is not limited to, for example, a keyboard, a mouse, a voice input module, etc., and the user inputs circuit information or data required for circuit generation. The information input from the input unit 110 is provided to the controller 160. The output unit 120 includes, but is not limited to, a display, a speaker, etc., and outputs various information required for circuit generation. The communication unit 130 enables, but is not limited to, connection to external devices or external networks via wireless or wired connection. In one embodiment, the communication unit 130 transmits and receives data required for circuit generation to and from the cloud server 170.

[0021] The storage unit 150 is not particularly limited, but may be configured to include a storage device such as a semiconductor memory or a hard disk. The storage unit 150 includes data of a Monte Carlo tree structure for performing a Monte Carlo search. As will be described later, the Monte Carlo tree structure includes nodes at each level from the root node to the leaf nodes, and a cell registered in the library is assigned to each node.

[0022] The controller 160 includes, but is not limited to, an arithmetic processing device such as a CPU or a GPU, reads out a circuit generation program stored in the storage unit 150 or the ROM / RAM 140, and executes the circuit generation program. The circuit generation program makes it possible to search for a route using a Monte Carlo tree structure and generate a target circuit based on the searched route.

[0023] 3 is a diagram showing a flow of generating a target circuit by Monte Carlo search using a Monte Carlo tree structure. When generating a target circuit, a user, i.e., a circuit designer, inputs circuit information of the target circuit from input unit 110 (step S110). The circuit information includes, for example, the target circuit and its operating specifications or characteristics.

[0024] The target circuit may be any circuit, such as an analog circuit, a mixed circuit including an analog circuit and a digital circuit, or a digital circuit. For example, when the target circuit is an operational amplifier (analog circuit), the user inputs the operational specifications or characteristics, such as the gain, amplitude, phase margin, area, and power, of the operational amplifier as circuit information.

[0025] Next, the controller 160 searches for an optimal route using a Monte Carlo tree structure based on the circuit information input by the user (step S120). An example of a Monte Carlo tree structure is shown in Fig. 3. It should be noted that the number of layers and the number of nodes of the Monte Carlo tree structure shown here are merely examples and are simplified for ease of explanation.

[0026] As shown in the figure, the Monte Carlo tree structure has a root node N RT Starting from node N in the first hierarchy 11 ~N 13 , node N in the second hierarchy 21 ~N 23 , node N in the third hierarchy 31 ~N 33 Then, the fourth level leaf node N 41 ~N 43 Reaching the leaf node N 41 ~N 43 is defined as the last node that has no child nodes.

[0027] The Monte Carlo tree structure includes, as a data structure, for example, node identification information for identifying each node and attribute information for each node. Each attribute information includes connection information indicating which node in another layer the node is connected to, cell identification information for identifying a cell assigned to each node, and search information for the number of trials n and the cumulative value w used in the Monte Carlo search.

[0028] The controller 160 expands or generates the Monte Carlo tree structure according to a Monte Carlo search algorithm. In one embodiment, a group of cells of the same type registered in the library is mapped or assigned to each layer of the Monte Carlo tree structure. In the example of FIG. 3, a group of cells of the first type registered in the library is mapped to a first layer of the Monte Carlo tree structure, a group of cells of the second type is mapped to a second layer, and a group of cells of the third type is mapped to a third layer, and any cell selected from the group of cells of the first type is assigned to each node of the first layer, any cell selected from the group of cells of the second type is assigned to each node of the second layer, and any cell selected from the group of cells of the third type is assigned to each node of the third layer. Each cell of the group of cells of the same type has a common function but has a different circuit topology. That is, each cell in the group of cells of the first type, the group of cells of the second type, and the group of cells of the third type has a different function.

[0029] The mapping of the cell group to each layer is performed, for example, by referring to the addresses of the cell group. An address area for storing each cell of the first type of cell group is assigned to the first layer, an address area for storing each cell of the second type of cell group is assigned to the second layer, and an address area for storing each cell of the third type of cell group is assigned to the third layer. The controller 160 refers to the mapped address areas and selects cells to be assigned to the nodes of each layer from the cell group.

[0030] In the library, a large number of cells, which are the constituent units of a circuit, are registered, and the cells include at least information on the circuit topology. The types and number of cells to be registered are not particularly limited, but for example, analog circuit cells (AnaCell), digital circuit cells (DegiCell), standard cells (logic gates, flip-flops, registers, multiplexers, etc.), cells representing connections between multiple elements (for example, resistors and capacitors), etc. are registered. The library is stored in, for example, the storage unit 150 or the cloud server 170.

[0031] When the target circuit is an operational amplifier, the operational amplifier may be composed of, for example, a differential input circuit, a phase compensation circuit, and an output circuit. In one embodiment, a group of cells of the differential input circuit is mapped or assigned to a first layer of the Monte Carlo tree structure, a group of cells of the phase compensation circuit is mapped or assigned to a second layer, which is the next layer, and a group of cells of the output circuit is mapped or assigned to a third layer. The root node is an operational amplifier and can be used to identify the operational amplifier.

[0032] According to the Monte Carlo search algorithm, the controller 160 assigns a cell selected from the group of cells of the differential input circuit to a node in the first hierarchical level when the node in the first hierarchical level is expanded or expanded, assigns a cell selected from the group of cells of the phase compensation circuit to the node in the second hierarchical level when the node in the second hierarchical level is expanded or expanded, and assigns a cell selected from the group of cells of the output circuit to the node in the third hierarchical level when the node in the third hierarchical level is expanded or expanded, and updates the attribute information of each node.

[0033] FIG. 4 is a diagram showing an example of a cell (AnaCell) used in an operational amplifier registered in the library. As shown in the figure, there are single-ended and differential types of differential input circuits, and the former types include a current mirror type, a cascode current mirror type, and a telescopic current mirror type, which are further classified into an n-well or p-well structure. The latter types include a constant current load type, a cascode constant current load type, and a telescopic constant current load type, which are further classified into an n-well or p-well structure. In this way, the library contains many cells that have a common function but different circuit topologies.

[0034] The controller 160 searches for an optimal route from the root node to the leaf node in a Monte Carlo search, synthesizes cells assigned to each node identified by the route, and generates a target circuit (S130). Next, the controller 160 executes a test bench for the generated target circuit, and updates the w cumulative value and n number of trials held in each node on the route from the leaf node to the root node (S140).

[0035] The test bench circuit is a circuit for evaluating and verifying the performance of a circuit, and is used to determine whether or not the generated target circuit satisfies the operation specifications of the target circuit input by the user. The test bench circuit applies a specific input pattern to the circuit and observes the output to evaluate the operation. For example, when the target circuit is an operational amplifier, the test bench inputs a sine wave signal to measure the gain and phase response of the operational amplifier, inputs a pulse signal to measure the step response and response time of the operational amplifier, inputs a square wave signal to measure the waveform (distortion) of the amplified signal, and inputs a noise signal to measure the noise level and noise spectrum in order to evaluate the amplification ability and frequency characteristics of the operational amplifier. The controller 160 measures the gain, bandwidth, phase response, distortion, noise characteristics, etc. of the operational amplifier, and determines whether or not the measurement results satisfy the operation specifications of the target circuit input by the user.

[0036] After executing the test bench, the controller 160 adds points to the w cumulative value of each node on the searched route according to the measurement result of the test bench. That is, when the measurement value of the test bench satisfies the operation specification input by the user, points are added to the w cumulative value, and when it does not satisfy, points are subtracted from the w cumulative value or no points are added. Furthermore, the controller 160 adds points to the number of n trials of each node on the searched route.

[0037] For example, from the root node to node N 12 , node N 22 , node N 32 via leaf node N 42When a route to reach node N is found, the controller 160 12 , node N 22 , node N 32 , node N 42 The controller 160 also adds "+1" to the number of trials of each of the nodes N 12 , node N 22 , node N 32 , node N 42 The target circuit generated by synthesizing the cells assigned to is evaluated by a test bench, and it is determined whether the measured value of the test bench satisfies the operation specifications input by the user. If it is determined that the operation specifications are satisfied, the node N 12 , node N 22 , node N 32 , node N 42 If the cumulative value of each w is added by, for example, "+1", and it is determined that the operation specification is not satisfied, the node N 12 , node N 22 , node N 32 , node N 42 For example, "-1" is subtracted from each of the w cumulative values ​​of the nodes. When the operation specifications input by the user are changed or new operation specifications are input, the controller 160 clears the w cumulative value and the number of n trials of each node to "0."

[0038] FIG. 5 is a diagram showing an example of a Monte Carlo tree structure of an operational amplifier. The root node represents the identification of the operational amplifier. Cells registered in the library are assigned to each layer of the Monte Carlo tree structure. Here, the node N 11 ~N 13 The AnaCell of the differential input circuit is assigned to node N 21 ~N 23 The cells of the phase compensation circuit, which indicate the element values ​​and connection method, are assigned to the node N 31 ~N 33 For example, the AnaCell of the output circuit is assigned to node N 12The attribute information is the cell identification information for identifying the cell of the differential input circuit of the differential cascode constant current load type (see Fig. 4), and the upper layer root node N RT and the lower node N 21 , node N 22 , node N 23 Contains connection information to node N 32 The attribute information includes cell identification information (see Fig. 4) that identifies the cells of the source-grounded resistive load type output amplifier circuit, and the cell ID information of the upper layer node N 21 , node N 22 , node N 23 and the leaf node N 42 Contains connection information to.

[0039] Next, a specific example of the control flow of the Monte Carlo search according to this embodiment will be described. 1. Selection Policy (selection): e.g. UCB (Upper Confidence Bounds) n: Number of trials w: Accumulated value t: the sum of all trials

[0040] TIFF2025032441000002.tif25170w / n=success rate √ =bias

[0041] The search starts from the root node, and if a child node exists, the operation of selecting and moving from the root node is repeated until a leaf node is reached. This operation is called selection. The controller 160 selects the child node with the largest "UCB1" (bias + success rate) according to formula (1). The success rate is the first term w / n in the above formula, and the bias is the second term. This makes it easier to select a node with a high w cumulative value, but on the other hand, a node with a small number of attempts can be appropriately selected. Note that "UCB1" cannot be calculated unless all "child nodes" have an attempt count of 1 or more (it is divided by 0), so if there is a "child node" with an attempt count of 0, that node is selected. Since all are 0 the first time, the first one found is selected (random).

[0042] 2. Expansion Since there are so many, it is necessary to limit the expansion, and it is desirable to decide in advance what extent should be prepared. Whether or not all circuit configurations should be generated in advance depends on the number of cell types. For example, in the Monte Carlo tree structure of the op-amp shown in Figure 5, whether or not all 500 x 500 x 10 = 2,500,000 final circuit diagrams should be prepared depends on the machine resources. It is realistic to have the user specify the maximum disk usage amount depending on the design environment, and it is desirable to decide in advance what should be expanded and what should be generated at run time.

[0043] 3. Parameter Optimization After determining the target circuit structure by combining optimal cells through Monte Carlo search, the parameters of cells such as AnaCell are optimized by reinforcement learning etc. to meet the target specifications. For speedup, it is desirable to assign initial values ​​analytically.

[0044] In reinforcement learning, etc., when varying the LW parameters of AnaCell or the LW of C or other transistors not included in AnaCell, it is necessary to increase the range of variation and perform the process quickly. Here, it is more important to satisfy the operating specifications than to optimize the design.

[0045] As an example, the execution time for op-amp circuit-level parameter optimization is expected to be within about 10 minutes on one CPU (approximately 60 / 10 x 20 = 120 pattern trials per hour on 24 CPUs). During training, with typical specifications, it is possible to train 24 x 60 x 7 / 10 x 20 x 2 = 40,320 topologies in one week on two machines with 24 CPUs. If training is not sufficient, it is also possible to train for several weeks or on the cloud. The closer the specifications during training are to those during trials, the shorter the convergence (solution search) time will be, so it is essentially adjustable. In addition, it is necessary to consider in advance how much memory and disk size the machine will require for the above learning. As a result, if the target specification is reached within a certain time, points n are awarded, and if not, negative points -n are awarded. Circuit parameter optimization can be analysis-based or simulation-based. For example, in simulation-based optimization, parameters such as L, W, and C (capacitor) of the DUT (Device under Test: for example, an operational amplifier) ​​are adjusted, and an input signal is applied from a test bench circuit to simulate and confirm the circuit specifications. The parameter values ​​are adjusted so as to reduce the difference between the circuit specifications and the target values. This loop is repeated to get closer to the target values.

[0046] 4.Backpropagation The above points are reflected in the w cumulative value of each node up to the root node. Also, points are added to the n trial count of each node for the search route in which the final combinational circuit is simulated in the test bench. 5.Recursively repeat the search from the root node to the leaf node. By repeating the search a certain number of times while updating the cumulative value of w and the number of trials of n, the cumulative value of w and the number of trials of n are set so that the optimal route (combination of cells) for the operation specifications of the target circuit input by the user is obtained. 6. Execute steps 1 to 5 above comprehensively as long as time allows, using the target circuit, e.g. typical values ​​of an op-amp. If necessary, you can divide the circuit into several groups and let them learn, and select the Monte Carlo tree structure closest to the target used by the user. The above steps 1 to 6 are trained with typical values ​​for the open network, taking as much time and resources as possible. This creates thousands or tens of thousands of topologies, and their parameters are optimized. 7. Give a new target specification and execute again from step 1 above. This increases the probability of quickly finding a combination of cells that satisfies the target specification. At this point, the selection policy has already been created for the typical specification. However, the points in backpropagation will be cleared. According to this policy, parameter optimization is performed with different specifications, making it possible to search for topologies that satisfy new specifications as long as time and resources permit. Regarding hierarchical optimization of the Monte Carlo tree structure, it is possible to reach the optimal solution more quickly by grouping similar cells (such as differential circuits) and adding tree layers. For example, adding the type shown in Figure 4 (current mirror type, telescopic type, etc.) to the intermediate nodes.

[0047] Reusing learning results There is a risk that learning with typical specifications before trial will be unable to be used due to a large difference in specifications between learning and trial, and the trial time for new specifications will be about the same as the learning time. To reduce this risk, it is desirable to carry out pretrial trials of leaves that can realize a wide range of circuit structures, not just typical values, so as to be able to adapt to as many ranges of specifications as possible, and to have the circuit specifications learned as much as possible. In other words, in pre-learning (1) Trial of several patterns (MINIMAL / TYPICAL / MAX) from the viewpoint of specifications Here, the user determines the specification pairs that are considered critical. For example, it can be just the key specifications, such as gain and input range. Dependencies are also taken into account. In effect, this gives a certain range of performance that can be achieved with this architecture using the corresponding PDK. The risk here is that if no structure exists that satisfies this condition, the search will never terminate, and termination will depend on the limit of the number of trials. (2) To increase the comprehensiveness from the viewpoint of structure so as to provide a rough overview of the circuit structure. In this case, the combination is determined arbitrarily by selecting from the types of each cell. Note that in this case, the target specifications are unrelated, and the specifications become the results.

[0048] Next, another embodiment of the present invention will be described. Regarding the timing of determining the target specifications, (1) When searching the Monte Carlo tree structure, there is a problem in that the results of the target specification cannot be determined until the end. (2) Regarding the expectation of predicting an arbitrary value of a trial at the level of each node, as shown in Fig. 6, by accumulating the MAX value (maximum value) for each operating specification across all lower nodes in the FEATURE of the attribute information of each node, it is possible to perform a preferential search for a new target value. Fig. 6 shows an example of an operational amplifier, where each node holds the maximum values ​​across all lower nodes for gain, phase margin, area, and power. This makes it possible to know that it is difficult to obtain performance above the maximum values ​​held in the node on a route that passes through the node, without reaching a leaf node and performing parameter optimization. -Update the MAX value of the upper node during back annotation at the end of the search. During search, nodes close to the new target value are searched for preferentially but probabilistically. Changes to the UCB1 evaluation formula This makes it possible to predict the expected value of each target value at each subnode by inputting the trial results for each classification in advance. (3) FEATURE depends on the target specifications of the circuit architecture.

[0049] Next, an example of the control flow of the Monte Carlo search according to this embodiment will be described. Here, a child node is selected according to formula (2). New target values ​​during exploration: Target1, Target2, Target3... (T1, T2, T3...) Accumulative achievement target value during exploration: Accumulate1, Accumulate2, Accumulate3... (A1 A2 A3...) Satisfaction value between T and A fi(Ti,Ai)=0~1 (The number of target values ​​is m, 1 is satisfied, 0 is not achieved, and the values ​​in between are transformed, for example, by linear / sigmoid.) Example: Area T1=10 A1=20 f1(T1,A1)=0 T1=10 A1=12 f1(T1,A1)=0.2 Gain T2=500 A2=600 f2(T2,A2)=1

[0050] TIFF2025032441000003.tif25170

[0051] Expansion / Search Selection Decision (1) During Monte Carlo search for target value X · w / n is updated during the search ·If Ai is a value that exceeds (is better than) the current Ai during backpropagation from the leaf node, it will be overwritten. In the above multiple search, the cost is calculated according to formula (2). The target value and device values ​​(L / W / R (resistance) / C (capacitor)) for each leaf node are stored in a table. How to use this table If the inference (actual target value) is the same as the learned target value, it can be used again without the need for optimization. If the target value is close, it can be used as the initial value. (2) The Monte Carlo search for the target value X is completed. · w / n of all nodes is initialized. · The Ai of all nodes is stored. (3) Start searching for a new target value Y In equation (2), w / n starts from an initial value, and after γ, it proceeds in the same manner while referring to the numerical values ​​of each node.

[0052] In the above embodiment, an example of synthesizing cells registered in a library is shown, but the present invention is not limited to this and can be applied to existing circuits. Migration including cell-based topology generation is possible by extracting AnaCell from an existing circuit and executing Monte Carlo tree structure learning and search for the AnaCell group. This makes it possible to optimize only parameters of the same circuit topology as migration using AI, and differentiate from existing tools. Specifically, AnaCell / LogiCell are extracted from an existing circuit, and the user selects the cell to be replaced. After that, the process is the same as that of 1 to 6 above.

[0053] In the above embodiment, an operational amplifier is used as the target circuit, but this is only one example, and the present invention can be applied to other circuit generation. The parameter optimization can be applied not only to operational amplifiers, but also to LDOs, comparators, and some blocks of ADCs.

[0054] 7 is a diagram showing a configuration example of a SAR ADC (successive approximation type analog-digital converter). As shown in the figure, the SAR ADC includes a circuit for sampling / holding an analog input signal, a successive approximation register (SAR), a D / A converter (RDAC) for converting the digital value of the successive approximation register to an analog value, a comparator (COMP) for comparing the sampled voltage with the output voltage of the RDAC, a conversion result register (Register) for holding the digital value of the successive approximation register, and Logic 300 for arithmetically processing the digital value of the successive approximation register and outputting EOCB.

[0055] Logic300 can be configured with any of Logic-1, Logic-2, Logic-3, and Logic-4, as shown in Figures 8(A), (B), (C), and (D). Therefore, by constructing a Monte Carlo tree structure of the SAR ADC, it is possible to find the optimal combination of the internal circuit of the SAR ADC and LogiCell (cell of Logic300) by Monte Carlo search.

[0056] FIG. 9 is a diagram showing an example of a Monte Carlo tree structure of a SAR ADC. In the diagram, dashed lines between nodes indicate non-selection, and solid lines between nodes indicate selection. SAR ADC-1, SAR ADC-2, and SAR ADC-3, which are root nodes (target circuits), are connected to nodes corresponding to Logic, AMP, RDAC, COMP, and Register in the next layer. This connection is non-selection. Logic is connected to nodes corresponding to Logic-1, Logic-2, and Logic-3 in the next layer. This connection is selection. Logic-1, Logic-2, and Logic-3 are connected to MUX (multiplexer) in the next layer. This connection is non-selection. MUX is connected to leaf nodes corresponding to LogiCell 1, LogiCell 2, Dynamic Cell, StCell (standard cell), and AnaCell in the next layer. These connections are selection.

[0057] As in the above-described embodiment, various target specifications within a determined range are provided to the controller 160, and the controller 160 performs measurements using a test bench for those target specifications, updates the number of trials n and the cumulative value w based on the results of the test bench measurements, and searches for an optimal combination of cells using a Monte Carlo tree structure.

[0058] When a SAR-ADC designer inputs a target specification via the input unit 110, the controller 160 searches for a route that is an optimal combination of cells based on the n number of trials and the w cumulative value of the Monte Carlo tree structure. For example, in the example of FIG. 9, a route is searched for that passes from SAR ADC-1 through Logic, Logic-1, MUX, and LogiCell2. The controller 160 generates a SAR ADC by combining the cells on the route, and outputs the circuit topology and cell details of the generated SAR ADC to the output unit 120.

[0059] Although the preferred embodiments of the present invention have been described in detail above, the present invention is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the gist of the invention described in the claims. [Explanation of symbols]

[0060] 100: Circuit generation device 110: Input unit 120: Output section 130: Communication section 140:ROM / RAM 150:Storage section 160: Controller 170: Cloud server

Claims

1. An electronic device having a circuit generation function, a searching means for assigning cells, which are constituent units of a circuit and have a specific function, to nodes in each layer of a Monte Carlo tree structure and searching for a root in the Monte Carlo tree structure; a generating means for generating a target circuit by combining a plurality of cells based on the searched route; An electronic device having:

2. Each node of the Monte Carlo tree holds w cumulative values ​​and n number of trials, 2. The electronic device according to claim 1, wherein the searching means selects a node based on w cumulative value and n number of trials, and searches for a route from a root node to a leaf node.

3. 2. The electronic device according to claim 1, wherein the search means executes a test bench for evaluating performance of the generated target circuit when searching for a route from the root node to a leaf node, and updates the w-accumulation value of each node according to a test bench result.

4. 4. The electronic device according to claim 3, wherein the search means determines whether a measured value of the performance of the target circuit obtained by the test bench satisfies an operational specification of the target circuit input by a user, and adds points to the w cumulative value when the measured value satisfies the operational specification, and does not add points to the w cumulative value or subtracts points when the measured value does not satisfy the operational specification.

5. 4. The electronic device according to claim 3, wherein said searching means adds points to the n-trial count of each node on the route when searching the route from the root node to a leaf node.

6. Each node of the Monte Carlo tree further maintains a cumulative maximum value of measurements of the performance of the target circuit obtained by the test bench; The electronic device according to claim 2 , wherein the search means searches for a route based on the maximum cumulative value.

7. 2. The electronic device according to claim 1, wherein the searching means assigns a cell registered in a library to each node of a Monte Carlo tree structure.

8. The electronic device according to claim 1 , wherein the library includes cells of analog circuits, cells of digital circuits, and cells showing connections of multiple elements.

9. 1. A method for generating a circuit in an electronic device, comprising: A step of assigning cells, which are building blocks of a circuit and have a specific function, to nodes in each layer of a Monte Carlo tree structure and searching for a root in the Monte Carlo tree structure; generating a target circuit by synthesizing a plurality of cells based on the searched route; A circuit generating method comprising the steps of:

10. A circuit generation program executed by an electronic device, A step of assigning cells, which are building blocks of a circuit and have a specific function, to nodes in each layer of a Monte Carlo tree structure and searching for a root in the Monte Carlo tree structure; generating a target circuit by synthesizing a plurality of cells based on the searched route; A circuit generation program having the above construction.

Images