Circuit device and physical quantity sensor

Abstract

To solve the problem of the characteristics of physical quantity sensors varying when the frequencies of clock signals differ.SOLUTION: A circuit device has an A / D conversion circuit that performs A / D conversion on a signal output from a sensor element, a signal processing circuit that performs digital filter processing on a digital signal output from the A / D conversion circuit, a storage circuit that stores individual data corresponding to a sampling frequency of digital filter processing, and a characteristic determination unit that determines the characteristics of the digital filter processing on the basis of the individual data.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a circuit device and a physical quantity sensor. [Background technology]

[0002] Conventionally, there are known techniques for preventing interference between different signals used inside a physical quantity sensor. For example, Patent Document 1 discloses a configuration in which, in a physical quantity sensor in which a sensor element is driven by a drive signal and a clock signal is generated by PLL operation to operate a circuit, j×fdr≠fck / i (i and j are integers equal to or greater than 1) is satisfied, where fdr is the frequency of the drive signal for the sensor element and fck is the frequency of the clock signal. With this configuration, in a physical quantity sensor using sensor elements with individual differences, it is possible to prevent interference between the drive frequency of the drive circuit and the oscillation frequency of the built-in oscillation circuit. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2018-163037 A Summary of the Invention [Problem to be solved by the invention]

[0004] In the conventional technology, the frequency of the drive signal is determined according to each sensor element, and the frequency of the clock signal is determined according to the frequency of the drive signal, so that the frequency of the clock signal is also determined depending on the individual difference of the sensor element. Therefore, the frequency of the clock signal may differ for each sensor element. The frequency of the clock signal affects the frequency of digital processing, such as the sampling frequency of A / D conversion. The frequency of digital processing may affect the characteristics of various digital processes, so if the frequency of the clock signal differs, the characteristics of the physical quantity sensor will vary. [Means for solving the problem]

[0005] The circuit device includes an A / D conversion circuit that performs A / D conversion on a signal output from a sensor element, a signal processing circuit that performs digital filter processing on the digital signal output from the A / D conversion circuit, a memory circuit that stores individual data corresponding to a sampling frequency of the digital filter processing, and a characteristic determination unit that determines the characteristics of the digital filter processing based on the individual data.

[0006] The physical quantity sensor includes a sensor element, an A / D conversion circuit that performs A / D conversion on a signal output from the sensor element, a signal processing circuit that performs digital filter processing on the digital signal output from the A / D conversion circuit, a memory circuit that stores individual data corresponding to a sampling frequency of the digital filter processing, and a characteristic determination unit that determines characteristics of the digital filter processing based on the individual data. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a functional block diagram of a physical quantity sensor according to a first embodiment. [Diagram 2] FIG. 13 is a diagram showing the 1st-order coefficients and the 0th-order coefficients associated with combinations of orders and cutoff frequencies. [Diagram 3] FIG. 1 is a block diagram showing the configuration of a DSP. [Figure 4] FIG. 4 is a diagram showing an example of a filter configuration. [Diagram 5] FIG. 1 illustrates an example of the configuration of an IIR filter. [Figure 6] FIG. 13 is a diagram illustrating an example of the gain of an IIR filter. [Figure 7] FIG. 13 is a diagram showing the relationship between the sampling frequency and the filter coefficient. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Preferred embodiments of the present invention will be described in detail below with reference to the drawings. Note that the embodiments described below do not unduly limit the contents of the present invention described in the claims. Furthermore, not all of the configurations described below are necessarily essential components of the present invention. Below, a physical quantity sensor (angular velocity sensor) that detects angular velocity as a physical quantity will be described as an example.

[0009] 1. First embodiment FIG. 1 is a functional block diagram of a physical quantity sensor of the first embodiment. The physical quantity sensor 1 of the first embodiment includes a sensor element 2 and a circuit device 3. In this embodiment, the sensor element 2 is an angular velocity sensor. The angular velocity sensor can be realized by various known configurations. For example, the sensor element 2 can be configured by an element that outputs a signal indicating vibration based on the Coriolis force acting on the vibrating arm. Of course, the shape of the sensor is not limited, and sensors of various shapes such as a double T type, a tuning fork type, and an H type can be used.

[0010] The sensor element 2 has an input terminal to which the drive signal DRV is input from the drive circuit 20, and an output terminal to which a feedback signal DI is output to the drive circuit 20. In this embodiment, the input terminal is electrically connected to a pad DS. The output terminal is electrically connected to a pad DG. The sensor element 2 has two detection signal output terminals that output detection signals, and each detection signal output terminal is electrically connected to a pad S1, S2.

[0011] The circuit device 3 in this embodiment includes a reference voltage circuit 10, a drive circuit 20, a detection circuit 30, a digital processing unit 40, an oscillation circuit 50, a storage unit 60, an interface circuit 70, a temperature sensor 80, an A / D conversion circuit 82, a temperature correction value calculation unit 84, and a characteristic determination unit 90. The circuit device 3 may be, for example, a one-chip integrated circuit (IC). Note that the circuit device 3 may be configured such that some of these elements are omitted or modified, or other elements are added.

[0012] The reference voltage circuit 10 generates constant voltages such as reference voltages VR1 and VR2 and constant currents from the power supply voltage supplied from the VDD terminal of the circuit device 3, and supplies them to the drive circuit 20 and the detection circuit 30.

[0013] The drive circuit 20 drives the sensor element 2. The drive circuit 20 is electrically connected to the sensor element 2 via pads DS and DG. The drive circuit 20 receives a feedback signal DI from the sensor element 2 via the pad DG, and drives the sensor element 2 by outputting a drive signal DRV corresponding to the feedback signal DI via the pad DS. The drive circuit 20 also generates a detection signal SDET in phase with the drive signal DRV, and outputs it to the detection circuit 30.

[0014] The drive circuit 20 can be realized by various known circuits. For example, the drive circuit 20 can be realized by a configuration including a current-voltage converter (I / V converter), a gain control circuit, and two comparators. That is, the AC voltage signal output from the current-voltage converter is converted by each comparator to become the drive signal DRV and the detection signal SDET. The gain control circuit controls the reference voltage of the comparator so as to maintain the amplitude of the AC voltage signal input to the comparator that generates the drive signal DRV at a constant value.

[0015] The detection circuit 30 detects the angular velocity component contained in the AC charge input from the sensor element 2 via the S1 and S2 terminals, and outputs a detection signal Sr which is an analog signal with a voltage level according to the magnitude of the angular velocity. The detection circuit 30 can be realized by various known circuits. For example, the detection circuit 30 can be realized by a configuration including a QV amplifier, a differential amplifier, a variable gain amplifier (PGA: Programmable Gain Amplifier), and a synchronous detection circuit. The synchronous detection circuit synchronously detects the angular velocity component contained in the signal output from the variable gain amplifier using the detection signal SDET.

[0016] The storage unit 60 has a register 61 and a non-volatile memory 62. The register 61 stores addresses and various data used in communication with an external device via the interface circuit 70. The register 61 also stores angular velocity data and angle data output from the DSP 44, which will be described later.

[0017] The non-volatile memory 62 stores various adjustment data and correction data for the drive circuit 20 and the detection circuit 30, and various information for establishing communication with the outside via the interface circuit 70. The non-volatile memory 62 can be configured as, for example, a MONOS (Metal Oxide Nitride Oxide Silicon) type memory or an EEPROM (Electrically Erasable Programmable Read-Only Memory).

[0018] The interface circuit 70 is electrically connected to the XCS terminal, the SCLK terminal, the SDI terminal, and the SDO terminal, and is a circuit for communicating with an external device via these terminals. In communication via the interface circuit 70, the external device functions as a master, and the physical quantity sensor 1 (circuit device 3) functions as a slave. The external device can write data to a specified address in the register 61, read data from a specified address in the register 61, and send various commands to control the operation of the circuit device 3 via the interface circuit 70.

[0019] The interface circuit 70 may function as either an SPI (Serial Peripheral Interface) interface circuit or an I2C (Inter-Integrated Circuit) interface circuit. For example, when the XCS terminal is at a low level, the interface circuit 70 functions as an SPI interface circuit, a clock signal is input via the SCLK terminal, a data signal is input via the SDI terminal, and a data signal is output via the SDO terminal. When the XCS terminal is at a high level, the interface circuit 70 functions as an I2C interface circuit, a clock signal is input via the SCLK terminal, and a data signal is input / output via the SDI terminal.

[0020] Communication with an external device via the interface circuit 70 is performed based on various information stored in the register 61. The external device can read angular velocity data from a predetermined address in the register 61 via the interface circuit 70. In this way, the physical quantity sensor 1 (circuit device 3) is configured to be able to output angular velocity data in response to a request from the external device.

[0021] In this embodiment, the frequency of the clock signal CLK is determined according to the inherent frequency of the sensor element 2 when the physical quantity sensor 1 is manufactured, and the sampling frequency fs in the A / D conversion described later is determined according to the frequency of the clock signal CLK. Specifically, when the sensor element 2 is driven at the time of shipment from the factory, as in the above-mentioned conventional technology, if the frequency of the drive signal used to drive the sensor element 2 is fdr and the frequency of the clock signal CLK is fck, then j×fdr≠fck / i (i and j are integers equal to or greater than 1). When the frequency fck of the clock signal is determined, the frequency of the clock signal fck or a frequency obtained by multiplying the frequency of the clock signal CLK is set as the sampling frequency fs. The frequency of the clock signal CLK and the sampling frequency fs are stored in the non-volatile memory 62, and the sampling frequency fs is stored at a predetermined address of the register 61. The user can read out the sampling frequency fs stored at the address using an external device.

[0022] Furthermore, in this embodiment, digital filtering is performed by the DSP 44, which will be described later. In this embodiment, the digital filtering includes processing by an infinite impulse response (IIR) filter 44c and a second filter 44d. The IIR filter 44c can change its filter characteristics by changing a filter coefficient k. The non-volatile memory 62 stores data for determining the filter coefficient k.

[0023] Specifically, the filter coefficient k is calculated by the formula k=a×(sampling frequency fs)+b, and the first-order coefficient a and the zeroth-order coefficient b of the formula are stored in the non-volatile memory 62. When using the IIR filter 44c, the user sets the order n of the filter and the cutoff frequency fc required for the filter. Since the filter characteristics differ depending on the setting, in this embodiment, the first-order coefficient a and the zeroth-order coefficient b are configured to change depending on the setting of the IIR filter 44c. FIG. 2 shows an example in which the first-order coefficient a and the zeroth-order coefficient b correspond to a combination of the order n and the cutoff frequency fc of the IIR filter 44c. Such data is stored in the non-volatile memory 62.

[0024] A user writes the order n and sampling frequency fs that the user desires to use to a specified address using an external device. In this case, the first-order coefficient a and the zeroth-order coefficient b corresponding to the order n and sampling frequency fs are transferred from the non-volatile memory 62 to the register 61, and the filter coefficient k of the IIR filter 44c is determined by the above-mentioned formula based on the first-order coefficient a and the zeroth-order coefficient b. The above process will be described in detail later.

[0025] The oscillation circuit 50 generates a clock signal CLK and outputs the clock signal CLK to the digital processing unit 40. The oscillation circuit 50 includes circuits such as a PLL (Phase Locked Loop) circuit and a DLL (Digital Locked Loop) circuit, and outputs the clock signal CLK at a frequency stored in a storage unit 60. That is, the frequency of the clock signal CLK is stored in a non-volatile memory 62, and when the physical quantity sensor 1 is started, the frequency is transferred to a register 61. The oscillation circuit 50 acquires the frequency stored in the register 61, and generates an oscillation signal at the frequency to generate the clock signal CLK.

[0026] The digital processing unit 40 includes an A / D (Analog to Digital) conversion circuit 42 and a DSP (Digital Signal Processor) 44 as a signal processing circuit. The A / D conversion circuit 42 operates at a sampling frequency fs synchronized with a clock signal CLK output by an oscillation circuit 50, and converts the output signal of the detection circuit 30 into a digital signal (angular velocity data) Da and outputs it. The sampling frequency fs, which is a period at which the A / D conversion circuit 42 converts an analog signal into a digital signal, may be the same as the frequency of the clock signal CLK, or may be a frequency obtained by multiplying the frequency of the clock signal CLK. The A / D conversion circuit 42 can be realized by various known circuits, and may be, for example, a delta-sigma type or successive approximation type A / D conversion circuit.

[0027] The DSP 44 operates in synchronization with the clock signal CLK output by the oscillation circuit 50, and performs digital processing, including digital filter processing, on the digital signal (angular velocity data) Da output by the A / D conversion circuit 42. The configuration of the DSP 44 will be described later, but the digital processing includes digital filter processing that passes signals in a specific frequency band, as well as digital processing that corrects fluctuations in the angular velocity data due to temperature. The value of the angular velocity data that has been subjected to these digital processes represents the angular velocity detected by the sensor element 2, and is updated sequentially at a predetermined rate. Furthermore, the DSP 44 may perform digital processing that corrects the offset of the zero point of the angular velocity data, and digital processing that calculates the angular velocity data by time integration (addition) of the sequentially updated angular velocity data. The angular velocity data output by the DSP 44 is stored in a register 61, and is transferred to an external device or the like via an interface circuit 70, for example.

[0028] The temperature sensor 80 is a sensor that outputs a signal (temperature signal) with a voltage level according to the temperature around it, and may be a positive polarity sensor that outputs a higher output voltage as the temperature increases, or a negative polarity sensor that outputs a lower output voltage as the temperature increases. The temperature sensor 80 may be, for example, a circuit that outputs a voltage proportional to absolute temperature (PTAT (Proportional To Absolute Temperature) voltage). The temperature signal output from the temperature sensor 80 is input to an A / D conversion circuit 82.

[0029] The A / D conversion circuit 82 operates in synchronization with the clock signal CLK output by the oscillation circuit 50, and converts the signal output by the temperature sensor 80 into a digital signal (temperature data) and outputs it. A sampling frequency fs, which is a period at which the A / D conversion circuit 82 converts an analog signal into a digital signal, may be the same as the frequency of the clock signal CLK, or may be a frequency obtained by multiplying the frequency of the clock signal CLK. The A / D conversion circuit 82 can be realized by various known circuits, and may be, for example, a delta-sigma type or successive approximation type A / D conversion circuit. The signal output from the A / D conversion circuit 82 is input to a temperature correction value calculation unit 84.

[0030] The temperature correction value calculation unit 84 calculates and outputs the temperature correction value Ta based on the signal output by the A / D conversion circuit 82. The temperature correction value Ta may be calculated by various methods, such as a method of calculating the temperature correction value Ta by a function with temperature as a variable, or a method of acquiring the temperature correction value Ta corresponding to the temperature based on information stored in the storage unit 60. The temperature correction value Ta output from the temperature correction value calculation unit 84 is input to the DSP 44. The temperature correction value calculation unit 84 may be any circuit that performs digital processing, and may be realized by various integrated circuits such as a CPU, or may be realized by an FPGA (Field Programmable Gate Array), for example.

[0031] The characteristic determination unit 90 is a digital circuit that determines the characteristics of the digital filter processing based on the individual data. Specifically, the characteristic determination unit 90 is a digital circuit that performs processing to determine the filter characteristics of the IIR filter 44c (described later) included in the DSP 44. The characteristic determination unit 90 acquires, from the register 61, the first-order coefficient a and the zeroth-order coefficient b corresponding to the order n and the cutoff frequency fc, which are the settings of the IIR filter 44c set by the user. The characteristic determination unit 90 also acquires, from the register 61, the sampling frequency fs as individual data unique to the sensor element 2. Then, the characteristic determination unit 90 assigns the acquired first-order coefficient a, zeroth-order coefficient b, and sampling frequency fs to the formula k=a×(sampling frequency fs)+b to determine the filter coefficient k. The determined filter coefficient k is input to the IIR filter 44c of the DSP 44. The characteristic determination unit 90 may be any circuit that performs digital processing, and may be realized, for example, by various integrated circuits such as a CPU, or may be realized by an FPGA or the like.

[0032] 1.1 DSP Configuration Next, the configuration of the DSP 44 will be described in detail. FIG. 3 is a block diagram showing the configuration of the DSP 44. The DSP 44 includes a temperature correction unit 44a, a notch filter 44b, an IIR filter 44c, and a second filter 44d. The temperature correction unit 44a corrects the digital signal Da based on a temperature correction value Ta output by a temperature correction value calculation unit 84. The temperature correction value Ta is a value for offsetting fluctuations in the output of the sensor element 2 due to temperature, and in this embodiment, the temperature correction unit 44a corrects the digital signal Da by executing a predetermined calculation based on the temperature correction value Ta, for example, Da+Ta, on the digital signal Da.

[0033] The notch filter 44b is a digital filter that attenuates and outputs signals in a specific frequency band among the input signals. The notch filter 44b may be used for various purposes, for example, to attenuate signals in a frequency band of noise (e.g., signals at detuning frequencies) that may occur under specific conditions in the sensor element 2. The notch filter 44b may be realized in various configurations, for example, by adjusting the filter coefficients of the filter shown in FIG. 4.

[0034] The filter shown in FIG. 4 is a filter formed by repeating two units. The first unit is formed of elements 44b1 to 44b11. The second unit is formed of elements 44b12 to 44b22. The first unit and the second unit are connected in series. In the example shown in FIG. 4, the delay units 44b5 and 44b6 give a unit delay to the input signal and output the signal. The multiplication units 44b7 to 44b11 multiply the input signal by a coefficient and output the result. The coefficients of the multiplication units 44b7 to 44b11 are a10 to b12 shown for the multiplication units 44b7 to 44b11 in FIG. 4. The addition units 44b1 to 44b4 add the input signals shown in FIG. 4 with the codes shown in the figures, and output the results.

[0035] 4, the adder 44b1 adds the input signal and a signal obtained by making the fed-back signal a negative signal, and outputs the result. The signal output from the adder 44b1 is delayed by delay units 44b5 and 44b6. The signal delayed by delay unit 44b5 is input to multiplier units 44b7 and 44b10 and delay unit 44b6. The signal delayed by delay unit 44b6 is input to multiplier units 44b8 and 44b11.

[0036] The signals input to the multipliers 44b7 and 44b8 are multiplied by coefficients b11 and b12, the results are added by the adder 44b2, and the result is input to the adder 44b1. The signals input to the multipliers 44b10 and 44b11 are multiplied by filter coefficients a11 and a12, the results are added by the adder 44b4, and the result is input to the adder 44b3. The adder 44b3 receives a signal that has been multiplied by the filter coefficient a10 by the multiplier 44b9 with respect to the output of the adder 44b1. The adder 44b3 outputs the sum of both input signals.

[0037] The second unit is composed of the same elements as the first unit. However, the filter coefficients used may be different. The filter shown in FIG. 4 can have various characteristics by adjusting the filter coefficients a10, a11, a12, b11, b12, a20, a21, a22, b21, and b22. In this embodiment, the filter coefficients are determined in advance so that the filter shown in FIG. 4 functions as a notch filter that attenuates signals in a specific frequency band. These filter coefficients are stored in the non-volatile memory 62, and when the physical quantity sensor 1 is started, the filter coefficients are transferred to the register 61. Then, the filter coefficients stored in the register 61 are acquired by the notch filter 44b, and the filter coefficients of the notch filter 44b are determined.

[0038] The IIR filter 44c is a filter that performs digital filtering to pass signals in a specific frequency band among the input signals. The IIR filter 44c may be used for various purposes, such as passing signals in a frequency band required for performing the predetermined processing and attenuating signals in other frequency bands when the angular velocity is measured by the sensor element 2 and a predetermined processing is performed based on the measured angular velocity. That is, the IIR filter 44c may be used as a low-pass filter, a high-pass filter, or a band-pass filter.

[0039] The IIR filter 44c may be realized in various configurations, and is configured, for example, by repeating the unit filter shown in FIG. 5. The example shown in FIG. 5 shows one unit of the filter that configures the IIR filter 44c. The one unit filter includes adders 44c1-44c3, a delay unit 44c4, and multipliers 44c5 and 44c6. The adders 44c1-44c3 add the illustrated codes to the input signals, add them, and output them. The delay unit 44c4 gives a unit delay to the input signal and outputs it. The multipliers 44c5 and 44c6 multiply the input signal by a coefficient and output it. The coefficients of the multipliers 44c5 and 44c6 are k and 0.5 shown for each of the multipliers 44c5 and 44c6 in FIG. 5.

[0040] Therefore, in the example shown in FIG. 5, the adder 44b1 adds the input signal and a signal obtained by making the fed back signal (the output signal of the delay unit 44c4) a negative signal, and outputs the result. The output signal is multiplied by k by the multiplier 44c5 and input to the adder 44c2. The adder 44c2 adds the output signal of the multiplier 44c5 and the fed back signal (the output signal of the delay unit 44c4), and outputs the result. The adder 44c3 adds the output signal of the adder 44c2 and the fed back signal (the output signal of the delay unit 44c4), and outputs the result. The output of the adder 44c3 is then multiplied by 0.5 by the multiplier 44c6 to become the output signal of the IIR filter 44c.

[0041] The IIR filter 44c is a digital filter configured by serially connecting a plurality of unit filters shown in Fig. 5. The transfer function of such a digital filter can be expressed by the following equation (1).

number

[0042] When using the sensor element 2, various needs may arise for the user. For example, there may be a situation in which the information to be extracted from the signal output from the sensor element 2 is information of a specific frequency band, and the information of the specific frequency band is unnecessary. This is because the information of the unnecessary frequency band becomes noise. In this case, the user needs to extract information of a desired frequency band, that is, to select a frequency band that has a desired gain. There may also be a need to set the phase change characteristic and group phase change characteristic when the IIR filter 44c is activated to a desired range.

[0043] Therefore, in this embodiment, the user can set the filter characteristics of the IIR filter 44c. Specifically, the user can specify the order n and the cutoff frequency fc, and set the IIR filter 44c to have the filter characteristics desired by the user. In other words, by specifying the cutoff frequency fc, the frequency at which the gain is attenuated by 3 dB in the IIR filter 44c can be specified, and the user can specify the desired frequency band. Furthermore, even if the filter has the same cutoff frequency fc, if the order n is made higher, the gain attenuation characteristics become steeper, so the user can specify the desired attenuation characteristics.

[0044] As described above, in this embodiment, the characteristics of the IIR filter 44c are specified by the order n and the cutoff frequency fc. Here, the filter characteristics are determined by the transfer function shown in the above-mentioned formula (1), and 1 / z included in the transfer function depends on the sampling frequency fs. FIG. 6 is a diagram illustrating the gain of the second-order IIR filter 44c. FIG. 6 is a graph with the vertical axis representing gain (dB) and the horizontal axis representing frequency (Hz), and shows the gain by the filter of the transfer function shown in formula (1) for a plurality of sampling frequencies fs. The solid line indicates the gain when the sampling frequency fs is 11000 Hz, the dashed line indicates the gain when the sampling frequency fs is 12000 Hz, the dashed line indicates the gain when the sampling frequency fs is 12500 Hz, and the dashed line indicates the gain when the sampling frequency fs is 13000 Hz.

[0045] As shown in Fig. 6, when the sampling frequency fs is different, the filter characteristics are different even for IIR filters 44c with the same order n. Therefore, even if the filter coefficient k is determined by setting the frequency f1 at which the gain is attenuated by 3 dB when the sampling frequency fs is 11000 Hz as the cutoff frequency fc, if the sampling frequency fs changes, the gain may not be attenuated by 3 dB at the frequency f1 when the same filter coefficient k is used. In this way, the situation in which the filter characteristics depend on the sampling frequency fs may also occur in the phase delay characteristics and group delay characteristics.

[0046] Particularly, in this embodiment, the sampling frequency fs is a value determined according to the frequency fck of the clock signal, and the frequency fck of the clock signal is determined depending on the frequency fdr of the drive signal of the sensor element 2. Therefore, the sampling frequency fs is individual data that differs for each individual sensor element 2, and different individual physical quantity sensors 1 can operate at different sampling frequencies fs. For this reason, the sampling frequency fs is a value that cannot be determined by the user.

[0047] In this way, in a situation where the sampling frequency fs may differ for each individual, if a fixed filter coefficient k corresponding to the order and cutoff frequency fc is used in common for all individuals, the filter characteristics desired by the user may be achieved in one individual, but not in another individual.

[0048] In this embodiment, the filter coefficient k is determined according to the order n, the cutoff frequency fc, and the sampling frequency fs, and the filter coefficient k is calculated so that the characteristics of the IIR filter 44c are constant regardless of the sampling frequency fs. For this calculation, the inventors of the present application have found that the filter coefficient k can be described as a function of the sampling frequency fs.

[0049] Specifically, the inventors of the present application found that the filter coefficient k changes linearly with respect to the sampling frequency fs in the assumed frequency band. Therefore, in this embodiment, the characteristics determination unit 90 is configured to determine the filter coefficient k by a linear expression of the sampling frequency.

[0050] FIG. 7 is a diagram showing the relationship between the sampling frequency fs and the filter coefficient k, with the horizontal axis representing the sampling frequency fs (Hz) and the vertical axis representing the filter coefficient k. Note that FIG. 7 shows the value of the filter coefficient k in a part (11000 Hz to 13000 Hz) of the frequency band of the sampling frequency fs assumed in this embodiment. Also, in FIG. 7, the filter coefficient k set so that the cutoff frequency fc, which is the filter characteristic of the IIR filter 44c, is the same (within a range in which the error is equal to or less than a predetermined standard), is connected by a straight line. For example, the plot indicated by the symbol C1 shows the value of the filter coefficient k for making the cutoff frequency fc of the IIR filter 44c a certain common value for each sampling frequency fs.

[0051] In Fig. 7, multiple plots are connected by multiple straight lines, and each straight line represents a different combination of the order n and the cutoff frequency fc of the IIR filter 44c. Specifically, the order n is changed to 2, 3, and 4, and the cutoff frequency fc is changed to 1, 10, 25, 50, 100, 200, 400, and 500 Hz, and each combination is plotted as shown in Fig. 7. Note that in Fig. 7, the straight lines that overlap on the drawing are omitted and are not shown.

[0052] 7, for each combination of an arbitrary order n and cutoff frequency fc, the filter coefficient k for making the filter characteristic of the IIR filter 44c a common value changes approximately linearly with respect to the change in the sampling frequency fs. Therefore, in this embodiment, the characteristic determining unit 90 is configured to determine the filter coefficient k by a linear expression of the sampling frequency.

[0053] Specifically, the characteristic determination unit 90 determines the filter coefficient k based on the formula k=a×(sampling frequency fs)+b. The sampling frequency fs is stored in the non-volatile memory 62, and is transferred and stored in the register 61 after the physical quantity sensor 1 is started. Therefore, the characteristic determination unit 90 refers to the register 61 to identify the sampling frequency fs, which is individual data.

[0054] The first-order coefficient a and the zeroth-order coefficient b depend on the order n and the cutoff frequency fc. Therefore, the first-order coefficient a and the zeroth-order coefficient b are stored in the non-volatile memory 62 in association with the combination of the order n and the cutoff frequency fc, as shown in Fig. 2 above. In addition, the user determines the order n and the cutoff frequency fc that he or she wishes to use, for example, by using a simulator, and writes the desired order n and sampling frequency fs to a predetermined address of the register 61 using an external device.

[0055] The characteristic determination unit 90 refers to the register 61 and transfers the first-order coefficient a and the zeroth-order coefficient b corresponding to the combination of the order n and the cutoff frequency fc from the non-volatile memory 62 to the register 61. The characteristic determination unit 90 refers to the register 61 and identifies the transferred first-order coefficient a and zeroth-order coefficient b. Then, the characteristic determination unit 90 acquires the filter coefficient k by substituting the acquired sampling frequency fs, first-order coefficient a, and zeroth-order coefficient b into the calculation formula k=a×(sampling frequency fs)+b.

[0056] The characteristic determination unit 90 outputs the filter coefficient k to the IIR filter 44c. The characteristic determination unit 90 also refers to the register 61, identifies the order n, and outputs the order n to the IIR filter 44c. When the IIR filter 44c acquires the filter coefficient k and the order n, the gain of the multiplication unit 44c5 is set to the acquired filter coefficient k, and the filter after the setting is set to be repeated n times. As a result, the filter coefficient k according to the sampling frequency fs set in accordance with the individual sensor element 2 is determined, the order of the IIR filter 44c becomes the order n specified by the user, and the filter characteristic becomes the cutoff frequency fc specified by the user.

[0057] The second filter 44d is a filter that performs digital filtering (second digital filtering) to pass signals in a specific frequency band among the input signals. In this embodiment, the user can determine the filter characteristics of the second filter 44d. The second filter 44d may be used for various purposes, for example, to attenuate a frequency band that remains even after the digital filtering by the IIR filter 44c is performed. More specifically, the IIR filter 44c may function as a low-pass filter and the second filter 44d may function as a high-pass filter, so that the two filters together form a band-pass filter.

[0058] The second filter 44d may be realized by various filters capable of adjusting the filter characteristics, for example, an IIR filter. More specifically, the second filter 44d may be configured by the first unit of the filter shown in Fig. 4. Of course, the second filter 44d may have the same configuration as that shown in Fig. 4 in which the first unit and the second unit are connected in series, or the number of units connected in series may be increased.

[0059] In any case, the second filter 44d can have various filter characteristics by adjusting the filter coefficients. For example, when the second filter 44d is configured by the first unit shown in Fig. 4, the second filter 44d can have various characteristics by adjusting the filter coefficients a10, a11, a12, b11, and b12.

[0060] In this embodiment, the user can determine the filter coefficients of the second filter 44d. That is, the user determines the filter coefficients in order to make the characteristics of the second filter 44d into desired characteristics. The filter coefficients can be determined by various methods, and for example, the user can determine the filter coefficients by using simulator software or the like that runs on an external device.

[0061] Specifically, the transfer function can be determined based on the digital circuit configuration of the second filter 44d. For example, when the second filter 44d is configured by the first unit shown in FIG. 4, the transfer function is expressed by the following formula (2).

number

[0062] The user adjusts the filter coefficient values ​​in the transfer function shown in equation (2) and simulates the gain, phase change characteristics, and group phase change characteristics in an external device. However, as mentioned above, 1 / z included in the transfer function depends on the sampling frequency fs. Therefore, in order to perform an accurate simulation, the user needs to obtain the sampling frequency fs, which is individual data.

[0063] In this embodiment, the sampling frequency fs, which is individual data, can be read out by using an external device. Specifically, the user operates the external device to transmit a command to read out the sampling frequency fs. When the interface circuit 70 receives the command, for example, the DSP 44 transmits the sampling frequency fs stored in the register 61 to the external device via the interface circuit 70. As a result, the user can read out the sampling frequency fs. When the sampling frequency fs is acquired, the user can use the acquired sampling frequency fs to calculate a transfer function at any filter coefficient using simulator software or the like. As a result, it becomes possible to accurately simulate the gain, phase change characteristics, and group phase change characteristics in the external device.

[0064] When the filter coefficients for providing the desired filter characteristics are obtained, the user transfers the filter coefficients to the physical quantity sensor 1 using an external device. That is, the user operates the external device to transmit information indicating the filter coefficients. The physical quantity sensor 1 acquires the filter coefficients via the interface circuit 70. The interface circuit 70 writes the acquired filter coefficients to the register 61. The second filter 44d acquires the filter coefficients by referring to the register 61, and sets the values ​​of each filter in the second filter 44d so as to operate with the acquired filter coefficients. As a result, the second filter 44d is able to execute second digital filtering processing that results in filter characteristics desired by the user.

[0065] The digital signal after the second digital filter process is performed by the second filter 44d is output from the DSP 44 as a digital signal Da' in which the digital signal (angular velocity data) indicating the detection result detected by the sensor element 2 is corrected. The output manner is not limited, and the DSP 44 may output the generated digital signal Da' to an external device using the interface circuit 70, or may store it in the storage unit 60. In this case, the digital signal Da' is output to the external device via the interface circuit 70 in response to a request from the external device at any timing.

[0066] 2. Other embodiments The above-described embodiment is an example for carrying out the present invention, and various other embodiments can be adopted. For example, the processing order of the DSP 44 is not limited to the processing order in the above-described embodiment, and may be the processing order of the notch filter 44b, the second filter 44d, the IIR filter 44c, etc., or the processing order may be changed arbitrarily. Furthermore, the notch filter 44b and the second filter 44d may be omitted as necessary. Of course, other digital filter processes may be added. Furthermore, the filter coefficient of the notch filter 44b may be selectable by the user. Furthermore, the filter coefficient of the notch filter 44b and the second filter 44d may be configured to change according to the sampling frequency fs.

[0067] The A / D conversion circuit only needs to be able to A / D convert the signal output from the sensor element. In other words, since an analog signal is output from the sensor element, the A / D conversion circuit only needs to be able to convert the detection value of the physical quantity indicated by the analog signal into a digital signal. The signal input to the A / D conversion circuit may be the signal itself output from the sensor element, or may be a signal that has been subjected to various processes on the signal output from the sensor element.

[0068] The signal processing circuit only needs to be able to perform digital filter processing on the digital signal output from the A / D conversion circuit. That is, the signal processing circuit performs various digital filter processing on the digital signal indicating the detection result of the sensor element. As a result, for example, a signal in an easy-to-handle state that is used outside the physical quantity sensor is obtained. The digital filter processing may be various types of processing and is not limited to the processing in the above-mentioned embodiment. For example, the above-mentioned notch filter, second digital filter, etc. may be omitted. In addition, other filters may be added. Furthermore, the order of the digital filter processing is not limited, and the digital filter processing may be performed in various orders.

[0069] The memory circuit only needs to be able to store individual data corresponding to the sampling frequency of the digital filter processing. That is, the memory circuit stores individual data that is at least one of the sampling frequency itself, which is a unique value reflecting the individual difference of the sensor element, and a value determined according to the sampling frequency. The latter value may be the sampling period, a value obtained by converting the sampling frequency, or a value for calculating the sampling frequency.

[0070] The characteristic determination unit may determine the characteristics of the digital filter processing based on the individual data. The characteristics of the digital filter processing are input / output characteristics of the digital filter processing, and may be changed by any method in the digital filter processing in which the input / output characteristics are variable. In the above example, the filter coefficient k is determined by a linear equation of the sampling frequency, and the filter characteristics are determined, but the present invention is not limited to such a configuration. For example, the filter coefficient may be determined based on an equation of second degree or higher.

[0071] In the above-described embodiment, the characteristic determination unit specifies the filter coefficient k that makes the IIR filter characteristics constant regardless of the sampling frequency, and in this case, the cutoff frequency fc is made the same to make the IIR filter characteristics constant. This configuration is an example, and the index indicating the filter characteristics is not limited to the cutoff frequency fc. For example, the filter coefficient k may be set to provide a constant attenuation amount at a specific frequency different from the cutoff frequency fc. In addition, the filter coefficient k may be set to provide a constant gain characteristic for various indexes, or the filter coefficient k may be set to provide a constant phase change characteristic and group phase change characteristic.

[0072] The interface circuit may be configured to be capable of reading out individual data, but may also be configured to be capable of reading out other data, or may be configured to be capable of writing other data. The data to be read out or written is stored in a memory circuit.

[0073] The above-described embodiments are merely examples, and the present invention is not limited to these. The present invention includes configurations that are substantially the same as those described in the embodiments (for example, configurations with the same functions, methods, and results, or configurations with the same purpose and effect). The present invention also includes configurations in which non-essential parts of the configurations described in the embodiments are replaced. The present invention also includes configurations that achieve the same effects as the configurations described in the embodiments, or configurations that can achieve the same purpose. The present invention also includes configurations in which publicly known technology is added to the configurations described in the embodiments. [Explanation of symbols]

[0074] 1...physical quantity sensor, 2...sensor element, 3...circuit device, 10...reference voltage circuit, 20...drive circuit, 30...detection circuit, 40...digital processing unit, 42...A / D conversion circuit, 44a...temperature compensation unit, 44b...notch filter, 44b1, 44b2, 44b3, 44b4, 44c1, 44c2, 44c3...addition unit, 44b5, 44b7, 44b8, 44b9, 44b10, 44b11, 44c5, 44c6...multiplication unit, 44b5, 44b6, 44c4...delay unit, 44c...IIR filter, 44d...second filter, 50...oscillating circuit, 60...storage unit, 61...register, 62...non-volatile memory, 70...interface circuit, 80...temperature sensor, 82...A / D conversion circuit, 84...temperature compensation value calculation unit, 90...characteristic determination unit

Claims

1. An A / D conversion circuit that performs A / D conversion on a signal output from the sensor element; a signal processing circuit that performs digital filtering on the digital signal output from the A / D conversion circuit; a memory circuit for storing individual data corresponding to a sampling frequency of the digital filter processing; a characteristic determining unit that determines a characteristic of the digital filter processing based on the individual data; A circuit device comprising:

2. the digital filtering process includes an IIR filter using a filter coefficient k; The characteristic determination unit determines the filter coefficient k by a linear expression of the sampling frequency. The circuit device according to claim 1 .

3. the storage circuit stores, for each setting of the IIR filter, a and b in a calculation formula k=a×(the sampling frequency)+b for calculating the filter coefficient k that keeps the characteristics of the IIR filter constant regardless of the sampling frequency; the characteristic determination unit acquires the a and the b corresponding to settings of the IIR filter and the sampling frequency as the individual data, and determines the filter coefficient k based on the acquired a, b, and the sampling frequency and the calculation formula. The circuit device according to claim 2 .

4. Further comprising an interface circuit configured to be able to read the individual data. The circuit device according to claim 1 .

5. The signal processing circuit performs a second digital filter process; an interface circuit configured to be able to write a filter coefficient of the second digital filter processing to the memory circuit; The circuit device according to claim 1 .

6. The second digital filtering process is performed by an IIR filter. The circuit arrangement according to claim 5 .

7. A sensor element; an A / D conversion circuit that performs A / D conversion on a signal output from the sensor element; a signal processing circuit that performs digital filtering on the digital signal output from the A / D conversion circuit; a memory circuit for storing individual data corresponding to a sampling frequency of the digital filter processing; a characteristic determining unit that determines a characteristic of the digital filter processing based on the individual data; A physical quantity sensor comprising:

8. Further comprising a drive circuit for driving the sensor element, The signal output from the sensor element corresponds to the angular velocity detected by the sensor element. The physical quantity sensor according to claim 7 .

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