Semiconductor device

Abstract

To provide a semiconductor device which can be easily reduced in size, and can suppress deterioration of a quality.SOLUTION: A semiconductor device comprises a print circuit board, including: first and second semiconductor chips 3a and 3b that are separately provided each other, and includes first main electrodes 32a and 32b on an upper surface side and second main electrodes 33a and 33b on a lower surface side; a first wiring layer 24c on the uppermost layer that is provided to a circumference of the first and second semiconductor chips 3a and 3b, and is electrically connected to the first main electrode 32a of the first semiconductor chip 3a via a connection member 72a; a plurality of wiring layers 21b, 22b, 23c, and 24c that is electrically connected to the first wiring layer 24c through vias 81b, 82e, 82f, 83e, and 83f, and contains a second wiring layer 21b on the lowest layer electrically connected to the second main electrode 33b of the second semiconductor chip 3b; and an insulation layer 20 that is provided between the plurality of wiring layers 21b, 22b, 23c, and 24c.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a semiconductor device (semiconductor module) incorporating a power semiconductor element. [Background technology]

[0002] Patent Document 1 discloses a composite ceramic multilayer substrate which includes a glass ceramic insulating layer including a wiring layer and a highly thermally conductive ceramic insulating layer made of a ceramic material having a higher thermal conductivity than the glass ceramic insulating layer, and in which the glass ceramic insulating layer is formed directly and / or via a wiring layer on one main surface or both main surfaces of the highly thermally conductive ceramic insulating layer, and which, when viewed from a direction perpendicular to the main surface of the composite ceramic multilayer substrate, has one or more heat generating element mounting portions which are surrounded by the glass ceramic insulating layer and in which wiring for mounting a heat generating element formed on the main surface of the highly thermally conductive ceramic insulating layer is exposed.

[0003] Patent Document 2 discloses a semiconductor module including power wiring provided with power elements, a glass ceramic multilayer substrate provided with a control element for controlling the power elements, and a highly thermally conductive ceramic substrate made of a ceramic material having a higher thermal conductivity than the glass ceramic contained in the glass ceramic multilayer substrate, in which the power wiring is provided on the highly thermally conductive ceramic substrate and the glass ceramic multilayer substrate is directly provided on the highly thermally conductive ceramic substrate.

[0004] Patent Document 3 discloses that a bonding layer is interposed between a low-temperature fired multilayer substrate and an aluminum nitride substrate, and that the two substrates are firmly bonded by the bonding layer, and that a glass paste is used as the bonding layer. Patent Document 4 discloses a ceramic circuit board in which a glass ceramic sheet is mounted on an aluminum nitride substrate and has a hole in the center for mounting a semiconductor chip. Patent Document 5 discloses that a control wiring board is disposed on a laminated substrate via a bonding material, and that the control wiring board is made into a multilayer substrate. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2018 / 181523 [Patent Document 2] International Publication No. 2018 / 179538 [Patent Document 3] Japanese Patent Application Publication No. 4-288854 [Patent Document 4] Japanese Patent Application Publication No. 2-238642 [Patent Document 5] Patent Publication No. 2021-141220 Summary of the Invention [Problem to be solved by the invention]

[0006] In conventional semiconductor modules, when a power semiconductor element mounted on an insulating circuit board is connected to a terminal case or an external connection terminal via a connecting member such as a bonding wire, a bonding area (connection region) must be provided on the insulating circuit board, making it difficult to miniaturize the semiconductor module. Also, when a printed circuit board is placed opposite to the upper side of a power semiconductor element mounted on an insulating circuit board and the power semiconductor element is connected to the printed circuit board via a pin terminal or the like, components such as the power semiconductor element are hidden by the printed circuit board, making it difficult to inspect alignment and joints during component mounting, which may result in a decrease in quality.

[0007] In view of the above problems, an object of the present invention is to provide a semiconductor device that can be easily miniaturized and that can suppress deterioration in quality. [Means for solving the problem]

[0008] One aspect of the present invention is a semiconductor device comprising: first and second semiconductor chips spaced apart from each other, each having a first main electrode on an upper surface side and a second main electrode on a lower surface side; a printed circuit board having multiple wiring layers including a first wiring layer on the periphery of the first and second semiconductor chips and electrically connected to the first main electrode of the first semiconductor chip through a connecting member, and a second wiring layer on the lowermost layer electrically connected to the first wiring layer through a via and electrically connected to the second main electrode of the second semiconductor chip; and an insulating layer provided between the multiple wiring layers. Effect of the Invention

[0009] According to the present invention, it is possible to provide a semiconductor device that can be easily miniaturized and in which deterioration in quality can be suppressed. [Brief description of the drawings]

[0010] [Figure 1] 1 is a top view of a semiconductor device according to a first embodiment. [Diagram 2] 2 is a vertical cross-sectional view taken along line AA' in FIG. 1. [Diagram 3] 1 is a horizontal cross-sectional view passing through the bottom wiring layer of a printed circuit board. [Figure 4] This is a horizontal cross-sectional view passing through the second wiring layer from the bottom of the printed circuit board. [Diagram 5] This is a horizontal cross-sectional view passing through the third wiring layer from the bottom of the printed circuit board. [Figure 6] 1 is a horizontal cross-sectional view passing through the top wiring layer of a printed circuit board. [Figure 7] 1 is an equivalent circuit diagram of a semiconductor device according to a first embodiment. [Figure 8] 1 is a vertical cross-sectional view of a semiconductor device according to a first comparative example. [Figure 9] FIG. 11 is a side view of a semiconductor device according to a second comparative example. [Figure 10] FIG. 11 is a top view of a semiconductor device according to a second embodiment. [Figure 11]11 is a vertical cross-sectional view taken along line AA' in FIG. 10. [Figure 12] FIG. 13 is a top view of a semiconductor device according to a third embodiment. [Figure 13] 13 is a vertical cross-sectional view taken along line AA' in FIG. 12. [Figure 14] FIG. 13 is a top view of a semiconductor device according to a fourth embodiment. [Figure 15] FIG. 13 is a vertical cross-sectional view of a semiconductor device according to a fifth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, the first to fifth embodiments will be described with reference to the drawings. In the description of the drawings, the same or similar parts are denoted by the same or similar reference numerals, and duplicated explanations will be omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of thickness of each layer, etc. may differ from the actual ones. Furthermore, the drawings may include parts with different dimensional relationships and ratios. Moreover, the first to fifth embodiments shown below are examples of devices and methods for embodying the technical idea of ​​the present invention, and the technical idea of ​​the present invention does not specify the materials, shapes, structures, arrangements, etc. of the components as described below.

[0012] In addition, the term "first main electrode" in this specification means either the emitter electrode or the collector electrode in the case of an insulated gate bipolar transistor (IGBT). In the case of a field effect transistor (FET) or a static induction transistor (SIT), it means either the source electrode or the drain electrode. In the case of a static induction thyristor (SI thyristor), a gate turn-off thyristor (GTO), or a diode, it means either the anode electrode or the cathode electrode. In addition, the term "second main electrode" means either the emitter electrode or the collector electrode that is not the first main electrode in the case of an IGBT. In the case of a FET or a SIT, it means either the source electrode or the drain electrode that is not the first main electrode. In the case of a SI thyristor, a GTO, or a diode, it means either the anode electrode or the cathode electrode that is not the first main electrode. That is, if the "first main electrode" is a source electrode, the "second main electrode" means a drain electrode. If the "first main electrode" is an emitter electrode, the "second main electrode" means a collector electrode. If the "first main electrode" is an anode electrode, the "second main electrode" means a cathode electrode.

[0013] In addition, the definitions of directions such as "up", "down", "up and down", "left", "right", "left and right" in this specification are merely for the convenience of explanation and do not limit the technical idea of ​​the present invention. For example, if an object is rotated 90 degrees and observed, "up and down" is converted and read as "left and right", and of course, if it is rotated 180 degrees and observed, "up and down" is read in the reversed state.

[0014] (First embodiment) As an example of the semiconductor device according to the first embodiment, a semiconductor module called "2-in-1" having the functions of two power semiconductor elements will be described.

[0015] Fig. 1 is a top view of the semiconductor device according to the first embodiment, and Fig. 2 is a vertical cross-sectional view taken along line AA' in Fig. 1. The semiconductor device according to the first embodiment, as shown in Figs. 1 and 2, includes an insulating circuit board 1, power semiconductor elements (semiconductor chips) 3a-3d provided on the upper surface of the insulating circuit board 1, and a printed circuit board (multilayer board) 2 provided on the upper surface of the insulating circuit board 1 so as to surround the side surfaces of the semiconductor chips 3a-3d.

[0016] As shown in FIG. 2, the insulating circuit board 1 includes an insulating substrate 11, conductive plates (circuit boards) 12a and 12b spaced apart from each other on the upper surface of the insulating substrate 11, and a conductive plate (heat sink) 13 on the lower surface of the insulating substrate 11. The insulating circuit board 1 may be, for example, a direct copper bonded (DCB) substrate or an active metal brazing (AMB) substrate. The insulating substrate 11 is made of a ceramic substrate made of, for example, aluminum oxide (Al2O3), aluminum nitride (AlN), silicon nitride (Si3N4), boron nitride (BN), or a resin insulating substrate made of a polymer material. The circuit boards 12a and 12b and the heat sink 13 have a substantially rectangular planar pattern. The circuit boards 12a and 12b and the heat sink 13 are made of a conductive material such as a conductor foil made of, for example, copper (Cu), aluminum (Al), or the like.

[0017] As shown in Fig. 2, the upper arm semiconductor chip 3a is bonded to the upper surface of the circuit board 12a via a bonding material 4c such as solder or sintered material, or by using a direct bonding technique. The lower arm semiconductor chip 3b is bonded to the upper surface of the circuit board 12b via a bonding material 4d such as solder or sintered material, or by using a direct bonding technique. The upper arm semiconductor chip 3c shown in Fig. 1 is bonded to the upper surface of the circuit board 12a via a bonding material such as solder or sintered material, or by using a direct bonding technique, similar to the semiconductor chip 3a. The lower arm semiconductor chip 3d is bonded to the upper surface of the circuit board 12b via a bonding material such as solder or sintered material, or by using a direct bonding technique, similar to the semiconductor chip 3b.

[0018] The semiconductor chips 3a to 3d may be made of, for example, silicon (Si), or may be made of wide band gap semiconductor materials such as silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), diamond (C), etc. The types of the semiconductor chips 3a to 3d vary depending on the application, and may be, for example, power semiconductor elements such as field effect transistors (FETs), insulated gate bipolar transistors (IGBTs), static induction (SI) thyristors, and gate turn-off (GTO) thyristors, and rectifier elements such as free wheel diodes (FWDs), etc. In the semiconductor device according to the first embodiment, the case where the semiconductor chips 3a to 3d are MOSFETs is illustrated.

[0019] 1 and 2, four semiconductor chips 3a to 3d are illustrated, but the number of semiconductor chips is not particularly limited and can be appropriately selected according to the rated current, etc. As shown in Fig. 1 and 2, the semiconductor chip 3a has a source electrode 32a which is a first main electrode (upper surface electrode) and a gate electrode 31a which is a control electrode on the upper surface side, and a drain electrode 33a which is a second main electrode (lower surface electrode) on the lower surface side. The semiconductor chip 3b has a source electrode 32b which is a first main electrode (upper surface electrode) and a gate electrode 31b which is a control electrode on the upper surface side, and a drain electrode 33b which is a second main electrode (lower surface electrode) on the lower surface side.

[0020] The semiconductor chip 3c shown in Fig. 1 has a source electrode 32c which is a first main electrode (upper surface electrode) and a gate electrode 31c which is a control electrode on the upper surface side, and a drain electrode (not shown) which is a second main electrode (lower surface electrode) on the lower surface side. The semiconductor chip 3d shown in Fig. 1 has a source electrode 32d which is a first main electrode (upper surface electrode) and a gate electrode 31d which is a control electrode on the upper surface side, and a drain electrode (not shown) which is a second main electrode (lower surface electrode) on the lower surface side.

[0021] 1 and 2, the printed circuit board 2 is provided so as to straddle the upper surface sides of the circuit plates 12a and 12b of the insulating circuit board 1. The printed circuit board 2 has a plurality of (multi-layer) wiring layers 21a, 21b, 22a, 22b, 22d, 22e, 23a, 23c, 23e, 23g, and 24a to 24o that are electrically connected to each other through vias (connecting members) such as filled vias and electrically connect the source electrodes 32a and 32c of the semiconductor chips 3a and 3c to the drain main electrodes 33d of the semiconductor chips 3b and 3d, and an insulating layer 20 provided between the plurality of wiring layers 21a, 21b, 22a, 22b, 22d, 22e, 23a, 23c, 23e, 23g, and 24a to 24o.

[0022] Of the multiple wiring layers 21a, 21b, 22a, 22b, 22d, 22e, 23a, 23c, 23e, 23g, and 24a to 24o, the first wiring layer from the bottom and the lowest wiring layer (first wiring layers 21a and 21b) are joined to the insulating circuit board 1.

[0023] Among the multiple wiring layers 21a, 21b, 22a, 22b, 22d, 22e, 23a, 23c, 23e, 23g, 24a to 24o, the second wiring layers (second wiring layers) 22a, 22b, 22d, and 22e from the bottom are provided on the upper surface side of the first wiring layers 21a and 21b via an insulating layer 20. The second wiring layers 22a, 22b, 22d, and 22e form a main circuit through which a main current flows, a control circuit for controlling the semiconductor chips 3a to 3d, and the like.

[0024] Among the multiple wiring layers 21a, 21b, 22a, 22b, 22d, 22e, 23a, 23c, 23e, 23g, 24a to 24o, the third wiring layer (third wiring layer) 23a, 23c, 23e, 23g from the bottom is provided on the upper surface side of the second wiring layers 22b, 22d, 22e via an insulating layer 20. The third wiring layers 23a, 23c, 23e, 23g form a main circuit through which a main current flows, a control circuit for controlling the semiconductor chips 3a to 3d, and the like.

[0025] Among the multiple wiring layers 21a, 21b, 22a, 22b, 22d, 22e, 23a, 23c, 23e, 23g, and 24a to 24o, the fourth wiring layer from the bottom and the uppermost wiring layer (fourth wiring layer) 24a to 24o is provided on the upper surface side of the third wiring layers 23a, 23c, and 23g via an insulating layer 20. The fourth wiring layers 24a to 24o are provided with connection regions (bonding areas) for connection members such as bonding wires connected to the semiconductor chips 3a to 3d, and are equipped with external connection terminals for connection to an external circuit, etc.

[0026] The insulating layer 20 is made of an insulating material such as a ceramic or a resin mainly composed of alumina (Al2O3), aluminum nitride (AlN), silicon nitride (Si3N4), etc. The insulating layer 20 may be made of an insulating material such as a polyimide resin or a combination of glass fiber and epoxy resin.

[0027] The first wiring layers 21a and 21b, the second wiring layers 22a, 22b, 22d, and 22e, the third wiring layers 23a, 23c, 23e, and 23g, and the fourth wiring layers 24a to 24o are made of, for example, copper. It is made of conductive materials such as (Cu), a Cu alloy whose main component is Cu, aluminum (Al), or an Al alloy whose main component is Al.

[0028] 2, the first-layer wiring layers 21a and 21b are joined to the circuit boards 12a and 12b of the insulating circuit board 1. The first-layer wiring layer 21a is joined to the circuit board 12a via a joining material 4a such as solder or a sintered material, or by using a direct joining technique. The first-layer wiring layer 21b is joined to the circuit board 12b via a joining material 4b such as solder or a sintered material, or by using a direct joining technique. The top surfaces of the first-layer wiring layers 21a and 21b are joined to the insulating layer 20.

[0029] As shown in FIG. 2, the second-layer wiring layers 22a, 22b, 22d, and 22e are embedded inside an insulating layer 20. The second-layer wiring layer 22a is provided above a position where it overlaps with the first-layer wiring layer 21a via an insulating layer 20. The second-layer wiring layer 22b is provided above a position where it overlaps with the first-layer wiring layer 21a and a part of the first-layer wiring layer 21b via an insulating layer 20. The second-layer wiring layer 22b is electrically connected to the first-layer wiring layer 21b via a via 81b that penetrates a through hole provided in the insulating layer 20. The second-layer wiring layer 22d is provided above a position where it overlaps with a part of the first-layer wiring layer 21b via an insulating layer 20. The second-layer wiring layer 22e is provided above a position where it overlaps with the first-layer wiring layer 21b via an insulating layer 20.

[0030] As shown in FIG. 2, the third-layer wiring layers 23a, 23c, 23e, and 23g are embedded inside the insulating layer 20. The third-layer wiring layer 23a is provided above a position where it overlaps with the second-layer wiring layer 22a via the insulating layer 20. The third-layer wiring layer 23a is provided with a through hole 231. The third-layer wiring layer 23c is provided above a position where it overlaps with the second-layer wiring layer 22b via the insulating layer 20. The third-layer wiring layer 23c is electrically connected to the second-layer wiring layer 22b via vias 82e and 82f that penetrate through the through holes provided in the insulating layer 20. The third-layer wiring layer 23e is provided above a position where it overlaps with the second-layer wiring layer 22d via the insulating layer 20. The third-layer wiring layer 23e is electrically connected to the second-layer wiring layer 22d via a via 82g that penetrates a through hole provided in the insulating layer 20. The third wiring layer 23g is provided above a position where it overlaps with the second wiring layer 22e, with an insulating layer 20 interposed therebetween. A through hole 235 is provided in the third wiring layer 23g.

[0031] As shown in FIG. 2, the fourth-layer wiring layers 24e, 24c, 24i, and 24m are bonded to the upper surface side of the insulating layer 20. The fourth-layer wiring layer 24e is provided above a position where it overlaps with the third-layer wiring layer 23a via the insulating layer 20. The fourth-layer wiring layer 24e is electrically connected to the second-layer wiring layer 22a via a via 82b that penetrates a through hole provided in the insulating layer 20 and a through hole 231 provided in the third-layer wiring layer 23a. The fourth-layer wiring layer 24c is provided above a position where it overlaps with the third-layer wiring layer 23c via the insulating layer 20. The fourth-layer wiring layer 24c is electrically connected to the third-layer wiring layer 23c via vias 83e and 83f that penetrate through holes provided in the insulating layer 20.

[0032] The fourth-layer wiring layer 24i is provided above a position where it overlaps with the third-layer wiring layer 23e via an insulating layer 20. The fourth-layer wiring layer 24i is electrically connected to the third-layer wiring layer 23e via a via 83g that penetrates a through hole provided in the insulating layer 20. The fourth-layer wiring layer 24m is provided above a position where it overlaps with the third-layer wiring layer 23g via an insulating layer 20. The fourth-layer wiring layer 24m is electrically connected to the second-layer wiring layer 22e via a via 82i that penetrates a through hole provided in the insulating layer 20 and a through hole 235 provided in the third-layer wiring layer 23g.

[0033] 1, openings 2a-2d are provided in the insulating layer 20 so as to surround the outer periphery (side surface) of the semiconductor chips 3a-3d. The openings 2a-2d penetrate the insulating layer 20 from the upper surface to the lower surface. The upper surfaces of the semiconductor chips 3a-3d are exposed through the openings 2a-2d. Fourth-layer wiring layers 24a-24o are provided around the mounting positions of the semiconductor chips 3a-3d and the openings 2a-2d of the insulating layer 20.

[0034] The lower end of a control terminal (gate control terminal) 6a, which is an external connection terminal, is bonded onto the fourth wiring layer 24a via a bonding material such as solder or a sintered material, or by using a direct bonding technique. The gate control terminal 6a extends upward from the fourth wiring layer 24a. The upper end of the gate control terminal 6a is connected to an external circuit (not shown). The gate control terminal 6a is electrically connected to the gate electrodes 31a and 31c of the semiconductor chips 3a and 3c. The gate control terminal 6a applies a control signal to the gate electrodes 31a and 31c of the semiconductor chips 3a and 3c to control the on / off of the semiconductor chips 3a and 3c.

[0035] The lower end of a control terminal (auxiliary source terminal) 6b, which is an external connection terminal, is bonded onto the fourth wiring layer 24b via a bonding material such as solder or a sintered material, or by using a direct bonding technique. The auxiliary source terminal 6b extends upward from the fourth wiring layer 24b. The upper end of the auxiliary source terminal 6b is connected to an external circuit (not shown). The auxiliary source terminal 6b is electrically connected to the source electrodes 32a and 32c of the semiconductor chips 3a and 3c. The auxiliary source terminal 6b detects the current flowing through the semiconductor chips 3a and 3c.

[0036] The source electrode 32a of the semiconductor chip 3a is connected to the fourth wiring layer 24c via a bonding wire 72a, which is a connecting member. Furthermore, the source electrode 32c of the semiconductor chip 3c is connected to the fourth wiring layer 24c via a bonding wire 72b, which is a connecting member.

[0037] As shown in FIG. 1 and FIG. 2, the lower end of the output terminal 5c, which is an external connection terminal on the output side, is bonded onto the fourth wiring layer 24c via a bonding material 4e such as solder or sintered material, or by using a direct bonding technique. The output terminal 5c extends toward the upper side of the insulating circuit board 1. The upper end of the output terminal 5c is connected to an external circuit (not shown). The output terminal 5c is electrically connected to the source electrodes 32a and 32c of the semiconductor chips 3a and 3c and the drain electrodes 33b of the semiconductor chips 3b and 3d. When the semiconductor chips 3a and 3c are in the ON state, the output terminal 5c passes a current from the source electrodes 32a and 32c of the semiconductor chips 3a and 3c to the external circuit. When the semiconductor chips 3b and 3d are in the ON state, the output terminal 5c supplies a current from the external circuit to the drain electrodes 33b of the semiconductor chips 3b and 3d.

[0038] 1, the gate electrode 31a of the semiconductor chip 3a is connected to the fourth-layer wiring layer 24d via a bonding wire 71a which is a connecting member. The source electrode 32a of the semiconductor chip 3a is connected to the fourth-layer wiring layer 24e via a bonding wire 73a which is a connecting member. The gate electrode 31c of the semiconductor chip 3c is connected to the fourth-layer wiring layer 24f via a bonding wire 71c which is a connecting member. The source electrode 32c of the semiconductor chip 3c is connected to the fourth-layer wiring layer 24g via a bonding wire 73c which is a connecting member.

[0039] The lower end of a positive terminal (P terminal) 5a, which is a high-potential external connection terminal, is bonded onto the fourth wiring layer 24h via a bonding material such as solder or a sintered material, or by using a direct bonding technique. The P terminal 5a extends upward from the fourth wiring layer 24h. The upper end of the P terminal 5a is connected to an external circuit (not shown). The P terminal 5a is electrically connected to the drain electrodes 33a of the semiconductor chips 3a and 3c. The P terminal 5a supplies a current to the drain electrodes 33a of the semiconductor chips 3a and 3c via the external circuit.

[0040] A source electrode 32b of the semiconductor chip 3b is connected to the fourth wiring layer 24i via a bonding wire 72b, which is a connecting member. Furthermore, a source electrode 32d of the semiconductor chip 3d is connected to the fourth wiring layer 24i via a bonding wire 72d, which is a connecting member.

[0041] The lower end of a negative terminal (N terminal) 5b, which is an external connection terminal on the low potential side, is bonded onto the fourth wiring layer 24i via a bonding material such as solder or a sintered material, or by using a direct bonding technique. The N terminal 5b extends upward from the fourth wiring layer 24i. The upper end of the N terminal 5b is connected to an external circuit (not shown). The N terminal 5b is electrically connected to the source electrodes 32b and 32d of the semiconductor chips 3b and 3d. The N terminal 5b passes a current from the source electrodes 32b and 32d of the semiconductor chips 3b and 3d to the external circuit.

[0042] The lower end of a control terminal (auxiliary source terminal) 6c, which is an external connection terminal, is bonded onto the fourth wiring layer 24j via a bonding material such as solder or a sintered material, or by using a direct bonding technique. The auxiliary source terminal 6c extends upward from the fourth wiring layer 24j. The upper end of the auxiliary source terminal 6c is connected to an external circuit (not shown). The auxiliary source terminal 6c is electrically connected to the source electrodes 32b and 32d of the semiconductor chips 3b and 3d. The auxiliary source terminal 6c detects the current flowing through the semiconductor chips 3b and 3d.

[0043] The lower end of a control terminal (gate control terminal) 6d, which is an external connection terminal, is bonded onto the fourth wiring layer 24k via a bonding material such as solder or a sintered material, or by using a direct bonding technique. The gate control terminal 6d extends upward from the fourth wiring layer 24k. The upper end of the gate control terminal 6d is connected to an external circuit (not shown). The gate control terminal 6d is electrically connected to the gate electrodes 31b and 31d of the semiconductor chips 3b and 3d. The gate control terminal 6d applies a control signal to the gate electrodes 31b and 31d of the semiconductor chips 3b and 3d to control the on / off of the semiconductor chips 3b and 3d.

[0044] The gate electrode 31b of the semiconductor chip 3b is connected to the fourth-layer wiring layer 24l via a bonding wire 71b which is a connecting member. The source electrode 32b of the semiconductor chip 3b is connected to the fourth-layer wiring layer 24m via a bonding wire 73b which is a connecting member. The gate electrode 31d of the semiconductor chip 3d is connected to the fourth-layer wiring layer 24n via a bonding wire 71d which is a connecting member. The source electrode 32d of the semiconductor chip 3d is connected to the fourth-layer wiring layer 24o via a bonding wire 73d which is a connecting member.

[0045] 1 and 2, the bonding wires 71a to 71d, 72a to 72d, and 73a to 73d, which are connecting members, are made of a conductive material such as aluminum (Al). The thickness and number of the bonding wires 71a to 71d, 72a to 72d, and 73a to 73d are not particularly limited and can be adjusted as appropriate.

[0046] 1 and 2 are made of conductive materials such as metals, such as copper (Cu), a Cu alloy mainly made of Cu, aluminum (Al), or an Al alloy mainly made of Al, etc. The gate control terminals 6a, 6d, the auxiliary source terminals 6b, 6c, the P terminal 5a, the N terminal 5b, and the output terminal 5c may be made of the same material or different materials.

[0047] 1 and 2, the gate control terminals 6a, 6d, the auxiliary source terminals 6b, 6c, the P terminal 5a, the N terminal 5b, and the output terminal 5c are illustrated as being cylindrical or rod-shaped, but the shapes of the gate control terminals 6a, 6d, the auxiliary source terminals 6b, 6c, the P terminal 5a, the N terminal 5b, and the output terminal 5c are not particularly limited and may be polygonal prism-shaped or flat plate-shaped, for example. The thickness of the gate control terminals 6a, 6d and the auxiliary source terminals 6b, 6c may be thinner than the thickness of the P terminal 5a, the N terminal 5b, and the output terminal 5c.

[0048] Fig. 3 is a horizontal cross-sectional view passing through the first wiring layers 21a, 21b of the printed circuit board 2. In Fig. 3, the insulating layer 20 on the upper surface side of the first wiring layers 21a, 21b and the vias 81a, 81b joined to the upper surface side of the first wiring layers 21a, 21b are shown by dashed lines. As shown in Fig. 3, the first wiring layers 21a, 21b are provided spaced apart from each other.

[0049] The first wiring layer 21a has a planar pattern with a rectangular outline. The first wiring layer 21a is provided with an opening 21x that collectively surrounds the openings 2a and 2c of the insulating layer 20. A via 81a is joined to the upper surface side of the first wiring layer 21a. The number and joining positions of the vias 81a are not particularly limited.

[0050] The first wiring layer 21b has a planar pattern with a rectangular outline. The first wiring layer 21b is provided with an opening 21y that collectively surrounds the openings 2b and 2d of the insulating layer 20. Vias 81b are joined to the upper surface side of the first wiring layer 21b. The number and joining positions of the vias 81b are not particularly limited.

[0051] Fig. 4 is a horizontal cross-sectional view passing through the second wiring layers 22a-22e of the printed circuit board 2. In Fig. 4, vias 82a-82j joined to the upper surface sides of the second wiring layers 22a-22e are typically shown by dashed lines. As shown in Fig. 4, the second wiring layers 22a-22e are spaced apart from one another via an insulating layer 20.

[0052] The second wiring layer 22a has an L-shaped planar pattern. The second wiring layer 22a is provided above a position where it overlaps with a part of the first wiring layer 21a shown in FIG. 3, with an insulating layer 20 interposed therebetween. Vias 82a to 82c are joined to the upper surface side of the second wiring layer 22a. The number and joining positions of the vias 82a to 82c are not particularly limited. Note that one via 82b is shown in FIG. 4, but three vias 82a are shown in FIG. 2.

[0053] The second wiring layer 22b has an L-shaped planar pattern. The second wiring layer 22b is provided above a position where it overlaps with a part of the first wiring layers 21a and 21b shown in FIG. 3, via an insulating layer 20, so as to straddle the first wiring layers 21a and 21b. The via 81b shown in FIG. 3 is joined to the lower surface side of the second wiring layer 22b. The second wiring layer 22b and the first wiring layer 21b are electrically connected by the via 81b. The vias 82e and 82f are joined to the upper surface side of the second wiring layer 22b. The number and joining positions of the vias 82e and 82f are not particularly limited. Although one via 82e and one via 82f are shown in FIG. 4, three vias 82e and three vias 82f are shown in FIG. 2.

[0054] The second-layer wiring layer 22c has a rectangular planar pattern. The second-layer wiring layer 22c is provided above a position where it overlaps with a part of the first-layer wiring layer 21a shown in FIG. 3, with the insulating layer 20 interposed therebetween. The via 81a shown in FIG. 3 is joined to the lower surface side of the second-layer wiring layer 22c. The second-layer wiring layer 22c and the first-layer wiring layer 21a are electrically connected by the via 81a. A via 82d is joined onto the second-layer wiring layer 22c. The number and joining position of the via 82d are not particularly limited. Although one via 82d is shown in FIG. 4, three vias 82d are shown in FIG. 2.

[0055] The second wiring layer 22d has a U-shaped planar pattern. The second wiring layer 22d is provided above a position where it overlaps with a part of the first wiring layer 21b shown in Fig. 3, with an insulating layer 20 interposed therebetween. Vias 82g are joined onto the second wiring layer 22d. The number and joining positions of the vias 82g are not particularly limited.

[0056] The second wiring layer 22e has an L-shaped planar pattern. The second wiring layer 22e is provided above a position where it overlaps with a part of the first wiring layer 21b shown in FIG. 3, with an insulating layer 20 interposed therebetween. Vias 82h-82j are joined onto the second wiring layer 22d. The number and joining positions of the vias 82h-82j are not particularly limited. Although one via 82i is shown in FIG. 4, three vias 82i are shown in FIG. 2.

[0057] Fig. 5 is a horizontal cross-sectional view passing through the third wiring layers 23a-22e of the printed circuit board 2. In Fig. 5, vias 83a-83j joined to the upper surface sides of the third wiring layers 23a-22e are typically shown by dashed lines. As shown in Fig. 5, the third wiring layers 23a-22e are provided spaced apart from one another with an insulating layer 20 interposed therebetween.

[0058] The third wiring layer 23a has a rectangular planar pattern. The third wiring layer 23a is provided above a position overlapping a part of the second wiring layer 22a shown in FIG. 4, with an insulating layer 20 interposed therebetween. The third wiring layer 23a is provided with through holes 231 and 232 through which the vias 82b and 82c penetrate. The vias 83a to 83c are joined to the upper surface side of the third wiring layer 23a. The number and joining positions of the vias 83a to 83c are not particularly limited.

[0059] The third wiring layer 23b has a rectangular planar pattern. The third wiring layer 23b is provided above a position where it overlaps with a part of the second wiring layer 22a shown in Fig. 4, with an insulating layer 20 interposed therebetween. The third wiring layer 23b is provided with a through hole 233 through which the via 82a penetrates.

[0060] The third-layer wiring layer 23c has an L-shaped planar pattern. The third-layer wiring layer 23c is provided above the position where it overlaps with the second-layer wiring layer 22b shown in FIG. 4, with the insulating layer 20 interposed therebetween. The vias 82e and 82f shown in FIG. 4 are joined to the lower surface side of the third-layer wiring layer 23c. The third-layer wiring layer 23c and the second-layer wiring layer 22b are electrically connected by the vias 82e and 82f. The vias 83e and 83f are joined to the upper surface side of the third-layer wiring layer 23c. The number and joining positions of the vias 83e and 83f are not particularly limited. Although one via 83e and one via 83f are shown in FIG. 4, three vias 83e and three vias 83f are shown in FIG. 2.

[0061] The third-layer wiring layer 23d has a rectangular planar pattern. The third-layer wiring layer 23d is provided above a position where it overlaps with the second-layer wiring layer 22c shown in FIG. 4, with the insulating layer 20 interposed therebetween. The via 82d shown in FIG. 4 is joined to the lower surface side of the third-layer wiring layer 23d. The third-layer wiring layer 23d and the second-layer wiring layer 22c are electrically connected by the via 82d. The via 83d is joined to the upper surface side of the third-layer wiring layer 23d. The number and joining position of the via 83d are not particularly limited.

[0062] The third-layer wiring layer 23e has a U-shaped planar pattern. The third-layer wiring layer 23e is provided above a position where it overlaps with the second-layer wiring layer 22d shown in FIG. 4, with the insulating layer 20 interposed therebetween. The via 82g shown in FIG. 4 is joined to the lower surface side of the third-layer wiring layer 23e. The third-layer wiring layer 23e and the second-layer wiring layer 22d are electrically connected by the via 82g. The via 83g is joined to the upper surface side of the third-layer wiring layer 23e. The number and joining position of the via 83g are not particularly limited. Note that one via 83g is shown in FIG. 4, but three vias 83g are shown in FIG. 2.

[0063] The third wiring layer 23f has a rectangular planar pattern. The third wiring layer 23f is provided above a position where it overlaps with a part of the second wiring layer 22e shown in Fig. 4, with an insulating layer 20 interposed therebetween. The third wiring layer 23f is provided with a through hole 234 through which the via 82h penetrates.

[0064] The third-layer wiring layer 23g has a rectangular planar pattern. The third-layer wiring layer 23g is provided above a position overlapping a part of the second-layer wiring layer 22e shown in FIG. 4, with an insulating layer 20 interposed therebetween. The third-layer wiring layer 23g is provided with through holes 235 and 236 through which the vias 82i and 82j penetrate. The vias 83h to 83j are joined to the upper surface side of the third-layer wiring layer 23g. The number and joining positions of the vias 83h to 83j are not particularly limited.

[0065] Fig. 6 is a horizontal cross-sectional view passing through the fourth wiring layers 24a-24o of the printed circuit board 2. In Fig. 6, the insulating layer 20 on the lower surface side of the fourth wiring layers 24a-24o is shown by a dashed line. As shown in Fig. 6, the fourth wiring layers 24a-24o are provided spaced apart from each other.

[0066] The fourth wiring layer 24a has a rectangular planar pattern. The fourth wiring layer 24a is provided above a position where it overlaps with a part of the third wiring layer 23a shown in Fig. 5, with the insulating layer 20 interposed therebetween. The via 83a shown in Fig. 5 is joined to the lower surface side of the fourth wiring layer 24a. The fourth wiring layer 24a and the third wiring layer 23a are electrically connected by the via 83a.

[0067] The fourth wiring layer 24b has a rectangular planar pattern. The fourth wiring layer 24b is provided above a position where it overlaps with the third wiring layer 23b shown in Fig. 5, with the insulating layer 20 interposed therebetween. The via 82a shown in Fig. 5 is joined to the lower surface side of the fourth wiring layer 24b. The via 82a electrically connects the fourth wiring layer 24b and the second wiring layer 22a.

[0068] The fourth-layer wiring layer 24c has an L-shaped planar pattern. The fourth-layer wiring layer 24c is provided above a position where it overlaps with the third-layer wiring layer 23c shown in Fig. 5, with an insulating layer 20 interposed therebetween. The vias 83e and 83f shown in Fig. 5 are joined to the lower surface side of the fourth-layer wiring layer 24c. The vias 83e and 83f electrically connect the fourth-layer wiring layer 24c and the third-layer wiring layer 23c.

[0069] The fourth-layer wiring layer 24d has a rectangular planar pattern. The fourth-layer wiring layer 24d is provided above a position where it overlaps with a part of the third-layer wiring layer 23a shown in Fig. 5, with the insulating layer 20 interposed therebetween. The via 83b shown in Fig. 5 is joined to the lower surface side of the fourth-layer wiring layer 24d. The fourth-layer wiring layer 24d and the third-layer wiring layer 23a are electrically connected by the via 83b.

[0070] The fourth-layer wiring layer 24e has a rectangular planar pattern. The fourth-layer wiring layer 24e is provided above a position where it overlaps with a part of the third-layer wiring layer 23a shown in Fig. 5, with the insulating layer 20 interposed therebetween. The via 82b shown in Fig. 5 is joined to the lower surface side of the fourth-layer wiring layer 24e. The via 82b electrically connects the fourth-layer wiring layer 24e and the second-layer wiring layer 22a.

[0071] The fourth-layer wiring layer 24f has a rectangular planar pattern. The fourth-layer wiring layer 24f is provided above a position where it overlaps with a part of the third-layer wiring layer 23a shown in Fig. 5, with the insulating layer 20 interposed therebetween. The via 83c shown in Fig. 5 is joined to the lower surface side of the fourth-layer wiring layer 24f. The fourth-layer wiring layer 24f and the third-layer wiring layer 23a are electrically connected by the via 83c.

[0072] The fourth-layer wiring layer 24g has a rectangular planar pattern. The fourth-layer wiring layer 24g is provided above a position where it overlaps with a part of the third-layer wiring layer 23a shown in Fig. 5, with the insulating layer 20 interposed therebetween. The via 82c shown in Fig. 5 is joined to the lower surface side of the fourth-layer wiring layer 24g. The fourth-layer wiring layer 24g and the second-layer wiring layer 22a are electrically connected by the via 82c.

[0073] The fourth wiring layer 24h has a rectangular planar pattern. The fourth wiring layer 24h is provided above a position where it overlaps with the third wiring layer 23d shown in Fig. 5, with the insulating layer 20 interposed therebetween. The via 83d shown in Fig. 5 is joined to the lower surface side of the fourth wiring layer 24h. The fourth wiring layer 24h and the third wiring layer 23d are electrically connected by the via 83d.

[0074] The fourth-layer wiring layer 24i has a U-shaped planar pattern. The fourth-layer wiring layer 24i is provided above a position where it overlaps with the third-layer wiring layer 23e shown in Fig. 5, with an insulating layer 20 interposed therebetween. The via 83g shown in Fig. 5 is joined to the lower surface side of the fourth-layer wiring layer 24i. The via 83g electrically connects the fourth-layer wiring layer 24i and the third-layer wiring layer 23e.

[0075] The fourth-layer wiring layer 24j has a rectangular planar pattern. The fourth-layer wiring layer 24j is provided above a position where it overlaps with the third-layer wiring layer 23f shown in Fig. 5, with the insulating layer 20 interposed therebetween. The via 82h shown in Fig. 5 is joined to the lower surface side of the fourth-layer wiring layer 24j. The via 82h electrically connects the fourth-layer wiring layer 24j and the second-layer wiring layer 22e.

[0076] The fourth-layer wiring layer 24k has a rectangular planar pattern. The fourth-layer wiring layer 24k is provided above a position where it overlaps with a part of the third-layer wiring layer 23g shown in Fig. 5, with an insulating layer 20 interposed therebetween. The via 83h shown in Fig. 5 is joined to the lower surface side of the fourth-layer wiring layer 24k. The fourth-layer wiring layer 24k and the third-layer wiring layer 23g are electrically connected by the via 83h.

[0077] The fourth-layer wiring layer 24l has a rectangular planar pattern. The fourth-layer wiring layer 24l is provided above a position where it overlaps with a part of the third-layer wiring layer 23g shown in Fig. 5, with an insulating layer 20 interposed therebetween. The via 83i shown in Fig. 5 is joined to the lower surface side of the fourth-layer wiring layer 24l. The fourth-layer wiring layer 24l and the third-layer wiring layer 23g are electrically connected by the via 83i.

[0078] The fourth-layer wiring layer 24m has a rectangular planar pattern. The fourth-layer wiring layer 24m is provided above a position where it overlaps with a part of the third-layer wiring layer 23g shown in Fig. 5, with an insulating layer 20 interposed therebetween. The via 82i shown in Fig. 5 is joined to the lower surface side of the fourth-layer wiring layer 24m. The via 82i electrically connects the fourth-layer wiring layer 24m and the second-layer wiring layer 22e.

[0079] The fourth-layer wiring layer 24n has a rectangular planar pattern. The fourth-layer wiring layer 24n is provided above a position where it overlaps with a part of the third-layer wiring layer 23g shown in Fig. 5, with the insulating layer 20 interposed therebetween. The via 83j shown in Fig. 5 is joined to the lower surface side of the fourth-layer wiring layer 24n. The fourth-layer wiring layer 24n and the third-layer wiring layer 23g are electrically connected by the via 83j.

[0080] The fourth-layer wiring layer 24o has a rectangular planar pattern. The fourth-layer wiring layer 24o is provided above a position where it overlaps with a part of the third-layer wiring layer 23g shown in Fig. 5, with the insulating layer 20 interposed therebetween. The via 82j shown in Fig. 5 is joined to the lower surface side of the fourth-layer wiring layer 24o. The via 82j electrically connects the fourth-layer wiring layer 24o and the second-layer wiring layer 22e.

[0081] Fig. 7 shows an example of an equivalent circuit of the semiconductor device according to the first embodiment. As shown in Fig. 7, the semiconductor device according to the first embodiment configures a part of a three-phase bridge circuit.

[0082] A second main electrode (drain electrode) of the transistor T1 on the upper arm side is connected to the drain side terminal P, and a first main electrode (source electrode) of the transistor T2 on the lower arm side is connected to the source side terminal N. The source electrode of the transistor T1 and the drain electrode of the transistor T2 are connected to the output terminal U and the auxiliary source terminal S1. The source electrode of the transistor T2 is connected to the auxiliary source terminal S2.

[0083] A gate control terminal G1 is connected to the gate electrode of transistor T1. A gate control terminal G2 is connected to the gate electrode of transistor T2. A body diode D1 that functions as a free wheel diode (FWD) is built in and connected in anti-parallel to transistor T1. A body diode D2 that functions as a free wheel diode (FWD) is built in and connected in anti-parallel to transistor T2.

[0084] The drain side terminal P, the source side terminal N, and the output terminal U shown in Fig. 7 correspond to the P terminal 5a, the N terminal 5b, and the output terminal 5c shown in Fig. 1. The transistor T1 shown in Fig. 7 corresponds to the semiconductor chips 3a and 3c shown in Fig. 1. The transistor T2 shown in Fig. 7 corresponds to the semiconductor chips 3b and 3d shown in Fig. 1. The gate control terminals G1 and G2 shown in Fig. 7 correspond to the gate control terminals 6a and 6d shown in Fig. 1. The auxiliary source terminals S1 and S2 shown in Fig. 7 correspond to the auxiliary source terminals 6b and 6c shown in Fig. 1.

[0085] 1 and 2, a control signal for controlling the on / off of the semiconductor chips 3a and 3c is applied to the gate electrodes 31a and 31c of the semiconductor chips 3a and 3c via the gate control terminal 6a, and a control signal for controlling the on / off of the semiconductor chips 3b and 3d is applied to the gate electrodes 31b and 31d of the semiconductor chips 3b and 3d via the gate control terminal 6d. As a result, the semiconductor chips 3a and 3c and the semiconductor chips 3b and 3d are alternately turned on and off repeatedly.

[0086] When the semiconductor chips 3a and 3c on the upper arm side are in the ON state, the current that has entered from the P terminal 5a passes through the fourth wiring layer 24h, the via 83d, the third wiring layer 23d, the via 82d, the second wiring layer 22c, the via 81a, the first wiring layer 21a, and the circuit board 12a of the printed circuit board 2 to the drain electrode 33a of the semiconductor chips 3a and 3c. Then, the current from the source electrodes 32a and 32c of the semiconductor chips 3a and 3c passes through the bonding wires 72a and 72c and the fourth wiring layer 24c of the printed circuit board 2 to flow from the output terminal 5c to the external circuit.

[0087] When the semiconductor chips 3b and 3d on the lower arm side are in the ON state, the current that has entered the output terminal 5c from the external circuit passes through the fourth wiring layer 24i, via 83g, the third wiring layer 23e, via 82g, the second wiring layer 22d, via 81b, the first wiring layer 21b, and the circuit board 12b of the printed circuit board 2 to the drain electrode 33b of the semiconductor chips 3b and 3d on the lower arm side. Then, the current from the source electrodes 32b and 32d of the semiconductor chips 3b and 3d passes through the bonding wires 72b and 72d and the fourth wiring layer 24i of the printed circuit board 2 to flow from the N terminal 5b to the external circuit.

[0088] <Method of Manufacturing Semiconductor Device> Next, an example of a manufacturing method (assembly method) of the semiconductor device according to the first embodiment will be described. First, the insulating circuit board 1 and the printed circuit board 2 shown in Figs. 1 and 2 are prepared. Then, the first wiring layers 21a and 21b of the printed circuit board 2, which are the bottom layer, are bonded to the upper surface side of the circuit boards 12a and 12b of the insulating circuit board 1. Next, the printed circuit board 2 is used as an alignment jig to align the semiconductor chips 3a and 3c through the openings 2a and 2c of the printed circuit board 2, and the semiconductor chips 3a and 3c are bonded to the upper surface side of the circuit board 12a of the insulating circuit board 1. Also, the semiconductor chips 3b and 3d are aligned through the openings 2b and 2d of the printed circuit board 2, and the semiconductor chips 3b and 3d are bonded to the upper surface side of the circuit board 12b of the insulating circuit board 1.

[0089] Next, as shown in FIG. 1, a gate control terminal 6a is bonded to the fourth wiring layer 24a, which is the uppermost layer of the printed circuit board 2, an auxiliary source terminal 6b is bonded to the fourth wiring layer 24b, an output terminal 5c is bonded to the fourth wiring layer 24c, a P terminal 5a is bonded to the fourth wiring layer 24h, an N terminal 5b is bonded to the fourth wiring layer 24i, an auxiliary source terminal 6c is bonded to the fourth wiring layer 24j, and a gate control terminal 6a is bonded to the fourth wiring layer 24k.

[0090] Next, the fourth wiring layers 24d, 24l, 24f, and 24n, which are the uppermost layers of the printed circuit board 2, are connected to the gate electrodes 31a to 31d of the semiconductor chips 3a to 3d, respectively, using the bonding wires 71a to 71d. The fourth wiring layer 24c, which is the uppermost layer of the printed circuit board 2, is connected to the source electrodes 32a and 32c of the semiconductor chips 3a and 3c, respectively, using the bonding wires 72a and 72c. The fourth wiring layer 24i, which is the uppermost layer of the printed circuit board 2, is connected to the source electrodes 32b and 32d of the semiconductor chips 3b and 3d, respectively, using the bonding wires 72b and 72d. The fourth wiring layer 24e, 24g, 24m, and 24o, which are the uppermost layers of the printed circuit board 2, are connected to the source electrodes 32a to 32d of the semiconductor chips 3a to 3d, respectively, using the bonding wires 73a to 73d.

[0091] Next, if necessary, the semiconductor chips 3a to 3d and the printed circuit board 2 are sealed with a sealing member, thereby completing the semiconductor device according to the first embodiment shown in FIGS.

[0092] <First Comparative Example> Next, a semiconductor device according to a first comparative example will be described. In the semiconductor device according to the first comparative example, as shown in Fig. 8, a semiconductor chip 103 is bonded to the upper surface side of an insulating circuit board 102 by solder 109. A terminal case 104 and external connection terminals 105, 106 are connected to the upper surfaces of the insulating circuit board 102 and the semiconductor chip 103 via bonding wires (aluminum wires) 110, 111. A copper base 101 is bonded to the lower surface side of the insulating circuit board 102 by solder 108. The periphery of the semiconductor chip 103 is coated with a gel sealant 107.

[0093] In the semiconductor device according to the first comparative example, a bonding area must be provided on the upper surface of the insulating circuit board 102 in order to form a circuit, making it difficult to miniaturize the module, etc. In contrast, in the semiconductor device according to the first embodiment, as shown in Figures 1 and 2, a multi-layered printed circuit board 2 is provided around the semiconductor chips 3a to 3d, so that a connection area such as a bonding area is provided on the top layer of the printed circuit board 2, and a main circuit, control circuit, etc. can be formed on a layer different from the connection area inside the printed circuit board 2, making it possible to miniaturize the semiconductor module (high-density mounting).

[0094] <Second Comparative Example> Next, a semiconductor device according to a second comparative example will be described. As shown in Fig. 9, the semiconductor device according to the second comparative example includes an insulating circuit board 201 having an insulating substrate 211, circuit boards 212a and 212b provided on the upper surface side of the insulating substrate 211, and a heat sink 213 provided on the lower surface side of the insulating substrate 211. Semiconductor chips 202a and 202b are bonded to the upper surface sides of the circuit boards 212a and 212b.

[0095] A printed circuit board 204 is provided above the semiconductor chips 202a and 202b. The semiconductor chips 202a and 202b are connected to the printed circuit board 204 via post electrodes (pin terminals) 203a and 203b. The printed circuit board 204 includes an insulating layer 241, a wiring layer 242 on the upper surface side of the insulating layer 241, and a wiring layer 243 on the lower surface side of the insulating layer 241. An external connection terminal 206a is bonded to the upper surface side of the circuit board 212a. An external connection terminal 206b is bonded to the upper surface side of the wiring layer 242. An external connection terminal 206c is bonded to the upper surface side of the circuit board 212b.

[0096] In the semiconductor device according to the second comparative example, the printed circuit board 204 is arranged above the semiconductor chips 202a and 202b, and the semiconductor chips 202a and 202b are connected to the printed circuit board 204 by the post electrodes 203a and 203b. Since there is no need to provide a bonding area as in the semiconductor device according to the first comparative example, the size can be easily reduced. However, the printed circuit board 204 above the semiconductor chips 202a and 202b hides the components such as the semiconductor chips 202a and 202b, which makes it difficult to inspect the alignment and joints when mounting the components, and there is a possibility that the quality may be reduced. In contrast, according to the semiconductor device according to the first embodiment, as shown in FIGS. 1 and 2, the upper surfaces of the semiconductor chips 3a to 3d are exposed through the openings 2a to 2d of the printed circuit board 2 in the top view of the semiconductor device according to the first embodiment. This allows the arrangement of the components such as the semiconductor chips 3a to 3d to be confirmed, which makes it easier to inspect the alignment and joints when mounting the components, thereby suppressing the deterioration of quality and improving reliability.

[0097] Furthermore, according to the semiconductor device of the first embodiment, in mounting chips, a jig such as carbon is conventionally used to align the semiconductor chips, but the printed circuit board 2 itself serves as the jig, and the semiconductor chips 3a to 3d can be mounted in the openings 2a to 2d of the printed circuit board 2. This eliminates the need for a jig such as carbon, making chip mounting easier.

[0098] Furthermore, in the semiconductor device according to the first embodiment, the printed circuit board 2 is joined to the upper surface side of the insulating circuit board 1, so that heat from the printed circuit board 2 is more easily transferred to the insulating circuit board 1 and the printed circuit board 2 is more easily cooled than in the case where the printed circuit board is disposed above the semiconductor chip as in the semiconductor device according to the second comparative example.

[0099] Furthermore, according to the semiconductor device of the first embodiment, the third-layer wiring layer 23a shown in Fig. 5 electrically connected to the gate control terminal 6a and the second-layer wiring layer 22a shown in Fig. 4 electrically connected to the auxiliary source terminal 6b are arranged opposite each other with the insulating layer 20 interposed therebetween, and the third-layer wiring layer 23g shown in Fig. 5 electrically connected to the gate control terminal 6d and the second-layer wiring layer 22e shown in Fig. 4 electrically connected to the auxiliary source terminal 6c are arranged opposite each other with the insulating layer 20 interposed therebetween. As a result, currents flow in the opposite directions between the third-layer wiring layer 23a and the second-layer wiring layer 22a, and between the third-layer wiring layer 23g and the second-layer wiring layer 22e, thereby reducing the wiring inductance.

[0100] Second embodiment Fig. 10 is a top view of the semiconductor device according to the second embodiment, and Fig. 11 is a vertical cross-sectional view taken along line AA' in Fig. 10. As shown in Figs. 10 and 11, the semiconductor device according to the second embodiment is different from the configuration of the semiconductor device according to the first embodiment shown in Figs. 1 and 2 in that source electrodes 32a, 32c of semiconductor chips 3a, 3c and a fourth-layer wiring layer 24c of a printed circuit board 2 are connected via lead frames 81, 83 which are connecting members, and source electrodes 32b, 32d of semiconductor chips 3b, 3d and a fourth-layer wiring layer 24i of a printed circuit board 2 are connected via lead frames 81-84 which are connecting members.

[0101] One end of the lead frame 81 is joined to the source electrode 32a of the semiconductor chip 3a, and the other end of the lead frame 81 is joined to the fourth-layer wiring layer 24c. One end of the lead frame 82 is joined to the source electrode 32b of the semiconductor chip 3b, and the other end of the lead frame 82 is joined to the fourth-layer wiring layer 24i. One end of the lead frame 83 is joined to the source electrode 32c of the semiconductor chip 3c, and the other end of the lead frame 83 is joined to the fourth-layer wiring layer 24c. One end of the lead frame 84 is joined to the source electrode 32d of the semiconductor chip 3d, and the other end of the lead frame 84 is joined to the fourth-layer wiring layer 24d. Other configurations of the semiconductor device according to the second embodiment are similar to those of the semiconductor device according to the first embodiment, so duplicated explanations will be omitted.

[0102] According to the semiconductor device of the second embodiment, similarly to the semiconductor device of the first embodiment, it is possible to miniaturize the semiconductor module (high density mounting), and it is also possible to easily inspect the alignment and joints when mounting components, thereby suppressing deterioration in quality. Furthermore, by using the lead frames 81 to 84 as the connecting members, it is possible to improve reliability.

[0103] Third embodiment Fig. 12 is a top view of the semiconductor device according to the third embodiment, and Fig. 13 is a vertical cross-sectional view taken along line AA' in Fig. 12. As shown in Figs. 12 and 13, the semiconductor device according to the third embodiment differs from the configuration of the semiconductor device according to the first embodiment shown in Fig. 3 in that semiconductor chips 3a-3d and fourth wiring layers 24c, 24d, 24e, 24f, 24g, 24i, 24l, 24m, 24n, and 24o are connected via flexible substrates 9a-9d, which are connecting members.

[0104] The flexible substrate 9a includes an insulating film (insulating layer) 90a and copper foils (conductive layers) 91a, 92a, and 93a provided on the lower surface side of the insulating film 90a. In FIG. 12, the copper foils 91a, 92a, and 93a hidden under the insulating film 90a are shown by dashed lines, and the same is true for the flexible substrates 9b to 9d. The copper foil 91a electrically connects the fourth-layer wiring layer 24d and the gate electrode 31a (see FIG. 1) of the semiconductor chip 3a. The copper foil 92a electrically connects the fourth-layer wiring layer 24e and the source electrode 32a (see FIG. 1) of the semiconductor chip 3a. The copper foil 93a electrically connects the source electrode 32a (see FIG. 1) of the semiconductor chip 3a and the fourth-layer wiring layer 24c.

[0105] As shown in Fig. 13, the thickness of the copper foil 92a is thinner than the thickness of the copper foil 93a. The copper foil 92a is joined to the source electrode 32a of the semiconductor chip 3a via a copper bump 94a. The thickness of the copper foil 91a shown in Fig. 12 is thinner than the thickness of the copper foil 93a. The copper foil 91a is joined to the gate electrode 31a of the semiconductor chip 3a via a copper bump (not shown) similar to the copper bump 94a.

[0106] The flexible substrate 9b includes an insulating film 90b and copper foils 91b, 92b, and 93b provided on the lower surface side of the insulating film 90b. The copper foil 91b electrically connects the fourth-layer wiring layer 24l and the gate electrode 31b (see FIG. 1) of the semiconductor chip 3b. The copper foil 92b electrically connects the fourth-layer wiring layer 24m and the source electrode 32b (see FIG. 1) of the semiconductor chip 3b. The copper foil 93b electrically connects the source electrode 32b (see FIG. 1) of the semiconductor chip 3b and the fourth-layer wiring layer 24i.

[0107] As shown in Fig. 13, the thickness of the copper foil 92b is thinner than the thickness of the copper foil 93b. The copper foil 92b is joined to the source electrode 32b of the semiconductor chip 3b via a copper bump 94b. The thickness of the copper foil 91b shown in Fig. 12 is thinner than the thickness of the copper foil 93a. The copper foil 91b is joined to the gate electrode 31b of the semiconductor chip 3b via a copper bump (not shown) similar to the copper bump 94b.

[0108] The flexible substrate 9c shown in FIG. 12 includes an insulating film 90c and copper foils 91c, 92c, and 93c provided on the lower surface side of the insulating film 90c. The copper foil 91c electrically connects the fourth-layer wiring layer 24f and the gate electrode 31c (see FIG. 1) of the semiconductor chip 3c. The copper foil 92c electrically connects the fourth-layer wiring layer 24g and the source electrode 32c (see FIG. 1) of the semiconductor chip 3c. The copper foil 93c electrically connects the source electrode 32c (see FIG. 1) of the semiconductor chip 3c and the fourth-layer wiring layer 24c. The configuration of the flexible substrate 9c is similar to that of the flexible substrates 9a and 9b.

[0109] The flexible substrate 9d shown in FIG. 12 includes an insulating film 90d and copper foils 91d, 92d, and 93d provided on the lower surface side of the insulating film 90d. The copper foil 91d electrically connects the fourth-layer wiring layer 24n and the gate electrode 31d (see FIG. 1) of the semiconductor chip 3d. The copper foil 92d electrically connects the fourth-layer wiring layer 24o and the source electrode 32d (see FIG. 1) of the semiconductor chip 3d. The copper foil 93d electrically connects the source electrode 32d (see FIG. 1) of the semiconductor chip 3d and the fourth-layer wiring layer 24i. The configuration of the flexible substrate 9d is the same as that of the flexible substrates 9a and 9b. Other configurations of the semiconductor device according to the third embodiment are the same as those of the semiconductor device according to the first embodiment, so that repeated explanations will be omitted.

[0110] According to the semiconductor device of the third embodiment, similarly to the semiconductor device of the first embodiment, it is possible to miniaturize the semiconductor module (high density mounting), and it is also possible to easily inspect the alignment and joints when mounting components, thereby suppressing deterioration in quality. Furthermore, by using flexible substrates 9a to 9d as connecting members, it is possible to improve reliability.

[0111] (Fourth embodiment) FIG. 14 is a top view of the semiconductor device according to the fourth embodiment. As shown in FIG. 14, the semiconductor device according to the fourth embodiment is different from the semiconductor device according to the first embodiment shown in FIG. 1 in that the insulating layer 20 of the printed circuit board 2 is not provided between the semiconductor chips 3a to 3d. The opening 2a surrounding the semiconductor chip 3a and the opening 2c surrounding the semiconductor chip 3c, which are provided in the insulating layer 20 of the printed circuit board 2, are continuous with each other. Also, the opening 2b surrounding the semiconductor chip 3b and the opening 2d surrounding the semiconductor chip 3d, which are provided in the insulating layer 20 of the printed circuit board 2, are continuous with each other. Other configurations of the semiconductor device according to the fourth embodiment are similar to those of the semiconductor device according to the first embodiment, so that repeated explanations will be omitted.

[0112] As with the semiconductor device of the first embodiment, the semiconductor device of the fourth embodiment enables miniaturization of the semiconductor module (high density mounting), and also makes it easier to inspect alignment and joints during component mounting, thereby suppressing deterioration in quality.

[0113] Fifth embodiment Fig. 15 is a cross-sectional view of the semiconductor device according to the fifth embodiment. As shown in Fig. 15, the semiconductor device according to the fifth embodiment differs from the configuration of the semiconductor device according to the first embodiment shown in Fig. 2 in that the insulating circuit board 1 is not provided and the semiconductor chips 3a and 3b are provided on a part of the printed circuit board 2.

[0114] The first wiring layers 21a and 21b of the printed circuit board 2 are embedded inside an insulating layer 20. A metal plate 7 is provided on the lower surface side of the first wiring layers 21a and 21b via the insulating layer 20. The metal plate 7 may be made of a metal such as copper.

[0115] Part of the upper surfaces of the first-layer wiring layers 21a, 21b are exposed from the openings 2a, 2b of the insulating layer 20. A semiconductor chip 3a is bonded to the exposed upper surface of the first-layer wiring layer 21a. The semiconductor chip 3a is provided inside the opening 2a. A semiconductor chip 3b is bonded to the exposed upper surface of the first-layer wiring layer 21b. The semiconductor chip 3b is provided inside the opening 2b. Other configurations of the semiconductor device according to the fifth embodiment are similar to those of the semiconductor device according to the first embodiment, so duplicated explanations will be omitted.

[0116] As with the semiconductor device of the first embodiment, the semiconductor device of the fifth embodiment enables miniaturization of the semiconductor module (high-density mounting), and also makes it easier to inspect alignment and joints during component mounting, thereby suppressing deterioration in quality.

[0117] (Other embodiments) As described above, the present invention has been described by the first to fifth embodiments, but the descriptions and drawings forming a part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments, examples, and operation techniques will become apparent to those skilled in the art from this disclosure.

[0118] For example, as the semiconductor device according to the first to fifth embodiments, a "2-in-1" configuration having the functions of two power semiconductor elements has been exemplified, but this is not limited thereto, and the present invention can also be applied to, for example, a "1-in-1" configuration having the functions of one power semiconductor element.

[0119] In addition, as the semiconductor device according to the first to fifth embodiments, the case where the printed circuit board 2 has four wiring layers has been exemplified, but the present invention is not limited thereto, and the number of layers can be appropriately adjusted according to the complexity of the circuit pattern, the magnitude of the main current, and the like. For example, the printed circuit board 2 may have five or more wiring layers. In addition, the printed circuit board 2 may have three wiring layers by forming the third wiring layers 23a, 23g electrically connected to the gate control terminals 6a, 6d and the second wiring layers 22a, 22e electrically connected to the auxiliary source terminals 6b, 6c in the same layer, or by not providing the auxiliary source terminals 6b, 6c.

[0120] Furthermore, in the semiconductor devices according to the first to fifth embodiments, the third-layer wiring layers 23a, 23g electrically connected to the gate control terminals 6a, 6d are the upper layers, and the second-layer wiring layers 22a, 22e electrically connected to the auxiliary source terminal 6b are the lower layers, but the top-bottom relationship may be reversed.

[0121] In addition, the configurations disclosed in the first to fifth embodiments can be appropriately combined within a range that does not cause contradictions. As such, the present invention naturally includes various embodiments not described here. Therefore, the technical scope of the present invention is determined only by the invention-specifying matters related to the claims that are appropriate from the above description. [Explanation of symbols]

[0122] 1...Insulated circuit board 2a~2d…opening 3a~3d…Semiconductor chips 4a~4e…Joining material 5a…P terminal 5b…N terminal 5c…Output terminal 6a, 6d...Gate control terminals 6b, 6c...Auxiliary source terminals 7...Metal plate 9a to 9d: Flexible substrate 11...Insulating substrate 12a,12b...Circuit board 13...Heat sink 20…Insulating layer 21x,21y…opening 21a, 21b, 22a~22e, 23a~22e, 24a~24o...wiring layer 31a to 31d: gate electrodes 32a to 32d: Source electrodes 33a, 33b...Drain electrodes 71a to 71d, 72a to 72d, 73a to 73d... Bonding wire 81~84…Lead frame 81a, 81b, 82a~82j, 83a~83j...Via 90a~90d…Insulating film 91a~91d, 92a~92d, 93a~93d...Copper foil 94a, 94b…Copper bump 101…Copper base 102...Insulated circuit board 103...Semiconductor chip 104 Terminal case 105, 106…External connection terminals 107...Gel sealant 110,111...Bonding wire 201...Insulated circuit board 202a, 202b...Semiconductor chip 203a, 203b... Post electrodes 204...Printed circuit board 206a~206c…External connection terminals 211...Insulating substrate 212a,212b...Circuit board 213...Heat sink 231~236…Through hole 241...insulating layer 242,242...Wiring layer D1, D2: Body diode G1, G2: Gate control terminals N: Source terminal P: Drain terminal S1, S2: Auxiliary source terminals T1, T2: Transistor U: Output terminal

Claims

1. a first semiconductor chip and a second semiconductor chip spaced apart from each other, each semiconductor chip having a first main electrode on an upper surface side and a second main electrode on a lower surface side; a printed circuit board having multiple wiring layers including a first wiring layer in an uppermost layer provided around the first and second semiconductor chips and electrically connected to the first main electrode of the first semiconductor chip through a connection member, and a second wiring layer in a lowermost layer electrically connected to the first wiring layer through a via and electrically connected to the second main electrode of the second semiconductor chip, and an insulating layer provided between the multiple wiring layers; A semiconductor device comprising:

2. The connection member is any one of a bonding wire, a lead frame, and a flexible substrate. The semiconductor device according to claim 1 .

3. The semiconductor device further includes an external connection terminal electrically connected to the first wiring layer. The semiconductor device according to claim 1 .

4. The plurality of wiring layers further includes a third wiring layer that is an uppermost layer provided apart from the first wiring layer and electrically connected to the first main electrode of the second semiconductor chip via a connecting member. The semiconductor device according to claim 1 .

5. The third wiring layer is electrically connected to an external connection terminal. The semiconductor device according to claim 4.

6. The plurality of wiring layers are a third wiring layer that is a lowermost layer and is provided at a distance from the second wiring layer and is electrically connected to the second main electrode of the first semiconductor chip; a fourth wiring layer that is an uppermost layer and is provided at a distance from the first wiring layer and is electrically connected to the third wiring layer through a via; Further comprising The semiconductor device according to claim 1 .

7. The fourth wiring layer is electrically connected to an external connection terminal. The semiconductor device according to claim 6.

8. the first semiconductor chip further includes a control electrode on an upper surface side; The plurality of wiring layers are a third wiring layer that is an uppermost layer provided at a distance from the first wiring layer and electrically connected to the control electrode of the first semiconductor chip via a connecting member; a fourth wiring layer that is electrically connected to the third wiring layer through a via and is located below the third wiring layer; a fifth wiring layer that is an uppermost layer and is provided at a distance from the first wiring layer and the third wiring layer and is electrically connected to the fourth wiring layer through a via; Further comprising The semiconductor device according to claim 1 .

9. a first control terminal electrically connected to the fifth wiring layer The semiconductor device according to claim 8.

10. The plurality of wiring layers are a sixth wiring layer as an uppermost layer provided at a distance from the first wiring layer, the third wiring layer, and the fifth wiring layer, and electrically connected to the first main electrode of the first semiconductor chip via a connecting member; a seventh wiring layer that is lower than the fourth wiring layer and is electrically connected to the sixth wiring layer through a via; an eighth wiring layer that is an uppermost layer provided apart from the first wiring layer, the third wiring layer, the fifth wiring layer, and the sixth wiring layer and is electrically connected to the seventh wiring layer through a via; Further comprising The semiconductor device according to claim 8.

11. a second control terminal electrically connected to the eighth wiring layer The semiconductor device according to claim 10.

12. The fourth wiring layer and the seventh wiring layer face each other with the insulating layer interposed therebetween. The semiconductor device according to claim 10.

13. The via that connects the seventh wiring layer and the eighth wiring layer passes through a through hole provided in the fourth wiring layer. The semiconductor device according to claim 12.

14. The printed circuit board is a first opening surrounding the first semiconductor chip; a second opening surrounding the second semiconductor chip; It is provided The semiconductor device according to claim 1 .

15. an insulating circuit board including an insulating substrate, a first circuit board and a second circuit board spaced apart from each other on an upper surface side of the insulating substrate, and a heat sink provided on a lower surface side of the insulating substrate; the first semiconductor chip is disposed on the first circuit board; The second semiconductor chip is disposed on the second circuit board. The semiconductor device according to claim 1 .

16. the plurality of wiring layers further includes a third wiring layer that is a lowermost layer and is provided at a distance from the second wiring layer and is electrically connected to the second main electrode of the first semiconductor chip; a portion of an upper surface of each of the second wiring layer and the third wiring layer is exposed from the insulating layer; the first semiconductor chip is provided on an exposed upper surface of the third wiring layer; The second semiconductor chip is provided on the exposed upper surface of the second wiring layer. The semiconductor device according to claim 1 .

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