Processor, and computer system for alignment processing

Abstract

To provide a suitable processor for alignment processing.SOLUTION: A processor (core A3) includes: a first source operand; a second source operand; a third source operand; a fourth source operand; a fifth source operand; and a sixth source operand. The processor (core A3) also includes: a first adder-subtractor for computing a first intermediate sum of the element of the first source operand and the element of the second source operand; a second adder-subtractor for computing a second intermediate sum of the element of a third source operand and the element of the fourth source operand; and a third adder-subtractor for computing a third intermediate sum of the element of the fifth source operand and sixth resultant data obtained based on the element of the sixth source operand. Further, the processor (core A3) has a selector for selecting the maximum value and / or the minimum value from among at least the first intermediate sum, the second intermediate sum, and the third intermediate sum.SELECTED DRAWING: Figure 21

Description

[Technical field]

[0001] The present invention relates to a processor that is applied to an alignment processing computer system or the like. [Background technology]

[0002] The human genome is a set of genetic information that a person possesses, and the material that carries this information is DNA (deoxyribonucleic acid), which is a string of approximately 3 billion pairs of bases. The bases are adenine (A), guanine (G), cytosine (C), and thymine (T). In other words, a person's genetic information is determined by the arrangement (sequence) of these bases.

[0003] A device called a sequencer is used to read the human genome. The sequencer reads the sample human genome, cuts it into a specified upper limit (several hundred base pairs), amplifies it, and outputs a huge data sequence consisting of hundreds of millions of pieces of genetic information. Current sequencers can read one human genome in about an hour.

[0004] The individual pieces of data read by the sequencer are compared with the human genome reference sequence, which is defined as the standard genome sequence for humans, and then reconstructed into the original length of the human genome sequence and analyzed. For example, the position of each piece of data is examined (mapped) in comparison with the human genome reference sequence. After mapping is complete, analysis is also performed to determine what mutations are present.

[0005] For mapping data fragments, a program tool such as BWA (Burrow-Wheeler Aligner) is used. BWA consists of three algorithms, BWA-backtrack, BWA-SW, and BWA-MEM. Of these, BWA-MEM is widely used as a high-speed algorithm that supports Indels (insertion deletions). BWA-MEM is an algorithm that creates an index using a suffix sequence for the part of a query string based on the read data fragment that appears repeatedly in the human genome reference sequence, and performs mapping.

[0006] The mapped data fragment (matching character string) is matched with a partial sequence (matched character string) at the same position in the human genome reference sequence, and the type of mutation is analyzed. For example, an alignment algorithm is used to match the partial sequence of the human genome reference sequence with the data fragment. In the alignment algorithm, a similar character string is identified while calculating the degree of mutation (similarity) for each element of a sequence called an alignment table according to dynamic programming. Examples of the alignment algorithm include the Smith-Waterman algorithm, the Smith-Waterman-Gotoh algorithm, and the Needleman-Wunsch algorithm (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0007] [Patent Document 1] U.S. Patent No. 11,550,584 Summary of the Invention [Problem to be solved by the invention]

[0008] In a computer processor in which the above-mentioned alignment algorithm is executed, multiple instructions are executed when calculating the degree of variation (similarity) of each element (cell) of an alignment table (alignment array), and the processing speed is accordingly slowed down. Furthermore, when multiple instructions are executed, access to an external memory is required, and the processing speed of the processor is limited by the access time to the memory.

[0009] An object of the present invention is to provide a processor suitable for alignment processing. Another object of the present invention is to provide, for example, a technique for performing alignment processing at high speed and / or efficiently. [Means for solving the problem]

[0010] In relation to the above object, the present invention is a processor comprising a first source operand, a second source operand, a third source operand, a fourth source operand, a fifth source operand, a sixth source operand, a first adder / subtractor for calculating a first intermediate sum of elements of the first source operand and elements of the second source operand, a second adder / subtractor for calculating a second intermediate sum of elements of the third source operand and elements of the fourth source operand, a third adder / subtractor for calculating a third intermediate sum of sixth cause data obtained based on the elements of the fifth source operand and elements of the sixth source operand, and a selector for selecting a maximum value and / or a minimum value from at least the first intermediate sum, the second intermediate sum, and the third intermediate sum.

[0011] The above processor may be characterized in that the first source operand, the third source operand, and the fifth source operand are stored in a general-purpose register file, and the second source operand, the fourth source operand, and the sixth source operand are stored in a dedicated register file.

[0012] The processor may further include a seventh source operand and a second selection unit, and the sixth cause data may be data selected by the second selector from at least elements of the sixth source operand and the seventh source operand.

[0013] The processor may further include an eighth source operand, and the selector may select maximum and / or minimum values ​​from among at least the first intermediate sum, the second intermediate sum, the third intermediate sum, and elements of the eighth source operand.

[0014] The above processor may further include an instruction decoder that decodes instructions, and a single instruction decoded by the instruction decoder may execute the calculation of the first intermediate sum by the first adder / subtractor, the calculation of the second intermediate sum by the second adder / subtractor, the calculation of the third intermediate sum by the third adder / subtractor, and the selection of the maximum value and / or the minimum value by the selector.

[0015] The present invention, which relates to the above object, provides a left-upward variation source operand, the element of which is a variation on the left diagonal with respect to a current position of an alignment matrix used in an alignment process between a first character string and a second character string; a true-left variation source operand, the element of which is a variation on the true-left with respect to the current position of the alignment matrix; a penalty source operand, the element of which is a linear gap penalty value of the alignment process; a true-upward variation source operand, the element of which is a variation with respect to the current position of the alignment matrix; a first adder / subtractor for calculating a first intermediate sum of elements of the left variance source operand and elements of the penalty source operand; a second adder / subtractor for calculating a second intermediate sum of elements of the diagonal-up variance source operand and a score function value based on a match / mismatch between elements of the first string and elements of the second string corresponding to the current position; and a mutation selector for selecting a maximum value and / or a minimum value from at least the first intermediate sum, the second intermediate sum, and the third intermediate sum.

[0016] The processor may include a match score source operand, a mismatch score source operand, a first string character source operand whose elements are characters in a first string corresponding to the current position, a second string character source operand whose elements are characters in a second string corresponding to the current position, and a score function selector that selects an element of the match score source operand when an element of the first string character source operand matches an element of the second string character source operand, and that selects an element of the mismatch score source operand and outputs the element as the score function value when an element of the first string character source operand does not match an element of the second string character source operand.

[0017] The processor may comprise a score function source operand, the score function value being stored in the score source operand.

[0018] In the above processor, the left diagonal-upward mutation source operand, the directly above mutation source operand, and the directly left mutation source operand may be stored in a general-purpose register file, and the gap source operand may be stored in a dedicated register file.

[0019] The processor may further include a restriction constant source operand having a restriction constant as an element, and the variance selector may select a maximum value and / or a minimum value from among at least the first intermediate sum, the second intermediate sum, the third intermediate sum, and elements of the restriction constant source operand.

[0020] The above processor may further include an instruction decoder that decodes instructions, and a single mutation degree calculation instruction by the instruction decoder may collectively execute the calculation of the first intermediate sum by the first adder / subtractor, the calculation of the second intermediate sum by the second adder / subtractor, the calculation of the third intermediate sum by the third adder / subtractor, and the selection of the maximum value and / or the minimum value by the mutation degree selector.

[0021] The present invention, which relates to the above-mentioned object, is a computer device for alignment processing, which has a storage device in which a first character string and a second character string are stored, and a processor, and which performs alignment processing using an alignment matrix of the first character string and the second character string, wherein the processor is any of those described above, and the processor calculates the degree of deviation of the current position of the alignment matrix based on an alignment program stored in the storage device. Effect of the Invention

[0022] According to the present invention, the alignment process can be performed quickly and / or efficiently by a processor suitable for the alignment process. [Brief description of the drawings]

[0023] [Figure 1]1 is a block diagram showing an example of a schematic configuration of a computer system according to an embodiment of the present invention. [Diagram 2] 10 is a flowchart illustrating an example of an approximate string matching process performed by the computer system. [Diagram 3] 13 is a flowchart illustrating an example of an alignment process procedure performed by the computer system. [Figure 4] 13 is a block diagram illustrating an example of functional blocks of an alignment processing computer system realized by the computer system. FIG. [Diagram 5] FIG. 2 is a diagram showing the data structure of an alignment matrix used in the alignment process of the computer system. [Figure 6] FIG. 13 is a diagram showing the partitioning of the alignment matrix and the order of calculation of the degree of mutation of each partition. [Figure 7] FIG. 13 is a diagram showing a modified example of partition division of the alignment matrix and the order of calculation of the degree of mutation of each partition. [Figure 8] FIG. 13 is a diagram showing a modified example of partition division of the alignment matrix and the order of calculation of the degree of mutation of each partition. [Figure 9] FIG. 13 is a diagram showing a concept of calculating the mutation degree and the return pathway flag in a data cell of the alignment matrix. [Figure 10] FIG. 13 is a diagram showing backtrack data in the same alignment matrix. [Figure 11] FIG. 13 is a diagram showing a specific example of mutation calculation using the same alignment matrix. [Figure 12] FIG. 13 is a diagram showing a specific example of mutation calculation using the same alignment matrix. [Figure 13] FIG. 13 is a diagram showing a specific example of backtrack data using the same alignment matrix. [Figure 14] FIG. 2 is a diagram showing the data structure of a score matrix used in the alignment process of the computer system. [Figure 15] FIG. 2 is a diagram illustrating an example of a hardware configuration of the computer system. [Figure 16]FIG. 2 is a block diagram showing an example of a processor module in the hardware configuration of the computer system. [Figure 17] 2 is a block diagram showing the internal configuration of a core of the processor module. FIG. [Figure 18] 1 is a block diagram showing the internal configurations of a general-purpose register file, a dedicated register file, and a mutation-dedicated arithmetic logic unit of the core. FIG. [Figure 19] FIG. 13 is a block diagram showing a modified example of the internal configuration of the core. [Figure 20] FIG. 13 is a block diagram showing a modified example of the internal configuration of the core. [Figure 21] FIG. 13 is a block diagram showing a modified example of the internal configuration of the core. [Figure 22] FIG. 13 is a block diagram showing a modified example of the internal configuration of the core. [Figure 23] FIG. 13 is a block diagram showing a modified example of the internal configuration of the core. [Figure 24] FIG. 13 is a block diagram showing a modified example of the internal configuration of the core. [Diagram 25] FIG. 13 is a block diagram showing a modified example of the internal configuration of the core. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. However, the embodiment described below is merely an example, and there is no intention to exclude various modifications and application of techniques not specified below. The present invention can be implemented by various modifications (for example, combining the respective embodiments) within the scope of the gist of the present invention. In addition, in the following description of the drawings, the same or similar parts are represented by the same or similar reference numerals. The drawings are schematic and do not necessarily correspond to actual dimensions, ratios, etc. The drawings may also include parts with different dimensional relationships and ratios.

[0025] FIG. 1 is a block diagram showing an example of a schematic configuration of a computer system according to an embodiment of the present invention. As shown in the figure, the computer system 1 includes, for example, a host computer 10, a plurality of lower computers 20(1)-20(n), and a database 30. The host computer 10 and the lower computers 20(1)-20(n) are communicatively connected via a predetermined interface. In the present disclosure, the computer system 1 is configured as a centralized computer system in which the host computer 10 comprehensively controls the plurality of lower computers 20(1)-20(n), but is not limited thereto and may be configured as, for example, a distributed computer system. In a distributed computer system, each computer can operate cooperatively by parallel distributed processing, but for a specific process, only one representative computer may execute the process.

[0026] The computing hardware common to the upper computer 10 and the lower computer 20 is a computing device 100 as exemplified in Fig. 15. The computing device 100 has a memory module 102 serving as a main storage device such as a DRAM, a processor module 104 serving as a central computer, a chipset 106 serving as a bridge between the processor module 104 and an external device, an internal storage device 108 such as an HDD or SDD, an I / O controller 110, an output interface 112, an input / output interface 114, a communication interface 116, and an external storage device 118 such as an external HDD.

[0027] 16, the processor module 104 includes a plurality of cores A, B, C, and D that execute independent calculation processes, first cache memories (L1 cache memories) L1a, L1b, L1c, and L1d and second cache memories (L2 cache memories) L2a, L2b, L2c, and L2d that are provided for each of the cores A, B, C, and D, and a third cache memory (L3 cache memory) L3n that is shared by all the cores A, B, C, and D. The access latency of the cores A, B, C, and D is shortest for the L1 cache memories L1a, L1b, L1c, and L1d, followed by the L2 cache memories L2a, L2b, L2c, and L2d, and longest for the L3 cache memory L3n. On the other hand, the access latency of the L1, L2, and L3 cache memories is significantly shorter than that of the memory module (main memory) 102. With these structures, the multiple cores A, B, C, and D in the processor module 104 can process tasks in parallel. For example, each of the multiple cores A, B, C, and D can perform analysis processing in comparison with a reference string based on a given individual query string. Here, a case where the cache memory is divided into three stages is illustrated, but the present invention is not limited to this, and may be one or two stages, or may be four or more stages. Hereinafter, the first cache memory (L1 cache memory) L1a, L1b, L1c, and L1d, the second cache memory (L2 cache memory) L2a, L2b, L2c, and L2d, and the third cache memory (L3 cache memory) L3n can be collectively referred to as "cache memory". In the present invention, the number of cores in the processor module 104 is not particularly limited. The number of cores can be selected from a variety of numbers, from several to tens of thousands.

[0028] 15 and 16 show examples of general-purpose hardware structures, but the present invention is not limited thereto. All or part of these hardware structures may employ hardware that is individually customized (programmed) by an FPGA or the like. Furthermore, hereinafter, the memory module 102, the internal storage device 108, the external storage device 118, the first cache memory (L1 cache memory) L1a, L1b, L1c, and L1d, the second cache memory (L2 cache memory) L2a, L2b, L2c, and L2d, and the third cache memory (L3 cache memory) L3n, which are hardware capable of storing data, may be collectively referred to as a "storage device."

[0029] Returning to FIG. 1, in the present disclosure, the lower computers 20 process tasks in parallel under the control of the upper computer 10. For example, each of the multiple lower computers 20 performs analysis processing in comparison with a reference string based on an individual given query string. Hereinafter, the lower computers 20(1) to 20(n) may be simply referred to as "lower computers 20" unless there is a particular need to distinguish between them.

[0030] The database 30 stores various data, such as reference character strings, under the control of the host computer 10. As an example, the database 30 stores a human genome reference sequence. The human genome reference sequence is data showing a sequence of base pairs defined as a standard genome sequence for humans. The database 30 also stores an index created based on the reference character string. The index is a type of data array structure used to search for the reference character string. In the figure, the database 30 is configured to be connected so as to be accessible only to the host computer 10, but this is not limited thereto, and the lower computer 20 may also be connected so as to be accessible. The lower computer 20 may also have a similar database. Here, a case where a human genome reference sequence is used is illustrated, but a metagenomic reference sequence that compiles multiple organisms (animals), plants, etc. may also be used.

[0031] 2 is a flowchart for explaining an example of an outline of approximate string matching processing by the computer system 1 according to an embodiment of the present invention. This processing is realized, for example, by the host computer 10 and the multiple lower level computers 20 executing an approximate string matching program in the processor module 104 in cooperation with other hardware components. As a result, the computer system 1, or the host computer 10, or the multiple lower level computers 20 function as an approximate string matching computer system 200 shown in FIG. 4. The approximate string matching program has multiple processing blocks (subroutines), and as a result, the approximate string matching computer system 200, in more detail, includes an index creation computer system 201, a mapping computer system 202, a string pair creation computer system 203, and an alignment processing computer system 204.

[0032] As shown in FIG. 2, first, the host computer 10 reads out the reference string stored in the database 30, and creates an index based on the read reference string (index creation process: S201). Specifically, the host computer 10 creates an index having a predetermined data array structure by expanding and / or sorting and arranging substrings in the reference string according to a predetermined condition. The data array structure is a hierarchical tree structure. In the present disclosure, such an index is referred to as a hierarchical index. The host computer 10 stores the created index based on the reference string in the database 30. The process of creating a hierarchical index based on the reference string will be described in detail later. Note that if a hierarchical index based on the reference string has already been created and stored in the database 30, the index creation process S201 may be omitted. In this way, the computer system 1 functions as an index creation computer system 201.

[0033] Next, the host computer 10 receives a query string from an external device (not shown), refers to the hierarchical index based on the received query string, and performs a mapping process of the query string to the reference string (mapping process: S202). In one example, the external device is a sequencer that reads out a human genome, and the query string is a data piece of about 150 to 200 base pairs output from the sequencer. The query string may be temporarily stored in the database 30. The number of characters in the query string is preferably 50 or more, more preferably 100 or more. On the other hand, the number of characters in the query string is preferably 1000 or less, desirably 300 or less, and more desirably 200 or less. In the present disclosure, the lower computer 20 also performs mapping by referring to the hierarchical index based on the assigned query string under the control of the upper computer 10. Thereby, the computer system 1 functions as a mapping computer system 202.

[0034] Mapping is a process of identifying a substring (matching string) in a reference string that matches at least a portion of a query string. That is, mapping identifies the start position and length (number of characters) of a substring in the reference string that matches at least a portion of the query string. In the mapping according to the present disclosure, a hierarchical index is searched or explored for the query string to identify the start position of the query string in the reference string. In order to speed up processing, the created hierarchical index is preferably expanded in a high-speed memory such as a cache memory in memory module 102 or processor module 104.

[0035] In the above example, the upper computer 10 and the lower computer 20 each perform mapping according to the assigned query string, but this is not limited to this. For example, only the upper computer 10 may perform a search by referring to the hierarchical index based on the assigned query string.

[0036] Next, the host computer 10 and the lower computer 20 each create a string pair for approximate string matching (string pair creation process: S203), which will be described later. The string pair is composed of a matched string in the reference string, including a matching string identified by mapping, and a matching string in the query string. In this way, the computer system 1 functions as a string pair creation computer system 203.

[0037] Specifically, the host computer 10 and the lower computer 20 create a matched string by adding a corresponding string of a predetermined length in the reference string to the beginning and end of the matching string identified by mapping. In other words, the matched string is a string in the vicinity of the matching string including the matching string identified in the reference string. For example, if the reference string is "CCGATCTGTATACCCTACGA" and the matching string is "TACC", the string "TATACCCT" obtained by adding two characters to the beginning and end becomes the matched string. In the case of human genome analysis, the length of bases added to the beginning and end of the matching string for the reference string may be, for example, about 50 bases.

[0038] In addition, the host computer 10 creates a comparison string by adding a corresponding string of a predetermined length in the query string to the end of the match string. In the case of analyzing the human genome, the length of the string to be added to the end of the match string for the query string is, for example, about 50 bases.

[0039] In the present disclosure, a reference string is added with a character string of a predetermined length to the beginning and end of a matching string, but this is not limited thereto, and for example, a character string of a predetermined length may be added only to either the beginning or the end. Also, a query string may be added with a character string of a predetermined length to the beginning and end of a matching string, or the matching string itself may be treated as a matching string without adding a character string.

[0040] Next, the upper computer 10 and the lower computer 20 derive at least one approximate string based on a string pair consisting of a matched string based on the reference string and a matched string based on the query string (alignment process: S204). A predetermined alignment using dynamic programming is applied to derive the approximate string. Alignment is a method of comparing two sequences (strings) while allowing substitution, insertion, and deletion between their elements, and calculating the degree of variation (similarity) according to a defined score / penalty. As an algorithm for realizing alignment, the Smith-Waterman algorithm and the Needleman-Wunsch algorithm are known. Dynamic programming is a method of calculating the optimal solution for the next stage based on the optimal solution obtained at a certain stage. That is, in the calculation of the degree of variation, a score is calculated for each element of the alignment table in the form of an array according to dynamic programming, and the element with the maximum score is determined, thereby deriving at least one approximate string. As a result, the computer system 1 functions as an alignment processing computer system 204.

[0041] As described above, in the approximate string matching process of this embodiment, after a hierarchical index based on a reference string is created, a matching string (and its length) is identified by searching the hierarchical index according to a given query string, and an approximate string is derived by performing approximate string matching on a string pair consisting of a matched string and a match string based on the identified matching string. In other words, the approximate string matching program of this embodiment has an index creation program based on a reference string, a mapping program that searches the hierarchical index according to the query string, a program that creates a string pair consisting of a matched string and a match string, and an alignment program that derives an approximate string by performing approximate string matching using the string pair. Note that the index creation program, mapping program, and string pair creation program can be publicly known programs, so detailed explanations will be omitted.

[0042] <Alignment process> First, the alignment process will be described. In this embodiment, the alignment process will be performed using dynamic programming. The alignment process is a method of comparing two sequences (character strings), a character string (matched character string) near an identified appearance start position in a reference character string and a query character string (matching character string), while allowing substitution, insertion, and deletion between elements, and calculating a degree of variation (similarity) according to a defined score / penalty. For example, in a comparison between a matched character string X (i.e., a matched character string based on a reference character string) and a character string Y (i.e., a matching character string based on a query character string), if some characters in the matching character string Y are substituted, inserted, or deleted, the matching character string Y is determined not to match the matched character string X. In other words, the relationship between the characters at each position in each of the matched character string X and the matching character string Y can be said to be one of the cases where they match (match), do not match (mismatch), and one character does not exist (gap). In this disclosure, the Needleman-Wunsch algorithm, which is an example of global alignment, will be described for calculating the degree of variation. For ease of understanding, the following describes an example of performing alignment processing between an extremely short eight-character match string X and a match string Y. Note that the actual number of strings is about 150 to 200, or more.

[0043] In the alignment process, a data set of a matrix (grid) alignment matrix V (alignment table) shown in Figure 5 is generated using a matched string X and a matching string Y. In the table, "φ" means a null character. Here, the matched string X is defined as X = x1 x2 .. xi, the matching string Y is defined as Y = y1 y2 .. yj, and a specific position (i,j) in the alignment matrix V is defined as a data storage cell v(i,j).

[0044] <Alignment processor (core)> Next, the internal configuration of each of the cores A, B, C, and D used in the alignment process in the upper computer 10 and the lower computer 20 will be described with reference to Fig. 17. Note that since the internal configurations of the cores A, B, C, and D that are processed in parallel are the same, only the core A will be described here, and descriptions of the other cores B, C, and D will be omitted.

[0045] Core A has a program counter 800, a decoder 804, a general-purpose register file 806, a dedicated register file 808, and an execution unit 830. The program counter 800 is a register that holds the address of the instruction currently being executed by Core A. Core A uses the value of this register to refer to the storage device and obtain the instruction stored at the corresponding address. When the execution of an instruction is completed, the address of the next instruction to be executed is set in the program counter according to the execution result.

[0046] The decoder 804 analyzes the type of instruction and the operands required for the operation by looking at the bit string of the instruction. Depending on the analysis result, the necessary operands are read from the general-purpose register file 806 and / or the dedicated register file 808. The decoder 804 also selects an appropriate arithmetic unit in the execution unit 830, and switches the data path so that the signal read from the general-purpose register file 806 and / or the dedicated register file 808 is sent to the selected arithmetic unit. The general-purpose register file 806 and the dedicated register file 808 are areas for temporarily storing data required for the operation. The general-purpose register file 806 and the dedicated register file 808 are made up of multiple registers, and one piece of data is basically stored in one register. The dedicated register file 808 of this embodiment is different from the register file for system control, and means that it is a file that exclusively stores only specific data among the data required for the operation. Data in the storage device is written to the general-purpose register file 806 and the dedicated register file 808 by executing a load instruction. Also, the data is written back to the main storage device by a store instruction.

[0047] The execution unit 830 has various built-in calculators, such as an adder / subtractor 832, a multiplier 834, and a floating-point calculator 836. In particular, the execution unit 830 of this embodiment has a mutation-dedicated arithmetic logic unit 840 that is selected to calculate the mutation in the alignment process. The calculation results of the execution unit 830 are written to the designated general-purpose register file 806 and / or dedicated register file 808.

[0048] These cores A, B, C, and D are controlled by an alignment processing kernel, which is included as part of an alignment program described later.

[0049] <Register file> 18 shows the detailed configuration of the general-purpose register file 806 and the dedicated register file 808 of the core A. The general-purpose register file 806 stores an upper array character source operand 806A, a left array character source operand 806B, a left diagonally upward mutation source operand 806C, a directly above mutation source operand 806D, a directly left mutation source operand 806E, and an output destination operand 806F. The upper array character source operand 806A receives a matched character string xi corresponding to the data storage cell v(i,j). The left array character source operand 806B receives a matched character string yj corresponding to the data storage cell v(i,j). The left diagonally upward mutation source operand 806C receives a mutation (score) F(i-1,j-1) of the cell v(i-1,j-1) diagonally above and to the left of the data storage cell v(i,j). The directly above mutation source operand 806D receives the mutation (score) of the cell v(i,j-1) directly above the data storage cell v(i,j). The directly left mutation source operand 806E receives the mutation (score) of the cell v(i-1,j) directly to the left of the data storage cell v(i,j). The destination operand 806F receives the output data of the mutation dedicated arithmetic logic unit 840, which will be described later.

[0050] The dedicated register file 808 stores a match score source operand 808A, a mismatch score source operand 808B, a gap score source operand 808C, and a penalty source operand 808D. The match score source operand 808A receives the match score (e.g., "+2") of a pair of character pairs (xj, yj) selected from a matched string X and a match string Y. The mismatch score source operand 808B receives the mismatch score (e.g., "-1") of a pair of character pairs (xj, yj). The gap score source operand 808C receives the gap score (e.g., "-2") of a pair of character pairs (xj, yj). The penalty source operand 808D receives the value of the gap penalty (e.g., "-2").

[0051] <Mutation Dedicated Arithmetic Logic Unit 840> The arithmetic logic unit 840 dedicated to the variation has a score function selector 841B, a first adder / subtractor 840A, a second adder / subtractor 840B, a third adder / subtractor 840C, and a variation selector 841A. The score function selector 841B is a multiplexer that refers to each element of the upper array character source operand 806A, the left array character source operand 806B, the match score source operand 808A, the mismatch score source operand 808B, and the gap score source operand 808C and outputs a score based on a score function s (described later). The third adder / subtractor 840C adds an element of the left diagonally upward variation source operand 806C and an output element of the score function selector 841B. The first adder / subtractor 840A adds an element of the directly above variation source operand 806D and an element of the penalty source operand 808D. The second adder / subtractor 840B adds an element of the true left mutation source operand 806E and an element of the penalty source operand 808D. The mutation selector 841A is a multiplexer that selects the maximum or minimum value (here, the maximum value) of the output element of the first adder / subtractor 840A, the output element of the second adder / subtractor 840B, and the output element of the third adder / subtractor 840C. In particular, the mutation selector 841A can adopt a configuration in which individual selectors (multiplexers) that select the larger and / or smaller value of a pair of elements are connected in multiple stages to select the maximum and / or minimum values ​​of three or more elements.

[0052] <Alignment program> Next, the alignment program will be described. The alignment program executes alignment processing using dynamic programming. The alignment program allows the host computer 10 and the lower computer 20 to estimate how much a string pair consisting of a string (matched string) near the identified appearance start position in the reference string and a query string (matching string) varies from each other (degree of variation).

[0053] Fig. 3 is a flow chart for explaining an example of an alignment processing procedure by the computer system according to this embodiment. That is, Fig. 3 shows details of the alignment processing (S204) in the approximate string matching processing shown in Fig. 2. Fig. 4 also shows a functional block configuration of the alignment processing computer system 204. The alignment processing computer system 204 has an alignment matrix creation means 602, a constant setting means 604, a filling area selection means 606, a filling route setting means 608, a filling cell selection means 610, a variation / path calculation means 612, a backtrack processing means 620, and an approximate string derivation means 622.

[0054] (Alignment matrix creation means 602 / Alignment matrix creation step S602) In the alignment matrix creation step S602, the alignment matrix creation means 602 generates a data group of an (m+1)×(n+1) matrix-shaped alignment matrix V (alignment table) shown in FIG. 5 using the matched string X and the matching string Y. In the table, "φ" means a null character. Here, the matched string X is defined as X=x1x2...xi...xm, the matching string Y is defined as Y=y1y2.. .yj...n, and a specific position (i,j) in the alignment matrix V is defined as a data storage cell v(i,j). The alignment matrix creation means 602 is synonymous with the process of selecting a string pair of the matched string X and the matching string Y to be aligned (storing them at a specified address in a storage device).

[0055] (Constant setting means 604 / constant setting step S604) In the constant setting step S604, the constant setting means 604 sets constants required for the alignment process. Specifically, it sets the match, mismatch, and gap scores of a pair of character pairs (xj, yj) selected from the matched string X and the matched string Y, and the gap penalties between the top and bottom and the left and right of the cells. In this embodiment, the score when the character pairs match is set to, for example, "+2", the score when the characters do not match is set to, for example, "-1", and the score when the character pairs have a gap is set to, for example, "-2", and the gap penalty is set to, for example, "-2". Based on this constant setting means 604, the alignment process kernel takes these values ​​into the match score source operand 808A, the mismatch score source operand 808B, the gap score source operand 808C, and the penalty source operand 808D of the dedicated register file 808.

[0056] (Filling area selection means 606 / Filling area selection step S606) In the filling region selection step S606, the filling region selection means 606 generates a plurality of array regions V1V2...Vk...Vp by dividing the alignment matrix V into a plurality of (p) sections as shown in FIG. 6, for example, and selects the array region Vk for calculation in order according to the arrangement order. In FIG. 6, the alignment matrix V is divided into a plurality of sections in the vertical direction, so that the array region Vk is a group of cells that are continuous in the left-right direction. There are various division methods other than that shown in FIG. 6. For example, in FIG. 7, the alignment matrix V is divided into a plurality of sections in the horizontal direction, so that the array region Vk is a group of cells that are continuous in the up-down direction. For example, in FIG. 8, the alignment matrix V is divided into a plurality of sections in a lattice shape, so that the array region Vk is a group of cells that are continuous in the up-down and left-right directions. The order of the multiple array areas V1V2...Vk...Vp is set so that, for the data storage cell v(i,j) being the subject of the operation, the calculations of the cell v(i-1,j-1) diagonally to the left, the cell v(i,j-1) directly above, and the cell v(i-1,j) directly to the left are always executed first.

[0057] Specifically, to determine the array area Vk, a substring pair of a substring {xs...xi...xe} of the matched string X and a substring {ys...yi...ye} of the matched string Y is extracted from the string pair X·Y of the matched string X and the matched string Y, and stored as the array area Vk at a predetermined address in the storage device. Note that (xs, ys) means the start character of the substring pair, and (xe, ye) means the end character of the substring pair. Selection of substrings in the matched string X must be performed in order from left to right, and selection of substrings in the matched string Y must be performed in order from top to bottom. The size of the array area Vk is preferably a size that fits in the cache memory. In this embodiment, a size that fits in the L1 cache memory is preferable, a size that fits in the L2 cache memory is more preferable, and a size that fits in the L3 cache memory is even more preferable. Note that, although an example has been given here of dividing the alignment matrix V into multiple (p) sections, the present invention is not limited to this, and the filling area selection means 606 may extract one sequence area that will become a part of the alignment matrix V from within the range of the alignment matrix V (in other words, excluding unnecessary sequences) and calculate the degree of mutation only within that extracted range.

[0058] (Filling route setting means 608 / Filling route setting step S608) In the filling route setting step S608, the filling route setting means 608 defines the calculation order (calculation route) Rk of the data storage cell v(i,j) in the array area Vk. The setting of this calculation order Rk takes into account the selection order of the array area Vk in the filling area selection step S606, and sets an order in which, for example, as shown by the arrow in Fig. 6, the calculations of the cell v(i-1,j-1) diagonally above to the left, the cell v(i,j-1) directly above, and the cell v(i-1,j) directly to the left are always executed first for the data storage cell v(i,j) to be calculated. Here, the calculation order moving from left to right is selected, but, for example, as shown in Fig. 7, the calculation order Rk moving from top to bottom may be selected, or the calculation order Rk moving diagonally as shown in Fig. 8 may be selected.

[0059] (Filling cell selection means 610 / Filling cell selection step S610) 9, the fill cell selection means 610 selects the data storage cell v(i,j) to be operated on in the order set by the fill route setting means 608. Based on this fill cell selection means 610, the alignment processing kernel imports the character set (xi,yj) corresponding to the data storage cell v(i,j) into the upper array character source operand 806A and the left array character source operand 806B of the general-purpose register file 806. Furthermore, the alignment processing kernel imports the mutation (score) F(i-1, j-1) that has been pre-calculated (stored in a storage device) for the cell v(i-1, j-1) diagonally above to the left into the left-upward mutation source operand 806C, imports the mutation (score) F(i, j-1) that has been pre-calculated (stored in a storage device) for the cell v(i, j-1) directly above into the directly above mutation source operand 806D, and imports the mutation (score) F(i-1, j) that has been pre-calculated (stored in a storage device) for the cell v(i-1, j) to the directly left into the directly left mutation source operand 806E.

[0060] (Variation degree / route calculation means 612 / Variation degree / route calculation step S612) In the variation / path calculation step S612, the variation / path calculation means 612 calculates the variation F(i,j) of the data storage cell v(i,j) to be calculated. Specifically, for example, in a comparison between a character string X=x1x2...xi...ym and a character string Y=y1y2...yj...yn, the variation F(i,j) between characters xi and yj is defined as in the following formula 1.

number

[0061] Specifically, the calculation of Equation 1 is executed by an alignment processing kernel based on the mutation / path calculation means 612. The alignment processing kernel causes the decoder 804 to retrieve a single dedicated instruction (a mutation calculation instruction) for calculating the mutation F(i,j). As a result, the decoder 804 reads operands required by the mutation calculation instruction from the general-purpose register file 806 and / or the dedicated register file 808. Furthermore, the decoder 804 switches the data path so that the elements of these operands are sent to the mutation dedicated arithmetic logic unit 840.

[0062] (Mutation calculation command) In the variation-only arithmetic logic unit 840, in the score function selector 841B, if the element (character xi) of the upper array character source operand 806A and the element (character yj) of the left array character source operand 806B match, the value ("+2") of the match score source operand 808A is output, if the element (character xi) of the upper array character source operand 806A and the element (character yj) of the left array character source operand 806B do not match, the value ("-1") of the mismatch score source operand 808B is output, and if at least one of the element (character xi) of the upper array character source operand 806A and the element (character yj) of the left array character source operand 806B is missing, the value ("-2") of the gap score source operand 808C is output. This output corresponds to the calculation of the score function s(i,j) described above.

[0063] Furthermore, in the variability-dedicated arithmetic logic unit 840, the first adder / subtractor 840A adds the element (F(i,j-1)) of the directly above variability source operand 806D to the element ("-2") of the penalty source operand 808D, the second adder / subtractor 840B adds the element (F(i-1,j)) of the directly left variability source operand 806E to the element ("-2") of the penalty source operand 808D, and the third adder / subtractor 840C adds the element (F(i-1,j-1)) of the diagonally above left variability source operand 806C to the output element of the score function selector 841B. These outputs correspond to the calculations of m1, m2, and m3 in Equation 1.

[0064] Furthermore, in the mutation dedicated arithmetic logic unit 840, the mutation selector 841A selects the maximum or minimum value (here, the maximum value) of the output element of the first adder / subtractor 840A, the output element of the second adder / subtractor 840B, and the output element of the third adder / subtractor 840C. This output corresponds to the operation of the max function in Equation 1, that is, the result data of the mutation F(i,j). This output (mutation F(i,j)) is recorded in the output destination operand 806F.

[0065] After the mutation calculation command is completed, the mutation / path calculation means 612 calculates the return path flag B(i,j) of the data storage cell v(i,j) to be calculated. The return path flag B is path information that links the data storage cell v(i,j) to the upstream data storage cells corresponding to m1, m2, and m3 selected as the maximum values ​​in formula 1. For example, when m1 is selected as the maximum value, the data storage cell v(i,j) is linked to the cell v(i,j-1) directly above. For example, when m2 is selected as the maximum value, the data storage cell v(i,j) is linked to the cell v(i-1,j) directly to the left. For example, when m3 is selected as the maximum value, the data storage cell v(i,j) is linked to the cell v(i-1,j-1) diagonally above to the left. In other words, the return path flag B(i,j) is a combination of three types of information: a path directly above, a path directly to the left, and a path diagonally above to the left. For example, in this embodiment, the return path flag B(i,j) is defined as 1 when the maximum value is selected in the order of m1, m2, and m3, and as 0 when not selected. As a result, the return path flag B(i,j)=([1 or 0], [1 or 0], [1 or 0]).

[0066] (Step S614 for determining remaining filled cells) When the variation / path calculation step S612 is completed, the process proceeds to a filling cell determination step S614, where it is determined whether or not an uncalculated data storage cell v(i,j) remains according to the calculation order R. If so, the process returns to the filling cell selection step S610, where the filling cell selection means 610 selects the data storage cell v(i,j) to be the next calculation target. As a result, in the variation / path calculation step S612, the variation F(i,j) of the next data storage cell v(i,j) is output. On the other hand, if no uncalculated data storage cell v(i,j) remains in the filling cell determination step S614, the process proceeds to an unprocessed filling area determination step S616.

[0067] (Step S616 for determining unprocessed filled areas) In the unprocessed filling area determination step S616, it is determined whether or not an unprocessed sequence area Vn remains. If it remains, the process returns to the filling area selection step S606, where the filling area selection means 606 selects the sequence area Vn to be the next calculation target. Thereafter, the above-mentioned filling route setting step S608, filling cell selection step S610, mutation degree / path calculation step S612, and remaining filling cell determination step S614 are repeated. On the other hand, in the unprocessed filling area determination step S616, if no unprocessed sequence area Vn remains, filling of the mutation degree F in the alignment matrix V is completed, and the process proceeds to the backtrack process S620.

[0068] (Backtrack processing S620) In the backtrack process S620, the backtrack processing means 620 selects the data storage cell v with the maximum mutation degree as the starting cell vs, as shown in FIG. 10, and selects the data storage cell v(i,j) with the largest mutation degree F(i,j) from among all the data storage cells v(i,j) linked to the upstream side by the return path flag B(i,j). This makes it possible to trace back to the data storage cell (end point cell ve) where one of the element positions (i,j) is 0, for example. Here, information on the element position group (element position array) that is the path from the element position (is,js) of the starting point cell vs to the element position (ie,je) of the end point cell ve is defined as backtrack data BT. Once the backtrack data BT is generated, the process proceeds to the approximate string derivation process S622.

[0069] (Approximate character string derivation process S622) In the approximate character string derivation process S622, the approximate character string derivation means 622 derives an approximate character string by referring to the backtrack data BT from the end position (ie, je) toward the start position (is, js). In the reference path, a movement diagonally downward to the right means "the presence (matching or replacement) of both the matched character xi and the collation character yi at the destination position", a movement directly to the right means "loss of the collation character yi for the matched character xi at the destination position", and a movement directly downward means "insertion of the collation character yi for the matched character xi at the destination position". In addition, in the path meaning "the presence (matching or replacement) of both the matched character xi and the collation character yi at the destination position", the matched character xi and the collation character yi at the destination position may match or may not match. In the case of a mismatch, it means that the matched character xi has been "replaced" by the collation character yi.

[0070] For example, in the case of the backtrack data BT in FIG. X: (x1) (x2) (x3) - (x4) <x5><h2 style=";text-align:left;direction:ltr">(y6)(y7)<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr"> Y:(y1)(y2)(y3)<h2 style=";text-align:left;direction:ltr"> <y4>(y5) - (y6)(y7) The symbol "( )" indicates the presence of both, and if the matched character xi and the matching character yi are the same, it is a match, and if they are different, it is a substitution. The symbol "< >" indicates the insertion of a character, and the symbol "-" indicates the absence of a character. In other words, the approximate string is a data set that shows the correlation between the matched string X and the matching string Y.

[0071] As shown by the dotted line in Fig. 10, the same applies when the backtrack data BT branches midway, generating multiple backtrack data BT2, or when there are multiple data storage cells v (origin cells vs) with the maximum mutation degree, generating other backtrack data BT3. In this case, there are multiple approximate character strings corresponding to each backtrack data. After going through all the above steps, derivation of the approximate character string using the Needleman-Wunsch algorithm is completed.

[0072] <Example of alignment processing> Next, as a specific example, an alignment process between the matched string X "GCCTCGCT" and the matched string Y "GCCATTGA" will be described. In the alignment matrix creation step S602, the alignment matrix V in FIG. 11 is generated. In the alignment matrix V, "φ" in the table is a null character, and F(0,0)=0 is defined. Also, in formula 1, if at least one of the arguments (i,j) that determine the mutation degree F(i,j) is a negative value, it is outside the range of the calculation, so the calculation is omitted (output Null). The alignment matrix V is expanded on a storage device as a kind of lattice-like data structure and is made available for use by the processor.

[0073] In the constant setting step S604, the score for a matched character pair is set to "+2", the score for a mismatch is set to "-1", and the score for a gap is set to "-2", and the gap penalty is set to "-2". In the filling region selection step S606, the sequence region V1 for which the calculation is performed first is selected. In the filling route setting step S608, a route R1 is defined in the sequence region V1.

[0074] In the fill cell selection step S610, first, the data storage cell v(0,0) to be calculated is selected, but since its mutation degree F(0,0) is predefined as 0, subsequent calculations are omitted and the next data storage cell v(1,0) is selected.

[0075] In the mutation / path calculation step S61, m1, m2, and m3 in the max function of Equation 1 that calculates the mutation F(1,0) are as follows: m1=F(1,-1)-d=Null m2=F(0,0)-d=0-2=-2 m3=F(0,-1)+s(x1,y0)=Null As a result, the max function selects m2, and F(1,0) = -2. And the return path flag B(1,0) is as follows: B(1,0)=(0,1,0) (i.e. only "direct left")

[0076] When the variation / path calculation step S612 is completed, the process proceeds to the filling cell determination step S614, where it is determined according to the calculation order R1 whether or not an uncalculated data storage cell v(i,j) remains. Since there is an uncalculated data storage cell v(i,j), the process returns to the filling cell selection step S610, where the filling cell selection means 610 selects the data storage cell v(2,0) to be the next calculation target. Next, in the variation / path calculation step S612, F(2,0) and B(2,0) are calculated as follows: F(2,0)=F(1,0)-d=-4 B(2,0)=(0,1,0) (i.e. only "direct left")

[0077] After that, through filling cell determination step S614 and filling cell selection step S610, the data storage cell v(3,0) to be the next calculation target is selected, and in mutation / path calculation step S612, F(3,0) and B(3,0) are calculated as follows. F(3,0)=F(2,0)-d=-4 B(3,0))=(0,1,0) (i.e. only "direct left")

[0078] By repeating these steps n times, F(n,0) and B(n,0) are calculated in the data storage cell v(n,0) as follows: F(n,0)=-nd B(n,0)) = (0,1,0) (i.e. only "direct left")

[0079] As a result of the above, the mutation degree F and return path flag B of the array area V1 become as shown in Fig. 11. In the filling cell determination step S614, according to the calculation order R1, it is determined that there are no uncalculated data storage cells v(i,j) remaining, so the process proceeds to the unprocessed filling area determination step S616, where it is determined whether or not there is an unprocessed array area Vk remaining. Since there is an unprocessed array area Vk remaining, the process returns to the filling area selection step S606, where the filling area selection means 606 selects the array area V2 to be the next calculation target.

[0080] m1, m2, and m3 in the max function of formula 1 in the first data storage cell v(0,1) in array area V2 are as follows: m1=F(0,0)-d=0-2=-2 m2=F(-1,1)-d=Null m3=F(-1,0)+s(x0,y1)=Null As a result, the max function selects m1, and the mutation degree F(0,1) = -2. And the return path flag B(0,1) is as follows: B(1,0)=(1,0,0) (i.e. "directly above" only)

[0081] In the next data storage cell v(1,1) to be selected next, m1, m2, and m3 in the max function of formula 1 are as follows: m1=F(1,0)-d=-2-2=-4 m2=F(0,1)-d=-2-2=-4 m3 = F(0,0) + s(x1,y1) = 0 + 2 = 2 As a result, the max function selects m3, and the mutation degree F(1,1) = 2. And the return path flag B(1,1) is as follows: B(1,1)=(0,0,1) (i.e. only "upper left")

[0082] In the data storage cell v(2,1) to be selected next, m1, m2, and m3 in the max function of formula 1 are as follows: m1=F(2,0)-d=-4-2=-6 m2=F(1,1)-d=2-2=0 m3=F(1,0)+s(x2,y1)=-2-1=-3 As a result, the max function selects m2, and the mutation degree F(2,1) = 0. And the return path flag B(2,1) is as follows. B(2,1)=(0,1,0) (i.e. only "direct left")

[0083] In the data storage cell v(3,1) to be selected next, m1, m2, and m3 in the max function of formula 1 are as follows: m1=F(3,0)-d=-6-2=-8 m2=F(2,1)-d=0-2=-2 m3=F(2,0)+s(x3,y1)=-4-1=-5 As a result, the max function selects m2, and the mutation degree F(3,1) = -2. And the return path flag B(3,1) is as follows: B(3,1)=(0,1,0) (i.e. only "direct left")

[0084] Omitting some explanation of the subsequent calculations, m1, m2, and m3 in the max function of formula 1 in data storage cell v(6,1) are as follows: m1=F(6,0)-d=-12-2=-14 m2=F(5,1)-d=-6-2=-8 m3=F(5,0)+s(x6,y1)=-10+2=-8 As a result, the max function selects m2 or m3, and the mutation degree F(6,1) = -8. And the return path flag B(6,1) is as follows: B(6,1)=(0,1,1) (i.e. the combination of "direct left" and "diagonally up left") Like this return route flag B(6,1), the return route flag B may select multiple routes.

[0085] When the above repeated calculations are performed on array area V2, the result is as shown in Fig. 12. Similarly, when all array areas V1 to V9 are sequentially performed, the alignment matrix V in Fig. 13 is completed. In step S616 for determining an unprocessed filling area, since there are no unprocessed array areas remaining, the process proceeds to backtrack processing S620.

[0086] In the backtrack process S620, since the mutation degree F(6,7) of the data storage cell v(6,7) has the maximum value "7", this is selected as the starting cell vs. Therefore, from among the routes linked by the arrow indicating the return route flag B from the data storage cell v(6,7) to the data storage cell v(0,0), the route with the maximum mutation degree F is selected. By performing this backtrack, the backtrack data BT {(6,7) → (5,6) → (4,5) → (3,4) → (3,3) → (2,2) → (1,1) → (0,0)} colored in gray is selected. When the acquisition of the backtrack data BT is completed, the process proceeds to the approximate string derivation process S622.

[0087] In the approximate character string derivation process S622, the backtrack data BT is referenced from the end position (0,0) toward the start position (6,7) to derive an approximate character string. Here, (0,0)→(1,1)="G(match)", (1,1)→(2,2)="C(match)", (2,2)→(3,3)="C(match)", (3,3)→(3,4)="A(insertion)", (3,4)→(4,5)="T(match)", (4,5)→(5,6)="T(replacement)", (5,6)→(6,7)="T(match)".

[0088] This results in the following approximate string: X: "GCC - TCG" Y: "GCC T[T]G.” Here, the symbols "< >" indicate insertion between characters, the symbol "-" indicates a missing character, and the symbol "[ ]" indicates a substitution. In other words, in this example, the referenced string X is "GCCTCG", and "A" has been inserted between the "C" and "T" in the referenced string X, and the "C" in the referenced string "TCG" has been replaced with "T".

[0089] As described above, by identifying the element position in the aligned sequence where the degree of variation is the maximum value according to the Needleman-Wunsch algorithm, an approximate character string can be derived therefrom.

[0090] (Introduction of the first variant) In the core A shown in FIG. 18, the variation dedicated arithmetic logic unit 840 is provided with a score function selector 841B, and the score function s is simultaneously calculated in a variation calculation instruction that is a single instruction, but the present invention is not limited to this. For example, as in the core A1 shown in FIG. 19, the score function selector 841B can be arranged in the score function dedicated arithmetic logic unit 842 that is executed by an instruction independent of the variation dedicated arithmetic logic unit 840, and the calculation of the score function s can be executed. In this case, the score source operand 806S can be stored in the general-purpose register file 806, so that the output data of the score function dedicated arithmetic logic unit 842 (score function selector 841B) can be taken into the score source operand 806S. In the third adder / subtractor 840C of the variation dedicated arithmetic logic unit 840, an element of the score source operand 806S and an element of the upper left variation source operand 806C can be added.

[0091] 18 illustrates an example in which the score source operand 806S directly imports the output data of the score function dedicated arithmetic logic unit 842, but the present invention is not limited to this. In the alignment program, the score function dedicated arithmetic logic unit 842 may be used to generate a data group of a (m+1)×(n+1) matrix-shaped score matrix S (score table) based on the matched string X and the matched string Y, as shown in FIG. 14, for example, and the score values ​​may be calculated and stored in a storage device. In this case, it is preferable that the score source operand 806S imports the desired score value s(i,j) from the score matrix S stored in the storage device.

[0092] (Introduction of the second modified example) In the cores A and A1 shown in FIG. 18 and FIG. 19, the mutation selector 841A of the mutation dedicated arithmetic logic unit 840 selects the maximum or minimum value (here, the maximum value) of the output element of the first adder-subtractor 840A, the output element of the second adder-subtractor 840B, and the output element of the third adder-subtractor 840C. This is suitable for so-called global alignment processing such as the Needleman-Wunsch algorithm. On the other hand, the present invention is not limited to this and can be applied to so-called local alignment processing. In this case, for example, as in the core A2 of the second modified example of FIG. 20 which is a further modified version of the first modified example of FIG. 19, the dedicated register file 808 may further store a limited constant operand 808E, and the mutation selector 841A may select the maximum or minimum value (here, the maximum value) of the output element of the first adder-subtractor 840A, the output element of the second adder-subtractor 840B, the output element of the third adder-subtractor 840C, and the element of the limited constant operand 808E. The limiting constant operand 808E holds data (for example, "0") for limiting the mutation degree F(i,j) value selected by the mutation degree selector 841A so that it is not smaller than a predetermined value.

[0093] For example, in local alignment processing using the Smith-Waterman algorithm, in comparing a string X=x1x2...xi...ym with a string Y=y1y2...yj...yn, the degree of variation F(i,j) between characters xi and yj is defined as shown in the following equation 2.

number

[0094] (Introduction of the third modified example) In the cores A, A1, and A2 shown in Figures 18 to 20, an example is shown in which a dedicated register file 808 stores a match score source operand 808A, a mismatch score source operand 808B, and a gap score source operand 808C, and the values ​​of these elements are selectively output by a score function selector 841B, but the present invention is not limited to this.

[0095] 21, the match score, mismatch score, and gap score can be stored as arguments in the variation calculation instruction itself processed by the decoder 804. In this case, a general-purpose or dedicated comparator 807 compares in advance whether an element (character xi) of the upper array character source operand 806A matches or mismatches an element (character yj) of the left array character source operand 806B, and records the match or mismatch determination result in a flag register 809. In the score function selector 841B, by referring to the judgment result recorded in the flag register 809, if an element (character xi) of the upper array character source operand 806A matches an element (character yj) of the left array character source operand 806B, the variation calculation instruction is masked by the mask register to extract and output the argument: match score ("+2"); if an element (character xi) of the upper array character source operand 806A does not match an element (character yj) of the left array character source operand 806B, the variation calculation instruction is masked by the mask register to extract and output the argument: mismatch score ("-1"). This makes it possible to reduce the number of operands. In other words, a dedicated instruction register such as the decoder 804 can also serve as the dedicated register file 808 (dedicated operand) by holding the argument. Regarding the defect judgment as to whether or not at least one of the elements (character xi) of the upper array character source operand 806A and the elements (character yj) of the left array character source operand 806B is defective, the defect judgment is performed by reloading the above comparator 807, and the defect judgment result is recorded in the flag register 809, so that the score function selector 841B can mask the variation calculation command by the mask register and extract and output the argument: gap score ("-2"). Of course, by providing two or more comparators 807 and flag registers 809, a configuration in which match / mismatch judgment and defect judgment are performed simultaneously may be used.

[0096] (Fourth modified example: Introduction of a generalized example)

[0097] 18 to 21 are provided with a general-purpose register file 806 and a dedicated register file 808 to illustrate examples of customizing the alignment process, but the present invention is not limited to this, and all operand groups may be stored in the general-purpose register file 806. A core A3 according to a third modified example in which the core A shown in FIG. 18 is generalized is shown in FIG. 22.

[0098] The core A3 includes a general-purpose register file 806-H3, a dedicated register file 808-H3, and a general-purpose arithmetic logic unit 840-H3. The general-purpose register file 806-H3 stores a ninth source operand 806A-H3, a tenth source operand 806B-H3, a fifth source operand 806C-H3, a first source operand 806D-H3, a third source operand 806E-H3, and an output destination operand 806F-H3.

[0099] The dedicated register file 808-H3 stores a sixth source operand 808A-H3, a seventh source operand 808B-H3, an eighth source operand 808C-H3, a second source operand 808D-H3a, and a fourth source operand 808D-H3b. Note that the second source operand 808D-H3a and the fourth source operand 808D-H3b are generalized versions of the penalty source operand 808D in Fig. 18, which are divided into two independent operands, and allow different elements to be added to the first adder-subtractor 840A-H3 and the second adder-subtractor 840B-H3.

[0100] The general-purpose arithmetic logic unit 840-H3 includes a second selector 841B-H3, a first adder / subtractor 840A-H3, a second adder / subtractor 840B-H3, a third adder / subtractor 840C-H3, and a first selector 841A-H3. The second selector 841B-H3 is a multiplexer that references each element of the ninth source operand 806A-H3, the tenth source operand 806B-H3, the sixth source operand 808A-H3, the seventh source operand 808B-H3, and the eighth source operand 808C-H3 and outputs a score based on the score function s. The third adder / subtractor 840C-H3 adds an element of the fifth source operand 806C-H3 and an output element of the second selector 841B-H3. The first adder / subtractor 840A-H3 adds the elements of the first source operand 806D-H3 and the elements of the second source operand 808D-H3a. The second adder / subtractor 840B-H3 adds the elements of the third source operand 806E-H3 and the elements of the fourth source operand 808D-H3b. The first selector 841A-H3 is a multiplexer that selects the maximum or minimum value (here, the maximum value) of the output elements of the first adder / subtractor 840A-H3, the output elements of the second adder / subtractor 840B-H3, and the output elements of the third adder / subtractor 840C-H3. Needless to say, the first selector 841A-H3 can be realized in a general-purpose manner, for example, by a combination of a first comparator that compares two of these three elements (for example, the output element of the first adder / subtractor 840A-H3 and the output element of the second adder / subtractor 840B-H3) and a second comparator that compares the output of the first comparator with the remaining one (for example, the output element of the third adder / subtractor 840C-H3).

[0101] The reference numerals given to the generalized parts and materials in the core A3 in Fig. 22 are the same as those given to the dedicated parts and materials of the core A shown in Fig. 18 with "-H3" added. Due to this reference numeral correspondence, a detailed description of the functions of the core A3 in Fig. 22 will be omitted.

[0102] As described above, the core A3 in FIG. 21 includes a first source operand 806D-H3, a second source operand 808D-H3a, a third source operand 806E-H3, a fourth source operand 808D-H3b, a fifth source operand 806C-H3, a sixth source operand 808A-H3, a first adder / subtractor 840A-H3 that calculates a first intermediate sum of the elements of the first source operand 806D-H3 and the elements of the second source operand 808D-H3a, and and the elements of the fourth source operand 808D-H3b; a third adder / subtractor 840C-H3 for calculating a third intermediate sum of sixth causing data (here, the output elements of the second selector 841B-H3) obtained based on the elements of the fifth source operand 806C-H3 and the elements of the sixth source operand 808A-H3; and a first selector 841A-H3 for selecting a maximum value and / or a minimum value from at least the first intermediate sum, the second intermediate sum, and the third intermediate sum.

[0103] The function executed by a single instruction in this core A3 can be generalized as follows:

number

[0104] The core A3 in Fig. 22 can be suitably used for alignment processing similar to that of the core A in Fig. 18, but can also be used for other general-purpose purposes. Note that, although an example is shown here in which the register file is divided into a general-purpose register file 806-H3 and a dedicated register file 808-H3, versatility may be further enhanced by storing all operands in the general-purpose register file 806-H3.

[0105] (Fifth modified example: Introduction of a generalized example) 23 shows a core A4 according to a fifth modified example, which is a generalized version of the core A1 according to the first modified example shown in FIG. 19. The core A4 includes a general-purpose register file 806-H4, a dedicated register file 808-H4, a first general-purpose arithmetic and logic unit 840-H4, and a second general-purpose arithmetic and logic unit 842-H4. The general-purpose register file 806-H4 stores a tenth source operand 806A-H4, an eleventh source operand 806B-H4, a sixth source operand 806S-H4, a fifth source operand 806C-H4, a first source operand 806D-H4, a third source operand 806E-H4, and an output destination operand 806F-H4.

[0106] The dedicated register file 808-H4 stores a seventh source operand 808A-H4, an eighth source operand 808B-H4, a ninth source operand 808C-H4, a second source operand 808D-H4a, and a fourth source operand 808D-H4b. Note that the second source operand 808D-H4a and the fourth source operand 808D-H4b are generalized versions of the penalty source operand 808D in Fig. 19, which are divided into two independent operands, and allow different elements to be added to the first adder-subtractor 840A-H4 and the second adder-subtractor 840B-H4.

[0107] The second general-purpose arithmetic logic unit 842-H4 includes a second selector 841B-H4. The second selector 841B-H4 is a multiplexer that references each element of the tenth source operand 806A-H4, the eleventh source operand 806B-H4, the seventh source operand 808A-H4, the eighth source operand 808B-H4, and the ninth source operand 808C-H4 and outputs a score based on the score function s. The output data of the second selector 841B-H4 can be input to the sixth source operand 806S-H4.

[0108] The first general-purpose arithmetic logic unit 840-H4 includes a first adder / subtractor 840A-H4, a second adder / subtractor 840B-H4, a third adder / subtractor 840C-H4, and a first selector 841A-H4. The third adder / subtractor 840C-H4 adds elements of the fifth source operand 806C-H4 and elements of the sixth source operand 806S-H4. The first adder / subtractor 840A-H4 adds elements of the first source operand 806D-H4 and elements of the second source operand 808D-H4a. The second adder / subtractor 840B-H4 adds elements of the third source operand 806E-H4 and elements of the fourth source operand 808D-H4b. The first selector 841A-H4 is a multiplexer that selects the maximum or minimum value (here, the maximum value) of the output elements of the first adder / subtractor 840A-H4, the output elements of the second adder / subtractor 840B-H4, and the output elements of the third adder / subtractor 840C-H4.

[0109] The reference numerals given to the generalized parts and materials in the core A4 in Fig. 23 are the same as those given to the dedicated parts and materials in the core A1 in Fig. 19 with "-H4" added. Due to this reference numeral correspondence, a detailed description of the functions of the core A4 in Fig. 23 will be omitted.

[0110] As described above, the core A4 in FIG. 23 includes a first source operand 806D-H4, a second source operand 808D-H4a, a third source operand 806E-H4, a fourth source operand 808D-H4b, a fifth source operand 806C-H4, a sixth source operand 806S-H4, a first adder / subtractor 840A-H4 that calculates a first intermediate sum of the elements of the first source operand 806D-H4 and the elements of the second source operand 808D-H4a, and a second adder / subtractor 840A-H4 that calculates a first intermediate sum of the elements of the third source operand 806E-H4 and the fourth source operand 808D-H4b. The input / output device 840A-H4 includes a second adder / subtractor 840B-H4 for calculating a second intermediate sum of the elements of the source operand 808D-H4b, a third adder / subtractor 840C-H4 for calculating a third intermediate sum of sixth cause data (here, the elements of the sixth source operand 806S-H4 themselves) obtained based on the elements of the fifth source operand 806C-H4 and the elements of the sixth source operand 806S-H4, and a first selector 841A-H4 for selecting a maximum value and / or a minimum value from at least the first intermediate sum, the second intermediate sum, and the third intermediate sum.

[0111] The function executed by a single instruction in this core A4 can be generalized to the following equation 4.

number

[0112] The core A4 in Fig. 23 can be suitably used for alignment processing similar to that of the core A1 in Fig. 19, but can also be used for other general-purpose purposes. Note that, although an example is shown here in which the register file is divided into a general-purpose register file 806-H4 and a dedicated register file 808-H4, versatility may be further enhanced by storing all operands in the general-purpose register file 806-H4.

[0113] (Sixth modified example: Introduction of a generalized example) FIG. 24 shows a core A5 according to a sixth modified example, which is a generalized version of the core A2 according to the second modified example shown in FIG.

[0114] The core A5 includes a general-purpose register file 806-H5, a dedicated register file 808-H5, a first general-purpose arithmetic logic unit 840-H5, and a second general-purpose arithmetic logic unit 842-H5. The general-purpose register file 806-H5 stores a twelfth source operand 806A-H5, a thirteenth source operand 806B-H5, a sixth source operand 806S-H5, a fifth source operand 806C-H5, a first source operand 806D-H5, a third source operand 806E-H5, and an output destination operand 806F-H5.

[0115] The dedicated register file 808-H5 stores a ninth source operand 808A-H5, a tenth source operand 808B-H5, an eleventh source operand 808C-H5, a second source operand 808D-H5a, a fourth source operand 808D-H5b, and an eighth source operand 808E-H5. Note that the second source operand 808D-H5a and the fourth source operand 808D-H5b are generalized versions of the penalty source operand 808D in Fig. 20, which are divided into two independent operands, and allow different elements to be added to the first adder-subtractor 840A-H5 and the second adder-subtractor 840B-H5.

[0116] The second general purpose arithmetic logic unit 842-H5 includes a second selector 841B-H5. The second selector 841B-H5 is a multiplexer that references each element of the twelfth source operand 806A-H5, the thirteenth source operand 806B-H5, the ninth source operand 808A-H5, the tenth source operand 808B-H5, and the eleventh source operand 808C-H5 and outputs a score based on the score function s. The output data of the second selector 841B-H5 can be input to the sixth source operand 806S-H5.

[0117] The first general purpose arithmetic logic unit 840-H5 includes a first adder / subtractor 840A-H5, a second adder / subtractor 840B-H5, a third adder / subtractor 840C-H5, and a first selector 841A-H5. The third adder / subtractor 840C-H5 adds elements of the fifth source operand 806C-H5 and elements of the sixth source operand 806S-H5. The first adder / subtractor 840A-H5 adds elements of the first source operand 806D-H5 and elements of the second source operand 808D-H5a. The second adder / subtractor 840B-H5 adds elements of the third source operand 806E-H5 and elements of the fourth source operand 808D-H5b. The first selector 841A-H5 is a multiplexer that selects the maximum or minimum value (here the maximum value) of the output elements of the first adder / subtractor 840A-H5, the output elements of the second adder / subtractor 840B-H5, the output elements of the third adder / subtractor 840C-H5, and the elements of the eighth source operand 808E-H5.

[0118] The reference numerals given to the generalized parts and materials in the core A5 in Fig. 24 are the same as those given to the dedicated parts and materials in the core A2 in Fig. 20 with "-H5" added. Due to this reference numeral correspondence, a detailed description of the functions of the core A5 in Fig. 24 will be omitted.

[0119] As described above, the core A5 in FIG. 24 includes a first source operand 806D-H5, a second source operand 808D-H5a, a third source operand 806E-H5, a fourth source operand 808D-H5b, a fifth source operand 806C-H5, a sixth source operand 806S-H5, an eighth source operand 808E-H5, a first adder / subtractor 840A-H5 that calculates a first intermediate sum of the elements of the first source operand 806D-H5 and the elements of the second source operand 808D-H5a, and a fourth source operand 808E-H5 that calculates a second intermediate sum of the elements of the third source operand 806E-H5 and the elements of the fourth source operand 808D-H5b. the second adder / subtractor 840B-H5 for calculating a second intermediate sum of the elements of the fifth source operand 806C-H5 and the elements of the sixth source operand 806S-H5; and a first selector 841A-H5 for selecting the maximum and / or minimum values ​​from among the elements of the eighth source operand 808E-H5 of at least the first intermediate sum, the second intermediate sum, and the third intermediate sum.

[0120] The function executed by a single instruction in this core A5 can be generalized to the following equation 5.

number

[0121] The core A5 in Fig. 24 can be suitably used for alignment processing similar to that of the core A2 in Fig. 20, but can also be used for other general-purpose purposes. Note that, although an example is shown here in which the register file is divided into a general-purpose register file 806-H5 and a dedicated register file 808-H5, versatility may be further enhanced by storing all operands in the general-purpose register file 806-H5.

[0122] (Seventh modified example: Introduction of a generalized example) FIG. 25 shows a core A6 according to a seventh modification, which is a further simplification of the general-purpose core A3 shown in FIG. 22. This core A6 omits the sixth source operand 808A-H3, the seventh source operand 808B-H3, and the eighth source operand 808C-H3 stored in the general-purpose register file 806-H3 of the core A3. Instead, the core A6 stores the values ​​of these elements (sixth source r1, seventh source r2, and eighth source r3) in the argument side of the general-purpose arithmetic instruction processed by the decoder 804-H6. The core A6 may further include a comparator 807-H6 and a flag register 809-H6. The comparator 807-H6 performs a comparison operation to determine whether the ninth source operand 806A-H6 and the tenth source operand 806B-H6 are a match, a mismatch, or a missing item, and records the comparison result in the flag register 809-H6. The second selector 841B-H6 is a multiplexer that uses a mask register to extract and output one of the sixth source r1, the seventh source r2, and the eighth source r3, which are arguments, based on the result recorded in the flag register 809-H6. In other words, a dedicated instruction register such as the decoder 804 can hold the argument and serve as part of the operands stored in the dedicated register file 808-H6 and the general-purpose register file 806-H6. In the core A6, the symbols of devices similar to the dedicated parts and components of the core A3 in FIG. 22 are replaced with the symbols of the core A3 by "-H6" instead of "-H3", and detailed descriptions of the functions of the core A6 are omitted.

[0123] The function executed by a single instruction in this core A6 can be generalized to the following equation 6.

number

[0124] In addition, in the cores A4, A5, A6, and A7, which are generalized examples, the case has been exemplified in which both element b of the second source operand 808D-H3a and element d of the fourth source operand 808D-H3b are used, but if necessary, either element b or element d may be omitted, which is suitable for the Smith-Waterman-Gotoh algorithm, etc.

[0125] In the alignment processing computer system 204 of this embodiment, since the processor module 104 includes cores A to D, the mutation degree F(i,j) of the current position of the alignment matrix V can be calculated for the cores A to D with a single command. This reduces the number of accesses to the memory module (main memory) 102 and increases the hit rate of the L1 to L3 cache memories, thereby realizing extremely high-speed mutation calculation. As a result, an approximate string can be derived in a short time for a string pair consisting of a matched string and a matching string. Furthermore, in the alignment processing computer system 204, the constant setting means 604 stores constant data such as gap penalty in the dedicated register file 808, so that the data is shared in multiple mutation calculations in the mutation / path calculation means 612. This also reduces the number of accesses to the memory module (main memory) 102, thereby increasing the calculation speed.

[0126] Furthermore, in the alignment processing computer system 204, the filling area selection means 606 extracts array areas V1V2...Vk...Vp that are part of the entire alignment matrix V, and the mutation / path calculation means 612 calculates the mutation within that range. This further increases the hit rate of the L1 to L3 cache memories, thereby increasing the calculation speed.

[0127] The above-described embodiments are merely examples for explaining the present invention, and are not intended to limit the present invention to these embodiments. The present invention can be embodied in various forms without departing from the spirit of the present invention.

[0128] For example, in the above embodiment, the core A performs alignment processing of a string pair consisting of a matched string and a matching string, but multiple cores A to D may be used in parallel to perform alignment processing of a common string pair. In this case, the alignment processing kernel may adopt, for example, a single instruction, multiple data (Single Instruction, Multiple Data) method to manage the calculation order of the cores A to D, and may also adopt a pipeline processing method. Furthermore, the alignment processing kernel may adopt a single instruction, multiple threads (Single Instruction, Multiple Threads) method. Also, although four cores A to D are illustrated here, the number of cores is not particularly limited.

[0129] For example, in the methods disclosed herein, steps, operations, or functions may be performed in parallel or in a different order, provided that the results are consistent. The steps, operations, and functions described are provided merely as examples, and some of the steps, operations, and functions may be omitted or combined into one, or other steps, operations, or functions may be added, without departing from the spirit of the invention.

[0130] The above-mentioned embodiments are examples for explaining the present invention, and the present invention is not limited to these embodiments. The present invention can be implemented in various forms without departing from the gist of the present invention. For example, in the present embodiment, an example is given of an alignment process for a reference character string that is genetic information, but the present invention is not limited to this, and can be applied to an alignment process for a character string pair other than genetic information.

[0131] Furthermore, in the above embodiment, the hardware configuration of the computing device is a general-purpose structure, but the present invention is not limited to this. For example, individually customized hardware such as an FPGA (Field Programmable Gate Array) may be used.

[0132] In addition, although various embodiments are disclosed in this specification, specific features (technical matters) in one embodiment can be added to or replaced with specific features in other embodiments, with appropriate modifications, and such forms are also included in the spirit of the present invention. [Explanation of symbols]

[0133] A,B,C,D Core 1. Computer Systems 10 Top Computers 20 Lower level computers 30 Databases 100 computing devices 102 Memory Module 104 Processor Module 106 Chipset 108 Internal Storage Device 112 Output Interface 114 Input / Output Interface 116 Communication Interface 118 External Storage Devices 200 Computer system for approximate string matching 201 Indexing computer system 202 Mapping Computer System 203 Computer system for generating string pairs 204 Computer system for alignment processing 602 Alignment matrix creation method 604 Constant setting means 606 Filling area selection means 608 Filling route setting means 610 Filling cell selection means 612 Variation and Route Calculation Method 620 Backtrack Processing Means 622 Approximate string derivation means 800 Program Counter 804 Decoder 806 General Purpose Register File 806A Upper array character source operand 806B Left aligned character source operand 806C Upper Variation Source Operand 806D Directly above mutation source operand 806E True left variance source operand 806F Output destination operand 806S Score Source Operand 808 Dedicated Register File 808A Match Score Source Operand 808B Mismatch score source operand 808C Gap Score Source Operand 808D Penalty Source Operand 808E Limited constant operand 830 Execution Unit 832 Adder / Subtractor 834 Multiplier 836 Floating Point Unit 840 Mutation-specific arithmetic logic unit 840A First adder / subtractor 840B Second adder / subtractor 840C Third Adder / Subtractor 841A Mutation Selector 841B Score Function Selector 841B Score Function Dedicated Arithmetic Logic Unit 842 Score Function Dedicated Arithmetic Logic Unit

Claims

1. A first source operand; A second source operand; and a third source operand; and a fourth source operand; and a fifth source operand; and A sixth source operand; and a first adder / subtractor for computing a first intermediate sum of elements of the first source operand and elements of the second source operand; a second adder / subtractor for computing a second intermediate sum of elements of the third source operand and elements of the fourth source operand; a third adder / subtractor that calculates a third intermediate sum of sixth cause data obtained based on elements of the fifth source operand and elements of the sixth source operand; a selector for selecting a maximum value and / or a minimum value from at least the first intermediate sum, the second intermediate sum, and the third intermediate sum; A processor comprising:

2. the first source operand, the third source operand, and the fifth source operand are stored in a general purpose register file; the second source operand, the fourth source operand, and the sixth source operand are stored in a dedicated register file. The processor of claim 1 .

3. a seventh source operand; and a second selection unit, the sixth cause data is data selected by the second selector from at least an element of the sixth source operand and a seventh source operand, The processor of claim 1 .

4. an eighth source operand; the selector selects maximum and / or minimum values ​​from among at least the first intermediate sum, the second intermediate sum, the third intermediate sum, and elements of the eighth source operand. The processor of claim 1 .

5. An instruction decoder for decoding an instruction, a single instruction decoded by the instruction decoder executes the calculation of the first intermediate sum by the first adder-subtractor, the calculation of the second intermediate sum by the second adder-subtractor, the calculation of the third intermediate sum by the third adder-subtractor, and the selection of the maximum value and / or the minimum value by the selector; The processor according to any one of claims 1 to 5.

6. an upper left deviation source operand, the source operand having an element that is an upper left deviation from a current position of an alignment matrix used in an alignment process of the first character string and the second character string; a true left variance source operand, the element of which is a true left variance relative to the current position of the alignment matrix; a penalty source operand whose elements are the linear gap penalty values ​​of the alignment process; an above-alignment source operand having an element representing a degree of alignment based on a current position of the alignment matrix; a first adder / subtractor for computing a first intermediate sum of elements of the overhead variance source operand and elements of the penalty source operand; a second adder / subtractor for computing a second intermediate sum of the elements of the true left variance source operand and the elements of the penalty source operand; a third adder / subtractor that calculates a third intermediate sum of the elements of the diagonal upward variation source operand and a score function value based on a match / mismatch between the elements of the first character string and the elements of the second character string corresponding to the current position; a mutation selector that selects a maximum value and / or a minimum value from at least the first intermediate sum, the second intermediate sum, and the third intermediate sum; A processor comprising:

7. a match score source operand; a mismatch score source operand; a first string character source operand whose element is the character in the first string that corresponds to the current position; a second string character source operand having an element that is the character in the second string that corresponds to the current position; a score function selector that selects an element of the match score source operand when an element of the first string character source operand matches an element of the second string character source operand, and selects an element of the mismatch score source operand when an element of the first string character source operand does not match an element of the second string character source operand, and outputs the element as the score function value; The processor of claim 6, comprising:

8. a score function source operand; The score function value is stored in the score source operand. The processor of claim 6.

9. the left diagonal-upper variance source operand, the directly above variance source operand, and the directly left variance source operand are stored in a general-purpose register file; the gap source operand is stored in a dedicated register file; The processor of claim 6.

10. A limit constant source operand having a limit constant as an element, the variability selector selects maximum and / or minimum values ​​from among at least the first intermediate sum, the second intermediate sum, the third intermediate sum, and elements of the limited constant source operand; The processor of claim 6.

11. An instruction decoder for decoding an instruction, a first intermediate sum calculation by the first adder-subtractor, a second intermediate sum calculation by the second adder-subtractor, a third intermediate sum calculation by the third adder-subtractor, and selection of the maximum value and / or the minimum value by the mutation selector, all of which are executed in response to a single mutation calculation instruction by the instruction decoder; A processor according to any one of claims 6 to 10.

12. A computer device for alignment processing, comprising a storage device in which a first character string and a second character string are stored, and a processor, and configured to perform alignment processing using an alignment matrix of the first character string and the second character string, The processor is according to any one of claims 1 to 10, The processor calculates a degree of variation of a current position of the alignment matrix based on an alignment program stored in the storage device. Computer system for alignment processing.

Images