Current detection amplifier and semiconductor device for current detection

Abstract

To reduce a capacity of a noise removal filter.SOLUTION: A current detection amplifier amplifies a detection signal of a current flowing through a current detection resistor and then outputs it to an AD converter, and includes: a first noise removal filter that is connected to one end of the current detection resistor and has a first capacitance and a first resistance; and a first capacitance connection switch that is provided between the first capacitance of the first noise removal filter and a first sampling capacitance of the AD converter.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a current detection amplifier and a current detection semiconductor device. [Background technology]

[0002] Conventionally, when detecting a current using a current detection resistor, it is required to reduce the resistance of the current detection resistor in order to suppress the power loss caused by the current detection resistor. However, when the resistance of the current detection resistor is reduced, the detection signal becomes smaller and the S / N ratio deteriorates, so noise reduction is required. Methods for reducing noise include, for example, a method of chopping to suppress 1 / f noise, and a method of installing a noise reduction filter.

[0003] For example, Patent Document 1 listed below discloses a technology for a ΔΣ type AD converter that includes a detection resistor and a ΔΣ modulator that converts an analog signal detected by the detection resistor into a digital signal, in which an anti-aliasing filter is provided between the detection resistor and the ΔΣ modulator to remove high-frequency components of the signal input to the ΔΣ modulator. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2009-260605 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the technology of Patent Document 1, charge redistribution occurs from the capacitance of the anti-aliasing filter to the ΔΣ modulator during sampling to the ΔΣ modulator, so the capacitance of the anti-aliasing filter needs to be increased.

[0006] Furthermore, in the technology of Patent Document 1, if the signal input to the ΔΣ modulator is configured to be chopped (polarity inverted) by a current detection amplifier, chopping noise occurs at the time of polarity inversion. In order to suppress this chopping noise, the capacitance of the anti-aliasing filter needs to be increased, and it was not possible to implement the capacitance of the anti-aliasing filter in the same semiconductor integrated circuit as the current detection amplifier. [Means for solving the problem]

[0007] A current detection amplifier according to one embodiment amplifies a detection signal of a current flowing through a current detection resistor and then outputs the amplified signal to an AD converter. The current detection amplifier includes a first noise removal filter connected to one end of the current detection resistor and including a first capacitance and a first resistance, and a first capacitance connection switch provided between the first capacitance of the first noise removal filter and a first sampling capacitance of the AD converter. Effect of the Invention

[0008] According to one embodiment of a current detection amplifier, when sampling to an AD converter, the first capacitance connection switch is turned off to disconnect the first capacitance of the first noise removal filter from the AD converter, thereby preventing charge redistribution from the first capacitance and allowing the first capacitance to be reduced in size.

[0009] Furthermore, according to a current detection amplifier of one embodiment, when a signal input to an AD converter is configured to be chopped (polarity inverted) by the current detection amplifier, the first capacitance-connecting switch and the second capacitance-connecting switch are turned off during chopping to disconnect the first capacitance and the second capacitance from the AD converter, thereby preventing noise generated during polarity inversion from being superimposed on the first capacitance and the second capacitance, and thereby enabling the first capacitance and the second capacitance to be reduced in capacity. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram showing a circuit configuration of a current detection device according to an embodiment; [Diagram 2] A timing chart showing timings of each part in a current detection device according to an embodiment. [Diagram 3] FIG. 1 is a diagram showing a modification of the circuit configuration of a current detection device according to an embodiment; [Figure 4] A timing chart showing an example of an output when the capacitance of an anti-aliasing filter is connected at a constant cycle during startup of a current detection amplifier according to an embodiment. [Diagram 5] FIG. 1 is a timing diagram illustrating an example of an output when the capacitance of an anti-aliasing filter is kept connected during startup of a current sense amplifier according to an embodiment; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, an embodiment will be described with reference to the drawings.

[0012] (Circuit configuration of current detection device 100) Fig. 1 is a diagram showing a circuit configuration of a current detection device 100 according to an embodiment. The current detection device 100 shown in Fig. 1 detects a current flowing through a wiring L1 to be detected, amplifies and AD-converts the detection signal of the current, and then outputs the AD-converted digital signal. The current detection device 100 can be used, for example, in a battery remaining gauge. However, the use of the current detection device 100 is not limited to this, and the device can be applied to any low-noise use that can detect low voltages.

[0013] As shown in FIG. 1, the current detection device 100 includes a current detection resistor R1, a current detection amplifier 110, and a ΔΣ AD converter 120.

[0014] The current detection resistor R1 is provided on the wiring L1 that is the target of current detection. The potential difference across the current detection resistor R1 changes in response to the current flowing through the current detection resistor R1.

[0015] The current detection amplifier 110 is connected to both ends of the current detection resistor R1, and amplifies a detection signal of the potential difference across the current detection resistor R1.

[0016] The current sense amplifier 110 includes a resistor R21, a resistor R22, a resistor R23, and a resistor R24.

[0017] One end of the resistor R21 is connected to one end of the current detection resistor R1. The resistor R22 is connected to the other end of the current detection resistor R21. That is, the resistors R21 and R22 are connected in series with each other.

[0018] One end of the resistor R23 is connected to the other end of the current detection resistor R1. The resistor R24 ​​is connected to the other end of the current detection resistor R23. That is, the resistors R23 and R24 are connected in series with each other.

[0019] The gain of the current detection amplifier 110 is R22 / R21=R24 / R23. That is, the resistors R21, R22, R23, and R24 are examples of “gain determining resistors” that determine the gain of the current detection amplifier 110.

[0020] The current detection amplifier 110 includes a differential operational amplifier 111. The differential operational amplifier 111 amplifies the difference voltage between the negative input terminal and the positive input terminal, and outputs the amplified voltage from the negative output terminal and the positive output terminal.

[0021] The negative input terminal of the differential operational amplifier 111 is connected between resistors R21 and R22 via the chopping switch SW11. Also, the negative input terminal of the differential operational amplifier 111 is connected between resistors R23 and R24 via the chopping switch SW21.

[0022] The positive input terminal of the differential operational amplifier 111 is connected between resistors R21 and R22 via a chopping switch SW22. The positive input terminal of the differential operational amplifier 111 is also connected between resistors R23 and R24 via a chopping switch SW12.

[0023] The + output terminal of the differential operational amplifier 111 is connected to a first input terminal Vin+ of the ΔΣ AD converter 120 via the chopping switch SW13. In addition, the + output terminal of the differential operational amplifier 111 is connected to a second input terminal Vin- of the ΔΣ AD converter 120 via the chopping switch SW23.

[0024] The negative output terminal of the differential operational amplifier 111 is connected to a first input terminal Vin+ of the ΔΣ AD converter 120 via a chopping switch SW24. In addition, the negative output terminal of the differential operational amplifier 111 is connected to a second input terminal Vin− of the ΔΣ AD converter 120 via a chopping switch SW14.

[0025] This allows the current detection amplifier 110 to chop (that is, invert the polarity of) the signal Vamp input from the differential operational amplifier 111 to the ΔΣ AD converter 120 by switching the chopping switches SW11 to SW14 and SW21 to SW24.

[0026] Specifically, the current detection amplifier 110 can input a positive polarity signal Vamp output from the differential operational amplifier 111 to a first input terminal Vin+ of the ΔΣAD converter 120, and input a negative polarity signal Vamp output from the differential operational amplifier 111 to a second input terminal Vin- of the ΔΣAD converter 120, by simultaneously switching on the chopping switches SW11 to SW14 and simultaneously switching off the chopping switches SW21 to SW24.

[0027] Conversely, by simultaneously switching off the chopping switches SW11 to SW14 and simultaneously switching on the chopping switches SW21 to SW24, the current detection amplifier 110 can input the negative polarity signal Vamp output from the differential operational amplifier 111 to the first input terminal Vin+ of the ΔΣAD converter 120, and input the positive polarity signal Vamp output from the differential operational amplifier 111 to the second input terminal Vin- of the ΔΣAD converter 120.

[0028] The current detection amplifier 110 can suppress 1 / f noise in the signal Vamp by chopping the signal Vamp input to the ΔΣAD converter 120. The chopping switches SW11-SW14 and SW21-SW24 are an example of a “first chopping unit” that chops the signal Vamp input to the ΔΣAD converter 120.

[0029] Moreover, the current detection amplifier 110 includes a first anti-aliasing filter 112, a second anti-aliasing filter 113, a first capacitance-connecting switch SW1, and a second capacitance-connecting switch SW2.

[0030] The first anti-aliasing filter 112 includes the above-mentioned resistor R22 (one example of the "first resistor") and a first capacitance C1. The first capacitance C1 is connected in parallel with the resistor R22. The first capacitance C1 is also connected to the first input terminal Vin+ of the ΔΣAD converter 120. The first anti-aliasing filter 112 is a noise removal filter (i.e., a low-pass filter) that removes high-frequency components from the detection signal Vout input to the first input terminal Vin+ of the ΔΣAD converter 120 when sampling is performed on the ΔΣAD converter 120.

[0031] The second anti-aliasing filter 113 is configured to include the above-mentioned resistor R24 ​​(one example of the "second resistor") and a second capacitance C2. The second capacitance C2 is connected in parallel with the resistor R24. The second capacitance C2 is also connected to the second input terminal Vin- of the ΔΣAD converter 120. The second anti-aliasing filter 113 is a noise removal filter (i.e., a low-pass filter) that removes high-frequency components from the detection signal Vout (i.e., the detection signal Vout having a polarity different from that of the detection signal Vout input to the first input terminal Vin+) input to the second input terminal Vin- of the ΔΣAD converter 120 when sampling is performed on the ΔΣAD converter 120.

[0032] The first capacitance connection switch SW1 is provided between the first capacitance C1 of the first anti-aliasing filter 112 and the first input terminal Vin+ of the ΔΣAD converter 120. The first capacitance connection switch SW1 can switch the first capacitance C1 of the first anti-aliasing filter 112 between a state in which it is connected to the first input terminal Vin+ of the ΔΣAD converter 120 and a state in which it is disconnected from the first input terminal Vin+ of the ΔΣAD converter 120.

[0033] The second capacitance connection switch SW2 is provided between the second capacitance C2 of the second anti-aliasing filter 113 and the second input terminal Vin- of the ΔΣAD converter 120. The second capacitance connection switch SW2 can switch the second capacitance C2 of the second anti-aliasing filter 113 between a state in which it is connected to the second input terminal Vin- of the ΔΣAD converter 120 and a state in which it is disconnected from the second input terminal Vin- of the ΔΣAD converter 120.

[0034] The ΔΣAD converter 120 is provided in the subsequent stage of the current detection amplifier 110, and performs AD conversion on the detection signal Vout (analog signal) output from the current detection amplifier 110 to a digital signal.

[0035] For example, the ΔΣ AD converter 120 is configured to include a ΔΣ modulator that performs AD conversion on the detection signal Vout (analog signal) output from the current detection amplifier 110, and a digital filter that performs filtering processing on the detection signal that has been AD converted by the ΔΣ modulator.

[0036] Note that Fig. 1 illustrates a portion (input section) of the ΔΣAD converter 120. As shown in Fig. 1, the portion (input section) of the ΔΣAD converter 120 includes a first input terminal Vin+, a second input terminal Vin-, a first sampling capacitor C31 connected to the first input terminal Vin+, and a second sampling capacitor C32 connected to the second input terminal Vin-.

[0037] Furthermore, a part (input section) of the ΔΣ AD converter 120 includes a differential operational amplifier 121 connected to a first sampling capacitor C31 and a second sampling capacitor C32, a first integrating capacitor C35 provided between the negative input terminal and the positive output terminal of the differential operational amplifier 121, a second integrating capacitor C36 provided between the positive input terminal and the negative output terminal of the differential operational amplifier 121, sampling switches SW51 to SW56, and integrating switches SW61 to SW64.

[0038] By switching the sampling switches SW51-SW56 and the integration switches SW61-SW64, the ΔΣ AD converter 120 can be switched between a state in which the detection signal Vout output from the current detection amplifier 110 is sampled in the first sampling capacitor C31 and the second sampling capacitor C32, and a state in which the charges sampled in the first sampling capacitor C31 and the second sampling capacitor C32 are integrated in the first integration capacitor C35 and the second integration capacitor C36.

[0039] Specifically, the ΔΣ AD converter 120 can switch to a state in which the detection signal Vout output from the current detection amplifier 110 is sampled by the first sampling capacitor C31 and the second sampling capacitor C32 by simultaneously switching on the sampling switches SW51 to SW56 and simultaneously switching off the integration switches SW61 to SW64.

[0040] Conversely, the ΔΣ AD converter 120 can switch to a state in which the charges sampled in the first sampling capacitor C31 and the second sampling capacitor C32 are integrated in the first integrating capacitor C35 and the second integrating capacitor C36 by simultaneously switching off the sampling switches SW51 to SW56 and simultaneously switching on the integration switches SW61 to SW64.

[0041] In this embodiment, the ΔΣ AD converter 120 is provided. Although a ΔΣ AD converter is used here as an example, any type of AD converter can be used as long as it is an AD converter equipped with a sampling capacitance.

[0042] The current detection device 100 of this embodiment is an example of a "semiconductor device for current detection", and the current detection amplifier 110 and the ΔΣAD converter 120 are implemented in a single semiconductor integrated circuit. In particular, the current detection device 100 of this embodiment can reduce the capacitance of the first capacitance C1 and the second capacitance C2 for removing high-frequency components, so that the first capacitance C1 and the second capacitance C2 can be implemented in the current detection amplifier 110, and the current detection amplifier 110 and the ΔΣAD converter 120 can be implemented in a single semiconductor integrated circuit.

[0043] (Timing of each signal in the current detection device 100) FIG. 2 is a timing chart showing timings of each part in the current detection device 100 according to one embodiment.

[0044] The timing chart shown in Figure 2 shows, from top to bottom, the switching timing of the capacitance connection switches SW1 and SW2 provided in the current detection amplifier 110, the switching timing of the sampling switches SW51 to SW56 provided in the ΔΣ AD converter 120, the switching timing of the integration switches SW61 to SW64 provided in the ΔΣ AD converter 120, the switching timing of the chopping switches SW11 to SW14 provided in the current detection amplifier 110, the switching timing of the chopping switches SW21 to SW24 provided in the current detection amplifier 110, and the voltage level of the signal Vamp output from the differential operational amplifier 111.

[0045] In the timing chart shown in FIG. 2, timings T1 and T4 indicate the timings at which chopping is performed on the signal Vamp output from the differential operational amplifier 111.

[0046] 2, timings T2 and T5 indicate the timings at which the first sampling capacitor C31 and the second sampling capacitor C32 included in the ΔΣ AD converter 120 start sampling.

[0047] Also, in the timing chart shown in Figure 2, timings T3 and T6 indicate the timings at which the capacitances C1 and C2 of the anti-aliasing filters 112 and 113 are connected to the first sampling capacitance C31 and the second sampling capacitance C32 provided in the ΔΣ AD converter 120 and sampled by the first sampling capacitance C31 and the second sampling capacitance C32.

[0048] As shown in FIG. 2, in the current detection amplifier 110, chopping is performed on the signal Vamp by switching between the chopping switches SW11 to SW14 and the chopping switches SW21 to SW24 at a constant cycle.

[0049] Also, as shown in FIG. 2, in the ΔΣ AD converter 120, by switching the sampling switches SW51-SW56 and the integrating switches SW61-SW64 at a constant period, the detection signal Vout output from the current detection amplifier 110 is alternately switched between a state in which the detection signal Vout is sampled by the first sampling capacitor C31 and the second sampling capacitor C32, and a state in which the charges sampled by the first sampling capacitor C31 and the second sampling capacitor C32 are integrated by the first integrating capacitor C35 and the second integrating capacitor C36.

[0050] Furthermore, as shown in FIG. 2, the current detection amplifier 110 can sample the capacitances C1 and C2 of the anti-aliasing filters 112 and 113 to the first sampling capacitance C31 and the second sampling capacitance C32 by switching on the capacitance-connecting switches SW1 and SW2 at a constant cycle.

[0051] 2, at the times T1 and T4 when chopping is performed, the capacitance-connecting switches SW1 and SW2 are off. That is, at the times T1 and T4 when chopping is performed, the capacitances C1 and C2 of the anti-aliasing filters 112 and 113 are not connected.

[0052] As a result, the current detection amplifier 110 according to one embodiment can prevent noise generated in the detection signal Vout when the polarity of the signal Vamp is inverted from being superimposed on the capacitances C1 and C2, thereby making it possible to reduce the capacitances of the capacitances C1 and C2.

[0053] 2, the capacitance-connecting switches SW1 and SW2 are also off at timings T2 and T5 when sampling is started for the first sampling capacitance C31 and the second sampling capacitance C32. That is, the capacitances C1 and C2 of the anti-aliasing filters 112 and 113 are not connected at timings T2 and T5 when sampling is started.

[0054] As a result, in the current detection amplifier 110 of one embodiment, the charge redistribution that occurs at the start of sampling is performed by the differential operational amplifier 111, and charge redistribution is not performed by the capacitances C1 and C2, so that the capacitances C1 and C2 can be made small.

[0055] 2, after sampling is started, at timings T3 and T6 immediately before the sampling switches SW51 to SW56 are switched off, the capacitance-connecting switches SW1 and SW2 are switched on, and the capacitances C1 and C2 of the anti-aliasing filters 112 and 113 are connected to the first sampling capacitance C31 and the second sampling capacitance C32. As a result, the current detection device 100 according to one embodiment can cause the ΔΣ AD converter 120 to sample the signal from which high-frequency noise has been removed by the anti-aliasing filters 112 and 113.

[0056] In this way, the current detection amplifier 110 according to one embodiment can prevent noise during chopping from being superimposed on the capacitances C1 and C2, and can also prevent charge redistribution from the capacitances C1 and C2, making it possible to make the capacitances C1 and C2 extremely small. Therefore, the current detection amplifier 110 according to one embodiment can implement the capacitances C1 and C2 on a single semiconductor integrated circuit.

[0057] For example, in the configuration of Patent Document 1, the anti-aliasing filter required a capacitance of 0.01 to 0.1 μF, but in the present invention, the anti-aliasing filter can have a capacitance of 100 pF or less, making it possible to incorporate the anti-aliasing filter into a semiconductor integrated circuit.

[0058] (Modification of the circuit configuration of the current detection device 100) FIG. 3 is a diagram showing a modified example of the circuit configuration of the current detection device 100 according to the embodiment.

[0059] The current detection device 100-2 shown in FIG. 3 differs from the current detection device 100 shown in FIG.

[0060] The current detection amplifier 110-2 includes a resistor chopping switch SW31, a resistor chopping switch SW32, a resistor chopping switch SW33, and a resistor chopping switch SW34 between the current detection resistor R1 and the resistors R21 and R23.

[0061] The resistor chopping switch SW31 is provided between one end of the current detection resistor R1 and the resistor R21. The resistor chopping switch SW32 is provided between one end of the current detection resistor R1 and the resistor R23. The resistor chopping switch SW33 is provided between the other end of the current detection resistor R1 and the resistor R21. The resistor chopping switch SW34 is provided between the other end of the current detection resistor R1 and the resistor R23.

[0062] This allows the current detection amplifier 110-2 to chop (that is, invert the polarity of) the detection signal input from the current detection resistor R1 to the resistors R21 and R23 by switching the resistor chopping switches SW31 to SW34.

[0063] 3, polysilicon resistors are used for each of resistors R21 to R24 (gain determining resistors). Therefore, in current detection amplifier 110-2, there is a risk that 1 / f noise will occur in resistors R21 to R24.

[0064] Therefore, the current detection amplifier 110-2 chops the detection signals input to the resistors R21 and R23. Specifically, the current detection amplifier 110-2 switches the resistor chopping switches SW31 and SW34 on and off at the same timing as the switching timing of SW11 to SW14 shown in FIG. 2, and switches the resistor chopping switches SW32 and SW33 on and off at the same timing as the switching timing of SW21 to SW24 shown in FIG.

[0065] This allows the current detection amplifier 110-2 to chop the detection signal input to the resistors R21 and R23, and therefore allows the 1 / f noise generated in the resistors R21 to R24 and the 1 / f noise generated in the differential operational amplifier 111 to be suppressed.

[0066] The resistor chopping switches SW31 to SW34 are an example of a "second chopping section" that chops the signal input to the gain detection resistor.

[0067] (An example of output from the current detection amplifier 110) Fig. 4 is a timing chart showing an example of an output when the capacitances C1 and C2 of the anti-aliasing filters 112 and 113 are connected at a constant cycle when the current detection amplifier 110 according to one embodiment is started up. Fig. 5 is a timing chart showing an example of an output when the capacitances C1 and C2 of the anti-aliasing filters 112 and 113 are kept connected when the current detection amplifier 110 according to one embodiment is started up.

[0068] The timing charts shown in Figures 4 and 5 show, from top to bottom, the switching timing of the enable signal of the current detection device 100, the switching timing of the capacitance connection switches SW1 and SW2 provided in the current detection amplifier 110, the switching timing of the sampling switches SW51 to SW56 provided in the ΔΣ AD converter 120, the switching timing of the integration switches SW61 to SW64 provided in the ΔΣ AD converter 120, the switching timing of the chopping switches SW11 to SW14 provided in the current detection amplifier 110, the switching timing of the chopping switches SW21 to SW24 provided in the current detection amplifier 110, and the amount of charge of the capacitances C1 and C2 of the anti-aliasing filters 112 and 113.

[0069] As shown in FIG. 5, a current detection amplifier 110 according to one embodiment may switch on the capacitance connection switches SW1 and SW2 at startup (i.e., the timing when the startup signal (Enable signal) of the current detection device 100 is switched on) to connect the capacitances C1 and C2 of the anti-aliasing filters 112 and 113 to the sampling capacitances C31 and C32 of the ΔΣ AD converter 120 until a predetermined time has elapsed or until the amount of charge of the capacitances C1 and C2 of the anti-aliasing filters 112 and 113 reaches a predetermined threshold.

[0070] As a result, in one embodiment of the current detection amplifier 110, the charging time until the charge amount of the capacitances C1 and C2 of the anti-aliasing filters 112 and 113 reaches a certain amount at startup can be shortened compared to when the capacitances C1 and C2 of the anti-aliasing filters 112 and 113 are connected to the sampling capacitances C31 and C32 of the ΔΣ AD converter 120 at a constant period at startup (see Figure 4), thereby shortening the startup time.

[0071] Although one embodiment of the present invention has been described in detail above, the present invention is not limited to these embodiments, and various modifications and changes are possible within the scope of the gist of the present invention described in the claims.

[0072] For example, the present invention is applicable not only to a differential current detection amplifier but also to a single-ended current detection amplifier. [Explanation of symbols]

[0073] 100, 100-2 Current detection device (current detection semiconductor device) 110,110-2 Current Sense Amplifier 111 Differential Op-Amp 112 1st anti-aliasing filter (1st noise reduction filter) 113 Second anti-aliasing filter (second noise reduction filter) 120 ΔΣAD converter (AD converter) 121 Differential Op-Amp L1 wiring R1 Current detection resistor R21~R24 Resistors (gain determining resistors) SW11~SW14, SW21~SW24 Chopping switches (first chopping section) C1 First capacitance C2 Second Capacity C31 First sampling capacitance C32 Second sampling capacitor C35 First integral capacitance C36 Second integration capacitor SW1 First capacitor connection switch SW2 Second capacitor connection switch SW31~SW34 Resistor chopping switches (second chopping section) SW51~SW56 Sampling switches SW61~SW64 Integral switches Vin+ 1st input terminal Vin- 2nd input terminal

Claims

1. A current detection amplifier that amplifies a detection signal of a current flowing through a current detection resistor and then outputs the amplified signal to an AD converter, a first noise elimination filter connected to one end of the current detection resistor and including a first capacitance and a first resistor; a first capacitance connection switch provided between the first capacitance of the first noise removal filter and a first sampling capacitance of the AD converter; A current detection amplifier comprising:

2. When sampling of the detection signal output from the current detection amplifier is started in the first sampling capacitor of the AD converter, The first capacitor connection switch is turned off to not connect the first capacitor of the first noise elimination filter to the first sampling capacitor of the AD converter.

2. The current detection amplifier according to claim 1 .

3. After starting sampling of the detection signal output from the current detection amplifier to the first sampling capacitor of the AD converter, The first capacitance connection switch is turned on to connect the first capacitance of the first noise elimination filter to the first sampling capacitance of the AD converter.

3. The current detection amplifier according to claim 2.

4. a first chopping unit that chops the detection signal input from the current detection amplifier to the AD converter; When the first chopping unit chops the detection signal, The first capacitor connection switch is turned off to not connect the first capacitor of the first noise elimination filter to the first sampling capacitor of the AD converter.

4. The current detection amplifier according to claim 3.

5. a second noise elimination filter connected to the other end of the current detection resistor and including a second capacitance and a second resistor; a second capacitance connection switch provided between the second capacitance of the second noise removal filter and a second sampling capacitance of the AD converter, turning off the second capacitance connection switch to not connect the second capacitance of the second noise removal filter to the second sampling capacitance of the AD converter; The second capacitance connection switch is turned on to connect the second capacitance of the second noise elimination filter to the second sampling capacitance of the AD converter.

5. The current detection amplifier according to claim 4.

6. a gain determining resistor that determines a gain of the detection signal by the current detection amplifier; a second chopping unit that chops the detection signal input from the current detection resistor to the gain determination resistor; 6. The current sense amplifier of claim 5, further comprising:

7. At startup, The first capacitance is connected to the first sampling capacitance until a predetermined time has elapsed or until the charge amount of the first sampling capacitance reaches a predetermined threshold.

3. The current detection amplifier according to claim 2.

8. A current detection amplifier according to any one of claims 1 to 7; The AD converter A current detection semiconductor device comprising the above in a single semiconductor integrated circuit.

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