Manufacturing method of packaging substrate and the packaging substrate using them

Abstract

To provide a manufacturing method of a packaging substrate, capable of rapidly reducing a wrapping phenomenon after the formation of an insulation layer, and largely improving a yield and a quality, and the packaging substrate.SOLUTION: A manufacturing method of a packaging substrate contains: a step of generating a glass structure of a core via 23, a cavity part 28, or all of them to a glass core 21 containing a first surface 213 and a second surface 214 that are opposite each other; a step of forming an upper insulation layer 253 onto a first surface by using an insulation film; and a step of forming an upper layer 26 containing an upper part distribution layer 25 and an upper surface connection layer 27 onto an upper part of the upper part insulation layer. The step of forming the upper part insulation layer contains a primary hardening step of performing a primary hardening after laminating the first insulation film onto the first surface, and a secondary hardening step of performing a secondary hardening after the second insulation film is laminated onto the first insulation film to which the primary hardening is made. Through the steps, a warpage is improved, and a deviation of an electron element can be prevented.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present embodiment relates to a method for manufacturing a semiconductor packaging substrate, and is a technique for manufacturing a packaging substrate including a glass core and an insulating layer, and a packaging substrate using the same. [Background technology]

[0002] In manufacturing electronic components, the process of creating circuits on a semiconductor wafer is called the front-end process (FE: Front-End), and the process of assembling the wafer so that it can be used in an actual product is called the back-end process (BE: Back-End), which includes the packaging process.

[0003] The four core technologies of the semiconductor industry that have enabled the recent rapid development of electronic products are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. Semiconductor technology has evolved into various forms, such as nano-level line widths below the micron level, over 10 million cells, high-speed operation, and large amounts of heat dissipation, but the technology to perfectly package these has not been supported. As a result, the electrical performance of semiconductors is sometimes determined by the packaging technology and the resulting electrical connections, rather than the performance of the semiconductor technology itself.

[0004] Although ceramic or resin is used as a material for packaging substrates, recently, research has been conducted on the application of silicon or glass to high-end packaging substrates, and in particular, packaging substrates having a cavity structure using a glass core have been developed.

[0005] Related prior art includes U.S. Patent Publication US2022 / 0293560A1 and Korean Patent Publication No. 10-2018-0142742. Summary of the Invention [Problem to be solved by the invention]

[0006] An object of the embodiment is to provide a method for manufacturing a packaging substrate that can improve warping that can occur due to differences in the degree of thermal expansion and the resulting stress in a packaging substrate using a glass core and an insulating film, and a packaging substrate using the same.

[0007] Another object of the embodiment is to provide a method for manufacturing a packaging substrate capable of preventing separation or detachment of an electronic element disposed in a cavity of a glass core, and a packaging substrate using the same. [Means for solving the problem]

[0008] To achieve the above object, a manufacturing method of a packaging substrate according to one embodiment includes the steps of: generating a glass structure, which is a core via, a cavity portion, or all of these, in a glass core having a first surface and a second surface facing each other; forming an insulating layer using an insulating film on the first surface or the second surface; and forming an upper layer including an upper distribution layer and an upper surface connection layer on top of the insulating layer.

[0009] The step of forming the insulating layer may include a primary curing step of laminating a first insulating film on the first surface and then primary curing, and a secondary curing step of laminating a second insulating film on the primarily cured first insulating film and then secondary curing.

[0010] The cavity portion is recessed and opens toward the first surface or the second surface of the glass core, or has a space penetrating the first surface and the second surface in which an electronic element is disposed.

[0011] The method for manufacturing the packaging substrate may further include arranging electronic elements in the cavity portion.

[0012] In one embodiment, the step of arranging the electronic elements may be performed between the step of forming the glass structure and the step of forming the insulating layer.

[0013] In an embodiment, the first insulating film may be laminated on the entire first surface or on the cavity portion in which the electronic elements are arranged.

[0014] In an embodiment, when the first insulating film is laminated in the cavity portion, the first insulating film may be cut based on the shape and size of the cavity portion.

[0015] In an embodiment, the first insulating film and the second insulating film may have different thicknesses.

[0016] In an embodiment, the first curing step and the second curing step may each be performed by a reduced pressure lamination method, and the pressure and temperature applied in the second curing step may be higher than the pressure and temperature applied in the first curing step.

[0017] The method for manufacturing the packaging substrate may further include a final curing step after the secondary curing step.

[0018] The final curing step is a step of further curing the first insulating film and the second insulating film to achieve final curing.

[0019] In an embodiment, the electronic element may include a passive element or an active element.

[0020] Meanwhile, in order to achieve the above object, a packaging substrate according to one embodiment includes a core layer and an upper layer located on the core layer, and the core layer includes a glass core having a first surface and a second surface facing each other, a plurality of core vias and a cavity portion penetrating the glass core in a thickness direction, an electrically conductive layer disposed on a surface of the glass core, electronic elements arranged in the cavity portion, and an insulating layer filling the core vias and the cavity portion.

[0021] The cavity portion may be recessed and open toward the first surface or the second surface of the glass core, or may have a space penetrating the first surface and the second surface, and the insulating layer may include a first insulating layer formed by laminating a first insulating film on the first surface and curing it, and a second insulating layer formed by laminating a second insulating film on the first insulating layer and curing it.

[0022] In an embodiment, the first insulating layer may be formed on the entire first surface or in the cavity portion in which the electronic elements are arranged.

[0023] In an embodiment, the insulating layer may further include a third insulating layer formed by laminating a third insulating film on the second surface and curing the third insulating layer, and the third insulating layer may be formed on the second surface by being embedded in a direction toward the first surface.

[0024] In an embodiment, a first boundary where the first insulating film and the second insulating film contact each other may be formed between the first insulating layer and the second insulating layer.

[0025] In an embodiment, a second boundary where the first insulating film and the third insulating film contact each other may be formed between the first insulating layer and the third insulating layer.

[0026] The second boundary may be formed within the core via and the cavity portion.

[0027] In an embodiment, the color of the first insulating layer and the color of the third insulating layer may be differentiated from each other, i.e., may be different from each other.

[0028] In an embodiment, the first insulating layer and the second insulating layer may have different thicknesses.

[0029] In one embodiment, the glass core may be a rectangular glass sheet.

[0030] In one embodiment, the glass core may have a thickness of 300 μm to 1,500 μm.

[0031] In one embodiment, a height at which a corner of the packaging substrate is spaced from a floor on which the packaging substrate is placed may be 12 mm or less.

[0032] The electronic elements may include passive elements or active elements. Effect of the Invention

[0033] In the method for manufacturing a packaging substrate according to the embodiment and the packaging substrate using the same, the warping phenomenon is significantly reduced even after the insulating layer is formed, and the yield and quality of the packaging substrate can be significantly improved.

[0034] In addition, the improvement in the warping phenomenon makes it possible to prevent the electronic elements disposed in the cavity of the glass core from being separated or detached. [Brief description of the drawings]

[0035] [Figure 1] 1 is a conceptual diagram illustrating a cross-sectional structure of a packaging substrate according to an embodiment; [Diagram 2] 13 is a conceptual diagram illustrating a cross-sectional structure of a packaging substrate according to another embodiment; FIG. [Diagram 3] 1A and 1B are schematic cross-sectional views illustrating a portion of a packaging substrate according to an embodiment. [Figure 4] 1 is a flowchart illustrating a process of forming a core distribution layer in a process of manufacturing a packaging substrate according to an embodiment. [Diagram 5] 1 is a flowchart illustrating a process of forming an insulating layer in a process of manufacturing a packaging substrate according to an embodiment. [Figure 6] 1A and 1B are diagrams for explaining a warpage phenomenon that occurs in a packaging substrate when an insulating layer is formed as in the conventional method. [Figure 7]1 is a cross-sectional view illustrating a concept of a method for manufacturing a packaging substrate according to an embodiment; [Figure 8] 1 is a flowchart illustrating a cross-sectional view of a manufacturing process of a packaging substrate according to an embodiment, in which P1 represents a first pre-cure step, P2 represents a second pre-cure step, L1 represents expected boundary line 1, and L2 represents expected boundary line 2. [Figure 9A] FIG. 9A is a photograph showing the boundaries of insulating layers produced by manufacturing a packaging substrate according to an embodiment, and shows a sample in which an insulating film having a thickness of 70 μm is used as the first insulating film, and insulating films having a thickness of 60 μm and 80 μm are used as the second insulating film and the third insulating film, respectively. [Figure 9B] FIG. 9B is a photograph showing the boundaries of insulating layers generated by manufacturing a packaging substrate according to an embodiment. From the left, FIG. 9B shows samples in which an insulating film having a thickness of 60 μm, an insulating film having a thickness of 70 μm, and an insulating film having a thickness of 80 μm are applied as the second insulating film. [Figure 10] 1 is a photograph for explaining warpage of a packaging substrate produced by manufacturing a packaging substrate according to an embodiment; [Figure 11] 11 is a flowchart illustrating a manufacturing process of a packaging substrate according to another embodiment. [Figure 12] 11 is a conceptual cross-sectional view illustrating a structure of a packaging substrate according to another embodiment; FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0036] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily understand the embodiments. However, the embodiments may be embodied in many different forms and are not limited to the embodiments described herein. The same reference numerals are used throughout the specification to refer to similar parts.

[0037] Throughout this specification, the term "combinations thereof" in a Markush form phrase means a mixture or combination of one or more selected from the group of elements set forth in the Markush form phrase, including one or more selected from the group of elements.

[0038] Throughout this specification, terms such as "first," "second," or "A," "B" are used to distinguish identical terms from one another, and singular expressions include plural expressions unless the context clearly indicates otherwise.

[0039] In this specification, the term "-" may mean that the compound includes a compound that corresponds to "-" or a derivative of "-".

[0040] In this specification, the term "B is located on A" means that B is located on A in direct contact therewith, or that B is located on A with another layer located therebetween, and is not to be interpreted as being limited to B being located in contact with the surface of A.

[0041] In this specification, the expression "B is linked to A" means that A and B are directly linked, or that A and B are linked via another component between them, and unless otherwise specified, it is not to be interpreted as being limited to A and B being directly linked.

[0042] In this specification, the term "singular" is to be construed as including the singular or plural as the context requires, unless otherwise specified.

[0043] In the process of developing a semiconductor device that is more integrated and can achieve high performance with a thinner thickness, the inventors recognized that not only the element itself but also the packaging is an important factor in improving performance. As a result of their research, they discovered that unlike conventional interposers and organic substrates, which use two or more layers of cores on a motherboard as a packaging substrate, by applying a single layer of glass core and applying a cavity structure, it is possible to make the packaging substrate thinner and help improve the electrical characteristics of the semiconductor device, and thus completed the invention.

[0044] The RDL formation process involves the hardening of insulating layers such as ABF (Ajinomoto Build-up Film), and during this process, the packaging substrate may warp. The inventors determined that this phenomenon is caused by the difference in the degree of thermal expansion (thermal expansion coefficient) between the internal components that make up the substrate and the ABF, which generates thermal stress, and recognized the need to improve the warpage phenomenon.

[0045] As a result of further research, we discovered that when creating an insulating layer in a core-via and cavity structure, pre-curing the insulating film multiple times instead of just once can improve the warping phenomenon of the glass core caused by factors such as the difference in CTE (coefficient of thermal expansion) between the insulating film and the glass core (WARPAGE), and thus completed our invention.

[0046] FIG. 1 is a conceptual diagram illustrating the cross-sectional structure of a packaging substrate according to an embodiment, FIG. 2 is a conceptual diagram illustrating the cross-sectional structure of a packaging substrate according to another embodiment, and FIGS. 3(a) and (b) are conceptual diagrams illustrating the cross-section of a portion of a packaging substrate according to an embodiment.

[0047] To achieve the above objective, the semiconductor device 100 of the embodiment includes a semiconductor element section 30 in which one or more semiconductor elements 32, 34, and 36 are located, a packaging substrate 20 electrically connected to the semiconductor elements, and a motherboard 10 electrically connected to the packaging substrate 20, which transmits external electrical signals to and connects the semiconductor elements 32, 34, and 36 to each other.

[0048] The packaging substrate 20 according to an embodiment includes a core layer 22, an upper layer 26 disposed on one surface of the core layer 22, and a cavity portion 28 in which an electronic element 40 can be disposed.

[0049] The semiconductor element section 30 means an element mounted on a semiconductor device, and is mounted on the packaging substrate 20 by connection electrodes or the like. Specifically, the semiconductor element section 30 may be, for example, a computing element such as a CPU or a GPU (first element: 32, second element: 34), a storage element such as a memory chip (third element: 36), or the like, but any semiconductor element mounted on a semiconductor device can be used without any restrictions.

[0050] The motherboard 10 may be a motherboard such as a printed circuit board or a printed wiring board.

[0051] The packaging substrate 20 may optionally further include a lower layer 38 located below the core layer.

[0052] The core layer 22 may include a glass core 21 including a first region 221 having a first thickness 211 and a second region 222 adjacent to the first region 221 and having a second thickness 212 that is thinner than the first thickness; a number of core vias 23 penetrating the glass core 21 in the thickness direction; and a core distribution layer 24 located on the surface of the glass core 21 or the core vias 23 and electrically connecting a first surface 213 of the glass core 21 to a second surface 214 facing the first surface through the core vias 23. That is, the core layer 22 may refer to a glass structure that is a glass core 21 including a first surface 213 and a second surface 214 facing each other, a core via 23, a cavity portion 28, or all of these.

[0053] The second region 222 of the core layer 22 may serve as a cavity structure.

[0054] Within the same area, the glass core 21 has a first surface 213 and a second surface 214 opposed to each other, and these two surfaces are generally parallel to each other, so that the glass core 21 has a constant thickness throughout.

[0055] An internal space 281 formed by the difference in thickness between the first region 221 and the second region 222 serves to accommodate a part or the whole of the electronic element 40 .

[0056] The glass core 21 may include core vias 23 penetrating the first surface 213 and the second surface 214. The core vias 23 may be formed in both the first region 221 and the second region 222 and may be formed at any desired pitch and pattern.

[0057] Conventionally, packaging substrates for semiconductor devices have been applied in the form of a laminate of a silicon substrate and an organic substrate. In the case of a silicon substrate, due to the characteristics of a semiconductor, there is a risk of parasitic elements being generated when applied to high-speed circuits, and there is a drawback in that the power loss is relatively large. In addition, in the case of an organic substrate, a large area is required to form an increasingly complex distribution pattern, which does not fit with the trend of manufacturing electronic devices that are becoming ultra-miniaturized. In order to form a complex distribution pattern within a set size, it is necessary to substantially fine the pattern, but there is a substantial limit to the fine pattern due to the characteristics of materials such as polymers applied to organic substrates.

[0058] In the embodiment, to solve this problem, the glass core 21 is used as a support for the core layer 22. In addition, by using the glass core 21 and the core via 23 formed penetrating the glass core 21, the length of electrical flow is further shortened, providing a packaging substrate 20 that is more compact, has faster response, and has less loss characteristics.

[0059] The glass core 21 is preferably made of a plate glass used in semiconductors. For example, borosilicate plate glass, non-alkali plate glass, etc. may be used, but is not limited thereto.

[0060] The core via 23 penetrates the glass core 21. The core via 23 may be formed by removing a predetermined region of the glass core 21, specifically, by etching a plate-shaped glass by a physical and / or chemical method.

[0061] Specifically, the formation of the core via 23 may be achieved by forming a defect (groove) on the surface of the glass core using a laser or other method, followed by chemical etching, laser etching, etc., but is not limited thereto.

[0062] The core vias 23 may be positioned at 100 to 3,000, 100 to 2,500, or 225 to 1,024 per unit area (1 cm×1 cm) of the glass core 21. When such pitch conditions are satisfied, the formation of an electrically conductive layer and the performance of the packaging substrate can be improved.

[0063] The core distribution layer 24 includes a core distribution pattern 241, which is an electrically conductive layer that electrically connects the first and second surfaces of the glass core through a through via, and a core insulating layer 223 that surrounds the core distribution pattern. The core layer 22 has an electrically conductive layer formed therein through a core via, and serves as an electrical path across the glass core 21, and connects the upper and lower parts of the glass core over a relatively short distance, allowing for faster electrical signal transmission and low loss characteristics. The electrically conductive layer may be, for example, a copper plating layer, but is not limited thereto.

[0064] The shape of the cavity portion 28 is not limited and may be substantially circular, triangular, rectangular, hexagonal, octagonal, cross-shaped, or the like.

[0065] The electronic element 40 may be generally cylindrical, rectangular, or polygonal in shape.

[0066] The cavity portion 28 may include a cavity distribution pattern, which is an electrically conductive layer that electrically connects the electronic element 40 and the core distribution layer 24, and an insulating layer that surrounds the cavity distribution pattern.

[0067] Meanwhile, the cavity portion according to another embodiment may be embodied in a form penetrating the first surface 213 and the second surface 214 of the glass core 21. In this case, the cavity portion may be formed by the same process as the process of forming the core via 23, and the area and shape penetrating the glass core 21 may be different from those of the core via 23.

[0068] In this embodiment, an insulating layer may be formed in the cavity after the electronic device 40 is arranged in the cavity. That is, an insulating layer may be formed in the cavity through the process of forming the core insulating layer 223 described above.

[0069] The core distribution pattern 241 may be patterned so as to be electrically connectable to the electronic element 40 .

[0070] The electronic element 40 may include an active element such as a transistor, or a power transfer element, ie, a passive element, such as a multi-layer ceramic capacitor (MLCC).

[0071] When an element such as a transistor that converts electrical signals between a motherboard and a semiconductor element portion to an appropriate level is applied as the electronic element 40, a transistor or the like is applied to the passage of the packaging substrate 20, so that a more efficient and faster semiconductor device 100 can be provided.

[0072] In addition, power transfer devices such as multilayer ceramic capacitors (MLCCs) play an important role in the performance of semiconductor devices. Power transfer devices, which are passive devices, are generally applied to semiconductor devices in numbers of at least 200, and the performance of the device is also affected by the characteristics of the electrical conductive layer around the device when transferring power. In one embodiment, a non-circular core via can be applied to such power transfer devices, where an electrical conductive layer with low resistance is required.

[0073] Meanwhile, the electronic device 40 may be applied by inserting passive devices such as capacitors individually, or a device group including a number of passive devices embedded between insulating layers (cavity insulating layers) may be formed with electrodes exposed and then inserted into the electronic device. In the latter case, the workability of manufacturing the packaging substrate may be further improved, and it is more advantageous for insulating layers to be positioned sufficiently and reliably in spaces between complex devices.

[0074] The glass core 21 acts as an intermediate or mediator connecting the semiconductor device part 30 and the motherboard 10 at the upper and lower parts, respectively, and the core vias 23 act as paths for transmitting electrical signals, thereby ensuring smooth signal transmission.

[0075] A top layer 26 is positioned on the first surface 213 .

[0076] The upper layer 26 includes an upper distribution layer 25 and an upper surface connection layer 27 located on the upper distribution layer 25, and the top surface of the upper layer 26 can be protected by a cover layer 60 having an opening formed therein to which a connection electrode of a semiconductor element portion can directly abut.

[0077] The upper distribution layer 25 includes an upper insulating layer 253 located on the first surface, and an upper distribution pattern 251 having a predetermined pattern and being an electrically conductive layer to which at least a portion of the core distribution layer 24 is electrically connected, the upper distribution pattern 251 being embedded in the upper insulating layer 253.

[0078] The upper insulating layer 253 may be any material that can be used as an insulating layer for a semiconductor device or a packaging substrate, such as, but not limited to, an epoxy resin containing a filler.

[0079] The insulator layer may be formed by forming a coating layer and curing it, or may be formed by laminating an insulator film in an uncured or semi-cured state onto the core layer 22 and curing it. In this case, if a reduced pressure lamination method is used, the insulator can be filled into the inner space of the core via 23, allowing for efficient process.

[0080] According to one embodiment, even if multiple insulating layers are applied by stacking, it may be difficult to substantially separate the insulating layers, and the multiple insulating layers are collectively referred to as the upper insulating layer. Also, the core insulating layer 223 and the upper insulating layer 253 may be made of the same insulating material, in which case the boundary between them is not substantially separated. Alternatively, according to another embodiment, the boundary between the insulating layers may be created by setting different pressures and temperatures for curing the multiple insulating layers.

[0081] The upper distribution pattern 251 means an electrically conductive layer located in the upper insulating layer 253 in a predetermined shape, and may be formed, for example, by a build-up layer method. In particular, an insulating layer is formed, unnecessary parts of the insulating layer are removed, an electrically conductive layer is formed by a method such as copper plating, and an unnecessary part of the electrically conductive layer is selectively removed, an insulating layer is formed again on the electrically conductive layer, the unnecessary parts are removed again, and an electrically conductive layer is formed by a method such as plating, and the like. By repeating these methods, the upper distribution pattern 251 having an electrically conductive layer formed vertically or horizontally in a desired pattern can be formed.

[0082] The upper distribution pattern 251 is located between the core layer 22 and the semiconductor device part 30, and therefore is formed to include a fine pattern in at least a part thereof so that electrical signals can be smoothly transmitted to the semiconductor device part 30 and the intended complex pattern can be fully accommodated. In this case, the fine pattern may have a width and interval each of less than 4 μm, 3.5 μm or less, 3 μm or less, 2.5 μm or less, or 1 to 2.3 μm (the same applies to the following explanation of the fine pattern).

[0083] The upper connection layer 27 includes an upper connection pattern 272, at least a portion of which is electrically connected to the upper distribution pattern 251 and located on the upper insulating layer 253, and an upper connection electrode 271 that electrically connects the semiconductor device unit 30 and the upper connection pattern 272. The upper connection pattern 272 may be located on one surface of the upper insulating layer 253, or may be embedded with at least a portion thereof exposed on the upper insulating layer. For example, when the upper connection pattern is located on one surface of the upper insulating layer, the upper insulating layer may be formed by plating or the like, and when the upper connection pattern is embedded with a portion thereof exposed on the upper insulating layer, a copper plating layer or the like may be formed, and then a portion of the insulating layer or the electrically conductive layer may be removed by surface polishing, surface etching, or the like.

[0084] The upper connection pattern 272 may include a fine pattern at least in a portion thereof, like the above-mentioned upper distribution pattern 251. The upper connection pattern 272 including such a fine pattern can electrically connect more elements in a small area, facilitate the connection of electrical signals between elements or with the outside, and enable more integrated packaging.

[0085] The upper connection electrodes 271 may be directly connected to the semiconductor device part 30 via terminals or the like, or may be connected via device connection parts 51 such as solder balls.

[0086] The cavity portion 28 is located above and / or below the second region 222 and includes a cavity distribution layer 282 electrically connected to the core distribution pattern 241 and an internal space 281 in which the electronic element 40 is located.

[0087] Specifically, the thickness of the glass core 21 in the second region 222 is thinner than that in the first region 221, and the electronic element 40 can be positioned in an internal space 281 formed by the difference in thickness. In addition, the core via 23 and the core distribution layer 24 formed in the glass core 21 serve as an electrical connection structure that connects the electronic element 40 to an external element.

[0088] Also, as described above, a cavity portion may be generated in the first area 221, i.e., penetrating the first surface 213 and the second surface 214 of the glass core 1, rather than the second area 222, and an electronic element 40 may be arranged in the cavity portion.

[0089] The packaging substrate 20 is also connected to the motherboard 10. The terminals of the motherboard 10 may be directly connected to a core distribution pattern 241 located on at least a portion of the second surface 214 of the core layer 22, or may be electrically connected to the motherboard 10 via a board connection part 52 such as a solder ball. The core distribution pattern 241 in contact with the motherboard 10 may be connected to the motherboard 10 via a lower layer 38 located at the bottom of the core layer 22.

[0090] For example, the packaging substrate 20 located between the semiconductor device unit 30 and the motherboard 10 may not include any additional substrate other than the glass core 21 .

[0091] Conventionally, when connecting a device to a motherboard, an interposer and an organic substrate are laminated between them. It is understood that this multi-layered structure is applied for at least two reasons. One is that there is a scale problem when directly bonding a fine pattern of a device to a motherboard, and the other is that a problem of wiring damage may occur due to the difference in thermal expansion coefficient during the bonding process or the operation process of the semiconductor device. In the embodiment, this problem is solved by applying a glass core with a thermal expansion coefficient similar to that of a semiconductor device, and forming a fine pattern with a fine scale sufficient for mounting a device on the first surface of the glass core and its upper layer.

[0092] Hereinafter, a method for manufacturing a packaging substrate according to an embodiment of the present invention will be described.

[0093] 4 and 5 are flow charts illustrating a cross-sectional view of a manufacturing process of a packaging substrate according to an embodiment.

[0094] First, as shown in (a) of FIG. 4, a glass core 21a having flat first and second surfaces is prepared, and a defect (groove) 21b is formed on the glass surface at a predetermined position for forming a core via. The glass may be a glass core applied to a substrate of an electronic device, for example, but is not limited to, an alkali-free glass core. As a commercially available product, a product manufactured by a manufacturer such as Corning, Schott, or AGC may be applied. The defect (groove) may be formed by mechanical etching, laser irradiation, or other methods.

[0095] As shown in Fig. 4(b), the glass core 21a having the defect (groove) 21b undergoes an etching step to form a core via 23 through a physical or chemical etching process. In the etching process, the glass core forms a via at the defect, and the surface of the glass core 21a may also be etched at the same time. In order to prevent such etching of the glass surface, a masking film or the like may be applied, but in consideration of the troublesome process of applying and removing the masking film, the glass core having the defect itself may be etched, and in this case, the thickness of the glass core having the core via may be somewhat thinner than the thickness of the initial glass core.

[0096] Thereafter, a core layer manufacturing step may be performed by forming an electrically conductive layer 21d on the glass core as shown in Fig. 4(c) and (d). The electrically conductive layer may be a metal layer typically including, but not limited to, copper metal.

[0097] The adhesion between the glass surface (including the glass core surface and the core via surface) and the copper metal surface is poor due to their different properties. In the present embodiment, the adhesion between the glass surface and the metal can be improved by two methods, a dry method and a wet method.

[0098] The dry method is a method of applying sputtering, i.e., forming a seed layer 21c on the glass surface and the inner diameter of the core via by metal sputtering. In forming the seed layer, a different metal such as titanium, chromium, or nickel may be sputtered together with copper, etc., and in this case, the adhesion between the glass and the metal may be improved due to an anchor effect in which the surface morphology of the glass and the metal particles interact with each other.

[0099] The wet method is a method of performing a primer treatment, and is a method of forming a primer layer 21c by pretreating with a compound having a functional group such as an amine. Depending on the intended degree of adhesion, a primer treatment can be performed with a compound or particles having an amine functional group after pretreating with a silane coupling agent. As mentioned above, the support substrate of the embodiment needs to have high performance to be able to form a fine pattern, and this should be maintained even after the primer treatment. Therefore, when such a primer includes nanoparticles, it is preferable that nanoparticles having an average diameter of 150 nm or less are applied, and for example, it is preferable that nanoparticles are applied as particles having an amine group. The primer layer may be formed by applying an adhesion improver manufactured, for example, by MEC's ​​CZ series.

[0100] The seed layer / primer layer 21c may selectively form an electrically conductive layer or a metal layer with or without removing portions that do not require the formation of an electrically conductive layer. In addition, the seed layer / primer layer 21c may be selectively treated with portions that require or do not require the formation of an electrically conductive layer in an activated or inactivated state for metal plating, and the subsequent steps may be performed. For example, the activation or inactivation treatment may be a light irradiation treatment using a laser of a certain wavelength, a chemical treatment, or the like. The formation of the metal layer may be performed using a copper plating method or the like that is applied to the manufacture of semiconductor devices, but is not limited thereto.

[0101] As shown in (e) of Figure 4, a portion of the core distribution layer may be removed if unnecessary, or the seed layer may be partially removed or passivated, and then metal plating may be performed to form an electrically conductive layer in a predetermined pattern, thereby forming an etched layer 21e of the core distribution layer.

[0102] FIG. 5 illustrates a manufacturing step of forming an insulating layer and an upper distribution pattern according to one embodiment.

[0103] As shown in (a) of Fig. 5, the core via may undergo an insulating layer formation step in which an insulating layer is used to fill empty spaces after the formation of the core distribution layer, which is the electrically conductive layer. The insulating layer may be in the form of a film, and may be, for example, a method of vacuum laminating an insulating layer in the form of a film. When vacuum lamination is performed in this manner, the insulating layer is sufficiently filled into the empty spaces inside the core via, thereby forming a core insulating layer without the formation of voids.

[0104] 5(b)-(e) illustrate the top layer fabrication steps.

[0105] The upper layer manufacturing step is a step of forming an upper distribution layer including an upper insulating layer and an upper distribution pattern on the core layer. The upper insulating layer may be formed by coating a resin composition forming the insulating layer 23a or laminating an insulating film, and the method of laminating an insulating film is preferable for simplicity. The lamination of the insulating film may be performed by laminating and curing the insulating film, and if a reduced pressure lamination method is applied, the insulating resin may be sufficiently embedded even in layers in which no electrically conductive layer is formed inside the core via. The upper insulating layer also directly contacts the glass core at least partially, and therefore has sufficient adhesion. Specifically, the glass core and the upper insulating layer preferably have a characteristic that satisfies an adhesion test value of 4B or more according to ASTM D3359.

[0106] The upper distribution pattern may be formed by repeating the process of forming the insulating layer 23a, forming the electrically conductive layer 23c in a predetermined pattern, and etching unnecessary portions to form an etched layer 23d of the electrically conductive layer, and in the case of electrically conductive layers formed adjacent to each other with an insulating layer in between, the upper distribution pattern may be formed by forming blind vias 23b in the insulating layer and then performing a plating process. The blind vias may be formed by dry etching such as laser etching or plasma etching, or wet etching using a masking layer and an etchant.

[0107] Thereafter, a top connection layer and a cover layer may be formed, not shown.

[0108] The upper connection pattern and the upper connection electrodes may also be formed by a process similar to that for forming the upper distribution layer. Specifically, they may be formed by forming an etching layer of the insulating layer on the insulating layer 23e, forming an electrically conductive layer thereon again, and then forming an etching layer of the electrically conductive layer, or by selectively forming only the electrically conductive layer without applying an etching method. The cover layer may be formed by forming openings (not shown) at positions corresponding to the upper connection electrodes to expose the upper connection electrodes and to allow direct connection to the element connection parts or terminals of the elements.

[0109] After the upper layer is formed, a process of forming a lower connection layer and a cover layer to form a lower layer can be performed. In a similar manner to the above-mentioned upper connection layer and cover layer formation steps, a lower distribution layer and / or a lower connection layer, and optionally a cover layer (not shown) can be formed.

[0110] FIG. 6 is a diagram for explaining the warping phenomenon that occurs in a substrate when an insulating layer is formed in a conventional manner.

[0111] Electronic elements can be formed so as to be inserted into the insulating layer. This is called the embedding process, and if a thick insulating film, such as ABF (Ajinomoto Build-up Film), is used to fill the space remaining after the electronic elements in the cavity are placed, i.e., the cavity area, all at once, asymmetric shrinkage may occur on one side of the substrate after curing, as shown in Figure 6.

[0112] The step of curing the insulating layer may include a pre-cure step of preliminarily curing the insulating film without completely curing it, and an additional curing step of completely curing the insulating film.

[0113] During pre-curing, a large shrinkage force can occur in a specific direction due to chemical reactions between insulating films such as ABF and components in the insulating film, deviations in the CTE (coefficient of thermal expansion) of the glass core, residual thermal stress, etc., and the stress generated at this time can cause warpage.

[0114] As shown in Figure 6, warping in the direction of the insulating film can cause the glass core to bulge, resulting in defects in the packaging substrate. As described below, the manufacturing process of the packaging substrate is as follows. After fixing the position of the electronic element in the through-hole cavity with an adhesive film, an insulating film is placed on the surface opposite the adhesive film. Then, pre-curing is performed along with reduced pressure lamination, and the adhesive film is removed to prepare for the next step. At this time, residual stress in the insulating layer can easily cause a shrinkage force in the insulating layer, which is thought to cause warping in the glass core for various reasons, including this.

[0115] In this case, the device disposed in the cavity region may be dislodged, moved, or separated from its original position. Also, in the case of pre-curing, the insulating film is not completely hardened, so separation of the device may occur relatively easily.

[0116] Warpage can be measured by placing the packaging substrate (or glass core) on a flat floor and measuring the height of the corner of the packaging substrate (or glass core) from the floor on which the packaging substrate is placed. As shown in Figure 6, there was a case where one corner of the packaging substrate (or glass core) was approximately 20 mm, or 2 cm, away from the floor due to shrinkage caused by pre-curing. This can act as a fatal defect in the production of packaging substrates.

[0117] In the packaging substrate of the embodiment, the height at which the corners are spaced apart may be 12 mm or less, which is superior to the existing example of FIG.

[0118] When the packaging substrate of the embodiment is placed on a flat floor, the height at which the corners of the packaging substrate are spaced from the floor on which the packaging substrate is placed may be 10 mm or less, 8 mm or less, 6 mm or less, or 4 mm or less. The height may be 0 mm or more, or 1 mm or more. Since the packaging substrate has a relatively small degree of warping, a stable manufacturing process of the packaging substrate can be performed and the defective rate can be reduced.

[0119] The corner separation height is measured by placing the packaging substrate on a flat floor and measuring the height of the corners separated from the floor without applying any external force. For example, in the case of a rectangular packaging substrate, the highest value among the four corners is taken as the corner separation height.

[0120] Therefore, according to an embodiment of the present invention, it is proposed to perform the pre-curing process of the insulating film not once but multiple times.

[0121] FIG. 7 is a cross-sectional view illustrating a concept of a method for manufacturing a packaging substrate according to an embodiment.

[0122] The packaging substrate in FIG. 7 is a conceptually simplified diagram for explaining the formation of an insulating layer, and the contents described with reference to FIGS. 1 to 3 can be applied thereto.

[0123] 7 is formed through both the first and second surfaces of the glass core 21, and an electronic element 40 is disposed inside the cavity 29. The cavity 29 may be formed simultaneously through the same formation step as the core via, or may be formed independently after or before the core via is formed.

[0124] 7, the cavity portion 29 may be formed in the form of a recessed surface in which only one of the first surface and the second surface is open. In this case, the cavity portion 29 may be formed simultaneously through the same formation step as the core via, or may be formed independently after or before the core via is formed.

[0125] As discussed above, the electronic elements 40 may include passive and / or active elements.

[0126] As shown in FIG. 7, a relatively thin insulating film is used instead of the existing thick insulating film to fill the core via and cavity portion 29 of the glass core 21 that constitutes the core layer, and the insulating layer can be produced on at least one surface of the glass core through two or more processes.

[0127] That is, the insulating film is laminated in two or more steps and pre-cured after each lamination, thereby minimizing warpage and substantially preventing the electronic device from coming off the substrate.

[0128] Specifically, the first insulating film 61 can be laminated from the first surface to the second surface (including the case where vacuum lamination is applied to fill the space of the hole or cavity with the components of the insulating film) and cured, thereby producing the first insulating layer.

[0129] Thereafter, a second insulating film 63 may be laminated on the first insulating layer to form a hardened second insulating layer. At the same time or in a separate process, a third insulating film 64 may be laminated from the second surface to the first surface to form a hardened third insulating layer.

[0130] That is, a first insulating layer is formed through lamination of a first insulating film and a first curing step (pre-cure), and a second insulating layer is formed on the top of the glass core (top of the first insulating layer) through lamination of a second insulating film and a second curing step (pre-cure).

[0131] In addition, the lamination in the second curing step can be performed not only on the top of the glass core (top of the first insulating layer) but also on the bottom of the glass core (second surface) by laminating the third insulating film and performing the second curing step (pre-cure), thereby simultaneously forming the second insulating layer and the third insulating layer. In this case, the third insulating film may be the same as the second insulating film. In addition, in this case, since curing is performed simultaneously on both sides of the glass core, the occurrence of stress can be dispersed, which may be more advantageous in suppressing the occurrence of warping.

[0132] In this way, through the two-stage pre-curing treatment, it is possible to stably form an insulating layer inside the core via and the cavity portion 29, while improving or substantially improving the warpage phenomenon of the board.

[0133] FIG. 8 is a flowchart illustrating a process for manufacturing a packaging substrate according to an embodiment in cross section.

[0134] The step of forming an insulating layer on a packaging substrate will be described in more detail with reference to FIG.

[0135] First, as shown in FIG. 8(a), the glass core 21 is attached to an adhesive film 80 such as a PI tape (Polyimide Tape), and the electronic element 40 is selected and placed in the cavity portion 29 (position of the electronic element is specified).

[0136] Then, as shown in (b), a first lamination on top process may be performed on the first surface. When a first insulating film 61 is laminated over the entire first surface of the glass core 21 and a first pre-cure process is performed, the first insulating layer may fill the internal space of the cavity portion 29 with an insulator as shown in (c).

[0137] If necessary, the adhesive film 80 may be removed during a subsequent process. Exemplarily, the adhesive film 80 may be an adhesive film whose adhesive strength can be reduced by ultraviolet irradiation, etc. The adhesive film 80 can be easily removed from the glass core by reducing the adhesive strength of the adhesive film by irradiating the adhesive film with ultraviolet light directly or through the glass core.

[0138] In addition, the electronic element 40 can be fixed in position by the first insulating layer that has been pre-cured by the primary curing, and if the degree of warping is controlled below a certain level, subsequent processes can be applied without fixing the adhesive film 80.

[0139] Once the first insulating layer is produced, as shown in (c), a second pre-cure step may be performed in which a second insulating film 63 and / or a third insulating film 64 are laminated on the first cured first insulating film 61 and / or the second surface, respectively, and then pre-cured (2nd lamination on top & bottom).

[0140] When the secondary curing is completed, an insulating layer may be generated that is divided by the boundary between the insulating films, as shown in (d). In other words, the insulating layer may include a first insulating layer in which a first insulating film 61 is laminated and cured from the first surface to the second surface, and a second insulating layer in which a second insulating film 63 is laminated and cured on the first insulating layer. Optionally, the insulating layer may further include a third insulating layer in which a third insulating film 64 is laminated and cured from the second surface to the first surface. Between the first insulating layer and the second insulating layer, a predicted boundary 1 (L1) where the first insulating film 61 and the second insulating film 63 contact each other may be formed, and between the first insulating layer and the third insulating layer, a predicted boundary 2 (L2) where the first insulating film 61 and the third insulating film 64 contact each other may be formed.

[0141] For example, the thickness of the first insulating film 61 to which the primary curing is applied and the thickness of the second insulating film 63 to which the secondary curing is applied may be different from each other.

[0142] The first insulating film 61 and the second insulating film 63 may be applied in a thickness ratio of 1:0.5 to 2, or a thickness ratio of 1:0.6 to 1.5. For example, when the total thickness of the first insulating film 61 and the second insulating film 63 is 80 μm, the thickness ratio of the first insulating film 61 / the second insulating film 63 may be in a range of 30 / 50, 50 / 30, or 40 / 40, and when the total thickness of the first insulating film 61 and the second insulating film 63 is 60 μm, the thickness ratio of the first insulating film 61 / the second insulating film 63 may be in a range of 30 / 30, 20 / 40, or 40 / 20. Or, when the total thickness of the first insulating film 61 and the second insulating film 63 is 30 μm, the thickness ratio of the first insulating film 61 / the second insulating film may be in a range of 15 / 15, 10 / 20, or 20 / 10.

[0143] Of course, the pre-curing step may be performed more than twice. Depending on the size of the cavity portion 29 and the height of the glass core 21, the thickness of the insulating film and the number of curing steps can be optimally set.

[0144] Insulating films such as ABF may be cured by applying heat.

[0145] Specifically, the insulating film may be pre-cured by a thermal curing method after inducing some of the components of the insulating film to be disposed inside the vias, cavities, etc., by a reduced pressure lamination method. In this case, pre-curing means that the insulating film is cured to an intermediate stage rather than a completely cured state, and can be controlled by adjusting the curing temperature, etc.

[0146] The temperature and pressure during the first curing step are not the same as those during the second curing step, and the pressure and temperature applied during the second curing step are higher than those applied during the first curing step.

[0147] The primary curing step may be carried out at a primary curing temperature of 60°C to 145°C.

[0148] The primary curing temperature may be 60° C. or more, or 65° C. or more. The primary curing temperature may be 145° C. or less, 140° C. or less, 130° C. or less, 120° C. or less, 110° C. or less, 100° C. or less, or 90° C. or less. In this case, the insulating layer may not be completely cured, but may be cured to a pre-cured level.

[0149] The first curing step is 15kgf / cm 2 Below, 12kgf / cm 2 or less than 10kgf / cm 2 The vacuum may be 2 kgf / cm. 2 or more than 5kgf / cm 2 It may be more than that.

[0150] The secondary curing step may be carried out at a secondary curing temperature of 120°C to 180°C.

[0151] The secondary curing temperature may be 120° C. or more, 130° C. or more, 140° C. or more, 150° C. or more, or 160° C. or more. The secondary curing temperature may be 180° C. or less, 170° C. or less, or 165° C. or less. In this case, the insulating layer may not be completely cured, but may be cured to a pre-cured level.

[0152] Secondary curing step is 22kgf / cm 2 Below 20kgf / cm 2 or less than 18kgf / cm 2 The pressure reduction may be performed under the following reduced pressure conditions: 2 or more, or 13kgf / cm 2 It may be more than that.

[0153] The curing temperature of the first curing step may be applied at a higher temperature than the curing temperature of the second curing step.

[0154] The temperature rise to the first curing temperature may be performed for 20 to 120 minutes, or may be performed for 20 to 80 minutes. The first curing temperature may be maintained for 20 to 120 minutes, or may be maintained for 20 to 80 minutes.

[0155] The temperature rise to the secondary curing temperature may be performed for 20 to 100 minutes, or may be performed for 20 to 80 minutes. The secondary curing temperature may be maintained for 20 to 100 minutes, or may be maintained for 20 to 80 minutes.

[0156] When curing is carried out under such temperature and pressure conditions, respectively, an insulating layer can be obtained that is pre-cured or cured to the intended level.

[0157] After a pre-cure step such as a first cure and / or a second cure is performed, a final cure step may be further performed to completely cure the insulating film. Between the pre-cure and cure steps, a step of planarizing the surface of the substrate may be performed. That is, the top surface of the insulating layer may be induced to be planarized. For example, a method of placing a planarizing film (e.g., a PET film) on the insulating layer during the reduced pressure lamination process may be used. However, the planarization method is not limited thereto.

[0158] According to one example, such planarization may be performed between the first and second cures described above.

[0159] On the other hand, it will be apparent to those skilled in the art that the pre-curing step of the insulating film described with reference to FIG. 8 can also be applied to a cavity portion that opens in one of the directions of the first surface and the second surface of the glass core 21.

[0160] 9A and 9B are microscopic photographs of the boundaries of insulating layers produced by manufacturing a packaging substrate according to an embodiment.

[0161] 8, an insulating layer as shown in Fig. 9A or 9B is formed. That is, a first boundary L1 where the first insulating film 61 and the second insulating film 63 contact each other is formed between the first insulating layer and the second insulating layer, and a second boundary L2 where the first insulating film 61 and the third insulating film 64 contact each other is formed between the first insulating layer and the third insulating layer.

[0162] 9B shows a second boundary (a line between two types of materials) formed between the first and third insulating layers inside the cavity portion 29. Such a boundary indicates that the insulating layers are produced through multiple curing steps rather than a single curing step, and the boundary can be observed due to the different temperatures and pressures applied during curing.

[0163] Exemplarily, the boundary may be observed as a line of color difference.

[0164] For example, the boundary may be observed as a band shape in which the color has a relatively constant thickness (for example, a color change like a gradation). For example, the constant interval may be 2 μm to 30 μm, or 3 μm to 10 μm.

[0165] Also, at the boundary, the color of the insulating layers, for example the color of the first insulating layer and the color of the third insulating layer, may be differentiated from each other.

[0166] As shown in FIGS. 9A and 9B, the thickness of the first insulating film 61 may be 60 μm, 70 μm, or 80 μm, and the position where the second boundary is formed may vary depending on the thickness of the first insulating film 61.

[0167] FIG. 10 is a photograph for explaining warpage of a packaging substrate produced by manufacturing a packaging substrate according to an embodiment.

[0168] As mentioned above, warpage can be measured as the average distance between the corners of the glass core and the packaging substrate or floor on which the glass core is placed, and FIG. 10 shows warpage when a curing process for an insulating film is performed in multiple stages according to an embodiment of the present invention.

[0169] The glass core may have a rectangular shape (in one embodiment, the horizontal and vertical lengths of the glass core are about 53 cm) and, in one example, the thickness may be 400 μm to 600 μm. When the insulating film is cured in multiple steps on the glass core under such conditions, one apex of the glass core is spaced from the floor by less than 0.1 mm, as shown in FIG.

[0170] When comparing this type of warpage with that shown in Figure 6, the degree of improvement is very large, and it can be evaluated that warpage has almost disappeared.

[0171] FIG. 11 is a flowchart illustrating a manufacturing process of a packaging substrate according to another embodiment.

[0172] As shown in the figure, the cavity portion 29 in FIG. 11 also has a structure penetrating the first surface and the second surface of the glass core 21, and for example, a capacitor 41 is disposed as an electronic element.

[0173] As described above, in addition to passive elements such as the capacitor 41, active elements may also be disposed in the cavity portion 29 as electronic elements.

[0174] As shown in FIG. 11( a ), a glass core 21 is attached to an adhesive film 80 such as a PI tape, and an electronic element such as a capacitor 41 is disposed in the cavity portion 29 .

[0175] According to this embodiment, the first insulating film may be laminated and cured not on the entire first surface, but only on the cavity portion 29 in which the capacitor 41 is disposed or on a region including the cavity portion 29.

[0176] 11, the first insulating layer 61a formed on the packaging substrate is not formed on the entire upper surface of the glass core 21, but is formed to fill all or part of the vacant space of the core via and / or cavity portion 29. In this case, the first insulating layer 61a can function as an insulating layer surrounding an electronic element such as a capacitor 41.

[0177] In this case, the first insulating film may be cut based on the shape and size of the cavity portion 29, and may be laminated on the upper portion of the cavity portion 29. Exemplarily, the shape of the cut first insulating film may be substantially the same as or similar to the shape of the cavity portion 29 when viewed from above.

[0178] The size (area) of the first insulating film may be adjusted to be larger or smaller depending on the volume of the insulating layer to be embedded in the cavity portion 29, the thickness of the insulating layer, etc. For example, the size of the first insulating film may be slightly smaller than the shape of the opening of the cavity portion 29, and the thickness of the first insulating film may be smaller than the thickness of the cavity portion 29.

[0179] This allows a sufficient amount of insulating material to be embedded in the cavity while minimizing the formation of unnecessary insulating portions in areas other than the cavity portion 29. In addition, it is possible to minimize the occurrence of surface undulation that may occur between electronic elements and / or between the electronic element and the cavity, thereby obtaining a substantially flat surface of the insulating layer.

[0180] As described above, the step of forming the insulating layer may be performed at different times depending on the thickness of the glass core 21, the thickness of the insulating film, or the size and properties of the electronic device. In addition, the area of ​​the insulating layer to be subjected to the first curing may be modified into various structures depending on the arrangement of the cavities 29, the size and properties of the electronic device.

[0181] After the first insulating layer 61a is formed, as shown in FIG. 8(c), a second insulating film may be laminated over the entire first and second surfaces of the glass core 21, and a secondary curing may be performed.

[0182] After the secondary curing, as shown in FIG. 11(c), a second insulating layer 63a may be formed to completely surround the glass core 21 and the first insulating layer 61a.

[0183] FIG. 12 is a schematic cross-sectional view illustrating a structure of a packaging substrate according to another embodiment.

[0184] As shown in the figure, the packaging substrate may include a glass structure having a structure of a glass core 21, a core via 23, a cavity portion 29, and an electronic element 40 disposed in the cavity portion 29, i.e., a core layer, an upper layer 26 located on the upper part of the core layer, and a lower layer 38 located on the lower part of the core layer. A cover layer 60 is formed on the upper layer 26 and the lower layer 38. The number of electronic elements 40 is not specified, and is shown as two in this embodiment.

[0185] A core distribution pattern 241, which is an electrically conductive layer that electrically connects the first and second surfaces of the glass core 21, is formed on the surfaces of the core via 23 and the cavity portion 29. In addition, an element electrically conductive layer 42 for electrically connecting the electronic element 40 and the upper distribution pattern 251 of the upper layer 26 is formed on a part of the upper surface, the side surface, and a part of the lower surface of the electronic element 40.

[0186] Meanwhile, as shown in the figure, the first insulating layer 61a fills the space between the two electronic elements 40 and the internal space of the cavity. The packaging substrate of Fig. 12 is formed only in a limited area capable of covering the cavity, not on the entire first surface of the glass core 21, as in the first insulating layer described with reference to Fig. 11. Also, the first insulating layer 61a is not laminated on the top surface of the cavity 29, but can fill the empty space on the side of the cavity 29, i.e., the area where the electronic elements 40 are arranged.

[0187] According to one embodiment, the electronic device 40 may be a capacitor, and when the capacitor is disposed in the cavity portion 29 penetrating the glass core 21, one side of the capacitor, either the top or bottom, rather than both sides, may be connected to the upper distribution pattern 251. That is, the two electrodes 42a and 42b of the capacitor are electrically connected to the upper distribution pattern 251 formed on the upper layer 26 as shown in Fig. 12, and current flows into the first electrode 42a and out through the second electrode 42b. The electrodes 42a and 42b may be formed as part of the device's electrical conductive layer 42, or may be formed in stages through a separate lamination process.

[0188] Of course, the two electrodes 42a, 42b of the capacitor may be formed toward the second surface, which is the lower surface, of the glass core 21, rather than the first surface, which is the upper surface.

[0189] After the device electrical conductive layer 42 is formed on the electronic device 40 and the first insulating layer 61a surrounding it is formed, the second insulating layer 63a may be formed on the first insulating layer 61a and the upper and lower parts of the glass core 21. That is, instead of filling the cavity area at once as in the past, a relatively thin insulating film may be used to fill the cavity portion 29 instead of the existing thick insulating film, and an insulating layer may be formed on at least one surface of the glass core through two or more steps. That is, the insulating film may be laminated in two or more steps, and pre-curing may be performed after each lamination. This may minimize warpage and prevent the electronic device from coming off the substrate.

[0190] An upper layer 26 is formed on the upper part of the second insulating layer 63a formed on the first surface. The upper layer 26 may include an upper insulating layer 253 and an upper distribution pattern 251 having a predetermined pattern, which is an electrically conductive layer having at least a part electrically connected to the core distribution pattern 241 and the two electrodes 42a, 42b of the element electrical conductive layer 42 and is embedded in the upper insulating layer 253.

[0191] The second insulating layer 63a and the upper insulating layer 253 may be made of the same insulating material, and in this case, the boundary between them may be difficult to distinguish in cross section. Alternatively, in another embodiment, the boundary between the insulating layers may be relatively easily distinguished in cross section by setting different pressures and temperatures for curing the multiple insulating layers.

[0192] The second insulating layer 63a and the upper insulating layer 253 may be formed of different insulating materials, and in this case, the boundary therebetween may be more easily distinguished.

[0193] Also, as described above, the upper distribution pattern 251 refers to an electrically conductive layer located in the upper insulating layer 253 in a predetermined shape, and may be formed, for example, by a build-up layer method. The packaging substrate manufacturing method according to the embodiment described above and the packaging substrate using the same may improve the warping phenomenon caused by the difference in the degree of thermal expansion of the elements of the substrate, and may prevent the separation or detachment of the electronic elements.

[0194] The present invention described above has been described with reference to the embodiments shown in the drawings, but these are merely illustrative, and a person having ordinary skill in the art will understand that various modifications and variations of the embodiments are possible. That is, the scope of the present invention is not limited to the above-mentioned embodiments, and various modifications and improvements made by those skilled in the art using the basic concept of the embodiments defined in the accompanying claims also belong to the scope of the embodiments. Therefore, the true technical scope of protection of the present invention must be determined by the technical ideas of the accompanying claims. [Explanation of symbols]

[0195] 100 Semiconductor device 10 Motherboard 30 Semiconductor Device Section 32 First semiconductor element 34 Second semiconductor element 36 Third semiconductor element 20 Packaging Substrate 21,21a Glass core 22 Core Layer 223 Core insulation layer 213 Page 1 214 2nd page 23 Corebia 24 Core Distribution Layer 241 Core Distribution Pattern 26 Upper layer 25 Upper distribution layer 251 Upper distribution pattern 23b Blind Via 253 Upper insulating layer 27 Top connection layer 271 Top connection electrode 272 Top connection pattern 28 Cavity 281 Interior Space 282 Cavity Distribution Layer 40 Electronic Elements 50 Connection 51 Element connection part 52 Board connection 60 Cover Layer

Claims

1. A method for manufacturing a packaging substrate, comprising: creating a glass structure, the glass structure being a core via, a cavity, or both, in a glass core having opposing first and second surfaces; forming an insulating layer on the first surface or the second surface using an insulating film; forming an upper layer on top of the insulating layer, the upper layer including an upper distribution layer and an upper surface connection layer; The step of forming the insulating layer includes: a primary curing step of laminating a first insulating film on the first surface and then performing a primary curing; and laminating a second insulating film on the first cured first insulating film and then performing a second curing step.

2. the cavity portion is recessed to open toward the first surface or the second surface of the glass core, or has a space penetrating the first surface and the second surface in which an electronic element is disposed, The method for manufacturing the packaging substrate further includes arranging the electronic elements in the cavity portion, the step of arranging the electronic elements is performed between the step of producing the glass structure and the step of producing an insulating layer; The method of claim 1 , wherein the first insulating film is laminated on the entire first surface or on the cavity portion in which the electronic elements are arranged.

3. The method of claim 2 , wherein when the first insulating film is laminated in the cavity portion, the first insulating film is cut based on a shape and a size of the cavity portion.

4. The method of claim 1 , wherein the first insulating film and the second insulating film have different thicknesses.

5. The first curing step and the second curing step are each performed using a reduced pressure lamination method, The method of claim 1 , wherein the pressure and temperature applied in the second curing step are higher than the pressure and temperature applied in the first curing step.

6. The method for manufacturing a packaging substrate further includes a final curing step after the secondary curing step, The method of claim 1 , wherein the final curing step is a step of further curing the first insulating film and the second insulating film.

7. The method for manufacturing a packaging substrate according to claim 1 , wherein the electronic elements include passive elements or active elements.

8. A packaging substrate, The packaging substrate includes: A core layer; an upper layer positioned on the core layer; The core layer is a glass core including a first surface and a second surface opposed to each other; a plurality of core vias and cavities penetrating the glass core in a thickness direction; an electrically conductive layer disposed on a surface of the glass core; Electronic elements arranged in the cavity portion; an insulating layer filling the core via and the cavity portion; The cavity portion is recessed and opens toward the first surface or the second surface of the glass core, or has a space penetrating the first surface and the second surface, A packaging substrate, wherein the insulating layer includes a first insulating layer formed by laminating a first insulating film on the first surface and curing the first insulating layer, and a second insulating layer formed by laminating a second insulating film on the first insulating layer and curing the second insulating layer.

9. The packaging substrate according to claim 8 , wherein the first insulating layer is formed on the entire first surface or in the cavity portion in which the electronic elements are arranged.

10. The packaging substrate according to claim 8 , wherein the insulating layer further comprises a third insulating layer formed by laminating and curing a third insulating film on the second surface.

11. a first boundary where the first insulating film and the second insulating film are in contact with each other is formed between the first insulating layer and the second insulating layer; a second boundary where the first insulating film and the third insulating film are in contact with each other is formed between the first insulating layer and the third insulating layer; The packaging substrate according to claim 10 , wherein the second boundary is formed inside the core via and the cavity portion.

12. The packaging substrate of claim 8 , wherein the first insulating layer and the third insulating layer have different colors.

13. The packaging substrate of claim 8 , wherein the first insulating layer and the second insulating layer have different thicknesses.

14. The glass core is rectangular and has a thickness of 300 μm to 1,500 μm; The packaging substrate according to claim 8 , wherein a height at which a corner of the packaging substrate is spaced from a floor on which the packaging substrate is placed is 12 mm or less.

15. The packaging substrate of claim 8 , wherein the electronic element comprises a passive element or an active element.

Images