Packaging substrate and method of manufacturing the same

Abstract

To provide: a glass substrate that reduces undulation that may occur when various types of elements are mounted; a packaging substrate where a large number of elements are mounted on the glass substrate; and a manufacturing method of the packaging substrate.SOLUTION: In a semiconductor device, a packaging substrate 20 includes a core layer 22, which includes: a glass substrate 21 including a first surface 213 and a second surface 214 facing each other; and a plurality of cavity portions 28 that open toward the first surface or the second surface and have different depths. Accordingly, a packaging substrate can reduce undulation that may occur when active elements such as a transistor, or power transfer elements such as a multilayer ceramic capacitor (MLCC), that are various types of cavity elements including passive elements are mounted.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present embodiment relates to a packaging substrate and a method for manufacturing the same, and more particularly to a packaging substrate including a glass substrate and a method for manufacturing the same. [Background technology]

[0002] In manufacturing electronic components, the process of creating circuits on a semiconductor wafer is called the front-end process (FE: Front-End), and the process of assembling the wafer so that it can be used in an actual product is called the back-end process (BE: Back-End), which includes the packaging process.

[0003] The four core technologies of the semiconductor industry that have enabled the recent rapid development of electronic products are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. Semiconductor technology has evolved into various forms, such as nano-level line widths below the micron level, over 10 million cells, high-speed operation, and large amounts of heat dissipation, but the technology to perfectly package these has not been supported. As a result, the electrical performance of semiconductors is sometimes determined by the packaging technology and the resulting electrical connections, rather than the performance of the semiconductor technology itself.

[0004] Ceramic or resin is currently used as a material for packaging substrates. Recently, however, research has been conducted into the application of silicon or glass to high-end packaging substrates. In particular, a packaging substrate having a cavity structure has been developed by applying a glass substrate.

[0005] Meanwhile, Re-Distribution Layer (RDL) is a packaging process that refers to a technology that changes the position of electrical terminals (ex: Aluminum Pad) that have already been formed using Wafer Level Package (WLP) process technology to any position. This RDL is used as a method to resolve design limitations in semiconductor manufacturing factories through packaging, that is, it is used for stacking semiconductor chips.

[0006] Related prior art includes U.S. Patent Publication US2023 / 0162992A1 and Korean Patent Publication No. 10-2014-0082305. Summary of the Invention [Problem to be solved by the invention]

[0007] An object of the embodiment is to provide a packaging substrate that reduces undulation that occurs when mounting various types of devices on a glass substrate and a packaging substrate that mounts a number of devices on the glass substrate, and a manufacturing method thereof.

[0008] Also, an object of the embodiment is to provide a packaging substrate in which cavities of various depths are arranged to accommodate designs of devices having various heights, and a manufacturing method thereof.

[0009] It is also an object of the embodiment to be able to form a planar insulating layer on a glass substrate and a planar top layer on top of the insulating layer. [Means for solving the problem]

[0010] In order to achieve the above object, a packaging substrate according to one embodiment includes a core layer, the core layer including a glass substrate having a first surface and a second surface facing each other; and at least two or more cavity portions each having an opening that opens toward the first surface or the second surface.

[0011] The two or more cavities have different depths.

[0012] The packaging substrate may include: a cavity element including two or more individual elements arranged in the cavity portion and having different heights; and an insulating layer embedded inside the cavity portion and disposed on a surface of the glass substrate on which the opening is formed.

[0013] The cavity portion may include a first cavity portion recessed to open toward the first surface and having a first depth, and a second cavity portion recessed to open toward the first surface or toward the second surface and having a second depth, the second depth being greater than the first depth.

[0014] In this case, the cavity elements may include: a first cavity element arranged in the first cavity portion; and a second cavity element arranged in the second cavity portion.

[0015] One or more connecting electrodes may be disposed on the first cavity element and one or more connecting electrodes may be disposed on the second cavity element.

[0016] According to another example, the cavity portion includes a first cavity portion recessed to open toward the first surface and having a first depth, a second cavity portion recessed to open toward the first surface or toward the second surface and having a second depth, and a third cavity portion having a third depth penetrating the first surface and the second surface. The second depth may be greater than the first depth.

[0017] A first cavity element may be arranged in the first cavity portion, a second cavity element may be arranged in the second cavity portion, and a third cavity element may be arranged in the third cavity portion.

[0018] One or more connecting electrodes may be disposed on the first cavity element, one or more connecting electrodes may be disposed on the second cavity element, and one or more connecting electrodes may be disposed on the third cavity element towards the first face or towards the second face.

[0019] One or more connecting electrodes may further be arranged on said third cavity element between them in the direction of said second face.

[0020] One or more connecting electrodes may be disposed on the third cavity element towards both the first and second faces respectively.

[0021] To achieve the above object, a manufacturing method of a packaging substrate according to one embodiment may include: a defect forming step of providing a glass substrate having a first surface and a second surface facing each other, and forming a plurality of defects to different degrees on the first surface or the second surface; and a cavity forming step of etching the glass substrate to form at least two or more cavity portions having different depths.

[0022] The method for manufacturing the packaging substrate may further include an arrangement step and an insulating layer formation step after the cavity formation step.

[0023] The arranging step is a step of arranging cavity elements in the cavity portion.

[0024] The insulating layer forming step is a step of forming an insulating layer on a surface on which an opening of the cavity portion is formed.

[0025] The cavity elements disposed in the cavity portion may have different heights.

[0026] The cavity portion includes a first cavity portion and a second cavity portion, the first cavity portion being recessed and opening toward the first surface and having a first depth, and the second cavity portion being recessed and opening toward the first surface or the second surface and having a second depth deeper than the first depth.

[0027] The cavity elements include a first cavity element and a second cavity element, the first cavity element being arranged in the first cavity portion and the second cavity element being arranged in the second cavity portion.

[0028] The method for manufacturing the packaging substrate may further include a step of forming a connection electrode.

[0029] The connection electrode forming step may be a step of forming one or more connection electrodes connected to the first cavity element and one or more connection electrodes connected to the second cavity element.

[0030] According to another example, the cavity portion may include a first cavity portion, a second cavity portion, and a third cavity portion.

[0031] The first cavity portion is recessed to open toward the first surface and has a first depth.

[0032] The second cavity portion is recessed to open toward the first surface or the second surface, and has a second depth deeper than the first depth.

[0033] The third cavity portion extends through the first surface and the second surface and has a third depth.

[0034] The cavity elements may include a first cavity element, a second cavity element, and a third cavity element.

[0035] The first cavity element may be arranged in the first cavity portion.

[0036] The second cavity element may be arranged in the second cavity portion.

[0037] The third cavity element may be arranged in the third cavity portion.

[0038] The method for manufacturing the packaging substrate may further include a step of forming a connection electrode.

[0039] The connection electrode forming step may be a step of forming one or more connection electrodes connected to the first cavity element; one or more connection electrodes connected to the second cavity element; and one or more connection electrodes connected to the third cavity element.

[0040] The connection electrode forming step can further include forming connection electrodes on two or more surfaces of the third cavity element, respectively. Effect of the Invention

[0041] The packaging substrate and manufacturing method thereof according to the embodiment may reduce undulation that may occur when mounting various types of devices.

[0042] Embodiments may provide a packaging substrate having a core layer with an overall flat surface while mounting elements having various heights within a glass substrate.

[0043] In an embodiment, due to the structural features of the cavity portion having various heights, the surface of the core layer can be substantially flat, and by utilizing this, a packaging substrate having a substantially flat insulating layer and / or upper layer formed thereon can be provided. [Brief description of the drawings]

[0044] The above and other objects, features and advantages of the present disclosure will become more apparent to those of ordinary skill in the art from the detailed description of illustrative embodiments thereof, taken in conjunction with the accompanying drawings. [Figure 1] 1 is a conceptual diagram illustrating a cross-sectional structure of a packaging substrate according to an embodiment; [Diagram 2] 13 is a conceptual diagram illustrating a cross-sectional structure of a packaging substrate according to another embodiment; FIG. [Diagram 3] 1A and 1B are schematic cross-sectional views illustrating a portion of a packaging substrate according to an embodiment. [Figure 4] 1 is a flowchart illustrating a process of forming a core distribution layer in a process of manufacturing a packaging substrate according to an embodiment. [Diagram 5] 1 is a flowchart illustrating a process of forming an insulating layer in a process of manufacturing a packaging substrate according to an embodiment. [Figure 6] 1A to 1C are cross-sectional views illustrating a portion of a packaging substrate according to an embodiment. [Figure 7] 13A to 13C are cross-sectional views illustrating a portion of a packaging substrate according to another embodiment. [Figure 8] 1 is a flowchart illustrating a process for manufacturing a packaging substrate according to an embodiment in cross-section, in which S1 is a defect forming step, S2 is a cavity forming step, S3 is an arrangement step, S4 is an insulating layer forming step, and S5 is a connection electrode forming step. BEST MODE FOR CARRYING OUT THEINVENTION

[0045] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily understand the embodiments. However, the embodiments may be embodied in many different forms and are not limited to the embodiments described herein. The same reference numerals are used throughout the specification to refer to similar parts.

[0046] Throughout this specification, the term "combinations thereof" in a Markush form phrase is intended to mean a mixture or combination of one or more selected from the group of elements set forth in the Markush form phrase, including one or more selected from the group of elements.

[0047] Throughout this specification, terms such as "first," "second," or "A," "B" are used to distinguish identical terms from one another, and singular expressions include plural expressions unless the context clearly indicates otherwise.

[0048] In this specification, the term "-" may mean that the compound includes a compound that corresponds to "-" or a derivative of "-".

[0049] In this specification, the term "B is located on A" means that B is located on A in direct contact therewith, or that B is located on A with another layer located therebetween, and is not to be interpreted as being limited to B being located in contact with the surface of A.

[0050] In this specification, the expression "B is linked to A" means that A and B are directly linked, or that A and B are linked via another component between them, and unless otherwise specified, it is not to be interpreted as being limited to A and B being directly linked.

[0051] In this specification, the term "singular" is to be construed as including the singular or plural as the context requires, unless otherwise specified.

[0052] The inventors recognized that in the process of developing a semiconductor device that can achieve high performance with a more integrated and thinner thickness, not only the element itself but also the packaging portion is an important factor in improving performance. As a result of their research, they discovered that unlike conventional interposers and organic substrates, which use two or more layers of cores on a motherboard as a packaging substrate, it is possible to make the packaging substrate thinner and help improve the electrical characteristics of the semiconductor device by applying a single layer of glass core and applying a cavity structure.

[0053] Elements performing various functions can be mounted in a cavity structure of a glass substrate, and thus the overall thickness of the packaging substrate can be further reduced. Elements mounted in the cavity structure have different sizes and thicknesses (heights) depending on their types. Therefore, when applied to the same cavity structure, undulation, i.e., defects in the form of waves with undulation or highs and lows, may occur due to differences in the height of the elements. Such undulation may affect the thinning and weighting of the packaging substrate, and may also weaken the electrical characteristics.

[0054] As a result of further research, the inventors discovered that when forming a cavity structure for mounting elements on a glass substrate, the degree of etching can be adjusted taking into account the height (thickness) or size of the element, thereby improving undulations, and thus completed the invention.

[0055] FIG. 1 is a conceptual diagram illustrating the cross-sectional structure of a packaging substrate according to an embodiment, FIG. 2 is a conceptual diagram illustrating the cross-sectional structure of a packaging substrate according to another embodiment, and FIGS. 3(a) and (b) are conceptual diagrams illustrating the cross-section of a portion of a packaging substrate according to an embodiment.

[0056] To achieve the above objective, the semiconductor device 100 of the embodiment includes a semiconductor element section 30 in which one or more semiconductor elements 32, 34, and 36 are located, a packaging substrate 20 electrically connected to the semiconductor elements, and a motherboard 10 electrically connected to the packaging substrate 20 and transmitting external electrical signals to the semiconductor elements 32, 34, and 36.

[0057] The packaging substrate 20 according to one embodiment includes a core layer 22, an upper layer 26 disposed on one surface of the core layer 22, and a cavity portion 28 in which a cavity element 40 can be disposed.

[0058] The semiconductor element section 30 means an element mounted on a semiconductor device, and is mounted on the packaging substrate 20 by connection electrodes or the like. Specifically, the semiconductor element section 30 may be, for example, a computing element such as a CPU or a GPU (first element: 32, second element: 34), a storage element such as a memory chip (third element: 36), or the like, but any semiconductor element mounted on a semiconductor device can be used without any restrictions.

[0059] The motherboard 10 may be a motherboard such as a printed circuit board or a printed wiring board.

[0060] The packaging substrate 20 may optionally further include a lower layer (not shown) located below the core layer.

[0061] The core layer 22 may include a glass substrate 21 including a first region 221 having a first thickness 211 and a second region 222 adjacent to the first region 221 and having a second thickness 212 thinner than the first thickness; a number of core vias 23 penetrating the glass substrate 21 in the thickness direction; and a core distribution layer 24 located on the surface of the glass substrate 21 or the core vias 23 and electrically connecting a first surface 213 of the glass substrate 21 to a second surface 214 facing the first surface through the core vias 23. That is, the core layer 22 may include a glass substrate 21 including a first surface 213 and a second surface 214 facing each other, a core via 23, a cavity portion 28, or all of these.

[0062] The second region 222 of the core layer 22 may serve as a cavity structure.

[0063] Within the same area, the glass substrate 21 has a first surface 213 and a second surface 214 facing each other, and these two surfaces are generally parallel to each other, so that the glass substrate 21 has a constant thickness throughout.

[0064] The internal space 281 is formed by the difference in thickness between the first section 221 and the second section 222 and serves to accommodate a part or the whole of the cavity element 40 .

[0065] The glass substrate 21 may include core vias 23 penetrating the first surface 213 and the second surface 214. The core vias 23 may be formed in both the first area 221 and the second area 222, and may be formed at a desired pitch and pattern.

[0066] Conventionally, packaging substrates for semiconductor devices have been applied in the form of a laminate of a silicon substrate and an organic substrate. In the case of a silicon substrate, due to the characteristics of a semiconductor, there is a risk of parasitic elements being generated when applied to high-speed circuits, and there is a drawback in that the power loss is relatively large. In addition, in the case of an organic substrate, a large area is required to form an increasingly complex distribution pattern, which does not fit with the trend of manufacturing electronic devices that are becoming ultra-miniaturized. In order to form a complex distribution pattern within a set size, it is necessary to substantially fine the pattern, but there is a practical limit to the fine pattern due to the characteristics of materials such as polymers applied to organic substrates.

[0067] In the embodiment, to solve this problem, the glass substrate 21 is used as a support for the core layer 22. In addition, by using the glass substrate 21 and the core via 23 formed penetrating the glass substrate 21, the length of electrical flow is further shortened, providing a packaging substrate 20 that is more compact, has faster response, and has less loss characteristics.

[0068] The glass substrate 21 is preferably a glass substrate used in semiconductors. For example, a borosilicate glass substrate or an alkali-free glass substrate may be used, but is not limited thereto.

[0069] The core via 23 penetrates the glass substrate 21. The core via 23 may be formed by removing a predetermined region of the glass substrate 21, specifically, by etching a plate-shaped glass by a physical and / or chemical method.

[0070] Specifically, the formation of the core via 23 may be achieved by forming a defect (scratch) on the surface of the glass substrate using a method such as a laser, followed by chemical etching, laser etching, etc., but is not limited thereto.

[0071] The number of the core vias 23 may be 100 to 3,000, 100 to 2,500, or 225 to 1,024 per unit area (1 cm×1 cm) of the glass substrate 21. When such pitch conditions are satisfied, the formation of an electrically conductive layer and the like and the performance of the packaging substrate can be improved.

[0072] The core distribution layer 24 includes a core distribution pattern 241, which is an electrically conductive layer that electrically connects the first surface and the second surface of the glass substrate through a through via, and a core insulating layer 223 that surrounds the core distribution pattern 241. The core layer 22 has an electrically conductive layer formed therein through a core via, and serves as an electrical path across the glass substrate 21, and connects the upper and lower portions of the glass substrate over a relatively short distance, thereby allowing for faster electrical signal transmission and low loss characteristics. The electrically conductive layer may be, for example, a copper plating layer, but is not limited thereto.

[0073] The shape of the cavity portion 28 may be substantially circular, triangular, rectangular, hexagonal, octagonal, cross-shaped, or the like, and there is no limitation to the shape.

[0074] The shape of the cavity element 40 may be generally cylindrical, rectangular, or polygonal.

[0075] The cavity portion 28 may include a cavity distribution pattern, which is an electrically conductive layer that electrically connects the cavity element 40 and the core distribution layer 24, and an insulating layer that surrounds the cavity distribution pattern.

[0076] Meanwhile, the cavity portion according to another embodiment may be embodied in a form penetrating the first surface 213 and the second surface 214 of the glass substrate 21. In this case, the cavity portion may be formed by the same process as the process of forming the core via 23, and the area and shape penetrating the glass substrate 21 may be different from those of the core via 23.

[0077] In this embodiment, the insulating layer may be formed after the cavity element 40 is arranged in the cavity portion. That is, the insulating layer may be formed in the cavity portion through the process in which the core insulating layer 223 is formed.

[0078] The core distribution pattern 241 may be formed to be electrically connectable to the cavity element 40 .

[0079] The cavity element 40 may include an active element such as a transistor, or a power transfer element, ie, a passive element, such as a multi-layer ceramic capacitor (MLCC).

[0080] When an element such as a transistor that converts electrical signals between the motherboard and the semiconductor element portion to an appropriate level is applied as the cavity element 40, a transistor or the like is applied to the passage of the packaging substrate 20, thereby providing a semiconductor device 100 that is more efficient and has a higher speed.

[0081] In addition, power transfer devices such as multilayer ceramic capacitors (MLCCs) play an important role in the performance of semiconductor devices. Power transfer devices, which are passive devices, are generally applied to semiconductor devices in numbers of at least 200, and the performance of the device is also affected by the characteristics of the electrical conductive layer around the device when transferring power. In one embodiment, a non-circular core via may be applied to such power transfer devices where an electrical conductive layer with low resistance is required.

[0082] Meanwhile, passive elements such as capacitors may be individually inserted into the cavity element 40, or an element group including a number of passive elements may be formed with electrodes exposed and then inserted into the cavity element 40. In the latter case, the workability of manufacturing the packaging substrate may be further improved, and it is more advantageous for an insulating layer to be sufficiently and reliably positioned in spaces between complex elements.

[0083] The glass substrate 21 acts as an intermediate or mediator connecting the semiconductor device part 30 and the motherboard 10 at the upper and lower parts, respectively, and the core vias 23 act as a path for transmitting electrical signals, thereby ensuring smooth signal transmission.

[0084] A top layer 26 is positioned on the first surface 213 .

[0085] The upper layer 26 includes an upper distribution layer 25 and an upper surface connection layer 27 located on the upper distribution layer 25, and the top surface of the upper layer 26 can be protected by a cover layer 60 having an opening formed therein to which a connection electrode of a semiconductor element portion can directly abut.

[0086] The upper distribution layer 25 includes an upper insulating layer 253 located on the first surface, and an upper distribution pattern 251 having a predetermined pattern and being an electrically conductive layer to which at least a portion of the core distribution layer 24 is electrically connected, the upper distribution pattern 251 being embedded in the upper insulating layer 253.

[0087] The upper insulating layer 253 may be any material that can be used as an insulating layer for a semiconductor device or a packaging substrate, such as, but not limited to, an epoxy resin containing a filler.

[0088] The insulator layer may be formed by forming a coating layer and curing it, or may be formed by laminating an insulator film in an uncured or semi-cured state onto the core layer 22 and curing it. In this case, if a reduced pressure lamination method is used, the insulator can be filled into the inner space of the core via 23, allowing for efficient process.

[0089] According to one embodiment, even if multiple insulating layers are applied by stacking, it may be difficult to substantially separate the insulating layers, and the multiple insulating layers are collectively referred to as the upper insulating layer. Also, the core insulating layer 223 and the upper insulating layer 253 may be made of the same insulating material, in which case the boundary between them is not substantially separated. Alternatively, according to another embodiment, the boundary between the insulating layers may be created by setting different pressures and temperatures for curing the multiple insulating layers.

[0090] The upper distribution pattern 251 means an electrically conductive layer located in the upper insulating layer 253 in a predetermined shape, and may be formed, for example, by a build-up layer method. In particular, an insulating layer is formed, unnecessary parts of the insulating layer are removed, an electrically conductive layer is formed by a method such as copper plating, and an unnecessary part of the electrically conductive layer is selectively removed, an insulating layer is formed again on the electrically conductive layer, the unnecessary parts are removed again, and an electrically conductive layer is formed by a method such as plating, and the like. By repeating these methods, the upper distribution pattern 251 having an electrically conductive layer formed vertically or horizontally in a desired pattern can be formed.

[0091] The upper distribution pattern 251 is located between the core layer 22 and the semiconductor device part 30, and is formed to include a fine pattern in at least a part thereof so that electrical signals can be smoothly transmitted to the semiconductor device part 30 and an intended complex pattern can be sufficiently accommodated. In this case, the fine pattern may have a width and interval of less than 4 μm, 3.5 μm or less, 3 μm or less, 2.5 μm or less, or 1 to 2.3 μm (the same applies to the following explanation of the fine pattern).

[0092] At least a portion of the upper connection layer 27 is electrically connected to the upper distribution pattern 251, and the upper connection layer 27 includes an upper connection pattern 272 located on the upper insulating layer 253; and an upper connection electrode 271 electrically connecting the semiconductor device unit 30 and the upper connection pattern 272. The upper connection pattern 272 may be located on one surface of the upper insulating layer 253, or at least a portion of the upper connection pattern 272 may be embedded in the upper insulating layer 253 while being exposed thereon. For example, when the upper connection pattern is located on one surface of the upper insulating layer, the upper insulating layer may be formed by plating or the like, and when the upper connection pattern is embedded in the upper insulating layer while being exposed thereon, a copper plating layer or the like may be formed, and then a portion of the insulating layer or the electrically conductive layer may be removed by surface polishing, surface etching, or the like.

[0093] At least a portion of the upper connection pattern 272 may include a fine pattern like the above-mentioned upper distribution pattern 251. The upper connection pattern 272 including such a fine pattern allows more devices to be electrically connected in a small area, facilitates connection of electrical signals between devices or with the outside, and enables more integrated packaging.

[0094] The upper surface connection electrodes 271 may be directly connected to the semiconductor device part 30 via terminals or the like, or may be connected via device connection parts 51 such as solder balls.

[0095] The cavity portion 28 is located above and / or below the second region 222. The cavity portion 28 includes a cavity distribution layer 282 electrically connected to the core distribution pattern 241 and an internal space 281 in which the cavity element 40 is located.

[0096] Specifically, the thickness of the glass substrate 21 in the second area 222 is thinner than that of the glass substrate 21 in the first area 221, and the cavity element 40 can be located in an internal space 281 formed by the difference in thickness. In addition, the core via 23 and the core distribution layer 24 formed in the glass substrate 21 serve as an electrical connection structure that connects the cavity element 40 to an external element.

[0097] In addition, a cavity portion penetrating the first surface 213 and the second surface 214 of the glass substrate 21 may be formed in the glass substrate 21, and the cavity element 40 may be arranged in the cavity portion.

[0098] The packaging substrate 20 is also connected to the motherboard 10. The motherboard 10 may be directly connected to a core distribution pattern 241 located on at least a portion of the second surface 214 of the core layer 22 via a terminal or the like, or may be electrically connected to the motherboard 10 via a board connection part 52 such as a solder ball. In addition, the core distribution pattern 241 in contact with the motherboard 10 may be connected to the motherboard 10 via a lower layer (not shown) located under the core layer 22.

[0099] For example, the packaging substrate 20 located between the semiconductor device unit 30 and the motherboard 10 may not include any additional substrate other than the glass substrate 21 .

[0100] Conventionally, when connecting a device to a motherboard, an interposer and an organic substrate are laminated between them. This is understood to be applied in such a multi-layer form for at least two reasons. One is that there is a scale problem when directly bonding a fine pattern of a device to a motherboard, and the other is that a problem of wiring damage may occur due to the difference in thermal expansion coefficient during the bonding process or the operation of the semiconductor device. In the embodiment, this problem is solved by applying a glass substrate with a thermal expansion coefficient similar to that of a semiconductor device, and forming a fine pattern with a fine scale sufficient for mounting a device on the first surface of the glass substrate and its upper layer.

[0101] Hereinafter, a method for manufacturing a packaging substrate according to an embodiment of the present invention will be described.

[0102] 4 and 5 are flow charts illustrating a cross-sectional view of a manufacturing process of a packaging substrate according to an embodiment.

[0103] First, as shown in (a) of FIG. 4, a glass substrate 21a having flat first and second surfaces is prepared, and defects (scratches) 21b are formed on the glass surface at predetermined positions for forming core vias. The glass substrate may be a glass substrate used for electronic device substrates, for example, but is not limited to, an alkali-free glass substrate. As a commercially available product, a product manufactured by a manufacturer such as Corning, Schott, or AGC may be used. The defects (scratches) may be formed by mechanical etching, laser irradiation, or other methods.

[0104] As shown in FIG. 4(b), the glass substrate 21a having the defect (scratch) 21b undergoes an etching step to form a core via 23 through a physical or chemical etching process. In the etching process, the glass substrate forms a via in the defective portion, and the surface of the glass substrate 21a may also be etched at the same time. In order to prevent such etching of the glass surface, a masking film or the like may be applied. However, considering the troublesome process of applying and removing the masking film, it is preferable to etch the defective glass substrate itself. In such a case, the thickness of the glass substrate having the core via may be somewhat thinner than the thickness of the initial glass substrate.

[0105] Thereafter, a core layer manufacturing step may be performed by forming an electrically conductive layer 21d on the glass substrate as shown in Fig. 4(c) and (d). The electrically conductive layer may be a metal layer typically including, but not limited to, copper metal.

[0106] The adhesion between the glass surface (including the glass substrate surface and the core via surface) and the copper metal surface is poor due to their different properties. In the present embodiment, the adhesion between the glass surface and the metal can be improved by two methods, a dry method and a wet method.

[0107] The dry method is a method of applying sputtering, i.e., forming a seed layer 21c on the glass surface and the inner diameter surface of the core via by metal sputtering. In forming the seed layer, a different metal such as titanium, chromium, or nickel may be sputtered together with copper, etc., and in this case, the adhesion between the glass and the metal may be improved due to an anchor effect in which the surface morphology of the glass and the metal particles interact with each other.

[0108] The wet method is a method of performing a primer treatment, and is a method of forming a primer layer 21c by pretreating with a compound having a functional group such as an amine. Depending on the intended degree of adhesion, a primer treatment can be performed with a compound or particles having an amine functional group after pretreating with a silane coupling agent. As mentioned above, the support substrate of the embodiment needs to have high performance to be able to form a fine pattern, and this should be maintained even after the primer treatment. Therefore, when such a primer includes nanoparticles, it is preferable that nanoparticles having an average diameter of 150 nm or less are applied, and for example, it is preferable that nanoparticles are applied as particles having an amine group. The primer layer may be formed by applying an adhesion improver manufactured, for example, by MEC's ​​CZ series.

[0109] The seed layer / primer layer 21c may selectively form an electrically conductive layer or a metal layer with or without removing portions that do not require the formation of an electrically conductive layer. In addition, the seed layer / primer layer 21c may be selectively treated with portions that require or do not require the formation of an electrically conductive layer in an activated or inactivated state for metal plating, and the subsequent steps may be performed. For example, the activation or inactivation treatment may be a light irradiation treatment using a laser of a certain wavelength, a chemical treatment, or the like. The formation of the metal layer may be performed using a copper plating method or the like that is applied to the manufacture of semiconductor devices, but is not limited thereto.

[0110] As shown in (e) of Figure 4, a portion of the core distribution layer may be removed if unnecessary, or the seed layer may be partially removed or passivated, and then metal plating may be performed to form an electrically conductive layer in a predetermined pattern, thereby forming an etched layer 21e of the core distribution layer.

[0111] FIG. 5 illustrates a manufacturing step of forming an insulating layer and an upper distribution pattern according to one embodiment.

[0112] As shown in (a) of Fig. 5, the core via may undergo an insulating layer formation step in which an insulating layer is used to fill empty spaces after the formation of the core distribution layer, which is the electrically conductive layer. The insulating layer may be in the form of a film, and may be, for example, a method of vacuum laminating an insulating layer in the form of a film. When vacuum lamination is performed in this manner, the insulating layer is sufficiently filled into the empty spaces inside the core via, thereby forming a core insulating layer without the formation of voids.

[0113] 5(b)-(e) illustrate the top layer fabrication steps.

[0114] The upper layer manufacturing step is a step of forming an upper distribution layer including an upper insulating layer and an upper distribution pattern on the core layer. The upper insulating layer may be formed by coating a resin composition forming the insulating layer 23a or laminating an insulating film, and the method of laminating an insulating film is preferable for simplicity. The lamination of the insulating film may be performed by laminating and curing the insulating film, and if a reduced pressure lamination method is applied, the insulating resin may be sufficiently embedded even in layers where no electrically conductive layer is formed inside the core via. The upper insulating layer also directly contacts the glass substrate at least in part, and therefore has sufficient adhesion. Specifically, the glass substrate and the upper insulating layer preferably have a characteristic of satisfying an adhesion test value of 4B or more according to ASTM D3359.

[0115] The upper distribution pattern may be formed by repeating the process of forming the insulating layer 23a, forming the electrically conductive layer 23c in a predetermined pattern, and etching unnecessary portions to form an etched layer 23d of the electrically conductive layer, and in the case of electrically conductive layers formed adjacent to each other with an insulating layer in between, the upper distribution pattern may be formed by forming blind vias 23b in the insulating layer and then performing a plating process. The blind vias may be formed by dry etching such as laser etching or plasma etching, or wet etching using a masking layer and an etchant.

[0116] Thereafter, a top connection layer and a cover layer may be formed, not shown.

[0117] The upper connection pattern and the upper connection electrodes may also be formed by a process similar to that for forming the upper distribution layer. Specifically, the upper connection pattern and the upper connection electrodes may be formed by forming an etching layer of an insulating layer on the insulating layer 23e, forming an electrically conductive layer thereon again, and then forming an etching layer of the electrically conductive layer, or by selectively forming only the electrically conductive layer without applying an etching method. The cover layer may be formed by forming an opening (not shown) at a position corresponding to the upper connection electrode to expose the upper connection electrode so that it can be directly connected to an element connection part or a terminal of the element.

[0118] After the upper layer is formed, a process of forming a lower connection layer and a cover layer to form a lower layer can be performed. In a similar manner to the above-mentioned upper connection layer and cover layer formation steps, a lower distribution layer and / or a lower connection layer, and optionally a cover layer (not shown) can be formed.

[0119] According to an embodiment, when a number of elements are mounted on the glass substrate 21, cavity portions 29a, 29b of different heights may be created taking into consideration the design of the elements (i.e., the positions at which the elements are arranged, and the area or height of the elements).

[0120] 6(a) to 6(c) are cross-sectional views illustrating a portion of a packaging substrate according to an embodiment.

[0121] 6(a), one embodiment may include a first cavity portion 29a having a first depth h1 and a second cavity portion 29b having a second depth h2 formed in a glass substrate 21. Both the first cavity portion 29a and the second cavity portion 29b may be recessed and open toward a first surface 213.

[0122] The second depth h2 may be deeper than the first depth h1. A cavity element portion having a height corresponding to the depth of the first cavity portion 29a may be disposed in the first cavity portion 29a, and a cavity element portion having a height corresponding to the depth of the second cavity portion 29b may be disposed in the second cavity portion 29b. In this case, the height corresponding to A means a height that is substantially the same as or smaller than the height of A, but does not exclude a height that is greater than the height of A at a level that can be covered by an upper layer or the like (hereinafter the same). The cavity element portion may be an array of one or more cavity elements 40a, 40b. The cavity element portion may be an array of individual cavity elements that are arranged and molded. Alternatively, the cavity element portion may be an array of one or a number of cavity elements that are molded with an insulating material or the like.

[0123] Although the cavity element portion of the first cavity portion 29a and the cavity element portion of the second cavity portion 29b have different heights, the upper insulating layer 61 formed on the first cavity portion 29a and the second cavity portion 29b can be formed flat substantially without undulations.

[0124] Although the first cavity element 40a and the second cavity element 40b have different heights, the upper insulating layer 61 formed on the first cavity element 40a and the second cavity element 40b can be formed flat without substantially undulations.

[0125] The insulating layer can be formed by vacuum laminating an insulating film for semiconductors such as Ajinomoto Build-up Film (ABF) manufactured by Ajinomoto Co., but is not limited thereto.

[0126] Due to the characteristics of insulating materials manufactured in a certain form (e.g., film form), the deep and wide spaces in which the insulating material is placed during the insulating layer formation process can cause unevenness in the surface of the insulating layer. In particular, in the case of a cavity structure that requires filling an insulating material and forming an insulating layer in a space wider than that of a normal via, the occurrence of undulation can be relatively severe.

[0127] In the present embodiment, the depth of the cavity portion is formed to be different from that of the cavity element so as to correspond to the depth of the cavity element, thereby solving this problem.

[0128] A portion of the upper insulating layer 61 is embedded inside the first cavity portion 29a and the second cavity portion 29b, and the surface of the upper insulating layer 61 can be laminated substantially flat on the first surface 213. Since the first cavity portion 29a and the second cavity portion 29b are formed to have different depths, the first surface 213 of the glass substrate 21 can be relatively flat.

[0129] A lower insulating layer 63 may also be formed on the second surface 214, i.e., the lower portion, of the glass substrate 21.

[0130] Meanwhile, one or more connection electrodes 42 may be arranged on the first cavity element 40a in the direction of the first face 213, and one or more connection electrodes 42 may be arranged on the second cavity element 40b in the direction of the first face 213.

[0131] The connection electrodes 42 may be arranged or formed in a direction in which the first cavity portion 29a and the second cavity portion 29b are open, for example, on the first surface 213. The connection electrodes 42 may be electrically connected to an upper layer (not shown) that can be disposed on the upper portion of the glass substrate 21.

[0132] The connection electrode 42 may be formed as part of the electrodes of the first cavity element 40a and the second cavity element 40b, or may be formed or connected as a distributed electrode of the upper layer, or may be configured in a form that includes both of these.

[0133] In another embodiment, the first cavity portion 29a and the second cavity portion 29b may be recessed and open toward the second surface 214 of the glass substrate 21, instead of the first surface 213. In this case, the connection electrodes may be disposed or formed to contact the first cavity portion 29a and the second cavity portion 29b toward the second surface 214. That is, one of the technical features of the present invention is to generate cavities having different depths in the glass substrate 21, and various shapes of the openings of the cavities may be applied.

[0134] In addition, the first surface 213 and the second surface 214 of the glass substrate 21 refer to two surfaces facing each other and are not limited to a specific surface. The cavity portion being recessed and opening toward the first surface can be interpreted as opening toward either one of the opposing surfaces of the glass substrate 21.

[0135] 6(b), the core layer may include a second cavity portion 29b that is recessed toward the first surface 213 and has a second depth, and a third cavity portion 29c that has a third depth h3 and penetrates the first surface 213 and the second surface 214 of the glass substrate 21. The third depth h3 is equal to the height of the glass substrate 21 and is deeper than the second depth h2 of the second cavity portion 29b that is recessed in only one direction.

[0136] That is, according to an embodiment, some of the cavities having different depths may be open to one side of the glass substrate 21, and the other parts may be formed penetrating the glass substrate 21.

[0137] The third cavity element 40c mounted in the third cavity portion 29c penetrating the glass substrate 21 may have connection electrodes 42 arranged or formed on both the top surface facing the first surface 213 and the bottom surface facing the second surface 214. That is, in the case of the third cavity element 40c penetrating the glass substrate 21, one or more connection electrodes may be further arranged in a direction (second surface 214) opposite to the connection electrode formed on the first surface 213 across the third cavity element 40c.

[0138] The connection electrodes 42 can be electrically connected to the upper layer to supply power to the semiconductor chip, and can be electrically connected to the lower layer to connect to a motherboard.

[0139] 6(c), a plurality of half cavities recessed in one direction in the glass substrate 21 may have different opening directions. For example, the first cavity portion 29a may be open toward the first surface 213, and the second cavity portion 29b may be open toward the second surface 214.

[0140] As shown in the figure, the first depth h1 of the first cavity portion 29a and the second depth h2 of the second cavity portion 29b are different from each other, and in one example, the second depth h2 may be deeper than the first depth h1. Of course, the first depth h1 may be deeper than the second depth h2.

[0141] In an embodiment, the connection electrode 42 in contact with the first cavity element 40a may be electrically connected to the upper layer, and the connection electrode 42 in contact with the second cavity element 40b may be electrically connected to the lower layer.

[0142] The role of the cavity element mounted on the packaging substrate may change depending on the design of the semiconductor element or motherboard connected to the upper or lower layer, and the opening direction of the cavity portion may change depending on the role of the cavity element. The arrangement of the connection electrodes may also change depending on the opening direction of the cavity portion.

[0143] That is, a first cavity portion 29a may be formed in the glass substrate 21, which is recessed and opens toward the first surface 213 or the second surface 214, and has a first depth h1, and a second cavity portion 29b may be formed and opens toward the first surface 213 or the second surface 214, and has a second depth h2 different from the first depth h1.

[0144] As described above, the cavity elements 40a, 40b, and 40c may be passive elements such as MLCCs or active elements such as diodes, respectively. These various elements may have different sizes, areas, and heights, which may cause undulations during the formation of a re-distribution layer (RDL).

[0145] Therefore, according to an embodiment, when multiple elements are mounted on the glass substrate 21, cavity portions of different heights can be created taking into consideration the design of the elements (i.e., the positions at which the elements are arranged, and the area or height of the elements).

[0146] For this reason, when forming the cavity portion, a method of selectively masking and then etching is repeated, so that a packaging substrate having cavities of different heights can be manufactured. However, since masking must be repeatedly performed on the surface of the glass substrate 21 and then removed, the manufacturing process is complicated.

[0147] As another method, when forming the cavity portion, a laser beam having different intensities may be selectively irradiated or a laser irradiation time may be adjusted to form defects of different degrees, and the glass substrate 21 in which the cavity portion is formed may be etched to manufacture a packaging substrate. Thereafter, the etching of the glass substrate may be performed at one time. That is, the degree of defects formed in the substrate may be varied depending on the amount of the irradiated laser, and a plurality of half cavities or full cavities having different heights may be formed through this process. This may reduce or eliminate undulation that occurs due to different heights for different elements when mounting various types of elements.

[0148] 7(a) to 7(c) are cross-sectional views illustrating a portion of a packaging substrate according to yet another embodiment.

[0149] 7(a), a first cavity portion 29a having a first depth h1, a second cavity portion 29b having a second depth h2, and a third cavity portion 29c having a third depth h3 may be formed in the glass substrate 21. The first cavity portion 29a and the second cavity portion 29b are recessed and open toward the first surface 213, and the third cavity portion 29c may penetrate the glass substrate 21.

[0150] The second depth h2 is deeper than the first depth h1, and the third depth h3 is deeper than the second depth h2. The first cavity portion 29a, the second cavity portion 29b, and the third cavity portion 29c may have cavity element portions disposed therein, the cavity element portions having heights corresponding to the respective depths of the first cavity portion 29a, the second cavity portion 29b, and the third cavity portion 29c.

[0151] Although the cavity element portion of the first cavity portion 29a, the cavity element portion of the second cavity portion 29b, and the cavity element portion of the third cavity portion 29c have different heights, the upper insulating layer 61 disposed on the first cavity portion 29a, the second cavity portion 29b, and the third cavity portion 29c can be formed flat substantially without undulations.

[0152] Cavity elements 40a, 40b, 40c having heights corresponding to the depths of the first cavity portion 29a, the second cavity portion 29b, and the third cavity portion 29c, respectively, may be arranged in the first cavity portion 29a, the second cavity portion 29b, and the third cavity portion 29c.

[0153] The heights of the first cavity element 40a, the second cavity element 40b and the third cavity portion 29c are different from each other as shown in the figure, but the upper insulating layer 61 formed on the first cavity element 40a, the second cavity element 40b and the third cavity portion 29c can be formed flat substantially without undulations.

[0154] The upper insulating layer 61 is partially embedded inside the first cavity portion 29a, the second cavity portion 29b, and the third cavity portion 29c, and the surface thereof can be laminated substantially flat on the first surface 213. Optionally, a lower insulating layer 63 may also be formed on the second surface 214 of the glass substrate 21, i.e., the lower portion.

[0155] The core layer of the embodiment (a) of Figure 7 may include one or more connection electrodes 42 arranged on the first cavity element 40a in the direction of the first surface 213, one or more connection electrodes 42 arranged on the second cavity element 40b in the direction of the first surface 213, and one or more connection electrodes 42 arranged on the third cavity element 40c in the direction of the first surface 213.

[0156] The connection electrodes 42 are arranged or formed on the first surface 213, which is the direction in which the first cavity portion 29a, the second cavity portion 29b, and the third cavity portion 29c are open, and can be electrically connected to an upper layer (not shown) that can be formed on the upper part of the glass substrate 21.

[0157] Additionally, the third cavity element 40c mounted in the third cavity portion 29c penetrating the glass substrate 21 may have connection electrodes 42 arranged or formed on both the top surface facing the first surface 213 and the bottom surface facing the second surface 214. That is, in the case of the third cavity element 40c penetrating the glass substrate 21, one or more connection electrodes may be further arranged in a direction (second surface 214) opposite to the connection electrode formed on the first surface 213 across the third cavity element 40c.

[0158] The connection electrode 42 may be formed as part of the electrodes of the first cavity element 40a, the second cavity element 40b and the third cavity element 40c, or may be formed as a distributed electrode of the upper layer, or may be configured in a form that includes both of these two.

[0159] The core layer according to the embodiment of FIG. 7(b) includes cavity portions 29a, 29b, and 29c that are open toward the second surface 214 of the glass substrate 21, that is, the bottom surface of the glass substrate 21 and recessed.

[0160] In this case, the connection electrodes 42 may be disposed or formed on the bottom surfaces of the first cavity element 40a, the second cavity element 40b, and the third cavity element 40c. The connection electrodes 42 facing the bottom surfaces may be electrically connected to a motherboard (not shown) via a lower layer formed under the core layer.

[0161] In the core layer according to the embodiment of Fig. 7(c), a plurality of half cavities recessed in one direction in the glass substrate 21 may have different opening directions. For example, the first cavity portion 29a may be open toward the first surface 213, and the second cavity portion 29b may be open toward the second surface 214. As shown in the figure, the first depth h1 of the first cavity portion 29a and the second depth h2 of the second cavity portion 29b are different from each other, and in one example, the second depth h2 may be deeper than the first depth h1. Of course, the first depth h1 may be deeper than the second depth h2.

[0162] As described above, the connection electrode 42 in contact with the first cavity element 40a may be electrically connected to the upper layer, and the connection electrode in contact with the second cavity element 40b may be electrically connected to the lower layer.

[0163] The role of the cavity element mounted on the packaging substrate may change depending on the design of the semiconductor element or motherboard connected to the upper or lower layer, and the opening direction of the cavity portion may change depending on the role of the cavity element. The arrangement of the connection electrodes may also change depending on the opening direction of the cavity portion.

[0164] To summarize the shapes of the cavity portions shown in (a), (b), and (c) of Figures 7, a first cavity portion 29a may be formed in the glass substrate 21, which is recessed and opens toward the first surface 213 or the second surface 214, and has a first depth h1, a second cavity portion 29b may be formed and opens toward the first surface 213 or the second surface 214, and has a second depth h2 different from the first depth h1, and a third cavity portion 29c may be formed which penetrates the first surface 213 and the second surface 214.

[0165] 8 is a flow chart for explaining a process for manufacturing a packaging substrate according to an embodiment in cross section. A process for mounting a cavity element and forming a core layer in a packaging substrate will be described in detail below with reference to FIG. 8. As an example, a packaging substrate having three cavities will be described as a reference, but the number of cavities and the direction of the openings are not limited.

[0166] 8(a), a defect (or scratch) is formed on the surface of a glass substrate 21. The defect (or scratch) may be formed by mechanical etching, laser irradiation, or the like, and as shown in the figure, a defect can be generated by irradiating a laser (E1, E2, E3) (S1: defect forming step).

[0167] At this time, the degree of the defect, such as the size, width, or depth of the defect, may vary depending on the depth of the cavity portion. When the strength of the defect formation is strong, the etching speed may be fast, and when the range or strength of the defect formation is weak, the degree of etching may be slow. By adjusting the etching speed, it is possible to manufacture cavities with different depths. Also, if necessary, the degree of etching can be adjusted by partially applying masking.

[0168] The size of the cavity portion can be determined according to the element to be mounted inside the cavity portion. That is, the degree of defects can be controlled according to the height or area of ​​the cavity element.

[0169] When the defects are formed, an etching step may be performed to form cavities 29a, 29b, and 29c through a physical or chemical etching process as shown in Fig. 8(b). The etching of the cavities may be performed by immersing the substrate in an etching solution to simultaneously form cavities of different depths (S2: cavity forming step).

[0170] As shown, the depth h1 of the first cavity portion 29a is shallower than the depth h2 of the second cavity portion 29b, and the third cavity portion 29c is a full cavity that penetrates the glass substrate and has a depth h3 that may be the same as the height of the glass substrate 21.

[0171] In addition, the bottom area or width of the second cavity portion 29b may be larger than that of the first cavity portion 29a, and the area or width of the third cavity portion 29c may be larger than that of the second cavity portion 29b. The degree of defects and the degree of etching may be adjusted according to the number of cavity elements arranged in the cavity portion.

[0172] Through the defect generation and etching process, a core via (not shown in FIG. 8) may be formed in the glass substrate 21. The core via may be formed in the same process as the cavity portion or in a separate process.

[0173] Although not shown, an electrically conductive layer may be formed on the surface of the glass (including the surface of the glass substrate, the surface of the cavity portion, and the surface of the core via) after the etching process. The electrically conductive layer may be a metal layer including, but not limited to, copper metal. The electrically conductive layer may be formed in a dry manner by applying sputtering or in a wet manner by applying a primer.

[0174] After the above process, as shown in FIG. 8(c), the glass substrate 21 is attached to an adhesive film 80 such as a PI tape (Polyimide Tape), and the cavity elements 40a, 40b, and 40c are selected and arranged in the cavity portions 29a, 29b, and 29c (S3: Arrangement step).

[0175] As shown in the figure, the first cavity element 40a arranged in the first cavity portion 29a has a lower height than the second cavity element 40b or the third cavity element 40c, and the third cavity element 40c may have the greatest height. That is, the cavity portion is generated based on the height or size of the cavity element, and the cavity element is arranged according to the height, so that the upper surface of the glass substrate 21 has a substantially flat form with less waviness than the height difference of the cavity element, despite the height difference of the cavity element.

[0176] Thereafter, as shown in Fig. 8(d), a lamination process (lamination on top) may be performed on the first surface to form an insulating layer (S4: insulating layer formation step). When an insulating film such as ABF (Ajinomoto Build-up Film) is laminated and cured over the entire first surface of the glass substrate 21, the insulator may be filled into the internal spaces of the cavities 29a, 29b, and 29c. According to this embodiment, as shown in Fig. 8(e), the upper insulating layer may be formed in a relatively flat shape with substantially no waviness, i.e., undulation.

[0177] As an example, the insulating layer may be formed through multiple lamination processes, i.e., the process of laminating and curing the insulating film may be performed not once but two or more times, thereby improving the warping phenomenon of the glass substrate and preventing the separation or detachment of the cavity element.

[0178] If necessary, the adhesive film may be removed during a subsequent process. For example, the adhesive film may be an adhesive film whose adhesive strength can be reduced by ultraviolet irradiation, etc. The adhesive film may be easily removed from the glass core by reducing the adhesive strength of the adhesive film by irradiating the adhesive film with ultraviolet light directly or through the glass core.

[0179] After the insulating layer is formed on the first surface of the glass substrate 21, a lower insulating layer may be formed on the second surface as well, as shown in Fig. 8(e), and connection electrodes 42 electrically connected to the cavity elements 40a, 40b, and 40c may be formed (S5: Connection Electrode Forming Step). The connection electrode forming step may be performed after the arrangement step or the insulating layer forming step.

[0180] Then, a top layer (not shown) may be disposed (or formed) on top of the glass substrate 21 , and a bottom layer (not shown) may be disposed (or formed) on the bottom of the glass substrate 21 .

[0181] The process of forming the upper and lower layers is similar to that described with reference to (a) to (e) of FIG. 5, so a duplicated description will be omitted.

[0182] The packaging substrate and the manufacturing method thereof according to the embodiments described above enable elements of various shapes and sizes to be compactly mounted inside the glass substrate, and can reduce or eliminate undulation that may occur in the core layer.

[0183] The present invention described above has been described with reference to the embodiments shown in the drawings, but these are merely illustrative, and a person having ordinary skill in the art will understand that various modifications and variations of the embodiments are possible. In other words, the scope of the present invention is not limited to the above-mentioned embodiments, and various modifications and improvements made by those skilled in the art using the basic concept of the embodiments defined in the accompanying claims also belong to the scope of the embodiments. Therefore, the true technical scope of protection of the present invention must be determined by the technical ideas of the accompanying claims. [Explanation of symbols]

[0184] 100 Semiconductor device 10 Motherboard 20 Packaging Substrate 30 Semiconductor Device Section 32 First semiconductor element 34 Second semiconductor element 36 Third semiconductor element 21, 21a Glass substrate 22 Core Layer 223 Core insulation layer 23 Corebia 24 Core Distribution Layer 241 Core Distribution Pattern 26 Upper layer 28 Cavity 281 Interior Space 282 Cavity Distribution Layer 29a First cavity 29b Second cavity part 29c 3rd cavity part 213 Page 1 214 2nd page 25 Upper distribution layer 251 Upper distribution pattern 253 Upper insulating layer 27 Top connection layer 271 Top connection electrode 272 Top connection pattern 40 Cavity element 42 Connection electrode 40a First cavity element 40b Second cavity element 40c Third cavity element 60 Cover Layer 61a Insulating film 61,63 Insulating layer

Claims

1. A packaging substrate including a core layer, The core layer is a glass substrate including a first surface and a second surface opposed to each other; At least two or more cavities each having an opening that opens in the direction of the first surface or the direction of the second surface, The two or more cavities have different depths from each other.

2. a cavity element including two or more individual elements arranged in the cavity portion and having different heights; The packaging substrate according to claim 1 , further comprising: an insulating layer embedded in the cavity portion and disposed on a surface of the glass substrate on which the opening is formed.

3. The cavity portion includes: a first cavity portion that is recessed toward the first surface and has a first depth; a second cavity portion that is recessed and opens toward the first surface or the second surface and has a second depth; The second depth is greater than the first depth, The cavity element includes: a first cavity element arranged in the first cavity portion; The packaging substrate according to claim 2 , further comprising: a second cavity element arranged in the second cavity portion.

4. A connection electrode is disposed on the first cavity element; The packaging substrate according to claim 3 , wherein a connection electrode is disposed on the second cavity element.

5. The cavity portion includes: a first cavity portion that is recessed toward the first surface and has a first depth; a second cavity portion that is recessed and opens toward the first surface or the second surface and has a second depth; a third cavity portion having a third depth penetrating the first surface and the second surface; The packaging substrate of claim 1 , wherein the second depth is greater than the first depth.

6. The cavity element includes: a first cavity element arranged in the first cavity portion; A second cavity element arranged in the second cavity portion; a third cavity element arranged in the third cavity portion; A connection electrode is disposed on the first cavity element; A connection electrode is disposed on the second cavity element; The packaging substrate according to claim 5 , wherein one or more connection electrodes are disposed on the third cavity element in the direction of the first surface or the second surface.

7. The packaging substrate according to claim 6 , wherein the third cavity element has connection electrodes disposed on both the first surface and the second surface.

8. A method for manufacturing a packaging substrate, comprising: a defect forming step of providing a glass substrate including a first surface and a second surface opposed to each other, and forming a plurality of defects on the first surface or the second surface to different degrees; and forming at least two or more cavities having different depths by etching the glass substrate.

9. The method for manufacturing the packaging substrate further includes an arrangement step and an insulating layer formation step after the cavity formation step, the arranging step is a step of arranging cavity elements in the cavity portion, The insulating layer forming step is a step of forming an insulating layer on a surface on which an opening of the cavity portion is formed, The method for manufacturing a packaging substrate according to claim 8 , wherein the cavity elements disposed in the cavity portion have different heights.

10. The cavity portion includes a first cavity portion and a second cavity portion, the first cavity portion is recessed toward the first surface and has a first depth; the second cavity portion is recessed and opens toward the first surface or the second surface, and has a second depth that is deeper than the first depth; the cavity element includes a first cavity element and a second cavity element; The first cavity element is arranged in the first cavity portion, The second cavity element is arranged in the second cavity portion, The method for manufacturing the packaging substrate further includes a connection electrode forming step, 10. The method for manufacturing a packaging substrate according to claim 9, wherein the connection electrode forming step is a step of forming one or more connection electrodes connected to the first cavity element and one or more connection electrodes connected to the second cavity element.

11. The cavity portion includes a first cavity portion, a second cavity portion, and a third cavity portion, the first cavity portion is recessed toward the first surface and has a first depth; the second cavity portion is recessed and opens toward the first surface or the second surface, and has a second depth that is deeper than the first depth; the third cavity portion extends through the first surface and the second surface and has a third depth; the cavity elements include a first cavity element, a second cavity element, and a third cavity element; The first cavity element is arranged in the first cavity portion, The second cavity element is arranged in the second cavity portion, the third cavity element is arranged in the third cavity portion, The method for manufacturing the packaging substrate further includes a connection electrode forming step, 10. The method for manufacturing a packaging substrate as described in claim 9, wherein the connection electrode forming step is a step of forming one or more connection electrodes connected to the first cavity element, one or more connection electrodes connected to the second cavity element, and one or more connection electrodes connected to the third cavity element.

12. The method for manufacturing a packaging substrate according to claim 11 , wherein the connection electrode forming step further comprises forming connection electrodes on two or more surfaces of the third cavity element, respectively.

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