Semiconductor package and manufacturing method of them

Abstract

To provide a miniaturized semiconductor package, and a manufacturing method of them.SOLUTION: A semiconductor package 1 contains: a lower package substrate 300 containing a lower insulation layer 310; a semiconductor chip 200 that is mounted onto the lower package substrate; a core layer 100 that is separated to a side direction from the semiconductor chip, is arranged onto the lower package substrate, penetrates a core insulation layer 110, a core wiring layer 121, and a core insulation layer, and contains a core via 122 that electrically couples a vertical surface of the core layer; a sealing material 130 that surrounds the semiconductor chip, and covers an upper part of the core layer; and an upper package substrate 400 that contains a first upper part insulation layer 411A, contains a first upper rewiring pattern 420 that is arranged to the first upper part insulation layer, and contains a first upper rewiring layer RDL1 arranged onto the sealing material, a second upper part insulation layer 412 that is arranged onto an upper part of the first upper part insulation layer, and a second upper part rewiring layer RDL2 that contains a second upper rewiring pattern 430 that is arranged to the second upper part insulation layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor package and a manufacturing method thereof, and more particularly to a panel level semiconductor package and a manufacturing method thereof. [Background technology]

[0002] In the electronics market, the demand for portable devices is rapidly increasing, which has led to a continuous demand for smaller and lighter electronic components mounted in these electronic products. To accommodate the demand for smaller and lighter electronic components, the semiconductor packages mounted on them are becoming smaller in volume while still being required to process large amounts of data. Recently, a panel-level packaging (PLP) technology has been proposed that performs a semiconductor packaging process at the panel level and separates the panel-level semiconductor structures that have undergone the semiconductor packaging process into individual packages. Summary of the Invention [Problem to be solved by the invention]

[0003] The present invention has been made in consideration of the above-mentioned conventional technology, and an object of the present invention is to provide a semiconductor package in which the line width of the fine pattern included in the rewiring pattern of the upper package substrate is further refined. The problems that the technical idea of ​​the present invention is intended to solve are not limited to those described above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below. [Means for solving the problem]

[0004] In order to achieve the above object, according to one aspect of the present invention, a semiconductor package includes a lower package substrate including a lower insulating layer, a first semiconductor device mounted on the lower package substrate, a core layer disposed on the lower package substrate at a distance from the first semiconductor device to a side, the core layer including a core substrate, a core via penetrating the core substrate, and a core pattern connecting the core vias, an encapsulant surrounding the first semiconductor device and covering an upper portion of the core layer, and an upper package substrate including a first upper insulating layer, a first upper redistribution layer disposed on the encapsulant, and a second upper redistribution layer including a second upper insulating layer disposed on the first upper insulating layer, and a second upper redistribution layer including a second upper insulating layer disposed on the first upper insulating layer, and a second upper redistribution pattern disposed on the second upper insulating layer, wherein a first line width and a first line spacing of a first fine pattern included in the first upper redistribution pattern are equal to or larger than a corresponding second line width and a second line spacing of a second fine pattern included in the second upper redistribution pattern.

[0005] In order to achieve the above object, a method for manufacturing a semiconductor package according to one aspect of the present invention includes forming a first process structure including a lower package substrate, a first semiconductor device mounted on the lower package substrate, a core layer mounted on the lower package substrate and spaced apart from the first semiconductor device to a side, and an encapsulant interposed on the core layer and surrounding the first semiconductor device on the lower package substrate; forming a first upper redistribution layer including a first upper insulating layer and a first upper redistribution pattern provided on the first upper insulating layer on the encapsulant of the first process structure. forming a second upper redistribution layer including a second upper insulating layer on the first upper redistribution layer and a second upper redistribution pattern provided on the second upper insulating layer, the forming of the first upper redistribution layer including the first upper insulating ... forming a first upper via pattern in the plurality of first upper via holes and forming a first upper line pattern on the first upper via pattern, wherein forming the second upper redistribution layer includes forming a second upper insulating layer on the first upper redistribution layer, forming a plurality of second upper via holes penetrating the second upper insulating layer, forming a second seed layer on the second upper insulating layer having the plurality of second upper via holes, forming a plating resist layer on the second upper insulating layer on which the second seed layer is formed, and forming a first upper line pattern on the plurality of second upper via holes. forming a second upper via pattern on the first upper insulating layer and forming a second upper line pattern on the second upper via pattern, wherein the first upper redistribution pattern and the second upper redistribution pattern are formed such that a material contained in the first upper insulating layer is different from a material contained in the second upper insulating layer, and a first line width and a first line interval of a first fine pattern contained in the first upper redistribution pattern are equal to or larger than a corresponding second line width and a second line interval of a second fine pattern contained in the second upper redistribution pattern, and the first seed layer is formed by electroless plating,The second seed layer is formed by a sputtering process.

[0006] A method for manufacturing a semiconductor package according to another aspect of the present invention, which has been made to achieve the above object, includes forming a first process structure including a lower package substrate, a first semiconductor device mounted on the lower package substrate, a core layer mounted on the lower package substrate and spaced laterally from the first semiconductor device, and an encapsulant that surrounds the first semiconductor device on the lower package substrate and is interposed on the core layer; forming a first upper redistribution layer including a first upper insulating layer and a first upper redistribution pattern provided on the first upper insulating layer on the encapsulant of the first process structure; and forming a second upper redistribution layer including a second upper insulating layer and a second upper redistribution pattern provided on the second upper insulating layer on the first upper redistribution layer, wherein the forming of the first upper redistribution layer includes forming the first upper insulating layer on the encapsulant; forming a plurality of first upper via holes that penetrate the first upper insulating layer and are recessed in portions of the encapsulant to expose portions of the core layer; forming a first seed layer on the first upper insulating layer having first upper via holes; forming a first upper via pattern in the first upper via holes to be electrically connected to the core layer, and forming a first upper line pattern on the first upper via pattern, wherein forming the second upper redistribution layer includes forming a second upper insulating layer on the first upper redistribution layer, forming a plurality of second upper via holes penetrating the second upper insulating layer, forming a second seed layer on the second upper insulating layer having the plurality of second upper via holes, forming a plating resist layer on the second upper insulating layer on which the second seed layer is formed, and forming a second upper via pattern in the second upper via holes and forming a second upper line pattern on the second upper via pattern, wherein a material contained in the first upper insulating layer and a material contained in the second upper insulating layer are the same, and the first seed layer and the second seed layer are each formed by a sputtering process. Effect of the Invention

[0007] In the semiconductor package of the present invention, at least a portion of an upper insulating layer of an upper package substrate includes a photosensitive resin, and a seed layer for forming an upper redistribution pattern is formed on the upper insulating layer including the photosensitive resin through a sputtering process, thereby making it possible to further refine the line width and line spacing of the fine pattern of the upper redistribution pattern included in the upper package substrate, thereby improving the performance of the semiconductor package. [Brief description of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view showing a semiconductor package according to an exemplary embodiment of the present invention; [Diagram 2] 1 is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the present invention; [Diagram 3] 1 is a cross-sectional view showing a semiconductor package according to an exemplary embodiment of the present invention; [Figure 4] 1 is a cross-sectional view showing a semiconductor package according to an exemplary embodiment of the present invention; [Diagram 5] 2 is a flowchart illustrating a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention. [Figure 6] 4 is a flowchart for more specifically explaining a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention. [Figure 7A] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention. [Figure 7B] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention. [Figure 7C] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention. [Figure 7D] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention. [Figure 7E] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention. [Figure 7F] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention. [Figure 8A] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention. [Figure 8B] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention. [Figure 8C] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention. [Figure 8D] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention. [Figure 8E] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention. [Figure 8F] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention. [Figure 8G] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention. [Figure 8H] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention. [Figure 8I] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention. [Figure 8J] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention. [Figure 9] 4 is a flowchart for more specifically explaining a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention. [Figure 10A] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention. [Figure 10B] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention. [Figure 10C] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention. [Figure 10D] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention. [Figure 10E] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention. [Figure 10F] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention. [Figure 10G] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention. [Figure 10H] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention. [Figure 10I] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention. [Figure 10J] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the technical concept of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used to refer to the same components in the drawings, and redundant description thereof will be omitted.

[0010] FIG. 1 is a cross-sectional view showing a semiconductor package 1 according to an exemplary embodiment of the present invention.

[0011] 1, the semiconductor package 1 includes a semiconductor chip 200, a lower package substrate 300 disposed under the semiconductor chip 200, a core layer 100 having through holes CA for mounting the semiconductor chip 200 therein, an encapsulant 130 surrounding the side and top surfaces of the semiconductor chip 200 and the top surface and some side surfaces of the core layer 100, and an upper package substrate 400 disposed on the encapsulant 130. The semiconductor package 1 is a fan-out type semiconductor package in which connection pads 220 of the semiconductor chip 200 are rewired outward. In this specification, the semiconductor chip 200 is referred to as a first semiconductor device.

[0012] The core layer 100 includes through holes CA penetrating the top and bottom surfaces so that the semiconductor chip 200 can be mounted thereon. The through holes CA are formed in the center of the core layer 100 as shown in FIG. 1, but the number and arrangement of the through holes CA are not limited to those shown in the drawings. In some embodiments, the through holes CA do not completely penetrate the bottom surface and have a cavity shape. For example, the through holes CA do not completely penetrate the bottom surface of the core layer 100, and a part of the core layer 100 remains below the through holes CA.

[0013] The core layer 100 includes a core insulating layer 110, a core wiring layer 121, and a core via 122. The core wiring layer 121 and the core via 122 are arranged to electrically connect the upper and lower surfaces of the core layer 100. The core wiring layer 121 is arranged inside the core insulating layer 110, but is not limited to this. The core wiring layer 121 exposed through the lower surface of the core layer 100 out of the core wiring layer 121 is arranged embedded in the core insulating layer 110, which is a structure based on the manufacturing process. The core insulating layer 110 is also called a base substrate.

[0014] The core insulating layer 110 may include an insulating material, for example, a thermosetting resin such as an epoxy resin or a thermoplastic resin such as a polyimide, and may further include an inorganic filler. Alternatively, the core insulating layer 110 may include a resin impregnated in a core material such as glass fiber (glass cloth, glass fabric), for example, prepreg, ABF (Ajinomoto Build-up Film), FR-4, or BT (Bismaleimide Triazine), together with the inorganic filler. The core insulating layer 110 is a multilayer substrate consisting of multiple layers.

[0015] The semiconductor chip 200 is mounted in the through-hole CA of the core layer 100 and is disposed at a distance from the inner wall of the through-hole CA. The first semiconductor chip 200 may be one or more. The semiconductor chip 200 includes a semiconductor substrate 210 having an active surface and a non-active surface facing each other, and a connection pad 220 disposed on the active surface side of the semiconductor chip 200. For example, the semiconductor chip 200 has a vertical thickness of about 150 μm or more.

[0016] The semiconductor chip 200 has a face-down arrangement in which the active surface faces the lower package substrate 300, and is mounted on the upper surface of the lower package substrate 300. In this case, the non-active surface of the semiconductor chip 200 is referred to as the upper surface of the semiconductor chip 200, and the surface of the semiconductor substrate 210 opposite the non-active surface of the semiconductor chip 200 is referred to as the lower surface of the semiconductor chip 200.

[0017] The semiconductor substrate 210 includes a semiconductor material such as silicon (Si) or germanium (Ge). Alternatively, the semiconductor substrate 210 includes a compound semiconductor material such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). The semiconductor substrate 210 includes a well doped with impurities, which is a conductive region. The semiconductor substrate 210 has various isolation structures such as a shallow trench isolation (STI) structure.

[0018] A semiconductor device including a variety of types of individual devices is formed on the active surface of the semiconductor substrate 210. The individual devices are electrically connected to conductive regions of the semiconductor substrate 210. The semiconductor device further includes conductive wiring or conductive plugs that electrically connect the individual devices to the conductive regions of the semiconductor substrate 210. Additionally, each of the individual devices is electrically isolated from adjacent individual devices by an insulating film.

[0019] In some embodiments, the semiconductor chip 200 includes logic elements. For example, the semiconductor chip 200 is a central processing unit chip, a graphic processing unit chip, or an application processor (AP) chip. In other embodiments, when the semiconductor package 1 includes multiple semiconductor chips 200, one of the multiple semiconductor chips 200 is a central processing unit chip, a graphic processing unit chip, or an application processor chip, and the other is a memory semiconductor chip including memory elements.

[0020] For example, the memory device may be a non-volatile memory device such as a Flash Memory, a Phase-change Random Access Memory (PRAM), a Magnetoresistive Random Access Memory (MRAM), a Ferroelectric Random Access Memory (FeRAM), or a Resistive Random Access Memory (RRAM). In some embodiments, the memory device may be a volatile memory device such as a Dynamic Random Access Memory (DRAM) or a Static Random Access Memory (SRAM).

[0021] The semiconductor chip 200 includes connection pads 220 disposed on a lower surface. The connection pads 220 are disposed to electrically connect the semiconductor chip 200 to other components. According to an embodiment, a redistribution layer or bumps connected to the connection pads 220 may be further disposed on the lower surface of the semiconductor chip 200. The connection pads 220 are made of a conductive material, for example, aluminum (Al). The semiconductor chip 200 is electrically connected to a lower redistribution pattern 320 of the lower package substrate 300 via the connection pads 220.

[0022] The lower package substrate 300 rewires the connection pads 220 under the semiconductor chip 200 to an outer region of the semiconductor chip 200. The lower package substrate 300 includes a plurality of lower insulating layers 310 and a lower rewiring pattern 320 including a lower via pattern 322 and a lower line pattern 321. The number and arrangement of the lower insulating layers 310, the lower via patterns 322, and the lower line patterns 321 constituting the lower package substrate 300 are not limited to those shown in the drawings and may be variously changed in the embodiments.

[0023] The lower insulating layer 310 is made of an insulating material, for example, a photo imagable dielectric (PID) resin. In this case, the lower insulating layer 310 may further include an inorganic filler. The lower insulating layers 310 may be made of the same or different materials. The lower redistribution pattern 320 including the lower via pattern 322 and the lower line pattern 321 serves to redistribute the connection pads 220.

[0024] The lower line pattern 321 is disposed on at least one of an upper surface and a lower surface of the lower insulating layer 310. The lower via pattern 322 penetrates the lower insulating layer 310 and is connected to a portion of the lower line pattern 321.

[0025] The lower via pattern 322 is completely filled with a conductive material or has a shape in which a conductive material is formed along the walls of the via. The lower redistribution pattern 320 includes a conductive material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof.

[0026] The lower surface of the semiconductor chip 200 is in direct contact with the lower insulating layer 310 disposed at the topmost layer among the lower insulating layers 310. In a semiconductor package manufacturing method S1, which is a manufacturing process of a semiconductor package 1 according to an exemplary embodiment of the present invention described below, the lower package substrate 300 is formed on the lower surface of the semiconductor chip 200 by a chip-first process. As described below with reference to FIG. 7F, due to the order in which the lower package substrate 300 is formed, in the semiconductor package 1 according to an exemplary embodiment of the present invention, the lower via pattern 322 has a tapered shape in which the horizontal width increases as it becomes farther from the semiconductor chip 200.

[0027] The lower passivation layer 350 is disposed on the lower surface of the lower package substrate 300 and serves to protect the lower package substrate 300. The lower passivation layer 350 is made of an insulating material, for example, but not limited to, a resin.

[0028] At least a portion of the lower line pattern 321 is exposed through the opening of the lower passivation layer 350, and the lower pads 330 are disposed on the exposed lower line pattern 321. The lower pads 330 are electrically connected to the external connection terminals 340, respectively.

[0029] The external connection terminals 340 connect the semiconductor package 1 to a main board of a separate electronic device in which the semiconductor package 1 is mounted. The external connection terminals 340 include at least one of a conductive material, for example, solder, tin (Sn), silver (Ag), copper (Cu), and aluminum (Al). The shape of the external connection terminals 340 may be changed to various shapes such as a land, a bump, a pillar, a pin, etc. in addition to a ball shape.

[0030] The encapsulant 130 seals the semiconductor chip 200 to protect the semiconductor chip 200 from physical and chemical damage from the outside. The encapsulant 130 fills the space in the through hole CA of the core layer 100 and extends onto the upper surface of the core layer 100. That is, the encapsulant 130 fills the space between the semiconductor chip 200 and the inner wall of the through hole CA, and covers a part of the upper surface of the semiconductor chip 200 and the upper surface of the core layer 100. According to the embodiment, the encapsulant 130 fills at least a part of the space between the semiconductor chip 200 and the upper package substrate 400. The encapsulant 130 is made of an insulating material, for example, an epoxy resin or a polyimide. However, the material of the encapsulant 130 is not limited to the above-mentioned materials.

[0031] The upper package substrate 400 includes a first upper redistribution layer RDL1 and a second upper redistribution layer RDL2. The upper package substrate 400 is disposed on the upper surface of the encapsulant 130 and is electrically connected to the semiconductor chip 200 and the lower package substrate 300 through the core wiring layer 121 and the core vias 122 of the core layer 100.

[0032] The first upper redistribution layer RDL1 includes a first upper insulating layer 411A disposed on the encapsulant 130, and a first upper redistribution pattern 420. The first upper redistribution pattern 420 includes a first upper via pattern 421, a first upper line pattern 422, and a first fine pattern FP1. A first seed layer SD1 used as a base for forming the first upper redistribution pattern 420 is provided on a lower surface of the first upper redistribution pattern 420.

[0033] The first upper via patterns 421 each penetrate the first upper insulating layer 411A. Also, the first upper via patterns 421 each penetrate a part of the encapsulant 130 to be electrically connected to the uppermost core wiring layer 121 of the core layer 100. The first upper line pattern 422 is disposed on the first upper insulating layer 411A and the first upper via pattern 421. Rewiring of electrical input / output is performed in the first upper rewiring layer RDL1 via the first fine pattern FP1.

[0034] A portion of the side of the first upper via pattern 421 is in contact with the first upper insulating layer 411A, and at least a portion of the remaining side of the first upper via pattern 421 that is not in contact with the first upper insulating layer 411A is in contact with the encapsulant 130.

[0035] The first seed layer SD1A is interposed between the first upper via pattern 421 and the first upper line pattern 422 and the first upper insulating layer 411A. In this specification, the first upper via pattern 421 and the first upper line pattern 422 are referred to including the first seed layer SD1A on the lower surface in contact with them. That is, although it is illustrated that a part of the side surface of the first upper via pattern 421 is in contact with the first seed layer SD1A and a part of the side surface of the first seed layer SD1A is in contact with the first upper insulating layer 411A, the first seed layer SD1A in contact with the first upper via pattern 421 is included in the first upper via pattern 421, so that as described above, a part of the side surface of the first upper via pattern 421 is described as being in contact with the first upper insulating layer 411A. At the same time, at least a part of the remaining side surfaces of the first upper via pattern 421 that are not in contact with the first upper insulating layer 411A are described as being in contact with the encapsulant 130.

[0036] The first upper via pattern 421 has a tapered shape in which the horizontal width of the first upper via pattern 421 increases as it becomes farther from the lower package substrate 300 .

[0037] The first upper insulating layer 411A is processed to form a first upper via hole 420R (see FIG. 8C) in which the first upper rewiring pattern 420 is provided in the first upper insulating layer 411A. For example, the first upper insulating layer 411A is laser processed to form a first upper via hole 420R (see FIG. 8C) in which the first upper rewiring pattern 420 is provided in the first upper insulating layer 411A.

[0038] The first upper insulating layer 411A is made of a build-up material. In an exemplary embodiment, the build-up material is a build-up film, which is a SiO 2 film mainly composed of epoxy resin on a PET film as a base. 2It has a three-layer structure including a filler, a resin structure containing a flame retardant, and an oriented polypropylene (OPP) film. The build-up material may be Ajinomoto Build-up Film (ABF) or other laminates. For example, ABF is used as the build-up material included in the first upper insulating layer 411A. Therefore, in an exemplary embodiment, the encapsulant 130 and the first upper insulating layer 411A are made of the same build-up material.

[0039] After the encapsulant 130 is formed including ABF, a first upper insulating layer 411A including ABF is newly formed on the upper surface of the encapsulant 130 including the already cured ABF in order to form the first seed layer SD1A, which is the base of the first upper rewiring pattern 420, through electroless plating. If the first upper insulating layer 411A including ABF before curing is formed on the encapsulant 130 including the cured ABF, the adhesion between the pre-cured ABF and the plating layer in electroless plating is greater than that of the cured ABF. Therefore, the first upper insulating layer 411A is formed on the encapsulant 130 by applying ABF so that electroless plating for forming the first seed layer SD1A can be easily performed. This improves the reliability of the wiring of the semiconductor package 1, which is an exemplary embodiment of the present invention.

[0040] The first seed layer SD1A formed via electroless plating includes one or more materials selected from the group consisting of copper (Cu), nickel (Ni), palladium (Pd), silver (Ag), chromium (Cr), titanium (Ti), and gold (Au).

[0041] The second upper redistribution layer RDL2 includes a second upper insulating layer 412 disposed on the first upper insulating layer 411A, and a second upper redistribution pattern 430. The second upper redistribution pattern 430 includes a second upper via pattern 431, a second upper line pattern 432, and a second fine pattern FP2. A second seed layer SD2 used as a base for forming the second upper redistribution pattern 430 is provided on the lower surface of the second upper redistribution pattern 430. In the second upper redistribution layer RDL2, rewiring of electrical input / output is performed through the second fine pattern FP2. Unlike the illustrated example, the semiconductor package 1 according to the exemplary embodiment of the present invention may include three or more redistribution layers by providing the second upper redistribution layer RDL2 in a multi-layered stack. The second upper via pattern 431 is provided in the second upper redistribution layer RDL2 as a stacked via or a staggered via. A stacked via refers to a structure in which via patterns are stacked while overlapping vertically, and a staggered via refers to a structure in which via patterns are stacked vertically, but the vias stacked vertically are offset from each other at a regular interval to the side.

[0042] The second upper insulating layer 412 is provided on the first upper insulating layer 411A and the first upper redistribution pattern 420. The second upper insulating layer 412 is made of an insulating material, for example, a photo-imagable dielectric (PID) resin. In this case, the second upper insulating layer 412 may further include an inorganic filler.

[0043] A second upper redistribution pattern 430 including a second upper via pattern 431 and a second upper line pattern 432 is formed in the second upper insulating layer 412. The second upper via pattern 431 penetrates the second upper insulating layer 412 and is electrically connected to at least a portion of the first upper line pattern 422 of the first upper redistribution layer RDL1. The second upper line pattern 432 is disposed on the second upper insulating layer 412 and provided on the second upper via pattern 431. A metal plating layer 433 is provided on at least a portion of the second upper line pattern 432. The metal plating layer 433 is made of a metal including, for example, gold (Au).

[0044] The upper passivation layer 440 is disposed on the upper surface of the second upper insulating layer 412 and serves to protect the upper package substrate 400. The upper passivation layer 440 is made of an insulating material, for example, but not limited to, a build-up material. The upper passivation layer 440 has a third hole 440R, which is a recessed portion of the upper passivation layer 440 to expose at least a portion of the second upper via pattern 431 and the metal plating layer 433. An upper connecting terminal 540 is positioned in the third hole 440R in a package-on-package type package to which the upper semiconductor device 500 described below is stacked or attached.

[0045] In an exemplary embodiment, the second upper insulating layer 412 is made of a photosensitive insulating (photo imagable dielectric, PID) resin, and the second seed layer SD2 serving as a base for the second upper redistribution pattern 430 is formed by a sputtering process. The second seed layer SD2 can be formed with a smaller line width than when the second seed layer SD2 is formed through electroless plating. Since the second upper insulating layer 412 is made of a photosensitive insulating resin, and the second seed layer SD2 is formed by a sputtering process, the line width of the second seed layer SD2 is smaller than the line width of the first seed layer SD1A serving as a base for the first upper redistribution pattern 420 formed through electroless plating. Therefore, the line width of the second fine pattern FP2 of the second upper redistribution pattern 430 is the same as or smaller than the line width of the first fine pattern FP1 of the first upper redistribution pattern 420. In other words, the line width of the first fine pattern FP1 of the first upper redistribution pattern 420 is equal to or greater than the line width of the second fine pattern FP2 of the second upper redistribution pattern 430.

[0046] For example, the first line width LW1A and the first line spacing LS1A of the first fine pattern FP1 are equal to or larger than the second line width LW2 and the second line spacing LS2 of the second fine pattern FP2. The first line width LW1A of the first fine pattern FP1 is 10 μm or less, the first line spacing LS1A is 13 μm or less, the second line width LW2 of the second fine pattern FP2 is 9 μm or less, and the second line spacing LS2 is 12 μm or less. Or, the first line width LW1A is 5 μm or more and 10 μm or less, the first line spacing LS1 is 5 μm or more and 13 μm or less, the second line width LW2 is 3 μm or more and 9 μm or less, and the second line spacing LS2 is 3 μm or more and 12 μm or less. Or, the second line width LW2 of the second fine pattern FP2 is 5 μm or less, and the second line spacing LS2 is 5 μm or less.

[0047] The first upper rewiring pattern 420 of the first rewiring layer RDL1 is entirely included in the first fine pattern FP1, or only a portion of the first upper rewiring pattern 420 is included in the first fine pattern FP1. The second upper rewiring pattern 430 of the second rewiring layer RDL2 is entirely included in the second fine pattern FP2, or only a portion of the second upper rewiring pattern 430 is included in the second fine pattern FP2.

[0048] The line width of a portion of the first upper rewiring pattern 420 not included in the first fine pattern FP1 exceeds 10 μm, and the line spacing exceeds 13 μm. Similarly, the line width of a portion of the second upper rewiring pattern 430 not corresponding to the second fine pattern FP2 exceeds 10 μm, and the line spacing exceeds 13 μm. The portion of the first upper rewiring pattern 420 not included in the first fine pattern FP1 and the portion of the second upper rewiring pattern 430 not corresponding to the second fine pattern FP2 are collectively referred to as a coarse pattern. For example, the line width and line spacing of the coarse pattern are 13 μm to 100 μm, respectively. The coarse pattern includes a ground wiring and a ground wiring. The first fine pattern FP1 and the second fine pattern FP2 include a signal wiring, a ground wiring, and a ground wiring.

[0049] The line width of the second fine pattern FP2 is smaller than the line width of the first fine pattern FP1 in the semiconductor package 1. Therefore, in the semiconductor package 1 according to the exemplary embodiment of the present invention, the fine pattern of the second package substrate 400 corresponding to the rear redistribution layer can be made finer, thereby improving the performance of the semiconductor package 1.

[0050] 2 is a cross-sectional view of a semiconductor package 1A according to an exemplary embodiment of the present invention. Description that overlaps with the above content will be omitted.

[0051] 2, the semiconductor package 1A includes a semiconductor chip 200, a lower package substrate 300 disposed under the semiconductor chip 200, a core layer 100 having through holes CA for mounting the semiconductor chip 200 therein, an encapsulant 130 surrounding the side and top surfaces of the semiconductor chip 200 and parts of the top and side surfaces of the core layer 100, and an upper package substrate 400 disposed on the encapsulant 130. FIG. 2 will be described focusing on the differences from FIG. 1.

[0052] The upper package substrate 400 includes a first upper redistribution layer RDL1 and a second upper redistribution layer RDL2.

[0053] The first upper redistribution layer RDL1 includes a first upper insulating layer 411B disposed on the encapsulant 130, and a first upper redistribution pattern 420. The first upper redistribution pattern 420 includes a first upper via pattern 421, a first upper line pattern 422, and a first fine pattern FP1. The first upper via pattern 421 penetrates the first upper insulating layer 411B. Also, the first upper via pattern 421 penetrates a part of the encapsulant 130 and is electrically connected to the uppermost core wiring layer 121 of the core layer 100. The first upper line pattern 422 is disposed on the first upper insulating layer 411B and the first upper via pattern 421.

[0054] Unlike the semiconductor package 1 of the exemplary embodiment of the present invention shown in Fig. 1, the semiconductor package 1A of another exemplary embodiment of Fig. 2 has a first upper insulating layer 411B made of an insulating material that is not a build-up material, such as a photo-imagable dielectric (PID) resin. In this case, the first upper insulating layer 411B may further include an inorganic filler.

[0055] In an exemplary embodiment, the first upper insulating layer 411B is made of a photosensitive insulating (photo imagable dielectric, PID) resin, and the first seed layer SD1B serving as the basis of the first upper redistribution pattern 420 is formed by a sputtering process. The first seed layer SD1B is formed with a smaller line width than when the first seed layer SD1B is formed by electroless plating. Since the first upper insulating layer 411B is made of a photosensitive insulating resin, the first seed layer SD1B is formed by a sputtering process, and therefore the line width of the first seed layer SD1B formed by the sputtering process is smaller than the line width of the first seed layer SD1B formed by electroless plating. Therefore, the line width of the first fine pattern FP1 of the first upper redistribution pattern 420 is made finer.

[0056] The range of the first line width LW1B of the first fine pattern FP1 and the range of the second line width LW2 of the second fine pattern FP2 are the same. The range of the first line spacing LS1B of the first fine pattern FP1 and the range of the second line spacing LS2 of the second fine pattern FP2 are substantially the same.

[0057] For example, the first line width LW1B of the first fine pattern FP1 is 9 μm or less, and the first line spacing LS1B is 12 μm or less, and similarly, the second line width LW2 of the second fine pattern FP2 is 9 μm or less, and the second line spacing LS2 is 12 μm or less. Alternatively, the first line width LW1B and the second line width LW2 are 3 μm or more and 9 μm or less, and the first line spacing LS1B and the second line spacing LS2 are 3 μm or more and 12 μm or less. Alternatively, the first line width LW1B and the second line width LW2 of the first fine pattern FP1 are 5 μm or less, and the first line spacing LS1B and the second line spacing LS2 are 5 μm or less.

[0058] Therefore, in the semiconductor package 1A according to the illustrative embodiment of the present invention, the fine pattern of the second package substrate 400, which corresponds to the rear redistribution layer, can be made finer, and the performance of the semiconductor package 1 is improved.

[0059] Fig. 3 is a cross-sectional view showing a semiconductor package 2 according to an exemplary embodiment of the present invention. Fig. 4 is a cross-sectional view showing a semiconductor package 2A according to an exemplary embodiment of the present invention. Descriptions that overlap with the above content will be omitted.

[0060] 3, a semiconductor package 2 according to an exemplary embodiment of the present invention further includes an upper semiconductor device 500 mounted on the upper part of the semiconductor package 1 described in FIG 1. That is, the semiconductor package 2 is a package-on-package type package in which the upper semiconductor device 500 corresponding to the upper package is stacked or attached on the semiconductor package 1 corresponding to the lower package.

[0061] The upper semiconductor device 500 is electrically connected to the upper package substrate 400 through the upper connection terminal 540. The upper connection terminal 540 includes at least one of a conductive material, for example, solder, tin (Sn), silver (Ag), copper (Cu), and aluminum (Al). The shape of the external connection terminal 340 may be changed to various shapes such as a land, a bump, a pillar, a pin, etc. in addition to a ball shape.

[0062] The upper semiconductor device 500 is a semiconductor package including at least one or more semiconductor chips. The at least one or more semiconductor chips included in the upper semiconductor device 500 include a memory chip, a logic chip, a system on chip (SOC), a power management integrated circuit (PMIC) chip, a radio frequency integrated circuit (RFIC) chip, and the like. The memory chip includes a DRAM chip, an SRAM chip, an MRAM chip, a Nand flash memory chip, and / or a high bandwidth memory (HBM) chip. The logic chip includes an application processor (AP), a microprocessor, a central processing unit (CPU), a controller, and / or an application specific integrated circuit (ASIC). For example, the SOC includes at least two circuits among a logic circuit, a memory circuit, a digital integrated circuit (IC), a radio frequency integrated circuit (RFIC), and an input / output circuit.

[0063] 4, a semiconductor package 2A according to an exemplary embodiment of the present invention further includes an upper semiconductor device 500 mounted on the upper part of the semiconductor package 1A described in FIG 2. That is, the semiconductor package 2A is a package-on-package type package in which the upper semiconductor device 500 corresponding to the upper package is stacked or attached on the semiconductor package 1A corresponding to the lower package.

[0064] Fig. 5 is a flow chart for explaining the method S1 for manufacturing a semiconductor package according to an exemplary embodiment of the present invention. Fig. 6 is a flow chart for explaining the method S1 for manufacturing a semiconductor package according to an exemplary embodiment of the present invention in more detail.

[0065] Referring to FIG. 5, a semiconductor package manufacturing method S1, which is an exemplary embodiment of the present invention, includes a step (S100) of forming a first process structure including a lower package substrate, a first semiconductor device, a core layer, and an encapsulant, a step (S200A, S200B) of forming a first upper redistribution layer including a first upper insulating layer and a first upper redistribution pattern, and a step (S300) of forming a second upper redistribution layer including a second upper line pattern, a second upper via pattern, and a second upper insulating layer.

[0066] FIG. 6 is a flowchart showing in more detail the steps of forming a first upper redistribution layer including a first upper insulating layer and a first upper redistribution pattern (S200A, S200B), and the step of forming a second upper redistribution layer including a second upper line pattern, a second upper via pattern, and a second upper insulating layer (S300).

[0067] Referring to FIG. 6, the step of forming a first upper redistribution layer (S200A) includes a step of forming a first upper insulating layer including a build-up material on an encapsulant (S210A), a step of forming a plurality of first upper via holes penetrating the first upper insulating layer and recessing a portion of the first encapsulant to expose a portion of the core layer (S220), a step of forming a first seed layer by an electroless plating process (S230A), and a step of forming a plurality of first upper via patterns and a plurality of first upper line patterns in the plurality of first upper via holes (S240).

[0068] The step of forming the second upper redistribution layer (S300) includes a step of forming a second upper insulating layer including a PID on the first upper redistribution layer (S310), a step of forming a plurality of second upper via holes through the second upper insulating layer (S320), a step of forming a second seed layer by a sputtering process (S330), a step of forming a liquid photoresist layer on the second upper insulating layer (S340), and a step of forming a plurality of second upper via patterns and a plurality of second upper line patterns in the plurality of second upper via holes (S350).

[0069] 5 and 6, together with FIGS. 7A-7F and 8A-8J described below, a method S1 for manufacturing a semiconductor package according to an exemplary embodiment of the present invention will be described.

[0070] 7A to 7F are cross-sectional views illustrating a method S1 for manufacturing a semiconductor package according to an exemplary embodiment of the present invention. The process illustrated in FIG. 7A to 7F corresponds to a step (S100) of forming a first process structure including a lower package substrate, a first semiconductor device, a core layer, and an encapsulant.

[0071] 7A, a core layer 100 having a through hole CA is disposed on a tape carrier TC. As described above, the core insulating layer 110 is a multi-layer substrate including an insulating material or a resin and is composed of a plurality of layers. The core layer 100 includes a core wiring layer 121 disposed between each of the layers of the core insulating layer 110 and on at least one of the upper and lower surfaces of the layers of the core insulating layer 110.

[0072] Referring to FIG. 7B, the semiconductor chip 200 and the connection pads 220 provided on the underside of the semiconductor chip 200 face the tape carrier TC and are disposed in the through holes CA formed in the core insulating layer 110 so that the active surface of the semiconductor chip 200 faces the tape carrier TC.

[0073] 7C, an encapsulant 130 is formed to surround the semiconductor chip 200 and surround some of the side surfaces and a part of the top surface of the core insulating layer 110. After the encapsulant 130 is formed, a planarization process is separately performed on the top surface of the encapsulant 130.

[0074] 7D, the wiring structure 120, the core insulating layer 110, and the semiconductor chip 200 arranged on the tape carrier TC are arranged on the first carrier CR1 so that the top surface of the semiconductor chip 200 faces the first carrier CR1. A first adhesive layer CF1 for adhering the process objects is interposed between the encapsulant 130 and the first carrier CR1. The first adhesive layer CF1 is a copper foil for adhesion.

[0075] Referring to Figures 7E and 7F, the tape carrier TC attached toward the lower surface of the semiconductor chip 200 where the connection pads 220 are located is removed, and a lower package substrate 300 is formed on the surface from which the tape carrier TC has been removed, on which the semiconductor chip 200, the encapsulant 130, and the core insulating layer 110 are located.

[0076] The process of forming the lower package substrate 300 is performed by a redistribution process. That is, the lower package substrate 300 is formed by the redistribution process with a lower insulating layer 310 and a lower redistribution pattern 320, which are alternately formed with a lower via pattern 322 and a lower line pattern 321. The process resultant product positioned on the first adhesive layer CF1, which has been completed up to the process of FIG. 7F, is referred to as a first process structure in this specification. That is, the first process structure includes the semiconductor chip 200, the core layer 100, the encapsulant 130, and the lower package substrate 300.

[0077] 8A to 8J are cross-sectional views for explaining a method S1 for manufacturing a semiconductor package according to an exemplary embodiment of the present invention. The process explained in FIG. 8A to 8J corresponds to a step (S200A) of forming a first upper redistribution layer including a first upper insulating layer and a first upper redistribution pattern, and a step (S300) of forming a second upper redistribution layer including a second upper line pattern, a second upper via pattern, and a second upper insulating layer. In particular, FIG. 8A to FIG. 8D correspond to the step (S200A) of forming the first upper redistribution layer, and FIG. 8E to FIG. 8J correspond to the step (S300) of forming the second upper redistribution layer.

[0078] 8A, the first process structure with the first adhesive layer CF1 is removed from the first carrier CR1 and placed on the second carrier CR2. A second adhesive layer CF2 for attaching the lower package substrate 300 to the second carrier CR2 is interposed between the lower package substrate 300 and the second carrier CR2. The second adhesive layer CF2 is a copper foil for attachment, similar to the first adhesive layer CF1.

[0079] Referring to FIG. 8B, the first adhesive layer CF1 is removed from the encapsulant 130, and a first upper insulating layer 411A is formed on the encapsulant 130. In an exemplary embodiment, as described above, the encapsulant 130 is made of a build-up material. The first upper insulating layer 411A is also made of a build-up material. The encapsulant 130 and the first upper insulating layer 411A are made of the same build-up material, for example, the encapsulant 130 and the first upper insulating layer 411A are made of ABF (Ajinomoto Build-up Film). FIG. 8B corresponds to a step (S210A) of forming a first upper insulating layer including a build-up material on the encapsulant.

[0080] A certain amount of time has passed since the formation of the sealing material 130, and the build-up material contained in the sealing material 130 has hardened. On the other hand, a certain amount of time has not passed since the formation of the first upper insulating layer 411A, and the first upper insulating layer 411A has not yet hardened completely.

[0081] 8D, when the first seed layer SD1A is formed by electroless plating, the first seed layer SD1A is formed before the first upper insulating layer 411A is formed on the encapsulant 130 and completely hardens, and therefore the adhesion between the first seed layer SD1A and the first upper insulating layer 411A is greater than when the first seed layer SD1A is formed on the encapsulant 130. That is, the first upper rewiring pattern 420 based on the first seed layer SD1A is more stably formed and maintained.

[0082] Referring to Fig. 8C, a first upper via hole 420R is formed in the process product of Fig. 8B. The first upper via hole 420R penetrates the first upper insulating layer 411A and penetrates a portion of the encapsulant 130 to expose a portion of the core layer 100. The first upper via hole 420R is formed by, but is not limited to, laser processing. After the first upper via hole 420R is formed, a desmear process is performed. Fig. 8C corresponds to a step (S220) of forming a plurality of first upper via holes that penetrate the first upper insulating layer and expose a portion of the core layer by recessing a portion of the encapsulant.

[0083] Due to the characteristics of a process for forming an upper via hole, the first upper via pattern 421 has a tapered shape in which the horizontal width of the first upper via pattern 421 increases as it becomes farther from the lower package substrate 300 .

[0084] Referring to FIG. 8D, a first seed layer SD1A is formed by electroless plating. The first seed layer SD1A is formed in the first upper via hole 420R and on the upper surface of the first upper insulating layer 411A. The first seed layer SD1A conformally covers the bottom and sidewall of the first upper via hole 420R and the upper surface of the first upper insulating layer 411A. The first seed layer SD1A includes a conductive material. For example, the first seed layer SD1A includes one or more materials selected from the group consisting of copper (Cu), nickel (Ni), palladium (Pd), silver (Ag), chromium (Cr), titanium (Ti), and gold (Au). Then, a resist pattern having a guide opening is formed on the first seed layer SD1A. The resist pattern is made of a dry film resist (DFR). The guide opening is for forming the first upper redistribution pattern 420.

[0085] 8D is formed by performing electroless plating using the first seed layer SD1A as an electrode. As described above, the first upper redistribution pattern 420 includes the first upper via pattern 421, the first upper line pattern 422, and the first fine pattern FP1. The first upper via pattern 421 and the first upper line pattern 422 are formed in a single process.

[0086] In an exemplary embodiment, the first upper redistribution pattern 420 is formed through a plating process such as AP (Additive Process), SAP (Semi Additive Process), or MSAP (Modified Semi Additive Process). AP, SAP, and MSAP are additive processes for forming fine patterns, and the above three additive processes differ in the seed layer formation method and seed layer removal method. SAP is a method of plating a pattern using an electroless copper plating layer as a seed layer, and after the pattern is plated, the seed layer is removed by flash etching. MSAP refers to a method of using copper foil and an electroless copper plating layer as a seed layer and removing the seed layer by quick etching. In particular, the first upper redistribution pattern 420 is formed by SAP (Semi Additive Process).

[0087] Thereafter, the resist pattern is removed by, for example, a strip process. The first seed layer SD1A is removed by an etching process having an etching selectivity for the first seed layer SD1A compared to the first upper redistribution pattern 420. Figure 8D corresponds to a step of forming a first seed layer by an electroless plating process (S230A) and a step of forming a plurality of first upper via patterns and a plurality of first upper line patterns in a plurality of first upper via holes (S240).

[0088] 8E, a second upper insulating layer 412 is formed on a portion of an upper surface of the first upper insulating layer 411A and a portion of an upper surface of the first upper redistribution pattern 420. The second upper insulating layer 412 is made of an insulating material, for example, a photo-imagable dielectric (PID) resin. In this case, the second upper insulating layer 412 further includes an inorganic filler. For example, the second upper insulating layer 412 made of a photo-sensitive insulating resin is hardened to form a second upper via hole 430R, which is a via hole, through a photo process.

[0089] A sputtering process is performed to form a second seed layer SD2. The second seed layer SD2 is formed in the second upper via hole 430R and on the upper surface of the second upper insulating layer 412. The second seed layer SD2 conformally covers the bottom surface and sidewall of the second upper via hole 430R and the upper surface of the second upper insulating layer 412. The second seed layer SD2 includes a conductive material. For example, the second seed layer SD2 includes one or more materials selected from the group consisting of copper (Cu), nickel (Ni), palladium (Pd), silver (Ag), chromium (Cr), titanium (Ti), and gold (Au).

[0090] FIG. 8E corresponds to a step of forming a plurality of second upper via holes through the second upper insulating layer (S320) and a step of forming a second seed layer SD2 by a sputtering process (S330).

[0091] 8F, a plating resist layer RL is formed on a portion of the upper surface of the second seed layer SD2 formed on the second upper insulating layer 412. For example, the plating resist layer RL is a liquid photoresist layer. The plating resist layer RL is formed to have a guide opening. The guide opening serves as a guide for subsequently forming the second upper redistribution pattern 430. The guide opening is located above the second upper via hole 430R. That is, the guide opening exposes at least a portion of the upper surface of the second seed layer SD2.

[0092] FIG. 8F corresponds to the step of forming a liquid photoresist layer on the second upper insulating layer (S340).

[0093] 8G, a second upper redistribution pattern 430 is formed by plating the guide openings of the plating resist layer RL and the second upper via holes 430R. The second upper redistribution pattern 430 includes a second upper via pattern 431, a second upper line pattern 432, and a second fine pattern FP2. The second upper via pattern 431 is formed by plating the second upper via holes 430R, and the second upper line pattern 432 is formed by filling the guide openings of the plating resist layer RL. FIG. 8G corresponds to a step (S350) of forming a plurality of second upper via patterns and a plurality of second upper line patterns in a plurality of second upper via holes.

[0094] As described above, the line width of the second seed layer SD2 is smaller than the line width of the first seed layer SD1A.

[0095] Therefore, the line width of the second fine pattern FP2 of the second upper rewiring pattern 430 is equal to or smaller than the line width of the first fine pattern FP1 of the first upper rewiring pattern 420. For example, the first line width LW1A and the first line spacing LS1A of the first fine pattern FP1 are equal to or larger than the second line width LW2 and the second line spacing LS2 of the second fine pattern FP2. The first line width LW1A of the first fine pattern FP1 is 10 μm or less, the first line spacing LS1A is 13 μm or less, the second line width LW2 of the second fine pattern FP2 is 9 μm or less, and the second line spacing LS2 is 12 μm or less. Or, the second line width LW2 of the second fine pattern FP2 is 5 μm or less, and the second line spacing LS2 is 5 μm or less.

[0096] Therefore, in the semiconductor package manufacturing method S1 which is an exemplary embodiment of the present invention, the fine pattern of the second package substrate 400 corresponding to the rear redistribution layer can be made finer through materials and processes, thereby improving the performance of the semiconductor package manufactured through the semiconductor package manufacturing method S1.

[0097] Referring to FIG. 8H, the plating resist layer RL is peeled off and removed, and the second seed layer SD2 on which the second upper redistribution pattern 430 is not formed is removed by etching. The second seed layer SD2 is removed by an etching process having an etching selectivity for the second seed layer SD2 compared to the second upper redistribution pattern 430. Referring to FIG. 8I, a metal plating layer 433 is provided on a portion of the upper surface of the second upper line pattern 432. The metal plating layer 433 is made of a metal including, for example, gold (Au). Thereafter, an upper passivation layer 440 is formed on the upper surface of the second upper insulating layer 412 with a third hole 440R. The upper passivation layer 440 serves to protect the upper package substrate 400. The upper passivation layer 440 is made of an insulating material, for example, but not limited to, a build-up material.

[0098] 8J, the second carrier CR2 and the second adhesive layer CF2 for attaching the second carrier CR2 are removed. At least a portion of the lower line pattern 322 is exposed through the opening of the lower passivation layer 350, and the lower pads 330 are disposed on the exposed lower line pattern 322. The lower pads 330 are electrically connected to the external connection terminals 340, respectively. The semiconductor package 1 according to the exemplary embodiment of the present invention is manufactured through the semiconductor package manufacturing method S1 described above.

[0099] FIG. 9 is a flow chart for more specifically explaining the semiconductor package manufacturing method S1 according to an exemplary embodiment of the present invention.

[0100] FIG. 9 is a flowchart showing in more detail the step (S200B) of forming a first upper redistribution layer including a first upper insulating layer and a first upper redistribution pattern, and the step (S300) of forming a second upper redistribution layer including a second upper line pattern, a second upper via pattern, and a second upper insulating layer.

[0101] Referring to FIG. 9, the step of forming a first upper redistribution layer (S200B) includes a step of forming a first upper insulating layer including a PID on an encapsulant (S210B), a step of forming a plurality of first upper via holes penetrating the second upper insulating layer and recessing a portion of the first encapsulant to expose a portion of the core layer (S220), a step of forming a first seed layer by a sputtering process (S230B), and a step of forming a plurality of first upper via patterns and a plurality of first upper line patterns in the plurality of first upper via holes (S240).

[0102] The step of forming the second upper redistribution layer (S300) includes a step of forming a second upper insulating layer including a PID on the first upper redistribution layer (S310), a step of forming a plurality of second upper via holes through the second upper insulating layer (S320), a step of forming a second seed layer by a sputtering process (S330), a step of forming a liquid photoresist layer on the second upper insulating layer (S340), and a step of forming a plurality of second upper via patterns and a plurality of second upper line patterns in the plurality of second upper via holes (S350).

[0103] 9, a method S1 for manufacturing a semiconductor package according to an exemplary embodiment of the present invention will be described in conjunction with FIGS. 10A to 10J.

[0104] 10A to 10J are cross-sectional views illustrating a method S1 for manufacturing a semiconductor package according to an exemplary embodiment of the present invention. The process illustrated in FIG. 10A to 10J corresponds to a step S200B of forming a first upper redistribution layer including a first upper insulating layer and a first upper redistribution pattern, and a step S300 of forming a second upper redistribution layer including a second upper line pattern, a second upper via pattern, and a second upper insulating layer.

[0105] In particular, FIGS. 10A to 10D correspond to a step of forming a first upper redistribution layer (S200B), and FIGS. 10E to 10J correspond to a step of forming a second upper redistribution layer (S300).

[0106] 10A, the first process structure having the first adhesive layer CF1 is removed from the first carrier CR1 and placed on the second carrier CR2, and the second adhesive layer CF2 is interposed between the lower package substrate 300 and the second carrier CR2.

[0107] Referring to FIG. 10B, unlike FIG. 8B, the first adhesive layer CF1 is removed from the encapsulant 130, and a first upper insulating layer 411B is formed on the encapsulant 130. The first upper insulating layer 411B is made of an insulating material, for example, a photo imagable dielectric (PID) resin. In this case, the first upper insulating layer 411B further includes an inorganic filler. FIG. 10B corresponds to a step (S210B) of forming a first upper insulating layer including a PID on the encapsulant.

[0108] Referring to Fig. 10C, a first upper via hole 420R is formed in the process product of Fig. 8B. The first upper via hole 420R is formed by penetrating the first upper insulating layer 411B and penetrating a part of the encapsulant 130 so as to expose a part of the core layer 100. For example, the first upper insulating layer 411B made of a photosensitive insulating resin is hardened and a second upper via hole 430R, which is a via hole, is formed through a photo process. Fig. 10C corresponds to the step (S220) of forming a plurality of first upper via holes penetrating the first upper insulating layer and exposing a part of the core layer by recessing a part of the first encapsulant.

[0109] Due to the characteristics of a process for forming an upper via hole, the first upper via pattern 421 has a tapered shape in which the horizontal width of the first upper via pattern 421 increases as it becomes farther from the lower package substrate 300 .

[0110] Referring to FIG. 10D, a sputtering process is performed to form a first seed layer SD1B. The first seed layer SD1B is formed in the first upper via hole 420R and on the upper surface of the first upper insulating layer 411B. The first seed layer SD1B conformally covers the bottom and sidewall of the first upper via hole 420R and the upper surface of the first upper insulating layer 411B. The first seed layer SD1B includes a conductive material. For example, the first seed layer SD1B includes one or more materials selected from the group consisting of copper (Cu), nickel (Ni), palladium (Pd), silver (Ag), chromium (Cr), titanium (Ti), and gold (Au).

[0111] A first upper redistribution pattern 420 is formed on the first seed layer SD1B. In an exemplary embodiment, the first upper redistribution pattern 420 is formed through a plating process such as an additive process (AP), a semi-additive process (SAP), or a modified semi-additive process (MSAP). In particular, the first upper redistribution pattern 420 is formed by a semi-additive process (SAP).

[0112] The line width of the first seed layer SD1B formed by the sputtering process is smaller than the line width of the first seed layer formed through electroless plating, so that the line width of the first fine pattern FP1 of the first upper rewiring pattern 420 is made finer.

[0113] For example, the first line width LW1B of the first fine pattern FP1 is 9 μm or less, and the first line spacing LS1B is 12 μm or less, and similarly, the second line width LW2 of the second fine pattern FP2 is 9 μm or less, and the second line spacing LS2 is 12 μm or less. Alternatively, the first line width LW1B and the second line width LW2 of the first fine pattern FP1 are 5 μm or less, and the first line spacing LS1B and the second line spacing LS2 are 5 μm or less.

[0114] Therefore, the semiconductor package manufacturing method S1, which is an exemplary embodiment of the present invention, further fines the circuit of the second package substrate 400, which corresponds to the rear redistribution layer, thereby improving the performance of the semiconductor package manufactured through the semiconductor package manufacturing method S1.

[0115] FIG. 10D corresponds to a step of forming a first seed layer by a sputtering process (S230B), and a step of forming a plurality of first upper via patterns and a plurality of first upper line patterns in a plurality of first upper via holes (S240).

[0116] 10E to 10J are substantially the same as the above-described processes of FIGS. 8E to 10J, and therefore a separate description thereof will be omitted.

[0117] Through the above-described semiconductor package manufacturing method S1, the semiconductor package 1A according to the exemplary embodiment of the present invention is manufactured.

[0118] Although the embodiments of the technical concept of the present invention have been described above with reference to the drawings, those skilled in the art will understand that the present invention can be embodied in other specific forms without changing the technical concept or essential features of the present invention. Therefore, the above-described embodiments are illustrative in all respects and should not be construed as limiting. [Explanation of symbols]

[0119] 1, 1A, 2, 2A Semiconductor Packages 100 Core Layer 110 Core insulation layer 121 Core wiring layer 122 Corebia 130 Encapsulating material 200 Semiconductor Chips 220 Connection Pad 300 Lower package substrate 310 Lower insulating layer 320 Lower rewiring pattern 321 Lower Line Pattern 322 bottom via pattern 330 Lower Pad 400 Top Package Substrate 411A, 411B First upper insulating layer 412 Second upper insulating layer 420 1st upper rewiring pattern 421 1st upper via pattern 422 1st Upper Line Pattern 430 2nd upper rewiring pattern 431 2nd upper via pattern 432 2nd Upper Line Pattern 433 Metal plating layer 440 Top passivation layer 500 Upper semiconductor device RDL1 1st upper redistribution layer RDL2 2nd upper redistribution layer SD1, SD1A, SD1B 1st seed layer SD2 2nd seed layer

Claims

1. a lower package substrate including a lower insulating layer; a first semiconductor device mounted on the lower package substrate; a core layer disposed on the lower package substrate and spaced apart laterally from the first semiconductor device, the core layer including a core substrate, a core via penetrating the core substrate, and a core pattern connecting the core vias; a sealing material surrounding the first semiconductor device and covering an upper portion of the core layer; an upper package substrate including a first upper insulating layer, a first upper redistribution layer including a first upper redistribution pattern disposed on the first upper insulating layer and disposed on the encapsulant, and a second upper insulating layer disposed on the first upper insulating layer, and a second upper redistribution layer including a second upper redistribution pattern disposed on the second upper insulating layer; a first line width of a first fine pattern included in the first upper redistribution pattern is equal to or larger than a corresponding second line width of a second fine pattern included in the second upper redistribution pattern; a first line spacing of a first fine pattern included in the first upper redistribution pattern is equal to or larger than a corresponding second line spacing of a second fine pattern included in the second upper redistribution pattern.

2. the first upper redistribution pattern includes a first upper via pattern penetrating the first upper insulating layer, and a first upper line pattern disposed on the first upper insulating layer and electrically connected to the first upper via pattern, 2. The semiconductor package of claim 1, wherein the first upper via patterns each penetrate the first upper insulating layer and the encapsulant, and the first upper insulating layer and the encapsulant contact at least a portion of a side of each of the first upper via patterns.

3. the second upper redistribution pattern includes a second upper via pattern penetrating the second upper insulating layer, and a second upper line pattern disposed on the second upper insulating layer and electrically connected to the second upper via pattern, 3. The semiconductor package of claim 2, wherein the first upper via pattern and the second upper via pattern have a tapered shape in which a horizontal width increases as the pattern moves away from the lower package substrate.

4. 4. The semiconductor package of claim 3, wherein the first upper via pattern and the second upper via pattern are stacked vias or staggered vias.

5. 5. The semiconductor package of claim 4, wherein the first upper insulating layer includes a build-up material, and the second upper insulating layer includes a photo image-able dielectric (PID).

6. the first line width is 5 μm or more and 10 μm or less, and the first line spacing is 5 μm or more and 13 μm or less; 6. The semiconductor package of claim 5, wherein the second line width is 3 [mu]m to 9 [mu]m, and the second line spacing is 3 [mu]m to 12 [mu]m.

7. The semiconductor package of claim 6 , wherein the first upper insulating layer and the encapsulant comprise the same material.

8. 4. The semiconductor package of claim 3, wherein the lower insulating layer and the second upper insulating layer are made of the same material, and the lower insulating layer and the second upper insulating layer include a PID.

9. 4. The semiconductor package of claim 3, wherein the first upper insulating layer and the encapsulant are made of different materials, but the first upper insulating layer and the second upper insulating layer include the same material.

10. 10. The semiconductor package of claim 9, wherein the encapsulant comprises a build-up material, and the first upper insulating layer and the second upper insulating layer comprise a photo image-able dielectric (PID).

11. 11. The semiconductor package of claim 10, wherein the first line width and the second line width are each in the range of 3 [mu]m to 9 [mu]m, and the first line spacing and the second line spacing are each in the range of 3 [mu]m to 12 [mu]m.

12. 4. The semiconductor package of claim 3, further comprising a second semiconductor device mounted on the upper package substrate.

13. forming a first process structure including a lower package substrate, a first semiconductor device mounted on the lower package substrate, a core layer mounted on the lower package substrate and spaced laterally from the first semiconductor device, and an encapsulant surrounding the first semiconductor device on the lower package substrate and interposed on the core layer; forming a first upper insulating layer on the encapsulant of the first process structure, the first upper redistribution layer including a first upper redistribution pattern provided on the first upper insulating layer; forming a second upper redistribution layer including a second upper insulating layer on the first upper redistribution layer and a second upper redistribution pattern provided on the second upper insulating layer; The step of forming the first upper redistribution layer includes: forming the first upper insulating layer on the encapsulant; forming a plurality of first upper via holes penetrating the first upper insulating layer and recessing portions of the encapsulant to expose portions of the core layer; forming a first seed layer on the first upper insulating layer having the first upper via holes; forming a first upper via pattern in the first upper via holes to be electrically connected to the core layer, and forming a first upper line pattern on the first upper via pattern; The step of forming the second upper redistribution layer includes: forming a second upper insulating layer on the first upper redistribution layer; forming a plurality of second upper via holes penetrating the second upper insulating layer; forming a second seed layer on the second upper insulating layer having the plurality of second upper via holes; forming a plating resist layer on the second upper insulating layer on which the second seed layer is formed; forming a second upper via pattern in the plurality of second upper via holes and forming a second upper line pattern on the second upper via pattern; the first upper insulating layer and the second upper insulating layer are made of different materials, the first upper redistribution pattern and the second upper redistribution pattern are formed such that a first line width of a first fine pattern included in the first upper redistribution pattern is equal to or larger than a corresponding second line width of a second fine pattern included in the second upper redistribution pattern; the first upper redistribution pattern and the second upper redistribution pattern are formed such that a first line interval of a first fine pattern included in the first upper redistribution pattern is equal to or larger than a corresponding second line interval of a second fine pattern included in the second upper redistribution pattern; 2. A method for manufacturing a semiconductor package, comprising: forming the first seed layer by electroless plating; and forming the second seed layer by a sputtering process.

14. 14. The method of claim 13, wherein the first upper insulating layer is made of a build-up material, and the second upper insulating layer is made of a photo image-able dielectric (PID).

15. The first line width of the first fine pattern is 5 μm or more and 10 μm or less, and the first line spacing is 5 μm or more and 13 μm or less; 14. The method of claim 13, wherein the second line width of the second fine pattern is 3 [mu]m to 9 [mu]m, and the second line spacing is 3 [mu]m to 12 [mu]m.

16. The first upper redistribution pattern is formed by a semi-additive process (SAP), 14. The method of claim 13, wherein the plating resist layer is a liquid photoresist (LPR).

17. forming a first process structure including a lower package substrate, a first semiconductor device mounted on the lower package substrate, a core layer mounted on the lower package substrate and spaced laterally from the first semiconductor device, and an encapsulant disposed on the lower package substrate and surrounding the first semiconductor device; forming a first upper insulating layer on the encapsulant of the first process structure, the first upper redistribution layer including a first upper redistribution pattern provided on the first upper insulating layer; forming a second upper redistribution layer including a second upper insulating layer on the first upper redistribution layer and a second upper redistribution pattern provided on the second upper insulating layer; The step of forming the first upper redistribution layer includes: forming the first upper insulating layer on the encapsulant; forming a plurality of first upper via holes penetrating the first upper insulating layer and recessing portions of the encapsulant to expose portions of the core layer; forming a first seed layer on the first upper insulating layer having the first upper via holes; forming a first upper via pattern in the first upper via holes to be electrically connected to the core layer, and forming a first upper line pattern on the first upper via pattern; The step of forming the second upper redistribution layer includes: forming a second upper insulating layer on the first upper redistribution layer; forming a plurality of second upper via holes penetrating the second upper insulating layer; forming a second seed layer on the second upper insulating layer having the plurality of second upper via holes; forming a plating resist layer on the second upper insulating layer on which the second seed layer is formed; forming a second upper via pattern in the plurality of second upper via holes and forming a second upper line pattern on the second upper via pattern; the first upper insulating layer and the second upper insulating layer are made of the same material, 2. A method for manufacturing a semiconductor package, wherein the first seed layer and the second seed layer are each formed by a sputtering process.

18. 18. The method of claim 17, wherein the first upper insulating layer and the second upper insulating layer are each made of a photo image-able dielectric (PID).

19. a first line width of a first fine pattern included in the first upper redistribution pattern and a second line width of a second fine pattern included in the second upper redistribution pattern are from 3 μm to 9 μm, 20. The method of claim 18, wherein the first line spacing of the first fine pattern and the second line spacing of the second fine pattern are in the range of 3 [mu]m to 12 [mu]m, respectively.

20. The first upper redistribution pattern is formed by a semi-additive process (SAP), 20. The method of claim 19, wherein the plating resist layer is a liquid photoresist (LPR).

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