Manufacturing method of packaging substrate and packaging substrate using the same

Abstract

To provide a packaging substrate which prevents an undulation phenomenon due to a gap between elements and / or a gap between a cavity portion and an element, and a manufacturing method thereof.SOLUTION: A packaging substrate includes a core layer 22 including a glass substrate 21 having a first surface and a second surface facing each other and a cavity portion passing through the glass substrate, wherein a cavity module is disposed in the cavity portion, the cavity module comprises a cavity element 40 and a first insulating layer 61 enclosing the cavity element. The first insulation layer is formed on some surfaces other than one surface or on all the surface of the cavity element, and a second insulating layer 62 is further incorporated into the remaining portion of the cavity portion other than the cavity module, and the first insulating layer and the second insulating layer have different dielectric constants.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] This document relates to a packaging substrate, a semiconductor package, a method for manufacturing a packaging substrate, and a method for manufacturing a semiconductor package. [Background technology]

[0002] In the manufacture of electronic components, the process of forming circuits on a semiconductor wafer is called the front-end process (FE), and the process of assembling the wafer so that it can be used in an actual product is called the back-end process (BE). This back-end process includes the packaging process.

[0003] The four core technologies of the semiconductor industry that have enabled the rapid development of electronic products in recent years are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. Semiconductor technology has evolved into various forms, such as nano-level line widths below the micron level, more than 10 million cells, high-speed operation, and large amounts of heat dissipation, but the technology to perfectly package these has not been fully supported. As a result, the electrical performance of semiconductors is sometimes determined by the packaging technology and the resulting electrical connections rather than the performance of the semiconductor technology itself.

[0004] The packaging substrate is made of ceramic or resin. Ceramic substrates such as silicon substrates have high resistance or high dielectric constant, so it is not easy to mount high-performance, high-frequency semiconductor elements on them. Resin substrates can mount relatively high-performance, high-frequency semiconductor elements, but there is a limit to how much the wiring pitch can be reduced.

[0005] Recently, glass plates can be used as high-end packaging substrates. By forming through holes in the glass substrate and filling the through holes with conductive materials, the wiring length between the device and the motherboard can be shortened, resulting in excellent electrical characteristics.

[0006] Furthermore, the semiconductor package may generate heat during operation, and may further include a heat dissipation means for dissipating such heat.

[0007] Related prior art includes U.S. Patent Publication US2022 / 0293560A1 and Korean Patent Publication No. 10-2018-0142742. Summary of the Invention [Problem to be solved by the invention]

[0008] An object of the embodiment is to provide a packaging substrate manufacturing method capable of improving an undulation phenomenon that occurs due to gaps between cavity elements and / or gaps between a cavity portion and a cavity element in a packaging substrate using a glass substrate, and a packaging substrate using the same.

[0009] In addition, an object of the embodiment is to provide a method for manufacturing a packaging substrate, which efficiently manufactures a packaging substrate by forming a first insulating layer on the entire surface or the entire surface except for one surface of a cavity element disposed in a cavity portion of a glass substrate, and forming a second insulating layer that is laminated on the first surface and the second surface of the glass substrate, and a packaging substrate using the same. [Means for solving the problem]

[0010] To achieve the above object, a packaging substrate according to one embodiment includes a glass substrate having a first surface and a second surface facing each other, and a core layer including a cavity portion penetrating the glass substrate, a cavity module is disposed in the cavity portion, the cavity module includes a cavity element and a first insulating layer surrounding the cavity element, the first insulating layer includes a second insulating layer disposed on the entire surface except for one surface of the cavity element and at least a portion of the cavity portion other than the cavity module is disposed so as to be embedded in the portion, and the first insulating layer and the second insulating layer may be characterized in that they have different dielectric constants.

[0011] The first insulating layer may have a lower dielectric constant than the second insulating layer.

[0012] The high frequency relative dielectric constant Dk is the relative dielectric constant at a high frequency of 5.8 GHz, and the difference between the high frequency relative dielectric constant Dk1 of the first insulating layer and the high frequency relative dielectric constant Dk2 of the second insulating layer may be 0.1 or more.

[0013] The first insulating layer may have a dielectric loss factor Df1, the second insulating layer may have a dielectric loss factor Df2, and the difference between Df1 and Df2 may be 0.0001 or more.

[0014] The first insulating layer may include liquid crystal polymer (LCP), epoxy molding compound (EMC), Ajinomoto build-up film (ABF), or modified polyimide (MPI).

[0015] The second insulating layer may include an insulating compound.

[0016] The insulating mixture may include a mixture of inorganic particles and a polymeric resin.

[0017] A connection electrode may be disposed on the cavity element.

[0018] The cavity elements may include passive or active elements.

[0019] A first insulating layer via may be disposed in the first insulating layer, the first insulating layer penetrating the first insulating layer.

[0020] The first insulating layer via may be partially or entirely filled with an electrode material.

[0021] Meanwhile, in order to achieve the above object, a method for manufacturing a packaging substrate according to one embodiment includes the steps of preparing a glass substrate having a cavity portion and a cavity module, arranging the cavity module in the cavity portion, and laminating a second insulating layer on the glass substrate, wherein the cavity module includes a cavity element and a first insulating layer surrounding the cavity element, and the first insulating layer may be arranged on the entire surface or the entire surface except for one side of the cavity element.

[0022] The first insulating layer and the second insulating layer may have different dielectric constants.

[0023] The first insulating layer may include liquid crystal polymer (LCP), epoxy molding compound (EMC), Ajinomoto build-up film (ABF), or modified polyimide (MPI).

[0024] The second insulating layer may include Ajinomoto Build-up Film (ABF) or Epoxy Molding Compound (EMC).

[0025] A connection electrode may be formed on the cavity element. Effect of the Invention

[0026] The method for manufacturing a packaging substrate according to the embodiment and the packaging substrate using the same can prevent an undulation phenomenon from occurring in a cavity portion in which a cavity element is embedded, thereby significantly improving the quality of the packaging substrate.

[0027] In addition, since the undulation phenomenon of the cavity portion is improved, leakage current can be prevented from occurring in the cavity element including the passive element and / or the active element, and the quality of the packaging substrate can be significantly improved.

[0028] In addition, by forming a first insulating layer having a dielectric constant different from that of the second insulating layer on the entire surface or the entire surface except for one surface of the cavity element, it is possible to prevent short circuits due to contact between cavity elements arranged side by side, and it is possible to prevent short circuits that may occur unintentionally during the manufacturing process of forming an electrically conductive layer on the side surface of the cavity portion. [Brief description of the drawings]

[0029] [Figure 1] 1 is a conceptual diagram illustrating a cross-sectional structure of a packaging substrate according to an embodiment; [Diagram 2] 13 is a conceptual diagram illustrating a cross-sectional structure of a packaging substrate according to another embodiment; FIG. [Diagram 3] 1A and 1B are schematic cross-sectional views illustrating a portion of a packaging substrate according to an embodiment. [Figure 4] 1 is a flowchart illustrating a process of forming a core distribution layer in a process of manufacturing a packaging substrate according to an embodiment. [Diagram 5] 1 is a flowchart illustrating a process of forming an insulating layer in a process of manufacturing a packaging substrate according to an embodiment. [Figure 6] 1 is an example of a cross-sectional structure of a core layer of a packaging substrate produced according to an embodiment. [Figure 7]1 is a flowchart illustrating a cross-sectional view of a method for manufacturing a packaging substrate according to an embodiment, in which S represents the formation of a first insulating layer, P1 represents the arrangement of elements, P2 represents the formation of a second insulating layer (upper part), P3 represents the formation of a second insulating layer (lower part), and P4 represents curing (upper / lower part). [Figure 8] 1 is a flowchart illustrating a cross-sectional view of a method for manufacturing a packaging substrate according to another embodiment, in which P1 represents element arrangement, S represents formation of a first insulating layer, P2 represents formation of a second insulating layer (upper part), P3 represents formation of a second insulating layer (lower part), and P4 represents curing (upper / lower part). BEST MODE FOR CARRYING OUT THEINVENTION

[0030] The following detailed description is provided to facilitate a comprehensive understanding of the method, device and / or system described herein. However, various changes, modifications and equivalents of the method, device and / or system described herein will become apparent after the contents presented in this application are understood. For example, the order of operations described herein is merely exemplary and is not limited to the operations described herein. Except for steps that necessarily proceed in a certain order, the order of operations may be changed depending on the understanding of the contents presented in this application. In addition, the description of known features may be omitted to improve clarity and conciseness after the disclosure of this application is understood. However, the omission of such features and their descriptions is not intended to be an admission of common knowledge.

[0031] The features described herein may be embodied in different forms and are not to be construed as being limited to the examples described herein, but rather the embodiments described herein are provided to illustrate some of the many possible implementations of the methods, devices and / or systems described herein that will become apparent upon reading the disclosure of this application.

[0032] As used herein, terms such as "first," "second," and "third" may be used to describe various members, components, regions, layers, or sections, but are not intended to limit these members, components, regions, layers, or sections to these words. Instead, such terms are used to distinguish one member, component, region, layer, or section from another member, component, region, layer, or section. Thus, a first member, component, region, layer, or section referred to in any embodiment described herein could also be a second member, component, region, layer, or section without departing from the teachings of the embodiment.

[0033] Throughout the specification, when an element such as a layer, region, or substrate is described as being "on," "connected to," or "bonded" to another element, it may be described as being directly "on," "connected," or "bonded" to the other element, or there may be one or more intervening elements between them. In contrast, when an element is described as being "directly on," "directly connected," or "directly bonded," there may not be any other intervening elements between them. Similarly, expressions such as "between" and "directly between," and "adjacent" and "directly adjacent" may be interpreted as previously described.

[0034] The terms used herein are merely for describing particular examples and are not used to limit the disclosure. As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise. As used herein, the term "and / or" includes any one or more combinations of the associated listed items. As used herein, the terms "comprises," "comprises," and "has" specify the presence of stated features, numbers, operations, elements, components, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, operations, elements, components, and / or combinations thereof. As used herein, the use of the term "can" in connection with an example or embodiment (e.g., what the example or embodiment can include or embody) means that there is at least one example or embodiment in which such feature is included or embodied, but not all examples are limited thereto.

[0035] In this application, "B is located on A" means that B is in direct contact with A or that B is disposed on A with another layer or structure therebetween, and therefore should not be construed as B being in direct contact with A.

[0036] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention pertains. Terms, such as those defined in commonly used dictionaries, should be interpreted to have a meaning consistent with their meaning in the context of the prior art and the present invention, and should not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0037] In one or more of the above examples, the term "A and / or B" means "A, B, or A and B."

[0038] In one or more of the above examples, terms such as "first," "second," "A," or "B" are used to distinguish identical terms from one another.

[0039] In one or more of the above instances, the singular forms are to be construed as including the plural forms as well as the singular forms unless specifically stated otherwise.

[0040] FIG. 1 is a conceptual diagram illustrating the cross-sectional structure of a packaging substrate according to an embodiment, FIG. 2 is a conceptual diagram illustrating the cross-sectional structure of a packaging substrate according to another embodiment, and FIGS. 3(a) and (b) are conceptual diagrams illustrating the cross-section of a portion of a packaging substrate according to an embodiment.

[0041] To achieve the above objective, the semiconductor device 100 of the embodiment includes a semiconductor element section 30 in which one or more semiconductor elements 32, 34, and 36 are located, a packaging substrate 20 electrically connected to the semiconductor elements, and a motherboard 10 electrically connected to the packaging substrate 20, which transmits external electrical signals to and connects the semiconductor elements 32, 34, and 36 to each other.

[0042] The packaging substrate 20 according to one embodiment includes a core layer 22, an upper layer 26 disposed on one surface of the core layer 22, and a cavity portion 28 in which a cavity element 40 can be disposed.

[0043] The semiconductor element section 30 means an element mounted on a semiconductor device, and is mounted on the packaging substrate 20 by connection electrodes or the like. Specifically, the semiconductor element section 30 may be, for example, a computing element such as a CPU or a GPU (first element: 32, second element: 34), a storage element such as a memory chip (third element: 36), or the like, but any semiconductor element mounted on a semiconductor device can be used without any restrictions.

[0044] The motherboard 10 may be a motherboard such as a printed circuit board or a printed wiring board.

[0045] The packaging substrate 20 may optionally further include a lower layer (not shown) located below the core layer.

[0046] The core layer 22 may include a glass substrate 21 including a first region 221 having a first thickness 211 and a second region 222 adjacent to the first region 221 and having a second thickness 212 that is thinner than the first thickness; a plurality of core vias 23 penetrating the glass substrate 21 in the thickness direction; and a core distribution layer 24 located on the surface of the glass substrate 21 or the core vias 23 and electrically connecting a first surface 213 of the glass substrate 21 to a second surface 214 opposite the first surface via the core vias 23.

[0047] The second region 222 of the core layer 22 may serve as a cavity structure.

[0048] In the same area, the glass substrate 21 has a first surface 213 and a second surface 214 facing each other, and the two surfaces are generally parallel to each other, so that the glass substrate 21 has a constant thickness throughout.

[0049] An internal space 281 formed by the difference in thickness between the first section 221 and the second section 222 serves to accommodate a part or the whole of the cavity element 40 .

[0050] The glass substrate 21 may include core vias 23 penetrating the first surface 213 and the second surface 214. The core vias 23 may be formed in both the first area 221 and the second area 222, and may be formed at a desired pitch and pattern.

[0051] Conventionally, packaging substrates for semiconductor devices have been applied in the form of a laminate of a silicon substrate and an organic substrate. In the case of a silicon substrate, due to the characteristics of a semiconductor, there is a risk of parasitic elements being generated when applied to high-speed circuits, and there is a drawback in that the power loss is relatively large. In addition, in the case of an organic substrate, a large area is required to form an increasingly complex distribution pattern, which does not fit with the trend of manufacturing electronic devices that are becoming ultra-miniaturized. In order to form a complex distribution pattern within a set size, it is necessary to substantially fine the pattern, but there is a practical limit to the fine pattern due to the characteristics of materials such as polymers applied to organic substrates.

[0052] In the embodiment, to solve this problem, the glass substrate 21 is used as a support for the core layer 22. In addition, by using the glass substrate 21 and the core via 23 formed penetrating the glass substrate 21, the length of electrical flow is further shortened, providing a packaging substrate 20 that is more compact, has faster response, and has less loss characteristics.

[0053] The glass substrate 21 is preferably a glass substrate used in semiconductors. For example, a borosilicate glass substrate or an alkali-free glass substrate may be used, but is not limited thereto.

[0054] The core via 23 penetrates the glass substrate 21. The core via 23 may be formed by removing a predetermined region of the glass substrate 21, specifically, by etching a plate-shaped glass by a physical and / or chemical method.

[0055] Specifically, the formation of the core via 23 may be achieved by forming a defect (groove) on the surface of the glass substrate using a laser or other method, followed by chemical etching, laser etching, etc., but is not limited thereto.

[0056] Based on a unit area (1 cm×1 cm) of the glass substrate 21, the number of the core vias 23 may be 100 to 3,000, 100 to 2,500, or 225 to 1,024. When such pitch conditions are satisfied, the formation of an electrically conductive layer and the performance of the packaging substrate can be improved.

[0057] The core distribution layer 24 includes a core distribution pattern 241, which is an electrically conductive layer that electrically connects the first and second surfaces of the glass substrate through a through via, and a core insulating layer 223 that surrounds the core distribution pattern. The core layer 22 has an electrically conductive layer formed therein through a core via, and serves as an electrical path across the glass substrate 21, and connects the upper and lower parts of the glass substrate over a relatively short distance, thereby allowing for faster electrical signal transmission and low loss characteristics. The electrically conductive layer may be, for example, a copper plating layer, but is not limited thereto.

[0058] The shape of the cavity portion 28 is not limited and may be substantially circular, triangular, rectangular, hexagonal, octagonal, cross-shaped, or the like.

[0059] The cavity element 40 may be generally cylindrical, rectangular, or polygonal in shape.

[0060] The cavity portion 28 may include a cavity distribution pattern, which is an electrically conductive layer that electrically connects the cavity element 40 and the core distribution layer 24, and an insulating layer that surrounds the cavity distribution pattern.

[0061] Meanwhile, the cavity portion according to another embodiment may be embodied in a form penetrating the first surface 213 and the second surface 214 of the glass substrate 21. In this case, the cavity portion may be formed by a process similar to the process of forming the core via 23, and the area and shape penetrating the glass substrate 21 may be different from those of the core via 23.

[0062] In this embodiment, an insulating layer may be formed in the cavity portion after the cavity element 40 is arranged in the cavity portion. That is, an insulating layer may be formed in the cavity portion through the process of forming the core insulating layer 223 described above.

[0063] The core distribution pattern 241 may be patterned so as to be electrically connectable with the cavity element 40 .

[0064] The cavity element 40 may include an active element such as a transistor, or a power transfer element, ie, a passive element, such as a multi-layer ceramic capacitor (MLCC).

[0065] When an element such as a transistor that converts electrical signals between the motherboard and the semiconductor element portion to an appropriate level is applied as the cavity element 40, a transistor or the like is applied to the passage of the packaging substrate 20, thereby providing a semiconductor device 100 that is more efficient and has a higher speed.

[0066] In addition, power transfer devices such as multilayer ceramic capacitors (MLCCs) play an important role in the performance of semiconductor devices. Power transfer devices, which are passive devices, are generally applied to semiconductor devices in numbers of at least 200, and the performance of the device is also affected by the characteristics of the electrical conductive layer around the device when transferring power. In one embodiment, a non-circular core via can be applied to such power transfer devices, where an electrical conductive layer with low resistance is required.

[0067] Meanwhile, passive elements such as capacitors may be individually inserted and applied as the cavity element 40, or an element group including a number of passive elements embedded between insulating layers (cavity element insulating layers) may be formed with electrodes exposed and then inserted into the cavity element. In the latter case, the workability of manufacturing the packaging substrate may be further improved, and it is more advantageous for insulating layers to be positioned sufficiently and reliably in spaces between complex elements.

[0068] The glass substrate 21 acts as an intermediate or mediator connecting the semiconductor device part 30 and the motherboard 10 at the upper and lower parts, respectively, and the core vias 23 act as a path for transmitting electrical signals, thereby ensuring smooth signal transmission.

[0069] A top layer 26 is positioned on the first surface 213 .

[0070] The upper layer 26 may include an upper distribution layer 25 and an upper surface connection layer 27 located on the upper distribution layer 25, and the top surface of the upper layer 26 may be protected by a cover layer 60 having an opening formed therein to which a connection electrode of a semiconductor element portion can directly abut.

[0071] The upper distribution layer 25 may include an upper insulating layer 253 located on the first surface, and an upper distribution pattern 251 having a predetermined pattern and being an electrically conductive layer to which at least a portion of the core distribution layer 24 is electrically connected, the upper distribution pattern 251 being embedded in the upper insulating layer 253.

[0072] The upper insulating layer 253 may be any material that can be used as an insulating layer for a semiconductor device or a packaging substrate, such as, but not limited to, an epoxy resin containing a filler.

[0073] The insulator layer may be formed by forming a coating layer and curing it, or may be formed by laminating an insulator film in an uncured or semi-cured state onto the core layer 22 and curing it. In this case, if a reduced pressure lamination method is used, the insulator can be filled into the inner space of the core via 23, allowing for efficient process.

[0074] According to one embodiment, even if multiple insulating layers are applied by stacking, it may be difficult to substantially separate the insulating layers, and the multiple insulating layers are collectively referred to as the upper insulating layer. Also, the core insulating layer 223 and the upper insulating layer 253 may be made of the same insulating material, in which case the boundary between them is not substantially separated. Alternatively, according to another embodiment, the boundary between the insulating layers may be created by setting different pressures and temperatures for curing the multiple insulating layers.

[0075] The upper distribution pattern 251 means an electrically conductive layer located in the upper insulating layer 253 in a predetermined shape, and may be formed, for example, by a build-up layer method. In particular, an insulating layer is formed, unnecessary parts of the insulating layer are removed, an electrically conductive layer is formed by a method such as copper plating, and an unnecessary part of the electrically conductive layer is selectively removed, an insulating layer is formed again on the electrically conductive layer, the unnecessary parts are removed again, and an electrically conductive layer is formed by a method such as plating, and the like. By repeating these methods, the upper distribution pattern 251 having an electrically conductive layer formed vertically or horizontally in a desired pattern can be formed.

[0076] The upper distribution pattern 251 is located between the core layer 22 and the semiconductor device part 30, and is formed to include a fine pattern in at least a part thereof so that electrical signals can be smoothly transmitted to the semiconductor device part 30 and the intended complex pattern can be fully accommodated. In this case, the fine pattern may have a width and interval each of less than 4 μm, 3.5 μm or less, 3 μm or less, 2.5 μm or less, or 1 to 2.3 μm (the same applies to the following explanation of the fine pattern).

[0077] The upper connection layer 27 includes an upper connection pattern 272 located on the upper insulating layer 253 and at least a portion of which is electrically connected to the upper distribution pattern 251, and an upper connection electrode 271 electrically connecting the semiconductor element portion 30 and the upper connection pattern 272.

[0078] The upper surface connection pattern 272 may be located on one surface of the upper insulating layer 253, or may be embedded with at least a portion thereof exposed on the upper insulating layer. For example, when the upper surface connection pattern is located on one surface of the upper insulating layer, the upper insulating layer may be formed by a method such as plating, and when the upper surface connection pattern is embedded with a portion thereof exposed on the upper insulating layer, a copper plating layer may be formed, and then a portion of the insulating layer or the electrically conductive layer may be removed by a method such as surface polishing or surface etching.

[0079] The upper connection pattern 272 may include a fine pattern at least in a portion thereof, like the above-mentioned upper distribution pattern 251. The upper connection pattern 272 including such a fine pattern can electrically connect more elements in a small area, facilitate the connection of electrical signals between elements or with the outside, and enable more integrated packaging.

[0080] The upper connection electrodes 271 may be directly connected to the semiconductor device part 30 via terminals or the like, or may be connected via device connection parts 51 such as solder balls.

[0081] The cavity portion 28 is located above and / or below the second region 222 and may include a cavity distribution layer 282 electrically connected to the core distribution pattern 241 and an internal space 281 in which the cavity element 40 is located.

[0082] Specifically, the thickness of the glass substrate 21 in the second region 222 is thinner than that in the first region 221, and the cavity element 40 can be located in an internal space 281 formed by the difference in thickness. In addition, the core via 23 and the core distribution layer 24 formed in the glass substrate 21 serve as an electrical connection structure that connects the cavity element 40 to an external element.

[0083] Also, as described above, a cavity portion may be generated in the first area 221, i.e., penetrating the first surface 213 and the second surface 214 of the glass substrate 1, rather than the second area 222, and a cavity element 40 may be arranged in the cavity portion.

[0084] The packaging substrate 20 is also connected to the motherboard 10. The core distribution pattern 241 located on at least a portion of the second surface 214 of the core layer 22 may be directly connected to a terminal of the motherboard 10, or may be electrically connected to the motherboard 10 via a board connection part 52 such as a solder ball. The core distribution pattern 241 in contact with the motherboard 10 may be connected to the motherboard 10 via a lower layer (not shown) located under the core layer 22.

[0085] For example, the packaging substrate 20 located between the semiconductor device unit 30 and the motherboard 10 may not include any additional substrate other than the glass substrate 21 .

[0086] Conventionally, when connecting a device to a motherboard, an interposer and an organic substrate are laminated between them. This is understood to be applied in such a multi-layer form for at least two reasons. One is that there is a scale problem when directly bonding a fine pattern of a device to a motherboard, and the other is that a problem of wiring damage may occur due to the difference in thermal expansion coefficient during the bonding process or the operation of the semiconductor device. In the embodiment, this problem is solved by applying a glass substrate with a thermal expansion coefficient similar to that of a semiconductor device, and forming a fine pattern with a fine scale sufficient for mounting a device on the first surface of the glass substrate and its upper layer.

[0087] Hereinafter, a method for manufacturing a packaging substrate according to an embodiment of the present invention will be described.

[0088] 4 and 5 are flow charts illustrating a cross-sectional view of a manufacturing process of a packaging substrate according to an embodiment.

[0089] First, as shown in (a) of FIG. 4, a glass substrate 21a having flat first and second surfaces is prepared, and a defect (groove) 21b is formed on the glass surface at a predetermined position for forming a core via. The glass substrate may be a glass substrate used for substrates of electronic devices, for example, but is not limited to, an alkali-free glass substrate. As a commercially available product, a product manufactured by a manufacturer such as Corning, Schott, or AGC may be used. The defect (groove) may be formed by mechanical etching, laser irradiation, or other methods.

[0090] 4(b), the glass substrate 21a having the defect (groove) 21b is subjected to an etching step to form a core via 23 through a physical or chemical etching process. In the etching process, the glass substrate forms a via in the defective portion, and the surface of the glass substrate 21a may also be etched at the same time. In order to prevent such etching of the glass surface, a masking film or the like may be applied, but in consideration of the troublesome process of applying and removing the masking film, the glass substrate having the defect may itself be etched, and in this case, the thickness of the glass substrate having the core via may be somewhat thinner than the thickness of the initial glass substrate.

[0091] Thereafter, a core layer manufacturing step may be performed by forming an electrically conductive layer 21d on the glass substrate as shown in Fig. 4(c) and (d). The electrically conductive layer may be a metal layer typically including, but not limited to, copper metal.

[0092] The adhesion between the glass surface (including the glass substrate surface and the core via surface) and the copper metal surface may be poor due to their different properties. In the present embodiment, the adhesion between the glass surface and the metal may be improved by two methods, a dry method and a wet method.

[0093] The dry method is a method of applying sputtering, i.e., forming a seed layer 21c on the glass surface and the inner diameter of the core via by metal sputtering. In forming the seed layer, a different metal such as titanium, chromium, or nickel may be sputtered together with copper, etc., and in this case, the adhesion between the glass and the metal may be improved due to an anchor effect in which the surface morphology of the glass and the metal particles interact with each other.

[0094] The wet method is a method of performing a primer treatment, and is a method of forming a primer layer 21c by pretreating with a compound having a functional group such as an amine. Depending on the intended degree of adhesion, a primer treatment can be performed with a compound or particles having an amine functional group after pretreating with a silane coupling agent. As mentioned above, the support substrate of the embodiment needs to have high performance to be able to form a fine pattern, and this should be maintained even after the primer treatment. Therefore, when such a primer includes nanoparticles, it is preferable that nanoparticles having an average diameter of 150 nm or less are applied, and for example, it is preferable that nanoparticles are applied as particles having an amine group. The primer layer may be formed by applying an adhesion improver manufactured, for example, by MEC's ​​CZ series.

[0095] The seed layer / primer layer 21c may selectively form an electrically conductive layer or a metal layer with or without removing portions that do not require the formation of an electrically conductive layer. In addition, the seed layer / primer layer 21c may be selectively treated with portions that require or do not require the formation of an electrically conductive layer in an activated or inactivated state for metal plating, and the subsequent steps may be performed. For example, the activation or inactivation treatment may be a light irradiation treatment using a laser of a certain wavelength, a chemical treatment, or the like. The formation of the metal layer may be performed using a copper plating method or the like that is applied to the manufacture of semiconductor devices, but is not limited thereto.

[0096] As shown in (e) of Figure 4, a portion of the core distribution layer may be removed if unnecessary, or the seed layer may be partially removed or passivated, and then metal plating may be performed to form an electrically conductive layer in a predetermined pattern, thereby forming an etched layer 21e of the core distribution layer.

[0097] FIG. 5 illustrates a manufacturing step of forming an insulating layer and an upper distribution pattern according to one embodiment.

[0098] As shown in (a) of Fig. 5, the core via may undergo an insulating layer formation step in which an insulating layer is used to fill empty spaces after the formation of the core distribution layer, which is the electrically conductive layer. The insulating layer may be in the form of a film, and may be, for example, a method of vacuum laminating an insulating layer in the form of a film. When vacuum lamination is performed in this manner, the insulating layer is sufficiently filled into the empty spaces inside the core via, thereby forming a core insulating layer without the formation of voids.

[0099] 5(b)-(e) illustrate the top layer fabrication steps.

[0100] The upper layer manufacturing step is a step of forming an upper distribution layer including an upper insulating layer and an upper distribution pattern on the core layer. The upper insulating layer may be formed by coating a resin composition forming the insulating layer 23a or laminating an insulating film, and the method of laminating an insulating film is preferable for simplicity. The lamination of the insulating film may be performed by laminating and curing the insulating film, and if a reduced pressure lamination method is applied, the insulating resin may be sufficiently embedded even in layers where no electrically conductive layer is formed inside the core via. The upper insulating layer also directly contacts the glass substrate at least in part, and therefore has sufficient adhesion. Specifically, the glass substrate and the upper insulating layer preferably have a characteristic of satisfying an adhesion test value of 4B or more according to ASTM D3359.

[0101] The upper distribution pattern may be formed by repeating the process of forming the insulating layer 23a, forming the electrically conductive layer 23c in a predetermined pattern, and etching unnecessary portions to form an etched layer 23d of the electrically conductive layer, and in the case of electrically conductive layers formed adjacent to each other with an insulating layer in between, the upper distribution pattern may be formed by forming blind vias 23b in the insulating layer and then performing a plating process. The blind vias may be formed by dry etching such as laser etching or plasma etching, or wet etching using a masking layer and an etchant.

[0102] Thereafter, a top connection layer and a cover layer may be formed, not shown.

[0103] The upper connection pattern and the upper connection electrodes may also be formed by a process similar to that for forming the upper distribution layer. Specifically, they may be formed by forming an etching layer of the insulating layer on the insulating layer 23e, forming an electrically conductive layer thereon again, and then forming an etching layer of the electrically conductive layer, or by selectively forming only the electrically conductive layer without applying an etching method. The cover layer may be formed by forming openings (not shown) at positions corresponding to the upper connection electrodes to expose the upper connection electrodes and to allow direct connection to the element connection parts or terminals of the elements.

[0104] After the upper layer is formed, a process of forming a lower connection layer and a cover layer to form a lower layer can be performed. In a similar manner to the above-mentioned upper connection layer and cover layer formation steps, a lower distribution layer and / or a lower connection layer, and optionally a cover layer (not shown) can be formed.

[0105] As described above, the cavity element may be formed in an insulating layer by laminating an insulating film (e.g., Ajinomoto Build-up Film (ABF)), in which case an undulation phenomenon may occur. In particular, the cavity portion in which the element is embedded may have a severe undulation phenomenon due to a gap between the elements and / or a gap between the cavity portion and the element. If the undulation phenomenon becomes severe, a leakage current may occur in the cavity portion, which may be fatal to active elements that are vulnerable to leakage current.

[0106] In addition, when a cavity element is disposed in a cavity portion having electrodes formed on its inner surface, or when multiple cavity elements are disposed in a cavity portion, the accuracy of the arrangement position may decrease, or defects may occur due to unintentional warping of the substrate during the manufacturing process, etc. For example, due to the characteristics of elements in which electrodes are exposed between adjacent elements and / or between elements and electrodes, short circuits may occur due to contact with each other, which may lead to defects in the packaging substrate.

[0107] Therefore, the present specification proposes an embodiment that prevents the occurrence of undulation in a cavity portion in which an element is embedded, thereby improving the effect of preventing leakage current, reducing defects in packaging substrates, etc. For example, in one embodiment of the present specification, it is proposed to perform a process of forming an insulating layer not once but multiple times.

[0108] 6 is an example of a cross-sectional structure of a core layer of a packaging substrate produced according to an embodiment. The packaging substrate of FIG. 6 is a conceptually simplified diagram for explaining a core layer produced according to an embodiment, and the contents described with reference to FIG. 1 to FIG. 3 may be applied.

[0109] For example, a glass substrate 21 having a first surface and a second surface facing each other, and a core layer 22 including a core via penetrating the glass substrate 21 may be formed. An electrode 63 may be formed on a surface of the glass substrate 21.

[0110] 6 is formed penetrating both the first and second surfaces of the glass substrate 21, and a cavity element 40 is disposed inside the cavity portion 28. As described above, the cavity element 40 may include either a passive element or an active element.

[0111] The cavity portion 28 may be formed simultaneously through the same formation step as the core via, or may be formed separately after the core via is formed or before the core via is formed.

[0112] Also, the cavity element 40 arranged inside the cavity portion 28 of Fig. 6 may be surrounded on all sides except one side by the first insulating layer 61. That is, for example, the cavity element 40 may be arranged in the cavity portion of Fig. 6, but the first insulating layer may be formed on all sides except one side of the cavity element 40. The cavity element and the first insulating layer surrounding the cavity element are collectively referred to as a cavity module.

[0113] For example, when the cavity element 40 has a hexahedral shape, five faces of the cavity element 40 excluding one face (e.g., a bottom face) may be surrounded by the first insulating layer 61. Alternatively, the edge of the upper surface of the cavity element 40 may be surrounded by the first insulating layer 61. That is, the first insulating layer 61 may be formed on the edge of the upper surface of the cavity element 40.

[0114] For example, when the cavity element 40 has a cylindrical shape, the side surfaces and / or the top surface of the cavity element 40 excluding the bottom surface may be surrounded by the first insulating layer 61. Alternatively, the edge of the top surface of the cavity element 40 may be surrounded by the first insulating layer 61. That is, the first insulating layer 61 may be formed on the edge of the top surface of the cavity element 40.

[0115] For example, one or more connection electrodes may be formed in the direction of the bottom surface of the cavity element 40. Or, for example, five surfaces of the cavity element 40 excluding the top surface may be surrounded by the first insulating layer 61. Or, for example, the edge of the bottom surface of the cavity element 40 may be surrounded by the first insulating layer 61. That is, the first insulating layer 61 may be formed on the edge of the bottom surface of the cavity element 40. In this case, for example, one or more connection electrodes may be formed in the direction of the top surface of the cavity element 40.

[0116] The first insulating layer 61 is formed on the entire surface except one side of the cavity element 40 or on the entire surface, thereby preventing short circuits caused by contact between cavity elements arranged side by side. In addition, the first insulating layer 61 formed on the entire surface except one side of the cavity element 40 or on the entire surface can prevent short circuits that may occur unintentionally during the manufacturing process of forming an electrically conductive layer on the side surface of the cavity portion 28.

[0117] 6 may include a second insulating layer 62 laminated on the first surface and the second surface. The remaining portion of the cavity portion 28 of FIG. 6 excluding the cavity element 40 and the first insulating layer 61 may be filled with the second insulating layer 62.

[0118] That is, after the cavity module is disposed in the cavity portion 28, there may be a remaining space inside the cavity portion, and the second insulating layer 62 may be formed therein. For example, the core layer 22 according to Fig. 6 may include the second insulating layer 62 embedded in the remaining portion of the cavity portion 28 excluding the cavity module. For example, the second insulating layer 62 may be laminated and cured on the upper portion (e.g., first surface) of the glass substrate 21 and the lower portion (e.g., second surface) of the glass substrate 21, thereby generating the second insulating layer.

[0119] A connection electrode may be connected to the cavity element 40 .

[0120] A connection electrode may be disposed on an exposed surface of the cavity element 40 on which the first insulating layer 61 is not disposed.

[0121] A connection electrode may be disposed through the first insulating layer 61 of the cavity element 40. The connection electrode may be in the form of a blind via.

[0122] The first insulating layer may further include a first insulating layer via (not shown) that penetrates the first insulating layer, and the first insulating layer via may be partially or entirely filled with an electrode material.

[0123] One end of the first insulating layer via may contact the cavity element 40 and the other end of the first insulating layer via may be exposed to the outside of the cavity portion 28 .

[0124] The first insulating layer via may be disposed in a form that does not directly contact the cavity element 40 but penetrates the cavity portion 28 from top to bottom.

[0125] The electrode material may be an electrically conductive material, for example, an electrically conductive metal, such as, but not limited to, copper, a copper alloy, or silver.

[0126] The first insulating layer 61 and the second insulating layer 62 may be made of the same material or different materials. In the latter case, materials having different dielectric constants may be used.

[0127] For example, the first insulating layer 61 and the second insulating layer 62 may have different dielectric constants. For example, the first insulating layer 61 may have a dielectric constant equal to or lower than that of the second insulating layer 62. In this case, there is an advantage that the occurrence of an undulation phenomenon in the cavity portion can be substantially suppressed and a sufficient insulating effect can be expected for each of the cavity elements.

[0128] The first insulating layer 61 and the second insulating layer 62 may each include an insulating material.

[0129] For example, the insulating material may be a polymer resin, a mixed material of a polymer resin and a filler (inorganic particles, organic particles, organic-inorganic composite particles, etc.), an inorganic deposition layer, or the like.

[0130] For example, the polymer resin may be an acrylic resin, an epoxy resin, or a modified resin thereof, and may be a material applicable to electronic devices for the purpose of molding, etc. For example, a liquid crystal polymer (LCP) may be used.

[0131] For example, the mixed material may be a mixture of an acrylic resin and a filler, a mixture of an acrylic resin, an epoxy resin, and a filler, or a mixture of an epoxy resin and a filler. The filler may be inorganic particles, for example, silica particles. Commercially available products may include, but are not limited to, ABF (Ajinomoto Build-up Film), EMC (Epoxy Molding Compound), and MPI (Modified Polyimide).

[0132] The inorganic deposition layer may be, for example, a silicon oxide deposition layer, a silicon nitride deposition layer, etc., but is not limited thereto.

[0133] The first insulating layer 61 and the second insulating layer 62 may be made of materials having the same or different coefficients of thermal expansion (CTE). Preferably, a material having a small difference between the coefficients of thermal expansion of the first insulating layer 61 and the second insulating layer 62 may be used.

[0134] The difference in thermal expansion coefficient between the material of the first insulating layer and the material of the second insulating layer may be 2 ppm / ° C. or less, 1.5 ppm / ° C. or less, 1 ppm / ° C. or less, or 0.5 ppm / ° C. or less. The difference in thermal expansion coefficient may be 0 ppm / ° C. or more, 0.1 ppm / ° C. or more, or 0.2 ppm / ° C. or more.

[0135] The thermal expansion coefficient of the first insulating layer 61 may be 8 ppm / ° C. or more, 10 ppm / ° C. or more, 12 ppm / ° C. or more, or 14 ppm / ° C. or more. The thermal expansion coefficient may be 20 ppm / ° C. or less, 18 ppm / ° C. or less, or 17 ppm / ° C. or less.

[0136] The thermal expansion coefficient of the second insulating layer 62 may be 8 ppm / ° C. or more, 10 ppm / ° C. or more, or 12 ppm / ° C. or more. The thermal expansion coefficient may be 20 ppm / ° C. or less, 18 ppm / ° C. or less, 16 ppm / ° C. or less, or 14 ppm / ° C. or less.

[0137] The first insulating layer 61 and the second insulating layer 62 may be made of materials having different dielectric constants. Preferably, the materials of the insulating layers may be selected so that the dielectric constant of the first insulating layer 61 is lower than the dielectric constant of the second insulating layer 62.

[0138] The first insulating layer 61 and the second insulating layer 62 may be made of materials having different dielectric constants Dk at a high frequency of 5.8 GHz. Exemplarily, the difference between the Dk of the first insulating layer 61 and the Dk of the second insulating layer 62 may be 0.1 or more. The difference in Dk may be 0.1 or more, 0.13 or more, 0.16 or more, or 0.2 or more. The difference in Dk may be 1 or less, 0.8 or less, 0.6 or less, 0.5 or less, 0.4 or less, 0.3 or less, or 0.25 or less.

[0139] The Dk of the first insulating layer 61 may be 2.3 or more, 2.5 or more, 2.7 or more, or 2.9 or more. The Dk may be 3.4 or less, 3.2 or less, or 3.1 or less.

[0140] The Dk of the second insulating layer 62 may be 3.0 or more, 3.1 or more, or 3.2 or more. The Dk may be 3.6 or less, 3.5 or less, or 3.4 or less.

[0141] The Dk of the first insulating layer 61 may be smaller than the Dk of the second insulating layer 62.

[0142] The first insulating layer 61 and the second insulating layer 62 may be made of materials having the same or different dielectric loss factors Df. Preferably, a material having a difference between Df of the first insulating layer 61 and Df of the second insulating layer 62 of 0.0001 or more may be used. The difference in Df may be 0.0001 or more, 0.0005 or more, or 0.001 or more. The difference in Df may be 0.02 or less.

[0143] The Df of the first insulating layer 61 may be 0.004 or less, 0.0038 or less, or 0.0036 or less. The Df may be 0.001 or more, 0.0015 or more, 0.0018 or more, or 0.002 or more.

[0144] The Df of the second insulating layer 62 may be 0.005 or less, 0.0048 or less, or 0.0046 or less. The Df may be 0.003 or more, 0.0032 or more, or 0.0034 or more.

[0145] The Df of the first insulating layer 61 may be smaller than the Df of the second insulating layer 62.

[0146] For example, ABF may be applied to the second insulating layer 62, and LCP may be applied to the first insulating layer 61. For example, EMC may be applied to the second insulating layer 62, and LCP may be applied to the first insulating layer 61. For example, ABP having different dielectric constants may be applied to the second insulating layer 62 and the first insulating layer 61.

[0147] The first insulating layer 61 can be formed on the surface of the cavity element 40 by, for example, a varnish type method, a selective lamination method, vapor deposition, or the like.

[0148] The second insulating layer 62 can be formed by applying a general method for forming an insulating layer in a cavity of a packaging substrate, and the method applied for forming the first insulating layer 61 may also be applied.

[0149] The present specification also proposes a manufacturing method for producing the packaging substrate according to the embodiment disclosed in FIG.

[0150] For example, a method for manufacturing a packaging substrate may be proposed in which a glass substrate 21 having a cavity portion 28 and a pretreated cavity element 40 are prepared, the cavity element 40 is arranged in the cavity portion 28, and a second insulating layer 62 is laminated on the glass substrate, but the cavity element 40 has a first insulating layer 61 formed on the entire surface except for one surface or on the entire surface. Also, for example, the first insulating layer 61 and the second insulating layer 62 may have different dielectric constants.

[0151] Specifically, the present specification proposes an embodiment for producing a packaging substrate according to the following embodiment.

[0152] As one embodiment, a method may be proposed in which, before selecting and placing a cavity element, a first insulating layer is placed on the cavity element (manufacturing a cavity module); then, the cavity module is positioned within the cavity, and a second insulating layer is formed by an RDL (Re-Distribution Layer) process.

[0153] FIG. 7 is a flowchart illustrating a cross-sectional view of an example of a method for manufacturing a packaging substrate according to an embodiment.

[0154] The step of forming the first and second insulating layers in the packaging substrate will be described in more detail with reference to FIG.

[0155] 7(a), a first insulating layer 61 may be formed on a portion of the surface of the cavity element 40 excluding the top or bottom surface (S). For example, the first insulating layer 61 may be formed on a portion of the surface of the cavity element 40 excluding the top or bottom surface by performing a sputtering, coating, or molding process on the cavity element 40.

[0156] That is, the cavity element 40 may have some surfaces, excluding the top surface or the bottom surface, surrounded by the first insulating layer 61. For example, five surfaces, excluding the bottom surface, of the cavity element 40 may be surrounded by the first insulating layer 61. Or, for example, the edge of the top surface of the cavity element 40 may be surrounded by the first insulating layer 61. That is, the first insulating layer 61 may be formed on the edge of the top surface of the cavity element 40. In this case, for example, one or more connection electrodes may be formed in the bottom surface direction of the cavity element 40. Or, for example, five surfaces, excluding the top surface of the cavity element 40, may be surrounded by the first insulating layer 61. Or, for example, the edge of the bottom surface of the cavity element 40 may be surrounded by the first insulating layer 61. That is, the first insulating layer 61 may be formed on the edge of the bottom surface of the cavity element 40. In this case, for example, one or more connection electrodes may be formed in the top surface direction of the cavity element 40.

[0157] The first insulating layer 61 is formed on a portion of the surface of the cavity element 40 excluding the top or bottom surface, thereby preventing a short circuit caused by contact between cavity elements arranged side by side. In addition, the first insulating layer 61 formed on a portion of the surface of the cavity element 40 excluding the top or bottom surface can prevent a short circuit that may occur unintentionally during the manufacturing process of forming an electrically conductive layer on the side surface of the cavity portion 28. A detailed description related to forming a first insulating layer on a cavity element will be omitted as it overlaps with the above description.

[0158] The cavity element 40 may include a passive element and / or an active element. For example, a multilayer ceramic capacitor (MLCC) may be used as the cavity element 40. Alternatively, an active element other than a passive element such as an MLCC may be used as the cavity element 40. In addition, for example, the first insulating layer 61 may include the above-mentioned liquid crystal polymer (LCP), epoxy molding compound (EMC), Ajinomoto build-up film (ABF), and / or modified polyimide (MPI), etc.

[0159] Thereafter, as shown in (b) of FIG. 7, a glass substrate 21 may be attached to an adhesive film such as a PI tape (Polyimide Tape), and a cavity element 40 on which a first insulating layer 61 is formed may be selected and placed in the cavity portion 28 (P1, designation of the position of the cavity element).

[0160] Next, as shown in Fig. 7(c), a process (Lamination on top) may be performed in which a second insulating layer 62 is laminated on the first surface (P2). When the second insulating layer 62 is laminated on the entire first surface of the glass substrate 21 and pre-cured, the second insulating layer 62 may be embedded in the internal space of the cavity portion 28 as shown in Fig. 7(d). For example, the second insulating layer 62 may include an insulating mixture, which may include inorganic particles and a polymer resin. For example, the second insulating layer 62 may include the above-mentioned Epoxy Molding Compound (EMC) and / or Ajinomoto Build-up Film (ABF).

[0161] If necessary, the adhesive film may be removed during a subsequent process. Exemplarily, the adhesive film may be an adhesive film whose adhesive strength can be reduced by ultraviolet irradiation, etc. The adhesive film can be easily removed from the glass substrate by reducing the adhesive strength of the adhesive film by irradiating the adhesive film with ultraviolet light directly or through the glass substrate. In addition, the cavity element can be fixed in position by the second insulating layer that has been pre-cured by curing, and if the degree of warping is controlled to a certain level or less, a subsequent process can be applied without fixing the adhesive film.

[0162] Next, as shown in Fig. 7(e), a process (Lamination on bottom) may be performed in which the second insulating layer 62 is laminated on the second surface (P3). When the second insulating layer 62 is laminated on the entire second surface of the glass substrate 21 and pre-cured, the second insulating layer 62 may be embedded in the internal space of the cavity portion 28 as shown in Fig. 7(f) (P4).

[0163] Therefore, according to FIG. 7, as one embodiment, a method for manufacturing a packaging substrate may be proposed, which includes: generating a core via in a glass substrate 21 having a first surface and a second surface facing each other, and generating a cavity portion 28 penetrating the first surface and the second surface of the glass substrate 21; arranging a cavity module having a first insulating layer 61 formed on the entire surface or the entire surface except for one surface of a cavity element 40 in the cavity portion 28; and laminating a second insulating layer 62 on the first surface and the second surface.

[0164] As one embodiment, a method for manufacturing a packaging substrate may be proposed, which includes: generating a core via in a glass substrate 21 having a first surface and a second surface opposing each other, and generating a cavity portion 28 penetrating the first surface and the second surface of the glass substrate 21; forming a first insulating layer 61 on the entire surface or the entire surface except for one surface of a cavity element 40; arranging the cavity element 40 having the first insulating layer 61 formed on the entire surface or the entire surface except for the one surface in the cavity portion 28; and laminating a second insulating layer 62 on the first surface and the second surface.

[0165] As another example, a method may be proposed in which a cavity element is selected and placed in a cavity; then a first insulating layer is coated (or placed) on the cavity element, the first insulating layer coated on a particular surface (e.g., the top surface or the bottom surface) of the cavity element is etched, and then a second insulating layer is formed by an RDL (Re-Distribution Layer) process.

[0166] FIG. 8 is a flowchart illustrating a method for manufacturing a packaging substrate according to another embodiment in cross section.

[0167] The step of forming the first and second insulating layers in the packaging substrate will be described in more detail with reference to FIG.

[0168] For example, as shown in FIG. 8(a), a cavity element 40 may be attached to an adhesive film such as a PI tape (Polyimide Tape). The cavity element 40 may include a passive element and / or an active element. For example, a multilayer ceramic capacitor (MLCC) may be used as the cavity element 40. Alternatively, for example, an active element other than a passive element such as an MLCC may be used as the cavity element 40.

[0169] Thereafter, as shown in FIG. 8(b), a first insulating layer 61 may be formed on a portion of the surface of the cavity element 40 disposed in the cavity portion 28 except for the top or bottom surface (S). The process may be performed after the cavity element is selected and disposed so as to be inserted into the cavity portion 28 of the glass substrate 21. For example, the first insulating layer 61 may be formed on a portion of the surface of the cavity element 40 except for the top or bottom surface by performing a sputtering, coating, or molding process on the cavity element 40 in the cavity portion 28. The cavity element 40 disposed in the cavity portion 28 may be surrounded on a portion of the surface except for the top or bottom surface by the first insulating layer 61. For example, five surfaces of the cavity element 40 except for the bottom surface may be surrounded by the first insulating layer 61. Or, for example, the edge of the top surface of the cavity element 40 may be surrounded by the first insulating layer 61. That is, the first insulating layer 61 may be formed on the edge of the upper surface of the cavity element 40. In this case, for example, one or more connection electrodes may be formed in the direction of the bottom surface of the cavity element 40. Or, for example, five surfaces of the cavity element 40 excluding the upper surface may be surrounded by the first insulating layer 61. Or, for example, the edge of the bottom surface of the cavity element 40 may be surrounded by the first insulating layer 61. That is, the first insulating layer 61 may be formed on the edge of the bottom surface of the cavity element 40. In this case, for example, one or more connection electrodes may be formed in the direction of the upper surface of the cavity element 40.

[0170] The first insulating layer 61 is formed on a portion of the surface of the cavity element 40 excluding the top or bottom surface, thereby preventing a short circuit caused by contact between cavity elements arranged side by side. In addition, the first insulating layer 61 formed on a portion of the surface of the cavity element 40 excluding the top or bottom surface can prevent a short circuit that may occur unintentionally during the manufacturing process of forming an electrically conductive layer on the side surface of the cavity portion 28.

[0171] The first insulating layer 61 may include the above-mentioned liquid crystal polymer (LCP), epoxy molding compound (EMC), Ajinomoto build-up film (ABF), and / or modified polyimide (MPI), etc. A more detailed description of the cavity element and the first insulating layer will be omitted since it overlaps with the above description.

[0172] Next, as shown in FIG. 8(c), a process (Lamination on top) may be performed in which the second insulating layer 62 is laminated on the first surface (P2). When the second insulating layer 62 is laminated on the entire first surface of the glass substrate 21 and pre-cured, the second insulating layer 62 may be embedded in the internal space of the cavity portion 28 as shown in FIG. 8(d). For example, the second insulating layer 62 may include an insulating mixture, which may include inorganic particles and polymer resin. For example, the second insulating layer 62 may include the above-mentioned ABF (Ajinomoto Build-up Film). A detailed description of each insulating layer will be omitted since it overlaps with the above description.

[0173] If necessary, the adhesive film may be removed during a subsequent process. Exemplarily, the adhesive film may be an adhesive film whose adhesive strength can be reduced by ultraviolet irradiation, etc. The adhesive film can be easily removed from the glass substrate by reducing the adhesive strength of the adhesive film by irradiating the adhesive film with ultraviolet light directly or through the glass substrate. In addition, the cavity element can be fixed in position by the second insulating layer that has been pre-cured by curing, and if the degree of warping is controlled to a certain level or less, a subsequent process can be applied without fixing the adhesive film.

[0174] Next, as shown in Fig. 8(e), a process (Lamination on bottom) may be performed in which the second insulating layer 62 is laminated on the second surface (P3). When the second insulating layer 62 is laminated on the entire second surface of the glass substrate 21 and pre-cured, the second insulating layer 62 may be embedded in the internal space of the cavity portion 28 as shown in Fig. 8(f) (P4).

[0175] Therefore, according to FIG. 8, as one embodiment, a method for manufacturing a packaging substrate may be proposed, which includes generating a core via in a glass substrate 21 including a first surface and a second surface opposing each other, generating a cavity portion 28 penetrating the first surface and the second surface of the glass substrate 21; arranging cavity elements 40 in the cavity portion 28, forming a first insulating layer 61 on a portion of the surface excluding the bottom surface of the arranged cavity elements 40; and laminating a second insulating layer 62 on the first surface and the second surface.

[0176] The packaging substrate manufacturing method according to the above-described embodiments and the packaging substrate using the same can prevent the undulation phenomenon caused by gaps between elements and / or gaps between the cavity portion and the element, and can prevent leakage current from occurring in the cavity portion.

[0177] The above description of the present specification has been described with reference to the embodiments shown in the drawings, but these are merely illustrative, and a person having ordinary skill in the art will understand that various modifications and variations of the embodiments are possible. In other words, the scope of the present specification is not limited to the above-mentioned embodiments, and various modifications and improvements made by those skilled in the art using the basic concepts of the embodiments defined in the accompanying claims also belong to the scope of the embodiments. Therefore, the true technical scope of protection of the present specification must be determined by the technical ideas of the accompanying claims. [Explanation of symbols]

[0178] 100 Semiconductor device 10 Motherboard 30 Semiconductor Device Section 32 First semiconductor element 34 Second semiconductor element 36 Third semiconductor element 20 Packaging Substrate 21, 21a Glass substrate 22 Core Layer 223 Core insulation layer 213 Page 1 214 2nd page 23 Corebia 24 Core Distribution Layer 241 Core Distribution Pattern 26 Upper layer 25 Upper distribution layer 251 Upper distribution pattern 23b Blind Via 253 Upper insulating layer 27 Top connection layer 271 Top connection electrode 272 Top connection pattern 28 Cavity 281 Interior Space 282 Cavity Distribution Layer 40 Cavity element 50 Connection 51 Element connection part 52 Board connection 60 Cover Layer 61 First insulating layer 62 Second insulating layer 63 Electrode

Claims

1. The present invention includes a glass substrate having a first surface and a second surface opposed to each other, and a core layer including a cavity portion penetrating the glass substrate, A cavity module is disposed in the cavity portion, the cavity module includes a cavity element and a first insulating layer surrounding the cavity element; The first insulating layer is disposed on the entire surface or the entire surface except for one surface of the cavity element; the second insulating layer is disposed so as to be at least partially embedded in a portion of the cavity portion excluding the cavity module; The first insulating layer and the second insulating layer have different dielectric constants.

2. The packaging substrate of claim 1 , wherein the first insulating layer has a lower dielectric constant than the second insulating layer.

3. The high frequency dielectric constant Dk is the dielectric constant at a high frequency of 5.8 GHz, 2. The packaging substrate according to claim 1, wherein a difference between a high-frequency relative dielectric constant Dk1 of the first insulating layer and a high-frequency relative dielectric constant Dk2 of the second insulating layer is 0.1 or more.

4. the dielectric loss factor of the first insulating layer is Df1; The dielectric loss factor of the second insulating layer is Df2; The packaging substrate according to claim 1 , wherein the difference between Df1 and Df2 is 0.0001 or more.

5. The packaging substrate of claim 1 , wherein the first insulating layer comprises a liquid crystal polymer (LCP), an epoxy molding compound (EMC), an Ajinomoto build-up film (ABF), or a modified polyimide (MPI).

6. the second insulating layer comprises an insulating compound; The packaging substrate of claim 1 , wherein the insulating compound comprises a mixture of inorganic particles and polymeric resin.

7. The packaging substrate according to claim 1 , wherein a connection electrode is disposed on the cavity element.

8. The packaging substrate of claim 1 , wherein the cavity element comprises a passive element or an active element.

9. A first insulating layer via penetrating the first insulating layer is further disposed in the first insulating layer; The packaging substrate of claim 1 , wherein the first insulating layer via is partially or entirely filled with an electrode material.

10. A method for manufacturing a packaging substrate, comprising: preparing a glass substrate having a cavity portion disposed thereon and a cavity module; arranging the cavity module in the cavity portion; and laminating a second insulating layer on the glass substrate; the cavity module includes a cavity element and a first insulating layer surrounding at least a portion of the cavity element; A method for manufacturing a packaging substrate, wherein the first insulating layer is disposed on the entire surface or the entire surface except for one surface of the cavity element.

11. The method of claim 10 , wherein the first insulating layer and the second insulating layer have different dielectric constants.

12. The method of claim 10, wherein the first insulating layer comprises a liquid crystal polymer (LCP), an epoxy molding compound (EMC), an Ajinomoto build-up film (ABF), or a modified polyimide (MPI).

13. The method of claim 10, wherein the second insulating layer includes an Ajinomoto Build-up Film (ABF) or an Epoxy Molding Compound (EMC).

14. The method for manufacturing a packaging substrate according to claim 10 , wherein a connection electrode is formed on the cavity element.

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