Display device

Abstract

To suppress the manufacturing cost, or improve the display quality of, a display device with a touch sensor function.SOLUTION: A display device includes: a plurality of display elements each including a lower electrode, an upper electrode facing the lower electrode, and an organic layer disposed between the lower electrode and the upper electrode and emitting light according to a potential difference between the lower electrode and the upper electrode; a rib including a plurality of pixel openings overlapping with the respective display elements; and partition walls including a conductive lower part disposed on the rib and an upper part projecting from a side surface of the lower part and surrounding the respective display elements. The partition walls are sectioned into a plurality of segments for detecting an object that is in contact with or approaches a display region including the display elements.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present embodiment relates to a display device. [Background technology]

[0002] In recent years, display devices that use organic light-emitting diodes (OLEDs) as display elements and have a touch sensor function that detects user operations on the display area have been put to practical use. For this type of display device, there is a demand for reducing manufacturing costs and improving display quality. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2000-195677 A [Patent Document 2] JP 2004-207217 A [Patent Document 3] JP 2008-135325 A [Patent Document 4] JP 2009-32673 A [Patent Document 5] JP 2010-118191 A [Patent Document 6] International Publication No. 2018 / 179308 [Patent Document 7] US Patent Application Publication No. 2022 / 0077251 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to reduce the manufacturing cost of a display device having a touch sensor function and to improve the display quality. [Means for solving the problem]

[0005] Generally, the display device according to the embodiment includes a lower electrode, an upper electrode facing the lower electrode, and a plurality of display elements each including an organic layer disposed between the lower electrode and the upper electrode and emitting light in response to a potential difference between the lower electrode and the upper electrode, a rib having a plurality of pixel openings overlapping the plurality of display elements, and a partition wall including a conductive lower portion disposed on the rib and an upper portion protruding from a side surface of the lower portion and surrounding each of the plurality of display elements. Furthermore, the partition wall is divided into a plurality of segments for detecting an object in contact with or in proximity to a display region including the plurality of display elements. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device according to a first embodiment. [Diagram 2] FIG. 2 is a schematic plan view showing an example of a layout of sub-pixels. [Diagram 3] FIG. 3 is a schematic cross-sectional view of the display device taken along line III-III in FIG. [Figure 4] FIG. 4 is a schematic plan view showing elements for detecting a touch operation on the display area. [Diagram 5] FIG. 5 is a schematic enlarged plan view of the segment shown in FIG. [Figure 6] FIG. 6 is a schematic cross-sectional view of the display device taken along line VI-VI in FIG. [Figure 7] FIG. 7 is a schematic enlarged plan view of a segment according to the second embodiment. [Figure 8] FIG. 8 is a schematic cross-sectional view of the display device taken along line VIII-VIII in FIG. [Figure 9] FIG. 9 is a diagram showing a touch detection method according to the third embodiment. [Figure 10] FIG. 10 is a schematic cross-sectional view showing an example of the configuration of a display device including a detection electrode. [Figure 11] FIG. 11 is a schematic cross-sectional view showing another example of the configuration of a display device including a detection electrode. [Figure 12]FIG. 12 is a schematic plan view of a segment according to the third embodiment. [Figure 13] FIG. 13 is a schematic plan view of a detection electrode according to the third embodiment. [Figure 14] FIG. 14 is a schematic enlarged plan view showing an example of a configuration that can be applied to the segment according to the third embodiment. [Figure 15] FIG. 15 is a schematic enlarged plan view showing another example of a configuration that can be applied to the segment according to the third embodiment. [Figure 16] FIG. 16 is a schematic enlarged plan view showing still another example of a configuration that can be applied to the segment according to the third embodiment. [Figure 17] FIG. 17 is a schematic plan view of a segment according to the fourth embodiment. [Figure 18] FIG. 18 is a schematic plan view of a detection electrode according to the fourth embodiment. [Figure 19] FIG. 19 is a schematic enlarged plan view showing an example of a configuration that can be applied to a segment according to the fourth embodiment. [Figure 20] FIG. 20 is a schematic enlarged plan view showing another example of a configuration that can be applied to the segment according to the fourth embodiment. [Figure 21] FIG. 21 is a schematic enlarged plan view showing still another example of a configuration that can be applied to the segment according to the fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Some embodiments will be described with reference to the drawings. The disclosure is merely an example, and those who are skilled in the art can easily conceive of appropriate modifications while maintaining the gist of the invention are naturally included in the scope of the present invention. In addition, the drawings may be schematic in width, thickness, shape, etc. of each part compared to the actual embodiment in order to make the explanation clearer, but they are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and each figure, components that perform the same or similar functions as those described above with respect to the previous figures are given the same reference numerals, and duplicate detailed explanations may be omitted as appropriate.

[0008] In addition, in the drawings, an X-axis, a Y-axis, and a Z-axis that are perpendicular to each other are shown as necessary to facilitate understanding. The direction along the X-axis is called the X-direction, the direction along the Y-axis is called the Y-direction, and the direction along the Z-axis is called the Z-direction. The Z-direction is the normal direction of a plane that includes the X-direction and the Y-direction. Moreover, viewing various elements parallel to the Z-direction is called planar view.

[0009] The display device according to each embodiment is an organic electroluminescence display device having an organic light-emitting diode (OLED) as a display element, and can be installed in various electronic devices such as televisions, personal computers, in-vehicle devices, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0010] [First embodiment] 1 is a diagram showing an example of the configuration of a display device DSP according to a first embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 has a display area DA for displaying an image and a peripheral area SA around the display area DA. The substrate 10 may be made of glass or a flexible resin film.

[0011] In this embodiment, the shape of the substrate 10 in a plan view is rectangular. However, the shape of the substrate 10 in a plan view is not limited to rectangular, and may be other shapes such as square, circular, or elliptical.

[0012] The display area DA includes a plurality of pixels PX arranged in a matrix in the X and Y directions. The pixels PX include a plurality of subpixels SP that display different colors. In this embodiment, it is assumed that the pixel PX includes a blue subpixel SP1, a green subpixel SP2, and a red subpixel SP3. However, the pixel PX may include subpixels SP of other colors, such as white, in addition to the subpixels SP1, SP2, and SP3, or instead of any of the subpixels SP1, SP2, and SP3.

[0013] The subpixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements constituted by, for example, thin film transistors.

[0014] In the display area DA, there are arranged a plurality of scanning lines GL that supply scanning signals to the pixel circuits 1 of each subpixel SP, a plurality of signal lines SL that supply video signals to the pixel circuits 1 of each subpixel SP, and a plurality of power lines PL. In the example of Fig. 1, the scanning lines GL and the power lines PL extend in the X direction, and the signal lines SL extend in the Y direction.

[0015] A gate electrode of the pixel switch 2 is connected to a scanning line GL. A source electrode of the pixel switch 2 is connected to a signal line SL. A drain electrode of the pixel switch 2 is connected to a gate electrode of the driving transistor 3 and a capacitor 4.

[0016] A source electrode of the driving transistor 3 is connected to the power line PL and the capacitor 4. A drain electrode of the driving transistor 3 is connected to the display element DE (lower electrodes LE1, LE2, LE3 described later). In this embodiment, the driving transistor 3 is composed of a thin film transistor including a p-type semiconductor.

[0017] It should be noted that the configuration of the pixel circuit 1 is not limited to the example shown in the drawing. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0018] The display device DSP further includes a terminal section T arranged in the peripheral area SA. To the terminal section T, for example, a flexible circuit board that supplies voltages and signals for driving the display device DSP is connected.

[0019] The display device DSP further includes a display controller CT1 that controls image display in the display area DA, and a detection controller CT2 that detects a touch operation on the display area DA. The display controller CT1 and the detection controller CT2 are, for example, ICs mounted on the flexible circuit board. As another example, the display controller CT1 and the detection controller CT2 may be mounted in the peripheral area SA.

[0020] Fig. 2 is a schematic plan view showing an example of the layout of subpixels SP1, SP2, and SP3. In the example of Fig. 2, subpixels SP2 and SP3 are aligned with subpixel SP1 in the X direction. Furthermore, subpixels SP2 and SP3 are aligned with subpixel SP1 in the Y direction.

[0021] When the subpixels SP1, SP2, and SP3 are laid out in this manner, the display area DA is formed with a column in which the subpixels SP2 and SP3 are alternately arranged in the Y direction, and a column in which multiple subpixels SP1 are repeatedly arranged in the Y direction. These columns are arranged alternately in the X direction. Note that the layout of the subpixels SP1, SP2, and SP3 is not limited to the example in FIG.

[0022] A rib 5 is disposed in the display area DA. The rib 5 has pixel apertures AP1, AP2, and AP3 in the subpixels SP1, SP2, and SP3, respectively. In the example of Fig. 2, the pixel aperture AP1 is larger than the pixel aperture AP2, and the pixel aperture AP2 is larger than the pixel aperture AP3. That is, among the subpixels SP1, SP2, and SP3, the subpixel SP1 has the largest aperture ratio, and the subpixel SP3 has the smallest aperture ratio.

[0023] The subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap the pixel aperture AP1. The subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap the pixel aperture AP2. The subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap the pixel aperture AP3.

[0024] The lower electrode LE1, the upper electrode UE1, and the organic layer OR1 overlapping with the pixel aperture AP1 constitute the display element DE1 of the subpixel SP1. The lower electrode LE2, the upper electrode UE2, and the organic layer OR2 overlapping with the pixel aperture AP2 constitute the display element DE2 of the subpixel SP2. The lower electrode LE3, the upper electrode UE3, and the organic layer OR3 overlapping with the pixel aperture AP3 constitute the display element DE3 of the subpixel SP3. The display elements DE1, DE2, and DE3 may further include a cap layer, which will be described later. The rib 5 surrounds each of these display elements DE1, DE2, and DE3.

[0025] A conductive partition wall 6 is disposed above the rib 5. The partition wall 6 overlaps the rib 5 as a whole and has the same planar shape as the rib 5. That is, the partition wall 6 has openings in each of the subpixels SP1, SP2, and SP3. From another perspective, the rib 5 and the partition wall 6 are lattice-shaped in a planar view and surround each of the display elements DE1, DE2, and DE3. The partition wall 6 serves as wiring that supplies a common voltage to the upper electrodes UE1, UE2, and UE3.

[0026] Fig. 3 is a schematic cross-sectional view of the display device DSP taken along line III-III in Fig. 2. A circuit layer 11 is disposed on the above-mentioned substrate 10. The circuit layer 11 includes various circuits and wiring such as the pixel circuits 1, scanning lines GL, signal lines SL, and power lines PL shown in Fig. 1. The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that planarizes unevenness caused by the circuit layer 11.

[0027] The lower electrodes LE1, LE2, and LE3 are disposed on the organic insulating layer 12. The rib 5 is disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. Ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib 5. Although not shown in the cross section of FIG. 3, the lower electrodes LE1, LE2, and LE3 are each connected to the pixel circuit 1 of the circuit layer 11 (the drain electrode of the driving transistor 3 shown in FIG. 1) through a contact hole provided in the organic insulating layer 12.

[0028] The partition 6 includes a conductive lower portion 61 disposed on the rib 5, and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a width greater than that of the lower portion 61. As a result, both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61. Such a shape of the partition 6 is called an overhang shape.

[0029] In the example of FIG. 3, the lower part 61 has a bottom layer 63 arranged on the rib 5 and a shaft layer 64 arranged on the bottom layer 63. For example, the bottom layer 63 is formed thinner than the shaft layer 64. In addition, in the example of FIG. 3, both ends of the bottom layer 63 protrude from the side surfaces of the shaft layer 64.

[0030] The organic layer OR1 covers the lower electrode LE1 through the pixel opening AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel opening AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel opening AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the side surfaces of the lower portion 61 of the partition wall 6.

[0031] The display element DE1 includes a cap layer CP1 that covers the upper electrode UE1. The display element DE2 includes a cap layer CP2 that covers the upper electrode UE2. The display element DE3 includes a cap layer CP3 that covers the upper electrode UE3. The cap layers CP1, CP2, and CP3 serve as optical adjustment layers that improve the extraction efficiency of light emitted by the organic layers OR1, OR2, and OR3, respectively.

[0032] In the following description, a multilayer body including an organic layer OR1, an upper electrode UE1, and a cap layer CP1 will be referred to as a laminate film FL1, a multilayer body including an organic layer OR2, an upper electrode UE2, and a cap layer CP2 will be referred to as a laminate film FL2, and a multilayer body including an organic layer OR3, an upper electrode UE3, and a cap layer CP3 will be referred to as a laminate film FL3.

[0033] A part of the laminated film FL1 is located on the upper part 62. This part is separated from a part of the laminated film FL1 located around the partition wall 6 (a part that constitutes the display element DE1). Similarly, a part of the laminated film FL2 is located on the upper part 62, and this part is separated from a part of the laminated film FL2 located around the partition wall 6 (a part that constitutes the display element DE2). Furthermore, a part of the laminated film FL3 is located on the upper part 62, and this part is separated from a part of the laminated film FL3 located around the partition wall 6 (a part that constitutes the display element DE3).

[0034] Sealing layers SE11, SE12, and SE13 are disposed in the subpixels SP1, SP2, and SP3, respectively. The sealing layer SE11 continuously covers the cap layer CP1 and the partition wall 6 around the subpixel SP1. The sealing layer SE12 continuously covers the cap layer CP2 and the partition wall 6 around the subpixel SP2. The sealing layer SE13 continuously covers the cap layer CP3 and the partition wall 6 around the subpixel SP3.

[0035] 3, the laminated film FL1 and the sealing layer SE11 on the partition 6 between the subpixels SP1 and SP2 are separated from the laminated film FL2 and the sealing layer SE12 on the partition 6. In addition, the laminated film FL1 and the sealing layer SE11 on the partition 6 between the subpixels SP1 and SP3 are separated from the laminated film FL3 and the sealing layer SE13 on the partition 6.

[0036] The sealing layers SE11, SE12, and SE13 are covered with a resin layer RS1. The resin layer RS1 is covered with a sealing layer SE2. The sealing layer SE2 is covered with a resin layer RS2. The resin layers RS1, RS2, and the sealing layer SE2 are continuously provided at least throughout the entire display area DA, and a part of them extends into the peripheral area SA.

[0037] A cover member such as a polarizing plate, a protective film, or a cover glass may be further disposed above the resin layer RS2. Such a cover member may be adhered to the resin layer RS2 via an adhesive layer such as OCA (Optical Clear Adhesive).

[0038] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib 5 and the sealing layers SE11, SE12, SE13, and SE2 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). In one example, the rib 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, and SE2 are formed of silicon nitride. The resin layers RS1 and RS2 are formed of a resin material (organic insulating material) such as epoxy resin or acrylic resin.

[0039] The lower electrodes LE1, LE2, and LE3 each have a reflective layer and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer. The reflective layer can be made of a metal material with excellent light reflectivity, such as silver. Each conductive oxide layer can be made of a transparent conductive oxide, such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0040] The upper electrodes UE1, UE2, UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg), etc. For example, the lower electrodes LE1, LE2, LE3 correspond to anodes, and the upper electrodes UE1, UE2, UE3 correspond to cathodes.

[0041] The organic layers OR1, OR2, and OR3 are composed of a plurality of thin films including a light-emitting layer. In one example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer are laminated in this order in the Z direction. However, the organic layers OR1, OR2, and OR3 may have other structures such as a so-called tandem structure including a plurality of light-emitting layers.

[0042] The cap layers CP1, CP2, and CP3 have a laminated structure in which, for example, a plurality of transparent layers are stacked. These transparent layers may include layers formed of inorganic materials and layers formed of organic materials. In addition, these transparent layers have different refractive indices. For example, the refractive indices of these transparent layers are different from the refractive indices of the upper electrodes UE1, UE2, and UE3 and the sealing layers SE11, SE12, and SE13. At least one of the cap layers CP1, CP2, and CP3 may be omitted.

[0043] The bottom layer 63 and the shaft layer 64 of the partition wall 6 are formed of, for example, a metal material. The metal material of the bottom layer 63 may be, for example, molybdenum, titanium, titanium nitride (TiN), a molybdenum-tungsten alloy (MoW), or a molybdenum-niobium alloy (MoNb). The metal material of the shaft layer 64 may be, for example, aluminum, an aluminum-neodymium alloy (AlNd), an aluminum-yttrium alloy (AlY), or an aluminum-silicon alloy (AlSi). At least one of the bottom layer 63 and the shaft layer 64 may have a laminated structure of a plurality of layers. The shaft layer 64 may also include a layer formed of an insulating material.

[0044] For example, the upper portion 62 of the partition wall 6 has a laminated structure of a lower layer formed of a metal material and an upper layer formed of a conductive oxide. The metal material forming the lower layer may be, for example, titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, or a molybdenum-niobium alloy. The conductive oxide forming the upper layer may be, for example, ITO or IZO. The upper portion 62 may have a single layer structure of a metal material. Furthermore, the upper portion 62 may include a layer formed of an insulating material.

[0045] A common voltage is supplied to the partition 6. This common voltage is supplied to each of the upper electrodes UE1, UE2, and UE3 in contact with the side surfaces of the lower portion 61. A pixel voltage corresponding to the video signal of the signal line SL is supplied to each of the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of the subpixels SP1, SP2, and SP3, respectively.

[0046] The organic layers OR1, OR2, and OR3 emit light in response to the application of a voltage. Specifically, when a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the organic layer OR1 emits light in the blue wavelength region. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the organic layer OR2 emits light in the green wavelength region. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the organic layer OR3 emits light in the red wavelength region.

[0047] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include color filters that convert the light emitted by the light-emitting layers into light of the colors corresponding to the subpixels SP1, SP2, and SP3. The display device DSP may also include a layer including quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the colors corresponding to the subpixels SP1, SP2, and SP3.

[0048] 4 is a schematic plan view showing elements for detecting a touch operation on the display area DA. The display device DSP has a plurality of segments SG that function as electrodes for the touch sensor. These segments SG are composed of partition walls 6 and upper electrodes UE1, UE2, and UE3.

[0049] 4, 16 segments SG (SG1 to SG16) overlapping with the display area DA are arranged in a matrix of 4 columns by 4 rows, although the number and arrangement of the segments SG are not limited to this example.

[0050] The segments SG1 to SG16 are connected to the terminal section T via lead wires L1 to L16 arranged in the peripheral area SA, respectively. In the example of FIG. 4, the lead wires L1 to L3 and L5 to L7 of the segments SG1 to SG3 and SG5 to SG7 pass between the display area DA and the end E1 of the substrate 10 on the left side in the figure. The lead wires L9 to L11 and L13 to L15 of the segments SG9 to SG11 and SG13 to SG15 pass between the display area DA and the end E2 of the substrate 10 on the right side in the figure. The lead wires L4, L8, L12 and L16 of the segments SG4, SG8, ​​SG12 and SG16 are generally arranged between the display area DA and the terminal section T.

[0051] The segments SG6, SG7, SG10, and SG11 are surrounded by other segments SG. In order to enable the connection of such segments SG6, SG7, SG10, and SG11 to the lead wires L6, L7, L10, and L11, relays R6, R7, R10, and R11 are disposed in the display area DA in the example of FIG.

[0052] The relay parts R6, R7, R10, and R11 connect the segments SG6, SG7, SG10, and SG11 to the leads L6, L7, L10, and L11, respectively. The relay parts R6 and R7 are located between the segments SG2 and SG3. The relay parts R10 and R11 are located between the segments SG14 and SG15.

[0053] The detection controller CT2 supplies drive signals at a predetermined cycle to each of the segments SG1 to SG16 via the leads L1 to L16. The drive signals charge the capacitance of the segments SG1 to SG16 themselves.

[0054] After supplying the drive signals, the detection controller CT2 reads detection signals (output voltages) from the segments SG1 to SG16 via the leads L1 to L16. The detection signals correspond to the amounts of charge stored in the capacitances of the segments SG1 to SG16 themselves, for example.

[0055] Such detection signals have different values ​​for segments SG1 to SG16 arranged in the XY plane (detection surface) that are close to an object such as a user's finger and the other segments SG. Therefore, the detection controller CT2 can detect the position information of the object based on the detection signals of each segment SG.

[0056] During the operation of the display device DSP, a display period for displaying an image and a sensor period for detecting a touch are repeated. In the display period, a display voltage is written to each of the display elements DE1, DE2, and DE3. In the sensor period, a drive signal is supplied to and read from the segments SG1 to SG16. The display voltage written in the display period is maintained in the sensor period. It should be noted that the detection method using the segments SG1 to SG16 and the operation of the display device DSP are not limited to those exemplified here.

[0057] 5 is a schematic enlarged plan view of the segment SG, showing the segments SG10, SG11, SG14, and SG15, and portions of the lead wires L10, L11, L14, and L15.

[0058] 5, the partition walls 6 include two types of partition walls 6A and 6B (first and second partition walls). The width of the partition wall 6A is greater than the width of the partition wall 6B.

[0059] The partition wall 6A has a lattice shape including a plurality of portions extending in the X direction and a plurality of portions extending in the Y direction. In the example of FIG. 5, the partition wall 6A surrounds the pixel PX composed of the sub-pixels SP1, SP2, and SP3. The partition wall 6B is disposed between the sub-pixels SP1, SP2, and SP3 (display elements DE1, DE2, and DE3) included in one lattice of the partition wall 6A.

[0060] Note that the configurations of the partition walls 6A and 6B are not limited to the example shown in FIG. 5. For example, the partition wall 6A may have a lattice shape surrounding two or more pixels PX.

[0061] The segments SG1 to SG16 are divided by the slit SL1. In the example of FIG. 5, the slit SL1 is provided entirely in the partition wall 6A. That is, the slit SL1 divides the partition wall 6A into a first portion P1 and a second portion P2.

[0062] The relay portions R10 and R11 are constituted by the partition wall 6 and the upper electrodes UE1, UE2, and UE3 in the same manner as the segment SG. The same applies to the relay portions R6 and R7. These relay portions R6, R7, R10, and R11 are divided from the surrounding segments SG2, SG3, SG14, and SG15 by the slit SL1 formed in the partition wall 6A.

[0063] FIG. 6 is a schematic cross-sectional view of the display device DSP along the line VI-VI in FIG. 5. In this figure, the illustration of the substrate 10, the circuit layer 11, the sealing layer SE2, and the resin layer RS2 is omitted.

[0064] The partition wall 6A has a width Wa. The partition wall 6B has a width Wb smaller than the width Wa (Wb < Wa). In the example of FIG. 6, the width of the rib 5 below the partition wall 6A is larger than the width of the rib 5 below the partition wall 6B. As another example, the widths of the ribs 5 below the partition walls 6A and 6B may be the same.

[0065] The first part P1 of the partition wall 6A has a width Wp1. The second part P2 of the partition wall 6A has a width Wp2. The slit SL1 has a width Ws1. In the example of FIG. 6, the widths Wp1 and Wp2 are equal (Wp1 = Wp2). Also, the width Ws1 is smaller than the widths Wp1 and Wp2 (Ws1 < Wp1, Wp2). In one example, the widths Wp1 and Wp2 are equal to the width Wb (Wp1 = Wp2 = Wb). Also, the sum of the widths Wp1, Wp2, and Ws1 is equal to the width Wa (Wp1 + Wp2 + Ws1 = Wa).

[0066] Note that the relationships of the widths Wa, Wb, Wp1, Wp2, and Ws1 are not limited to those shown here. As another example, the widths Wp1, Wp2, and Wb may be different. Also, the width Ws1 may be greater than or equal to the widths Wp1 and Wp2.

[0067] The partition wall 6A, the partition wall 6B, the first part P1, and the second part P2 are all in an overhanging shape. That is, the upper portions 62 of the partition wall 6A, the partition wall 6B, the first part P1, and the second part P2 all protrude from both side surfaces of the shaft layer 64.

[0068] In the example of FIG. 6, the ribs 5 below the first part P1 and the second part P2 are continuous. That is, the rib 5 is not divided at the slit SL1. From another perspective, the slit SL1 overlaps the rib 5 in the Z direction. Also, in the example of FIG. 6, the slit SL1 does not overlap the lower electrodes LE1, LE2, and LE3 in the Z direction.

[0069] The slit SL1 is not provided with the stacked films FL1, FL2, and FL3 and the sealing layers SE11, SE12, and SE13. The slit SL1 is filled with the resin layer RS1. The resin layer RS1 is in contact with the rib 5 at the slit SL1.

[0070] Note that the rib 5 may be divided at the slit SL1. Also, any one of the stacked films FL1, FL2, and FL3 and the sealing layers SE11, SE12, and SE13 may be arranged in the slit SL1.

[0071] In the present embodiment described above, the partition wall 6 and the upper electrodes UE1, UE2, and UE3 for supplying a common voltage to the display elements DE1, DE2, and DE3 also serve as electrodes for the touch sensor. With this configuration, the display device DSP can be made thinner than when electrodes for the touch sensor are provided separately. In addition, the number of steps for manufacturing the display device DSP can be reduced, and as a result, the manufacturing cost of the display device DSP can be reduced.

[0072] Each layer constituting the laminated films FL1, FL2, and FL3 is formed by deposition. The overhanging partition 6 also plays a role in dividing these laminated films FL1, FL2, and FL3 during deposition. This allows the laminated films FL1, FL2, and FL3 to be individually sealed by the partition 6 and the sealing layers SE11, SE12, and SE13, respectively, as shown in FIG. 3. In this configuration, it is possible to effectively prevent moisture from penetrating the laminated films FL1, FL2, and FL3. Even if moisture penetrates into any of the laminated films FL1, FL2, and FL3, the influence is unlikely to extend to the surrounding laminated films.

[0073] An electronic device equipped with a display device DSP may include an antenna for near field communication (NFC). This antenna is disposed, for example, facing the rear surface of the display device DSP (the lower surface of the substrate 10 shown in FIG. 3), and wirelessly communicates with other electronic devices through the display device DSP.

[0074] The partitions 6 and the upper electrodes UE1, UE2, and UE3 arranged in the display area DA constitute a common electrode to which a common voltage is applied. During wireless communication, an eddy current is generated in the common electrode due to the magnetic field generated by the antenna. This eddy current generates a magnetic field in a direction that cancels the magnetic field, and the signal strength is attenuated. Therefore, when wireless communication is performed via the display device DSP, the communication sensitivity may decrease.

[0075] In contrast, in this embodiment, the common electrode formed by the partition wall 6 and the upper electrodes UE1, UE2, and UE3 is divided into a plurality of segments SG by the slits SL1. In this case, eddy currents are suppressed more effectively than in the case where the common electrode is not divided, and the decrease in communication sensitivity can be mitigated.

[0076] Furthermore, electronic devices incorporating the display device DSP may include an optical sensor such as an illuminance sensor that detects external light. When such an optical sensor is disposed on the rear side of the display device DSP, the display device DSP is required to have light transmissivity.

[0077] However, each of the lower electrodes LE1, LE2, and LE3 includes the above-mentioned reflective layer. Also, the partition wall 6, at least a part of which is made of a metal material, has a light-shielding property. Therefore, if the lower electrodes LE1, LE2, and LE3 and the partition wall 6 are formed over the entire display area DA, most of the light incident on the display surface of the display device DSP may be reflected or blocked without being transmitted to the back side.

[0078] In contrast, in this embodiment, the partition 6 is divided by the slit SL1. As shown in FIG. 6, the slit SL1 does not overlap with the lower electrodes LE1, LE2, and LE3. Therefore, a part of the external light incident on the display area DA can be transmitted through the slit SL1 to the lower side of the display device DSP. This can improve the light transmittance of the display device DSP.

[0079] In this embodiment, the drive transistor 3 shown in Fig. 1 is configured by a thin film transistor including a p-type semiconductor, and its drain electrode is connected to the display element DE (lower electrodes LE1, LE2, LE3). With this configuration, even if the potential of the partition wall 6 and the upper electrodes UE1, UE2, UE3 constituting the touch detection segment SG fluctuates due to the influence of an object in contact with or close to the display area DA, the influence is unlikely to affect the voltage held by the capacitor 4. Therefore, stable image display is possible.

[0080] The display device DSP according to the second to fourth embodiments will be described below. In these embodiments, the same configuration as in the first embodiment can be applied to configurations that are not specifically mentioned.

[0081] [Second embodiment] Fig. 7 is a schematic enlarged plan view of a segment SG according to the second embodiment. In this figure, like Fig. 5, segments SG10, SG11, SG14, and SG15 and parts of lead wires L10, L11, L14, and L15 are shown.

[0082] In this embodiment, the partition wall 6A has a plurality of slits SL2 (second slits) arranged intermittently. These slits SL2 are provided in both the portion of the partition wall 6A extending in the X direction and the portion of the partition wall 6A extending in the Y direction. In the following description, the two portions of the partition wall 6A separated by the slits SL2 are referred to as a third portion P3 and a fourth portion P4, respectively.

[0083] The slit SL2 is not provided at an intersection of the partition wall 6A. That is, the length of the slit SL2 is equal to or less than the width of one grid of the partition wall 6A. As another example, the slit SL2 may be formed across a plurality of grids.

[0084] Fig. 8 is a schematic cross-sectional view of the display device DSP taken along line VIII-VIII in Fig. 7. In this figure, the substrate 10, the circuit layer 11, the sealing layer SE2, and the resin layer RS2 are omitted, as in Fig. 6. The configuration in the vicinity of the slit SL1 is the same as in the example of Fig. 6.

[0085] The third portion P3 of the partition wall 6A separated by the slit SL2 has a width Wp3. The fourth portion P4 of the partition wall 6A has a width Wp4. The slit SL2 has a width Ws2. For example, the widths Wp3, Wp4, and Ws2 are equal to the widths Wp1, Wp2, and Ws1, respectively.

[0086] The third portion P3 and the fourth portion P4 each have an overhanging shape. That is, the upper portions 62 of the third portion P3 and the fourth portion P4 each protrude from both side surfaces of the shaft layer 64.

[0087] In the example of Fig. 8, the rib 5 below the third portion P3 and the fourth portion P4 is continuous. That is, the rib 5 is not divided at the slit SL2. From another point of view, the slit SL2 overlaps with the rib 5 in the Z direction. Also, in the example of Fig. 8, the slit SL2 does not overlap with the lower electrodes LE1, LE2, and LE3 in the Z direction.

[0088] Like the slit SL1, the stacked films FL1, FL2, FL3 and the sealing layers SE11, SE12, SE13 are not provided in the slit SL2. The slit SL2 is filled with the resin layer RS1. The resin layer RS1 is in contact with the rib 5 at the slit SL2.

[0089] The rib 5 may be divided at the slit SL2. Any of the stacked films FL1, FL2, FL3 and the sealing layers SE11, SE12, SE13 may be disposed in the slit SL2.

[0090] 5, there is a possibility that the appearance of the reflection of external light by the partition 6A may differ between the portion where the slit SL1 is provided and other portions. In contrast, by providing a plurality of slits SL2 in the partition 6A as in this embodiment, it is possible to suppress the change in the appearance of the reflection caused by the slit SL1 and improve the display quality.

[0091] Moreover, by providing the slits SL2, the light transmittance of the display device DSP can be further increased, which improves the sensitivity of an optical sensor disposed on the back surface side of the display device DSP.

[0092] [Third embodiment] In the third embodiment, a touch detection method different from that in the first embodiment and a specific configuration for realizing the touch detection method will be disclosed.

[0093] 9 is a diagram showing a touch detection method according to the third embodiment. In this embodiment, it is assumed that a plurality of detection electrodes Rx are further used in addition to a plurality of segments SG to detect an object in contact with or in proximity to the display area DA.

[0094] The detection electrodes Rx are disposed above the segments SG and face the segments SG via an insulating layer. The detection controller CT2 inputs a drive signal to the segments SG. At this time, a detection signal is output from the detection electrodes Rx to the detection controller CT2.

[0095] A capacitance C is formed between the detection electrode Rx and the segment SG. When an object such as a user's finger approaches the detection electrode Rx, the capacitance C is affected, and the detection signal changes accordingly according to the capacitance C. The detection controller CT2 detects the position information of the object in response to such a change in the detection signal.

[0096] Fig. 10 is a schematic cross-sectional view showing an example of the configuration of a display device DSP having detection electrodes Rx. In the example of this figure, a substrate 20 (second substrate) having detection electrodes Rx is bonded to the above-mentioned substrate 10 (first substrate) by an adhesive layer AD. Note that in Fig. 10, elements other than the segments SG formed on the substrate 10 are omitted.

[0097] The substrate 20 is formed of glass or a resin film, similar to the substrate 10. The detection electrodes Rx may be provided on the lower surface of the substrate 20 as shown in the figure, or on the upper surface. The adhesive layer AD is, for example, OCA, and is formed on the resin layer RS2 shown in FIG.

[0098] 11 is a schematic cross-sectional view showing another example of the configuration of the display device DSP including the detection electrodes Rx. In the example of this figure, the detection electrodes Rx are disposed on the sealing layer SE2 and covered with the resin layer RS2. Note that the position of the detection electrodes Rx is not limited to this example. The detection electrodes Rx may be disposed between other layers formed on the substrate 10.

[0099] 10 and 11, the detection electrodes Rx can be formed of conductive thin metal wires. Alternatively, the detection electrodes Rx may be formed of a transparent conductive oxide such as ITO or IZO.

[0100] 12 is a schematic plan view of a segment SG according to the present embodiment. In the example of this figure, eight segments SG (SG1 to SG8) are arranged in a display area DA.

[0101] The segments SG1 to SG8 are all elongated in the Y direction and aligned in the X direction. That is, the extension direction (first direction) of the segments SG1 to SG8 is parallel to the extension direction of the signal line SL shown in Fig. 1. For example, the segments SG1 to SG8 have the same shape, but are not limited to this example. The segments SG1 to SG8 are connected to the terminal portion T via the lead wires La1 to La8.

[0102] 13 is a schematic plan view of the detection electrodes Rx according to the present embodiment. In the example of this figure, eight detection electrodes Rx (Rx1 to Rx8) are arranged in the display area DA.

[0103] The detection electrodes Rx1 to Rx8 each have a shape elongated in the X direction and are aligned in the Y direction. That is, the extension direction (second direction) of the detection electrodes Rx1 to Rx8 is parallel to the extension direction of the scanning lines GL shown in FIG. 1. In the example of FIG. 13, both ends of the detection electrodes Rx1 to Rx8 are located in the peripheral area SA. These both ends have a larger width in the Y direction than the portions of the detection electrodes Rx1 to Rx8 located in the display area DA. The shape of the detection electrodes Rx1 to Rx8 is not limited to this example. The detection electrodes Rx1 to Rx8 may have a constant width over the entire area in the X direction.

[0104] The detection electrodes Rx1 to Rx8 are connected to the terminal portion T via a pair of lead wires Lb1 to Lb8. As another example, the detection electrodes Rx1 to Rx8 may be connected to the terminal portion T via one lead wire Lb1 to Lb8, respectively.

[0105] 10, when the detection electrodes Rx1 to Rx8 are formed on the substrate 20, the lead wires Lb1 to Lb8 and the terminal portions to which they are connected are provided on the substrate 20. In other words, the lead wires La1 to La8 of the segments SG1 to SG8 and the lead wires Lb1 to Lb8 of the detection electrodes Rx1 to Rx8 may be connected to different terminal portions.

[0106] 13, a plurality of floating electrodes FE (dummy electrodes) are further arranged at a distance from the detection electrodes Rx1 to Rx8. The floating electrodes FE are formed in the same layer and made of the same material as the detection electrodes Rx1 to Rx8.

[0107] The floating electrodes FE are arranged in the X direction (extension direction of the detection electrodes Rx) in the region between the adjacent detection electrodes Rx and in the region outside the detection electrodes Rx1, Rx8 located at both ends in the Y direction among the detection electrodes Rx1 to Rx8. The floating electrodes FE may be rectangular as shown in the figure, or may have another shape. By providing such floating electrodes FE, it is possible to suppress the change in the reflective appearance caused by the detection electrodes Rx1 to Rx8 and improve the display quality.

[0108] 12 and 13, a configuration in which eight segments SG and eight detection electrodes Rx are provided is illustrated, but the numbers of segments SG and detection electrodes Rx are not limited to this example. Also, the numbers of segments SG and detection electrodes Rx may be different.

[0109] 14 is a schematic enlarged plan view showing an example of a configuration applicable to the segment SG according to this embodiment, in which the vicinity of the boundary between the segments SG1 and SG2 and the lead wires La1 and La2 are shown.

[0110] The segments SG1 to SG8 include partition walls 6A and 6B as in the example of FIG. 5, and are divided by slits SL1. In the example of FIG. 14, partition walls 6A are arranged between the pixels PX arranged in the X direction. Meanwhile, partition walls 6B having a width smaller than that of the partition walls 6A are arranged between the pixels PX arranged in the Y direction and between the sub-pixels SP1, SP2, and SP3 of each pixel PX. With this configuration, the partition walls 6A extending in the X direction can be reduced compared to the example of FIG. 5, and the width of the pixel PX in the Y direction can be increased. As a result, it is possible to increase the aperture ratio of the sub-pixels SP1, SP2, and SP3 constituting the pixel PX, and improve the display quality. The slits SL1 are provided in the partition walls 6A, for example, as shown in the figure, and extend in the Y direction.

[0111] 15 is a schematic enlarged plan view showing another example of a configuration applicable to the segment SG according to the present embodiment. In the example shown in this figure, the partition wall 6A has a plurality of slits SL2 arranged intermittently.

[0112] The slits SL2 have a shape elongated in the Y direction, for example, and are provided in the partition wall 6A in a portion extending in the Y direction. As another example, as shown in FIG. 7, the partition wall 6A may be in a lattice shape, and the slits SL2 may be provided in both the portion extending in the X direction and the portion extending in the Y direction of the partition wall 6A. By providing the slits SL2 in the partition wall 6A, it is possible to suppress the appearance of reflection caused by the slits SL1 and improve the display quality. In addition, the slits SL2 can also increase the translucency of the display device DSP.

[0113] 16 is a schematic enlarged plan view showing yet another example of a configuration applicable to the segment SG according to the present embodiment. In the example shown in this figure, the segment SG1 has a plurality of sub-segments SGa. Adjacent sub-segments SGa are separated by a slit SL3 (third slit). In addition, each sub-segment SGa is connected by a connection part CN.

[0114] The slits SL3 extend in the Y direction like the slits SL1, and have, for example, the same width as the slits SL1. In the example of Fig. 16, a slit SL3 is provided between each pair of pixels PX adjacent to each other in the X direction. That is, one pixel row aligned in the Y direction is disposed between adjacent slits SL3. As another example, two or more pixel rows may be disposed between adjacent slits SL3.

[0115] In the example of Fig. 16, the connection part CN is formed by a partition wall 6A extending in the X direction and connects one end of each sub-segment SGa in the Y direction. A lead wire La1 is connected to the connection part CN. The other end of the sub-segment SGa in the Y direction is separated by a slit SL3. As another example, both ends of the sub-segment SGa in the Y direction may be connected by the connection part CN.

[0116] Like the segment SG1, the segments SG2 to SG8 have a plurality of sub-segments SGa separated by slits SL3 and a connection portion CN that connects these sub-segments SGa. In this way, by providing the slits SL3 in each of the segments SG1 to SG8, ​​it is possible to suppress the appearance of reflection caused by the slits SL1 and improve the display quality. In addition, the slits SL3 can also increase the light transmittance of the display device DSP.

[0117] [Fourth embodiment] In the fourth embodiment, another configuration for realizing a touch detection method similar to that of the third embodiment will be disclosed.

[0118] Fig. 17 is a schematic plan view of a segment SG according to the fourth embodiment. As in the example of Fig. 12, eight segments SG (SG1 to SG8) are arranged in a display area DA. However, in the example of Fig. 17, each of the segments SG1 to SG8 has a shape elongated in the X direction and is lined up in the Y direction. That is, the extension direction (first direction) of the segments SG1 to SG8 is parallel to the extension direction of the scanning lines GL shown in Fig. 1.

[0119] The segments SG1 to SG8 are connected to the terminal portion T via pairs of lead wires La1 to La8. As another example, the segments SG1 to SG8 may be connected to the terminal portion T via one lead wire La1 to La8, respectively.

[0120] Fig. 18 is a schematic plan view of the detection electrodes Rx according to this embodiment. As in the example of Fig. 13, eight detection electrodes Rx (Rx1 to Rx8) are arranged in the display area DA. However, in the example of Fig. 18, each of the detection electrodes Rx1 to Rx8 has a shape elongated in the Y direction and is aligned in the X direction. That is, the extension direction (second direction) of the detection electrodes Rx1 to Rx8 is parallel to the extension direction of the signal lines SL shown in Fig. 1. The detection electrodes Rx1 to Rx8 are connected to the terminal portion T via the lead wires Lb1 to Lb8.

[0121] 13, a plurality of floating electrodes FE are arranged around the detection electrodes Rx1 to Rx8. The floating electrodes FE are arranged in the Y direction (extension direction of the detection electrodes Rx) in regions between adjacent detection electrodes Rx and in regions outside the detection electrodes Rx1, Rx8 located at both ends in the X direction among the detection electrodes Rx1 to Rx8.

[0122] 17 and 18, a configuration in which eight segments SG and eight detection electrodes Rx are provided is illustrated, but the numbers of segments SG and detection electrodes Rx are not limited to this example. Also, the numbers of segments SG and detection electrodes Rx may be different.

[0123] FIG. 19 is a schematic enlarged plan view showing an example of a configuration applicable to the segment SG according to the present embodiment. In this figure, the vicinity of the boundary between the segments SG1 and SG2 and the lead wires La1 and La2 are shown. The segments SG1 to SG8 are provided with the partition walls 6A and 6B as in the example of FIG. 14, and are divided by the slits SL1. In the example of FIG. 19, the partition walls 6A are arranged between the pixels PX arranged in the Y direction. Meanwhile, the partition walls 6B having a width smaller than that of the partition walls 6A are arranged between the pixels PX arranged in the X direction and between the sub-pixels SP1, SP2, and SP3 in each pixel PX. With this configuration, the partition walls 6A extending in the Y direction can be reduced compared to the example of FIG. 5, and the width of the pixel PX in the X direction can be increased. As a result, it is possible to increase the aperture ratio of the sub-pixels SP1, SP2, and SP3 constituting the pixel PX, and improve the display quality. The slits SL1 are provided in the partition walls 6A as shown in the figure, for example, and extend in the X direction.

[0124] Fig. 20 is a schematic enlarged plan view showing another example of a configuration applicable to the segment SG according to the present embodiment. In the example of this figure, the partition 6A has a plurality of slits SL2 arranged intermittently, similar to the example of Fig. 15.

[0125] The slits SL2 have a shape elongated in the X direction, for example, and are provided in a portion of the partition 6A extending in the X direction. As another example, as shown in Fig. 7, the partition 6A may have a lattice shape, and the slits SL2 may be provided in both the portion of the partition 6A extending in the X direction and the portion of the partition 6A extending in the Y direction.

[0126] Fig. 21 is a schematic enlarged plan view showing yet another example of a configuration applicable to the segment SG according to the present embodiment. In the example of this figure, the segment SG1 has a plurality of sub-segments SGa separated by slits SL3, as in the example of Fig. 16. In addition, each sub-segment SGa is connected by a connection part CN.

[0127] The slits SL3 extend in the X direction like the slits SL1. In the example of Fig. 21, a slit SL3 is provided between each pair of pixels PX adjacent to each other in the Y direction. That is, one pixel row aligned in the X direction is disposed between adjacent slits SL3. As another example, two or more pixel rows may be disposed between adjacent slits SL3.

[0128] In the example of Fig. 21, both ends of the subsegment SGa in the X direction are connected by a connection part CN. However, as in the example of Fig. 16, one end of the subsegment SGa may be connected by a connection part CN and the other end may not be connected by the connection part CN.

[0129] The configurations of the segments SG and the detection electrodes Rx disclosed in the third and fourth embodiments are merely examples. Various configurations other than those disclosed in the third and fourth embodiments can be applied to the segments SG and the detection electrodes Rx.

[0130] All display devices that can be implemented by those skilled in the art through appropriate design modifications based on the display devices described above as the embodiments of the present invention belong to the scope of the present invention as long as they include the gist of the present invention.

[0131] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, those in which a person skilled in the art appropriately adds or removes components or modifies the design of the above-mentioned embodiment, or adds or omits steps or modifies conditions, are also included in the scope of the present invention as long as they include the gist of the present invention.

[0132] Furthermore, with regard to other effects and advantages brought about by the aspects described in the above-mentioned embodiments, those which are obvious from the description in this specification or which can be appropriately thought up by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0133] DSP...display device, DA...display area, SA...peripheral area, PX...pixel, SP1, SP2, SP3...subpixel, LE1, LE2, LE3...lower electrode, OR1, OR2, OR3...organic layer, UE1, UE2, UE3...upper electrode, SE11, SE12, SE13...sealing layer, 5...rib, 6...partition wall, 61...lower part, 62...upper part, 63...bottom layer, 64...axis layer, SG...segment, SL1, SL2, SL3...slit, Rx...detection electrode.

Claims

1. a plurality of display elements each including a lower electrode, an upper electrode facing the lower electrode, and an organic layer disposed between the lower electrode and the upper electrode and emitting light in response to a potential difference between the lower electrode and the upper electrode; a rib having a plurality of pixel openings overlapping the plurality of display elements, a partition wall including a conductive lower portion disposed on the rib and an upper portion protruding from a side surface of the lower portion, the partition wall surrounding each of the plurality of display elements; Equipped with the partition is divided into a plurality of segments for detecting an object in contact with or in proximity to a display area including the plurality of display elements; Display device.

2. A terminal portion disposed in a peripheral region surrounding the display region; a plurality of lead wires arranged in the peripheral region and connecting the plurality of segments and the terminal portion; Further comprising: The display device according to claim 1 .

3. The partition wall is A lattice-shaped first partition wall; a second partition disposed between a plurality of display elements included in one grid of the first partition; Including, The width of the first partition is greater than the width of the second partition. The display device according to claim 1 .

4. The plurality of segments are separated by a first slit provided in the first partition wall. The display device according to claim 3 .

5. The first slit overlaps with the rib. The display device according to claim 4.

6. a first sealing layer covering the plurality of display elements and the partition wall; a resin layer covering the first sealing layer; Further equipped with The first slit is filled with the resin layer. The display device according to claim 4.

7. The first partition has a plurality of second slits arranged intermittently. The display device according to claim 4.

8. The length of the second slit is equal to or less than the width of one of the lattices of the first partition wall. The display device according to claim 7.

9. The upper electrode is in contact with the lower portion. The display device according to claim 1 .

10. A common voltage is supplied to the upper electrode through the partition wall. The display device according to claim 9.

11. a plurality of pixel circuits each driving the plurality of display elements; Each of the pixel circuits includes a driving transistor having a p-type semiconductor layer, the lower electrode is connected to a drain electrode of the driving transistor; The display device according to claim 10.

12. Further, a plurality of detection electrodes are provided facing the plurality of segments and outputting a signal according to a capacitance between the plurality of segments and the detection electrodes. The display device according to claim 1 .

13. The plurality of segments extend in a first direction and are arranged in a second direction intersecting the first direction, The plurality of detection electrodes extend in the second direction and are arranged in the first direction. The display device according to claim 12.

14. a plurality of pixel circuits each driving the plurality of display elements; A plurality of signal lines for supplying video signals to the plurality of pixel circuits; A plurality of scanning lines for supplying scanning signals to the plurality of pixel circuits; Further equipped with the first direction is parallel to an extension direction of the signal lines, The second direction is parallel to an extension direction of the plurality of scanning lines. The display device according to claim 13.

15. a plurality of pixel circuits each driving the plurality of display elements; A plurality of signal lines for supplying video signals to the plurality of pixel circuits; A plurality of scanning lines for supplying scanning signals to the plurality of pixel circuits; Further equipped with the first direction is parallel to an extension direction of the plurality of scanning lines, the second direction is parallel to an extension direction of the signal lines; The display device according to claim 13.

16. a first substrate on which the partition wall is formed; a second substrate on which the plurality of detection electrodes are formed; an adhesive layer that bonds the first substrate and the second substrate; Equipped with The display device according to claim 12.

17. a first sealing layer covering the plurality of display elements and the partition wall; a resin layer covering the first sealing layer; A second sealing layer covering the resin layer; Further equipped with the plurality of detection electrodes are disposed on the second sealing layer; The display device according to claim 12.

18. The semiconductor device further includes a plurality of floating electrodes disposed between two adjacent detection electrodes among the plurality of detection electrodes and spaced apart from the two detection electrodes. The display device according to claim 12.

19. The plurality of floating electrodes are arranged in an extension direction of the plurality of detection electrodes. The display device according to claim 18.

20. At least one of the plurality of segments is A plurality of sub-segments separated by a third slit; A connection portion that connects the plurality of sub-segments; Including, The display device according to claim 12.

Images