Semiconductor device

Abstract

To provide a semiconductor device in which the deterioration of characteristics is suppressed.SOLUTION: A semiconductor device 100 includes a substrate 10, a plurality of first FETs 35a including a plurality of first gate electrodes 14a and arranged in a first direction, a plurality of second FETs 35b including a plurality of second gate electrodes 14b and arranged in the first direction, and a plurality of third FETs 35c including a plurality of third gate electrodes 14c, arranged in the first direction, and having the second FETs held between the first FETs and the third FETs in a second direction Y that intersects with the first direction. A second central part distance of every other one of the second gate electrodes at a central part of the first FETs, the second FETs, and the third FETs in the first direction X is larger than a second end part distance of every other one of the second gate electrodes at a first end part close to a first end of the first FETs, the second FETs, and the third FETs in the first direction. The second end part distance is smaller than a first end part distance of every other one of the first gate electrodes at the first end part.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] In a field effect transistor (FET) having finger-shaped source, gate and drain electrodes, it is known to arrange a plurality of unit FETs having a source, gate and drain electrode in the direction of electrode extension (for example, Patent Documents 1 to 3). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2002-299351 A [Patent Document 2] US Patent Application Publication No. 2017 / 0271329 [Patent Document 3] JP 2022-135899 A Summary of the Invention [Problem to be solved by the invention]

[0004] In a semiconductor device in which multiple unit FETs are arranged, the unit FETs located in the center have poorer heat dissipation than the unit FETs located at the ends. This results in a large temperature difference between the unit FETs in the center and at the ends, which causes the characteristics of the unit FETs to become non-uniform. This leads to deterioration of the characteristics of the semiconductor device.

[0005] The present disclosure has been made in consideration of the above problems, and aims to suppress deterioration of characteristics. [Means for solving the problem]

[0006] One embodiment of the present disclosure is a semiconductor device comprising: a substrate; a plurality of first FETs, each comprising a plurality of first gate electrodes, arranged on the substrate in a first direction; a plurality of second FETs, each comprising a plurality of second gate electrodes, arranged in the first direction; and a plurality of third FETs, each comprising a plurality of third gate electrodes, arranged in the first direction and sandwiching the plurality of second FETs between the plurality of first FETs in a second direction intersecting the first direction, wherein a second central distance of every second gate electrode of the plurality of second gate electrodes at a central portion in the first direction of the plurality of first FETs, the plurality of second FETs and the plurality of third FETs is larger than a second end distance of every second gate electrode of the plurality of first FETs, the plurality of second FETs and the plurality of third FETs at a first end portion near a first end in the first direction of the plurality of first FETs, the plurality of second FETs and the plurality of third FETs, and the second end distance is smaller than a first end distance of every first gate electrode at the first end portion. Effect of the Invention

[0007] According to the present disclosure, deterioration of characteristics can be suppressed. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a cross-sectional view taken along line AA in FIG. [Diagram 3] FIG. 3 is a cross-sectional view taken along line BB in FIG. [Figure 4] FIG. 4 is a diagram showing an arrangement of gate electrodes in a semiconductor device according to a first comparative example. [Diagram 5] FIG. 5 is a diagram showing an arrangement of gate electrodes in a semiconductor device according to a second comparative example. [Figure 6] FIG. 6 is a diagram showing an arrangement of gate electrodes in the semiconductor device according to the first embodiment. [Figure 7] FIG. 7 is a diagram showing an arrangement of gate electrodes in a semiconductor device according to a second embodiment. [Figure 8]FIG. 8 is a diagram showing an arrangement of gate electrodes in a semiconductor device according to a third comparative example. [Figure 9] FIG. 9 is a plan view of a semiconductor device in accordance with a third embodiment. [Figure 10] FIG. 10 is a plan view of a semiconductor device according to a first modification of the third embodiment. [Figure 11] FIG. 11 is a diagram showing a distance D with respect to a position X in the semiconductor device according to the fourth embodiment. [Figure 12] FIG. 12 is a diagram showing a distance D with respect to a position X in a semiconductor device according to a first modification of the fourth embodiment. [Figure 13] FIG. 12 is a diagram showing a distance D with respect to a position X in a semiconductor device according to a second modification of the fourth embodiment. [Figure 14] FIG. 14 is a diagram showing a distance D with respect to a position X in a semiconductor device according to a third modification of the fourth embodiment. [Figure 15] FIG. 15 is a diagram showing an arrangement of gate electrodes in a semiconductor device according to a fourth modification of the fourth embodiment. [Figure 16] FIG. 16 is a diagram showing an arrangement of gate electrodes in a semiconductor device according to a fifth modification of the fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] [Description of the embodiments of the present disclosure] First, the contents of the embodiments of the present disclosure will be listed and described. (1) One embodiment of the present disclosure is a semiconductor device comprising: a substrate; a plurality of first FETs, each of which has a plurality of first gate electrodes, arranged in a first direction on the substrate; a plurality of second FETs, each of which has a plurality of second gate electrodes, arranged in the first direction; and a plurality of third FETs, each of which has a plurality of third gate electrodes, arranged in the first direction and sandwiching the plurality of second FETs between the plurality of first FETs in a second direction intersecting the first direction, wherein a second center distance between every two of the plurality of second gate electrodes at a center in the first direction of the plurality of first FETs, the plurality of second FETs, and the plurality of third FETs is greater than a second end distance between every two of the plurality of second gate electrodes at a first end near a first end in the first direction of the plurality of first FETs, the plurality of second FETs, and the plurality of third FETs, and the second end distance is smaller than a first end distance between every two of the plurality of first gate electrodes at the first end. This allows heat to be dissipated from the second FET at the first end. This makes it possible to make the temperature distribution of the semiconductor device uniform, thereby making the FET characteristics uniform, and thus suppressing deterioration of the characteristics of the semiconductor device. (2) In the above (1), the second center distance may be greater than the first center distance of every other one of the plurality of first gate electrodes in the center. This makes it possible to make the temperature distribution of the FET more uniform, thereby further suppressing deterioration of the characteristics of the semiconductor device. (3) In the above (1), the second end distance may be smaller than the third end distance of every other one of the plurality of third gate electrodes at the first end. This makes it possible to make the temperature distribution of the FET more uniform, and thus makes it possible to further suppress deterioration of the characteristics of the semiconductor device. (4) In the above (3), the second center distance may be greater than the first center distance of every other one of the first gate electrodes in the central portion, and the second center distance may be greater than the third center distance of every other one of the third gate electrodes in the central portion. This makes it possible to make the temperature distribution of the FET more uniform. As a result, it is possible to further suppress deterioration of the characteristics of the semiconductor device. (5) In any one of (1) to (4) above, a second intermediate distance of every other one of the plurality of second gate electrodes in an intermediate portion between the central portion and the first end portion in the first direction may be greater than the second end portion distance and smaller than the second central portion distance. This makes it possible to make the temperature distribution of the FET more uniform. As a result, deterioration of the characteristics of the semiconductor device can be further suppressed. (6) In the above (1), the second center distance may be greater than the distance between every other fifth end of the second gate electrodes at a second end closer to the second end of the first FETs, the second FETs, and the third FETs, opposite to the first end, than the center. This makes it possible to make the temperature distribution of the FETs more uniform. As a result, it is possible to further suppress deterioration of the characteristics of the semiconductor device. (7) In the above (4), the second central distance may be greater than a fifth end distance of every second gate electrode at a second end closer to a second end opposite to the first end of the first FETs, the second FETs, and the third FETs than the central distance, the fifth end distance is smaller than a fourth end distance of every first gate electrode at the second end, and the second end distance is smaller than a sixth end distance of every third gate electrode at the second end. This makes it possible to make the temperature distribution of the FETs more uniform. This makes it possible to further suppress deterioration of the characteristics of the semiconductor device. (8) In any one of the above (1) to (7), the distances between the second closest first gate electrodes in the plurality of first FETs may be equal to each other, which makes it easier to design the FET. (9) In any of the above (1) to (8), the number of the first FETs, the number of the second FETs, and the number of the third FETs may be the same, so that the first source electrodes to the third source electrodes can be electrically connected to each other, and the first drain electrodes to the third drain electrodes can be electrically connected to each other. (10) In any one of the above (1) to (9), the plurality of first FETs may include a plurality of first source electrodes and a plurality of first drain electrodes, each of the plurality of first gate electrodes being sandwiched in the first direction between one of the plurality of first source electrodes and one of the plurality of first drain electrodes, the plurality of second FETs may include a plurality of second source electrodes and a plurality of second drain electrodes, each of the plurality of second gate electrodes being sandwiched in the first direction between one of the plurality of second source electrodes and one of the plurality of second drain electrodes, and the plurality of third FETs may include a plurality of third source electrodes and a plurality of third drain electrodes, each of the plurality of third gate electrodes being sandwiched in the first direction between one of the plurality of third source electrodes and one of the plurality of third drain electrodes. In this way, a plurality of FETs can be configured. (11) In the above (10), the substrate may have a first active region, a second active region, and a third active region, a first inactive region provided between the first active region and the second active region, and a second inactive region provided between the second active region and the third active region, the first FETs are provided in the first active region, the second FETs are provided in the second active region, the third FETs are provided in the third active region, each of the first source electrodes is connected to a corresponding second source electrode in the first inactive region, each of the first drain electrodes is connected to a corresponding second drain electrode in the first inactive region, each of the second source electrodes is connected to a corresponding third source electrode in the second inactive region, and each of the second drain electrodes is connected to a corresponding third drain electrode in the second inactive region. This allows the first source electrodes to the third source electrodes to be electrically connected to each other, and the first drain electrodes to the third drain electrodes to be electrically connected to each other.

[0010] [Details of the embodiment of the present disclosure] Specific examples of semiconductor devices according to embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0011] [Example 1] A semiconductor device used in an amplifier for amplifying a high-frequency signal of, for example, 0.5 GHz to 10 GHz in a base station for mobile communication will be described as an example. Fig. 1 is a plan view of the semiconductor device in the first embodiment. Figs. 2 and 3 are a cross-sectional view taken along line AA and a cross-sectional view taken along line BB in Fig. 1, respectively. The thickness direction of the substrate 10 is the Z direction, the extension direction of the finger-shaped source electrodes 12a to 12c, gate electrodes 14a to 14c, and drain electrodes 16a to 16c is the Y direction (a second direction intersecting the first direction), and the arrangement direction of the source electrodes 12a to 12c, gate electrodes 14a to 14c, and drain electrodes 16a to 16c is the X direction (a first direction).

[0012] As shown in FIGS. 1 to 3, in the semiconductor device 100 of the first embodiment, the substrate 10 includes a substrate 10a and a semiconductor layer 10b provided on the substrate 10a. In an XY plane parallel to the X and Y directions, the regions of the semiconductor layer 10b that have been inactivated by ion implantation or the like are inactive regions 13, 13a, and 13b, and the regions that have not been inactivated (i.e., the regions where a part of the substrate 10 is activated) are active regions 11a to 11c. The active regions 11a to 11c extend in the X direction. The active regions 11a to 11c are arranged in the Y direction. Between the active regions 11a and 11b in the Y direction is an inactive region 13a (first inactive region). Between the active regions 11b and 11c in the Y direction is an inactive region 13b (second inactive region).

[0013] A plurality of unit FETs 35a (first FETs) are arranged in the X direction on an active region 11a (first active region) of the substrate 10. A plurality of unit FETs 35b (second FETs) are arranged in the X direction on an active region 11b (second active region) of the substrate 10. A plurality of unit FETs 35c (third FETs) are arranged in the X direction on an active region 11c (third active region) of the substrate 10.

[0014] The unit FET 35a includes a source electrode 12a (first source electrode), a gate electrode 14a (first gate electrode), and a drain electrode 16a (first drain electrode). The source electrodes 12a and the drain electrodes 16a are alternately provided in the X direction. One gate electrode 14a is provided between one of the source electrodes 12a and one of the drain electrodes 16a.

[0015] The unit FET 35b includes a source electrode 12b (second source electrode), a gate electrode 14b (second gate electrode), and a drain electrode 16b (second drain electrode). The source electrodes 12b and the drain electrodes 16b are alternately provided in the X direction. One gate electrode 14b is provided between one of the source electrodes 12b and one of the drain electrodes 16b.

[0016] The unit FET 35c includes a source electrode 12c (third source electrode), a gate electrode 14c (third gate electrode), and a drain electrode 16c (third drain electrode). The source electrodes 12c and the drain electrodes 16c are alternately provided in the X direction. One gate electrode 14c is provided between one of the source electrodes 12c and one of the drain electrodes 16c.

[0017] An insulating layer 30 is provided on the substrate 10 so as to cover the unit FETs 35a to 35c. Source wiring connecting the source electrodes 12a to 12c, gate wiring connecting the gate electrodes 14a to 14c, and drain wiring electrically connecting the drain electrodes 16a to 16c are not shown in Figures 1 to 3.

[0018] The multiple unit FETs 35a, the multiple unit FETs 35b and the multiple unit FETs 35c overlap one another when viewed from the Y direction. The unit FETs 35a to 35c have a central portion 50 in the X direction, an end portion 51 closer to the end E1 than the central portion 50, and an end portion 52 closer to the end E2 opposite the end E1 than the central portion 50.

[0019] The gate electrodes 14a to 14c are each linearly extending in the Y direction. The X distances between the source electrodes 12a to 12c and the gate electrodes 14a to 14c are approximately equal to each other, and the distances between the gate electrodes 14a to 14c and the drain electrodes 16a to 16c are approximately equal to each other. The widths (gate lengths) in the X direction of the gate electrodes 14a and 14c are approximately equal to each other.

[0020] The distance between the gate electrodes 14a sandwiching the drain electrode 16a may differ from the distance between the gate electrodes 14a sandwiching the source electrode 12a. Therefore, the distance D between the gate electrodes 14a is set to the distance between every other gate electrode 14a. The distance between the gate electrodes 14b and the distance between the gate electrodes 14c are also the same.

[0021] In the multiple unit FETs 35a, the distance D in the X direction between every other gate electrode 14a is approximately equal in the X direction. In the multiple unit FETs 35c, the distance D in the X direction between every other gate electrode 14c is approximately equal in the X direction. That is, in the multiple gate electrodes 14a, the distances DC1, DE1, and DE4 at the center 50, and the ends 51 and 52 are respectively equal to each other. In the multiple gate electrodes 14c, the distances DC3, DE3, and DE6 at the center 50, and the ends 51 and 52 are respectively equal to each other.

[0022] In the multiple unit FETs 35b, the distance between the gate electrodes 14b in the central portion 50 is greater than the distance between the gate electrodes 14b in the end portions 51 and 52. That is, in the multiple gate electrodes 14b, the distance DC2 in the central portion 50 is greater than the distances DE2 and DE5 at the end portions 51 and 52.

[0023] The position of end E1 is approximately the same in the multiple unit FETs 35a, 35b, and 35c. The position of end E2 is approximately the same in the multiple unit FETs 35a, 35b, and 35c. That is, the unit FET 35a closest to end E1, the unit FET 35b closest to end E1, and the unit FET 35c closest to end E1 overlap when viewed from the Y direction. The unit FET 35a closest to end E2, the unit FET 35b closest to end E2, and the unit FET 35c closest to end E2 overlap when viewed from the Y direction. The numbers of the multiple unit FETs 35a, the multiple unit FETs 35b, and the multiple unit FETs 35c are the same.

[0024] In such an arrangement, if distance DC2 is made larger than distances DE2 and DE5, distance DC2 will be larger than distances DC1 and DC3, distance DE2 will be smaller than distances DE1 and DE3, and distance DE5 will be smaller than distances DE4 and DE6.

[0025] When the semiconductor device 100 is, for example, a nitride semiconductor device, the substrate 10a is, for example, a silicon carbide (SiC) substrate, a silicon (Si) substrate, a gallium nitride (GaN) substrate, or a sapphire (Al2O3) substrate. The semiconductor layer 10b includes, for example, a nitride semiconductor layer such as a gallium nitride layer, an aluminum gallium nitride (AlGaN) layer, and / or an indium gallium nitride (InGaN) layer. When the unit FETs 35a to 35c are GaN HEMTs (Gallium Nitride High Electron Mobility Transistors), the semiconductor layer 10b includes a gallium nitride channel layer provided on the substrate 10a and an aluminum gallium nitride barrier layer provided on the channel layer. When the semiconductor device 100 is, for example, a gallium arsenide (GaAs)-based semiconductor device, the substrate 10a is, for example, a gallium arsenide substrate. The semiconductor layer 10b includes an arsenide semiconductor layer, such as a gallium arsenide layer, an aluminum gallium arsenide (AlGaAs) layer, and / or an indium gallium arsenide (InGaAs) layer, etc. The semiconductor device 100 may be a silicon semiconductor device, such as a Laterally Diffused Metal Oxide Semiconductor (LDMOS).

[0026] The source electrodes 12a to 12c and the drain electrodes 16a to 16c are metal films, for example, titanium films and aluminum films from the substrate 10 side. The gate electrodes 14a to 14c are metal films, for example, nickel films and gold films from the substrate 10 side. A low-resistance metal layer may be provided on the source electrodes 12a to 12c and the drain electrodes 16a to 16c. The metal layer is, for example, a gold layer, and has a lower resistivity than the source electrodes 12a to 12c and the drain electrodes 16a to 16c. The insulating layer 30 is, for example, an inorganic insulator layer such as a silicon nitride layer or a silicon oxide layer, an organic insulator layer such as a polyimide layer or a BCB (Benzocyclobutene) layer, or a laminated film of an inorganic insulator layer and an organic insulator layer.

[0027] The width of the source electrodes 12a to 12c in the X direction is, for example, 5 μm to 150 μm. The gate length of the gate electrodes 14a to 14c in the X direction is, for example, 0.25 μm to 2 μm. The width of the drain electrodes 16a to 16c in the X direction is, for example, 5 μm to 150 μm. The gate width of the unit FETs 35a to 35c in the Y direction is, for example, 100 μm to 400 μm.

[0028] [Comparative Example 1] 4 is a diagram showing the arrangement of gate electrodes in a semiconductor device according to Comparative Example 1. The upper diagram is a plan view showing the arrangement of gate electrodes 14a to 14c in semiconductor device 110 of Comparative Example 1. The middle diagram is a diagram showing distance D in the X direction between every other gate electrode 14a to 14c relative to the position in the X direction of semiconductor device 110. The lower diagram is an image diagram showing temperature at center line 54 in the Y direction of semiconductor device 110 relative to the position in the X direction.

[0029] As shown in the upper and middle diagrams of FIG. 4, the distance D is equal to each other in all of the gate electrodes 14a to 14c, that is, distance D0. Heat generated in the unit FETs 35a and 35c and the unit FET 35b located at the ends 51 and 52 is easily diffused to the surroundings. On the other hand, heat generated in the unit FET 35b in the central portion 50 is not easily diffused to the surroundings. As a result, as shown in the lower diagram of FIG. 4, the temperature of the unit FET 35b in the region 55 near the center in the Y direction becomes high. Therefore, the temperature difference between the unit FET 35b in the region 55 and the unit FETs 35a to 35c at the ends 51 and 52 becomes large. Therefore, the characteristics such as the high frequency characteristics of the unit FETs 35a to 35c become non-uniform. This causes the characteristics of the semiconductor device 110 to deteriorate.

[0030] [Comparative Example 2] 5 is a diagram showing the arrangement of gate electrodes in a semiconductor device according to Comparative Example 2. The upper diagram is a plan view showing the arrangement of gate electrodes 14a to 14c in semiconductor device 112 of Comparative Example 2. The middle diagram is a diagram showing distance D in the X direction between every other gate electrode 14a to 14c relative to the position in the X direction of semiconductor device 112. The lower diagram is an image diagram showing temperature at center line 54 in the Y direction of semiconductor device 112 relative to the position in the X direction.

[0031] 5, the distance DC at the central portion 50 is made larger than the distance DE at the ends 51 and 52. The distance DC at the central portion 50 is equal to each other in all of the gate electrodes 14a to 14c, and the distances DE at the ends 51 and 52 are equal to each other in all of the gate electrodes 14a to 14c.

[0032] In the unit FET 35b in the central portion 50, the density of the gate electrodes 14b in the X direction is low. Therefore, the unit FET 35b in the central portion 50 generates less heat, and the temperature of the unit FET 35b in the central portion 50 can be lowered. The density of the gate electrodes 14b in the X direction is high at the ends 51 and 52. The unit FET 35b in the region 56 near the central portion 50 among the ends 51 and 52 is surrounded on three sides by the region 57 in which the density of the gate electrodes 14a to 14c is high. The remaining direction is toward the central portion 50. Therefore, the heat generated in the unit FET 35b in the region 56 is difficult to diffuse. Therefore, as shown in the lower figure, the temperature of the unit FET 35b in the region 56 rises. This causes the temperature distribution of the unit FETs 35a to 35c to become large, and the characteristics such as the high frequency characteristics become non-uniform. Therefore, the characteristics of the semiconductor device 112 are deteriorated. Even if an optimization is attempted by changing the distances DC and DE, it is difficult to reduce the temperature distribution of the unit FETs 35a to 35c.

[0033] [Explanation of Example 1] 6 is a diagram showing the arrangement of gate electrodes in the semiconductor device according to the first embodiment. The upper diagram is a plan view showing the arrangement of gate electrodes 14a to 14c in the semiconductor device 100 of the first embodiment. The middle diagram is a diagram showing a distance D in the X direction between every other gate electrode 14a to 14c with respect to the position in the X direction of the semiconductor device 100. The lower diagram is an image diagram showing the temperature at a center line 54 in the Y direction of the semiconductor device 100 with respect to the position in the X direction.

[0034] As shown in the upper and middle diagrams of FIG. 6, the distance DC2 of the gate electrode 14b in the central portion 50 is set to be larger than the distances DC1 and DC3 of the gate electrodes 14a and 14c. The distances DE2 and DE5 of the gate electrode 14b in the ends 51 and 52 are set to be smaller than the distances DE1, DE3, DE4 and DE6 of the gate electrodes 14a and 14c. The heat generation amount of the unit FETs 35a and 35c in the ends 51 and 52 is smaller than the heat generation amount of the unit FET 35b in the ends 51 and 52. Therefore, the heat generated in the unit FET 35b in the ends 51 and 52 is easily diffused in the + direction and the - direction in the Y direction as shown by the arrow 58. This makes the temperature distribution of the unit FETs 35a to 35c more uniform as shown in the lower diagram. Therefore, the high frequency characteristics of the unit FETs 35a to 35c can be made more uniform, and deterioration of the characteristics as the semiconductor device 100 can be suppressed.

[0035] [Example 2] 7 is a diagram showing the arrangement of gate electrodes in a semiconductor device according to Example 2. The upper diagram is a plan view showing the arrangement of gate electrodes 14a to 14c in a semiconductor device 101 of Example 2. The lower diagram is a diagram showing a distance D in the X direction between every other gate electrode 14a to 14c with respect to the position in the X direction of the semiconductor device 101.

[0036] As shown in FIG. 7, in the semiconductor device 101 of the second embodiment, an intermediate portion 51a is provided between the end portion 51 and the central portion 50. An intermediate portion 52a is provided between the end portion 52 and the central portion 50. The distances D of the gate electrodes 14a to 14c in the intermediate portion 51a are DM1 to DM3, respectively. The distances D of the gate electrodes 14a to 14c in the intermediate portion 52a are DM4 to DM6, respectively. The distances DM2 and DM5 are smaller than the distance DC2 and larger than the distances DE2 and DE4. The distances DM1, DM3, DM4, and DM6 are equal to the distances DC1, DC3, DE1, DE3, DE4, and DE6. The other configurations are the same as those of the first embodiment, and the description thereof will be omitted.

[0037] 8 is a diagram showing the arrangement of gate electrodes in a semiconductor device according to Comparative Example 3. The upper diagram is a plan view showing the arrangement of gate electrodes 14a to 14c in a semiconductor device 114 of Comparative Example 3. The lower diagram is a diagram showing a distance D in the X direction between every other gate electrode 14a to 14c with respect to the position in the X direction of the semiconductor device 114.

[0038] 8, in the semiconductor device 114 of Comparative Example 3, the distance D between the gate electrodes 14a and 14c in the central portion 50 is DC and is equal to each other. The distance D between the gate electrodes 14a and 14c in the ends 51 and 52 is DE and is equal to each other. The distance D between the gate electrodes 14a and 14c in the intermediate portions 51a and 52a is DM and is equal to each other. The other configurations are the same as those of Example 2.

[0039] [simulation] The temperature distribution was simulated for Example 2 and Comparative Example 3. In the simulation, parallel heat sources corresponding to the gate electrodes 14a to 14c were provided on the substrate 10, and the heat sources were made to generate heat by passing a current through them. The simulation conditions were as follows. Substrate 10a: silicon carbide substrate with a thickness of 100 μm Semiconductor layer 10b: gallium nitride layer having a thickness of 0.6 μm Substrate 10: Width in the X direction is 3.26 mm, and width in the Y direction is 0.8 mm Size of source: Width in X direction is 5 μm, width in Y direction is 180 μm Inactive regions 13a and 13b: width in the Y direction is 10 μm Center 50: 8 gate electrodes Intermediate portions 51a and 52a: 5 gate electrodes each Ends 51 and 52: 6 gate electrodes each Distance D in Example 2 DC2=210μm, DM2, DM5=190μm, DE2, DE5=170μm DC1, DC3, DM1, DM3, DM4, DM6, DE1, DE3, DE4, DE6=190μm Distance D in Comparative Example 3 DC=210μm, DM=190μm, DE=170μm

[0040] The values ​​of the distances DC, DM, and DE in Comparative Example 3 are values ​​optimized to reduce the maximum temperature. The values ​​of the distances DC2, DM2, DM5, DE2, and DE5 in Example 2 were the same as the values ​​of the distances DC, DM, and DE optimized in Comparative Example 3. The distances DC1, DC3, DM1, DM3, DM4, DM6, DE1, DE3, DE4, and DE6 were set equal to each other.

[0041] The maximum temperatures on the substrate 10 in the simulation results in which the heat generation amounts of the heat sources were the same are shown below. Example 2: 108.2°C Comparative Example 3: 108.9°C As described above, the maximum temperature is lower in Example 2 than in Comparative Example 3 in which the distances DC, DM, and DE are optimized. It is considered that the temperature distribution in Example 2 is smaller than that in Comparative Example 3. Therefore, in the semiconductor device 101 of Example 2, the characteristics of the unit FETs 35a to 35c can be made more uniform than in the semiconductor device 114 of Comparative Example 3, and deterioration of the characteristics of the semiconductor device 101 can be suppressed.

[0042] [Example 3] Example 3 is an example of the source wiring, the gate wiring, and the drain wiring in Examples 1 and 2. Fig. 9 is a plan view of a semiconductor device according to Example 3. Fig. 9 shows a plan view of the central portion of Examples 1 and 2.

[0043] As shown in Fig. 9, the distance DC2 is greater than the distances DC1 and DC3. A source wiring 22a, a gate wiring 24a, and a drain wiring 26a are provided on the substrate 10 in the inactive region 13a between the active regions 11a and 11b. The source wiring 22a electrically connects the source electrodes 12a and 12b. The gate wiring 24a electrically connects the gate electrodes 14a and 14b. The drain wiring 26a electrically connects the drain electrodes 16a and 16b.

[0044] A source wiring 22b, a gate wiring 24b, and a drain wiring 26b are provided on the substrate 10 in the inactive region 13b between the active regions 11b and 11c. The source wiring 22b electrically connects the source electrodes 12b and 12c. The gate wiring 24b electrically connects the gate electrodes 14b and 14c. The drain wiring 26b electrically connects the drain electrodes 16b and 16c.

[0045] A drain bus bar 27 and a gate bus bar 28 are provided on the substrate 10 to sandwich the unit FETs 35a to 35c. The drain bus bar 27 is electrically connected to the drain electrodes 16a to 16c. The gate bus bar 28 is electrically connected to the gate electrodes 14a to 14c.

[0046] The source electrodes 12a to 12c are connected to the source electrodes 12a to 12c and are electrically connected to a metal layer provided on the lower surface of the substrate 10 through via holes (not shown) that penetrate the substrate 10. The source electrodes 12a to 12c may be electrically connected to a source bus bar.

[0047] As a result, a source potential is supplied to source electrodes 12a to 12c from the metal layer provided on the lower surface of substrate 10. A gate potential is supplied to gate electrodes 14a to 14c from gate bus bar 28. A drain potential is supplied to drain electrodes 16a to 16c from drain bus bar 27.

[0048] [Modification 1 of Example 3] Modification 1 of Example 3 is an example of the source wiring, the gate wiring, and the drain wiring in Examples 1 and 2. Fig. 10 is a plan view of a semiconductor device according to Modification 1 of Example 3. Fig. 10 shows a plan view of the central portion of Examples 1 and 2.

[0049] As shown in FIG. 10, two source wirings 22a are connected to one source electrode 12a. The two source wirings 22a are connected to two source electrodes 12b, two source wirings 22b, and two source electrodes 12c. A gate wiring 24 is provided between the two source wirings 22a, the two source electrodes 12b, the two source wirings 22b, and the two source electrodes 12c. The negative end of the gate wiring 24 in the Y direction is electrically connected to the gate bus bar 28. In the inactive region 13a, the gate wiring 25a crosses the source wiring 22a without contacting each other, and electrically connects the gate wiring 24 and the gate electrode 14a. In the inactive region 13b, the gate wiring 25b crosses the source wiring 22b without contacting each other, and electrically connects the gate wiring 24 and the gate electrode 14b.

[0050] As a result, the gate electrode 14c is supplied with a gate potential directly from the gate bus bar 28. The gate electrodes 14a and 14b are supplied with a gate potential from the gate bus bar 28 via the gate wirings 24, 25a and 25b. By providing the gate wiring 24, the gate resistance can be suppressed.

[0051] The via hole 20 penetrates the substrate 10, overlaps the source electrode 12a when viewed from the Z direction, and is electrically connected to the source electrode 12a. As a result, a source potential is supplied to the source electrode 12a from a metal layer provided on the lower surface of the substrate 10, a source potential is supplied to the source electrode 12b from the source electrode 12a via the source wiring 22a, and a source potential is supplied to the source electrode 12c from the source electrode 12a via the source wiring 22a, the source electrode 12b, and the source wiring 22b. The other configurations are the same as those of the third embodiment, and therefore a description thereof will be omitted.

[0052] [Example 4] FIG. 11 is a diagram showing the distance D with respect to the position X in the semiconductor device according to the fourth embodiment. As shown in FIG. 11, in the semiconductor device 104 of the fourth embodiment, the distances DC1 and DC3 of the gate electrodes 14a and 14c in the central portion 50 are larger than the distances DE1, DE3, DE4, and DE6 of the gate electrodes 14a and 14c in the end portions 51 and 52. The distance DC2 is larger than the distances DC1 and DC3, and the distances DE2 and DE5 are smaller than the distances DE1, DE3, DE4, and DE6. The other configurations are the same as those of the first embodiment, and the description thereof will be omitted. As in the fourth embodiment, the distances D of the gate electrodes 14a and 14c may be different between the central portion 50 and the end portions 51 and 52.

[0053] [Modification 1 of Example 4] 12 is a diagram showing the distance D with respect to the position X in the semiconductor device according to the first modification of the fourth embodiment. As shown in FIG. 12, in the semiconductor device 105 according to the first modification of the fourth embodiment, the distance D2 of the gate electrode 14b gradually increases from the ends E1 and E2 toward the center. The distances D1 and D3 of the gate electrodes 14a and 14c are the distance D0 and are constant. The other configurations are the same as those of the first embodiment, and the description thereof will be omitted. As in the first modification of the fourth embodiment, the distance D2 of the gate electrode 14b may gradually change as the position X moves toward the center in the X direction.

[0054] [Modification 2 of Example 4] FIG. 13 is a diagram showing the distance D with respect to the position X in the semiconductor device according to the second modification of the fourth embodiment. As shown in FIG. 13, in the semiconductor device 106 according to the second modification of the fourth embodiment, the distances D1 and D3 of the gate electrodes 14a and 14c gradually increase from the ends E1 and E2 toward the center. In the center portion 50, the distance D2 is greater than the distances D1 and D3, and in the ends 51 and 52, the distance D2 is smaller than the distances D1 and D3. The other configurations are the same as those of the first modification of the fourth embodiment, and the description thereof will be omitted. As in the second modification of the fourth embodiment, the distances D1 and D3 of the gate electrodes 14a and 14c may gradually change as the position X moves toward the center in the X direction.

[0055] [Modification 3 of Example 4] 14 is a diagram showing the distance D with respect to the position X in a semiconductor device according to the third modification of the fourth embodiment. As shown in FIG. 14, in a semiconductor device 107 according to the third modification of the fourth embodiment, the distance D between the gate electrodes 14a and 14b is the same as that in the first embodiment. The distances DC3, DE3, and DE6 of the gate electrode 14c are the same as those in the fourth embodiment. The other configurations are the same as those in the first embodiment, and the description thereof will be omitted. As in the third modification of the fourth embodiment, the distance D may be different between the gate electrodes 14a and 14c.

[0056] [Modification 4 of Example 4] 15 is a diagram showing the arrangement of gate electrodes in a semiconductor device according to Modification 4 of Example 4. The upper diagram is a plan view showing the arrangement of gate electrodes 14a to 14c in a semiconductor device 108 according to Modification 4 of Example 4. The lower diagram is a diagram showing a distance D in the X direction between every other gate electrode 14a to 14c with respect to the position in the X direction of the semiconductor device 108.

[0057] As shown in the upper diagram of Fig. 15, three rows of gate electrodes 14b arranged in the X direction are provided in the Y direction between gate electrodes 14a and 14c. The distances DC2, DE2, and DE5 in the three rows of unit FETs 35b are the same as each other. The other configurations are the same as in the first embodiment, and description thereof will be omitted. As in the fourth modification of the fourth embodiment, two or more rows of unit FETs 35b arranged in the X direction may be arranged in the Y direction.

[0058] [Modification 5 of Example 4] 16 is a diagram showing the arrangement of gate electrodes in a semiconductor device according to Modification 5 of Example 4. The upper diagram is a plan view showing the arrangement of gate electrodes 14a to 14c in a semiconductor device 109 according to Modification 5 of Example 4. The lower diagram is a diagram showing a distance D in the X direction between every other gate electrode 14a to 14c with respect to the position in the X direction of the semiconductor device 109.

[0059] 16, three columns of gate electrodes 14ba, 14b, and 14bb are provided between gate electrodes 14a and 14c in the Y direction. The distance D of gate electrodes 14ba at center portion 50 and at ends 51 and 52 is DC2a, DE2a, and DE5a, respectively. The distance D of gate electrodes 14bb at center portion 50 and at ends 51 and 52 is DC2b, DE2b, and DE5b, respectively.

[0060] In the central portion 50, the distances DC2a and DC2b are smaller than the distance DC2 and larger than the distances DC1 and DC3. In the end portion 51, the distances DE2a and DE2b are larger than the distance DE2 and smaller than the distances DE1 and DE3. In the end portion 52, the distances DE5a and DE5b are larger than the distance DE5 and smaller than the distances DE4 and DE6. This allows the temperature to be more uniform. The other configurations are the same as those in the fourth modification of the fourth embodiment, and a description thereof will be omitted. As in the fifth modification of the fourth embodiment, when two or more rows of a plurality of unit FETs 35b are arranged in the Y direction, the distances DC2a, DC2, and DC2b may be different from each other, the distances DE2a, DE2, and DE2b may be different from each other, and the distances DE5a, DE5, and DE5b may be different from each other.

[0061] According to the first to fourth embodiments and their modifications, the distance DC2 (second center distance) between the gate electrodes 14b at the center 50 in the X direction of the unit FETs 35a to 35c in the X direction is larger than the distance DE2 (second end distance) between the gate electrodes 14b at the first end 51 close to the first end E1 in the X direction of the unit FETs 35a to 35c. The distance DE2 is smaller than the distance DE1 (first end distance) between the gate electrodes 14a at the first end 51. This allows heat to be dissipated from the region 56 at the end 51 as indicated by the arrow 58, as shown in the upper diagram of FIG. 6. This allows the temperature distribution of the unit FETs 35a to 35c to be uniform, and therefore the characteristics of the unit FETs 35a to 35c to be uniform. This allows the deterioration of the characteristics of the semiconductor device to be suppressed.

[0062] The distance DC2 is greater than the distance DC1 (first central distance) between every other gate electrode 14a in the central portion 50. This makes it possible to make the temperature distribution of the unit FETs 35a to 35c more uniform, thereby making it possible to further suppress deterioration of the characteristics of the semiconductor device.

[0063] The distance DE2 is smaller than the distance DE3 (third end distance) between every other gate electrode 14c at the end 51. This allows heat to be dissipated in both the + and - directions in the Y direction from the region 56 at the end 51 as indicated by the arrows 58, as shown in the upper diagram of FIG. 6. This makes it possible to make the temperature distribution of the unit FETs 35a to 35c more uniform. This makes it possible to suppress deterioration of the characteristics of the semiconductor device.

[0064] The distance DC2 is greater than the distance DC1 and greater than the distance DC3 (third central distance) between every other gate electrode 14c in the central portion 50. This makes it possible to make the temperature distribution of the unit FETs 35a to 35c more uniform, thereby making it possible to further suppress deterioration of the characteristics of the semiconductor device.

[0065] As in the second embodiment, an intermediate portion 51a is provided between the central portion 50 and the end portion 51 in the X direction. The distance DM2 (second intermediate distance) between every other gate electrode 14b in the intermediate portion 51a is greater than the distance DE2 and smaller than the distance DC2. This makes it possible to make the temperature distribution of the unit FETs 35a to 35c more uniform. This makes it possible to further suppress deterioration of the characteristics of the semiconductor device.

[0066] As in the first to fourth embodiments and their modified examples, the distance DC2 is greater than the DE5 (fifth end distance) of every other gate electrode 14b at the second end 52 close to the second end E2 opposite to the first end E1. This allows heat to be dissipated from the region 56 at the end 52 as indicated by the arrows 58, as shown in the upper diagram of FIG. 6. This makes it possible to make the temperature distribution of the unit FETs 35a to 35c more uniform. This makes it possible to suppress deterioration of the characteristics of the semiconductor device.

[0067] The distance DE5 is smaller than the distance DE4 (fourth end distance) between every other gate electrode 14a at the second end 52. The distance DE5 is smaller than the distance DE6 (sixth end distance) between every other gate electrode 14c at the second end 52. This allows heat to be dissipated in both the + and - directions in the Y direction from the region 56 at the end 52 as indicated by the arrows 58, as shown in the upper diagram of FIG. 6. This makes it possible to make the temperature distribution of the unit FETs 35a to 35c more uniform. This makes it possible to suppress deterioration of the characteristics of the semiconductor device.

[0068] Distances DC1 to DC3 are assumed to be distances D of gate electrodes 14a and 14c including unit FETs 35a to 35c located at the center of the plurality of unit FETs 35a and 35c in the X direction. Distances DE1 to DE6 are assumed to be distances D of gate electrodes 14a and 14c including unit FETs 35a to 35c closest to ends E1 or E2. In this case, distance DC2 of unit FETs 35a to 35c can be 1.01 times or more, 1.05 times or more, or 1.1 times or more of distances DE2 and DE5. If the difference between distance DC2 and distances DE2 and DE5 is large, it becomes difficult to arrange unit FET 35b. From this viewpoint, distance DC2 can be 1.5 times or less of distances DE2 and DE5.

[0069] From the viewpoint of temperature uniformity, the distance DC2 may be 1.01 times or more, 1.05 times or more, or 1.1 times or more of the distances DC1 and DC3. From the viewpoint of facilitating the arrangement, the distance DC2 may be 1.5 times or less of the distances DC1 and DC3. From the viewpoint of temperature uniformity, the distances DE2 and DE5 may be 0.99 times or less, 0.95 times or less, or 0.9 times or less of the distances DE1, DE3, DE4, and DE6. From the viewpoint of facilitating the arrangement, the distances DE2 and DE5 may be 0.6 times or more of the distances DE1, DE3, DE4, and DE6.

[0070] If the distance D is made different among the multiple unit FETs 35a and the distance D is made different among the multiple unit FETs 35c, it becomes difficult to design the unit FETs 35a and 35c. As in the first, second and fourth embodiments, the distances D0 between the second closest gate electrodes 14a in the unit FET 35a are equal to each other. The distances D0 between the second closest gate electrodes 14c in the unit FET 35c are equal to each other. This makes it easier to design the unit FETs 35a and 35c. Note that the distances D0 being equal (approximately equal) allows for manufacturing errors.

[0071] In addition, the number of unit FETs 35a, the number of unit FETs 35b, and the number of unit FETs 35c are the same as one another. This allows the source electrodes 12a to 12c of the corresponding unit FETs 35a to 35c to be electrically connected, and the drain electrodes 16a to 16c of the corresponding unit FETs 35a to 35c to be electrically connected, as in the third embodiment and its first modified example.

[0072] The unit FET 35a has a source electrode 12a and a drain electrode 16a sandwiching a gate electrode 14a. The unit FET 35b has a source electrode 12b and a drain electrode 16b sandwiching a gate electrode 14b. The unit FET 35c has a source electrode 12c and a drain electrode 16c sandwiching a gate electrode 14c. In this way, the unit FETs 35a to 35c can be constructed.

[0073] As in the third embodiment and its first modification, each of the plurality of source electrodes 12a is connected to a corresponding source electrode 12b in the inactive region 13a. Each of the plurality of drain electrodes 16a is connected to a corresponding drain electrode 16b in the inactive region 13a. Each of the plurality of source electrodes 12b is connected to a corresponding source electrode 12c in the inactive region 13b. Each of the plurality of drain electrodes 16b is connected to a corresponding drain electrode 16c in the inactive region 13b. This allows the unit FETs 35a and 35b, and the unit FETs 35b and 35c to be electrically connected to each other.

[0074] In the second embodiment and its modified example, an example has been described in which 14 or 30 unit FETs 35a to 35c are arranged in the X direction, but it is sufficient that a plurality of unit FETs 35a to 35c are arranged in the X direction. An example has been described in which three or five rows of unit FETs 35a to 35c arranged in the X direction are arranged in the Y direction, but it is sufficient that three or more rows of unit FETs 35a to 35c are arranged in the Y direction.

[0075] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not by the above meaning, and is intended to include all modifications within the scope and meaning equivalent to the claims. [Explanation of symbols]

[0076] 10, 10a Board 10b Semiconductor layer 11a, 11b, 11c active area 12a, 12b, 12c Source electrodes 13, 13a, 13b inactive area 14a, 14b, 14c, 14ba, 14bb Gate electrodes 16a, 16b, 16c Drain electrodes 20 Beer Hall 22a, 22b Source wiring 24, 24a, 24b, 25a, 25b Gate wiring 27 Drain busbar 28 Gate bus bar 30 Insulating layer 50 central part 51, 52 End 51a, 52a middle part 55, 56, 57 areas 58 Arrow 100, 101, 104, 105, 106, 107, 108, 109, 110, 112, 114 Semiconductor device

Claims

1. A substrate; a plurality of first FETs arranged in a first direction on the substrate, each of the first FETs including a plurality of first gate electrodes; a plurality of second FETs arranged in the first direction, each of the second FETs having a plurality of second gate electrodes; a plurality of third FETs, each of which has a plurality of third gate electrodes, arranged in the first direction and sandwiching the plurality of second FETs between the plurality of first FETs in a second direction intersecting the first direction; Equipped with a second center distance between every two of the second gate electrodes at center portions of the first FETs, the second FETs, and the third FETs in the first direction is greater than a second end distance between every two of the second gate electrodes at first ends of the first FETs, the second FETs, and the third FETs close to first ends in the first direction; The semiconductor device, wherein the second end distance is smaller than a first end distance of every other one of the plurality of first gate electrodes at the first end.

2. 2 . The semiconductor device according to claim 1 , wherein the second center distance is greater than a first center distance of every other one of the plurality of first gate electrodes in the center portion.

3. 2 . The semiconductor device according to claim 1 , wherein the second end distance is smaller than every other third end distance of the plurality of third gate electrodes at the first end.

4. the second center distance is greater than a first center distance of every other one of the plurality of first gate electrodes in the center; 4. The semiconductor device according to claim 3, wherein the second center distance is greater than a third center distance of every other one of the plurality of third gate electrodes in the center portion.

5. 5. The semiconductor device according to claim 1, wherein a second intermediate distance of every second gate electrode in an intermediate portion between the central portion and the first end portion in the first direction is greater than the second end distance and smaller than the second central distance.

6. 2. The semiconductor device according to claim 1, wherein the second central distance is greater than a fifth end distance of every other of the second gate electrodes at a second end closer to a second end opposite the first ends of the first FETs, the second FETs and the third FETs than the central distance.

7. the second center distance is greater than every other fifth end distance of the plurality of second gate electrodes at second ends closer to second ends opposite the first ends of the plurality of first FETs, the plurality of second FETs, and the plurality of third FETs than the centers; the fifth end distance is smaller than every other fourth end distance of the plurality of first gate electrodes at the second end; 5 . The semiconductor device according to claim 4 , wherein the second end distance is smaller than every other sixth end distance of the plurality of third gate electrodes at the second end.

8. 5 . The semiconductor device according to claim 1 , wherein distances between the second closest first gate electrodes in the plurality of first FETs are equal to each other.

9. 5 . The semiconductor device according to claim 1 , wherein the number of the first FETs, the number of the second FETs, and the number of the third FETs are the same as one another.

10. the plurality of first FETs include a plurality of first source electrodes and a plurality of first drain electrodes, each of the plurality of first gate electrodes being sandwiched between one of the plurality of first source electrodes and one of the first drain electrodes in the first direction; the second FETs each include a plurality of second source electrodes and a plurality of second drain electrodes, each of the second gate electrodes being sandwiched between one of the second source electrodes and one of the second drain electrodes in the first direction; 5. The semiconductor device according to claim 1, wherein the plurality of third FETs include a plurality of third source electrodes and a plurality of third drain electrodes, and each of the plurality of third gate electrodes is sandwiched in the first direction between one of the plurality of third source electrodes and one of the plurality of third drain electrodes.

11. the substrate has a first active region, a second active region, and a third active region, a first inactive region provided between the first active region and the second active region, and a second inactive region provided between the second active region and the third active region; the first FETs are disposed in the first active region; the second FETs are disposed in the second active region; the third FETs are disposed in the third active region; each of the plurality of first source electrodes is connected to a corresponding second source electrode in the first inactive region; each of the plurality of first drain electrodes is connected to a corresponding second drain electrode in the first inactive region; each of the plurality of second source electrodes is connected to a corresponding third source electrode in the second inactive region; The semiconductor device according to claim 10 , wherein each of the plurality of second drain electrodes is connected to a corresponding third drain electrode in the second inactive region.

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