Input and digital output mechanisms for analog neural memory in deep learning artificial neural network

Abstract

To provide programming, verifying, and reading systems and methods for reading or verifying a value stored in a selected memory cell in a vector-by-matrix multiplication (VMM) array in an artificial neural network.SOLUTION: In a method for reading or verifying a value stored in a selected memory cell in a vector-by-matrix multiplication (VMM) array in an artificial neural network, an input comprises a set of input bits that result in a series of input signals applied to a terminal of the selected memory cell, further resulting in a series of output signals that are digitized, shifted based on the bit location of the corresponding input bit in the set of input bits, and added to yield an output indicating a value stored in the selected memory cell.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] (Priority Claim) This application claims priority to U.S. patent application Ser. No. 17 / 133,395, filed December 23, 2020, and entitled “Input and Digital Output Mechanisms for Analog Neural Memory in a Deep Learning Artificial Neural Network,” which is a continuation-in-part of U.S. patent application Ser. No. 16 / 919,697, filed July 2, 2020, and entitled “Precision Tuning for the Programming of Analog Neural Memory in a Deep Learning Artificial Neural Network,” which is a continuation-in-part of U.S. patent application Ser. No. 16 / 231,231, filed December 21, 2018, and entitled “Precision Tuning For the Programming Of Analog Neural Memory In A Deep Learning Artificial Neural Network,” which is a continuation-in-part of U.S. patent application Ser. This application claims priority to U.S. Provisional Patent Application No. 62 / 746,470, entitled "Network," all of which are incorporated herein by reference.

[0002] FIELD OF THEINVENTION Numerous embodiments of input and output mechanisms for reading or verifying non-volatile memory cells within a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. [Background technology]

[0003] Artificial neural networks mimic biological neural networks (the central nervous systems of animals, particularly the brain) and are used to estimate or approximate functions that may depend on multiple inputs and are generally unknown. Artificial neural networks generally contain layers of interconnected "neurons" that exchange messages between each other.

[0004] FIG. 1 shows an artificial neural network, where the circles represent layers of inputs or neurons. The connections (called synapses) are represented by arrows and have numerical weights that can be tuned based on experience. This allows the neural network to adapt to the inputs and learn. Typically, a neural network contains multiple layers of inputs. There are typically one or more hidden layers of neurons, and an output layer of neurons that provide the output of the neural network. At each level, the neurons make decisions individually or collectively based on the data they receive from the synapses.

[0005] One of the main challenges in the development of artificial neural networks for high-performance information processing is the lack of suitable hardware technology. In practice, practical neural networks rely on a very large number of synapses, which allows high connectivity between neurons, i.e., a very high degree of parallelization of computation. In principle, such complexity can be achieved by digital supercomputers or dedicated graphic processing unit clusters. However, in addition to high costs, these approaches also suffer from poor energy efficiency compared to biological networks, which mainly perform low-precision analog computations and therefore consume much less energy. CMOS analog circuits have been used for artificial neural networks, but most CMOS-implemented synapses are too bulky given the large number of neurons and synapses.

[0006] Applicant previously disclosed an artificial (analog) neural network utilizing one or more non-volatile memory arrays as synapses in U.S. Patent Application No. 15 / 594,439, which is incorporated by reference. The non-volatile memory array operates as an analog neuromorphic memory. The neural network device includes a first plurality of synapses configured to receive a first plurality of inputs and generate a first plurality of outputs therefrom, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, each of which includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending therebetween, a floating gate insulated and disposed above a first portion of the channel region, and a non-floating gate insulated and disposed above a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons in the floating gate. The plurality of memory cells is configured to multiply the first plurality of inputs by the stored weight values ​​to generate the first plurality of outputs.

[0007] Each non-volatile memory cell used in an analog neuromorphic memory system must hold a very specific and precise amount of charge, i.e., number of electrons, in its floating gate in response to erasure and programming. For example, each floating gate must hold one of N different values, where N is the number of different weights that can be exhibited by each cell. Examples of N include 16, 32, 64, 128, and 256.

[0008] Since the output of one VMM often needs to be applied to another VMM, it is desirable in a VMM system to be able to convert the output of a VMM into bits and apply the input bits to another VMM. The question then arises as to how best to implement the bit encoding mechanism of the VMM system.

[0009] What is needed is an improved programming, verify, and read system and method that utilizes input and output bits suitable for use with a VMM in an analog neuromorphic memory system. Summary of the Invention

[0010] Numerous embodiments are disclosed for reading or verifying values ​​stored in selected memory cells in a vector matrix multiplication (VMM) array in an artificial neural network. In one embodiment, the input includes a set of input bits resulting in a series of input signals applied to terminals of the selected memory cells, which are further digitized and shifted based on the bit locations of corresponding input bits in the set of input bits, resulting in a series of output signals that are summed to generate an output indicative of the value stored in the selected memory cells.

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[0054] [Brief description of the drawings]

[0055] [Figure 1] FIG. 1 illustrates an artificial neural network. [Diagram 2] 1 shows a prior art split-gate flash memory cell. [Diagram 3] 1 illustrates another prior art split-gate flash memory cell. [Figure 4] 1 illustrates another prior art split-gate flash memory cell. [Diagram 5] 1 illustrates another prior art split-gate flash memory cell. [Figure 6] FIG. 1 illustrates various levels of an exemplary artificial neural network that utilizes one or more non-volatile memory arrays. [Figure 7] FIG. 1 is a block diagram illustrating a vector matrix multiplication system. [Figure 8] FIG. 1 is a block diagram illustrating an example artificial neural network that utilizes one or more vector-matrix multiplication systems. [Figure 9] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 10] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 11] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 12] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 13] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 14] 1 shows a prior art long-short-term memory system. [Figure 15]An exemplary cell for use in a long- and short-term memory system is shown. [Figure 16] 16 illustrates an embodiment of the exemplary cell of FIG. 15. [Figure 17] 16 illustrates an alternative embodiment of the exemplary cell of FIG. [Figure 18] 1 shows a prior art gated recurrent unit system. [Figure 19] 1 shows an exemplary cell for use in a gated recurrent unit system. [Figure 20] 20 illustrates an embodiment of the exemplary cell of FIG. 19. [Figure 21] 20 illustrates an alternative embodiment of the exemplary cell of FIG. 19. [Figure 22A] 1 illustrates one embodiment of a method for programming a non-volatile memory cell. [Figure 22B] 1 illustrates another embodiment of a method for programming a non-volatile memory cell. [Figure 23] 1 illustrates one embodiment of a coarse programming method. [Figure 24] 3 illustrates exemplary pulses used in programming non-volatile memory cells. [Diagram 25] 3 illustrates exemplary pulses used in programming non-volatile memory cells. [Figure 26] 1 illustrates a calibration algorithm for programming non-volatile memory cells that adjusts programming parameters based on the tilt characteristics of the cell. [Figure 27] 27 shows the circuit used in the calibration algorithm of FIG. 26. [Figure 28] 1 illustrates a calibration algorithm for programming non-volatile memory cells. [Figure 29] 29 shows the circuit used in the calibration algorithm of FIG. 28. [Diagram 30] 4 illustrates an exemplary progression of voltages applied to the control gates of non-volatile memory cells during a programming operation. [Diagram 31] 4 illustrates an exemplary progression of voltages applied to the control gates of non-volatile memory cells during a programming operation. [Diagram 32] 1 illustrates a system for applying programming voltages during programming of non-volatile memory cells in a vector multiplication matrix system. [Diagram 33] 1 shows a charge adder circuit. [Diagram 34] 2 shows a current adder circuit. [Diagram 35] 1 shows a digital adder circuit. [Figure 36A] 1 illustrates one embodiment of an integrated analog-to-digital converter for neuron outputs. [Figure 36B] 36B shows a graph illustrating the voltage output over time of the integrating analog-to-digital converter of FIG. 36A. [Figure 36C] 13 shows another embodiment of an integrating analog-to-digital converter for neuron outputs. [Figure 36D] 36D shows a graph illustrating the voltage output over time of the integrating analog-to-digital converter of FIG. 36C. [Figure 36E] 13 shows another embodiment of an integrating analog-to-digital converter for neuron outputs. [Figure 36F] 13 shows another embodiment of an integrating analog-to-digital converter for neuron outputs. [Figure 37A] 1 shows a successive approximation analog-to-digital converter for neuron outputs. [Figure 37B] 1 shows a successive approximation analog-to-digital converter for neuron outputs. [Figure 38] 1 illustrates an embodiment of a sigma-delta analog-to-digital converter. [Figure 39] The output block is shown. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0056] The artificial neural network of the present invention utilizes a combination of CMOS technology and non-volatile memory arrays. Non-volatile Memory Cell

[0057] Digital non-volatile memories are well known. For example, U.S. Pat. No. 5,029,130 ​​("the '130 patent"), incorporated herein by reference, discloses an array of split-gate non-volatile memory cells, which are a type of flash memory cell. Such a memory cell 210 is shown in FIG. 2. Each memory cell 210 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 between the source region 14 and the drain region 16. A floating gate 20 is formed over and insulated from a first portion of the channel region 18 (and controls the conductivity of the first portion of the channel region 18) and over a portion of the source region 14. A word line terminal 22 (typically coupled to a word line) has a first portion disposed over and insulated from a second portion of the channel region 18 (and controls the conductivity of the second portion of the channel region 18) and a second portion extending upwardly above the floating gate 20. A floating gate 20 and a wordline terminal 22 are insulated from the substrate 12 by a gate oxide. A bitline 24 is coupled to the drain region 16.

[0058] The memory cell 210 is erased (electrons are removed from the floating gate) by applying a high positive voltage to the wordline terminal 22, which causes electrons in the floating gate 20 to pass via Fowler-Nordheim tunneling from the floating gate 20 to the wordline terminal 22 through the insulator between them.

[0059] The memory cell 210 is programmed (electrons are supplied to the floating gate) by applying a positive voltage to the word line terminal 22 and a positive voltage to the source region 14. An electronic current will flow from the source region 14 towards the drain region 16. The electrons accelerate and are heated when they reach the gap between the word line terminal 22 and the floating gate 20. Some of the heated electrons are injected into the floating gate 20 through the gate oxide due to electrostatic attraction from the floating gate 20.

[0060] The memory cell 210 is read by applying a positive read voltage to the drain region 16 and the word line terminal 22 (turning on the portion of the channel region 18 below the word line terminal). When the floating gate 20 is positively charged (i.e., erased with electrons), the portion of the channel region 18 below the floating gate 20 is also turned on and current flows through the channel region 18, which is sensed as the erased or "1" state. When the floating gate 20 is negatively charged (i.e., programmed with electrons), the portion of the channel region below the floating gate 20 is mostly or completely off and no (or very little) current flows through the channel region 18, which is sensed as the programmed or "0" state.

[0061] Table 1 shows typical voltage ranges that may be applied to the terminals of memory cell 110 to perform read, erase, and program operations. Table 1: Operation of the Flash Memory Cell 210 of FIG. [Table 1]

[0062] Other split-gate memory cell configurations are also known for other types of flash memory cells. For example, FIG. 3 shows a four-gate memory cell 310 including a source region 14, a drain region 16, a floating gate 20 above a first portion of a channel region 18, a select gate 22 (typically coupled to a word line, WL) above a second portion of the channel region 18, a control gate 28 above the floating gate 20, and an erase gate 30 above the source region 14. This configuration is described in U.S. Pat. No. 6,747,310, which is incorporated herein by reference for all purposes. Here, all gates, except for the floating gate 20, are non-floating gates, i.e., they are electrically connected or connectable to a voltage source. Programming is performed by heated electrons injecting themselves from the channel region 18 into the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0063] Table 2 shows typical voltage ranges that may be applied to the terminals of memory cell 310 to perform read, erase, and program operations. Table 2: Operation of the Flash Memory Cell 310 of FIG. [Table 2]

[0064] Figure 4 shows another type of flash memory cell, a three-gate memory cell 410. Memory cell 410 is identical to memory cell 310 of Figure 3, except that memory cell 410 does not have a separate control gate. Erase and read operations (where erasure occurs through the use of an erase gate) are similar to those of Figure 3, except that no control gate bias is applied. Programming operations are also performed without a control gate bias, and as a result, a higher voltage must be applied to the source line during a program operation to compensate for the lack of control gate bias.

[0065] Table 3 shows typical voltage ranges that may be applied to the terminals of memory cell 410 to perform read, erase, and program operations. Table 3: Operation of Flash Memory Cell 410 of FIG. [Table 3]

[0066] Figure 5 shows another type of flash memory cell, a stacked gate memory cell 510. Memory cell 510 is similar to memory cell 210 of Figure 2, except that the floating gate 20 extends over the entire channel region 18, and a control gate 22 (where it is coupled to a word line) extends over the floating gate 20, separated by an insulating layer (not shown). Erase, programming, and read operations operate in a similar manner as previously described for memory cell 210.

[0067] Table 4 shows typical voltage ranges that may be applied to the terminals of memory cell 510 and substrate 12 to perform read, erase, and program operations. Table 4: Operation of Flash Memory Cell 510 of FIG. [Table 4]

[0068] In order to utilize a memory array containing one of the non-volatile memory cell types in an artificial neural network as described above, two modifications are made: First, as explained further below, the lines are configured so that each memory cell can be individually programmed, erased, and read without adversely affecting the memory state of other memory cells in the array; Second, a continuous (analog) programming of the memory cells is provided.

[0069] Specifically, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be changed continuously from a fully erased state to a fully programmed state, independently and with minimal disturbance to other memory cells. In another embodiment, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be changed continuously from a fully programmed state to a fully erased state, and vice versa, independently and with minimal disturbance to other memory cells. This means that the cell storage is analog or can at a minimum store one of many discrete values ​​(such as 16 or 64 different values), which allows every cell in the memory array to be very precisely and individually tunable, making the memory array ideal for storage and fine tuning adjustments to the synaptic weights of neural networks. Neural network using non-volatile memory cell arrays

[0070] 6 conceptually illustrates a non-limiting example of a neural network utilizing the non-volatile memory array of the present embodiment. This example uses a non-volatile memory array neural network for a face recognition application, although other suitable applications can also be implemented using a non-volatile memory array-based neural network.

[0071] S0 is the input layer, which in this example is a 32x32 pixel RGB image with 5-bit precision (i.e., three 32x32 pixel arrays, one for each color R, G, and B, each pixel with 5-bit precision). Synapse CB1 going from input layer S0 to layer C1 scans the input image with overlapping filters (kernels) of 3x3 pixels, applying different sets of weights to some instances and shared weights to other instances, and shifts the filters by one pixel (or two or more pixels depending on the model). Specifically, the values ​​of the nine pixels in the 3x3 portion of the image (i.e., referred to as filters or kernels) are provided to synapse CB1, which multiplies these nine input values ​​by the appropriate weights, and after summing the outputs of the multiplications, a single output value is determined and given by the first synapse of CB1 to generate one pixel of the layer of feature map C1. The 3x3 filter is then shifted one pixel to the right in the input layer S0 (i.e., add a column of 3 pixels to the right and drop a column of 3 pixels on the left), so that the 9 pixel values ​​of this newly positioned filter are provided to synapse CB1, where they are multiplied by the same weights as above to determine a second single output value by the associated synapse. This process continues until the 3x3 filter scans the entire 32x32 pixel image of input layer S0 for all three colors and all bits (precision values). The process is then repeated using different sets of weights to generate different feature maps of C1, until all feature maps of layer C1 have been calculated.

[0072] In this example, in layer C1, there are 16 feature maps, each with 30x30 pixels. Each pixel is a new feature pixel extracted from the multiplication of the input with a kernel, and thus each feature map is a two-dimensional array, and thus in this example, layer C1 constitutes 16 layers of two-dimensional arrays (note that layers and arrays referred to herein are logical, not necessarily physical, relationships, i.e., arrays are not necessarily oriented in a physical two-dimensional array). Each of the 16 feature maps in layer C1 is generated by one of 16 different sets of synaptic weights applied to the filter scans. The C1 feature maps can all target different aspects of the same image feature, such as boundary identification. For example, a first map (generated using a first set of weights shared by all scans used to generate this first map) can identify circular edges, and a second map (generated using a second set of weights different from the first set of weights) can identify rectangular edges or the aspect ratio of a particular feature, etc.

[0073] Before going from layer C1 to layer S1, an activation function P1 (pooling) is applied that pools values ​​from non-overlapping, consecutive 2x2 regions in each feature map. The purpose of the pooling function is to average nearby positions (or a max function can be used), e.g., to reduce edge position dependency, and to reduce data size before going to the next stage. In layer S1, there are 16 15x15 feature maps (i.e., 16 different arrays of 15x15 pixels each). Synapse CB2 going from layer S1 to layer C2 scans the maps in S1 with a 4x4 filter with a filter shift of 1 pixel. In layer C2, there are 22 12x12 feature maps. Before going from layer C2 to layer S2, an activation function P2 (pooling) is applied that pools values ​​from non-overlapping, consecutive 2x2 regions in each feature map. In layer S2, there are 22 6x6 feature maps. At synapse CB3 going from layer S2 to layer C3, an activation function (pooling) is applied, where all neurons in layer C3 connect to all maps in layer S2 through respective synapses in CB3. There are 64 neurons in layer C3. Synapse CB4 going from layer C3 to output layer S3 fully connects C3 to S3, i.e. all neurons in layer C3 connect to all neurons in layer S3. The output at S3 contains 10 neurons, where the neuron with the highest output determines the class. This output can indicate, for example, the identification or classification of the content of the original image.

[0074] Each layer of the synapse is implemented using an array or a portion of an array of non-volatile memory cells.

[0075] FIG. 7 is a block diagram of an array that can be used for that purpose. A vector matrix multiplication (VMM) array 32 contains non-volatile memory cells and is utilized as a synapse between one layer and the next (such as CB1, CB2, CB3, and CB4 in FIG. 6). Specifically, the VMM array 32 includes an array of non-volatile memory cells 33, an erase gate and word line gate decoder 34, a control gate decoder 35, a bit line decoder 36, and a source line decoder 37, which decode the respective inputs to the non-volatile memory cell array 33. The inputs to the VMM array 32 can be from the erase gate and word line gate decoder 34 or from the control gate decoder 35. The source line decoder 37 in this example also decodes the output of the non-volatile memory cell array 33. Alternatively, the bit line decoder 36 can decode the output of the non-volatile memory cell array 33.

[0076] The non-volatile memory cell array 33 serves two purposes. First, the non-volatile memory cell array 33 stores the weights used by the VMM array 32. Second, the non-volatile memory cell array 33 effectively multiplies the inputs by the weights stored in the non-volatile memory cell array 33 and adds them for each output line (source line or bit line) to generate an output that becomes the input to the next layer or the input to the last layer. With the non-volatile memory cell array 33 performing the multiplication and addition functions, the need for separate multiplication and addition logic is eliminated and in-memory computation is also more power efficient.

[0077] The outputs of the non-volatile memory cell array 33 are fed to a differential summer (such as a summing op-amp or a summing current mirror) 38, which sums the outputs of the non-volatile memory cell array 33 to create a single value for the convolution. The differential summer 38 is arranged to perform a summation of the positive and negative weights.

[0078] The summed output value of the differential adder 38 is then fed to an activation function circuit 39 which rectifies the output. The activation function circuit 39 may provide a sigmoid, tanh, or ReLU function. The rectified output value of the activation function circuit 39 becomes an element of a feature map as the next layer (e.g., C1 in FIG. 6) and is then applied to the next synapse to generate the next feature map layer or the last layer. Thus, in this example, the non-volatile memory cell array 33 constitutes a number of synapses (which receive inputs from a previous layer of neurons or from an input layer such as an image database), and the summing op-amps 38 and the activation function circuit 39 constitute a number of neurons.

[0079] The inputs to the VMM array 32 of FIG. 7 (WLx, EGx, CGx, and optionally BLx and SLx) may be analog levels, binary levels, or digital bits (in which case a DAC is provided to convert the digital bits to the appropriate input analog levels), and the outputs may be analog levels, binary levels, or digital bits (in which case an output ADC is provided to convert the output analog levels to digital bits).

[0080] FIG. 8 is a block diagram illustrating the use of multiple layers of VMM array 32, labeled in the figure as VMM arrays 32a, 32b, 32c, 32d, and 32e. As shown in FIG. 8, an input (denoted Inputx) is converted from digital to analog by a digital-to-analog converter 31 and provided to input VMM array 32a. The converted analog input can be a voltage or a current. The first layer input D / A conversion can be done by using a function or a LUT (look-up table) that maps the input Inputx to the appropriate analog level of the matrix multiplier of input VMM array 32a. The input conversion can also be done by an analog to analog (A / A) converter to convert an external analog input to a mapped analog input to input VMM array 32a.

[0081] The output generated by input VMM array 32a is then provided as input to the next VMM array (hidden level 1) 32b, which in turn generates an output that is provided as input to input VMM array (hidden level 2) 32c, and so on. The various layers of the VMM array 32 function as layers of synapses and neurons of a convolutional neural network (CNN). Each of the VMM arrays 32a, 32b, 32c, 32d, and 32e can be a standalone physical non-volatile memory array, or the multiple VMM arrays can utilize different portions of the same physical non-volatile memory array, or the multiple VMM arrays can utilize overlapping portions of the same physical non-volatile memory array. 8 includes five layers (32a, 32b, 32c, 32d, 32e): one input layer (32a), two hidden layers (32b, 32c), and two fully connected layers (32d, 32e). Those skilled in the art will appreciate that this is merely an example and that the system may instead include more than two hidden layers and more than two fully connected layers. Vector Matrix Multiplication (VMM) Array

[0082] 9 shows a neuron VMM array 900 that is particularly suited for the memory cells 310 shown in FIG. 3 and is utilized as part of the synapses and neurons between the input layer and the next layer. The VMM array 900 includes a memory array 901 of non-volatile memory cells and a reference array 902 of non-volatile reference memory cells (located at the top of the array). Alternatively, a separate reference array can be located at the bottom.

[0083] In the VMM array 900, control gate lines such as control gate line 903 run vertically (so that the row-wise reference array 902 is orthogonal to control gate line 903) and erase gate lines such as erase gate line 904 run horizontally. Here, inputs to the VMM array 900 are provided on the control gate lines (CG0, CG1, CG2, CG3) and outputs of the VMM array 900 appear on the source lines (SL0, SL1). In one embodiment, only the even rows are used, and in another embodiment, only the odd rows are used. The current in each source line (SL0, SL1 respectively) performs a function of the sum of all the currents from the memory cells connected to that particular source line.

[0084] As described herein for neural networks, the non-volatile memory cells of VMM array 900, ie, the flash memory of VMM array 900, are preferably configured to operate in the sub-threshold region.

[0085] The non-volatile reference memory cells and non-volatile memory cells described herein are biased in weak inversion as follows: Ids=Io*e(Vg-Vth) / kVt=w*Io*e(Vg) / kVt Where w=e(-Vth) / kVt.

[0086] When using an IV-log converter that uses memory cells (such as reference or peripheral memory cells) or transistors to convert the input current to an input voltage: Vg=k*Vt*log[Ids / wp*Io] where wp is the w of the reference or periphery memory cell.

[0087] For a memory array used as a vector matrix multiplier VMM array, the output current is: Iout=wa*Io*e(Vg) / kVt, i.e. Iout=(wa / wp)*Iin=W*Iin W=e(Vthp-Vtha) / kVt where wa=w of each memory cell in the memory array.

[0088] The word line or control gate can be used as the input of the memory cell for an input voltage.

[0089] Alternatively, the flash memory cells of the VMM arrays described herein can be configured to operate in the linear region. Ids=beta*(Vgs-Vth)*Vds, beta=u*Cox*Wt / L W = α(Vgs-Vth)

[0090] The word line or control gate or bit line or source line can be used as the input of a memory cell operating in the linear region.

[0091] For an IV linear converter, memory cells (such as reference or peripheral memory cells) or transistors operating in the linear region can be used to linearly convert the input and output currents to input and output voltages.

[0092] Other embodiments for the VMM array 32 of Figure 7 are described in U.S. Patent Application Serial No. 15 / 826,345, which is incorporated herein by reference. As described in that application, the source lines or bit lines can be used as neuron outputs (current sum outputs).

[0093] FIG. 10 shows a neuron VMM array 1000 that is particularly suitable for the memory cells 210 shown in FIG. 2 and used as synapses between an input layer and the next layer. The VMM array 1000 includes a memory array 1003 of non-volatile memory cells, a reference array 1001 of a first non-volatile reference memory cell, and a reference array 1002 of a second non-volatile reference memory cell. The reference arrays 1001 and 1002 arranged in the columns of the array function to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs WL0, WL1, WL2, and WL3. In practice, the first and second non-volatile reference memory cells are diode-connected through a multiplexer 1014 (only some of which are shown) with current inputs flowing into them. The reference cells are tuned (e.g., programmed) to a target reference level. The target reference level is provided by a reference mini-array matrix (not shown).

[0094] The memory array 1003 serves two purposes. First, it stores the weights in each memory cell that are used by the VMM array 1000. Second, it effectively multiplies the inputs (i.e., the current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, which the reference arrays 1001 and 1002 convert to input voltages and provide to the word lines WL0, WL1, WL2, and WL3) by the weights stored in the memory array 1003, and then adds all the results (memory cell currents) to generate an output for each bit line (BL0-BLN), which is the input to the next layer or the input to the last layer. By performing the multiplication and addition functions, the memory array 1003 eliminates the need for separate multiplication and addition logic and is also power efficient. Here, voltage inputs are provided to word lines WL0, WL1, WL2, and WL3, and outputs appear on respective bit lines BL0-BLN during a read (inference) operation. The current in each of the bit lines BL0-BLN performs a function of the sum of the currents from all the non-volatile memory cells connected to that particular bit line.

[0095] Table 5 shows the operating voltages for the VMM array 1000. The columns in the table show the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit lines of the selected cells, the bit lines of the unselected cells, the source lines of the selected cells, and the source lines of the unselected cells. The rows show the operations of read, erase, and program. Table 5: Operation of VMM Array 1000 in Figure 10 [Table 5]

[0096] FIG. 11 shows a neuron VMM array 1100 that is particularly suited for the memory cells 210 shown in FIG. 2 and is utilized as part of the synapses and neurons between the input layer and the next layer. The VMM array 1100 includes a memory array 1103 of non-volatile memory cells, a reference array 1101 of first non-volatile reference memory cells, and a reference array 1102 of second non-volatile reference memory cells. The reference arrays 1101 and 1102 run in the row direction of the VMM array 1100. The VMM array is similar to the VMM 1000, except that the word lines run vertically in the VMM array 1100. Here, inputs are provided to the word lines (WLA0, WLB0, WLA1, WLB2, WLA2, WLB2, WLA3, WLB3) and outputs appear on the source lines (SL0, SL1) during a read operation. The current of each source line performs a function of the sum of all the currents from the memory cells connected to that particular source line.

[0097] Table 6 shows the operating voltages for the VMM array 1100. The columns in the table show the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit lines of the selected cells, the bit lines of the unselected cells, the source lines of the selected cells, and the source lines of the unselected cells. The rows show the operations of read, erase, and program. Table 6: Operation of VMM Array 1100 in FIG. 11 [Table 6]

[0098] 12 shows a neuron VMM array 1200, which is particularly suited for the memory cells 310 shown in FIG. 3 and is used as part of synapses and neurons between the input layer and the next layer. The VMM array 1200 includes a memory array 1203 of non-volatile memory cells, a reference array 1201 of a first non-volatile reference memory cell, and a reference array 1202 of a second non-volatile reference memory cell. The reference arrays 1201 and 1202 function to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs CG0, CG1, CG2, and CG3. In practice, the first and second non-volatile reference memory cells are diode-connected through a multiplexer 1212 (only a portion of which is shown), with the current inputs flowing through BLR0, BLR1, BLR2, and BLR3. The multiplexer 1212 includes a corresponding multiplexer 1205 and cascoding transistor 1204 to ensure a constant voltage on each bit line (e.g., BLR0) of the first and second non-volatile reference memory cells during a read operation. The reference cells are tuned to a target reference level.

[0099] The memory array 1203 serves two purposes. First, it stores the weights used by the VMM array 1200. Second, it effectively multiplies the inputs (current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, which the reference arrays 1201 and 1202 convert to input voltages and provide to the control gates (CG0, CG1, CG2, and CG3)) by the weights stored in the memory array, and then adds all the results (cell currents) to produce an output that appears on BL0-BLN and is the input to the next layer or the input to the last layer. Having the memory array perform the multiplication and addition functions eliminates the need for separate multiplication and addition logic and is also power efficient, where the inputs are provided to the control gate lines (CG0, CG1, CG2, and CG3) and the outputs appear on the bit lines (BL0-BLN) during read operations. The current in each bit line is a function of the sum of all the currents from the memory cells connected to that particular bit line.

[0100] The VMM array 1200 implements one-way tuning of the non-volatile memory cells in the memory array 1203. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. This can be done, for example, using the novel precision programming technique described below. If too much charge is added to the floating gate (such as an incorrect value being stored in the cell), the cell must be erased and the series of partial programming operations must be redone. As shown, two rows that share the same erase gate (such as EG0 or EG1) must be erased together (known as a page erase), and then each cell is partially programmed until the desired charge on the floating gate is reached.

[0101] Table 7 shows the operating voltages for VMM array 1200. The columns in the table show the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit line of the selected cell, the bit lines of the unselected cells, the control gate of the selected cell, the control gates of the unselected cells in the same sector as the selected cell, the control gates of the unselected cells in a different sector than the selected cell, the erase gate of the selected cell, the erase gates of the unselected cells, the source line of the selected cell, and the source lines of the unselected cells. The rows show the read, erase, and program operations. Table 7: Operation of VMM Array 1200 in FIG. 12 [Table 7]

[0102] FIG. 13 shows a neuron VMM array 1300, which is particularly suitable for the memory cells 310 shown in FIG. 3 and is used as part of synapses and neurons between the input layer and the next layer. The VMM array 1300 comprises a memory array 1303 of non-volatile memory cells, a reference array 1301 or a first non-volatile reference memory cell, and a reference array 1302 of a second non-volatile reference memory cell. The EG lines EGR0, EG0, EG1, and EGR1 run vertically, and the CG lines CG0, CG1, CG2, and CG3 and the SL lines WL0, WL1, WL2, and WL3 run horizontally. The VMM array 1300 is similar to the VMM array 1400, except that the VMM array 1300 implements bidirectional tuning, where each individual cell can be fully erased, partially programmed, and partially erased as needed to reach a desired amount of charge on the floating gate through the use of individual EG lines. As shown, reference arrays 1301 and 1302 convert input currents at terminals BLR0, BLR1, BLR2 and BLR3 into control gate voltages CG0, CG1, CG2 and CG3 (through the action of diode-connected reference cells via multiplexer 1314) which are applied to the memory cells in the row direction. The current outputs (neurons) are in bit lines BL0-BLN, each of which sums all the currents from the non-volatile memory cells connected to that particular bit line.

[0103] Table 8 shows the operating voltages for the VMM array 1300. The columns in the table show the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit line of the selected cell, the bit lines of the unselected cells, the control gate of the selected cell, the control gates of the unselected cells in the same sector as the selected cell, the control gates of the unselected cells in a different sector than the selected cell, the erase gate of the selected cell, the erase gates of the unselected cells, the source line of the selected cell, and the source lines of the unselected cells. The rows show the read, erase, and program operations. Table 8: Operation of VMM Array 1300 in FIG. 13 [Table 8] Long and short term memory

[0104] Prior art includes a concept known as long short-term memory (LSTM). LSTM units are often used within neural networks. LSTM allows a neural network to store information for any given period of time and use that information in subsequent operations. A traditional LSTM unit includes a cell, an input gate, an output gate, and a forget gate. The three gates regulate the flow of information into and out of the cell, and the period of time that information is stored within the LSTM. VMMs are particularly useful in LSTM units.

[0105] FIG. 14 illustrates an exemplary LSTM 1400. The LSTM 1400 in this example includes cells 1401, 1402, 1403, and 1404. Cell 1401 receives an input vector x0 and generates an output vector h0 and a cell state vector c0. Cell 1402 receives an input vector x1, an output vector (hidden state) h0 from cell 1401, and a cell state c0 from cell 1401, and generates an output vector h1 and a cell state vector c1. Cell 1403 receives an input vector x2, an output vector (hidden state) h1 from cell 1402, and a cell state c1 from cell 1402, and generates an output vector h2 and a cell state vector c2. Cell 1404 receives an input vector x3, an output vector (hidden state) h2 from cell 1403, and a cell state c2 from cell 1403, and generates an output vector h3. Additional cells can be used, the LSTM with four cells is just an example.

[0106] Figure 15 shows an example implementation of an LSTM cell 1500 that can be used for cells 1401, 1402, 1403, and 1404 in Figure 14. The LSTM cell 1500 receives an input vector x(t), a cell state vector c(t-1) from a previous cell, and an output vector h(t-1) from a previous cell, and produces a cell state vector c(t) and an output vector h(t).

[0107] LSTM cell 1500 includes sigmoid function devices 1501, 1502, and 1503, each of which applies a number between 0 and 1 to control the degree to which each component of the input vector contributes to the output vector. LSTM cell 1500 also includes tanh devices 1504 and 1505 for applying a hyperbolic tangent function to the input vector, multiplier devices 1506, 1507, and 1508 for multiplying two vectors, and adder device 1509 for adding the two vectors. The output vector h(t) can be provided to the next LSTM cell in the system or can be accessed for other purposes.

[0108] 16 shows an example of an implementation of LSTM cell 1500, LSTM cell 1600. For the convenience of the reader, the same numbering scheme from LSTM cell 1500 is used in LSTM cell 1600. Sigmoid function devices 1501, 1502, and 1503, and tanh device 1504 each include multiple VMM arrays 1601 and activation circuit blocks 1602. Thus, VMM arrays prove particularly useful in LSTM cells used in certain neural network systems.

[0109] An alternative example of LSTM cell 1600 (and another example of one implementation of LSTM cell 1500) is shown in Figure 17. In Figure 17, sigmoid function devices 1501, 1502 and 1503, and tanh device 1504 share the same physical hardware (VMM array 1701 and activation function block 1702) in a time-multiplexed manner. The LSTM cell 1700 also includes a multiplier device 1703 for multiplying two vectors, an adder device 1708 for adding two vectors, a tanh device 1505 (including an activation circuit block 1702), a register 1707 for storing a value i(t) when i(t) is output from the sigmoid function block 1702, a register 1704 for storing a value f(t)*c(t-1) when that value is output from the multiplier device 1703 via a multiplexer 1710, a register 1705 for storing a value i(t)*u(t) when that value is output from the multiplier device 1703 via the multiplexer 1710, a register 1706 for storing a value o(t)*ĉ(t) when that value is output from the multiplier device 1703 via the multiplexer 1710, and a multiplexer 1709.

[0110] Whereas LSTM cell 1600 includes multiple sets of VMM arrays 1601 and respective activation function blocks 1602, LSTM cell 1700 includes only one set of VMM arrays 1701 and activation function blocks 1702, which are used to represent multiple layers in embodiments of LSTM cell 1700. LSTM cell 1700 requires less space than LSTM cell 1600 because LSTM cell 1700 requires ¼ the space for the VMMs and activation function blocks compared to LSTM cell 1600.

[0111] It can be further appreciated that an LSTM unit typically includes multiple VMM arrays, each of which requires functionality provided by specific circuit blocks outside the VMM array, such as an adder and activation circuit block and a high voltage generation block. Providing a separate circuit block for each VMM array would require a significant amount of space within a semiconductor device and would be somewhat inefficient. Thus, the embodiments described below attempt to minimize the circuitry required outside the VMM array itself. Gated Recurrent Unit

[0112] Analog VMM implementations can be used for gated recurrent unit (GRU) systems. GRUs are a gating mechanism in recurrent neural networks. GRUs are similar to LSTMs, except that GRU cells generally contain fewer components than LSTM cells.

[0113] 18 illustrates an exemplary GRU 1800. The GRU 1800 in this example includes cells 1801, 1802, 1803, and 1804. Cell 1801 receives input vector x0 and generates output vector h0. Cell 1802 receives input vector x1 and output vector h0 from cell 1801 and generates output vector h1. Cell 1803 receives input vector x2 and output vector (hidden state) h1 from cell 1802 and generates output vector h2. Cell 1804 receives input vector x3 and output vector (hidden state) h2 from cell 1803 and generates output vector h3. Additional cells may be used, and a GRU with four cells is merely an example.

[0114] FIG. 19 illustrates an exemplary implementation of a GRU cell 1900 that can be used for cells 1801, 1802, 1803, and 1804 of FIG. 18. The GRU cell 1900 receives an input vector x(t) and an output vector h(t-1) from a preceding GRU cell, and generates an output vector h(t). The GRU cell 1900 includes sigmoid function devices 1901 and 1902, each of which applies a number between 0 and 1 to the output vector h(t-1) and components from the input vector x(t). The GRU cell 1900 also includes a tanh device 1903 for applying a hyperbolic tangent function to the input vector, a number of multiplier devices 1904, 1905, and 1906 for multiplying two vectors, an adder device 1907 for adding the two vectors, and a complement device 1908 for subtracting the input from 1 to generate an output.

[0115] Figure 20 shows GRU cell 2000, which is an example of one implementation of GRU cell 1900. For the convenience of the reader, the same numbering scheme from GRU cell 1900 is used in GRU cell 2000. As can be seen from Figure 20, sigmoid function devices 1901 and 1902 and tanh device 1903 each include multiple VMM arrays 2001 and activation function blocks 2002. It can therefore be seen that VMM arrays are particularly used in GRU cells used in certain neural network systems.

[0116] An alternative example of GRU cell 2000 (and another example of one implementation of GRU cell 1900) is shown in Figure 21. In Figure 21, GRU cell 2100 utilizes a VMM array 2101 and an activation function block 2102, which, when configured as a sigmoid function, applies a number between 0 and 1 to control how much each component of the input vector contributes to the output vector. In Figure 21, sigmoid function devices 1901 and 1902, and tanh device 1903 share the same physical hardware (VMM array 2101 and activation function block 2102) in a time-multiplexed manner. The GRU cell 2100 also comprises a multiplier device 2103 for multiplying the two vectors, an adder device 2105 for adding the two vectors, a complementation device 2109 for subtracting an input from one to generate an output, a multiplexer 2104, a register 2106 for holding the value h(t-1)*r(t) as it is output from the multiplier device 2103 via the multiplexer 2104, a register 2107 for holding the value h(t-1)*z(t) as it is output from the multiplier device 2103 via the multiplexer 2104, and a register 2108 for holding the value h^(t)*(1-z((t)) as it is output from the multiplier device 2103 via the multiplexer 2104.

[0117] Whereas GRU cell 2000 includes multiple sets of VMM array 2001 and activation function blocks 2002, GRU cell 2100 includes only one set of VMM array 2101 and activation function blocks 2102, which are used to represent multiple tiers in an embodiment of GRU cell 2100. GRU cell 2100 requires less space than GRU cell 2000 because GRU cell 2100 requires ⅓ of the space for the VMM and activation function blocks compared to GRU cell 2000.

[0118] It can be further appreciated that a GRU system typically includes multiple VMM arrays, each of which requires functionality provided by specific circuit blocks outside the VMM array, such as adder and activation circuit blocks and high voltage generation blocks. Providing separate circuit blocks for each VMM array would require a significant amount of space within a semiconductor device and would be somewhat inefficient. Thus, the embodiments described below attempt to minimize the circuitry required outside the VMM array itself.

[0119] The input to the VMM array can be analog levels, binary levels, or digital bits (in which case a DAC is required to convert the digital bits to the appropriate input analog levels), and the output can be analog levels, binary levels, or digital bits (in which case an output ADC is required to convert the output analog levels to digital bits).

[0120] For each memory cell in the VMM array, each weight w can be implemented by a single memory cell, or by a differential cell, or by two blended memory cells (average of two cells). In the case of differential cells, two memory cells are required to implement weight w as a differential weight (w=w+-w-). In the case of two blended memory cells, two memory cells are required to implement weight w as an average of two cells. Embodiments for precision programming of cells in a VMM

[0121] FIG. 22A illustrates a programming method 2200. Initially, the method begins (step 2201), typically in response to a program command received. Next, a mass program operation programs all cells to a "0" state (step 2202). Then, a soft erase operation erases all cells to an intermediate weak erase level (step 2203), such that each cell draws approximately 3-5 μA of current during a read operation. This is in contrast to a deeply erased level, where each cell draws approximately 20-30 μA of current during a read operation. Then, a hard program is performed (step 2204) on all unselected cells, adding electrons to the floating gates of the cells to a very deep programmed state, ensuring that those cells are truly "off", i.e., they draw a negligible amount of current during a read operation.

[0122] A coarse programming method is then performed on the selected cells (step 2205), followed by a fine programming method being performed on the selected cells (step 2206) to program the desired precise value into each selected cell.

[0123] FIG. 22B illustrates another programming method 2210 similar to programming method 2200. However, after the method begins (step 2201), instead of a program operation to program all cells to a "0" state as in step 2202 of FIG. 22A, an erase operation is used to erase all cells to a "1" state (step 2212). A soft program operation (step 2213) is then used to program all cells to an intermediate state (level) so that each cell draws approximately 3-5 μA of current during a read operation. This is followed by the coarse and fine programming methods as in FIG. 22A. A variation of the embodiment of FIG. 22B removes the soft programming method (step 2213) entirely.

[0124] FIG. 23 illustrates a first embodiment of the coarse programming method 2205, which is a search and execute method 2300. First, a lookup table lookup is performed to determine a coarse target current value (ICT) for a selected cell based on the value intended to be stored in the selected cell (step 2301). Let us assume that the selected cell can be programmed to store one of N possible values ​​(e.g., 128, 64, 32, etc.). Each of the N values ​​may correspond to a different desired current value (ID) to be drawn by the selected cell during a read operation. In one embodiment, the lookup table may contain M possible current values ​​to use as the coarse target current value ICT for the selected cell during the search and execute method 2300, where M is an integer less than N. For example, if N is 8, then M may be 4, meaning that there are eight possible values ​​that the selected cell may store, and one of the four coarse target current values ​​will be selected as the coarse target for the search and execute method 2300. That is, the search and execute method 2300 (which is again an embodiment of the coarse programming method 2205) is intended to quickly program the selected cell to a value (ICT) that is somewhat close to the desired value (ID), and then the fine programming method 2206 is intended to more precisely program the selected cell to be very close to the desired value (ID).

[0125] Examples of cell values, desired current values, and coarse target current values ​​are shown in Tables 9 and 10 for a simple example of N=8 and M=4. Table 9: Example of N desired current values ​​for N=8 [Table 9] Table 10: Example of M target current values ​​for M=4 [Table 10] The offset value ICTOFFSETx is used to prevent overshooting the desired current value during coarse adjustment.

[0126] Once the coarse target current value ICT is selected, the selected cell is programmed (step 2302) by applying a voltage v0 to an appropriate terminal of the selected cell based on the cell architecture type of the selected cell (e.g., memory cell 210, 310, 410, or 510). If the selected cell is of the type of memory cell 310 of FIG. 3, then a voltage v0 is applied to control gate terminal 28, where v0 can be 5-7 V depending on the coarse target current value ICT. The value of v0 can optionally be determined from a voltage lookup table that stores v0 in correspondence with the coarse target current value ICT.

[0127] The selected cell is then programmed by applying a voltage vi=vi-1+v increment, where i starts at 1 and increments each time this step is repeated, and v increment is a small voltage that causes programming to the granularity of the desired change (step 2303). Thus, a first time step 2303 is performed with i=1, and v1 is v0+v increment. A read operation is then performed on the selected cell, and a verify operation is performed in which the current drawn through the selected cell (I cell ) is measured (step 2304). If I cell is less than or equal to ICT (here a first threshold value), the search and execute method 2300 is complete and the fine programming method 2206 can begin. If I cell is not less than or equal to ICT, step 2303 is repeated and i is incremented.

[0128] Thus, at the point where the coarse programming method 2205 ends and the fine programming method 2206 begins, the voltage vi is the final voltage used to program the selected cell, and the selected cell will store a value associated with the coarse target current value ICT. The goal of the fine programming method 2206 is to program the selected cell to a point where, during a read operation, the selected cell will draw a current ID (plus or minus an acceptable amount of deviation, such as 50 pA or less), which is the desired current value associated with the value intended to be stored in the selected cell.

[0129] FIG. 24 shows examples of different voltage progressions that can be applied to the control gates of selected memory cells during the fine programming method 2206.

[0130] Under the first approach, increasing voltages are applied progressively to the control gate to further program the selected memory cell. The starting point is vi, which is the last voltage applied during the coarse programming method 2205. An increment vp1 is applied to v1, and then a voltage v1+vp1 is used to program the selected cell (indicated by the second pulse from the left in progression 2401). vp1 is an increment smaller than v increment (the voltage increment used during the coarse programming method 2205). After each programming voltage is applied, a verify step (similar to step 2304) is performed in which a determination is made whether Icell is less than or equal to IPT1 (the first fine target current value, here the second threshold value), where IPT1=ID+IPT1OFFSET, where IPT1OFFSET is an offset value added to prevent program overshoot. If the determination is not, another increment vp1 is added to the previously applied programming voltage, and the process is repeated. This part of the programming sequence stops when Icell is less than or equal to IPT1 Optionally, if IPT1 is equal to ID or approximately equal to ID with sufficient accuracy, the selected memory cell has been successfully programmed.

[0131] If IPT1 is not close enough to ID, further programming with smaller granularity can be done. Now, progression 2402 is used. The starting point of progression 2402 is the last voltage used for programming under progression 2401. An increment Vp2 (smaller than vp1) is added to that voltage and the combined voltage is applied to program the selected memory cell. After each programming voltage is applied, a verify step (similar to step 2304) is performed in which a determination is made whether Icell is less than or equal to IPT2 (a second precision target current value, here a third threshold value), where IPT2=ID+IPT2OFFSET, where IPT2OFFSET is an offset value added to prevent program overshoot. If the determination is not, another increment Vp2 is added to the previously applied programming voltage and the process is repeated. At the point where Icell is less than or equal to IPT2, this part of the programming sequence stops. Here, it is assumed that the target value has been reached with sufficient accuracy so that IPT2 is equal to ID or close enough to ID that programming can stop. Those skilled in the art will appreciate that additional progressions can be applied using smaller and smaller programming increments. For example, in Figure 25, three progressions (2501, 2502, and 2503) are applied instead of just two.

[0132] A second approach is shown in progression 2403. Here, instead of increasing the voltage applied during programming of a selected memory cell, the same voltage is applied for increasing periods of time duration. Instead of adding incremental voltages such as vp1 in progression 2401 and vp2 in progression 2403, an additional time increment tp1 is added to the programming pulse such that each applied pulse is tp1 longer than the previously applied pulse. After each programming pulse is applied, the same verify step as described above for progression 2401 is performed. Optionally, additional progressions can be applied in which the additional time increment added to the programming pulse is of shorter duration than the previous progression used. Although only one temporal progression is shown, one skilled in the art will understand that any number of different temporal progressions can be applied.

[0133] Further details are now provided for two further embodiments of the coarse programming method 2205.

[0134] 26 shows a second embodiment of the coarse programming method 2205, which is an adaptive calibration method 2600. The method starts (step 2601). The cell is programmed with a default starting value v0 (step 2602). Unlike the search and execute method 2300, v0 here is not obtained from a lookup table, but can instead be a relatively small initial value. The control gate voltage of the cell is measured at a first current value IR1 (e.g., 100 na) and a second current value IR2 (e.g., 10 na), and the subthreshold slope is determined (e.g., 360 mV / dec) based on those measurements and stored (step 2603).

[0135] A new desired voltage v is determined. The first time this step is performed, i=1, and v is determined based on the stored subthreshold slope value and the current target and offset values ​​using the subthreshold equation as follows: Vi=Vi-1+Vincrement, Vincrement is proportional to the slope Vg Vg=k*Vt*log[Ids / wa*Io] where wa is the w of the memory cell and Ids is the current target plus an offset value.

[0136] If the stored slope value is relatively steep, a relatively small current offset value can be used. If the stored slope value is relatively flat, a relatively high current offset value can be used. Thus, determining the slope information allows a current offset value to be selected that is customized for the particular cell in question. This ultimately makes the programming process shorter. As this step is repeated, i is incremented and vi=vi-1+vincrement. The cell is then programmed using vi. The v increment can be determined from a lookup table that stores the value of v increment in correspondence with the target current value.

[0137] A verify operation is then performed (step 2605) in which a read operation is performed on the selected cell and the current drawn through the selected cell (Icell) is measured. If Icell is less than or equal to ICT (here a coarse target threshold value) (ICT=ID+ICTOFFSET is set, where ICTOFFSET is an offset value added to prevent program overshoot), the adaptive calibration method 2600 is complete and the fine programming method 2206 can begin. If Icell is not less than or equal to ICT, steps 2604-2605 are repeated and i is incremented.

[0138] 27 illustrates an aspect of an adaptive calibration method 2600. During step 2603, a current source 2701 is used to apply exemplary current values ​​IR1 and IR2 to a selected cell (here memory cell 2702), and then the voltage at the control gate of memory cell 2702 (CGR1 for IR1 and CGR2 for IR2) is measured. The slope is (CGR2-CGR1) / dec.

[0139] 28 illustrates a second embodiment of the coarse programming method 2205, which is an absolute calibration method 2800. The method starts (step 2801). The cell is programmed with a default starting value V0 (step 2802). The control gate voltage of the cell (VCGRx) is measured and stored at a current value Itarget (step 2803). A new desired voltage v1 is determined based on the stored control gate voltage and the current target and offset values ​​Ioffset+Itarget (step 2804). For example, the new desired voltage v1 can be calculated as follows: v1=v0+(VCGBIAS-stored VCGR), where VCGBIAS=approximately 1.5V, which is the default read control gate voltage at the maximum target current, and the stored VCGR is the measured read control gate voltage of step 2803.

[0140] The cell is then programmed using vi. When i=1, the voltage v1 from step 2804 is used. When i>=2, the voltage vi=vi-1+Vincrement is used. Vincrement can be determined from a lookup table that stores values ​​of Vincrement corresponding to target current values. A verify operation is then performed in which a read operation is performed on the selected cell and the current drawn through the selected cell (Icell) is measured (step 2806). If Icell is less than or equal to ICT (here a threshold value), the absolute calibration method 2800 is complete and the fine programming method 2206 can begin. If Icell is not less than or equal to ICT, steps 2805-2806 are repeated and i is incremented.

[0141] Figure 29 shows a circuit 2900 for implementing step 2803 of the absolute calibration method 2800. A voltage source (not shown) generates a VCGR, which starts at an initial voltage and rises. Here, n + 1 different current sources 2901 (2901-0, 2901-1, 2901-2, ..., 2901-n) generate different currents IO0, IO1, IO2, ... IOn with increasing magnitudes. Each current source 2901 is connected to an inverter 2902 (2902-0, 2902-1, 2902-2, ..., 2902-n) and a memory cell 2903 (2903-0, 2903-1, 2903-2, ... 2903-n). As the VCGR rises, each memory cell 2903 draws an increasing amount of current, and the input voltage to each inverter 2902 decreases. Since IO0 < IO1 < IO2 <... < IOn, as the VCGR increases, first the output of inverter 2902-0 switches from low to high. Next, the output of inverter 2902-1 switches from low to high, then the output of inverter 2902-2 switches in the same way, and so on until the output of inverter 2902-n switches from low to high. Each inverter 2902 controls a switch 2904 (2904-0, 2904-1, 2904-2, ..., 2904-n), and as a result, when the output of the inverter 2902 is high, the switch 2904 is closed, which causes the VCGR to be sampled by the capacitor 2905 (2905-0, 2905-1, 2905-2, ..., 2905-n). Thus, the switches 2904 and the capacitors 2905 form a sample and hold circuit. The values of IO0, IO1, IO2, ..., IOn are used as possible values of Itarget, and each sampled voltage is used as the associated value VCGRx in the absolute calibration method 2800 of Figure 28. Graph 2906 shows the rising VCGR over time and the outputs of inverters 2902-0, 2902-1, and 2902-n that switch from low to high at various times.

[0142] FIG. 30 illustrates an exemplary progression 3000 for programming selected cells during the adaptive calibration method 2600 or the absolute calibration method 2800. In one embodiment, a voltage Vcgp is applied to the control gates of memory cells of a selected row. The number of selected memory cells in the selected row is, for example, 32 cells. Thus, up to 32 memory cells in the selected row can be programmed in parallel. Each memory cell is enabled to couple to a programming current Iprog by a bit line enable signal. When the bit line enable signal is inactive (meaning a positive voltage is applied to the selected bit line), the memory cell is inhibited (not programmed). As shown in FIG. 30, the bit line enable signal En_blx (x varies from 1 to n, n being the number of bit lines) is enabled at different times (and therefore for the selected memory on said bit line) at the Vcgp voltage level desired for that bit line. In another embodiment, the voltage applied to the control gates of the selected cells can be controlled using an enable signal on the bit line. Each bit line enable signal applies a desired voltage (such as vi in ​​FIG. 28) corresponding to that bit line as Vcgp. The bit line enable signal can also control the programming current flowing into the bit line. In this example, each subsequent control gate voltage Vcgp is higher than its previous voltage. Alternatively, each subsequent control gate voltage may be lower or higher than its previous voltage. Each subsequent increment of Vcgp may be either equal or unequal to its previous increment.

[0143] FIG. 31 illustrates an exemplary progression 3100 for programming a selected cell during adaptive calibration method 2600 or absolute calibration method 2800. In one embodiment, a bit line enable signal enables a selected bit line (meaning a selected memory cell in said bit line) to be programmed at a corresponding Vcgp voltage level. In another embodiment, the voltage applied to the incrementally increasing control gate of the selected cell can be controlled using the bit line enable signal. Each bit line enable signal applies a desired voltage (such as vi in ​​FIG. 28) corresponding to that bit line to the control gate voltage. In this example, each subsequent increment is equal to the previous increment.

[0144] FIG. 32 shows a system for implementing an input and output method for reading or verifying in a VMM array. An input function circuit 3201 receives digital bit values ​​and converts them into analog signals to be used to apply voltages to the control gates of selected cells in the array 3204, as determined via a control gate decoder 3202. At the same time, a word line decoder 3203 is also used to select the row in which the selected cell is located. An output neuron circuit block 3205 performs the output function of each column (neuron) of cells in the array 3204. The output circuit block 3205 can be implemented using an integrating analog-to-digital converter (ADC), a successive approximation (SAR) ADC, or a sigma-delta ADC.

[0145] In one embodiment, the digital value provided to the input function circuit 3201 includes, as an example, four bits (DIN3, DIN2, DIN1, and DIN0), with various bit values ​​corresponding to different numbers of input pulses applied to the control gate. The greater the number of pulses, the greater the output value (current) of the cell. Example bit and pulse values ​​are shown in Table 11. Table 11: Digital bit input and number of generated pulses [Table 11]

[0146] In the above example, there are up to 16 pulses for a 4-bit digital value to read the cell value. Each pulse is equal to one unit of cell value (current). For example, if Icell unit = 1nA, then for DIN[3~0]=0001, Icell = 1*1nA = 1nA, and for DIN[3~0]=1111, Icell = 15*1nA = 15nA.

[0147] In another embodiment, the digital bit input uses digital bit position summation to read out the cell value, as shown in Table 12. Here, only four pulses are needed to evaluate a four-bit digital value. For example, the first pulse is used to evaluate DIN0, the second pulse is used to evaluate DIN1, the third pulse is used to evaluate DIN2, and the fourth pulse is used to evaluate DIN3. The results from the four pulses are then summed according to the bit position. The digital bit summation formula realized is: Output = 2^0*DIN0 + 2^1*DIN1 + 2^2*DIN2 + 2^3*DIN3) * Icell unit.

[0148] For example, if Icell unit = 1nA, then for DIN[3~0] = 0001, Icell total = 0 + 0 + 0 + 1 * 1nA = 1nA, and for DIN[3~0] = 1111, Icell total = 8 * 1nA + 4 * 1nA + 2 * 1nA + 1 * 1nA = 15nA. Table 12: Digital bit input summation [Table 12]

[0149] FIG. 33 shows an example of a charge adder 3300 that can be used to sum the outputs of the VMM during a verify operation to obtain a single analog value representing the output, which can be optionally converted to a digital bit value. The charge adder 3300 includes a current source 3301 and a sample-and-hold circuit including a switch 3302 and a sample-and-hold (S / H) capacitor 3303. As shown in the example of a 4-bit digital value, there are four S / H circuits to hold values ​​from the four evaluation pulses, where these values ​​are summed at the end of the process. The S / H capacitors 3303 are selected with a ratio associated with the 2^n*DINn bit position of the S / H capacitor, e.g., C_DIN3=x8 Cu, C_DIN2=x4 Cu, C_DIN1=x2 Cu, DIN0=x1 Cu. The current sources 3301 are also multiplied with a ratio accordingly.

[0150] 34 shows a current adder 3400 that can be used to sum the output of the VMM during a verify operation. The current adder 3400 includes a current source 3401, a switch 3402, a switch 3403, and a switch 3404, and a switch 3405. As shown in the example of a 4-bit digital value, there is a current source circuit to hold the values ​​from the four evaluation pulses, and these values ​​are summed at the end of the process. The current sources are multiplied by a ratio based on the 2^n*DINn bit position, e.g., I_DIN3=x8 Icell units, _I_DIN2=x4 Icell units, I_DIN1=x2 Icell units, I_DIN0=x1 Icell units.

[0151] Figure 39 shows an output block 3900 (which is an embodiment of output block 3205 of Figure 32). Output block 3900 receives an output current from a VMM (such as array 3204 of Figure 32), here shown as ICELL 3901. Output block 3900 includes a D / A converter 3902, a shifter 3903, an adder 3904, and an output register 3905.

[0152] Here, the input to an input block of the VMM (such as input block 3201 in FIG. 32) is assumed to be din_n, where n is the number of bits, and there are a total of i bits from 0 to i-1. For example, if i=4, then the input would be 4 bits: din_3, din_2, din_1, and din_0. Each input bit din_n is applied to input block 3201 of the VMM 3204 one at a time.

[0153] Input block 3201 converts din_n into an input signal (using one of the embodiments described herein or other known techniques) that is applied to a terminal of a selected cell in array 3204. In one embodiment, the input signal is a pulse for an exemplary 4-bit input as shown in Table 13. Table 13. Example table of 4-bit inputs and pulses [Table 13]

[0154] In another embodiment, the input signal is an analog bias voltage for an exemplary 4-bit input as shown in Table 14A. Table 14A: Example table of 4-bit inputs and analog bias levels [Table 14A]

[0155] The 4-bit input DIN[3:0] for a particular row allows one analog level out of 16 levels (e.g., VCGIN0, ..., or VCGIN15) to be selected and applied to the row of the VMM array. This operation is performed on four data at the input at the same time. An alternative embodiment is to operate one data at a time at the input (input bit-wise operation), and the results for each data at the input are then added (summed) together in the analog domain (FIGS. 33, 34) or digital domain (FIGS. 35, 39). The addition of the results is adjusted for the binary weight for each input bit (shift and add in FIG. 39) if the analog bias level (VCGIN[15:0]) has the same voltage value for all data at the input bit. If the analog bias level (VCGIN[15:0]) has a voltage value equal to the binary value of the data input bit, no binary weight adjustment is required for the data of the input bit.

[0156] In another embodiment, the input signal to the input block of the array is the exemplary 4-bit input shown in Table 14B for an input bit-by-input operation (e.g., the operation is performed on the DIN0, then DIN1, then DIN2, then DIN3 inputs) with a constant analog bias voltage. Table 14B: Example table of single analog bias levels with 4-bit input and input bit-wise operations [Table 14B]

[0157] The binary weighted results for each input bit DIN are summed either in the analog domain (such as by using the current adder of FIG. 34) or in the digital domain (such as by using the embodiment of FIG. 35 or FIG. 39).

[0158] In another embodiment, the input signal to the input block of the array is an exemplary 4-bit input as shown in Table 14C for an input multi-bit per operation (e.g., DIN3 and DIN2 together, and DIN1 and DIN0 together) with two example analog bias levels. Table 14C: Example table of analog bias levels with 4-bit input and input multi-bit operations [Table 14C]

[0159] The multi-bitwise binary weighted results DIN[1:0] and DIN[3:2] are summed in the analog domain (such as the current adder in FIG. 34) or in the digital domain (FIGS. 35, 39).

[0160] In another embodiment, the input signal is a hybrid signal that includes an analog bias voltage component with a pulse component (analog bias supply modulated pulse width) added, as shown in Table 15 for an exemplary 4-bit input with an analog bias supply and a pulse. Table 15: Example table for 4-bit input and hybrid input of analog bias levels and pulses [Table 15]

[0161] In this hybrid system, the timing of the input pulses is reduced by half, as shown in Table 15. The input data is divided into multiple input data input sets, and each data input set is assigned to a specific bias level component. For example, for an 8-bit input DIN[7:0], the input data in the data input set DIN[3:0] receives a row power supply VCGIN1, and the input data in the data input set DIN[7:4] receives another row power supply VCGIN2 different from VCGIN1. In this exemplary embodiment of two binary input set division, the analog bias power supply VCGIN2 (for the second data input set DIN[7:4]) generates a cell current that is twice the cell current generated by the analog bias power supply VCGIN1 (for the first data input set DIN[3:0]), and the pulses for the second data input set DIN[7:4] are the same value as the pulses for the first data input set DIN[3:0]. For example, the ratio of VCGIN2 / VCGIN1 is twice for a cell operating in the linear region. In a variation of this embodiment, there are two divisions for the input data input set, each corresponding to a different analog bias voltage. For example, there could be four divisions, each with a different VCCGIN bias level, to reduce the width of the required input pulse by a factor of four.

[0162] 39, next, output block 3900 receives an output current ICELL from the VMM in response to an input din_n. A D / A converter 3902 converts ICELL into a digital form dout_n that represents the digital value of the output generated in response to din_n, where each dout_n is a set of one or more bits.

[0163] The shifter 3903, adder 3904, and register 3905 operate to apply a different weight to each output DOUT_n that is generated in response to each input bit DIN_n. In a simple example where n=4, the shifter 3902, adder 3904, and register 3905 perform the following functions: In response to (1) DIN_0, shifter 3903 receives DOUT_0 and does not shift it, producing the result of (1). (2) In response to DIN_1, shifter 3903 receives DOUT_1 and shifts it left one bit, and the adder adds the result to the result of (1) to produce the result of (2). In response to (3) DIN_2, shifter 3903 receives DOUT_2 and shifts it left two bits, and adder 3904 adds the result to the result of (2) to produce the result of (3). (4) In response to DIN_3, the shifter receives DOUT_3 and shifts it left by 3 bits, and the adder 3904 adds the result to the result of (3) to generate the result of (4), i.e., the final result.

[0164] If the DIN[n:0] inputs are combined with analog voltage levels to represent the binary weight of each data input, then only addition is required, no shifting for this hybrid input bit-wise operation. The output register 3905 outputs the result of (4) as DOUT.

[0165] FIG. 35 shows a digital adder 3500 that receives multiple digital values ​​and sums them together to generate an output DOUT that represents the sum of the inputs. The digital adder 3500 can be used during a verification operation. As shown with the example of a 4-bit digital value, there are digital output bits to hold the values ​​from the four evaluation pulses, which are summed at the end of the process. The digital output is digitally scaled based on the 2^n*DINn bit position, e.g., DOUT3=x8 DOUT0, _DOUT2=x4 DOUT1, I_DOUT1=x2 DOUT0, I_DOUT0=DOUT0.

[0166] FIG. 36A shows a dual slope integrating ADC 3600 applied to an output neuron to convert the cell current to a digital output bit. An integrator consisting of an integrating op-amp 3601 and an integrating capacitor 3602 integrates the cell current ICELL against a reference current IREF. As shown in FIG. 36B, for a fixed time t1, the cell current is integrated upwards (Vout rises) and then a reference current is applied such that it is integrated downwards (Vout falls) for a time t2. The current Icell is =t2 / t1*IREF. For example, for t1, with a digital bit resolution of 10 bits, 1024 cycles are used, and for t2 the number of cycles varies from 0 to 1024 cycles depending on the Icell value.

[0167] FIG. 36C shows a single slope integrating ADC 3660 applied to the output neuron to convert the cell current to a digital output bit. An integrator consisting of an integrating op-amp 3661 and an integrating capacitor 3662 integrates the cell current ICELL. As shown in FIG. 36D, during time t1, the cell current is integrated upwards (Vout rises until it reaches Vref2), and during time t2, another cell current is integrated upwards. The cell current I cell = Cint * Vref2 / t. A pulse counter is used to count the number of pulses (digital output bits) during the integration time t. For example, as shown, the digital output bits for t1 are less than the digital output bits for t2, which means that the cell current during t1 is greater than the cell current during t2 integration. An initial calibration is performed to calibrate the integrating capacitor value with a reference current and a fixed time, Cint = Tref * Iref / Vref2.

[0168] Figure 36E shows a dual slope integrating ADC 3680 applied to the output neuron to convert the cell current to a digital output bit. The dual slope integrating ADC 3680 does not utilize an integrating op-amp. The cell current or the reference current is directly integrated on the capacitor 3682. A pulse counter is used to count the pulses (digital output bits) during the integration time. The current Icell is = t2 / t1 * IREF.

[0169] Figure 36F shows a single slope integrating ADC 3690 applied to the output neuron to convert the cell current to a digital output bit. The single slope integrating ADC 3680 does not utilize an integrating op-amp. The cell current is directly integrated on a capacitor 3692. A pulse counter is used to count the pulses (digital output bits) during the integration time. The cell current I cell = C int * V ref2 / t.

[0170] FIG. 37A shows a SAR (successive approximation) ADC applied to the output neuron to convert the cell current to a digital output bit. The cell current can be dropped through a resistor and converted to a VCELL. Alternatively, the cell current can be converted to a VCELL by charging up a S / H capacitor. A binary search is used to calculate the bits starting from the MSB bit (most significant bit). A DAC 3702 is used to set the appropriate analog reference voltage to the comparator 3703 based on the digital bit from the SAR 3701. The output of the comparator 3703 is fed back to the SAR 3701 in order to select the next analog level. As shown in FIG. 37B, for an example of a 4-bit digital output bit, there are four evaluation periods, a first pulse to evaluate DOUT3 by setting the analog level to the middle, then a second pulse to evaluate DOUT2 by setting the analog level to the middle of the upper half or the middle of the lower half, and so on.

[0171] Figure 38 shows a sigma-delta ADC 3800 applied to an output neuron to convert the cell current to a digital output bit. An integrator consisting of an opamp 3801 and a capacitor 3805 integrates the sum of the current from the selected cell current and a reference current provided by a 1-bit current DAC 3804. A comparator 3802 compares the integrated output voltage against a reference voltage. A clocked DFF 3803 provides a digital output stream according to the output of the comparator 3802. The digital output stream typically goes to a digital filter before being output to a digital output bit.

[0172] It should be noted that, as used herein, both the terms "over" and "on" are inclusive of "directly" (with no intermediate material, element, or gap disposed between them) and "indirectly" (with an intermediate material, element, or gap disposed between them). Similarly, the term "adjacent" includes "directly adjacent" (with no intermediate material, element, or gap disposed between them) and "indirectly adjacent" (with an intermediate material, element, or gap disposed between them), "attached" includes "directly attached" (with no intermediate material, element, or gap disposed between them) and "indirectly attached" (with an intermediate material, element, or gap disposed between them), and "electrically coupled" includes "directly electrically coupled" (without an intermediate material or element disposed between them that electrically connects the elements together) and "indirectly electrically coupled" (with an intermediate material or element disposed between them that electrically connects the elements together). For example, forming an element "above the substrate" can include forming the element directly on the substrate, with no intermediate materials / elements between them, and forming the element indirectly on the substrate, with one or more intermediate materials / elements between them.

Claims

1. 1. A method of reading a selected non-volatile memory cell, the method comprising: sequentially providing a plurality of input bits to an input circuit; For each of the plurality of input bits, generating, by said input circuitry, an input signal in response to said input bits; applying the input signal to a terminal of the selected non-volatile memory cell; receiving an output generated by an output circuit in response to said input bits; converting said output to a digital output; shifting the digital output based on a bit location of the input bit within the plurality of input bits to generate a shifted result; and adding the shifted result for all of the plurality of input bits to generate a digital output.

2. 10. The method of claim 1, wherein the selected non-volatile memory cells are split-gate flash memory cells.

3. The method of claim 2 , wherein the terminal is a control gate terminal.

4. The method of claim 1 , wherein the selected non-volatile memory cell is part of a neural memory.

5. The method of claim 1 , wherein the input signal comprises a pulse.

6. The method of claim 1 , wherein the input signal comprises an analog bias signal.

7. The method of claim 1 , wherein the input signal comprises an analog bias signal and a pulse.

8. The method of claim 7 , wherein one of the plurality of input bits is encoded as the analog bias signal.

9. 1. A neuromorphic memory system, comprising: an array including a plurality of selected memory cells; an input block configured to apply, to each selected memory cell, a sequence of input signals to terminals of said selected memory cell in response to a sequence of input bits; an output block for generating an output of the selected memory cell, the output block comprising an analog-to-digital converter, a shifter, an adder, and a register for converting a current from the selected memory cell into a digital value; the shifter, adder, and register are configured to receive a series of digital values ​​in response to the series of input bits, shift each digital value in the series of digital values ​​based on a bit location of the input bit in the series of input bits, and add results of the shifting operations to generate an output indicative of a value stored in the selected memory cell.

10. 10. The method of claim 9, wherein the selected non-volatile memory cells are split-gate flash memory cells.

11. The method of claim 10 , wherein the terminal is a control gate terminal.

12. 10. The method of claim 9, wherein the selected non-volatile memory cell is part of a neural memory.

13. The method of claim 9 , wherein the input signal comprises a pulse.

14. The method of claim 9 , wherein the input signal comprises an analog bias signal.

15. The method of claim 9 , wherein the input signal comprises an analog bias signal and a pulse.

16. The method of claim 15 , wherein one of the plurality of input bits is encoded as the analog bias signal.

17. 1. A method of reading a selected non-volatile memory cell, the method comprising: sequentially providing a plurality of input bits to an input circuit; For each of the plurality of input bits, generating, by the input circuitry, an input signal in response to the input bits, the input signal including an analog bias level component and a pulse width component; applying the input signal to a terminal of the selected non-volatile memory cell; receiving an output generated by an output circuit in response to said input bits; and converting the output to a digital output.

18. shifting the digital output based on a bit location of the input bit within the plurality of input bits to generate a shifted result; 20. The method of claim 17, further comprising adding the shifted result for all of the plurality of input bits to generate a digital output.

19. The method of claim 17 , wherein the output is generated using a current summer.

20. The method of claim 17 , wherein the analog bias level components are binary weighted values.

21. The method of claim 17 , wherein the output value is generated based solely on the pulse width modulated input.

22. 20. The method of claim 17, wherein the selected non-volatile memory cell is part of a neural memory.

23. 1. A method of reading a selected non-volatile memory cell, the method comprising: sequentially providing a plurality of input bits to an input circuit; For each of the plurality of input bits, generating, by the input circuitry, an input signal in response to the multiple bits of the input bits, the input signal being an analog bias level; applying the input signal to a terminal of the selected non-volatile memory cell; and receiving, by an output circuit, an output generated in response to said input bits.

24. 24. The method of claim 23, further comprising converting the output to a digital output.

25. 25. The method of claim 24, further comprising adding the result for all of the plurality of input bits to generate a digital output.

26. shifting the digital output based on a bit location of the input bit within the plurality of input bits to generate a shifted result; 25. The method of claim 24, further comprising: adding the shifted result for all of the plurality of input bits to generate a digital output.

27. 26. The method of claim 25, wherein the output is generated using a current summer.

28. 24. The method of claim 23, wherein the analog bias level is a binary index value.

29. 24. The method of claim 23, wherein the analog bias level is such that the resulting cell output value is an output value that is generated based solely on the pulse width modulation input.

30. 24. The method of claim 23, wherein the selected non-volatile memory cell is part of a neural memory.

31. 1. A neuromorphic memory system, comprising: an array including selected memory cells; an input block configured to apply, for each selected memory cell, a sequence of input signals to terminals of said selected memory cell in response to a sequence of input bits; an output block for generating an output of the selected memory cell, the output block comprising an adder for adding outputs received from the array in response to the series of input bits, the neuromorphic memory system comprising:

32. 32. The method of claim 31, wherein the selected non-volatile memory cells are split-gate flash memory cells.

33. 33. The method of claim 32, wherein the terminal is a control gate terminal.

34. 32. The method of claim 31, wherein the selected non-volatile memory cell is part of a neural memory.

35. 32. The method of claim 31 , wherein the input signal comprises a pulse.

36. 32. The method of claim 31 , wherein the input signal comprises an analog bias signal.

37. 32. The method of claim 31 , wherein the input signal comprises an analog bias signal and a pulse.

38. 32. The method of claim 31 , wherein the adder comprises an output current adder.

39. 32. The method of claim 31 , wherein the adder comprises an output charge adder.

40. 32. The method of claim 31 , wherein the adder comprises a digital logic adder.

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