Comparator circuit, hybrid ad converter, and quantizer

Abstract

To suppress degradation in signal-to-quantization noise ratio (SQNR).SOLUTION: A comparator circuit includes: an adder that generates an output voltage by a plurality of capacitances; a comparator that performs a comparison operation using the output voltage generated by the adder; and an input voltage switching switch that switches an input voltage input to one capacitance among the plurality of capacitances. In the comparator, a reference voltage used for the comparison operation is determined according to the capacitance ratio of the plurality of capacitances, and the reference voltage used for the comparison operation is switched by switching the input voltage input to the one capacitance by the input voltage switching switch.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a comparator circuit, a hybrid type AD converter, and a quantizer. [Background technology]

[0002] The following Patent Document 1 discloses a cyclic A / D converter that includes an operation clock generating means that generates an operation clock based on an input master clock so that the operation cycle corresponding to each bit becomes smaller in sequence from the most significant bit to the least significant bit, and an A / D conversion means that repeats a comparison operation in sequence from the most significant bit to the least significant bit using the operation clock generated by the operation clock generating means. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2011-171974 A Summary of the Invention [Problem to be solved by the invention]

[0004] Meanwhile, a hybrid AD converter has been devised that can operate as both an incremental AD converter, which resets a ΔΣ AD converter every OSR (Over Sampling Rate), and a cyclic AD converter, which uses the residual of the incremental AD converter as its input.

[0005] However, when a quantizer with an adder function that has multiple differential pairs of comparators is used in a hybrid AD converter, an addition error is likely to occur due to mismatching of the differential pairs, which may result in a decrease in the signal-to-quantization noise ratio (SQNR).In addition, when a hybrid AD converter employs a configuration in which the input voltage of the quantizer is generated based on the resistance ratio of multiple resistors, an addition error is likely to occur due to mismatching of the resistors, which may result in a decrease in the signal-to-quantization noise ratio (SQNR). [Means for solving the problem]

[0006] A comparison circuit according to one embodiment includes an adder that generates an output voltage using a plurality of capacitances, a comparator that performs a comparison operation using the output voltage generated by the adder, and an input voltage selection switch that switches the input voltage input to one of the plurality of capacitances, and the comparator determines a reference voltage used in the comparison operation based on a capacitance ratio of the plurality of capacitances, and the input voltage selection switch switches the input voltage input to the one capacitance, thereby switching the reference voltage used in the comparison operation. Effect of the Invention

[0007] According to the comparison circuit of the embodiment, it is possible to suppress a decrease in the signal-to-quantization noise ratio (SQNR). [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a hybrid AD converter according to an embodiment; [Diagram 2] FIG. 2 is a diagram for explaining the operation of a hybrid AD converter according to an embodiment; [Diagram 3] FIG. 2 is a diagram for explaining the operation of a hybrid AD converter according to an embodiment; [Figure 4] FIG. 1 is a diagram showing a first example of a circuit configuration of a comparison circuit according to an embodiment; [Diagram 5] A timing chart showing the operation timing of each control signal in a hybrid AD converter according to an embodiment. [Figure 6] FIG. 2 is a diagram showing an example of a signal-to-quantization noise ratio (SQNR) in a comparison circuit according to an embodiment; [Figure 7] FIG. 2 is a diagram showing an example of a signal-to-quantization noise ratio (SQNR) in a comparison circuit according to an embodiment; [Figure 8] FIG. 1 is a diagram showing a second example of the circuit configuration of a comparison circuit according to an embodiment; [Figure 9] FIG. 1 is a diagram showing a circuit configuration of a comparison circuit according to an embodiment; [Figure 10] FIG. 1 is a diagram showing a modified example of the circuit configuration of a comparison circuit according to an embodiment; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment will be described with reference to the drawings.

[0010] (Configuration of hybrid type AD converter 100) Fig. 1 is a diagram showing an example of the configuration of a hybrid AD converter 100 according to an embodiment. The hybrid AD converter 100 shown in Fig. 1 can convert an analog signal (for example, an output signal of a current detection resistor, a sensor, etc.) into a digital signal.

[0011] As shown in FIG. 1, the hybrid AD converter 100 includes an input terminal 101, an output terminal 102, a switch 110A, a switch 110B, a line 115A, a line 115B, an adder 120, a delay integrator 130, an adder 140, a quantizer 150, a DA converter (Digital to Analog Converter) 160, a DEMUX (demultiplexer) 170, an integration unit 180A, a shift calculation unit 180B, a calculation unit 180C, and a control unit 190.

[0012] The input terminal 101 receives an analog signal U(V / V ref ) (for example, the output signal of a current detection resistor, a sensor, etc.) is input.

[0013] The output terminal 102 is connected to the output side of the calculation unit 180C. The output terminal 102 outputs the analog signal U(V / V ref ) is converted into a digital signal (total output D).

[0014] Switch 110A is provided between input terminal 101 and adder 120. Switch 110A is on / off controlled by control unit 190. Switch 110A is switched on in a first step, and switched off in a second step.

[0015] The switch 110B is provided on the line 115B. The switch 110B is on / off controlled by the control unit 190. The switch 110B is switched off in the first step, and is switched on in the second step.

[0016] The line 115A is a line that connects the input side of the switch 110A to the first input terminal IN1 of the adder 140, and is a line that connects the input side of the switch 110A to the first input terminal IN1 of the adder 140. ref ) is input to adder 140.

[0017] The line 115B is a feedback loop that connects the output side of the delay integrator 130 and one + input terminal of the adder 120. The line 115B is provided with a switch 110B.

[0018] The line 115C is a feedback loop that connects the output side of the quantizer 150 and the negative input terminal of the adder 120. A DA converter 160 is provided on the line 115C.

[0019] The adder 120 has two input terminals and one output terminal. One of the two input terminals is a + input terminal, and the other is a - input terminal. The + input terminal receives an input without inverting the sign, and the - input terminal receives an input with the sign inverted.

[0020] The switches 110A and 110B are connected to one + input terminal of the adder 120. The line 115C is connected to the - input terminal of the adder 120.

[0021] When switch 110A is on and switch 110B is off in the first step, adder 120 adds analog signal U input to switch 110A to an inverted output obtained by inverting the sign of the output of DA converter 160. That is, in the first step, adder 120 subtracts the output of DA converter 160 from analog signal U input to switch 110A.

[0022] Furthermore, when switch 110A is off and switch 110B is on in the second step, adder 120 adds the output of delay integrator 130 to an inverted output obtained by inverting the sign of the output of DA converter 160. That is, in the second step, adder 120 subtracts the output of DA converter 160 from the output of delay integrator 130.

[0023] The delay integrator 130 is provided between the adder 120 and the adder 140. The delay integrator 130 has an adder 131 and a holding unit 132. The holding unit 132 holds the output of the adder 131 one cycle before. The output terminal of the holding unit 132 is connected to one input terminal of the adder 131 by a feedback loop in the delay integrator 130 and a second input terminal IN2 of the adder 140. The other input terminal of the adder 131 is connected to the output terminal of the adder 120, and the output terminal is connected to the input terminal of the holding unit 132. The adder 131 adds the output of the holding unit 132 and the output of the adder 120 and outputs the sum to the holding unit 132. The holding unit 132 holds the output of the adder 131 at the end of each cycle in the first step and the second step. Therefore, in the next cycle, the holding unit 132 holds the output of the adder 131 one cycle before. Furthermore, the value held by the holding unit 132 is reset when the second step ends.

[0024] The adder 140 has three input terminals (a first input terminal IN1, a second input terminal IN2, and a third input terminal IN3). The first input terminal IN1 of the adder 140 is connected to the input side of the switch 110A, the second input terminal IN2 is connected to the output terminal of the holding unit 132 of the delay integrator 130, and the third input terminal IN3 is connected to the reference voltage V ref , and the output terminal is connected to the input terminal of the quantizer 150.

[0025] The quantizer 150 has an input terminal connected to the output terminal of the adder 140, and an output terminal connected to the input terminal of the DA converter 160 and the input terminal of the DEMUX 170. The quantizer 150 quantizes the analog signal input from the adder 140 and outputs a digital code. The quantizer 150 can perform quantization at three levels (1, 0, -1).

[0026] The adder 140 and the quantizer 150 constitute the comparison circuit 10. Specifically, the comparison circuits 10 have the same configuration (however, the input voltage V ref The comparison circuit 10 includes a first component section 10A and a second component section 10B (where the positive and negative signs of the first and second components are different), and each of the first component section 10A and the second component section 10B is provided with an adder 140 and a quantizer 150. Each of the first component section 10A and the second component section 10B functions as a two-level quantizer by itself. However, the comparison circuit 10 functions as a three-level quantizer by combining the two-level output signal output from the quantizer 150 of the first component section 10A and the two-level output signal output from the quantizer 150 of the second component section 10B and outputting the combined signal as a three-level (1, 0, -1) output signal.

[0027] The DA converter 160 is inserted in series into the line 115C, which is a feedback loop connecting the output side of the quantizer 150 and the negative terminal of the adder 120. The DA converter 160 converts the output (digital code) of the quantizer 150 into an analog code and outputs it. The DA converter 160 has three levels (+V ref (V), 0(V), -V ref(V)) can perform analog conversion.

[0028] The DEMUX 170 has an input terminal connected to the output terminal of the quantizer 150, and two output terminals connected to the integrator 180A and the shift calculator 180B, and connects between the input terminal and one of the two output terminals. This switching is performed by the controller 190. The input terminal of the DEMUX 170 is connected to the integrator 180A in the first step, and is connected to the shift calculator 180B in the second step.

[0029] In the first step, the integrator 180A integrates the output (digital code) of the quantizer 150 input via the DEMUX 170, and outputs the result to the calculator 180C.

[0030] In the second step, the shift operation unit 180B performs a shift operation on the output (digital code) of the quantizer 150 input via the DEMUX 170, and outputs the resultant output (second output) to the operation unit 180C.

[0031] The calculation section 180C adds the output (second output) of the shift calculation section 180B in the second step to the output (first output) of the integrating section 180A in the first step, and outputs a sum output D of the first and second outputs.

[0032] The control unit 190 is configured with a digital circuit (ASIC), and performs operations such as switching on and off the switches 110A and 110B, resetting the holding unit 132 of the delay integrator 130, and switching the DEMUX 170. The control unit 190 may be configured with a microcontroller (MCU).

[0033] (Operation of the hybrid type AD converter 100) 2 and 3 are diagrams for explaining the operation of the hybrid type AD converter 100 according to an embodiment.

[0034] 2, in the first step, the switch 110A is turned on and the switch 110B is turned off in the hybrid AD converter 100. As a result, in the first step, the hybrid AD converter 100 converts the analog signal U(V / V ref ) and the output of the delay integrator 130 (the output of the holding unit 132) are added by the adder 140, quantized into three levels by the quantizer 150, and fed back to the adder 120 by the DAC 160. By repeating such a cycle, in the first step, the hybrid type AD converter 100 operates as an incremental AD converter. The output of the quantizer 150 in each cycle in the first step is integrated by the integration unit 180A.

[0035] The number of cycles in which the repetitive operation is performed in the first step is K. In this case, the quantizer 150 outputs K digital codes, Q1[1], . . . , Q1[K]. Therefore, the output D1 of the integrator 180A is expressed by the following equation (1). K=2 M In the first step, an M+1-bit output D1 is obtained.

[0036]

number

[0037] 3, in the second step, the hybrid AD converter 100 turns off the switch 110A and turns on the switch 110B. As a result, in the second step, the hybrid AD converter 100 quantizes the value X held in the holding unit 132 of the delay integrator 130 in the Kth cycle of the first step in the quantizer 150 at three levels, and converts the digital code output from the quantizer 150 into an analog code at three levels in the DAC 160. By repeating such a cycle for N cycles, the hybrid AD converter 100 operates as a cyclic AD converter.

[0038] When the cyclic operation is performed for N cycles in the second step, the quantizer 150 outputs N digital codes up to Q2[1], . . . , Q2[N]. Therefore, the output D2 of the shift calculation unit 180B is expressed by the following equation (2). By performing the cyclic operation for N cycles, an output D2 of N+1 bits is obtained.

[0039]

number

[0040] As a result, the total output D outputted by the calculation section 180C is expressed by the following equation (3).

[0041]

number

[0042] (First Example of Circuit Configuration of Comparison Circuit 10) 4 is a diagram showing a first example of a circuit configuration of a comparison circuit 10 according to an embodiment. FIG. 4 shows an example in which the circuit configuration of the comparison circuit 10 is a single-ended configuration. As shown in FIG. 4, the comparison circuit 10 has a first component section 10A and a second component section 10B. The first component section 10A of the comparison circuit 10 includes a comparator 11 and an adder 20.

[0043] The second component 10B of the comparison circuit 10 has the same configuration as the first component 10A, that is, includes a comparator 11 and an adder 20. However, the first component 10A and the second component 10B have a different input voltage V ref The positive and negative signs are different.

[0044] The first component 10A has a first input terminal IN1 to V int is input, and the second input terminal IN2 is V in is input, and the negative reference voltage V is output from the third input terminal IN3. refn is entered.

[0045] The second component 10B is connected to the first input terminal IN1 through Vint is input, and the second input terminal IN2 is V in is input, and the positive reference voltage V is output from the third input terminal IN3. refp is entered.

[0046] The comparator 11 receives the output voltage V add The comparator 11 compares the output voltage V add is higher than the reference voltage input from the - input terminal, the comparator 11 outputs a high-level binary signal Q. Conversely, the comparator 11 outputs a high-level binary signal Q when the output voltage V add is lower than the reference voltage input from the - input terminal, a low-level binary signal Q is output.

[0047] The adder 20 has a first input terminal IN1, a second input terminal IN2, a third input terminal IN3, a switched capacitor circuit 21, a switched capacitor circuit 22, a switched capacitor circuit 23, an input voltage selector switch SW15, and a switch SW24.

[0048] The first input terminal IN1 is connected to the output voltage V int The second input terminal IN2 is connected to the input terminal 101 of the hybrid type AD converter 100, and the voltage V in The third input terminal IN3 is connected to a reference voltage V ref is entered.

[0049] The switched capacitor circuit 21 has a capacitance C a1 and capacity C a1 and a switch SW11 provided between the first input terminal IN1 and the first input terminal IN2. a1 and a switch SW21 provided between the input terminal and the ground potential.

[0050] The switched capacitor circuit 22 has a capacitance C b2 and capacity C b2 and a switch SW12 provided between the first input terminal IN1 and the second input terminal IN2, and a capacitance C b2 and a switch SW22 provided between the input terminal and the ground potential.

[0051] The switched capacitor circuit 23 has a capacitance C th and capacity C th and a switch SW13 provided between the third input terminal IN3 and a capacitance C th and a switch SW23 provided between the input terminal and the ground potential.

[0052] The adder 20 has a capacitance C a1 , capacity C b2 , and capacitance C th The charge stored in the add and generates the output voltage V add Output.

[0053] The input voltage changeover switch SW15 is connected to a first input terminal IN1 and a switched capacitor circuit 22 (a switch SW12 and a capacitance C b2 It is provided between the

[0054] The switch SW24 has a capacitance C a1 , capacity C b2 , and capacitance C th and the ground potential.

[0055] (Operation of the comparison circuit 10) FIG. 5 is a timing chart showing the operation timing of each control signal in the hybrid AD converter 100 according to an embodiment.

[0056] The comparison circuit 10 configured as above switches between a "standby mode" in which the comparator 11 does not perform a comparison operation and a "comparison mode" in which the comparator 11 performs a comparison operation, for each cycle. Specifically, the comparison circuit 10 switches to the "standby mode" when the control signal Φ1 is on and the control signal Φ2 is off. The comparison circuit 10 switches to the "comparison mode" when the control signal Φ1 is off and the control signal Φ2 is on.

[0057] In the comparison circuit 10, when the comparator 11 is in a "standby mode" in which the comparator 11 does not perform a comparison operation, the switches SW11 to SW13 are switched on by a control signal Φ1 and the switches SW21 to SW24 are switched off by a control signal Φ2, whereby the adder 20 calculates the output voltage V add can be generated and output.

[0058] In the comparison circuit 10, when the comparator 11 is in a comparison mode in which the comparator 11 performs a comparison operation, the switches SW11 to SW13 are switched off by a control signal Φ1, and the switches SW21 to SW24 are switched on by a control signal Φ2, so that the comparator 11 receives the output voltage V add A comparison operation is performed to compare the voltage Vcc with a reference voltage inputted from the - input terminal, and a binary signal Q indicating the comparison result is outputted.

[0059] As a result, the comparator circuit 10 detects the output voltage V add (an analog signal) can be quantized into a two-level digital signal, i.e., the comparator 11 functions as a two-level quantizer.

[0060] However, as shown in FIG. 5, in the first step in which the hybrid AD converter 100 operates as an incremental AD converter, the input voltage changeover switch SW15 is switched off by the control signal step2·Φ1, the switch SW12 is switched on every cycle by the control signal step1·Φ1, and the capacitance C b2 to the input voltage Vin is entered.

[0061] In the second step in which the hybrid AD converter 100 operates as a cyclic AD converter, the switch SW12 is switched off by the control signal step1·Φ1, and the input voltage changeover switch SW15 is switched on every cycle by the control signal step2·Φ1, thereby reducing the capacitance C b2 The output voltage V of the delay integrator 130 int is entered.

[0062] In addition, in the comparison circuit 10, the first component 10A receives a negative reference voltage V refn By inputting, the positive reference voltage V ref The comparator circuit 10 outputs a two-level (1, 0) binary signal Q based on the third input terminal IN3. refp When the negative reference voltage V ref Based on this, the negative polarity binary signal Q of two levels (1, 0) is output.

[0063] Therefore, the comparison circuit 10 can output the two-level (1, 0) positive binary signal Q output from the first component section 10A and the two-level (1, 0) negative binary signal Q output from the second component section 10B as a three-level digital signal. That is, the comparison circuit 10 functions as a three-level quantizer.

[0064] Specifically, in the first step in which the hybrid AD converter 100 operates as an incremental AD converter, the adder output V add [V] is calculated using the following formula (4).

[0065]

number

[0066] Here, C b2 =Ca1 When , the adder output V add [V] is calculated using the following formula (5).

[0067]

number

[0068] Therefore, the output signal Q0 of the comparator 11 is calculated by the following formula (6).

[0069]

number

[0070] That is, in the first step, the negative reference voltage V refn The reference voltage V of the comparator 11 of the first component 10A to which th1 is +(C th / C a1 )V ref The result is [V].

[0071] In the first step, the positive reference voltage V refp The reference voltage V of the comparator 11 of the second component 10B to which th1 is -(C th / C a1 )V ref The result is [V].

[0072] Therefore, the comparator circuit 10, having the first component section 10A and the second component section 10B, functions as a three-level quantizer in the first step.

[0073] In the second step in which the hybrid AD converter 100 operates as a cyclic AD converter, the adder output V add [V] is calculated by the following formula (7).

[0074]

number

[0075] At this time, the adder output V add [V] is calculated using the following formula (8).

[0076]

number

[0077] Therefore, the output signal Q0 of the comparator 11 is calculated by the following formula (9).

[0078]

number

[0079] That is, in the second step, the negative reference voltage V refn The reference voltage V of the comparator 11 of the first component 10A to which th2 is +(C th / (C b2 +C a1 ))V ref The result is [V].

[0080] In the second step, the positive reference voltage V refp The reference voltage V of the comparator 11 of the second component 10B to which th2 is -(C th / (C b2 +C a1 ))V ref The result is [V].

[0081] Therefore, by having the first component section 10A and the second component section 10B, the comparison circuit 10 also functions as a three-level quantizer in the second step.

[0082] (Effect of the comparison circuit 10) 6 and 7 are diagrams showing an example of the signal-to-quantization noise ratio (SQNR) in the comparison circuit 10 according to an embodiment.

[0083] The graph shown in FIG. 6 is a graph showing the reference voltage ±V of the comparator 11 in the first step in which the hybrid type AD converter 100 operates as an incremental AD converter. th1 [V / V ref ] and the signal-to-quantization-noise ratio (SQNR).

[0084] In the first step, the reference voltage of the comparator 11 is set to ±V th1 [V / V ref ], then the input full-scale range FSR=2V ref The signal-to-quantization noise ratio (SQNR) for ×c1 / b1 is calculated by the following formula (10).

[0085]

number

[0086] In the above formula (10), M1 indicates the number of clocks in the first step. Also, c1 indicates the feedback coefficient of the DAC. Also, the max(arg1, arg2) function is a function that selects the larger of arg1 and arg2. Also, during the first step, b1 is the input coefficient of the analog signal U to the integrator.

[0087] In the above formula (10), when M1=1024 and b1=1, the signal-to-quantization noise ratio (SQNR) is as shown in the graph of FIG. 6. th1 c1 / b1 / 2 [V / V ref It was found that setting [ ] gives the highest signal-to-quantization noise ratio (SQNR).

[0088] The graph shown in FIG. 7 is a graph showing the reference voltage ±V of the comparator 11 in the second step in which the hybrid type AD converter 100 operates as a cyclic AD converter. th2 [V / Vref ] and the signal-to-quantization-noise ratio (SQNR).

[0089] In the second step, the reference voltage of the comparator 11 is set to ±V th2 [V / V ref ], then the input full-scale range FSR=2V ref The signal-to-quantization noise ratio (SQNR) for ×c1 / b1 is calculated by the following formula (11).

[0090]

number

[0091] In the above formula (11), n2 indicates the number of clocks in the second step. Furthermore, c1 indicates the feedback coefficient of the DAC. Furthermore, the max(arg1, arg2) function is a function that selects the larger of arg1 and arg2. Furthermore, in the second step, b1 is the feedback coefficient of the delay integrator 130. That is, b1 is the input coefficient of the analog signal U in the first step, and is the feedback coefficient of the delay integrator 130 in the second step.

[0092] In the above formula (11), when n2=6 and b1=1, the signal-to-quantization noise ratio (SQNR) is as shown in the graph of FIG. 7, and the reference voltage V th2 c1 / b1 / 4[V / V ref It was found that setting [ ] gives the highest signal-to-quantization noise ratio (SQNR).

[0093] Here, in the first step, the reference voltage of the comparator 11 is ±V th1 [V / V ref ] is the value of c1 / b1 / 2[V / V ref ], C b2 =C a1 Then, C th / C a1 =c1 / b1 / 2 so that C th=c1 / b1 / 2×C a1 That is, C b2 :C a1 :C th =1:1:c1 / b1 / 2.

[0094] In the second step, the reference voltage ±V th2 [V / V ref ] is the value of c1 / b1 / 4[V / V ref ], (C th / (C b2 +C a1 ))=c1 / b1 / 4, so that C th =c1 / b1 / 4×(C b2 +C a1 ) can be used. That is, C b2 +C a1 :C th = 1:c1 / b1 / 4. As in the first step, C b2 =C a1 In this case, C b2 :C a1 :C th =1:1:c1 / b1 / 2.

[0095] That is, in both the first and second steps, to maximize the signal-to-quantization-noise ratio (SQNR), C b2 :C a1 :C th =1:1:c1 / b1 / 2. For example, when c1 / b1=1, C b2 :C a1 :C th = 2:2:1. Also, when c1 / b1=1 / 2, C b2 :C a1 :C th = 4:4:1. Also, when c1 / b1=1 / 4, C b2 :C a1 :C th =8:8:1 would be fine.

[0096] For this reason, the comparison circuit 10 according to the embodiment uses a plurality of capacitances C b2, C a1, C th The optimum reference voltage of the comparator 11 can be changed by simply switching the input voltage changeover switch SW15 without changing the capacitance value of the comparator 11.

[0097] Generally, capacitance ratio mismatch is smaller than resistance ratio mismatch, so the comparison circuit 10 according to one embodiment can reduce the additive error compared to a configuration in which the reference voltage of the comparator is varied depending on the resistance ratio of multiple resistors.

[0098] (Second Example of Circuit Configuration of Comparison Circuit 10) Fig. 8 is a diagram showing a second example of the circuit configuration of the comparison circuit 10 according to an embodiment of the present invention. Fig. 8 shows an example in which the comparison circuit 10 has a differential circuit configuration.

[0099] The comparator circuit 10 shown in FIG. ref By inputting, the positive reference voltage V th A first signal processing unit 10-1 outputs a two-level (1, 0) binary signal Q based on the ref When the negative reference voltage V th and a second signal processing unit 10-2 that outputs a two-level (1, 0) binarized signal Q based on the above.

[0100] Each of the first signal processing unit 10-1 and the second signal processing unit 10-2 includes an adder 20 and a comparator 11.

[0101] In the first signal processing unit 10-1 and the second signal processing unit 10-2, the adder 20 includes a first component unit 20A and a second component unit 20B. The first component unit 20A and the second component unit 20B each have a configuration similar to that of the adder 20 shown in FIG.

[0102] As a result, the first component 20A of the adder 20 generates a voltage to be input to the + input terminal of the comparator 11, and the second component 20B of the adder 20 generates a - input signal of the comparator 11.

[0103] The comparison circuit 10 shown in FIG. 8 uses a first signal processing unit 10-1 to calculate a positive reference voltage V th A binary signal Q1 of two levels (1, 0) based on the above can be output, and a negative reference voltage V th Based on this, it is possible to output a negative binary signal Q0 of two levels (1, 0).

[0104] Therefore, the comparison circuit 10 shown in Fig. 8 can output the two-level binary signal Q1 output from the first signal processing section 10-1 and the two-level binary signal Q0 output from the second signal processing section 10-2 as a three-level digital signal. That is, the comparison circuit 10 shown in Fig. 8 functions as a three-level quantizer.

[0105] According to the comparison circuit 10 shown in FIG. 8, it is possible to suppress a decrease in the signal-to-quantization noise ratio (SQNR) when quantizing a differential configuration.

[0106] (Circuit configuration of comparison circuit 200) 9 is a diagram showing a circuit configuration of a comparison circuit 200 according to an embodiment. The comparison circuit 200 shown in FIG. 9 outputs an output voltage V add The comparison circuit 200 compares the analog signals (analog signals) and outputs a binary signal Q (digital signal) indicating the comparison result. For example, the comparison circuit 200 can be used in a ΔΣ AD converter or the like. The comparison circuit 200 can also be used as the comparison circuit 10 included in the hybrid AD converter 100 according to one embodiment.

[0107] As shown in FIG. 9, the comparison circuit 200 includes a comparator 201, an adder 210, and a holding capacitance C hold , a shutoff switch SW14, and a reset switch SW25.

[0108] The comparator 201 receives the output voltage V add The comparator 201 compares the output voltage V add is higher than the reference voltage input from the - input terminal, the comparator 201 outputs a high-level binary signal Q. Conversely, the comparator 201 outputs an output voltage V add is lower than the reference voltage input from the - input terminal, it outputs a low-level binary signal Q. Note that, like the above-described comparator 11, the reference voltage of the comparator 201 is determined by the capacitance ratio of a plurality of capacitors.

[0109] The adder 210 has a first input terminal IN1, a second input terminal IN2, a third input terminal IN3, a switched capacitor circuit 211, a switched capacitor circuit 212, a switched capacitor circuit 213, and a switch SW24.

[0110] The first input terminal IN1 is connected to a voltage V int The second input terminal IN2 is connected to a voltage V in The third input terminal IN3 is connected to a voltage V ref is entered.

[0111] The switched capacitor circuit 211 has a capacitance C a1 and capacity C a1 and a switch SW11 provided between the first input terminal IN1 and a capacitance C a1 and a switch SW21 connected between the first input terminal IN1.

[0112] The switched capacitor circuit 212 has a capacitance C b2 and capacity C b2 and a switch SW12 provided between the first input terminal IN1 and the second input terminal IN2, and a capacitance C b2 and a switch SW22 connected between the first input terminal IN1 and the second input terminal IN2.

[0113] The switched capacitor circuit 213 has a capacitance C th and capacity C th and a switch SW13 provided between the third input terminal IN3 and a capacitance C th and a switch SW23 connected between the first input terminal IN1 and the third input terminal IN3.

[0114] The switch SW24 has a capacitance C a1 , capacity C b2 , and capacitance C th and the ground potential.

[0115] The adder 210 has a capacitance C a1 , capacity C b2 , and capacitance C th The charge stored in the add and generates the output voltage V add Output.

[0116] Hold capacity C hold One end of the hold capacitance C is connected to a connection path 202 between the adder 210 and the positive input terminal of the comparator 201, and the other end is connected to the ground potential. hold is the output voltage V output from the adder 210 add Hold.

[0117] The cut-off switch SW14 is provided on the connection path 202 between the adder 210 and the + input terminal of the comparator 201. When the cut-off switch SW14 is switched on, it connects the connection path 202. When the cut-off switch SW14 is switched off, it cuts off the connection path 202.

[0118] The reset switch SW25 has one end connected to the cutoff switch SW14 in the connection path 202 and the holding capacitance C hold The reset switch SW25 is connected between the holding capacitor C holdReset the potential of

[0119] (Operation of the comparison circuit 200) In the comparison circuit 200 configured as described above, when the comparator 201 is in a “standby mode” in which no comparison operation is performed, the switches SW11 to SW14 are turned on and the switches SW21 to SW25 are turned off, whereby the adder 210 calculates the output voltage V add and the output voltage V output from the adder 210 is generated and output. add , and the hold capacitance C hold The output voltage V output from the adder 210 is add [V] is calculated by the following formula (12).

[0120]

number

[0121] When the comparator 201 is in a comparison mode in which the comparator 201 performs a comparison operation, the comparator circuit 200 switches SW11 to SW14 off and switches SW21 to SW25 on, and the comparator 201 connects the hold capacitance C hold The output voltage V input via the + input terminal add A comparison operation is performed to compare the voltage Vcc with a reference voltage inputted from the - input terminal, and a binary signal Q indicating the comparison result is outputted.

[0122] As a result, the comparator circuit 200 outputs the output voltage V add (analog signal) can be quantized into a two-level (1, -1) digital signal. That is, the comparator 201 functions as a two-level quantizer.

[0123] The comparison circuit 200 may have a configuration including a first component 200A and a second component 200B having the same configuration as the comparison circuit 10 described above. In this case, the first component 200A of the comparison circuit 200 receives a negative reference voltage Vrefn from the third input terminal IN3, and outputs a two-level (1, 0) binary signal Q based on the positive reference voltage Vref. In this case, the second component 200B of the comparison circuit 200 receives a positive reference voltage Vrefp from the third input terminal IN3, and outputs a two-level (1, 0) negative binary signal Q based on the negative reference voltage Vref.

[0124] Therefore, in this case, the comparison circuit 200 can output the two-level (1, 0) positive binary signal Q output from the first component section 200A and the two-level (1, 0) negative binary signal Q output from the second component section 200B as a three-level digital signal. That is, the comparison circuit 200 can function as a three-level quantizer.

[0125] Here, in one embodiment of the comparison circuit 200, when the comparator 201 is in a “comparison mode” in which the comparator 201 performs a comparison operation, the cut-off switch SW14 is switched off, thereby cutting off the connection path 202 between the adder 210 and the + input terminal of the comparator 201.

[0126] This allows the comparison circuit 200 according to one embodiment to prevent the kickback noise of the comparator 201 from being transmitted to the adder 210 when the comparator 201 is in the "comparison mode."

[0127] In addition, in the comparison circuit 200 according to the embodiment, when the comparator 201 is in the “standby mode”, the holding capacitance C hold The output voltage V output from the adder 210 add Before charging, the reset switch SW25 is turned on to turn on the hold capacitor C hold Reset the potential of

[0128] As a result, the comparison circuit 200 according to the embodiment has a hold capacitance C hold Since the initial charge amount can be kept constant, the input voltage input from the adder 210 to the comparator 201 can be kept constant. Therefore, the comparison circuit 200 according to one embodiment can prevent the input voltage of the comparator 201 from deviating from the operating range of the comparator 201.

[0129] The adder 210 includes an input voltage changeover switch SW15. The input voltage changeover switch SW15 is connected between a first input terminal IN1 and a switched capacitor circuit 212 (a switch SW12 and a capacitance C b2 When the input voltage changeover switch SW15 is turned off, the adder 210 is connected to the capacitance C b2 The voltage V input from the second input terminal IN2 in When the input voltage selector switch SW15 is turned on, the capacitance C b2 The voltage V input from the first input terminal IN1 int For this reason, the comparison circuit 200 according to the embodiment has a plurality of capacitances C b2, C a1, C th The optimum reference voltage of the comparator 201 can be changed by simply switching the input voltage changeover switch SW15 without changing the capacitance value of the comparator 201.

[0130] (Modification of the circuit configuration of the comparison circuit 200) 10 is a diagram showing a modified example of the circuit configuration of the comparison circuit 200 according to an embodiment of the present invention. The comparison circuit 200-2 shown in FIG.

[0131] Similar to the comparison circuit 200, the comparison circuit 200-2 shown in FIG. 10 uses the output voltage V addThe comparison circuit 200-2 compares the analog signals (analog signals) and outputs a binary signal Q (digital signal) indicating the comparison result. For example, the comparison circuit 200-2 can be used in a ΔΣ AD converter or the like. The comparison circuit 200-2 can also be used as the comparison circuit 10 included in the hybrid AD converter 100 according to one embodiment.

[0132] As shown in FIG. 10, the comparison circuit 200-2 includes an adder 210-2 and a quantizer 220.

[0133] Similar to the adder 210, the adder 210-2 has a first input terminal IN1, a second input terminal IN2, a third input terminal IN3, a switched capacitor circuit 211, a switched capacitor circuit 212, a switched capacitor circuit 213, and a switch SW24.

[0134] However, the adder 210-2 differs from the adder 210 in the configuration of the switched capacitor circuit 213.

[0135] In the switched capacitor circuit 213 of the adder 210-2, the switch SW13 has a capacitance C a1 and capacity C b2 and the output terminal OUT.

[0136] In addition, in the switched capacitor circuit 213 of the adder 210-2, the capacitance C th One end of the switch SW13 is connected to the connection path 203 between the switch SW13 and the output terminal OUT, and the other end of the switch SW13 is connected to the ground potential.

[0137] In the switched capacitor circuit 213 of the adder 210-2, one end of the switch SW23 is connected between the switch SW13 in the connection path 203 and the output terminal OUT, and the other end is connected to the input terminal IN3.

[0138] The output terminal OUT of the switched capacitor circuit 213 of the adder 210-2 is connected to the + input terminal of the comparator 221 included in the quantizer 220.

[0139] In the adder 210-2, the switch SW24 has a capacitance C a1 and capacity C b2 and the switch SW13 included in the switched capacitor circuit 213.

[0140] The adder 210-2 has a capacity C a1 , capacity C b2 , and capacitance C th The charge stored in the add and generates the output voltage V add Output.

[0141] As described above, the comparison circuit 200-2 has the adder 210-2, and thus the holding capacitance C hold , the cutoff switch SW14, and the reset switch SW25 are not included.

[0142] Instead, the comparison circuit 200-2 has a capacitance C th functions as a "third capacitance", switch SW13 functions as a "shutoff switch", and switch SW23 functions as a "reset switch". a1 acts as the "first capacitance" and capacitance C b2 functions as a "second capacity."

[0143] The quantizer 220 includes a comparator 221 and a D flip-flop 222. The + input terminal (one of the input terminals) of the comparator 221 is connected to the output terminal OUT of the adder 210-2. The comparator 221 converts the output voltage V addThe comparator 221 compares the output voltage V add is higher than the reference voltage input from the - input terminal, the comparator 221 outputs a high-level binary signal Q. Conversely, when the output voltage Vadd input from the + input terminal is lower than the reference voltage input from the - input terminal, the comparator 221 outputs a low-level binary signal Q. Note that, like the comparator 11 described above, the reference voltage of the comparator 221 is determined by the capacitance ratio of a plurality of capacitances.

[0144] The output terminal of the comparator 221 is connected to the data input terminal of the D flip-flop 222. The D flip-flop 222 holds the input value of the data input terminal when the control signal Φ2 input from the clock input terminal is Lo, and updates the output according to the input value of the data input terminal when the control signal Φ2 input from the clock input terminal is Hi.

[0145] (Operation of the comparison circuit 200-2) In the comparison circuit 200-2 configured as described above, when the comparator 221 is in a "standby mode" in which the comparison operation is not performed, the switches SW11 to SW13 are switched on and the switches SW21 to SW24 are switched off, whereby the adder 210-2 outputs the output voltage V add and outputs the output voltage Vadd output from the adder 210-2 to the comparator 221.

[0146] At this time, the output voltage of adder 210-2 is calculated by the above formula (4).

[0147] In the comparison circuit 200-2, when the comparator 221 is in a "comparison mode" in which the comparator 221 performs a comparison operation, the switches SW11 to SW13 are switched off and the switches SW21 to SW24 are switched on, and the comparator 221 converts the output voltage Vadd with a reference voltage input from the - input terminal, and outputs a binary signal Q indicating the comparison result to the D flip-flop 222. Then, the D flip-flop 222 outputs the binary signal Q input from the data input terminal at the timing when the control signal Φ2 becomes Hi.

[0148] As a result, the quantizer 220 outputs the output voltage V add (analog signal) can be quantized into a two-level (1, -1) digital signal, i.e., the quantizer 220 functions as a two-level quantizer.

[0149] Here, in the comparison circuit 200-2 according to one modification, when the comparator 221 is in a “comparison mode” in which the comparator 221 performs a comparison operation, the switch SW13 (shutoff switch) included in the switched capacitor circuit 213 is switched off, thereby turning off the capacitance C a1 and capacity C b2 The connection path 203 between the output side of the output terminal OUT and the output terminal OUT is cut off.

[0150] As a result, in the comparison circuit 200-2 according to the one modified example, when the comparator 221 is in the “comparison mode”, the kickback noise of the comparator 221 is input to the capacitance C a1 and capacity C b2 This can be done so that it is not conveyed to others.

[0151] In addition, in the comparison circuit 200-2 according to the one modified example, when the comparator 221 is in a “comparison mode” in which the comparator 221 performs a comparison operation, the switch SW23 (reset switch) of the switched capacitor circuit 213 is switched on, thereby resetting the capacitance C th (third capacitance) with respect to reference voltage V ref can be applied as an initial voltage, i.e., capacitance C th The potential of the reference voltage V ref (initial voltage).

[0152] As a result, the comparison circuit 200-2 according to the modified example has a capacitance C th Since the amount of initial charge can be kept constant, the input voltage input from the adder 210-2 to the comparator 221 can be kept constant. Therefore, according to the comparison circuit 200-2 according to one modification, it is possible to prevent the input voltage of the comparator 221 from deviating from the operating range of the comparator 221.

[0153] The comparison circuit 200-2 may have a configuration including a first component 200A and a second component 200B having the same configuration as the comparison circuit 10 described above. In this case, the first component 200A of the comparison circuit 200-2 receives a negative reference voltage Vrefn from the third input terminal IN3, and can output a two-level (1, 0) binary signal Q based on the positive reference voltage Vref. In this case, the second component 200B of the comparison circuit 200-2 receives a positive reference voltage Vrefp from the third input terminal IN3, and can output a two-level (1, 0) negative binary signal Q based on the negative reference voltage Vref.

[0154] Therefore, in this case, the comparison circuit 200-2 can output the two-level (1, 0) positive binary signal Q output from the first component section 200A and the two-level (1, 0) negative binary signal Q output from the second component section 200B as a three-level digital signal. That is, the comparison circuit 200-2 can function as a three-level quantizer.

[0155] The comparison circuit 200-2 also includes an input voltage switch SW15. The input voltage switch SW15 is connected between a first input terminal IN1 and a switched capacitor circuit 212 (a switch SW12 and a capacitance C b2 When the input voltage changeover switch SW15 is switched off, the comparison circuit 200-2 is connected to the capacitance C b2 The voltage V input from the second input terminal IN2 in When the input voltage selector switch SW15 is turned on, the capacitance Cb2 The voltage V input from the first input terminal IN1 int For this reason, the comparison circuit 200-2, like the comparison circuit 10, has a plurality of capacitances C b2, C a1, C th The optimum reference voltage of the comparator 221 can be changed by simply switching the input voltage changeover switch SW15 without changing the capacitance value of the comparator 221.

[0156] Although one embodiment of the present invention has been described in detail above, the present invention is not limited to these embodiments, and various modifications and changes are possible within the scope of the gist of the present invention described in the claims. [Explanation of symbols]

[0157] 10 Comparison circuit 10A First Component 10B 2nd component 10-1 First signal processing section 10-2 Second signal processing section 11 Comparator 20 Adder IN1 First input terminal IN2 Second input terminal IN3 Third input terminal 21-23 Switched Capacitor Circuits 100 Hybrid AD converter 101 Input terminal 102 Output terminal 110A Switch 110B Switch 115A track 115B Railroad 120 Adder 130 Delay Integrator 140 Adder 150 Quantizer 160 DA Converter 170 DEMUX 180A integral section 180B Shift operation section 180C calculation section 190 Control section 200,200-2 comparison circuit 201 Comparator 202,203 Connection 210,210-2 Adder 211-213 Switched Capacitor Circuits 220 Quantizer 221 Comparator 222 D Flip-Flop OUT Output terminal C a1 ,C b2 ,C th capacity C hold Hold Capacity SW11-SW13, SW21-SW24 switches SW14 Isolation switch SW15 Input voltage selector switch SW25 Reset switch V add Output Voltage V in ,V int ,V ref Voltage Q Binarized signal Φ1,Φ2,step1·Φ1,step2·Φ1 Control signal

Claims

1. an adder that generates an output voltage by a plurality of capacitances; a comparator that performs a comparison operation using the output voltage generated by the adder; and an input voltage changeover switch that changes an input voltage input to one of the plurality of capacitances. Equipped with The comparator is a reference voltage used in the comparison operation is determined by a capacitance ratio of the plurality of capacitances; The input voltage to be input to the one capacitor is switched by the input voltage changeover switch, whereby the reference voltage used in the comparison operation is switched. A comparison circuit comprising:

2. a first component having the adder and the comparator, receiving a negative reference voltage and outputting a two-level binary signal based on the positive reference voltage; a second component having the adder and the comparator, receiving a positive reference voltage and outputting a two-level binary signal based on the negative reference voltage; 2. The comparison circuit according to claim 1, comprising:

3. A comparison circuit according to claim 2, In the first step, it operates as an incremental AD converter. In the second step, it operates as a cyclic AD converter. A hybrid AD converter comprising:

4. The comparator is The input voltage to be input to the one capacitor is switched by the input voltage changeover switch, so that in the first step, the reference voltage is switched to a first reference voltage, and in the second step, the reference voltage is switched to a second reference voltage.

4. The hybrid AD converter according to claim 3.

5. a first capacitance provided on a first path to which an analog signal is input; a second capacitance provided on a second path to which a reference voltage is input; a third capacitor provided on a third path through which an analog signal or an amplified quantization residual generated during an analog-to-digital conversion process is input to an integrator and a subtraction of the amplified quantization residual from the reference voltage is output; an adder that generates an output voltage according to a capacitance ratio between the first capacitance, the second capacitance, and the third capacitance; a comparator that performs a comparison operation using the output voltage generated by the adder; a switch provided on the first path and the third path; Equipped with The output voltage is changed by changing the switch.

1. A quantizer comprising:

6. a first component having the adder and the comparator, receiving the negative reference voltage and outputting a two-level binary signal based on a positive reference voltage; a second component having the adder and the comparator, receiving the positive reference voltage and outputting a two-level binary signal based on a negative reference voltage; The first component and the second component are configured in a differential manner to output a three-level quantized signal.

6. The quantizer of claim 5.

7. In a first step, the analog signal is input and the AD converter operates as an AD converter that performs delta-sigma modulation or incremental operation; In a second step, a hybrid AD converter operates as an AD converter that performs a cyclic operation of amplifying a quantization residual generated in the conversion process and subtracting the quantization residual from the reference voltage, The quantizer according to claim 5 or 6 outputs a quantized value obtained by quantizing the output of the delta-sigma modulation and the output of the cyclic operation. A hybrid AD converter comprising:

8. The quantizer switches the output voltage by switching the switch between the first step and the second step.

8. The hybrid AD converter according to claim 7.

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