Semiconductor device

Abstract

To provide a semiconductor device capable of improving breakdown tolerance.SOLUTION: A semiconductor substrate 40 is formed by sequentially stacking an n- type epitaxial layer 42 that serves as an n- type drift region 2, an n type epitaxial layer 43 that serves as an n type current diffusion region 23, and a p type epitaxial layer 44 that serves as a p type base region 3 on an n+ starting substrate 41 which serves as an n+ type drain region 1. The epitaxial layers 44, 43 have better crystallinity than the n- type epitaxial layer 42 and contain a trench gate structure. The semiconductor substrate 40 has a stacked structure in which all of the epitaxial layers 44, 43 are removed by etching in all regions other than an active effective region 31a. As a result, the semiconductor substrate 40 has a stacked structure in which all portions with longer minority carrier lifetimes than that of the n- type drift region 2 are removed, thereby making the minority carrier lifetime substantially uniform in all regions other than the active effective region 31a.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Conventional semiconductor devices include - n type drift region - A MOSFET (MOS field effect transistor with a MOS gate) is known in which each part of a MOS gate (insulated gate having a three-layer structure of Metal Oxide Semiconductor (metal-oxide film-semiconductor)) structure is formed in an n-type epitaxial layer and a p-type epitaxial layer stacked on a p-type epitaxial layer (see, for example, Patent Documents 1 to 3 listed below). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2020-120072 A [Patent Document 2] Patent No. 4640439 [Patent Document 3] Patent No. 6848382 Summary of the Invention [Problem to be solved by the invention]

[0004] However, the n-type and p-type epitaxial layers in which the various parts of the MOS gate structure are formed are - Compared to the n-type drift region, the crystallinity is good, so the carrier lifetime is long. - This region, which has a longer carrier lifetime than the type drift region, is locally destroyed when the MOSFET is switched, resulting in a decrease in the overall breakdown resistance of the MOSFET.

[0005] SUMMARY OF THE PRESENT EMBODIMENT In order to solve the above-mentioned problems associated with the conventional techniques, an object of the present invention is to provide a semiconductor device capable of improving the breakdown voltage. [Means for solving the problem]

[0006] In order to solve the above problems and achieve the object of the present invention, the semiconductor device according to the present invention has the following features. A semiconductor substrate is provided with an active region, a termination region surrounding the periphery of the active region, and a boundary region between the active region and the termination region. A first semiconductor region of a first conductivity type is provided inside the semiconductor substrate from the active region to the termination region. A second semiconductor region of a second conductivity type is provided between a first main surface of the semiconductor substrate and the first semiconductor region. An element structure including a pn junction between the second semiconductor region and the first semiconductor region is provided in the active region. A second conductivity type peripheral region is provided between the first main surface and the first semiconductor region in the boundary region. A first electrode is provided on the first main surface and is electrically connected to the element structure and the second conductivity type peripheral region. A second electrode is provided on the second main surface of the semiconductor substrate.

[0007] The semiconductor substrate has a laminated structure of a first epitaxial layer of a first conductivity type, in which the second conductive type peripheral region is provided in a surface region on the first main surface side, and the remaining portion except the second conductive type peripheral region is the first semiconductor region, and a second epitaxial layer in which the element structure is formed. The second epitaxial layer is provided only in the active region, and forms the first main surface in the active region. The first epitaxial layer forms the first main surface in the entire region other than the active region. In other words, the semiconductor substrate has a structure in which all parts in the entire region other than the active region that have a longer minority carrier lifetime than the first semiconductor region are removed. Or, the semiconductor substrate includes an epitaxial layer, and has a structure in which all parts of the epitaxial layer with relatively good crystallinity are removed in the entire region other than the active region.

[0008] According to the above-mentioned invention, during reverse recovery of the diode formed by the pn junction between the second semiconductor region and the first semiconductor region, the period until the reverse recovery current (hole current) is cut off can be made substantially uniform in the entire region other than the active region, which makes it possible to suppress local concentration of the hole current in the entire region other than the active region. Effect of the Invention

[0009] The semiconductor device according to the present invention has an effect of improving the breakdown voltage. [Brief description of the drawings]

[0010] [Figure 1] 1 is a plan view showing a layout of a semiconductor device according to an embodiment when viewed from the front surface side of a semiconductor substrate; [Diagram 2] 2 is a cross-sectional view showing a cross-sectional structure taken along line AA' in FIG. [Diagram 3] 2 is a cross-sectional view showing another example of the cross-sectional structure taken along line AA' in FIG. 1. [Figure 4] 2 is a cross-sectional view showing a cross-sectional structure taken along line BB' in FIG. [Diagram 5] 2 is a cross-sectional view showing a cross-sectional structure taken along line CC' in FIG. [Figure 6] 1 is a plan view showing a layout of a semiconductor device according to a reference example as viewed from the front surface side of a semiconductor substrate; [Figure 7] 7 is a cross-sectional view showing a cross-sectional structure taken along line AA-AA' in FIG. 6. [Figure 8] 7 is a cross-sectional view showing a cross-sectional structure taken along line BB-BB' in FIG. 6. [Figure 9] 7 is a cross-sectional view showing a cross-sectional structure taken along line CC-CC' in FIG. 6. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Preferred embodiments of the semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, in layers and regions prefixed with n or p, electrons or holes are the majority carriers, respectively. In addition, + and - appended to n or p respectively mean that the impurity concentration is higher and lower than that of layers and regions not prefixed with them. In the following description of the embodiments and the accompanying drawings, the same reference numerals are assigned to similar configurations, and duplicated explanations will be omitted.

[0012] (Reference example) The problem of the semiconductor device of the reference example will be described. Fig. 6 is a plan view showing the layout of the semiconductor device of the reference example seen from the front surface side of the semiconductor substrate. Figs. 7 to 9 are cross-sectional views showing the cross-sectional structures along the cutting lines AA-AA', BB-BB', and CC-CC' in Fig. 6, respectively. The semiconductor device 110 of the reference example shown in Figs. 6 to 9 is a vertical MOSFET with a trench gate structure that includes a metal wiring layer in a boundary region 132 between an active region 131 and an edge termination region 133 of a semiconductor substrate (semiconductor chip) 140 using silicon carbide (SiC) as a semiconductor material, and includes a predetermined breakdown voltage structure 160 in the edge termination region 133.

[0013] Provided on the front surface of the semiconductor substrate 140 are electrode pads such as a source pad (source electrode 111) and a gate pad 112, metal wiring layers such as a gate runner 113, a gate ring 115 and a source ring 116, a gate resistor 114 made of polysilicon (poly-Si) and gate polysilicon wiring layers 172, 174 and 176. The source electrode 111 is provided in an effective region (hereinafter referred to as an active effective region) 131a of the active region 131, and covers substantially the entire surface of the active effective region 131a.

[0014] The gate pad 112 and the gate runner 113 and the gate pad 112 and the gate runner 113 directly below them (n +Gate polysilicon wiring layers 174, 176 (on the side of the source drain region 101) and the gate resistor 114 are provided in an ineffective region (hereinafter referred to as an active ineffective region) 131b of the active region 131. The gate ring 115, the source ring 116, and the gate polysilicon wiring layer 172 directly below the gate ring 115 are provided in the boundary region 132. The gate electrodes 108 of all the cells of the MOSFET are connected to the gate polysilicon wiring layers 172, 176.

[0015] The gate pad 112, the gate runner 113 and the gate ring 115 are electrically connected to gate polysilicon wiring layers 174, 176 and 172 via barrier metals 175, 177 and 173, respectively. The gate polysilicon wiring layer 174 directly below the gate pad 112 is connected to one end of the gate resistor 114. The gate polysilicon wiring layer 176 directly below the gate runner 113 is connected to the other end of the gate resistor 114 and is electrically connected to the gate pad 112 via the gate resistor 114. The gate resistor 114 is formed by ion-implanting n-type impurities into polysilicon, for example.

[0016] The gate ring 115 surrounds the active region 131 in a partially open, generally rectangular shape. The gate polysilicon wiring layer 172 directly below the gate ring 115 surrounds the active region 131 in a partially open, generally rectangular shape or a closed, generally rectangular shape, similar to the gate ring 115. The source ring 116 is disposed outside (toward the chip end) the gate ring 115, and surrounds the active region 131 in a generally rectangular shape. The source ring 116 is connected to the source electrode 111 at a partially open portion of the gate ring 115, and is fixed to the potential of the source electrode 111.

[0017] The active region 131 has a substantially rectangular planar shape and is provided at substantially the center (chip center) of the semiconductor substrate 140. The active region 131 is a portion extending from the inner peripheral end (end toward the chip center) of the gate polysilicon wiring layer 172 directly below the gate ring 115 to the inside (chip center side). The active effective region 131a is a region that functions as a MOSFET, and in which MOSFET cells (functional units of an element) are arranged. The active ineffective region 131b is a region excluding the active effective region 131a, and is a region that does not function as a MOSFET.

[0018] Boundary region 132 is a portion extending from the inner periphery end of gate polysilicon wiring layer 172 outward to a step 145 (the boundary between first surface 140a and third surface 140c) described later, adjacent to active region 131 and surrounding the periphery of active region 131. Edge termination region 133 is a region between boundary region 132 and an end (chip end) of semiconductor substrate 140, adjacent to boundary region 132 and surrounding the periphery of boundary region 132. The active region 131 and boundary region 132 are isolated from the edge termination region 133 by a third surface 140c described later on the front surface of semiconductor substrate 140.

[0019] The semiconductor substrate 140 is a n-type semiconductor substrate using SiC as a semiconductor material. + On the front surface of the starting substrate 141, - The n-type drift region 102 - The n-type epitaxial layer 142, the n-type epitaxial layer 143 which becomes the n-type current diffusion region 123, and the p-type epitaxial layer 144 which becomes the p-type base region 103 are laminated in this order. + The starting substrate 141 is n + The semiconductor substrate 140 has a main surface on the p-type epitaxial layer 144 side as a front surface, and an n-type + The main surface on the mold starting substrate 141 side is referred to as the back surface.

[0020] A step 145 is formed on the front surface of the semiconductor substrate 140 by removing the epitaxial layers 144, 143 in the edge termination region 133. The epitaxial layers 143, 144 remain in a mesa shape in the active region 131 and the boundary region 132. On the front surface of the semiconductor substrate 140, the portion 140a of the active region 131 and the boundary region 132 (hereinafter referred to as the first surface) is an exposed surface of the p-type epitaxial layer 144, and the portion 140b of the edge termination region 133 (hereinafter referred to as the second surface) is an exposed surface of the n-type epitaxial layer 144. - 1 is an exposed surface of the type epitaxial layer 142.

[0021] The epitaxial layers 143 and 144 are provided with an element structure (trench gate structure) of the semiconductor device 110 and a p-type peripheral region 150. The trench gate structure is formed by a p-type base region 103 and a n-type MOSFET provided in the active effective region 131a. + type source region 104, p ++ The structure is made up of a contact region 105, a trench 106, a gate insulating film 107, and a gate electrode 108. A p-type contact region 105 is formed near the bottom of the trench 106 for electric field relaxation. + The n-type regions 121 and 122 and the n-type current diffusion region 123 are selectively provided.

[0022] The p-type peripheral region 150 is in contact with the front surface (first surface 140a) of the semiconductor substrate 140 over the entire active ineffective region 131b and the boundary region 132. - The p-type peripheral region 150 is provided between the active region 131 and the drift region 102. The p-type peripheral region 150 is composed of p-type regions 151-153 which are adjacent to each other in the depth direction and have different impurity concentrations. The p-type peripheral region 150 is fixed to the potential of the source electrode 111 via the source ring 116. The p-type peripheral region 150 surrounds the periphery of the active region 131 in the boundary region 132, and extends into the inactive region 131b.

[0023] In the active inactive region 131b, all of the p-type regions 151-153 constituting the p-type periphery region 150 face the gate pad 112, the gate runner 113, the gate resistor 114, and the gate polysilicon wiring layer 174 via the field oxide film 171. In the boundary region 132, all of the p-type regions 151-153 constituting the p-type periphery region 150 face the gate ring 115, the source ring 116, and the gate polysilicon wiring layers 172, 176 via the field oxide film 171.

[0024] The third surface 140c connecting the first surface 140a and the second surface 140b of the front surface of the semiconductor substrate 140 is the side surface of the epitaxial layers 143 and 144 exposed by the formation of the step 145. ++ The p-type regions 151 to 153 have their outer periphery ends (ends on the chip end side) connected together by a p-type connecting region 154. ++ The mold coupling region 154 surrounds the entire third surface 140c on the front surface of the semiconductor substrate 140, and has the function of alleviating the electric field in the vicinity of the third surface 140c.

[0025] The p-type base region 103 and the n-type base region 104 are provided in the active region 131 and the boundary region 132. + type source region 104, p ++ Type contact region 105, p + The n-type region 122, the n-type current diffusion region 123, the p-type regions 151 to 153, and the p ++ The type connection region 154 may be formed by the epitaxial layers 143, 144 themselves, may be a diffusion region formed by ion implantation in the surface region of the epitaxial layers 143, 144, or may be a region that partially includes a diffusion region formed by ion implantation in the epitaxial layers 143, 144.

[0026] In the edge termination region 133, p-type regions 161 and 162 constituting a breakdown voltage structure 160 and n-type regions 163 and 164 are provided on the front surface side of the semiconductor substrate 140. +As described above, the epitaxial layers 143 and 144 are removed from the edge termination region 133 to form an n-type channel stopper region 163 on the front surface (second surface 140b) of the semiconductor substrate 140. - The p-type epitaxial layer 142 is exposed. + The n-type channel stopper region 163 - The diffusion region is formed in the surface region of the type epitaxial layer 142 by ion implantation.

[0027] In the boundary region 132 and the edge termination region 133, the front surface of the semiconductor substrate 140 is covered with an insulating layer consisting of a field oxide film 171 and an interlayer insulating film 109. An external connection terminal 119 is soldered to a portion (source pad) of the source electrode 111 (111a to 111c) exposed in an opening of the passivation film 120. + The entire surface of the starting substrate 141 (the back surface of the starting substrate 141) is + Starting substrate 141(n + A drain electrode 124 is provided in contact with the n-type drain region 101).

[0028] However, in the semiconductor device 110 (MOSFET) of the reference example, the n-type epitaxial layer 143 and the p-type epitaxial layer 144 are - Type epitaxial layer 142(n - The epitaxial layers 143, 144 have better crystallinity than the n-type drift region 102, and therefore have a longer lifetime of minority carriers (holes in the n-type region and electrons in the p-type region formed in the epitaxial layers 143, 144). - This is because the crystal growth (epitaxial growth) rates are different between the type epitaxial layer 142 and the epitaxial layers 143 and 144 due to the difference in their roles.

[0029] n -Since the p-type epitaxial layer 142 is relatively thick to ensure a certain breakdown voltage, it is grown in a relatively short time at the expense of some crystallinity. On the other hand, the epitaxial layers 143 and 144 are grown over a long period of time with good crystallinity because they are the portions in which the trench gate structure is formed and their crystallinity affects the device characteristics of the MOSFET. In particular, the p-type epitaxial layer 144 is in contact with the gate insulating film 107 and a channel (n-type inversion layer) is formed when the MOSFET is on, so good crystallinity is required.

[0030] n - The difference in the lifetime of minority carriers between the p-type epitaxial layer 142 and the epitaxial layers 143 and 144 causes the following problem. + The p-type regions 121 and 122 and the p-type peripheral region 150, and the n-type current diffusion region 123 and - The parasitic pn junction diode (body diode) formed by the pn junction of the drift region 102 and the n - Minority carriers (holes and electrons) are injected into the type drift region 102 and are accumulated therein.

[0031] When the MOSFET turns off from this state (the transition period from the forward conduction of the body diode to the off state of the MOSFET), n - Holes in the n-type drift region 102 are discharged to the source electrode 111, - The number of holes decreases from the n-type drift region 102. - The holes in the n-type drift region 102 are discharged to the source electrode 111 or the source ring 116. In the active effective region 131a, the source contact area is relatively large, so that - The holes in the type drift region 102 are discharged relatively uniformly to the source electrode 111 .

[0032] On the other hand, n in the active invalid region 131b, the boundary region 132 and the edge termination region 133 -Holes in the p-type drift region 102 tend to flow into the p-type peripheral region 150 (the epitaxial layers 143, 144 in the active inactive region 131b and the boundary region 132) and are discharged to the source ring 116 through the p-type peripheral region 150. Since the lifetime of minority carriers in the p-type peripheral region 150 is relatively long, the period until the carriers disappear in the p-type peripheral region 150 is relatively long.

[0033] Therefore, n - The time it takes for the reverse recovery current (hole current) of the body diode to be cut off varies depending on the path that the holes in the drift region 102 take to be discharged to the source electrode 111 or the source ring 116. If dV / dt (the rate of change of the drain-source voltage over time) is small, n - The holes in the p-type drift region 102 are discharged relatively uniformly to the source ring 116 even when passing through the p-type peripheral region 150. However, if dV / dt is large and steep, the area or locations where the extraction of the hole current is delayed increases, and the hole current is likely to concentrate in those locations.

[0034] In the active invalid region 131b, boundary region 132, and edge termination region 133, the extraction of hole current is delayed at the four corners (vertices) of the gate pad 112 having a substantially rectangular planar shape, the four corners (vertices of the semiconductor substrate 140) of the edge termination region 133 that surrounds the boundary region 132 in a substantially rectangular shape, the vicinity of the gate resistor 114, and the vicinity of other circuit components (not shown). In such places (particularly the boundary region 132), the breakdown resistance during switching of the MOSFET, particularly the resistance to dV / dt, is locally reduced, leading to breakdown.

[0035] This problem becomes more noticeable as the temperature (junction temperature) of the semiconductor substrate 140 decreases. The reason is that when SiC is used as the semiconductor material, the sheet resistance of the p-type region in the semiconductor substrate 140 increases as the temperature of the semiconductor substrate 140 decreases. As the temperature of the semiconductor substrate 140 decreases, the resistance of the p-type peripheral region 150 increases, and the n-type junction temperature increases during reverse recovery of the body diode of the MOSFET. -Holes that have flowed from drift region 102 into p-type peripheral region 150 are less likely to flow through p-type peripheral region 150.

[0036] For example, in the semiconductor device 110 of the reference example, when the temperature of the semiconductor substrate 140 is a low temperature of about −40° C. or −55° C., there is a risk of destruction if a reverse recovery current of about two to three times the rated current flows through the body diode during the period until the reverse recovery current of the body diode is cut off. Problems to be solved in this embodiment include, for example, improving the reverse recovery characteristics of the body diode to improve the destruction resistance of the MOSFET (semiconductor device), particularly the resistance to steep dV / dt.

[0037] (Embodiment) The structure of the semiconductor device according to the embodiment will be described. FIG. 1 is a plan view showing the layout of the semiconductor device according to the embodiment as viewed from the front surface side of the semiconductor substrate. FIGS. 2, 4, and 5 are cross-sectional views showing the cross-sectional structures along the cutting lines A-A', B-B', and C-C' in FIG. 1, respectively. FIG. 3 is a cross-sectional view showing another example of the cross-sectional structure along the cutting line A-A' in FIG. 1. The semiconductor device 10 according to the embodiment shown in FIGS. 1 to 5 is a vertical MOSFET with a trench gate structure (insulated gate structure: element structure consisting of a three-layer structure of metal-oxide film-semiconductor) that includes a metal wiring layer in a boundary region 32 between an active region 31 and an edge termination region 33 of a semiconductor substrate (semiconductor chip) 40 using silicon carbide (SiC) as a semiconductor material, and includes a predetermined breakdown voltage structure 60 in the edge termination region 33.

[0038] The active region 31 is a region through which a main current (drift current) flows when the MOSFET is on. The active region 31 has, for example, a substantially rectangular planar shape, and is disposed substantially at the center (chip center) of the semiconductor substrate 40. The active region 31 occupies most of the area (surface area) of the semiconductor substrate 40. The effective region (active effective region) 31a of the active region 31 is a portion in which epitaxial layers 43 and 44, which will be described later, are disposed, and functions as a MOSFET. A plurality of cells (functional units of an element) of the MOSFET having the same structure are disposed adjacent to each other in the active effective region 31a. The ineffective region (active ineffective region) 31b of the active region 31 is a region of the active region 31 excluding the active effective region 31a, in which no MOSFET cells are disposed, and which does not function as a MOSFET.

[0039] Boundary region 32 is a portion outside (chip end side) of step 45 described later and inside (chip center side) of breakdown withstand structure 60, adjacent to active region 31 and surrounding active region 31 in a substantially rectangular shape. Edge termination region 33 is a region between boundary region 32 and the end (chip end) of semiconductor substrate 40, adjacent to boundary region 32 and surrounding boundary region 32 in a substantially rectangular shape. - Active region 31 and boundary region 32 are isolated from edge termination region 33 by a pn junction with type drift region 2. The widths of active region 31, boundary region 32 and edge termination region 33 (widths in the direction from the chip center to the chip end) are similar to those of active region 131, boundary region 132 and edge termination region 133 of the reference structure (see Figures 6 to 9), respectively.

[0040] On the front surface of the semiconductor substrate 40, there are provided electrode pads such as a source pad (source electrode 11) and a gate pad 12, metal wiring layers such as a gate runner 13, a gate ring 15 (solid thick line in FIG. 1), and a source ring 16 (solid dashed line in FIG. 1), a gate resistor 14 made of polysilicon (hatched portion in FIG. 1), and gate polysilicon wiring layers 72, 74, 76 (not shown in FIG. 1). The source electrode (first electrode) 11 is provided in the active effective region 31a and covers substantially the entire surface of the active effective region 31a. The source electrode 11 may be arranged in two or more separate locations in the active effective region 31a. For example, in the active region 31, a gate runner 13 extending linearly in a direction parallel to the front surface of the semiconductor substrate 40 through substantially the center of the semiconductor substrate 40, and two source electrodes 11 are arranged line-symmetrically with respect to the gate runner 13, and a plurality of cells having the same structure may be arranged line-symmetrically across the gate runner 13.

[0041] The gate pad 12 and the gate runner (gate wiring layer) 13 and the ... runner (gate wiring layer) 13 and the gate runner (gate wiring layer) 13 and the gate runner (gate wiring layer) 13 and the gate runner (gate wiring layer + Gate polysilicon wiring layers (gate wiring layers) 74, 76 on the source / drain region 1 side and the gate resistor 14 are provided in the active ineffective region 31b. The gate ring (gate wiring layer) 15, the source ring 16, and the gate polysilicon wiring layer (gate wiring layer) 72 directly below the gate ring 15 are provided in the boundary region 32. The gate pad 12 has, for example, a substantially rectangular planar shape and is disposed in the vicinity of the boundary between the active region 31 and the boundary region 32. The gate runner 13 faces the gate pad 12 at one end, passes through substantially the center of the semiconductor substrate 40, and extends linearly in a first direction X described later so as to move away from the gate pad 12.

[0042] The gate resistor 14 is disposed between the gate pad 12 and the gate runner 13. The gate ring 15 is disposed apart from the gate pad 12 and the gate runner 13, and surrounds the periphery of the active region 31, for example, in a substantially rectangular shape with a partial opening near the other end of the gate runner 13. The gate polysilicon wiring layer 72 directly below the gate ring 15 surrounds the periphery of the active region 31 in a substantially rectangular shape with a partial opening or a substantially closed rectangular shape, similar to the gate ring 15. The source ring 16 is disposed outside the gate ring 15, and surrounds the periphery of the active region 31 in a substantially rectangular shape. The source ring 16 is connected to the source electrode 11 at a partially open portion of the gate ring 15, and is fixed to the potential of the source electrode 11.

[0043] The semiconductor substrate 40 is a n-type semiconductor substrate using SiC as a semiconductor material. + On the front surface of the starting substrate 41, - n-type drift region (first semiconductor region) 2 - The n-type epitaxial layer (first epitaxial layer) 42, the n-type epitaxial layer (second epitaxial layer) 43 that will become the n-type current diffusion region 23, and the p-type epitaxial layer (second epitaxial layer) 44 that will become the p-type base region (second semiconductor region) 3 are laminated in this order. + The starting substrate 41 is n + This is the n-type drain region 1. - Since the epitaxial layer 42 is relatively thick to ensure a predetermined breakdown voltage, it may be grown in a relatively short time at the expense of some crystallinity. Since the crystallinity of the epitaxial layers 43 and 44 determines the device characteristics of the MOSFET (semiconductor device 10), it is preferable that the epitaxial layers 43 and 44 are grown with good crystallinity over a long period of time.

[0044] The semiconductor substrate 40 has a first main surface on the p-type epitaxial layer 44 side as a front surface, and an n +The second main surface on the mold starting substrate 41 side is referred to as the back surface. A step 45 is formed on the front surface of the semiconductor substrate 40, in which the epitaxial layers 44, 43 are all removed by etching in the active ineffective region 31b, the boundary region 32, and the edge termination region 33. The front surface of the semiconductor substrate 40 is closer to the active ineffective region 31b, the boundary region 32, and the edge termination region 33 (hereinafter referred to as the second surface) 40b than to the active effective region 31a (hereinafter referred to as the first surface) 40a, with the step 45 as the boundary. + The epitaxial layers 43 and 44 are recessed toward the active drain region 1. The epitaxial layers 43 and 44 remain only in the active effective region 31a.

[0045] In this manner, the entire area of ​​the semiconductor substrate 40 other than the active effective area 31a is + On the starting substrate 41 - n type drift region 2 - The layer structure is made up of only the n-type epitaxial layer 42. - Even if the crystallinity of the n-type epitaxial layer 42 is inferior to that of the epitaxial layers 43 and 44, the semiconductor substrate 40 can have a layered structure in which all the areas with relatively good crystallinity are removed except for the active ineffective region 31a. - The layered structure has a minority carrier lifetime that is approximately uniform by removing all of the portions in which the minority carrier lifetime is longer than that of the type drift region 2.

[0046] The first surface 40a of the front surface of the semiconductor substrate 40 is the exposed surface of the p-type epitaxial layer 44, and the second surface 40b is the n-type epitaxial layer 44. -This is an exposed surface of the type epitaxial layer 42. At both the boundary between the active effective region 31a and the active ineffective region 31b and the boundary between the active effective region 31a and the boundary region 32, it is preferable that the distances W1 and W2 from the step 45 (the boundary between the first surface 40a and the third surface 40c described below) to the sidewall of the trench 6 closest to the step 45 be approximately 5 μm or less. The entire step 45 (i.e., from the boundary between the first surface 40a and the third surface 40c to the boundary between the second surface 40b and the third surface 40c) is located in the active effective region 31a. When the step 45 is formed, the epitaxial layers 44, 43 are formed in the n-type epitaxial layer 42 together. - Some surface area of ​​the type epitaxial layer 42 may be removed.

[0047] The third surface 40c connecting the first surface 40a and the second surface 40b of the front surface of the semiconductor substrate 40 is a side surface of the epitaxial layers 43, 44 exposed by the formation of the step 45. The third surface 40c of the front surface of the semiconductor substrate 40 may be perpendicular to the first and second surfaces 40a, 40b of the front surface of the semiconductor substrate 40, or may be inclined so that the epitaxial layers 43, 44 have a tapered (trapezoidal) cross-sectional shape. Only a trench gate structure is provided inside the epitaxial layers 43, 44. The crystallinity of the epitaxial layers 43, 44 determines the device characteristics of the MOSFET, so it is preferable that the epitaxial layers 43, 44 are well grown. The trench gate structure is formed by forming a trench between the p-type base region 3 and the n-type base region 40 and the p-type base region 40. + Type source region 4, p ++ It is composed of a mold contact region 5 , a trench 6 , a gate insulating film 7 and a gate electrode 8 .

[0048] The p-type base region 3 is formed on a first surface 40a of the front surface of the semiconductor substrate 40 and on a n - Type epitaxial layer 42(n - The p-type base region 3 is provided over the entire active effective region 31a between the p-type drift region 2 and the n-type base region 3. The p-type base region 3 reaches the third surface 40c of the front surface of the semiconductor substrate 40. The p-type base region 3 is adjacent to all side walls of all the trenches 6. + Type source region 4 and p ++ The n-type contact region 5 is a diffusion region formed in the surface region of the p-type epitaxial layer 44 by ion implantation.+ Type source region 4 and p ++ The n-type contact regions 5 are selectively provided between the first surface 40a of the front surface of the semiconductor substrate 40 and the p-type base region 3, in contact with the p-type base region 3. + Type source region 4 and p ++ The contact region 5 contacts the ohmic electrode 17 on a first surface 40 a on the front surface of the semiconductor substrate 40 .

[0049] n + The source region 4 is provided adjacent to the side wall of the trench 6 and contacts the gate insulating film 7 at the side wall of the trench 6. The trench 6 closest to the active ineffective region 31b in a second direction Y (short direction of the trench 6) described later and the trench 6 closest to the boundary region 32 in the second direction Y have p ++ A p-type contact region 5 is provided adjacent to the other sidewall (the active ineffective region 31b side, the boundary region 32 side) and a p-type peripheral region 50, which will be described later, is provided adjacent to the other sidewall (the active ineffective region 31b side, the boundary region 32 side). + The p-type source region 4 is not provided. The p-type peripheral region 50 surrounds the periphery of the active effective region 31a and is adjacent to the end sidewall of the trench 6 in the longitudinal direction (first direction X described later). + Type source region 4 and p ++ The p-type contact region 5 extends linearly in the first direction X and contacts the p-type peripheral region 50 at its end in the first direction X.

[0050] The p-type epitaxial layer 44 has n + Type source region 4, p ++ The portion excluding the p-type contact region 5 and the p-type peripheral region 50 described later constitutes the p-type base region 3. ++ The p-type contact region 5 may not be provided. ++Instead of the contact region 5, the p-type base region 3 reaches the front surface of the semiconductor substrate 40. The trench 6 penetrates the p-type epitaxial layer 44 from the first surface 40a of the front surface of the semiconductor substrate 40 in the depth direction Z, and terminates inside the n-type epitaxial layer 43. The trenches 6 extend linearly in a first direction X (longitudinal direction) parallel to the front surface of the semiconductor substrate 40, for example, and are arranged in a stripe shape adjacent to each other in a second direction Y (lateral direction) parallel to the front surface of the semiconductor substrate 40 and perpendicular to the first direction X. A gate electrode 8 is provided inside the trench 6 with a gate insulating film 7 interposed therebetween.

[0051] p-type base region 3 and n - Between the n-type drift region 2 and the bottom surface of the trench 6, + A deep position on the drain region 1 side is + The p-type regions 21 and 22 and the n-type current diffusion region 23 are selectively provided. + The type region 21 is n - The p-type epitaxial layer 42 is a diffusion region formed by ion implantation into the surface region of the p-type epitaxial layer 42. + The n-type region 22 and the n-type current spreading region 23 are formed from the n-type epitaxial layer 43. - The p-type epitaxial layer 42 is a diffusion region formed by ion implantation over the surface region of the p-type epitaxial layer 42. + The p-type regions 21 and 22 are fixed to the potential of the source electrode 11, and have the function of depleting the n-type current diffusion region 23 when the MOSFET is turned off, thereby relaxing the electric field near the bottom of the trench 6. + The mold regions 21 and 22 extend linearly in the first direction X, and have p + It contacts the outer periphery region 51 of the mold.

[0052] p + The p-type region 21 is provided apart from the p-type base region 3 and faces the bottom surface of the trench 6 in the depth direction Z. + The mold region 21 may be in contact with the gate insulating film 7 at the bottom of the trench 6, or may be separated from the trench 6. +The type region 22 is formed between the adjacent trenches 6 and the p + The mold region 21 is provided apart from the upper surface (n + The p-type source region 4 faces the p-type base region 3. + The type region 22 is n - The lower (n + The upper portion (n + The portion on the side of the source region 4 is connected to the portion on the side of the source region 4 in the depth direction Z. + The type region 21 is p + It may be formed simultaneously with the lower part of the mold region 22. + The mold regions 21 and 22 are + n - It may be in contact with the mold drift region 2 .

[0053] The n-type current diffusion region 23 is a so-called current spreading layer (CSL) that reduces the spreading resistance of carriers. + The p-type base region 3 is provided adjacent to the p-type regions 21 and 22 and the trench 6, and the upper surface of the p-type base region 3 is in contact with the n-type - The n-type current diffusion region 23 is in contact with the n-type drift region 2. - The lower portion formed in the n-type epitaxial layer 42 and the upper portion formed in the n-type epitaxial layer 43 are connected in the depth direction Z. The n-type current diffusion region 23 may not be provided. In this case, instead of the n-type current diffusion region 23, - p type drift regions 2 adjacent to each other + The p-type base region 3 is connected to the p-type base region 3 in the second direction Y. + It extends between the mold region 21 and reaches the trench 6 .

[0054] n - The p-type epitaxial layer 42 + The n-type regions 21 and 22, the n-type current diffusion region 23, and the p + The mold outer peripheral region 51, FLRs 61 and 62 described later, and n+ The portion excluding the type channel stopper region 63 is n - The n-type drift region is - The drift region 2 is provided from the active region 31 to the boundary region 32 and the edge termination region 33, and is exposed at the chip edge (the side surface of the semiconductor substrate 40). - Between the n-type drift region 2 and the n-type drift region 3, - Adjacent to the drift region 2, + A second conductive type peripheral region 51 is provided. + The mold peripheral region 51 is n - The p-type epitaxial layer 42 is a diffusion region formed by ion implantation into the surface region of the p-type epitaxial layer 42. + The mold periphery region 51 surrounds the periphery of the active effective region 31a.

[0055] p + The mold periphery region 51 extends beyond the step 45 on the front surface of the semiconductor substrate 40 toward the active region 31a, and reaches the side wall of the trench 6 closest to the step 45. + The mold peripheral region 51 extends toward the first surface 40a along the third surface 40c of the front surface of the semiconductor substrate 40, and contacts, at its upper surface, the p-type epitaxial layer 44 between the third surface 40c of the front surface of the semiconductor substrate 40 and the trench 6 closest to the step 45. + The mold peripheral region 51 is a region facing the bottom surface of the trench 6 closest to the step 45. + It may be in contact with the mold region 21. + The depth position of the lower surface of the mold peripheral region 51 is p + It may be substantially the same as the depth position of the lower surface of the mold region 21. + The outer peripheral region 51 is covered with a field oxide film 71. + The mold peripheral region 51 is a ++ Electrical connection is made to the source ring 16 via the mold perimeter contact region 54 .

[0056] The p-type epitaxial layer 44 (p-type base region 3) between the third face 40c of the front surface of the semiconductor substrate 40 and the trench 6 closest to the step 45 constitutes a p-type peripheral base region 52. The p-type peripheral base region 52 extends along the periphery of the active effective region 31a. ++ A mold peripheral area 53 is provided. ++ The p-type peripheral region 53 is a diffusion region formed in the surface region of the p-type epitaxial layer 44 by ion implantation. ++ The p-type peripheral region 53 contacts the p-type peripheral base region 52 at its lower surface. ++ The mold periphery region 53 is adjacent to the sidewall of the trench 6 closest to the step 45. ++ The mold periphery region 53 extends along the periphery of the active effective region 31a. ++ The mold peripheral region 53 is p ++ It may be formed at the same time as the mold contact region 5 .

[0057] The p-type peripheral base region 52 is + The mold peripheral region 51 and p ++ The entire surface except for the contact surface with the mold peripheral region 53 is in contact with the gate insulating film 7 and the field oxide film 71. ++ The p-type peripheral region 53 contacts the gate insulating film 7 and the field oxide film 71 on the entire surface thereof except for the contact surface with the p-type peripheral base region 52. ++ The mold outer peripheral region 53 may not be provided. In this case, p ++ Instead of the p-type peripheral region 53, the p-type peripheral base region 52 reaches the first surface 40a of the front surface of the semiconductor substrate 40. + Between the mold peripheral region 51, p + In contact with the mold outer peripheral region 51 ++ A mold peripheral contact region 54 is optionally provided. ++ The mold peripheral contact region 54 contacts an ohmic electrode 55 on the second surface 40 b of the front surface of the semiconductor substrate 40 .

[0058] These p +a p-type peripheral region 51, a p-type peripheral base region 52 and a p ++ The p-type peripheral region 50 is formed by the n-type peripheral region 53. The p-type peripheral region 50 surrounds the periphery of the active effective region 31a. The p-type peripheral region 50 is formed by the n-type peripheral region 53. The p-type peripheral region 50 surrounds the periphery of the active effective region 31a. - The p-type drift region 2 has a function of drawing out holes accumulated in the p-type drift region 2 to the source electrode 11 or source ring 16 described later when the MOSFET is turned off. + The p-type peripheral base region 52 and the p-type source ring 16 are electrically connected to the p-type peripheral base region 51, and are fixed to the potential of the source electrode 11. ++ The mold periphery region 53 is not electrically or directly connected to the source electrode 11 and the source ring 16 .

[0059] Along the third surface 40c of the front surface of the semiconductor substrate 40, ++ A mold connection region 57 may be provided (see FIG. 3). ++ The type-linked region 57 is p + a p-type peripheral region 51, a p-type peripheral base region 52 and a p ++ The outer peripheral end portions of the mold outer peripheral region 53 (the end portion on the active ineffective region 31b side and the end portion on the boundary region 32 side) are connected. ++ The p-type connection region 57 surrounds the entire third surface 40c of the front surface of the semiconductor substrate 40 and the boundary between the second surface 40b and the third surface 40c, and has the function of alleviating the electric field in the vicinity of the third surface 40c. In this embodiment, the step 45 is not formed in the edge termination region 33 or in a position adjacent to the edge termination region 33, so that the p-type region (p + a p-type peripheral region 51, a p-type peripheral base region 52 and a p ++ It is sufficient that the mold peripheral region 53) is all connected, and p ++ The mold connection region 57 does not have to be provided (see FIG. 2).

[0060] The interlayer insulating film 9 is provided on almost the entire front surface of the semiconductor substrate 40, and covers all of the gate electrodes 8. In the active effective region 31a, the interlayer insulating film 9 is provided with n+ Type source region 4 and p ++ A contact hole is provided to expose the type contact region 5. The ohmic electrode 17 is in ohmic contact with the semiconductor substrate 40 through the contact hole. The ohmic electrode 17 is, for example, a nickel silicide (NixSiy, where x and y are positive numbers) film formed by silicidation with the semiconductor substrate 40. A barrier metal 18 covers substantially the entire surface of the interlayer insulating film 9 and the ohmic electrode 17 in the active effective region 31a. The barrier metal 18 has a function of preventing atomic diffusion and mutual reaction between the source electrode 11 and the semiconductor substrate 40.

[0061] The source electrode 11 is provided on almost the entire surface (first surface 40a) of the semiconductor substrate 40 in the active effective region 31a, and is connected to the n-type ... + Type source region 4 and p ++ The source electrode 11 is electrically connected to the contact region 5. The source electrode 11 is formed by laminating an aluminum (Al) alloy film 11a (or Al film), a plating film 11b, and a solder layer 11c in this order. The Al alloy film 11a is provided on the surface of the barrier metal 18. The plating film 11b is provided on the surface of the Al alloy film 11a. The plating film 11b has a function of improving solder wettability when the solder layer 11c is formed. A terminal pin 19 (or a bonding wire: not shown) is solder-joined to the plating film 11b via the solder layer 11c.

[0062] The plating film 11b and the solder layer 11c are provided in the opening of the passivation film 20. The terminal pin 19 is a round bar-shaped (cylindrical) wiring member that is solder-joined to the plating film 11b in a state where it stands approximately perpendicular to the front surface of the semiconductor substrate 40. The passivation film 20 covers the surface of the Al alloy film 11a except for the plating film 11b. The passivation film 20 covers the outer peripheral end of the plating film 11b. The portion of the plating film 11b exposed in the opening of the passivation film 20 functions as a source pad. The rear surface (n +A drain electrode (second electrode) 24 is provided on the entire back surface of the starting substrate 41. The drain electrode 24 is in ohmic contact with the back surface of the semiconductor substrate 40, and + Type drain region 1(n + The mold is electrically connected to a starting substrate 41).

[0063] The second surface 40b of the front surface of the semiconductor substrate 40 is covered with an insulating layer formed by laminating a field oxide film 71 and an interlayer insulating film 9 in this order. The field oxide film 71 extends between the front surface of the semiconductor substrate 40 and the interlayer insulating film 9 toward the active effective region 31a side, covers the third surface 40c of the front surface of the semiconductor substrate 40, and terminates on the first surface 40a. Gate polysilicon wiring layers 74, 76 and a gate resistor 14 (not shown in FIGS. 2 to 5) are provided between the field oxide film 71 and the interlayer insulating film 9 in the active ineffective region 31b. A gate polysilicon wiring layer 72 is provided between the field oxide film 71 and the interlayer insulating film 9 in the boundary region 32. The gate polysilicon wiring layers 72, 74, 76 are exposed to different contact holes in the interlayer insulating film 9.

[0064] The gate pad 12, the gate runner 13, and the gate ring 15 are electrically connected to the gate polysilicon wiring layers 74, 76, and 72 through the barrier metals 75, 77, and 73 at the contact holes. The gate polysilicon wiring layer 74 directly below the gate pad 12 is connected to one end of the gate resistor 14. The gate polysilicon wiring layer 76 directly below the gate runner 13 is connected to the other end of the gate resistor 14 and is electrically connected to the gate pad 12 through the gate resistor 14. The gate resistor 14 is formed by ion-implanting n-type impurities into polysilicon. The gate electrodes 8 of all the cells of the MOSFET are connected to either or both of the gate polysilicon wiring layers 76 and 72 directly below the gate runner 13 and the gate ring 15. The barrier metals 73, 75, and 77 each have the function of preventing atomic diffusion and mutual reaction between layers facing each other. The barrier metals 73, 75, and 77 are formed, for example, at the same time as the barrier metal 18. When the gate resistor 14 is not built in, the gate pad 12 and the gate polysilicon wiring layer 74 directly below the gate pad 12 may be in contact with each other.

[0065] The interlayer insulating film 9 and the field oxide film 71 have p ++ A contact hole is provided to expose the peripheral contact region 54. The ohmic electrode 55 is in ohmic contact with the semiconductor substrate 40 through the contact hole. The source ring 16 is connected to the p ++ The gate pad 12, the gate runner 13, the gate resistor 14, the gate ring 15, the source ring 16 and the gate polysilicon wiring layers 72, 74, 76 are electrically connected to the outer peripheral contact region 54. The ohmic electrode 55 and the barrier metal 56 are formed, for example, simultaneously with the ohmic electrode 17 and the barrier metal 18, respectively. The gate pad 12, the gate runner 13, the gate ring 15 and the source ring 16 are formed, for example, simultaneously with the Al alloy film 11a. The entire surfaces of the gate pad 12, the gate runner 13, the gate resistor 14, the gate ring 15, the source ring 16 and the gate polysilicon wiring layers 72, 74, 76 are formed in the depth direction Z by p + It faces the mold outer periphery region 51 .

[0066] The second surface 40b of the front surface of the semiconductor substrate 40 and n - Between the n-type drift region 2, - A plurality of p-type regions (hereinafter referred to as FLRs) 61 and a plurality of p - Type region (hereinafter referred to as FLR) 62 and n + and a type channel stopper region 63 are selectively provided. Here, a case where the breakdown voltage structure 60 has a field limiting ring (FLR) structure will be described as an example, but the breakdown voltage structure 60 may also have a junction termination extension (JTE) structure.

[0067] The FLRs 61 and 62 form, for example, a spatially modulated FLR structure. The spatially modulated FLR structure is a voltage-resistant structure in which the p-type impurity concentration per unit volume is gradually decreased toward the outside. The multiple FLRs 61 are spaced apart from each other and concentrically surround the boundary region 32. The FLRs 61 arranged closer to the outside have a narrower width (width from the chip center toward the chip end) and a wider gap between them and the adjacent FLRs 61 on the inside. The innermost FLR 62 surrounds all the FLRs 61 and is arranged between all the adjacent FLRs 61. The innermost FLRs 61 and 62 contact the p-type peripheral region 50.

[0068] The multiple FLRs 62 are spaced apart from one another and concentrically surround the boundary region 32. The FLRs 62 arranged on the outside have a narrower width (width in the direction from the chip center to the chip end) and are spaced apart from the adjacent FLRs 62 on the inside. The multiple FLRs 62, except for the innermost FLR 62, are arranged on the outside of the FLR 61. There is a gap of n between the adjacent FLRs 62. - The type drift region 2 extends to the second surface 40b of the front surface of the semiconductor substrate 40. - The drift region 2 surrounds all the FLRs 62 and is disposed between all the FLRs 62 adjacent to each other.

[0069] n +The type channel stopper region 63 is provided outside the breakdown voltage structure 60 and separated from the breakdown voltage structure 60. + The type channel stopper region 63 is exposed at the chip end (the side surface of the semiconductor substrate 40). + Instead of the p type channel stopper region 63, + A type channel stopper region may be provided. + The n-type channel stopper region 63 - The passivation film 20 is a diffusion region formed by ion implantation in the surface region of the type epitaxial layer 42. The passivation film 20 is a surface protective film that covers substantially the entire outermost surface of the front surface of the semiconductor substrate 40 (i.e., the surface of the interlayer insulating film 9) and protects the front surface of the semiconductor substrate 40.

[0070] The operation of the semiconductor device 10 according to the embodiment will be described. When a voltage equal to or higher than the gate threshold voltage is applied to the gate electrode 8 in a state where a positive voltage with respect to the source electrode 11 is applied to the drain electrode 24, the n + A channel (n-type inversion layer) is formed along the sidewall of the trench 6 in the region between the n-type source region 4 and the n-type current diffusion region 23. ++ From the drain region 1, - The n-type drift region 2, the n-type current diffusion region 23, and the channel are passed through the n + A drift current (main current) flows toward the type source region 4, turning the MOSFET on.

[0071] On the other hand, when a voltage positive with respect to the source electrode 11 is applied to the drain electrode 24, and the voltage applied to the gate electrode 8 is less than the gate threshold voltage, the p-type base region 3 and the p + The n-type regions 21 and 22, the n-type current diffusion region 23 and the n -Since the pn junction (main junction) with the type drift region 2 is reverse biased, the MOSFET maintains the off state. A depletion layer spreads from the pn junction in the vertical direction (toward the source electrode 11 and the drain electrode 24) in the active effective region 31a, and also spreads laterally from the active effective region 31a toward the active inactive region 31b and the boundary region 32. - By depleting the type drift region 2, a predetermined breakdown voltage of the active effective region 31a is ensured.

[0072] In addition, in the active ineffective region 31b and the boundary region 32, the p-type peripheral region 50 and the n - The pn junction with the drift region 2 is reverse biased, so that n - A depletion layer spreads laterally in the drift region 2. Furthermore, in the edge termination region 33, the FLRs 61 and 62 and the n - The pn junction with the drift region 2 is reverse biased, so that the n - The depletion layer spreads laterally outward in the n-type drift region 2. - The depletion layer extends outward in the type drift region 2, ensuring a predetermined breakdown voltage in the edge termination region 33 based on the dielectric breakdown field strength of the semiconductor material.

[0073] When the MOSFET is in the on-to-off state, the p-type base region 3, + The p-type regions 21 and 22 and the p-type peripheral region 50, the n-type current diffusion region 23 and the n - The parasitic pn junction diode (body diode) formed by the pn junction of the drift region 2 and the n - Minority carriers (holes and electrons) are injected into the n-type drift region 2 and stored there. When the MOSFET turns off from this state (reverse recovery of the body diode occurs), - The holes in the n-type drift region 2 are discharged to the source electrode 11 or the source ring 16, and the MOSFET is turned off. -Holes in the p-type drift region 2 tend to flow into the p-type peripheral region 50 and are discharged to the source ring 16 through the p-type peripheral region 50.

[0074] The semiconductor substrate 40 has n - The p-type epitaxial layer 42 has a layered structure in which all of the portions having better crystallinity than the p-type epitaxial layer 42 have been removed. - A diffusion region formed in the n-type epitaxial layer 42, the minority carrier lifetime of which is n - The lifetime of the minority carriers in the active inactive region 31b is approximately the same as the lifetime of the minority carriers in the type drift region 2. Therefore, there is almost no variation in the period until the reverse recovery current (hole current) of the body diode is cut off in the active inactive region 31b, the boundary region 32, and the edge termination region 33. Therefore, it is possible to suppress the hole current from concentrating locally in the active inactive region 31b, the boundary region 32, and the edge termination region 33.

[0075] As described above, according to the embodiment, the entire area other than the active effective area is n - All areas with better crystallinity than the n-type drift region have been removed. That is, in the active dead zone, boundary region, and edge termination region, - The lifetime of minority carriers in the n-type drift region is substantially uniform because all of the areas where the lifetime of minority carriers is longer than that in the n-type drift region are removed. - A p-type peripheral region is provided in the entire area between the p-type drift region and the n-type peripheral region. - A p-type region (FLR) is selectively provided between the p-type drift region and the p-type drift region to form a breakdown voltage structure, and the lifetime of minority carriers in the p-type drift region is n - This is approximately the same as the minority carrier lifetime in the type drift region.

[0076] As a result, when the MOSFET is turned off (when the body diode is in reverse recovery), the period until the reverse recovery current (hole current) of the body diode is cut off can be made almost uniform in the active ineffective region, the boundary region, and the edge termination region. This makes it possible to suppress local concentration of the hole current in the active ineffective region, the boundary region, and the edge termination region, and improve the reverse recovery characteristics of the body diode, thereby increasing the breakdown resistance during switching of the MOSFET, particularly the resistance to steep dV / dt. In addition, even when the temperature of the semiconductor substrate is low, for example, around -40°C or -55°C, the reverse recovery current of the body diode flows more easily in the p-type outer peripheral region than in the reference structure (see Figures 6 to 9), and the breakdown resistance when the junction temperature is low is also improved.

[0077] The present invention is not limited to the above-mentioned embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, in the above-mentioned embodiment, instead of the trench gate structure having a gate electrode extending in the depth direction from the front surface of the semiconductor substrate, a planar gate structure having a flat gate electrode extending along the front surface of the semiconductor substrate may be used. When the present invention is applied to a planar gate structure, n - It is preferable that the distance from a step formed on the front surface of the semiconductor substrate by removing all the parts having better crystallinity than the mold drift region to the end of the gate electrode closest to the step is about 5 μm or less. A gate runner may be provided in the boundary region. Circuit structures other than the main semiconductor element may be provided in the active inactive region or the boundary region.

[0078] Furthermore, the present invention is not limited to MOSFETs, but can be applied to vertical semiconductor devices having pn junctions, such as IGBTs (Insulated Gate Bipolar Transistors), BJTs (Bipolar Junction Transistors), and pin (p-intrinsic-n) diodes. The present invention can also be applied to cases where the semiconductor material is silicon (Si) or gallium nitride (GaN). In addition, in the above-mentioned embodiment, the first conductivity type is n-type and the second conductivity type is p-type, but the present invention is similarly valid even if the first conductivity type is p-type and the second conductivity type is n-type. [Industrial Applicability]

[0079] INDUSTRIAL APPLICABILITY As described above, the semiconductor device according to the present invention is useful as a power semiconductor device used in power conversion devices and power supply devices for various industrial machines. [Explanation of symbols]

[0080] 1,101 n + Type drain region 2,102 n - Mold Drift Region 3,103 p-type base region 4,104 n + Type Source Area 5,105 p ++ Mold Contact Area 6,106 Trench 7,107 Gate insulating film 8,108 Gate electrode 9,109 Interlayer insulating film 10,110 Semiconductor equipment 11,111 Source electrode 11a Al alloy membrane 11b Plating film 11c Solder layer 12,112 Gate Pad 13,113 Gate Runner 14,114 Gate resistor 15,115 Gate Ring 16,116 Source Ring 17 Ohmic electrode 18 Barrier metal 19,119 Terminal Pins 20,120 Passivation film 21,22,121,122 p for electric field relaxation + type area 23,123 n-type current diffusion region 24,124 Drain electrode 31,131 active area 31a,131a Active area 31b,131b Active Invalid Area 32,132 border area 33,133 Edge Termination Area 40,140 Semiconductor substrate 40a, 40b, 40c, 140a, 140b, 140c Front surface of semiconductor substrate 41,141 n + Starting substrate 42,142 n - Type epitaxial layer 43,143 n-type epitaxial layer 44,144 p-type epitaxial layer 45,145 steps 50,150 p-type outer area 51,151 p + Mold outer area 52,152 p-type peripheral base region 53,153 p ++ Mold outer area 54 p ++ Mold peripheral contact area 55 Ohmic electrode 56 Barrier Metal 57,154 p ++ type connection area 60,160 Pressure-resistant structure 61,62,161,162 p-type region that constitutes the breakdown voltage structure 63,163 n + Type channel stopper region 71,171 Field oxide 72,74,76,172,174,176 Gate polysilicon wiring layer 73,75,77,173,175,177 Barrier metal W1, W2: Distance from the step on the front surface of the semiconductor substrate to the sidewall of the trench closest to the step X: A first direction parallel to the front surface of the semiconductor substrate Y: A second direction that is parallel to the front surface of the semiconductor substrate and perpendicular to the first direction. Z depth direction

Claims

1. an active region provided in a semiconductor substrate; a termination region surrounding the active region; a boundary region between the active region and the termination region; a first semiconductor region of a first conductivity type provided within the semiconductor substrate across the active region and the termination region; a second semiconductor region of a second conductivity type provided between the first main surface of the semiconductor substrate and the first semiconductor region; an element structure provided in the active region and including a pn junction between the second semiconductor region and the first semiconductor region; a second conductivity type outer periphery region provided between the first major surface and the first semiconductor region in the boundary region; a first electrode provided on the first main surface and electrically connected to the element structure and the second conductivity type peripheral region; a second electrode provided on a second main surface of the semiconductor substrate; Equipped with The semiconductor substrate is a first epitaxial layer of a first conductivity type, the second conductivity type peripheral region being provided in a surface region on the first main surface side, the remaining portion excluding the second conductivity type peripheral region being the first semiconductor region; a second epitaxial layer on which the element structure is formed; the second epitaxial layer is provided only in the active region and forms the first main surface in the active region; The first epitaxial layer forms the first main surface over the entire area other than the active region.

2. The active region comprises: an active effective region in which the element structure is provided; an active ineffective region in which the element structure is not provided; the second conductivity type peripheral region is provided between the first main surface and the first semiconductor region in the active ineffective region, the second epitaxial layer is provided only in the active effective region and forms the first main surface in the active effective region; 2. The semiconductor device according to claim 1, wherein the first epitaxial layer forms the first main surface over an entire area other than the active region.

3. an active region provided in a semiconductor substrate; a termination region surrounding the active region; a boundary region between the active region and the termination region; a first semiconductor region of a first conductivity type provided within the semiconductor substrate across the active region and the termination region; a second semiconductor region of a second conductivity type provided between the first main surface of the semiconductor substrate and the first semiconductor region; an element structure provided in the active region and including a pn junction between the second semiconductor region and the first semiconductor region; a second conductivity type outer periphery region provided between the first major surface and the first semiconductor region in the boundary region; a first electrode provided on the first main surface and electrically connected to the element structure and the second conductivity type peripheral region; a second electrode provided on a second main surface of the semiconductor substrate; Equipped with The semiconductor device according to the present invention is characterized in that the semiconductor substrate has a structure in which all areas other than the active region, in which a minority carrier lifetime is longer than that of the first semiconductor region, have been removed.

4. The active region comprises: an active effective region in which the element structure is provided; an active ineffective region in which the element structure is not provided; the second conductivity type peripheral region is provided between the first main surface and the first semiconductor region in the active ineffective region, 4. The semiconductor device according to claim 3, wherein the semiconductor substrate has a structure in which all of the portions having a longer minority carrier lifetime than the first semiconductor region have been removed from the entire region other than the active region.

5. an active region provided in a semiconductor substrate; a termination region surrounding the active region; a boundary region between the active region and the termination region; a first semiconductor region of a first conductivity type provided within the semiconductor substrate across the active region and the termination region; a second semiconductor region of a second conductivity type provided between the first main surface of the semiconductor substrate and the first semiconductor region; an element structure provided in the active region and including a pn junction between the second semiconductor region and the first semiconductor region; a second conductivity type outer periphery region provided between the first major surface and the first semiconductor region in the boundary region; a first electrode provided on the first main surface and electrically connected to the element structure and the second conductivity type peripheral region; a second electrode provided on a second main surface of the semiconductor substrate; Equipped with The semiconductor device is characterized in that the semiconductor substrate includes an epitaxial layer, and has a structure in which all of the portions of the epitaxial layer having relatively good crystallinity are removed from the entire region other than the active region.

6. The active region comprises: an active effective region in which the element structure is provided; an active ineffective region in which the element structure is not provided; the second conductivity type peripheral region is provided between the first main surface and the first semiconductor region in the active ineffective region, 6. The semiconductor device according to claim 5, wherein the semiconductor substrate has a structure in which all of the portions of the epitaxial layer having relatively good crystallinity are removed from the entire region other than the active region.

7. The device structure is an insulated gate structure having a three-layer structure of metal-oxide film-semiconductor, 7. The semiconductor device according to claim 2, further comprising a gate pad provided on the first main surface via an insulating layer, facing the second conductivity type peripheral region in the depth direction in the active inactive region, and electrically connected to a gate electrode constituting the insulated gate structure.

8. The device structure is an insulated gate structure having a three-layer structure of metal-oxide film-semiconductor, 7. The semiconductor device according to claim 2, further comprising a gate wiring layer provided on the first main surface via an insulating layer, facing the second conductivity type peripheral region in the depth direction in the active inactive region, and electrically connected to a gate electrode constituting the insulated gate structure.

9. The device structure is an insulated gate structure having a three-layer structure of metal-oxide film-semiconductor, The semiconductor device according to any one of claims 1 to 6, further comprising a gate wiring layer provided on the first main surface via an insulating layer, facing the second conductivity type peripheral region in the depth direction in the boundary region, and electrically connected to a gate electrode constituting the insulated gate structure.

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