Semiconductor device including capacitor structure

Abstract

To provide a semiconductor device including a capacitor structure.SOLUTION: An example semiconductor device includes a capacitor structure on a substrate. The capacitor structure includes: a first electrode structure that includes first horizontal electrode portions apart from each other in a first direction perpendicular to the upper surface of the substrate and a first conductive pillar connected to each of the first horizontal electrode portions and extending in the first direction; a second electrode structure that includes a second conductive pillar extending through the first horizontal electrode portions in the first direction and second horizontal electrode portions apart from each other in the first direction on a side wall of the second conductive pillar and alternately arranged with the first horizontal electrode portions; and a capacitor dielectric layer that is arranged between the side wall of the second conductive pillar and the first horizontal electrode portions, and arranged on the upper surface, side surface and bottom surface of each of the second horizontal electrode portions.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device including a capacitor structure, and more particularly to a semiconductor device including a three-dimensional capacitor structure. [Background technology]

[0002] With the development of electronic devices, semiconductor devices such as integrated circuit devices and image sensors are becoming highly integrated and miniaturized. Along with the high integration and miniaturization of semiconductor devices, there is also a demand for integration and miniaturization of passive elements such as capacitors. For example, there is a demand for capacitors that have high capacitance even in a relatively small area in order to be used in high resolution image sensors. Summary of the Invention [Problem to be solved by the invention]

[0003] SUMMARY OF THE PRESENT DISCLOSURE The problem to be solved by the present invention is to provide a semiconductor device including a capacitor structure having an enhanced capacitance. [Means for solving the problem]

[0004] A semiconductor device according to an exemplary embodiment for achieving the above-mentioned technical problem includes a capacitor structure arranged on a substrate, the capacitor structure including a first electrode structure including a plurality of first horizontal electrode portions spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, and a first conductive pillar connected to each of the plurality of first horizontal electrode portions and extending in the first direction; a second electrode structure including a second conductive pillar penetrating the plurality of first horizontal electrode portions and extending in the first direction, and a plurality of second horizontal electrode portions on sidewalls of the second conductive pillar, spaced apart from each other in the first direction, and alternately arranged with the plurality of first horizontal electrode portions; and a capacitor dielectric layer arranged between the sidewalls of the second conductive pillar and the plurality of first horizontal electrode portions, and on the top surface, side surface and bottom surface of each of the plurality of second horizontal electrode portions.

[0005] According to an exemplary embodiment for achieving the technical problem, a semiconductor device includes a capacitor structure arranged on a substrate, the capacitor structure including a first electrode structure including a plurality of first horizontal electrode portions spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, a plurality of mold insulating layers arranged alternately with the first horizontal electrode portions and including a plurality of openings at positions overlapping each other in the first direction, and a first conductive pillar connected to each of the first horizontal electrode portions and extending in the first direction; a second electrode structure including a second conductive pillar penetrating the first horizontal electrode portions and extending in the first direction, and a plurality of second horizontal electrode portions on sidewalls of the second conductive pillar, spaced apart from each other in the first direction, and respectively arranged in the plurality of openings; and a capacitor dielectric layer arranged between the first electrode structure and the second electrode structure, the capacitor dielectric layer including portions arranged on the top surface, side surface and bottom surface of each of the second horizontal electrode portions within the plurality of openings.

[0006] According to an exemplary embodiment for achieving the technical problem, a semiconductor device includes: a semiconductor substrate having a plurality of pixel regions defined therein, the semiconductor substrate including a photoelectric conversion region in each pixel region; and a capacitor structure disposed on the semiconductor substrate, the capacitor structure including a first electrode structure including a plurality of first horizontal electrode portions spaced apart from each other in a first direction perpendicular to an upper surface of the semiconductor substrate, and a first conductive pillar connected to each of the plurality of first horizontal electrode portions and extending in the first direction; a second electrode structure including a second conductive pillar penetrating the plurality of first horizontal electrode portions and extending in the first direction, and a plurality of second horizontal electrode portions on sidewalls of the second conductive pillar, spaced apart from each other in the first direction, and alternately disposed with the plurality of first horizontal electrode portions; and a capacitor dielectric layer disposed between the sidewalls of the second conductive pillar and the plurality of first horizontal electrode portions, and on the upper surface, side surface and bottom surface of each of the plurality of second horizontal electrode portions. Effect of the Invention

[0007] According to the technical idea of ​​the present invention, a capacitor structure includes a first electrode structure having a stack structure of a plurality of first horizontal electrode portions and a plurality of first mold insulating layers, and a second electrode structure having a plurality of second horizontal electrode portions disposed in openings of the first mold insulating layer, and an area between the plurality of first horizontal electrode portions and the plurality of second horizontal electrode portions may correspond to an effective capacitance area. Since the capacitor structure has a three-dimensional stack structure, it may have a high capacitance in a relatively small area. [Brief description of the drawings]

[0008] [Figure 1] 1 is a perspective view illustrating a semiconductor device according to an exemplary embodiment; [Diagram 2] FIG. 2 is a cross-sectional view showing the semiconductor device of FIG. [Diagram 3] FIG. 3 is an enlarged view of a portion CX1 in FIG. [Figure 4] 4A to 4C are plan views showing various planar layouts of the first electrode structure and the second electrode structure. [Diagram 5] 4A to 4C are plan views showing various planar layouts of the first electrode structure and the second electrode structure. [Figure 6] 4A to 4C are plan views showing various planar layouts of the first electrode structure and the second electrode structure. [Figure 7] 4A to 4C are plan views showing various planar layouts of the first electrode structure and the second electrode structure. [Figure 8] 1 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment. [Figure 9] FIG. 9 is an enlarged view of a portion CX1 in FIG. [Figure 10] 1 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment. [Figure 11] FIG. 11 is an enlarged view of a portion CX1 in FIG. [Figure 12] 1 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment. [Figure 13] 1 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment. [Figure 14]1 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment. [Figure 15] 1 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment. [Figure 16] 1 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment. [Figure 17A] 1A-1D are schematic diagrams illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 17B] 1A-1D are schematic diagrams illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 18A] 1A-1D are schematic diagrams illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 18B] 1A-1D are schematic diagrams illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 19A] 1A-1D are schematic diagrams illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 19B] 1A-1D are schematic diagrams illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 20A] 1A-1D are schematic diagrams illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 20B] 1A-1D are schematic diagrams illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 21] 1A-1D are schematic diagrams illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 22A] 1A-1D are schematic diagrams illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment.

[0009] [Figure 22B] 1A-1D are schematic diagrams illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 23A] 1A-1D are schematic diagrams illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 23B] 1A-1D are schematic diagrams illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 24] 1A-1D are schematic diagrams illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. [Diagram 25]1A-1D are schematic diagrams illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 26] 1A-1D are schematic diagrams illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 27] 1A-1D are schematic diagrams illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 28] 1A-1D are schematic diagrams illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, exemplary embodiments of the technical concept of the present invention will be described in detail with reference to the accompanying drawings.

[0011] Fig. 1 is a perspective view showing a semiconductor device 100 according to an exemplary embodiment. Fig. 2 is a cross-sectional view showing the semiconductor device 100 of Fig. 1. Fig. 3 is an enlarged view of a portion CX1 of Fig. 2.

[0012] 1 to 3, a semiconductor device 100 includes a substrate 110 and a capacitor structure CS disposed on the substrate 110. The capacitor structure CS may include a first electrode structure 130 having a three-dimensional structure, a second electrode structure 140 having a three-dimensional structure, and a capacitor dielectric layer 150 disposed between the first electrode structure 130 and the second electrode structure 140.

[0013] The substructure 120 may be disposed on the substrate 110. The substrate 110 may include a semiconductor material such as silicon, germanium, SiC, GaAs, InAs, or InP. Various types of individual devices may be disposed on the substrate 110. The individual devices may include various micro electronic devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs) such as complementary metal-insulator-semiconductor transistors (CMOS transistors), system large scale integration (LSIs), image sensors, active devices, passive devices, and the like.

[0014] The substructure 120 may be disposed on the substrate 110 to cover the individual elements. The substructure 120 may further include conductive plugs or wiring layers electrically coupled to the individual elements and / or the substrate 110. In an exemplary embodiment, the substructure 120 may include insulating layers disposed in multiple vertical levels to cover the individual elements and surround the conductive plugs or wiring layers.

[0015] The first lower conductive line LM1 may be covered by the lower structure 120 and may extend, for example, in a first horizontal direction HD1. The first lower conductive line LM1 may also be a connection line for applying power and / or signals to the first electrode structure 130 of the capacitor structure CS. In an exemplary embodiment, the first lower conductive line LM1 may include at least one of TiN, TaN, WN, MoN, NbN, CoN, Ti, Ta, W, Ru, Mo, Nb, Co, and silicides thereof.

[0016] A first electrode structure 130 may be disposed on the lower structure 120. The first electrode structure 130 may include a plurality of first horizontal electrode portions 132, a plurality of first mold insulating layers 134, and a first conductive pillar 136. The plurality of first horizontal electrode portions 132 and the plurality of first mold insulating layers 134 may be alternately disposed in a vertical direction VD1, and the first conductive pillar 136 may penetrate the plurality of first horizontal electrode portions 132 and the plurality of first mold insulating layers 134 and extend in the vertical direction VD1.

[0017] In an exemplary embodiment, the first horizontal electrode portions 132 may include a semiconductor material such as polysilicon, germanium, or silicon germanium, for example, the first horizontal electrode portions 132 may include doped or undoped polysilicon. The first mold insulating layers 134 may include an insulating material, for example, the first mold insulating layers 134 may include at least one of silicon nitride, silicon oxynitride, silicon oxide, and silicon carbon oxide.

[0018] In an example embodiment, the first horizontal electrode portions 132 and the first mold insulating layers 134 may include materials having an etch selectivity with respect to one another. In some examples, the first horizontal electrode portions 132 may include polysilicon and the first mold insulating layers 134 may include silicon nitride.

[0019] The first conductive pillar 136 may be disposed in a first vertical hole 136H penetrating the first horizontal electrode portions 132 and the first mold insulating layers 134, and a bottom of the first conductive pillar 136 may be connected to the first lower conductive line LM1. A portion of a sidewall of the first conductive pillar 136 may be surrounded by the first horizontal electrode portions 132, and the first horizontal electrode portions 132 may be electrically connected to the first lower conductive line LM1 through the first conductive pillar 136. In an exemplary embodiment, the first conductive pillar 136 may include at least one of TiN, TaN, WN, MoN, NbN, CoN, Ti, Ta, W, Ru, Mo, Nb, Co, and silicides thereof.

[0020] Each of the first mold insulating layers 134 includes a plurality of openings OP, and the openings OP may be arranged at positions vertically overlapping each other. For example, the second vertical holes 144H may be formed penetrating the first horizontal electrode units 132 and the first mold insulating layers 134 alternately stacked in the vertical direction VD1, and the openings OP may be formed by laterally removing the portions of the first mold insulating layers 134 exposed by the second vertical holes 144H by a pull-back process. In such a pull-back process, the first horizontal electrode units 132 may remain without being removed or damaged, and in some embodiments, the openings OP may be formed to have a shape concentric with the second vertical holes 144H.

[0021] The second electrode structure 140 may include a plurality of second horizontal electrode portions 142 and a second conductive pillar 144. The plurality of second horizontal electrode portions 142 may be disposed in a plurality of openings OP. Thus, the plurality of second horizontal electrode portions 142 may be surrounded by a plurality of first mold insulating layers 134 in the plurality of openings OP. For example, each of the plurality of second horizontal electrode portions 142 may be disposed in an opening OP of a corresponding first mold insulating layer 134, and each of the plurality of second horizontal electrode portions 142 may be disposed at the same vertical level as the corresponding first mold insulating layer 134. For example, as shown in FIG. 2, the number of layers of the plurality of first mold insulating layers 134 stacked in the vertical direction VD1 is the same as the number of the plurality of second horizontal electrode portions 142 stacked in the vertical direction VD1.

[0022] The second conductive pillar 144 may be disposed in a second vertical hole 144H extending in the vertical direction VD1 while penetrating the plurality of first horizontal electrode portions 132. The second conductive pillar 144 may extend in the vertical direction VD1, and the plurality of second horizontal electrode portions 142 may be disposed on a sidewall of the second conductive pillar 144 to be spaced apart in the vertical direction VD1. The second conductive pillar 144 may have a bottom surface disposed at a lower level than a bottom surface of the lowermost second horizontal electrode portion 142, and a bottom portion of the second conductive pillar 144 may be surrounded by the lower structure 120.

[0023] In an exemplary embodiment, the plurality of second horizontal electrode portions 142 and the second conductive pillar 144 may include at least one of TiN, TaN, WN, MoN, NbN, CoN, Ti, Ta, W, Ru, Mo, Nb, Co, and suicides thereof.

[0024] In an exemplary embodiment, the second conductive pillar 144 may be formed integrally with the plurality of second horizontal electrode units 142. For example, the second conductive pillar 144 may be formed by the same forming process as the plurality of second horizontal electrode units 142. For example, the second conductive pillar 144 and the plurality of second horizontal electrode units 142 may be formed in the same process step by filling the second vertical hole 144H and the plurality of openings OP with a conductive material. For example, in a material layer formed by the conductive material, a portion filling the plurality of openings OP and extending in the horizontal direction may be referred to as the plurality of second horizontal electrode units 142, and a portion filling the second vertical hole 144H and extending in the vertical direction VD1 may be referred to as the second conductive pillar 144. For example, the second conductive pillar 144 may form a material layer continuous with the plurality of second horizontal electrode units 142.

[0025] The capacitor dielectric layer 150 may be interposed between the first electrode structure 130 and the second electrode structure 140. The capacitor dielectric layer 150 may include a first portion P1, a second portion P2, and a third portion P3.

[0026] The capacitor dielectric layer 150 may be made of at least one selected from a high-k dielectric material having a higher dielectric constant than silicon oxide and a ferroelectric material. In some embodiments, the capacitor dielectric layer 150 may be made of hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO ), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), lead zirconate titanate (PZT), strontium tantalate bismuth (SBT), bismuth iron oxide (BFO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), or lead scandium tantalum oxide (PbScTaO).

[0027] The first portion P1 of the capacitor dielectric layer 150 may be disposed on a sidewall of the second vertical hole 144H, for example, between a sidewall of the second conductive pillar 144 and sidewalls of the plurality of first horizontal electrode portions 132. For example, the first portion P1 of the capacitor dielectric layer 150 may extend in the vertical direction VD1 on the sidewall of the second conductive pillar 144.

[0028] The second portion P2 of the capacitor dielectric layer 150 may be disposed in the openings OP, for example, on the upper and bottom surfaces of each of the second horizontal electrode portions 142. For example, the second portion P2 of the capacitor dielectric layer 150 may be interposed between the upper surface of one second horizontal electrode portion 142 and the bottom surface of one first horizontal electrode portion 132 disposed immediately above the one second horizontal electrode portion 142, and may be interposed between the bottom surface of the one second horizontal electrode portion 142 and the upper surface of another one first horizontal electrode portion 132 disposed immediately below the one second horizontal electrode portion 142. The second portion P2 of the capacitor dielectric layer 150 may extend horizontally from the upper and bottom surfaces of each of the second horizontal electrode portions 142.

[0029] The third portion P3 of the capacitor dielectric layer 150 may be disposed in the multiple openings OP and may be interposed between the multiple first mold insulating layers 134 and the multiple second horizontal electrode portions 142. For example, the third portion P3 of the capacitor dielectric layer 150 may contact the side surfaces 142S of the multiple second horizontal electrode portions 142 and extend in the vertical direction VD1.

[0030] In an exemplary embodiment, the first portion P1 of the capacitor dielectric layer 150 may be disposed between a sidewall of the first horizontal electrode portion 132 and a sidewall of the second conductive pillar 144, such that the first portion P1 of the capacitor dielectric layer 150 functions as a first effective capacitor area exhibiting capacitance, and the second portion P2 of the capacitor dielectric layer 150 may be disposed between the alternating first horizontal electrode portions 132 and the alternating second horizontal electrode portions 142, such that the second portion P2 of the capacitor dielectric layer 150 functions as a second effective capacitor area exhibiting capacitance. In an exemplary embodiment, the width of the second horizontal electrode portion 142 in the horizontal direction (e.g., the width in the second horizontal direction HD2) may be larger than the thickness of the second horizontal electrode portion 142 (e.g., the thickness in the vertical direction VD1) and / or the thickness of the first horizontal electrode portion 132 (e.g., the thickness in the vertical direction VD1), such that the area of ​​the second effective capacitor area may be larger than the area of ​​the first effective capacitor area. In an exemplary embodiment, the area of ​​the second effective capacitor region is increased depending on the number of the first horizontal electrode portions 132 and the number of the second horizontal electrode portions 142, and the capacitor structure CS may have a relatively large capacitance.

[0031] In some embodiments, the multiple openings OP of each of the multiple first mold insulating layers 134 may be formed to have at least a portion having a curved shape. For example, for an opening OP arranged in a space between one first mold insulating layer 134, one first horizontal electrode portion 132 arranged immediately above the one first mold insulating layer 134, and another first horizontal electrode portion 132 arranged immediately below the one first mold insulating layer 134, a sidewall portion of the opening OP arranged adjacent to the one first horizontal electrode portion 132 and a sidewall portion of the opening OP arranged adjacent to the other first horizontal electrode portion 132 may have a curved profile, and the first mold insulating layer 134 may include a tail portion 134T corresponding to the curved profile of the opening OP. The first mold insulating layer 134 includes a tail portion 134T, and the capacitor dielectric layer 150 is disposed to conformally cover the tail portion 134T, so that the side surface 142S of the second horizontal electrode portion 142 may have a chamfered shape.

[0032] 3, the openings OP of each of the first molded insulating layers 134 may be formed to have a substantially vertical profile, and the tail portion 134T may not be formed in the first molded insulating layer 134. In such a case, the side surface 142S of the second horizontal electrode portion 142 may also have a substantially vertical profile due to the vertical profile of the openings OP.

[0033] An upper insulating layer 160 may be disposed on the uppermost first horizontal electrode portion 132. A first upper conductive line UM1 and a second upper conductive line UM2 may be disposed in openings extending into the upper insulating layer 160.

[0034] The first upper conductive line UM1 may be connected to the first conductive pillar 136 of the first electrode structure 130 and may extend in the first horizontal direction HD1 on the first conductive pillar 136. The first upper conductive line UM1 may be a connection line for applying power and / or signals to the first electrode structure 130 of the capacitor structure CS.

[0035] The second upper conductive line UM2 may be connected to the second conductive pillar 144 of the second electrode structure 140 and may extend in the first horizontal direction HD1 on the second conductive pillar 144. The second upper conductive line UM2 may be spaced apart from the first upper conductive line UM1. The second upper conductive line UM2 may be a connection line for applying power and / or signals to the second electrode structure 140 of the capacitor structure CS.

[0036] In an exemplary embodiment, the first upper conductive line UM1 and the second upper conductive line UM2 may include at least one of TiN, TaN, WN, MoN, NbN, CoN, Ti, Ta, W, Ru, Mo, Nb, Co, and suicides thereof.

[0037] 2 exemplarily illustrates that a bottom surface of the first conductive pillar 136 is connected to the first lower conductive line LM1 and a top surface of the first conductive pillar 136 is connected to the first upper conductive line UM1. However, in some embodiments, the first conductive pillar 136 may be connected to the first upper conductive line UM1 and the first lower conductive line LM1 may be omitted, or the first conductive pillar 136 may be connected to the first lower conductive line LM1 and the first upper conductive line UM1 may be omitted.

[0038] 4 to 7 are plan views showing various planar layouts of the first electrode structure 130 and the second electrode structure 140. Figures 4 to 7 correspond to horizontal cross-sectional views at a first vertical level LV1 of Figure 2.

[0039] 4, the first vertical hole 136H may have a trench shape extending in a first horizontal direction HD1, and the first conductive pillar 136 disposed in the first vertical hole 136H may extend in the first horizontal direction HD1. For example, the first conductive pillar 136 may have a bar-shaped horizontal cross section extending in the first horizontal direction HD1.

[0040] The second conductive pillar 144 may have a circular horizontal cross section, and the second horizontal electrode portion 142 may have an annular horizontal cross section. For example, the side surface 142S of the second horizontal electrode portion 142 may be concentric with the second conductive pillar 144, and the lateral distance ld in the radial direction from the side surface 142S of the second horizontal electrode portion 142 to the second conductive pillar 144 may be the same.

[0041] 2, a second vertical hole 144H is formed penetrating a plurality of first horizontal electrode units 132 and a plurality of first mold insulating layers 134 alternately stacked in the vertical direction VD1, and a portion of the first mold insulating layers 134 exposed by the second vertical hole 144H is laterally removed by a pull-back process to form a plurality of openings OP. By such a pull-back process, the plurality of openings OP are formed to have a shape concentric with the second vertical hole 144H, and the second horizontal electrode unit 142 filling the interior of the plurality of openings OP may also have a shape concentric with the second conductive pillar 144 disposed inside the second vertical hole 144H.

[0042] 5, the first vertical hole 136H may have a circular horizontal cross-section, the first conductive pillar 136 disposed in the first vertical hole 136H may have a circular horizontal cross-section, the second conductive pillar 144 may have a circular horizontal cross-section, and the second horizontal electrode portion 142 may have an annular horizontal cross-section.

[0043] FIG. 5 illustrates the first conductive pillar 136 being offset from the second conductive pillar 144 along the first horizontal direction HD1; however, unlike what is illustrated in FIG. 5, the second conductive pillar 144 may be located at the same position as the first conductive pillar 136 in the first horizontal direction HD1 and spaced apart from the first conductive pillar 136 in the second horizontal direction HD2.

[0044] 6, the first vertical hole 136H may have a trench shape extending in a first horizontal direction HD1, and the first conductive pillar 136 disposed in the first vertical hole 136H may extend in the first horizontal direction HD1.

[0045] The second conductive pillar 144 may have a bar shape extending in the first horizontal direction HD1. The second horizontal electrode portion 142 may include a first sub-electrode portion 142L arranged on a first side surface 144S1 of the second conductive pillar 144 and a second sub-electrode portion 142R arranged on a second side surface 144S2 of the second conductive pillar 144. For example, the first sub-electrode portion 142L and the second sub-electrode portion 142R may be formed symmetrically with respect to each other.

[0046] In an exemplary embodiment, the width in the second horizontal direction HD2 from the first side 144S1 of the second conductive pillar 144 to the side of the first sub-electrode portion 142L (e.g., the side of the first sub-electrode portion 142L that faces the first mold insulating layer 134) may be the same as the width in the second horizontal direction HD2 from the second side 144S2 of the second conductive pillar 144 to the side of the second sub-electrode portion 142R (e.g., the side of the second sub-electrode portion 142R that faces the first mold insulating layer 134).

[0047] 2, a second vertical hole 144H may be formed penetrating a plurality of first horizontal electrode portions 132 and a plurality of first mold insulating layers 134 alternately stacked in a vertical direction VD1, and a plurality of openings OP may be formed by laterally removing portions of the plurality of first mold insulating layers 134 exposed by the second vertical hole 144H using a pull-back process. The second vertical hole 144H may have a trench shape extending in a first horizontal direction HD1, and at this time, portions of the plurality of first mold insulating layers 134 disposed on both sides of the second vertical hole 144H may be removed using a pull-back process.

[0048] In an exemplary embodiment, the plurality of openings OP may include a first sidewall and a second sidewall, the first sidewall of the plurality of openings OP may be arranged parallel to the first sidewall of the second vertical hole 144H, and the second sidewall of the plurality of openings OP may be arranged parallel to the second sidewall of the second vertical hole 144H. For example, the first sidewall of the plurality of openings OP may be arranged parallel to the first side surface 144S1 of the second conductive pillar 144, and the second sidewall of the plurality of openings OP may be arranged parallel to the second side surface 144S2 of the second conductive pillar 144.

[0049] 7, the first vertical hole 136H may have a circular horizontal cross section, and the first conductive pillar 136 disposed in the first vertical hole 136H may have a circular horizontal cross section. The second conductive pillar 144 may have a bar shape extending in a first horizontal direction HD1. The second horizontal electrode portion 142 may include a first sub-electrode portion 142L disposed on a first side surface 144S1 of the second conductive pillar 144 and a second sub-electrode portion 142R disposed on a second side surface 144S2 of the second conductive pillar 144.

[0050] Fig. 8 is a cross-sectional view showing a semiconductor device 100A according to an exemplary embodiment, and Fig. 9 is an enlarged view of a portion CX1 in Fig. 8.

[0051] 8 and 9, the second vertical hole 144H may have a tapered shape in which the upper width of the second vertical hole 144H is wider than the lower width of the second vertical hole 144H.

[0052] In an exemplary embodiment, a second vertical hole 144H is formed penetrating a plurality of first horizontal electrode portions 132 and a plurality of first mold insulating layers 134 alternately stacked in a vertical direction VD1, and a plurality of openings OP can be formed by laterally removing portions of the plurality of first mold insulating layers 134 exposed by the second vertical hole 144H using a pullback process.

[0053] In the process of forming the second vertical hole 144H, the upper side of the second vertical hole 144H may be more exposed to the etching atmosphere, so that the upper width of the second vertical hole 144H may be wider than the lower width of the second vertical hole 144H.

[0054] In addition, when portions of the first mold insulating layer 134 disposed on both sides of the second vertical hole 144H are removed by the pull-back process, the portion of the first mold insulating layer 134 adjacent to the upper side of the second vertical hole 144H may be more exposed to the etching atmosphere than the portion of the first mold insulating layer 134 adjacent to the lower side of the second vertical hole 144H. In such a case, the amount of etching of the first mold insulating layer 134 adjacent to the upper side of the second vertical hole 144H may be greater than the amount of etching of the first mold insulating layer 134 adjacent to the lower side of the second vertical hole 144H, and the width of the opening OP of the first mold insulating layer 134 adjacent to the upper side of the second vertical hole 144H may be wider than the width of the opening OP of the first mold insulating layer 134 adjacent to the lower side of the second vertical hole 144H.

[0055] In an exemplary embodiment, the horizontal width of one of the plurality of second horizontal electrode units 142 adjacent to an upper side of the second vertical hole 144H may be wider than the horizontal width of another of the plurality of second horizontal electrode units 142 adjacent to a lower side of the second vertical hole 144H. For example, the horizontal width of the second horizontal electrode unit 142 arranged at the first vertical level LV1 may be wider than the horizontal width of the second horizontal electrode unit 142 arranged at a vertical level lower than the first vertical level LV1.

[0056] In an exemplary embodiment, the second vertical hole 144H has a sloping sidewall, and at least a portion of each opening OP may also have a sloping sidewall profile, so that at least a portion of the side surface 142S of the plurality of second horizontal electrode portions 142 disposed in each opening OP may have a sloping profile.

[0057] Fig. 10 is a cross-sectional view showing a semiconductor device 100B according to an exemplary embodiment, and Fig. 11 is an enlarged view of a portion CX1 in Fig. 10.

[0058] 10 and 11, the first electrode structure 130B may include a plurality of first horizontal electrode portions 132, a plurality of first mold insulating layers 134, a first conductive pillar 136, and a conductive electrode layer 138.

[0059] In an exemplary embodiment, the conductive electrode layer 138 may be disposed along the sidewall of the second vertical hole 144H and the inner wall of the opening OP, between the plurality of first horizontal electrode portions 132 and the capacitor dielectric layer 150, and between the plurality of first mold insulating layers 134 and the capacitor dielectric layer 150. For example, the conductive electrode layer 138 may be conformally disposed on the first portion P1, the second portion P2, and the third portion P3 of the capacitor dielectric layer 150. Thus, the capacitor dielectric layer 150 may be interposed between the second electrode structure 140 and the conductive electrode layer 138 without contacting the plurality of first horizontal electrode portions 132 or the plurality of first mold insulating layers 134.

[0060] In an exemplary embodiment, the conductive electrode layer 138 may include at least one of titanium, tantalum, tungsten, molybdenum, niobium, titanium nitride, tantalum nitride, tungsten nitride, molybdenum nitride, and niobium nitride.

[0061] In an exemplary embodiment, a first upper insulating layer 160A may be disposed on the uppermost first horizontal electrode portion 132, and a second upper insulating layer 160B may be disposed on the first upper insulating layer 160A. The second vertical hole 144H may extend in the vertical direction VD1 through the first upper insulating layer 160A, the first horizontal electrode portions 132, and the first mold insulating layers 134, and the conductive electrode layer 138 may be disposed on the second vertical hole 144H and the inner walls of the openings OP, and a portion of the conductive electrode layer 138 may extend on the upper surface of the first upper insulating layer 160A.

[0062] According to an exemplary embodiment, the capacitor structure CS may be a metal-insulator-metal-semiconductor (MIMS) type capacitor including the first horizontal electrode portion 132 and the conductive electrode layer 138 as electrodes of the first electrode structure 130B. For example, the conductive electrode layer 138 may be electrically connected to the first conductive pillar 136 through the plurality of first horizontal electrode portions 132 in contact with the conductive electrode layer 138. The conductive electrode layer 138 may function as an effective electrode area of ​​the first electrode structure 130 together with the plurality of first horizontal electrode portions 132. In addition, the conductive electrode layer 138 may be conformally extended and disposed along the inner walls of the second vertical hole 144H and the opening OP, so that the first portion P1, the second portion P2, and the third portion P3 of the capacitor dielectric layer 150 may all function as effective capacitor areas. The semiconductor device 100B according to the above embodiment may have a relatively high capacitance.

[0063] FIG. 12 is a cross-sectional view illustrating a semiconductor device 100C according to an exemplary embodiment.

[0064] 12, a second lower conductive line LM1A may be disposed on the lower structure 120, and the second lower conductive line LM1A may be spaced apart from the first lower conductive line LM1 and extend in a first horizontal direction HD1. The second lower conductive line LM1A may be electrically connected to a bottom surface of the conductive electrode layer 138.

[0065] FIG. 13 is a cross-sectional view illustrating a semiconductor device 100D according to an exemplary embodiment.

[0066] 13, the first electrode structure 130D may include a plurality of first mold insulating layers 134, a conductive electrode layer 138, and a plurality of second mold insulating layers 139. The plurality of first mold insulating layers 134 and the plurality of second mold insulating layers 139 may be mold structures for defining a three-dimensional shape of the conductive electrode layer 138. The plurality of first mold insulating layers 134 may include a plurality of openings OP, and the conductive electrode layer 138 may be disposed on inner walls of the plurality of openings OP.

[0067] For example, the plurality of first mold insulating layers 134 and the plurality of second mold insulating layers 139 may include materials having an etching selectivity with respect to each other. For example, the plurality of first mold insulating layers 134 and the plurality of second mold insulating layers 139 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, and silicon carbon oxide. For example, the plurality of first mold insulating layers 134 may include silicon nitride, and the plurality of second mold insulating layers 139 may include silicon oxide.

[0068] Each of the first mold insulating layers 134 includes a plurality of openings OP, and the openings OP may be arranged at positions vertically overlapping each other. For example, the second vertical holes 144H may be formed penetrating the first mold insulating layers 134 and the second mold insulating layers 139 alternately stacked in the vertical direction VD1, and the openings OP may be formed by laterally removing the portions of the first mold insulating layers 134 exposed by the second vertical holes 144H by a pull-back process. In such a pull-back process, the second mold insulating layers 139 may remain without being removed or damaged, and in some embodiments, the openings OP may be formed to have a shape concentric with the second vertical holes 144H.

[0069] The second electrode structure 140 may include a plurality of second horizontal electrode portions 142 and a second conductive pillar 144. The second conductive pillar 144 may extend in a vertical direction VD1 within the second vertical hole 144H, and the plurality of second horizontal electrode portions 142 may be disposed to extend in the horizontal direction from a sidewall of the second conductive pillar 144.

[0070] A conductive electrode layer 138 and a capacitor dielectric layer 150 may be sequentially formed in the openings OP, and the remaining portions of the openings OP may be filled with the second horizontal electrode portions 142. As a result, an effective capacitor region having a three-dimensional structure may be defined in the openings OP, and the area of ​​the effective capacitor region may be relatively large.

[0071] In an exemplary embodiment, the planar shape of the second electrode structure 140 may be similar to that described with reference to FIGS. 4 to 7. In some embodiments, as described with reference to FIGS. 4 and 5, the second conductive pillar 144 may have a circular horizontal cross-sectional shape, and the plurality of second horizontal electrode portions 142 may have an annular horizontal cross-sectional shape concentric with the second conductive pillar 144. In some embodiments, as described with reference to FIGS. 6 and 7, the second conductive pillar 144 may have a bar-shaped horizontal cross-section extending in the first horizontal direction HD1, and the plurality of second horizontal electrode portions 142 may include a first sub-electrode portion 142L ( FIG. 6 ) arranged on a first sidewall of the second conductive pillar 144 and a second sub-electrode portion 142R ( FIG. 6 ) arranged on a second sidewall of the second conductive pillar 144.

[0072] A second lower conductive line LM1A may be disposed on the lower structure 120 and may extend in a first horizontal direction HD1. The second lower conductive line LM1A may be electrically connected to a bottom surface of the conductive electrode layer 138.

[0073] FIG. 14 is a cross-sectional view illustrating a semiconductor device 100E according to an exemplary embodiment.

[0074] 14, the lower structure 120 may have a textured upper surface, for example, including a concave-convex surface. The first horizontal electrode portions 132 and the first mold insulating layers 134 may have concave-convex surfaces having a shape conforming to the concave-convex surface of the lower structure 120, and the second horizontal electrode portions 142 disposed in the openings OP of the first mold insulating layers 134 may also have concave-convex surfaces having a shape conforming to the concave-convex surface of the first horizontal electrode portions 132. A capacitor dielectric layer 150 may be conformally interposed between the concave-convex surfaces of the first horizontal electrode portions 132 and the concave-convex surfaces of the second horizontal electrode portions 142.

[0075] In an exemplary embodiment, the uneven surface of the lower structure 120 may be formed by forming a mask pattern on the lower structure 120 and removing an upper portion of the lower structure 120 using the mask pattern as an etching mask. Then, the first horizontal electrode units 132 and the first mold insulating layers 134 may be alternately and sequentially formed on the lower structure 120 having the uneven surface, so that the first horizontal electrode units 132 and the first mold insulating layers 134 may be formed in a shape having an uneven surface.

[0076] In another exemplary embodiment, the lower structure 120 has a flat upper surface, and a template layer having an uneven surface is further formed between the lower structure 120 and the lowest first horizontal electrode portion 132, and a plurality of first horizontal electrode portions 132 and a plurality of first mold insulating layers 134 are alternately and sequentially formed on the template layer, so that the plurality of first horizontal electrode portions 132 and the plurality of first mold insulating layers 134 can be formed into a shape having an uneven surface.

[0077] According to an exemplary embodiment, the plurality of first horizontal electrode portions 132 and the plurality of second horizontal electrode portions 142 have uneven surfaces, thereby increasing the area of ​​the effective capacitor area and allowing the capacitor structure CS to have a relatively high capacitance.

[0078] 15 is a cross-sectional view showing a semiconductor device 200 according to an exemplary embodiment. In FIG. 15, the same reference numerals as in FIGS. 1 to 14 denote the same components.

[0079] Referring to FIG. 15, the semiconductor device 200 may be a global shutter type image sensor including a plurality of photoelectric conversion regions PD formed in a semiconductor substrate 210 and a capacitor structure CS arranged on a front face of the semiconductor substrate 210.

[0080] The transfer gate TG may be disposed to extend within the semiconductor substrate 210 and configured to control the photoelectrons stored in the photoelectric conversion region PD. A pixel transistor may be further formed on the front surface of the semiconductor substrate 210, and the pixel transistor may be electrically connected to a capacitor structure CS, so that charges transferred from the photoelectric conversion region PD of each pixel region may be stored in the capacitor structure CS.

[0081] A front wiring layer FL and a front insulating layer FI may be disposed on the front surface of the semiconductor substrate 210 to cover the capacitor structure CS, and a color filter CF and a microlens ML may be disposed on the rear surface of the semiconductor substrate 210.

[0082] The capacitor structure CS includes a first electrode structure 130, a second electrode structure 140, and a capacitor dielectric layer 150, and the structure of the capacitor structure CS may include any one of those described with reference to Figures 1 to 15. In an exemplary embodiment, the capacitor structure CS may be formed in a plurality of pieces, and the plurality of capacitor structures CS may be arranged to correspond to a plurality of pixel regions formed on the semiconductor substrate 210, respectively.

[0083] According to an exemplary embodiment, the capacitor structure CS has a relatively large capacitance even in a relatively small area, so that a global shutter type image sensor including the capacitor structure CS can have high resolution and excellent image quality.

[0084] FIG. 16 is a cross-sectional view illustrating a semiconductor device 200A according to an exemplary embodiment.

[0085] 16, the capacitor structure CS may be disposed on a plurality of pixels formed on the semiconductor substrate 210. For example, the first electrode structure 130 may be disposed extending in the horizontal direction so as to vertically overlap a plurality of pixels (e.g., so as to vertically overlap a plurality of photoelectric conversion regions PD), and the second electrode structure 140 may be disposed passing through the first electrode structure 130. For example, the first electrode structure 130 may be a common electrode and may be electrically connected in common to a plurality of pixel regions. A plurality of second electrode structures 140 may be formed, and at least one second electrode structure 140 may be electrically connected to each pixel region.

[0086] Although an image sensor including the capacitor structure CS has been exemplarily described in FIG. 15 and FIG. 16, in other embodiments, the capacitor structure CS may be integrated into an integrated circuit device including a memory device and / or a logic device. In some exemplary embodiments, the capacitor structure CS may be included in an integrated circuit device including a logic device and used as an element control circuit such as a power regulator for the logic device. For example, the capacitor structure CS may have a relatively large capacitance to reduce noise in a power line and / or a signal line of the integrated circuit device. In some exemplary embodiments, the capacitor structure CS may be included in an electronic system such as a mobile electronic device and used as a backup power source such as a battery back-up random access memory (RAM). For example, the capacitor structure CS may have a relatively large capacitance to allow stable operation of the system even if a momentary power interruption occurs in the electronic system such as a mobile electronic device.

[0087] 17A, 17B, 18A, 18B, 19A, 19B, 20A, 20B, 21, 22A, 22B, 23A, 23B, and 24 are schematic diagrams showing a manufacturing method of the semiconductor device 100 according to an exemplary embodiment. 17A, 18A, 19A, 20A, 21, 22A, 23A, and 24 are cross-sectional views illustrated according to a process sequence, and 17B, 18B, 19B, 20B, 22B, and 23B are horizontal cross-sectional views at a first vertical level LV1 of 17A, 18A, 19A, 20A, 22A, and 23A.

[0088] 17A and 17B, a lower structure 120 may be formed on a substrate 110, and a first lower conductive line LM1 may be formed surrounded by the lower structure 120 and extending in a first horizontal direction HD1.

[0089] A plurality of first horizontal electrode portions 132 and a plurality of first mold insulating layers 134 may be alternately formed on the lower structure 120 .

[0090] In an exemplary embodiment, the first horizontal electrode portions 132 may be formed using a semiconductor material such as polysilicon, germanium, or silicon germanium, and the first mold insulating layers 134 may be formed using at least one insulating material selected from the group consisting of silicon nitride, silicon oxynitride, silicon oxide, and silicon carbon oxide. In an exemplary embodiment, the first horizontal electrode portions 132 and the first mold insulating layers 134 may be formed using materials having an etching selectivity with respect to each other.

[0091] Then, an upper insulating layer 160 may be formed on the uppermost first horizontal electrode portion 132 .

[0092] 18A and 18B, a mask pattern may be formed on the upper insulating layer 160, and the mask pattern may be used as an etching mask to remove portions of the first horizontal electrode portions 132 and the first mold insulating layers 134 to form second vertical holes 144H. The second vertical holes 144H may be disposed at a lower level than the lowermost first horizontal electrode portion 132 and may have a bottom portion covered by the lower structure 120.

[0093] In an exemplary embodiment, the second vertical holes 144H may have a circular horizontal cross-section, as shown in Fig. 18B. In another embodiment, the second vertical holes 144H may have a bar-shaped horizontal cross-section extending in the first horizontal direction HD1, as shown in Fig. 7.

[0094] 18A exemplarily illustrates that the second vertical hole 144H has a vertical sidewall profile, and the upper width of the second vertical hole 144H is formed to be substantially the same as the lower width of the second vertical hole 144H. In some embodiments, depending on the etching process conditions, the upper side of the second vertical hole 144H is more exposed to the etching atmosphere, and the upper width of the second vertical hole 144H is formed to be wider than the lower width of the second vertical hole 144H. In such a case, the second vertical hole 144H may have a sloped sidewall, as described with reference to FIGS. 8 and 9.

[0095] 19A and 19B, portions of the first mold insulating layers 134 may be removed through exposed sidewalls of the second vertical holes 144H to form a plurality of openings OP. In an exemplary embodiment, in the process of removing the portions of the first mold insulating layers 134, the plurality of first horizontal electrode portions 132 may remain substantially unremoved.

[0096] In an exemplary embodiment, the process for removing a portion of the plurality of first mold insulating layers 134 may be referred to as a pull-back process. In the pull-back process, an etching recipe may be used in which the etching rate of the plurality of first horizontal electrode portions 132 is relatively slow, while the etching rate of the plurality of first mold insulating layers 134 is relatively fast. In an exemplary embodiment, in the pull-back process, an etching recipe may be used in which the etching rate of the plurality of first horizontal electrode portions 132 is relatively slow, while the etching rate of the plurality of first mold insulating layers 134 is relatively fast. 3 PO 4 ) may be used.

[0097] The openings OP may be spaces defined between the first horizontal electrode portions 132 after portions of the first mold insulating layers 134 are removed. In an exemplary embodiment, the openings OP may have an annular horizontal cross section surrounding the second vertical hole 144H. The openings OP may have a relatively wide width in the lateral direction. The openings OP may be concentric with the second vertical hole 144H, and for example, the lateral distances ld from the sidewalls of the openings OP to the second vertical hole 144H in the radial direction may be the same.

[0098] In an exemplary embodiment, as shown in Fig. 19B, the second vertical hole 144H may have a circular horizontal cross section, and the plurality of openings OP may have an annular horizontal cross section concentric with the second vertical hole 144H. In another embodiment, as shown in Fig. 7, the second vertical hole 144H may have a bar-shaped horizontal cross section extending in the first horizontal direction HD1, and the plurality of openings OP may include a first opening OP1 disposed on a first side of the second vertical hole 144H and a second opening OP2 disposed on a second side of the second vertical hole 144H.

[0099] 20A and 20B, a capacitor dielectric layer 150 may be conformally formed in the second vertical hole 144H and in the multiple openings OP, and a second electrode layer 140L may be formed on the capacitor dielectric layer 150 to fill the second vertical hole 144H and the multiple openings OP.

[0100] A portion of the second electrode layer 140L fills the spaces between the plurality of first horizontal electrode portions 132, and a capacitor dielectric layer 150 may be interposed between the second electrode layer 140L and the plurality of first horizontal electrode portions 132.

[0101] In an exemplary embodiment, the second electrode layer 140L may include at least one of TiN, TaN, WN, MoN, NbN, CoN, Ti, Ta, W, Ru, Mo, Nb, Co, and suicides thereof.

[0102] 21 , the capacitor dielectric layer 150 and the second electrode layer 140L disposed on the upper surface of the upper insulating layer 160 may be removed. Here, a portion of the second electrode layer 140L filling the interiors of the plurality of openings OP may be referred to as a second horizontal electrode portion 142, and a portion of the second electrode layer 140L filling the second vertical hole 144H and extending in the vertical direction VD1 may be referred to as a second conductive pillar 144.

[0103] 22A and 22B, a mask pattern may be formed on the upper insulating layer 160, and the mask pattern may be used as an etching mask to remove portions of the first horizontal electrode portions 132 and the first mold insulating layers 134 to form a first vertical hole 136H. The first vertical hole 136H may be disposed at a lower level than the lowermost first horizontal electrode portion 132, and an upper surface of the first lower conductive line LM1 may be exposed at the bottom of the first vertical hole 136H.

[0104] In an exemplary embodiment, the first vertical holes 136H may have a bar-shaped horizontal cross-section extending in a first horizontal direction HD1, as shown in Fig. 22B. In another embodiment, the first vertical holes 136H may have a circular horizontal cross-section, as shown in Fig. 5.

[0105] 23A and 23B, a first conductive pillar 136 may be formed in the first vertical hole 136H. The first conductive pillar 136 may include at least one of TiN, TaN, WN, MoN, NbN, CoN, Ti, Ta, W, Ru, Mo, Nb, Co, and silicides thereof.

[0106] 24, a portion of the upper insulating layer 160 may be removed to form a line trench, and a first upper conductive line UM1 and a second upper conductive line UM2 may be formed in the line trench. The first upper conductive line UM1 may be electrically connected to the first conductive pillar 136, and the second upper conductive line UM2 may be electrically connected to the second conductive pillar 144.

[0107] Through the above-described steps, the semiconductor device 100 can be formed.

[0108] According to an exemplary embodiment, a plurality of openings OP may be formed by removing portions of the first mold insulating layers 134 through a pull-back process, thereby obtaining a three-dimensional capacitor structure CS having a relatively large effective capacitor area.

[0109] 25-28 are schematic diagrams illustrating a method for manufacturing a semiconductor device 100D according to an exemplary embodiment.

[0110] 25, a plurality of first mold insulating layers 134 and a plurality of second mold insulating layers 139 may be alternately formed on a lower structure 120. As shown in FIG.

[0111] In an exemplary embodiment, the plurality of first mold insulating layers 134 and the plurality of second mold insulating layers 139 may include materials having an etch selectivity with respect to one another. For example, the plurality of first mold insulating layers 134 and the plurality of second mold insulating layers 139 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, and silicon carbon oxide. For example, the plurality of first mold insulating layers 134 may include silicon nitride, and the plurality of second mold insulating layers 139 may include silicon oxide.

[0112] Thereafter, a first upper insulating layer 160A may be formed on the uppermost second mold insulating layer 139.

[0113] 26, a portion of the plurality of first mold insulating layers 134 and the plurality of second mold insulating layers 139 may be removed to form second vertical holes 144H.

[0114] Thereafter, portions of the first mold insulating layers 134 may be removed through the exposed sidewalls of the second vertical holes 144H to form a plurality of openings OP. In an exemplary embodiment, in the process for removing portions of the first mold insulating layers 134, the second mold insulating layers 139 may be left substantially unremoved.

[0115] In an exemplary embodiment, the process for removing a portion of the first mold insulating layers 134 may be referred to as a pull-back process. In the pull-back process, an etching recipe may be used in which the etching rate of the second mold insulating layers 139 is relatively slow, while the etching rate of the first mold insulating layers 134 is relatively fast. In an exemplary embodiment, in the pull-back process, phosphoric acid (H 3 PO 4 ) may be used.

[0116] The second lower conductive line LM1A may be exposed at the bottom of the second vertical hole 144H. For example, the upper surface of the second lower conductive line LM1A may be exposed in the pull-back process. Alternatively, the upper surface of the second lower conductive line LM1A may be covered by the lower structure 120 in the pull-back process and not exposed at the bottom of the second vertical hole 144H, and an additional etching process may be used after the pull-back process to expose the upper surface of the second lower conductive line LM1A.

[0117] Referring to FIG. 27, a conductive electrode layer 138 and a capacitor dielectric layer 150 may be sequentially formed in the second vertical hole 144H and in the multiple openings OP, and a second electrode layer 140L may be formed on the capacitor dielectric layer 150 to fill the second vertical hole 144H and the multiple openings OP.

[0118] 28, the conductive electrode layer 138, the capacitor dielectric layer 150, and the second electrode layer 140L disposed on the upper surface of the first upper insulating layer 160A may be removed. Here, a portion of the second electrode layer 140L disposed inside the plurality of openings OP may be referred to as a second horizontal electrode portion 142, and a portion of the second electrode layer 140L filling the second vertical hole 144H and extending in the vertical direction VD1 may be referred to as a second conductive pillar 144.

[0119] 13, a second upper insulating layer 160B covering the second conductive pillar 144 may be formed on the first upper insulating layer 160A. A portion of the second upper insulating layer 160B may then be removed to form a line trench, and a second upper conductive line UM2 may be formed in the line trench.

[0120] Through the above-described steps, the semiconductor device 100D can be formed.

[0121] According to an exemplary embodiment, a plurality of openings OP may be formed by removing portions of the first mold insulating layers 134 through a pull-back process, thereby obtaining a three-dimensional capacitor structure CS having a three-dimensional structure and a relatively large effective capacitor area.

[0122] As described above, the drawings and the specification disclose exemplary embodiments. In this specification, specific terms are used to describe the embodiments, but they are used only for the purpose of describing the technical idea of ​​the present disclosure, and are not used to limit the meaning or the scope of the present disclosure described in the claims. Therefore, a person having ordinary skill in the art will understand that various modifications and other equivalent embodiments are possible. Therefore, the true technical scope of protection of the present disclosure is defined by the technical idea of ​​the claims. [Explanation of symbols]

[0123] 100 Semiconductor device 130 First electrode structure 132 1st horizontal electrode section 134 First molded insulating layer 136 First conductive pillar 140 Second electrode structure 142 2nd horizontal electrode section 144 Second conductive pillar 150 Capacitor Dielectric Layer CS Capacitor Structure

Claims

1. A capacitor structure disposed on a substrate, the capacitor structure comprising: a first electrode structure including: a plurality of first horizontal electrode portions spaced apart from each other in a first direction perpendicular to an upper surface of the substrate; and a first conductive pillar connected to each of the first horizontal electrode portions and extending in the first direction; a second electrode structure including: a second conductive pillar penetrating the plurality of first horizontal electrode portions and extending in the first direction; and a plurality of second horizontal electrode portions spaced apart from each other in the first direction on a side wall of the second conductive pillar and alternately arranged with the plurality of first horizontal electrode portions; a capacitor dielectric layer disposed between the sidewall of the second conductive pillar and the plurality of first horizontal electrode portions, and on the top surface, side surface and bottom surface of each of the plurality of second horizontal electrode portions.

2. the second conductive pillar has a circular planar shape, The semiconductor device according to claim 1 , wherein each of the second horizontal electrode portions has an annular planar shape surrounding the second conductive pillar.

3. 3. The semiconductor device according to claim 2, wherein a side surface of at least one of the plurality of second horizontal electrode portions forms a concentric circle with a side surface of a portion of the second conductive pillar arranged at the same level as the at least one second horizontal electrode portion.

4. The first conductive pillar extends in a first horizontal direction; The semiconductor device according to claim 1 , wherein the second conductive pillar extends in the first horizontal direction and is spaced apart from the first conductive pillar in a second horizontal direction.

5. Each of the plurality of second horizontal electrode portions is a first sub-electrode portion disposed on a first side surface of the second conductive pillar; a second sub-electrode portion disposed on a second side surface of the second conductive pillar opposite to the first side surface, 5. The semiconductor device according to claim 4, wherein a width of the first sub-electrode portion in the second horizontal direction is the same as a width of the second sub-electrode portion in the second horizontal direction.

6. The first electrode structure is a plurality of mold insulating layers alternately arranged with the plurality of first horizontal electrode portions; Each of the mold insulating layers includes a plurality of openings at positions where the mold insulating layers overlap each other in the first direction, 2. The semiconductor device according to claim 1, wherein the second horizontal electrode portions are disposed in the openings.

7. 7. The semiconductor device of claim 6, wherein the portions of the capacitor dielectric layer disposed on the side of each of the second horizontal electrodes are disposed within corresponding ones of the openings in the mold insulating layers.

8. 7. The semiconductor device of claim 6, wherein a portion of the capacitor dielectric layer disposed on the side of each of the second horizontal electrode portions contacts a corresponding one of the mold insulating layers.

9. the plurality of mold insulating layers include silicon nitride; 7. The semiconductor device of claim 6, wherein the first horizontal electrodes include doped or undoped polysilicon.

10. The first electrode structure is a conductive electrode layer interposed between the first horizontal electrode portions and the capacitor dielectric layer and between the mold insulating layers and the capacitor dielectric layer, 7. The semiconductor device of claim 6, wherein the conductive electrode layer includes at least one of titanium, tantalum, tungsten, molybdenum, niobium, titanium nitride, tantalum nitride, tungsten nitride, molybdenum nitride, and niobium nitride.

11. the plurality of first horizontal electrode portions include a first uneven surface; 2 . The semiconductor device of claim 1 , wherein the second horizontal electrode portions facing the first horizontal electrode portions include a second uneven surface conforming to a shape of the first uneven surface.

12. A capacitor structure disposed on a substrate, the capacitor structure comprising: a first electrode structure including: a plurality of first horizontal electrode portions spaced apart from each other in a first direction perpendicular to an upper surface of the substrate; a plurality of mold insulating layers alternately arranged with the first horizontal electrode portions and including a plurality of openings at positions overlapping each other in the first direction; and a first conductive pillar connected to each of the first horizontal electrode portions and extending in the first direction; a second electrode structure including: a second conductive pillar penetrating the plurality of first horizontal electrode portions and extending in the first direction; and a plurality of second horizontal electrode portions spaced apart from each other in the first direction on side walls of the second conductive pillar and respectively disposed in the plurality of openings; a capacitor dielectric layer disposed between the first electrode structure and the second electrode structure, the capacitor dielectric layer including portions disposed on the top surface, side surface and bottom surface of each of the plurality of second horizontal electrode portions within the plurality of openings.

13. The semiconductor device according to claim 12 , wherein the second horizontal electrode portions and the first horizontal electrode portions are arranged alternately.

14. the second conductive pillar has a circular planar shape, The semiconductor device according to claim 12 , wherein each of the plurality of openings has an annular planar shape surrounding the second conductive pillar.

15. The semiconductor device according to claim 14 , wherein a side surface of each of the plurality of openings forms a circle concentric with the side wall of the second conductive pillar.

16. The first conductive pillar extends in a first horizontal direction; The semiconductor device of claim 12 , wherein the second conductive pillar extends in the first horizontal direction and is spaced apart from the first conductive pillar in a second horizontal direction.

17. Each of the plurality of second horizontal electrode portions is a first sub-electrode portion disposed on a first side surface of the second conductive pillar; a second sub-electrode portion disposed on a second side surface of the second conductive pillar opposite to the first side surface, 17. The semiconductor device according to claim 16, wherein a width of the first sub-electrode portion in the second horizontal direction is the same as a width of the second sub-electrode portion in the second horizontal direction.

18. The first electrode structure is a conductive electrode layer interposed between the first horizontal electrode portions and the capacitor dielectric layer and between the mold insulating layers and the capacitor dielectric layer, 13. The semiconductor device of claim 12, wherein the conductive electrode layer includes at least one of titanium, tantalum, tungsten, molybdenum, niobium, titanium nitride, tantalum nitride, tungsten nitride, molybdenum nitride, and niobium nitride.

19. a semiconductor substrate having a plurality of pixel regions defined therein, each pixel region including a photoelectric conversion region; a capacitor structure disposed on the semiconductor substrate; The capacitor structure includes: a first electrode structure including: a plurality of first horizontal electrode portions spaced apart from each other in a first direction perpendicular to an upper surface of the semiconductor substrate; and a first conductive pillar connected to each of the first horizontal electrode portions and extending in the first direction; a second electrode structure including: a second conductive pillar penetrating the plurality of first horizontal electrode portions and extending in the first direction; and a plurality of second horizontal electrode portions spaced apart from each other in the first direction on a side wall of the second conductive pillar and alternately arranged with the plurality of first horizontal electrode portions; a capacitor dielectric layer disposed between the sidewall of the second conductive pillar and the plurality of first horizontal electrode portions, and on the top surface, side surface and bottom surface of each of the plurality of second horizontal electrode portions.

20. The first electrode structure is a plurality of mold insulating layers alternately arranged with the plurality of first horizontal electrode portions; Each of the mold insulating layers includes a plurality of openings at positions where the mold insulating layers overlap each other in the first direction, 20. The semiconductor device according to claim 19, wherein the second horizontal electrode portions are disposed in the openings.

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