Semiconductor device

Abstract

To provide a semiconductor device of which the avalanche breakdown voltage is improved by suppressing the increase of an electric field by reducing a hole density in a trench end in the semiconductor device.SOLUTION: In an outer peripheral part of a trench 7, which is positioned in an outer peripheral region 40 of a semiconductor device, in an extension direction, an extension part 10a of a lower electrode 10, which is extended to the outside of an upper electrode 9, in the lower electrode is further extended to a top face of a semiconductor substrate so as to cover an end of the upper electrode 9 and a width of the trench 7 is made most narrow in a trench end 7a.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device equipped with a MOSFET having a split gate structure in which an electrode inside a trench is divided into upper and lower parts. The invention described in Patent Document 1 improves the breakdown voltage at the end of the trench located in the outer periphery by widening the width of the trench in the outer periphery of the semiconductor device. It also describes that the invention can be applied even when the semiconductor switching element is an IGBT other than a MOSFET. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-128948 Summary of the Invention [Problem to be solved by the invention]

[0004] The semiconductor device described in Patent Document 1 does not sufficiently consider the movement of carriers. For example, an increase in hole density at the trench end during turn-off switching can be considered. Specifically, holes flow into the trench end at high density during turn-off switching, increasing the hole density at the trench end. Then, as the hole density increases, the space charge increases, increasing the electric field and causing an avalanche. This phenomenon occurs particularly conspicuously in IGBTs (Insulated Gate Bipolar Transistors) in bipolar devices. When the invention described in Patent Document 1 is applied to an IGBT, the width of the trench becomes wider at the trench end located at the outer periphery, narrowing the area between the trenches and making it easy for the hole density to increase. Therefore, as the hole density increases, the electric field increases and the avalanche breakdown voltage decreases.

[0005] The present disclosure has been made to solve the above-mentioned problems, and aims to provide a semiconductor device in which the hole density at the end of the trench is reduced to suppress an increase in the electric field and improve the avalanche breakdown voltage. [Means for solving the problem]

[0006] A semiconductor device according to the present disclosure is a semiconductor device having an active region in which a semiconductor switching element is configured, and an outer periphery region in which a gate electrode is provided outside the active region, the semiconductor switching element comprising: a first conductivity type drift layer, a second conductivity type base layer disposed on an upper surface side of the first conductivity type drift layer, a first conductivity type source layer disposed on the upper surface side of the second conductivity type base layer, a second conductivity type collector layer disposed on a lower surface side of the first conductivity type drift layer, an emitter electrode electrically connected to the first conductivity type source layer, and a collector electrode electrically connected to the second conductivity type collector layer, the range from an upper surface of the first conductivity type source layer to a lower surface of the second conductivity type collector layer being a semiconductor substrate, the outer periphery region, a lower electrode, a boundary insulating film, and an upper electrode are stacked in that order within the trench, with an insulating film interposed therebetween, to form a two-stage structure, the lower electrode being electrically connected to the emitter electrode, and the upper electrode being electrically connected to the gate electrode, and at the outer periphery of the trench in the extension direction located in the outer periphery region, an extension portion of the lower electrode that extends further outward than the upper electrode is further extended to an upper surface of the semiconductor substrate so as to cover an end of the upper electrode, and the width of the trench is narrowest at the end of the trench. Effect of the Invention

[0007] According to the semiconductor device according to the present disclosure, the hole density at the end of the trench is reduced, thereby suppressing an increase in the electric field and improving the avalanche breakdown voltage. [Brief description of the drawings]

[0008] [Figure 1] 1 is an overall plan view of a semiconductor device according to a first embodiment. [Diagram 2] 2 is a cross-sectional view of the semiconductor device according to the first embodiment taken along line AA in FIG. [Diagram 3] 2 is a cross-sectional view of the semiconductor device according to the first embodiment taken along line BB in FIG. [Figure 4] 2 is an enlarged plan view of the semiconductor device according to the first embodiment at C in FIG. [Diagram 5] 2 is an enlarged plan view of the outer periphery of a trench in the semiconductor device according to the first embodiment. FIG. [Figure 6] 11 is an enlarged plan view of the outer periphery of a trench in a semiconductor device according to a second embodiment. FIG. [Figure 7] 11 is an enlarged plan view of the outer periphery of a trench in a semiconductor device according to a second embodiment. FIG. [Figure 8] 13 is an enlarged plan view of the outer periphery of a trench in a semiconductor device according to a third embodiment. FIG. [Figure 9] 13 is an enlarged plan view of the outer periphery of a trench in a semiconductor device according to a third embodiment. FIG. [Figure 10] 13 is an enlarged plan view of the outer periphery of a trench in a semiconductor device according to a third embodiment. FIG. [Figure 11] 13 is an enlarged plan view of the outer periphery of a trench in a semiconductor device according to a fourth embodiment. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] <Introduction> In the following description, n-type and p-type indicate the conductivity types of semiconductors. In this disclosure, the first conductivity type is described as n-type and the second conductivity type is described as p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type. -The n-type impurity concentration is lower than that of the n-type. + The term p-type indicates that the impurity concentration is higher than that of n-type. - The impurity concentration is lower than that of p-type, and p + The n-type indicates that the impurity concentration is higher than that of the p-type.

[0010] Also, for ease of explanation, in the following, as shown in Figures 1 to 11, the width direction of semiconductor device 100 is defined as the x direction, the depth direction of semiconductor device 100 that intersects with the x direction is defined as the y direction, and the thickness direction or depth direction of semiconductor device 100, i.e., the normal direction to the xy plane, is defined as the z direction.

[0011] In addition, the drawings are shown diagrammatically, and the size and positional relationship of the images shown in different drawings are not necessarily described accurately and may be changed as appropriate. In addition, in the following description, similar components are illustrated with the same reference numerals, and their names and functions are also the same. Therefore, detailed description thereof may be omitted.

[0012] Embodiment 1 The first embodiment will be described below with reference to the drawings. FIG. 1 is a plan view showing a schematic top view of the entire semiconductor device 100 according to the first embodiment. As shown in FIG. 1, the semiconductor device 100 includes an active region 30 in which a semiconductor switching element is configured, and an outer peripheral region 40 around the active region 30. Furthermore, a trench 7 is provided so as to extend in the Y direction from the active region 30 toward the outer peripheral region 40. The Y direction is the extension direction of the trench 7. Furthermore, a plurality of trenches 7 are provided so as to be adjacent to each other in the X direction, which is a direction perpendicular to the extension direction of the trench 7. In FIG. 1, the number of trenches 7 is shown as five, but the number of trenches 7 is not limited to this. Furthermore, in this embodiment, a semiconductor device having a split gate trench structure and using an insulated gate bipolar transistor (hereinafter abbreviated as IGBT) as a semiconductor switching element will be described as an example. Below, a detailed structure of the semiconductor device 100 of this embodiment will be described with reference to FIGS. 2 to 5.

[0013] FIG. 2 is a cross-sectional view in a direction perpendicular to the extension direction of the trench 7 in the active region 30 of the semiconductor device 100 according to the first embodiment. FIG. 2 shows a cross-section taken along dashed line A-A in FIG. 1. FIG. 3 is a cross-sectional view in a direction parallel to the extension direction of the trench 7 according to the first embodiment. FIG. 3 shows a cross-section taken along dashed line BB in FIG. 1. FIG. 4 is a plan view of the outer periphery of the trench 7 of the semiconductor device 100 according to the first embodiment. FIG. 4 shows an enlarged view of region C shown in FIG. 1 and a plan view taken along dotted line C in FIG. 2. FIG. 5 is a plan view showing a modified example of the trench 7 shown in FIG. 4.

[0014] First, a cross-sectional configuration of the semiconductor device 100 will be described with reference to Figures 2 and 3. As shown in Figure 2, the semiconductor device 100 has a semiconductor switching element configured in an active region 30. The semiconductor switching element has n - n-type drift layer 1, n-type carrier accumulation layer 2, p-type base layer 3, n +The semiconductor device includes a n-type source layer 4, an n-type buffer layer 5, a p-type collector layer 6, a trench 7, an upper insulating film 8a, a lower insulating film 8b, an upper electrode 9, a lower electrode 10, a boundary insulating film 11, an interlayer insulating film 12, an emitter electrode 13, and a collector electrode 14. In addition, as shown in FIG. 3, a gate electrode 15 is provided in the peripheral region 40.

[0015] The first main surface of the semiconductor substrate in the active region 30 is n + The p-type source layer 4 and + The first main surface corresponds to the surface (upper surface) of the p-type contact layer. The first main surface is the upper surface of the semiconductor substrate. The second main surface of the semiconductor substrate corresponds to the surface (lower surface) of the p-type collector layer 6. The second main surface is the surface opposite to the first main surface, which is the lower surface of the semiconductor substrate. In FIG. 2, the semiconductor substrate is + Type source layer 4 and p + This corresponds to the range from the upper surface of the p-type contact layer to the lower surface of the p-type collector layer 6 .

[0016] n - The n-type drift layer 1 is made of a semiconductor substrate. - The n-type drift layer 1 is provided between a first main surface and a second main surface of a semiconductor substrate. - The n-type drift layer 1 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is preferably 1.0E+12 / cm 3 More than 1.0E+15 / cm 3 The following is the result.

[0017] The n-type carrier accumulation layer 2 is - The n-type carrier accumulation layer 2 is provided on the first main surface side of the semiconductor substrate with respect to the n-type drift layer 1. The n-type carrier accumulation layer 2 is a semiconductor layer having an n-type impurity such as arsenic or phosphorus, and the concentration of the n-type impurity is preferably 1.0E+13 / cm 3 More than 1.0E+17 / cm 3 The reason is as follows. By providing the n-type carrier accumulation layer 2, it is possible to reduce the current loss when a current flows. Note that the semiconductor device 100 does not have the n-type carrier accumulation layer 2 and has n -The n-type drift layer 1 may be provided, and the n-type carrier accumulation layer 2 and the n - The combination of the first drift layer and the second drift layer 1 may be defined as the drift layer.

[0018] The p-type base layer 3 is provided on the first main surface side of the semiconductor substrate with respect to the n-type carrier accumulation layer 2. The p-type base layer 3 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is preferably 1.0E+12 / cm 3 More than 1.0E+19 / cm 3 The p-type base layer 3 is in contact with the upper insulating film 8a of the trench 7. When a gate drive voltage is applied to the upper electrode 9, a channel is formed in the p-type base layer 3.

[0019] n + The n-type source layer 4 is provided on the first main surface side of the semiconductor substrate with respect to the p-type base layer 3. + The n-type source layer 4 is selectively provided above the p-type base layer 3 as a surface layer of the semiconductor substrate. + The source layer 4 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is preferably 1.0E+17 / cm 3 More than 1.0E+20 / cm 3 The following is true: + The n-type source layer 4 is in contact with the upper insulating film 8a of the trench 7. + The n-type source layer 4 + This may be called the type emitter layer.

[0020] p + Although not shown, the p-type contact layer is provided on the first main surface side of the semiconductor substrate with respect to the p-type base layer 3. + The p-type contact layer is selectively provided above the p-type base layer 3 as a surface layer of the semiconductor substrate. + The n-type contact layer is disposed above the p-type base layer 3 along the extension direction of the trench 7. + The p-type source layer 4 is not provided in the region. +The contact layer is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is preferably 1.0E+15 / cm 3 More than 1.0E+20 / cm 3 The following is the case. Note that p + The p-type contact layer is a region having a higher concentration of p-type impurities than the p-type base layer 3. + When it is necessary to distinguish between the p-type contact layer and the p-type base layer 3, they may be referred to individually. + The type contact layer and the p-type base layer 3 may be defined as one p-type base layer 3 in combination.

[0021] The n-type buffer layer 5 is - The n-type buffer layer 5 is provided on the second main surface side of the semiconductor substrate with respect to the n-type drift layer 1. The n-type buffer layer 5 is a semiconductor layer containing at least one of phosphorus and protons as an n-type impurity, and the concentration of the n-type impurity is preferably 1.0E+12 / cm 3 More than 1.0E+18 / cm 3 The n-type buffer layer 5 is - The n-type buffer layer 5 has a higher concentration of n-type impurities than the p-type drift layer 1. The n-type buffer layer 5 reduces the occurrence of punch-through caused by the depletion layer extending from the p-type base layer 3 to the second main surface side when the semiconductor device 100 is in an off state. - The n-type drift layer 1 is a single - The n-type drift layer 1 may be defined as an n-type carrier accumulation layer 2, an n-type buffer layer 5, and an n-type - The n-type drift layer 1 and the n-type drift layer 2 are combined to form a single n-type - The n-type drift layer 1 may be defined as the n-type buffer layer 5. The n-type buffer layer 5 is not necessarily required. - A type drift layer 1 may be provided.

[0022] The p-type collector layer 6 is provided on the second main surface side of the semiconductor substrate with respect to the n-type buffer layer 5. The p-type collector layer 6 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is preferably 1.0E+16 / cm3 More than 1.0E+20 / cm 3 The following is the result.

[0023] The trench 7 is provided on the first main surface of the semiconductor substrate, i.e., the upper surface of the semiconductor substrate. The trench 7 is formed at a depth of n + The n-type source layer 4 and the p-type base layer 3 are formed in a thickness direction. - The drift layer 1 has been reached.

[0024] The inner wall surface of the trench 7 is covered with an insulating film 8. The insulating film 8 may be composed of a single film, but in this embodiment, it is composed of an upper insulating film 8a covering the upper part of the trench 7 and a lower insulating film 8b covering the lower part. The upper insulating film 8a covers the side surface of the upper part of the trench 7, and the lower insulating film 8b covers the side surface from the bottom of the trench 7 to the lower part. The upper insulating film 8a and the lower insulating film 8b are, for example, oxide films. The lower insulating film 8b may be thicker than the upper insulating film 8a. With this configuration, it is possible to suppress the insulation film breakdown due to electric field concentration at the trench end 7a described later.

[0025] Furthermore, the trench 7 has a two-stage structure having two electrodes, an upper electrode 9 and a lower electrode 10, inside, i.e., a split gate structure. The upper electrode 9 is provided inside the trench 7 via an upper insulating film 8a, and the lower electrode 10 is provided on the second main surface side of the upper electrode 9 via a lower insulating film 8b. The upper electrode 9 and the lower electrode 10 are insulated from each other by a boundary insulating film 11. That is, inside the trench 7, the lower electrode, the boundary insulating film, and the upper electrode are stacked in this order via an insulating film to form a two-stage structure. Here, the lower electrode 10 is connected to the n-type MOS transistor via the lower insulating film 8b. - The upper electrode 9 faces the p-type drift layer 1. The bottom of the upper electrode 9 is located closer to the second main surface than the p-type base layer 3.

[0026] The upper electrode 9 and the lower electrode 10 are formed by depositing polysilicon doped with n-type or p-type impurities, and the concentration of the impurities in the polysilicon is 1.0E+17 / cm 3 ~1.0E+22 / cm 3 The impurity concentration of the lower electrode 10 is higher than that of the upper electrode 9, for example, 1.0E+19 / cm 3 ~1.0E+22 / cm 3 Preferably, 1.0E+20 / cm 3 ~1.0E+22 / cm 3 It is.

[0027] As shown in FIG. 3, the upper electrode 9 is electrically connected to the gate electrode 15 in the peripheral region 40, and the lower electrode 10 is electrically connected to the emitter electrode 13 in the active region 30. Furthermore, in the peripheral portion in the extension direction of the trench 7 located in the peripheral region 40, the lower electrode 10 is extended further outward than the upper electrode 9. The portion of the lower electrode 10 that is extended further outward than the upper electrode 9 is defined as an extension portion 10a of the lower electrode 10. The extension portion 10a is further extended to the first main surface of the semiconductor substrate so as to cover the end of the upper electrode 9. The extension portion 10a and the upper electrode 9 are also insulated by the boundary insulating film 11. The portion of the lower electrode 10 for electrically connecting the lower electrode 10 to the emitter electrode 13 is defined as a pull-up region portion 10b. The pull-up region portion 10b is further extended to the first main surface of the semiconductor substrate so as to penetrate the upper electrode 9. The pull-up region portion 10b and the upper electrode 9 are also insulated by the boundary insulating film 11.

[0028] As shown in FIG. 3, the interlayer insulating film 12 is provided on the upper electrode 9 and the lower electrode 10 in the trench 7 .

[0029] Although not shown, the barrier metal is formed on the region of the first main surface of the semiconductor substrate where the interlayer insulating film 12 is not provided and on the interlayer insulating film 12. The barrier metal is formed of, for example, a conductor containing titanium. The conductor containing titanium is, for example, titanium nitride or TiSi. TiSi is an alloy of titanium and silicon (Si). The barrier metal is formed of n + Type source layer 4, p + The barrier metal is in ohmic contact with the n-type contact layer and the lower electrode 10. + Type source layer 4, p + The contact layer and the lower electrode 10 are electrically connected to each other.

[0030] The emitter electrode 13 is provided on a barrier metal provided in the active region 30. The emitter electrode 13 is formed of, for example, an aluminum silicon alloy (Al-Si alloy). The emitter electrode 13 is connected to an n + Type source layer 4, p + The emitter electrode 13 is electrically connected to the die contact layer and the lower electrode 10. The emitter electrode 13 may be composed of a plurality of metal films including an aluminum alloy film and other metal films. For example, the emitter electrode 13 may be composed of an aluminum alloy film and a plating film. The plating film is formed by, for example, electroless plating or electrolytic plating. The plating film is, for example, a nickel (Ni) film. A tungsten film may be formed in the fine region between the adjacent interlayer insulating films 12. The emitter electrode 13 is formed on the tungsten film. The tungsten film has better embedding properties than the plating film, so that a good emitter electrode 13 is formed.

[0031] The barrier metal and the emitter electrode 13 may be combined and defined as one emitter electrode 13. The barrier metal is not necessarily required. When the barrier metal is not provided, the emitter electrode 13 is n + on type source layer 4, p + The barrier metal is provided on the n-type contact layer and the lower electrode 10 and is in ohmic contact with them. +Alternatively, the emitter electrode 13 may be provided only on an n-type semiconductor layer such as the n-type source layer 4. An interlayer insulating film 12 may be provided on a portion of the lower electrode 10. In this case, the emitter electrode 13 is electrically connected to the lower electrode 10 in any region on the lower electrode 10.

[0032] As shown in FIG. 3, the gate electrode 15 has an n-type - The gate electrode 15 is provided on the type drift layer 1 and the upper electrode 9 and is in ohmic contact with them. An interlayer insulating film 12 may be provided on a part of the upper electrode 9. In that case, the gate electrode 15 is electrically connected to the upper electrode 9 in any region on the upper electrode 9.

[0033] The collector electrode 14 is provided on the second main surface side of the semiconductor substrate with respect to the p-type collector layer 6. The collector electrode 14 is made of, for example, an aluminum alloy, similar to the emitter electrode 13. The collector electrode 14 is in ohmic contact with the p-type collector layer 6 and is electrically connected to the p-type collector layer 6. The collector electrode 14 may be made of an aluminum alloy and a plating film. The collector electrode 14 may have a different configuration from the emitter electrode 13.

[0034] In the manner described above, the semiconductor device 100 having the IGBT is configured. Next, details of the structure of the outer periphery in the extension direction of the trench 7 will be described with reference to FIG.

[0035] 4, a region of the trench 7 corresponding to the extension portion 10a of the lower electrode 10 is defined as the trench end 7a. The trench width is narrowest at the trench end 7a. Here, the width of the trench end 7a is defined as a first width W1, and the trench width is the smallest W1 at the trench end 7a.

[0036] The above-mentioned configuration makes it possible to improve the avalanche breakdown voltage of the semiconductor device 100. The reason for this will be explained below.

[0037] First, in the on-state of an IGBT, n - A large amount of electrons and holes flow into the n-type drift layer 1. Next, at the time of turn-off switching, - The inflow of electrons and holes into the n-type drift layer 1 stops. - The holes that have flowed into the drift layer 1 flow from the outer circumferential region 40, where there is no discharge path, toward the emitter electrode 13 from which the holes are discharged. That is, holes also flow into the trench end 7a at high density, and the hole density at the trench end 7a increases. Because the inflow of electrons has stopped, the space charge density at the trench end 7a increases, and the electric field strength increases, causing an avalanche.

[0038] As described above, by configuring the trench width to be the narrowest W1 at the trench end 7a, the mesa width W M Since the area can be made wider, the hole discharge path can be enlarged and the hole density can be reduced, which reduces the space charge density, suppresses the increase in the electric field strength, and improves the avalanche breakdown voltage.

[0039] In addition, since the lower electrode 10 is electrically connected to the emitter electrode 13, its potential is lower than that of the upper electrode 9. Therefore, during turn-off switching, holes are attracted not only to the sidewall of the region of the trench 7 that corresponds to the upper electrode 9, but also to the sidewall of the region that corresponds to the lower electrode 10. As described above, by disposing the extension portion 10a of the lower electrode 10 at the tip portion within the trench 7, holes are attracted to the sidewall of the trench end 7a as well, and n - A low-resistance p-type inversion layer can be formed in the drift layer 1. That is, at the trench end 7a, holes can pass through the low-resistance p-type inversion layer, facilitating the discharge of holes.

[0040] Next, a modification of the first embodiment will be described with reference to FIG. 5. As shown in FIG. 5, the region where the trench width is narrowest may be the region of the trench 7 that corresponds to the extension portion 10a as well as the region that corresponds to a part of the upper electrode 9. Here, the region that corresponds to the part of the upper electrode 9 is the region that corresponds to the upper electrode 9 that exists in the outer peripheral region 40. With this configuration, the region in the trench 7 where the trench width is narrowest W1 is expanded. Therefore, the mesa width W M Since the region with a large hole density is expanded, the hole density can be further reduced and the avalanche breakdown voltage can be improved.

[0041] As described above, in the semiconductor device 100 of this embodiment, the mesa width is changed by changing the trench width so that the mesa width is largest at the trench end 7a. This makes it possible to reduce the hole density at the trench end 7a, and to improve the avalanche breakdown voltage in the semiconductor device 100 having an IGBT with a split gate structure.

[0042] Furthermore, in the semiconductor device 100 of this embodiment, the hole discharge path can be expanded, making it easier to discharge holes and reducing turn-off loss. Therefore, by reducing the turn-off loss, the semiconductor device 100 having the split-gate IGBT can reduce switching loss.

[0043] The method for manufacturing the semiconductor device 100 of this embodiment is basically the same as the method for manufacturing the semiconductor device 100 provided with an IGBT having a conventional split-gate trench structure, except that an etching mask is used in the etching process for forming the trench 7, which sets the trench width W1 at least at the trench end 7a to the narrowest value.

[0044] A detailed description will now be given of a method for manufacturing the semiconductor device 100. The method for manufacturing the semiconductor device 100 includes a step of preparing a semiconductor substrate, a step of forming a first main surface side of the semiconductor substrate, and a step of forming a second main surface side of the semiconductor substrate.

[0045] First, the process of preparing a semiconductor substrate will be described. In this embodiment, an n-type wafer containing n-type impurities is prepared as the semiconductor substrate. The semiconductor substrate may be a so-called FZ wafer produced by the FZ (Floating Zone) method, or a so-called MCZ wafer produced by the MCZ (Magnetic field applied CZochralki) method. Alternatively, the semiconductor substrate may be a wafer produced by sublimation or chemical vapor deposition (CVD). In this process, the entire semiconductor substrate is n-type. - The n-type drift layer 1 corresponds to the n-type impurity concentration. The concentration of the n-type impurity is appropriately selected depending on the withstand voltage specification of the semiconductor device 100. For example, when the withstand voltage specification of the semiconductor device 100 is 1200 V, the concentration of the n-type impurity is n - The resistivity of the n-type drift layer 1 is adjusted to be about 40 to 120 Ω·cm. - The process of preparing an n-type wafer as the n-type drift layer 1 is shown, but the process of preparing a semiconductor substrate is not limited thereto. For example, a process of ion-implanting an n-type impurity from a first main surface or a second main surface of a semiconductor substrate and a process of diffusing the n-type impurity by heat treatment can be used to prepare an n-type drift layer 1. - A semiconductor substrate including a type drift layer 1 may be provided.

[0046] Next, a process for forming the first main surface side of the semiconductor substrate will be described. First, n-type impurities for forming the n-type carrier accumulation layer 2 are introduced from the first main surface side of the semiconductor substrate to the n-type impurity layer 2. - Ions are implanted into the surface layer of n-type drift layer 1. The n-type impurity is, for example, phosphorus. Next, p-type impurities for forming p-type base layer 3 are ion-implanted from the first main surface side of the semiconductor substrate. The p-type impurity is, for example, boron. After the ion implantation, a heat treatment is performed, and the n-type impurities and p-type impurities are diffused, forming n-type carrier accumulation layer 2 and p-type base layer 3.

[0047] During the above ion implantation, a mask having openings in predetermined regions is formed on the first main surface of the semiconductor substrate. The n-type impurities and the p-type impurities are implanted in regions corresponding to the openings of the mask. The mask is formed by a process of applying a resist onto the first main surface of the semiconductor substrate and a process of forming openings in predetermined regions of the resist by photolithography (photoengraving) technology. Hereinafter, the process of forming a mask having openings in such predetermined regions is referred to as a mask process. The n-type impurities and the p-type impurities are implanted in the predetermined regions by the mask process. As a result, the n-type carrier accumulation layer 2 and the p-type base layer 3 are selectively formed within the plane of the first main surface of the semiconductor substrate.

[0048] Next, n + An n-type impurity for forming the p-type source layer 4 is ion-implanted into the surface layer of the p-type base layer 3 from the first main surface side of the semiconductor substrate. At this time, the n-type impurity is implanted using a mask treatment. + An n-type source layer 4 is selectively formed on the surface of the p-type base layer 3. The n-type impurity is, for example, arsenic or phosphorus.

[0049] Next, p + A p-type impurity for forming a p-type contact layer is ion-implanted into the surface layer of the p-type base layer 3 from the first main surface side of the semiconductor substrate. At this time, the p-type impurity is implanted using a mask treatment. + A p-type contact layer is selectively formed on the surface of the p-type base layer 3. The p-type impurity is, for example, boron or aluminum.

[0050] Next, n is + The n-type source layer 4 and the p-type base layer 3 are penetrated. - A trench 7 is formed in the active region 30, reaching the n-type drift layer 1. + The trench 7 penetrating the source layer 4 has a side wall of n + It constitutes a part of the mold source layer 4 .

[0051] To form the trench 7, first, an oxide film is deposited on the first main surface of the semiconductor substrate. The oxide film is, for example, a thin film such as SiO2. Next, an opening is formed in the oxide film in the portion where the trench 7 is to be formed, and a mask having the opening is formed. Note that, when forming the mask, a mask having an opening is formed such that the trench width at the trench end 7a of the trench 7 is the narrowest width W1. Finally, the semiconductor substrate is etched through the mask to form the trench 7.

[0052] Next, the semiconductor substrate is heated in an atmosphere containing oxygen to form lower insulating film 8b on the inner wall of trench 7 and the first main surface of the semiconductor substrate. Note that lower insulating film 8b formed on the first main surface of the semiconductor substrate will be removed in a later process.

[0053] Next, a lower electrode 10 is formed inside the trench 7 with the lower insulating film 8b formed on the inner wall. Polysilicon doped with n-type or p-type impurities is deposited inside the trench 7 by CVD (chemical vapor deposition) or the like to form the lower electrode 10. As a result, the lower electrode 10 is formed inside the trench 7 via the lower insulating film 8b.

[0054] Next, a mask having an opening for the trench 7 to be filled with the upper electrode 9 is formed by mask processing, and the lower electrode 10 in the trench 7 is etched. Thereafter, the portion of the lower insulating film 8b in the trench 7 where the upper insulating film 8a is to be formed is removed.

[0055] Next, the semiconductor substrate is heated in an atmosphere containing oxygen to form an upper insulating film 8a on the inner wall of the trench 7 and the first main surface of the semiconductor substrate. Also, a boundary insulating film 11 is formed on the first main surface of the lower electrode 10. The upper insulating film 8a formed on the first main surface of the semiconductor substrate will be removed in a later process.

[0056] Next, an upper electrode 9 is formed inside the trench 7 with the upper insulating film 8a formed on the inner wall. Polysilicon doped with n-type or p-type impurities is deposited inside the trench 7 by CVD (chemical vapor deposition) or the like to form the upper electrode 9. As a result, the upper electrode 9 is formed inside the trench 7 via the upper insulating film 8a.

[0057] Next, the interlayer insulating film 12 is formed on the trench 7. The interlayer insulating film 12 is deposited by a mask process, and the oxide film formed on the first main surface of the semiconductor substrate is removed. The interlayer insulating film 12 includes, for example, SiO2 as an oxide film.

[0058] Then, a contact hole is formed in the interlayer insulating film 12. The contact hole is + on type source layer 4, p + A metal contact layer is formed on the metal contact layer.

[0059] Next, a barrier metal is formed on the first main surface of the semiconductor substrate and the interlayer insulating film 12. The barrier metal is formed by PVD (physical vapor deposition) or CVD.

[0060] Next, the emitter electrode 13 is formed on the barrier metal. The emitter electrode 13 is formed by a PVD method such as sputtering or vapor deposition. The emitter electrode 13 includes, for example, an aluminum silicon alloy (Al-Si alloy). Furthermore, the second emitter electrode 13 may be formed on the emitter electrode 13 by an electroless plating method or an electrolytic plating method. The second emitter electrode 13 includes, for example, nickel or a nickel alloy. The second emitter electrode 13 may have, for example, a laminated structure including two or more kinds of metal layers. The laminated structure is, for example, composed of a Ni film, a Pd film, and an Au film, and is formed by a plating method.

[0061] The plating method makes it possible to easily form a thick metal film. In the thick emitter electrode 13, the heat capacity increases, and therefore the heat resistance of the emitter electrode 13 improves. When a nickel alloy is further formed on the aluminum silicon alloy by plating, the plating may be performed after the second main surface of the semiconductor substrate is processed.

[0062] Next, a process for forming the second main surface side of the semiconductor substrate will be described. First, a process for thinning the semiconductor substrate will be described. The second main surface of the semiconductor substrate is ground to thin the semiconductor substrate to a predetermined thickness according to the design of the semiconductor device 100. The thickness of the semiconductor substrate after grinding is, for example, 80 μm or more and 200 μm or less.

[0063] Next, a process for forming the n-type buffer layer 5 and the p-type collector layer 6 will be described. First, the n-type impurity for forming the n-type buffer layer 5 is introduced from the second main surface side of the thinned semiconductor substrate. - Ions are implanted into the surface layer of n-type drift layer 1. As the n-type impurity, for example, phosphorus may be implanted or protons may be implanted. Alternatively, for example, both phosphorus and protons may be implanted.

[0064] Protons are implanted deep into the second main surface of the semiconductor substrate with a relatively low acceleration energy. The proton implantation depth can be controlled relatively easily by changing the acceleration energy. Therefore, when protons are ion-implanted multiple times while changing the acceleration energy, an n-type buffer layer 5 is formed that is wider in the thickness direction of the semiconductor substrate than the n-type buffer layer 5 containing phosphorus.

[0065] Moreover, phosphorus has a higher activation rate as an n-type impurity than protons. Even in a thinned semiconductor substrate, the n-type buffer layer 5 containing phosphorus more reliably reduces the occurrence of punch-through caused by the expansion of the depletion layer. In order to further thin the semiconductor substrate, it is preferable to form the n-type buffer layer 5 containing both protons and phosphorus. In this case, the protons are implanted deeper from the second main surface of the semiconductor substrate than the phosphorus.

[0066] Next, p-type impurities for forming p-type collector layer 6 are ion-implanted from the second main surface side of the semiconductor substrate. For example, boron is implanted as the p-type impurity. After the ion implantation, a laser is irradiated onto the second main surface of the semiconductor substrate. The implanted boron is activated by the laser annealing, and p-type collector layer 6 is formed.

[0067] During this laser annealing, the n-type impurity phosphorus implanted at a position relatively shallow from the second main surface of the semiconductor substrate is also activated at the same time. On the other hand, protons are activated at a relatively low annealing temperature of about 350°C to 500°C. Therefore, after the protons are implanted, it is preferable that the semiconductor substrate is not heated to a temperature higher than 350°C to 500°C except for the step of activating the protons. Laser annealing heats only the vicinity of the second main surface of the semiconductor substrate to a high temperature. Therefore, laser annealing is effective in activating the n-type impurity or p-type impurity after the protons are implanted.

[0068] Next, the process of forming the collector electrode 14 will be described. The collector electrode 14 is formed on the second main surface of the semiconductor substrate. The collector electrode 14 may be formed over the entire surface of the second main surface of the semiconductor substrate. The collector electrode 14 includes an aluminum silicon alloy, titanium, or the like. The collector electrode 14 is formed by PVD such as sputtering or vapor deposition. The collector electrode 14 may be formed of a plurality of metal layers each including an aluminum silicon alloy, titanium, nickel, gold, or the like. Alternatively, the collector electrode 14 may have a structure in which another metal film is formed by electroless plating or electrolytic plating on a metal film formed by PVD.

[0069] The above-described process manufactures the semiconductor device 100. Since a plurality of semiconductor devices 100 are manufactured in a matrix on one n-type wafer, the semiconductor devices 100 are completed by dicing the wafer into individual semiconductor devices 100 by laser dicing or blade dicing.

[0070] Embodiment 2 The semiconductor device according to Embodiment 2 will be described with reference to FIGS. 6 and 7. FIGS. 6 and 7 show a plan view of the outer peripheral portion of the trench 7, similar to FIGS. 4 and 5. Here, as shown in FIG. 6, for the trench 7, the width of the trench end 7a is defined as the first width W1. Also, for the trench 7, the trench width of the region where the trench width is the widest is defined as the second width W2. The semiconductor device of Embodiment 2 is formed such that the trench 7 has the narrowest trench width at the trench end 7a, similar to Embodiment 1. Further, the trench width of the trench end 7a is characterized by being narrower than the width of the region where the trench width of the trench 7 is the widest. That is, the trench 7 is formed such that the trench width is W1 < W2, and further, as it goes toward the tip of the trench end 7a where the trench width changes from W2 to W1, the trench width gradually becomes narrower. In Embodiment 2, the region where the trench width is the widest is the region corresponding to a part of the upper electrode 9 in the outer peripheral region of the trench 7.

[0071] With the above-described configuration, since the mesa width expands in the region where the trench width becomes narrow, the discharge path of holes can be expanded. Therefore, since hole discharge is promoted, an increase in hole density in the region where the trench width is the widest and it is difficult for holes to be discharged can be suppressed, and the avalanche breakdown voltage can be improved.

[0072] Also, as shown in FIG. 7, the region where the trench width is the widest exists in the pull-up region 50 that electrically connects the upper electrode 9 to the gate electrode 15. It is conceivable that the trench width in the pull-up region 50 is wider than the trench width corresponding to the upper electrode 9 existing in the active region 30 among the trenches 7. This is because the trench width of the pull-up region 50 becomes wider by the area for arranging the contact hole for electrically connecting the upper electrode 9 to the gate electrode 15. Therefore, since the mesa width in the pull-up region 50 becomes narrow, the hole density increases, and the avalanche breakdown voltage is likely to decrease.

[0073] In this case, as shown in FIG. 7, let the trench width of the pulling-up region 50, which is the region where the trench width is the widest, be W2, and the trench width of the trench end 7a, which is the region where the trench width is the narrowest, be W1, and make sure that W1 < W2. Further, the trench width is gradually narrowed toward the trench end 7a so as to change from W2 to W1.

[0074] With the above-described configuration, in the region excluding the pulling-up region 50, since the mesa width expands, the discharge path of holes can be expanded. Therefore, since hole discharge is promoted, an increase in the hole density in the pulling-up region 50 where it is difficult to discharge holes can be suppressed, and the avalanche breakdown voltage can be improved.

[0075] As described above, in the semiconductor device according to Embodiment 2, in addition to the same effects as in Embodiment 1, even when there is a region where the trench width is the widest and it is difficult to discharge holes, an increase in the hole density can be suppressed, and the avalanche breakdown voltage can be improved.

[0076] Embodiment 3. The semiconductor device according to Embodiment 3 will be described with reference to FIGS. 8 to 10. FIGS. 8 to 10 show a plan view of the outer peripheral portion of the trench 7, similar to FIGS. 4 and 5. Here, the semiconductor device of Embodiment 3 has the same first width W1 for the width of the trench end 7a as in Embodiment 1, and is formed such that the trench width at the trench end 7a is the minimum W1. Further, at the trench end 7a, the trench width gradually narrows toward the tip of the trench end 7a.

[0077] As shown in FIG. 8, in the semiconductor device of Embodiment 3, the trench width becomes narrow due to two or more steps and becomes the minimum W1 at the trench end 7a. By narrowing step by step, the bias of the hole density in the trench 7 can be reduced, the electric field concentration can be alleviated, and further, the avalanche breakdown voltage can be improved.

[0078] 9, a taper 20 may be provided at the trench end 7a. By providing the taper 20, the width of the trench 7 can be gradually narrowed toward the tip of the trench 7. In other words, the width of the trench 7 can be set to the minimum W1 at the trench end 7a. With the above-mentioned configuration, the bias of the hole density in the trench 7 can be reduced and the electric field concentration can be alleviated, thereby further improving the avalanche breakdown voltage. Also, in FIG. 9, only the trench end 7a is tapered, but the region of the trench 7 corresponding to the upper electrode 9 may also be tapered.

[0079] 10, the tip of the trench end 7a may be rounded. If the tip of the trench end 7a is angular, an electric field is likely to concentrate at the trench end 7a. By eliminating the corners of the trench end 7a and forming it round, the width of the trench 7 can be gradually narrowed toward the tip of the trench 7. In other words, the width of the trench 7 can be set to a minimum W1 at the trench end 7a. With the above-mentioned configuration, the bias in hole density in the trench 7 can be reduced and the electric field concentration can be alleviated, thereby further improving the avalanche breakdown voltage.

[0080] As described above, in the semiconductor device according to the third embodiment, in addition to the same effects as those of the first embodiment, the bias in hole density can be suppressed and the electric field concentration can be alleviated, thereby further improving the avalanche breakdown voltage.

[0081] Embodiment 4 A semiconductor device according to the fourth embodiment will be described with reference to FIG. 11. Like FIGS. 4 and 5, FIG. 11 shows a plan view of the outer periphery of trench 7. Like the first embodiment, the semiconductor device according to the fourth embodiment is formed such that the width of trench end 7a is a first width W1 and the trench width at trench end 7a is a minimum W1. Furthermore, each of extension portions 10a is joined by intersection trenches 21 extending in the X direction, which is a direction intersecting the extension direction of trench 7, and adjacent lower electrodes 10 are connected to each other.

[0082] The inner wall surface of the intersection trench 21 is covered with an insulating film. The insulating film may be a single film similar to the upper insulating film 8a and the lower insulating film 8b, but in the fourth embodiment, it is an intersection insulating film 22. In addition, an intersection electrode 23 is provided in the intersection trench 21 via the intersection insulating film 22. The intersection electrode 23 may be formed so that the extension portion 10a of the lower electrode 10 further extends in the X direction, which is a direction intersecting the extension direction of the trench 7. In addition, the intersection electrode 23 is electrically connected to the emitter electrode 13. Here, when the intersection trench 21 is formed as in the fourth embodiment, the portion of the intersection trench 21 is not included in the "trench end 7a". The above-mentioned configuration makes it possible to further improve the avalanche breakdown voltage at the trench end 7a. The reason for this will be explained below.

[0083] The trench end 7a is a location where the electric field is likely to concentrate. In particular, during turn-off switching, holes are more likely to be attracted to the lower electrode 10 at the emitter potential than to the upper electrode 9 at the gate potential. In other words, holes are more likely to be attracted to the trench end 7a where the extension portion 10a of the lower electrode 10 is disposed. Therefore, the electric field at the trench end 7a increases, causing a dynamic avalanche, which may lead to deterioration of the characteristics of the semiconductor device.

[0084] Here, as in the fourth embodiment, adjacent trench ends 7a are connected by an intersection trench 21, thereby eliminating overhang at the trench ends 7a and alleviating the electric field. Furthermore, as in the first embodiment, by making the trench width W1 narrowest at the trench ends 7a, it is possible to obtain the same effect as in the first embodiment.

[0085] As described above, in the semiconductor device according to the fourth embodiment, the hole density can be suppressed and the occurrence of avalanche can be suppressed in the same manner as in the first embodiment. Furthermore, the electric field at the trench end 7a can be further relaxed, and the avalanche breakdown voltage can be further improved.

[0086] The configurations shown in the above embodiments are merely examples of the contents of the present disclosure, and may be combined with other known techniques. Furthermore, parts of the configurations may be omitted or modified without departing from the scope of the present disclosure.

[0087] In the above embodiment, an IGBT having a split gate trench structure with a first conductivity type being n-type and a second conductivity type being p-type has been described as an example. However, this is merely an example, and an IGBT having a split gate trench structure with a p-channel type in which the conductivity types of each component are inverted from an n-channel type may also be used. Furthermore, the present invention can be applied to a MOSFET having a similar structure. In the case of a MOSFET, electrons and holes are generated when an avalanche occurs. By applying the present invention to a MOSFET, the discharge of the generated holes is promoted, and deterioration of the characteristics of the semiconductor device can be suppressed. [Explanation of symbols]

[0088] 1n - 3 p-type drift layer, 4 n-type base layer + a p-type source layer, 6 a collector layer, 7 a trench, 7 a trench end, 8 an insulating film, 8 a upper insulating film, 8 b a lower insulating film, 9 an upper electrode, 10 a lower electrode, 10 a extension portion, 10 b a lift-up region portion, 11 a boundary insulating film, 12 an interlayer insulating film, 13 an emitter electrode, 14 a collector electrode, 15 a gate electrode, 20 a taper, 21 an intersecting trench, 22 an intersecting insulating film, 23 an intersecting electrode, 30 an active region, 40 a peripheral region, 50 a lift-up region, 100 a semiconductor device

Claims

1. A semiconductor device having an active region in which a semiconductor switching element is formed, and a peripheral region in which a gate electrode is provided outside the active region, The semiconductor switching element is a first conductivity type drift layer; a second conductivity type base layer provided on an upper surface side of the first conductivity type drift layer; a first conductivity type source layer provided on an upper surface side of the second conductivity type base layer; a second conductivity type collector layer provided on a lower surface side of the first conductivity type drift layer; an emitter electrode electrically connected to the first conductivity type source layer; a collector electrode electrically connected to the second conductivity type collector layer, a region from an upper surface of the first conductive type source layer to a lower surface of the second conductive type collector layer is defined as a semiconductor substrate; a plurality of trenches penetrating in a depth direction from an upper surface of the semiconductor substrate to the first conductivity type drift layer and extending from the active region toward the outer periphery region; an interlayer insulating film covering each of the trenches; Each of the plurality of trenches is a lower electrode, a boundary insulating film, and an upper electrode are laminated in this order within the trench via an insulating film to form a two-stage structure; the lower electrode is electrically connected to the emitter electrode; the upper electrode is electrically connected to the gate electrode; an extension portion of the lower electrode, which is extended further outward than the upper electrode in an outer periphery of the trench located in the outer periphery region in an extension direction of the trench, is further extended to an upper surface of the semiconductor substrate so as to cover an end portion of the upper electrode; A semiconductor device in which the width of the trench is narrowest at the ends of the trench.

2. 2. The semiconductor device according to claim 1, wherein the width of the trench is narrowest in a region of the trench that corresponds to the extension of the lower electrode and a part of the upper electrode.

3. 2. The semiconductor device according to claim 1, wherein the width of the trench gradually narrows toward the tip of the trench end.

4. The semiconductor device according to claim 3 , wherein the width of the trench is narrowed in a stepwise manner.

5. 4. The semiconductor device according to claim 3, wherein an end of the trench is tapered.

6. 4. The semiconductor device according to claim 3, wherein the end of the trench is rounded.

7. 2. The semiconductor device according to claim 1, wherein the width of the trench gradually narrows from the widest region of the trench toward the tip of the trench end.

8. 8. The semiconductor device according to claim 7, wherein the widest region of the trench is in a raised region connecting the upper electrode to the gate electrode.

9. An intersection trench is further provided to connect the tip of the trench end and the tip of the adjacent trench end, A cross electrode is provided inside the cross trench via an insulating film, The semiconductor device according to claim 1 , wherein the cross electrode is electrically connected to the emitter electrode.

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