System and method for defragmentation of memory device

Abstract

To provide a system, and the like, for improving memory access performance by defragmentation.SOLUTION: In a memory system 102, a memory controller includes: controller memories 411, 413 for storing a logical-to-physical (L2P) address mapping table corresponding to a file; and a controller processor configured to control a memory device, receive a mapping update command, and update the L2P address mapping table according to the mapping update command by replacing original logical addresses of logical block address (LBA) segments of the file with new continuous logical addresses of a merged LBA segment of the file, and changing an original mapping relation between the original logical addresses of the LBA segment of the file and physical addresses of the file, to a new mapping relation between the new continuous logical addresses of the merged LBA segment of the file and the physical addresses of the file.SELECTED DRAWING: Figure 4A

Description

[Technical field]

[0001] The present disclosure relates to systems and methods for defragmentation of memory devices. [Background technology]

[0002] Data stored in systems and memory devices becomes fragmented over time, which degrades the performance of the system and memory devices by slowing down access and processing speeds. Sometimes it even causes unwanted corruption and data loss. Defragmentation is the process of reducing the degree of fragmentation by reorganizing the data on the storage device for faster access and better system performance. Summary of the Invention [Means for solving the problem]

[0003] In one aspect, a memory controller includes a controller memory for storing a logical-to-physical (L2P) address mapping table corresponding to a file, and a controller processor configured to control the memory device, receive a mapping update command, and update the L2P address mapping table in accordance with the mapping update command by replacing original logical addresses of a logical block address (LBA) segment of the file with new contiguous logical addresses of a merged LBA segment of the file, and changing an original mapping relationship between the original logical addresses of the LBA segment of the file and the physical addresses of the file to a new mapping relationship between the new contiguous logical addresses of the merged LBA segment of the file and the physical addresses of the file.

[0004] In some implementations, the controller memory includes a volatile controller memory for storing an L2P address mapping table corresponding to the file.

[0005] In some implementations, the controller memory further includes a non-volatile controller memory. The controller processor is configured to store the updated L2P address mapping table in the non-volatile controller memory as a non-volatile L2P address mapping table.

[0006] In some implementations, the controller processor is configured to send an indication to the host confirming that the L2P address mapping table has been updated.

[0007] In some implementations, the controller processor is configured to generate a merge log by recording new mapping relationships between new contiguous logical addresses of the merge LBA segments of the file and the physical addresses of the file.

[0008] In some implementations, in response to a sudden power loss, the controller processor is configured to rebuild the volatile L2P address mapping table according to a merge log that records new mapping relationships between new consecutive logical addresses of the merge LBA segments of the file and the physical addresses of the file after the memory system is resumed.

[0009] In some implementations, the controller processor is configured to scan a physical-to-logical (P2L) address mapping table and a merge log of the metadata block, and in response to the merge log being updated, the controller processor is configured to rebuild the L2P address mapping table according to the merge log.

[0010] In another aspect, a memory system includes a memory controller including a memory device including the physical data blocks, a controller memory for storing a logical-to-physical (L2P) address mapping table corresponding to a file, and a controller processor configured to control the memory device, receive a mapping update command, and update the L2P address mapping table in accordance with the mapping update command by replacing original logical addresses of a logical block address (LBA) segment of the file with new contiguous logical addresses of a merged LBA segment of the file, and changing an original mapping relationship between the original logical addresses of the LBA segment of the file and the physical addresses of the file to a new mapping relationship between the new contiguous logical addresses of the merged LBA segment of the file and the physical addresses of the file.

[0011] In some implementations, the controller memory includes a volatile controller memory for storing an L2P address mapping table corresponding to the file.

[0012] In some implementations, the controller memory further includes a non-volatile controller memory. The controller processor is configured to store the updated L2P address mapping table in the non-volatile controller memory as a non-volatile L2P address mapping table.

[0013] In some implementations, the controller processor is configured to send an indication to the host confirming that the L2P address mapping table has been updated.

[0014] In some implementations, the controller processor is configured to generate a merge log by recording new mapping relationships between new contiguous logical addresses of the merge LBA segments of the file and the physical addresses of the file.

[0015] In some implementations, in response to a sudden power loss, the controller processor is configured to rebuild the L2P address mapping table according to a merge log that records new mapping relationships between new consecutive logical addresses of the merge LBA segments of the file and the physical addresses of the file after the memory system is resumed.

[0016] In some implementations, the controller processor is configured to scan a physical-to-logical (P2L) address mapping table and a merge log of the metadata block, and in response to the merge log being updated, the controller processor is configured to rebuild the L2P address mapping table according to the merge log.

[0017] In yet another aspect, a system includes a memory system including a host including a host memory configured to store a file, and a host processor configured to execute a merge LBA command to remap original logical addresses of a logical block address (LBA) segment of the file to new contiguous logical addresses of the merged LBA segment of the file and to send a mapping update command, and a memory controller including a memory device with physical data blocks, a controller memory for storing a logical-to-physical (L2P) address mapping table corresponding to the file, and a controller processor configured to control the memory device, receive the mapping update command, and update the L2P address mapping table in accordance with the mapping update command by replacing the original logical addresses of the LBA segment of the file with the new contiguous logical addresses of the merged LBA segment of the file and changing an original mapping relationship between the original logical addresses of the LBA segment of the file and the physical addresses of the file to a new mapping relationship between the new contiguous logical addresses of the merged LBA segment of the file and the physical addresses of the file.

[0018] In some implementations, the controller memory includes a volatile controller memory for storing an L2P address mapping table corresponding to the file.

[0019] In some implementations, the host processor is configured to remap the original logical addresses of the LBA segments of the file to new logical addresses of the merged LBA segment of the file by rewriting all logical addresses of the LBA segments of the file to free or unused LBA segments in consecutive order of logical addresses to become new consecutive logical addresses of the merged LBA segment of the file.

[0020] In some implementations, the host processor is configured to send an update mapping command that causes the memory controller to update the L2P address mapping table according to the new contiguous logical addresses of the merged LBA segments of the file.

[0021] In some implementations, the host processor is configured to receive an indication from the memory controller confirming that the L2P address mapping table has been updated.

[0022] In some implementations, the host processor is configured to update the index node of the file after determining that the L2P address mapping table has been updated.

[0023] In some implementations, the host processor is configured to update the index node of the file by pointing the new LBA segment to the new consecutive logical addresses of the merged LBA segment.

[0024] In still yet another aspect, a method for operating a memory controller includes receiving a mapping update command from a host; updating a logical-to-physical (L2P) address mapping table in accordance with the mapping update command by replacing original logical addresses of the LBA segments of the file with new contiguous logical addresses of the merged LBA segment of the file; and changing original mapping relationships between the original logical addresses of the LBA segments of the file and the physical addresses of the file to new mapping relationships between the new contiguous logical addresses of the merged LBA segment of the file and the physical addresses of the file.

[0025] In some implementations, the method further includes sending an indication to the host confirming that the L2P address mapping table has been updated.

[0026] In some implementations, the method further includes recording in a merge log a new mapping relationship between new consecutive logical addresses of the merged LBA segments of the file and the physical addresses of the file, and in response to the sudden power loss, rebuilding the L2P address mapping table according to the merge log after the memory system is resumed.

[0027] In some implementation examples, the step of rebuilding the L2P address mapping table includes scanning a physical-to-logical (P2L) address mapping table and a merge log of the metadata block, and in response to determining that the merge log has been updated, rebuilding the L2P address mapping table according to the merge log.

[0028] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate aspects of the present disclosure and, together with the description, further serve to explain the disclosure and to enable one skilled in the art to make and use the disclosure. [Brief description of the drawings]

[0029] [Figure 1] FIG. 1 is a block diagram of an example system having a host and a memory system in accordance with some aspects of the present disclosure. [Figure 2A] FIG. 2 is a diagram of an exemplary memory card having a memory device in accordance with some aspects of the present disclosure. [Figure 2B] FIG. 1 illustrates an exemplary solid-state drive (SSD) having a memory device in accordance with some aspects of the present disclosure. [Diagram 3] FIG. 1 is a schematic diagram of an example memory device including peripheral circuitry in accordance with some aspects of the present disclosure. [Figure 4A] FIG. 1 is a block diagram of an exemplary memory system including a memory controller and a memory device in accordance with some aspects of the disclosure. [Figure 4B] FIG. 1 is a block diagram of an exemplary memory system including a memory controller and a memory device in accordance with some aspects of the disclosure. [Diagram 5] FIG. 1 is a block diagram of an example system including a host and a memory controller in accordance with some aspects of the disclosure. [Figure 6] FIG. 2 is a block diagram illustrating an example defragmentation scheme in accordance with some aspects of the present disclosure. [Figure 7] FIG. 2 is a block diagram illustrating an example defragmentation scheme in accordance with some aspects of the present disclosure. [Figure 8] FIG. 2 is a block diagram illustrating an example defragmentation scheme under sudden power loss in accordance with some aspects of the present disclosure. [Figure 9] 1 is a flowchart of an example method for operating a memory controller in accordance with some aspects of the present disclosure. [Figure 10] 1 is a flowchart of an exemplary method for operating a host in accordance with some aspects of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0030] Aspects of the present disclosure will now be described with reference to the accompanying drawings.

[0031] While specific configurations and arrangements are described, it should be understood that this is done for illustrative purposes only. As such, other configurations and arrangements can be used without departing from the scope of the present disclosure. The present disclosure can also be utilized in a variety of other applications. The functional and structural features as described in the present disclosure can be combined, adjusted, and modified with one another and in ways not specifically depicted in the drawings, and these combinations, adjustments, and modifications are within the scope of the present disclosure.

[0032] Generally, terminology may be understood, at least in part, from usage in context. For example, depending at least in part on the context, the term "one or more" as used herein may be used in a singular sense to describe any feature, structure, or characteristic, or in a plural sense to describe a combination of features, structures, or characteristics. Similarly, terms such as "a," "an," or "the" may also be understood to convey singular usage or to convey plural usage, depending at least in part on the context. In addition, the term "based on" may be understood not necessarily intended to convey an exclusive set of factors, but rather may allow for the presence of additional factors, also not necessarily explicitly described, depending at least in part on the context.

[0033] Disk defragmentation is a technique that allows users to defragment hard disk drives (HDDs) as well as other removable storage. For example, Windows systems, such as Windows 7, include a disk defragmentation utility called Microsoft Drive Optimizer or Disk Defragmenter that allows users to defragment their hard disks and relocate files stored on the disk to occupy adjacent storage locations, thereby increasing data access speed and improving the overall performance of the computer. Disk defragmentation, however, is not considered effective for solid-state drives (SSDs). In fact, defragmenting SSDs is generally not encouraged because it can use up the SSD's write cycles, potentially causing the SSD to end up with a premature end of life. Nevertheless, with the development of SSDs and the increase in storage capacity of SSDs, the software (SW) input / output stack (I / O stack) becomes a bottleneck in the system. That is, files fragmented at the logical level degrade the system's performance.

[0034] One solution to resolve fragmentation at the logical level is to use a defragmenter such as e2defrag. e2defrag may select contiguous logical address blocks to read and write for each segment of a file's logical address. However, e2defrag not only updates the logical address blocks, but may also update the physical blocks each time it updates the logical address blocks, thereby increasing the effects of write amplification, an undesirable phenomenon associated with flash memory and solid-state drives in which the actual amount of information physically written to the storage medium is a multiple of the logical amount intended to be written. This write amplification can wear out an SSD faster than expected and shorten the lifespan of the SSD. Furthermore, traditional e2defrag wastes time due to its redundant process of routinely updating the physical address blocks each time it reads a segment and updates a logical address block. It is not effective enough to resolve fragmentation issues at the logical level.

[0035] Moreover, conventional defragmentation tools may not have a good power loss protection design to ensure that data is not lost while the SSD is writing data when a sudden power failure occurs. When the defragmentation process is in progress, a sudden power loss may cause significant system corruption or data loss. A mechanism to prevent data loss from a sudden power loss during defragmentation is highly desirable.

[0036] To address one or more of the above problems, the present disclosure introduces a solution in which a merge logical block address (LBA) command is designed to merge segments of LBAs in a file into a merge LBA segment of the file, and update a logical-to-physical (L2P) address mapping table according to the merge LBA segment of the file. Furthermore, a merge log is created to record the mapping relationship between the L2P address mapping table and the physical-to-logical (P2L) address mapping table before updating the L2P address mapping table. Thus, after a sudden power loss, the L2P can be reconstructed or restored by using the merge log and the P2L address mapping table.

[0037] 1 illustrates a block diagram of an exemplary system 100 having a memory device according to some aspects of the present disclosure. The system 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. As illustrated in FIG. 1, the system 100 can include a host 108 having a host memory 110 and a host processor 112, and a memory system 102 having one or more memory devices 104 and a memory controller 106.

[0038] The host 108 can be a processor of an electronic device, such as a central processing unit (CPU), or a system on a chip (SoC), such as an application processor (AP). The host 108 can be coupled to the memory controller 106 and can be configured to send or receive data to or from the memory device 104 through the memory controller 106. For example, the host 108 may send program data in a program operation or receive read data in a read operation. The host processor 112 can be a control unit (CU) or an arithmetic logic unit (ALU). The host memory 110 can be a memory unit including a register or cache memory. The host 108 is configured to receive and send instructions and commands to and from the memory controller 106 of the memory system 102 and to perform or perform multiple functions and operations provided in this disclosure, which will be described below.

[0039] The memory device 104 can be any memory device disclosed in the present disclosure, such as a NAND flash memory device that includes a page buffer having multiple portions, for example, four quarters. It is noted that NAND flash is merely an example of a memory device for illustrative purposes. It can include any suitable solid-state, non-volatile memory, such as NOR flash, ferroelectric RAM (FeRAM), phase change memory (PCM), magnetoresistive random access memory (MRAM), spin transfer write magnetic random access memory (STT-RAM), or resistive random access memory (RRAM), etc. In some implementations, the memory device 104 includes a three-dimensional (3D) NAND flash memory device.

[0040] The memory controller 106 may be implemented by a microprocessor, a microcontroller (also known as a microcontroller unit (MCU)), a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a programmable logic device (PLD), a state machine, gate logic, discrete hardware circuits, and other suitable hardware, firmware, and / or software configured to perform various functions described in detail below.

[0041] The memory controller 106 is coupled to the memory device 104 and the host 108 and configured to control the memory device 104 according to some implementations. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108. In some implementations, the memory controller 106 is designed to operate in low duty cycle environments such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some implementations, the memory controller 106 is designed to operate in high duty cycle environments SSDs or embedded multimedia cards (eMMC) used as data storage for mobile devices such as smart phones, tablets, laptop computers, etc., and enterprise storage arrays. The memory controller 106 can be configured to control operations of the memory device 104, such as read, erase, and program operations, by providing instructions, such as read instructions, to the memory device 104. For example, memory controller 106 may be configured to provide read instructions to peripheral circuits of memory device 104 to control read operations. Memory controller 106 may also be configured to manage various functions related to data stored or to be stored in memory device 104, including, but not limited to, bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some implementations, memory controller 106 is further configured to process error correction codes (ECC) related to data read from or written to memory device 104. Any other suitable functions may also be performed by memory controller 106, such as formatting memory device 104.

[0042] The memory controller 106 can communicate with an external device (e.g., the host 108) according to a particular communication protocol. For example, the memory controller 106 may communicate with the external device through at least one of a variety of interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, and the like.

[0043] The memory controller 106 and the one or more memory devices 104 can be integrated into various types of storage devices that are included in the same package, such as a universal flash storage (UFS) package or an eMMC package. That is, the memory system 102 can be implemented and packaged into different types of end electronic products. In one example, as illustrated in FIG. 2A, the memory controller 106 and the single memory device 104 can be integrated into a memory card 202. The memory card 202 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 can further include a memory card connector 204 that couples the memory card 202 with a host (e.g., the host 108 in FIG. 1). In another example, as illustrated in FIG. 2B, the memory controller 106 and the multiple memory devices 104 can be integrated into an SSD 206. The SSD 206 may further include an SSD connector 208 that couples the SSD 206 to a host (eg, the host 108 in FIG. 1). In some implementations, the storage capacity and / or operating speed of the SSD 206 are greater than those of the memory card 202.

[0044] The memory controller 106 is configured to receive and send commands to and from the host 108 and to perform or carry out multiple functions and operations provided in this disclosure, which will be described below.

[0045] FIG. 3 shows a schematic circuit diagram of an exemplary memory device 300 including peripheral circuits according to some embodiments of the present disclosure. The memory device 300 can be an example of the memory device 104 in FIG. 1. It is noted that the NAND flash disclosed herein is merely an example of a memory device for illustrative purposes. It can include any suitable solid-state, non-volatile memory, such as NOR flash, FeRAM, PCM, MRAM, STT-RAM, or RRAM. The memory device 300 can include a memory cell array 301 and peripheral circuits 302 coupled to the memory cell array 301. The memory cell array 301 can be a NAND flash memory cell array in which memory cells 306 are provided in the form of an array of NAND memory strings 308 each extending vertically above a substrate (not shown). In some implementations, each NAND memory string 308 includes multiple memory cells 306 coupled in series and stacked vertically. Each memory cell 306 can hold a continuous analog quantity, such as a voltage or charge, that depends on the number of electrons captured within the area of ​​the memory cell 306. Each memory cell 306 can be either a floating gate type memory cell including a floating gate transistor or a charge trapping type memory cell including a charge trapping transistor.

[0046] In some implementations, each memory cell 306 is a single-level cell (SLC) that has two possible memory states and can therefore store one bit of data. For example, a first memory state "0" can correspond to a first range of voltages, and a second memory state "1" can correspond to a second range of voltages. In some implementations, each memory cell 306 is a multi-level cell (MLC) that can store two or more bits of data in four or more memory states. For example, an MLC can store two bits per cell, three bits per cell (also known as a triple-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to have a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to have one of three possible programming levels from an erased state by writing one of three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erased state.

[0047] As illustrated in FIG. 3, each NAND memory string 308 may include a source select gate (SSG) transistor 310 at its source end and a drain select gate (DSG) transistor 312 at its drain end. The SSG transistor 310 and the DSG transistor 312 may be configured to activate a selected NAND memory string 308 (column of the array) during read and program operations. In some implementations, the sources of the NAND memory strings 308 in the same block 304 are coupled through the same source line (SL) 314, e.g., a common SL. In other words, all the NAND memory strings 308 in the same block 304 have an array common source (ACS) according to some implementations. The drains of the DSG transistors 312 of each NAND memory string 308 are coupled to respective bit lines 316 through which data can be read or written via an output bus (not shown) according to some implementations. In some implementations, each NAND memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., above the threshold voltage of the DSG transistor 312) or a deselect voltage (e.g., 0V) to the gate of each DSG transistor 312 via one or more DSG lines 313 and / or by applying a select voltage (e.g., above the threshold voltage of the SSG transistor 310) or a deselect voltage (e.g., 0V) to the gate of each SSG transistor 310 via one or more SSG lines 315.

[0048] As illustrated in FIG. 3, the NAND memory strings 308 can be organized into multiple blocks 304, each of which can have a common source line 314 coupled to, for example, an ACS. In some implementations, each block 304 is the basic data unit for erase operations, i.e., all memory cells 306 on the same block 304 are erased at the same time. To erase memory cells 306 in a selected block 304, the source lines 314 coupled to the selected block 304 as well as to unselected blocks 304 in the same plane as the selected block 304 can be biased with an erase voltage (Vers), such as a positive high voltage (e.g., 20V or more). The memory cells 306 of adjacent NAND memory strings 308 can be coupled through word lines 318 that select which row of memory cells 306 are affected by read and program operations. In some implementations, each word line 318 is coupled to a page 320 of memory cells 306, which is the basic data unit for program and read operations. The bit size of a page 320 may relate to the number of NAND memory strings 308 coupled by word lines 318 in one block 304. Each word line 318 may include multiple control gates (gate electrodes) in each memory cell 306 in the respective page 320 and gate lines coupling the control gates. The peripheral circuitry 302 may be coupled to the memory cell array 301 through bit lines 316, word lines 318, source lines 314, SSG lines 315 and DSG lines 313. The peripheral circuitry 302 may include any suitable analog, digital and mixed signal circuitry for facilitating operation of the memory cell array 301 by applying and sensing voltage and / or current signals to and from each target memory cell 306 through the bit lines 316, word lines 318, source lines 314, SSG lines 315 and DSG lines 313. The peripheral circuitry 302 may include various types of peripheral circuits formed using metal oxide semiconductor (MOS) technology.

[0049] FIG. 4A illustrates a block diagram of an exemplary memory system 102 including a memory controller 106 and a memory device 104 according to some aspects of the present disclosure. As illustrated in FIG. 4A, the memory controller 106 can include a controller processor 408, such as a memory chip controller (MCC) or a memory controller unit (MCU). The controller processor 408 is configured to control modules that execute commands or instructions to perform functions disclosed in the present disclosure. The controller processor 408 can also be configured to control the operation of each peripheral circuit by generating and sending various control signals, such as a read command for a read operation. The controller processor 408 can also send clock signals with a desired frequency, period, and duty cycle to other peripheral circuits 302 to govern the operation of each peripheral circuit 302, for example, for synchronization. The memory controller 106 can further include a volatile controller memory 411 and a non-volatile controller memory. The volatile controller memory 411 may include a register or cache memory so that it does not have to retain the stored information after power is removed while allowing for faster access and processing speeds to read, write, or erase data stored therein. In some implementations, the volatile controller memory 411 includes a dynamic random access memory (DRAM), a static random access memory (SRAM). The non-volatile controller memory 413 can retain the stored information even after power is removed. In some implementations, the non-volatile controller memory 413 includes a NAND, a NOR, a FeRAM, a PCM, a MRAM, a STT-RAM, or a RRAM. The memory device 104 may include a memory cell array such as the memory cell array 301 in FIG. 3. In some implementations, the non-volatile controller memory 413 may not be provided in the memory controller 106, for example, the non-volatile controller memory 413 may be driven out of the memory controller 106 but coupled to the memory controller 106.In some implementations, the controller memory (e.g., 411 or 413) is configured to store an L2P address mapping table (e.g., 4271, 4273) corresponding to a file (e.g., 129).

[0050] 4B illustrates a block diagram of an example memory system 102 including a memory controller 106 and a memory device 104, in accordance with some aspects of the disclosure. As illustrated in FIG. 4B, the memory controller 106 can include a memory controller interface 429 configured to receive and send commands or instructions to and from a host (e.g., host 108 in FIG. 1). In some implementations, the memory controller interface 429 is coupled to receive and send commands or instructions to and from a controller processor 408 that cause the controller processor 408 to perform functions disclosed in the present disclosure.

[0051] The memory controller 106 may also include an update module 421 configured to generate and update the volatile L2P address mapping table 4271, the volatile merge log 4251, the non-volatile L2P mapping table 4273, and the non-volatile merge log 4253. The update module 421 may be implemented in firmware of the controller processor 408 through a firmware program. In some implementations, the update module 421 is configured to update the physical data blocks 431 and / or the metadata blocks 433 in the memory device 104. In some implementations, the update module 421 may be in or coupled to the controller processor 408 and controlled by the controller processor 408 to execute commands and instructions from the host 108. For example, the update module 421 is configured to execute a mapping update command received from the host 108 and update the volatile L2P address mapping table 4271 according to the mapping update command. In some implementations, the update module 421 is configured to update the volatile L2P address mapping table 4271 by rewriting the consecutive logical addresses of the merge LBA segment of the file to the volatile L2P address mapping table 4271. In some implementations, the update module 421 is configured to update the volatile L2P address mapping table 4271 by replacing the original logical addresses of the LBA segments of the file 129 with the new consecutive logical addresses of the merge LBA segment of the file, and changing the original mapping relationship between the original logical addresses of the LBA segments of the file and the physical addresses of the file to a new mapping relationship between the new consecutive logical addresses of the merge LBA segment of the file and the physical addresses of the file. The process of forming the consecutive logical addresses of the merge LBA segment of the file will be described below.Then, after updating the L2P address mapping table 4271, the update module 421 in the controller processor 408 will accordingly send an instruction to the host 108 confirming that the volatile L2P address mapping table 4271 has been updated, so that the host 108 may update the index node of the file in the host memory 110.

[0052] In some implementations, the volatile L2P address mapping table 4271 is configured to be stored and processed in the volatile controller memory 411 and sent to and updated in the non-volatile L2P address mapping table 4273 stored in the physical data block 431, so that the data is not erased after power off. In some implementations, after the system is resumed, the volatile L2P address mapping table 4271 in the volatile controller memory 411 can be loaded from the non-volatile L2P address mapping table 4273 in the physical data block 431 at any time for faster access and processing speed. In some implementations, the non-volatile L2P address mapping table 4273 can also be stored in the non-volatile controller memory 413 of the memory controller 106.

[0053] The merge logs (e.g., volatile merge log 4251 and non-volatile merge log 4253) are configured to record the mapping relationship between the L2P address mapping table (e.g., 4271 or 4273) and the physical addresses of the physical data blocks 431 before the update of the L2P address mapping table. In some implementations, the merge logs are configured to record the new mapping relationship between the new consecutive logical addresses of the merged LBA segments of the file 129 that respectively updated the L2P address mapping table and the physical addresses of the file 129. Thus, after a sudden power loss, the volatile L2P address mapping table 4271 may not have been updated yet and can be rebuilt or restored by using the non-volatile merge log 4253 and the physical addresses of the physical data blocks 431 after the system (e.g., 100) is resumed. It is noted that in some implementations, the update speed of the non-volatile merge log 4253 is faster than the non-volatile L2P address mapping table 4273 so that it may not cause excessive write amplification since it is a relatively small data compared to the non-volatile L2P address mapping table 4273 while it is already recorded during the sudden power loss. In particular, in response to the sudden power loss, the recovery module 423 in the controller processor 408 may scan the physical-to-logical (P2L) address mapping table 435 and the non-volatile merge log 4253 in the metadata block 433 in the memory device 104, and in response to the non-volatile merge log 4253 being updated, reconstruct the volatile L2P address mapping table 4271 according to the non-volatile merge log 4253 and the physical addresses of the physical data blocks 431 held before the sudden power loss. and in response to the non-volatile merge log 4253 not being updated, rebuilding the volatile L2P address mapping table 4271 according to the physical-to-logical (P2L) address mapping table 435 of the metadata block 433 and the physical addresses of the physical data block 431 that were retained before the sudden power loss.It is noted that the metadata block 433 is a relatively small portion of the data block in the memory cell array 301. The metadata block 433 is configured to store logical address information of the data stored in the physical data block 431. The logical address information is written to the metadata block 433 simultaneously when writing data to the physical data block 431, so that it can restore the data after a sudden power loss. In some implementations, the volatile merge log 4251 is configured to be stored and processed in the volatile controller memory 411, and sent to and updated in the non-volatile merge log 4253 stored in the physical data block 431, so that the data is not erased after power off. In some implementations, after the system is resumed, the volatile merge 4251 in the volatile controller memory 411 can be loaded from the non-volatile merge log 4253 in the physical data block 431 at any time for faster access and processing speed. In some implementations, the non-volatile merge log 4253 can also be stored in the non-volatile controller memory 413 of the memory controller 106. The recovery module 423 may be implemented in the firmware of the controller processor 408 through a firmware program.

[0054] FIG. 5 illustrates a block diagram of an exemplary system 100 including a host 108 and a memory controller 106 according to some aspects of the disclosure. As illustrated in FIG. 5, the host 108 may include a host interface 125, a host memory 110, and a host processor 112. The host interface 125 is configured to receive commands or instructions from a user to perform or execute a particular function or operation. The host memory 110 may store a logical address, such as a logical block address (LBA), of a file (e.g., file 129), and an index node 127 (e.g., inode) of the file. The host processor 112 may include or be coupled to an index node update module 121 (e.g., inode update module) and a merge LBA module 123. The index node update module 121 is configured to update the index node 127 of the file after the controller processor 408 (e.g., in FIG. 4A ) of the memory controller 106 sends an instruction to the host 108 confirming that the volatile L2P address mapping table 4271 has been updated. The index node update module 121 can also update the index node 127 of the file after receiving an indication that the physical data block 431 (e.g., in FIG. 4B ) has been updated. It is noted that an index node (e.g., an inode) may be a data structure in a Unix-style file system that describes a file system object such as a file or a directory. It can be a file data structure that stores information about any Linux file except its name and data. It stores metadata of the file, including the file size, the device on which the file is stored, the user and group IDs associated with the file, or the permissions required to access the file. In some implementations, the host processor 112 is configured to update the index node 127 of the file 129 by pointing the new LBA segment with the consecutive logical addresses of the merged LBA segment.

[0055] The merge LBA module 123 included in or coupled to the host processor 112 is configured to execute a merge LBA command to relocate the LBA segments (e.g., fragments of logical addresses in a logical block) of the file 129 to the merge LBA segments. For example, as shown in FIG. 6, the file A 129 may include one or more LBA segments (e.g., LBA segment 1, LBA segment 2, LBA segment 3..., LBA segment N). Every time the file is modified in the operation system, the number of LBA segments increases and the file is fragmented. Using a conventional e2defrag tool, as described above, it may need to read multiple LBA segments one by one and find the consecutive logical address blocks to write the segment new of the file. Then, the e2defrag tool will update the physical data blocks according to the segment new of the file. Therefore, every time the logical address block is updated, the physical data block is updated, thereby causing excessive write amplification. The merge LBA module 123 may execute the merge LBA command accordingly to relocate the LBA segments of the file 129 to the merge LBA segments as provided in this disclosure. Specifically, relocating the LBA segments of the file 129 includes rewriting all logical addresses of the LBA segments of the file 129 to consecutively ordered free or unused logical address blocks (e.g., free or unused LBA segments) to become consecutive logical address blocks (e.g., merge LBA segments). Unlike conventional e2defrag tools, the merge LBA segments will not be used to update physical data blocks (e.g., physical data block 431 in FIG. 4B). The merge LBA segments are only used to update the volatile L2P address mapping table 4271 in FIG. 4B. By doing so, write amplification is minimized since the physical data blocks are not updated every time a logical address block is updated.

[0056] After executing the merge LBA command, the host processor 112 may send a mapping update command to cause the controller processor (e.g., 408 in FIG. 4A) in the memory controller 106 to update the volatile L2P address mapping table 4271 according to the merged LBA segments. As illustrated in FIG. 7, the volatile L2P address mapping table 4271 with the originally non-contiguous and discrete logical addresses (e.g., LBA9, LBA11, LBA13, LBA18) corresponding to the logical addresses of the LBA segments in the file 129 (e.g., LBA9, LBA11, LBA13, LBA18) is updated to a contiguous logical address block (e.g., LBA114, LBA115, LBA116, LBA117). The physical addresses (e.g., PA333, PA337, PA339, PA440) of the updated volatile L2P address mapping table 4271 to the corresponding physical addresses of the physical data block 431 remain unchanged in the above update process. Thus, after the defragmentation process, the physical data blocks 431 are not written and remain the same.

[0057] 8 illustrates a block diagram showing an example defragmentation scheme under sudden power loss according to some aspects of the present disclosure. As described above, when a sudden power loss occurs, the volatile L2P address mapping table 4271 may not be updated or may not be able to complete a current update, and thus data may be lost because the physical data is not updated either. A metadata block (e.g., metadata block 433 in FIG. 4B) of a memory device (e.g., memory device 104) may have an old erroneous P2L mapping table (e.g., P2L address mapping table 435 in FIG. 4B) that records the physical addresses (e.g., LBA9, LBA11, LBA13, LBA18) of the old L2P address mapping table. Since the non-volatile merge log 4253 stores the mapping relationship between the P2L address mapping table 435 and the volatile L2P address mapping table 4271 after each update of the volatile L2P address mapping table 4271 (for example, LBA9 of P2L points to LBA114 of the new L2P, LBA11 of P2L points to LBA115 of the new L2P, LBA13 of P2L points to LBA116 of the new L2P, and LBA18 of P2L points to LBA117 of the new L2P), a new volatile L2P address mapping table 4271 can be reconstructed by using the non-volatile merge log 4253 and the retained P2L address mapping table 435 according to the mapping relationship.

[0058] 9 illustrates a flow chart of an example method for operating a memory controller according to some aspects of the disclosure. The memory controller may be any suitable memory controller disclosed herein, such as memory controller 106 in FIG. 4B. Method 900 may be implemented in part or in full by memory controller 106 as in FIG. 4A. It is understood that the operations illustrated in method 900 may not be exhaustive, and that other operations may occur before, after, or between any of the illustrated operations. Additionally, some of the operations may occur simultaneously or in a different order than illustrated in FIG. 9.

[0059] 9, method 900 begins at operation 902, in which a memory controller (e.g., memory controller 106 as in FIG. 4A) receives a mapping update command from a host (e.g., host 108 in FIG. 5). In some implementations, the mapping update command may cause memory controller 106 to initiate update module 421.

[0060] 9, the method 900 proceeds to operation 904, where an L2P address mapping table (e.g., volatile L2P address mapping table 4271 in FIG. 4B) stored in the memory controller 106 is updated according to the mapping update command. In some implementations, updating the L2P address mapping table includes rewriting consecutive logical addresses of merged LBA segments of a file (e.g., file 129 in FIGS. 5-7) to the L2P address mapping table.

[0061] 9, the method 900 proceeds to operation 906, where after updating the L2P address mapping table, an indication is sent to the host confirming that the L2P address mapping table has been updated. In some implementations, once updating the L2P address mapping table is completed, the update module is configured to send an instruction to the host through an interface (e.g., memory controller interface 429 in FIG. 4B). The host may then update the index node of the file stored in the host memory.

[0062] Further, the method 900 may further include an operation in which sudden power loss protection is implemented. Specifically, the method 900 may also include recording a mapping relationship between a P2L address mapping table (e.g., the P2L mapping table in FIG. 4B) and an L2P address mapping table in a metadata block (e.g., the metadata block 433 in FIG. 4B) in a merge log (e.g., the non-volatile merge log 4253 in FIG. 4B). After the sudden power loss, when the system is resumed, the method 900 may further include scanning the P2L address mapping table of the metadata block and the merge log. Then, in response to determining that the merge log has been updated, the L2P address mapping table is reconstructed according to the merge log and the P2L address mapping table of the metadata block. And, in response to determining that the merge log has not been updated, the L2P address mapping table is restored according to the P2L address mapping table of the metadata block. These operations may be implemented by the recovery module 423 as in FIG. 4B.

[0063] 10 illustrates a flowchart of an exemplary method for operating a host according to some aspects of the present disclosure. The host may be any suitable host disclosed herein. Method 1000 may be implemented in part or in full by host 108, such as in FIG. 5. It is understood that the operations illustrated in method 1000 may not be exhaustive, and that other operations may occur before, after, or between any of the operations illustrated. Additionally, some of the operations may occur simultaneously or in a different order than illustrated in FIG. 10.

[0064] Referring to FIG. 10, method 1000 begins with operation 1002 in which a merge LBA command is executed to relocate LBA segments of a file (e.g., file 129 as in FIG. 5) stored in a host memory (e.g., host memory 110 in FIG. 5) into a merge LBA segment. In some implementations, the merge LBA command may cause a host processor (e.g., host processor 112 in FIG. 5) to invoke a merge LBA module (e.g., merge LBA module 123 in FIG. 5). In some implementations, relocating the LBA segments of the file into the merge LBA segment includes rewriting the LBA segments of the file in a non-contiguous or discrete order of logical addresses into a merge LBA segment in a contiguous order of logical addresses. In some implementations, relocating the LBA segments of the file into the merge LBA segment includes sequentially reading the logical addresses of the LBA segments of the file before rewriting the logical addresses of the merge LBA segment to become a merge LBA segment with any LBA segments of the file.

[0065] 10, the method 1000 proceeds to operation 1004, where a mapping update command is sent to a memory controller (e.g., memory controller 106 in FIG. 4A) to cause a controller processor of the memory controller (e.g., controller processor 408 in FIG. 4A) to update an L2P address mapping table (e.g., volatile L2P address mapping table 4271 in FIG. 4B) according to the merged LBA segment. In some implementations, updating the L2P address mapping table includes rewriting contiguous logical addresses of the merged LBA segment of the file to the L2P address mapping table.

[0066] 10, the method 1000 proceeds to operation 1006, where an indication is received from the controller processor confirming that the L2P address mapping table has been updated. In some implementations, after receiving the indication, an index node update module (e.g., index node update module 121) is initiated.

[0067] As shown in FIG. 10, the method 1000 proceeds to operation 1008 where the index node of the file is updated after verifying that the L2P address mapping table has been updated.

[0068] The above description of specific implementations may be readily modified and / or adapted for various applications. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed implementations, based on the teaching and guidance presented herein.

[0069] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary implementations, but should be defined only in accordance with the following claims and their equivalents. [Explanation of symbols]

[0070] 100 Systems 102 Memory System 104 Memory Devices 106 Memory Controller 108 Host 110 Host Memory 112 Host Processor 121 Index Node Update Module 123 Merge LBA Module 125 Host Interface 127 index nodes 129 Files 202 Memory Card 204 Memory card connector 206 SSD 208 SSD Connector 300 Memory Devices 301 Memory Cell Array 302 Peripheral Circuit 304 Block 306 memory cells 308 NAND memory strings 310 Source Select Gate (SSG) Transistor 312 Drain Select Gate (DSG) Transistor 313 DSG line 314 Common Source Line 315 SSG Line 316 bit lines 318 Word Line 320 pages 408 Controller Processor 411 Volatile Controller Memory 413 Non-volatile Controller Memory 421 Update Module 423 Recovery Module 4251 Volatile Merge Log 4253 Non-volatile merge log 4271 Volatile Logical-to-Physical (L2P) Address Mapping Table 4273 Non-volatile L2P Address Mapping Table 429 Memory Controller Interface 431 Physical Data Blocks 433 Metadata Block 435 Physical-to-Logical (P2L) Address Mapping Table

Claims

1. a controller memory (411, 413) for storing a logical-to-physical (L2P) address mapping table (4271, 4273) corresponding to the file (129); Controlling the memory device (104) to receive a mapping update command; replacing original logical addresses of the logical block address (LBA) segments of said file (129) with new contiguous logical addresses of the merged LBA segments of said file (129); changing an original mapping relationship between the original logical addresses of the LBA segments of the file (129) and the physical addresses of the file (129) to a new mapping relationship between the new consecutive logical addresses of the merged LBA segments of the file (129) and the physical addresses of the file (129); a controller processor (408) configured to update the L2P address mapping table (4271, 4273) according to the mapping update command by A memory controller (106).

2. 2. The memory controller (106) of claim 1, wherein said controller memory (411, 413) comprises a volatile controller memory (411) for storing said L2P address mapping table (4271, 4273) corresponding to said file (129).

3. The controller memory (411, 413) 3. The memory controller (106) of claim 2, further comprising a non-volatile controller memory (413), wherein the controller processor (408) is configured to store the updated L2P address mapping table (4271, 4273) in the non-volatile controller memory (413) as a non-volatile L2P address mapping table (4273).

4. 4. The memory controller (106) of claim 1, wherein the controller processor (408) is configured to send an indication to a host (108) confirming that the L2P address mapping table (4271, 4273) has been updated.

5. 5. The memory controller (106) of claim 1, wherein the controller processor (408) is configured to generate a merge log (4251, 4253) by recording the new mapping relationship between the new consecutive logical addresses of the merged LBA segments of the file (129) and the physical addresses of the file (129).

6. 2. The memory controller (106) of claim 1, wherein in response to a sudden power loss, the controller processor (408) is configured to rebuild the volatile L2P address mapping table (4271) according to a merge log (4251, 4253) that records the new mapping relationship between the new consecutive logical addresses of the merged LBA segments of the file (129) and the physical addresses of the file (129) after the memory system (102) is resumed.

7. 7. The memory controller of claim 6, wherein the controller processor is configured to scan a physical-to-logical (P2L) address mapping table of a metadata block and the merge log, and in response to the merge log being updated, the controller processor is configured to reconstruct the L2P address mapping table according to the merge log.

8. a memory device (104) having a physical data block (431); A memory controller (106), a controller memory (411, 413) for storing a logical-to-physical (L2P) address mapping table (4271, 4273) corresponding to the file (129); Controlling the memory device (104) to receive a mapping update command; replacing original logical addresses of the logical block address (LBA) segments of said file (129) with new contiguous logical addresses of the merged LBA segments of said file (129); changing an original mapping relationship between the original logical addresses of the LBA segments of the file (129) and the physical addresses of the file (129) to a new mapping relationship between the new consecutive logical addresses of the merged LBA segments of the file (129) and the physical addresses of the file (129); a controller processor (408) configured to update the L2P address mapping table (4271, 4273) in accordance with the mapping update command by A memory system (102) comprising:

9. 9. The memory system (102) of claim 8, wherein said controller memory (411, 413) comprises a volatile controller memory (411) for storing said L2P address mapping table (4271, 4273) corresponding to said file (129).

10. The controller memory (411, 413) 9. The memory system (102) of claim 8, further comprising a non-volatile controller memory (413), wherein the controller processor (408) is configured to store the updated L2P address mapping table (4271, 4273) in the non-volatile controller memory (413) as a non-volatile L2P address mapping table (4273).

11. 11. The memory system (102) of claim 8, wherein the controller processor (408) is configured to send an indication to a host (108) confirming that the L2P address mapping table (4271, 4273) has been updated.

12. 12. The memory system (102) of claim 8, wherein the controller processor (408) is configured to generate a merge log (4251, 4253) by recording the new mapping relationship between the new consecutive logical addresses of the merged LBA segments of the file (129) and the physical addresses of the file (129).

13. 9. The memory system (102) of claim 8, wherein in response to a sudden power loss, the controller processor (408) is configured to rebuild the L2P address mapping table (4271, 4273) according to a merge log (4251, 4253) that records the new mapping relationship between the new consecutive logical addresses of the merged LBA segments of the file (129) and the physical addresses of the file (129) after the memory system (102) is resumed.

14. 14. The memory system (102) of claim 13, wherein the controller processor (408) is configured to scan a physical-to-logical (P2L) address mapping table (435) of a metadata block (433) and the merge log (4251, 4253), and in response to the merge log (4251, 4253) being updated, the controller processor (408) is configured to reconstruct the L2P address mapping table (4271, 4273) according to the merge log (4251, 4253).

15. 10. The memory system (102) of claim 8, wherein the memory device (104) comprises a three-dimensional (3D) NAND flash memory device.

16. A host (108), a host memory (110) configured to store a file (129); a host processor (112) configured to execute a merge LBA command to remap original logical addresses of the logical block address (LBA) segments of the file (129) to new contiguous logical addresses of the merge LBA segments of the file (129) and send a mapping update command; A memory system (102), comprising: a memory device (104) having a physical data block (431); A memory controller (106), a controller memory (411, 413) for storing a logical-to-physical (L2P) address mapping table (4271, 4273) corresponding to said file (129); Controlling the memory device (104) to receive the mapping update command; replacing the original logical addresses of the LBA segments of the file (129) with the new contiguous logical addresses of the merged LBA segments of the file (129); changing an original mapping relationship between the original logical addresses of the LBA segments of the file (129) and the physical addresses of the file (129) to a new mapping relationship between the new consecutive logical addresses of the merged LBA segments of the file (129) and the physical addresses of the file (129); a controller processor (408) configured to update the L2P address mapping table (4271, 4273) in accordance with the mapping update command; A system (100) comprising:

17. 17. The system (100) of claim 16, wherein said controller memory (411, 413) comprises a volatile controller memory (411) for storing said L2P address mapping table (4271, 4273) corresponding to said file (129).

18. 18. The system (100) of claim 16 or 17, wherein the host processor (112) is configured to remap the original logical addresses of the LBA segments of the file (129) to the new logical addresses of the merged LBA segments of the file (129) by rewriting all logical addresses of the LBA segments of the file (129) to free or unused LBA segments in consecutive order of logical addresses to become new consecutive logical addresses of the merged LBA segments of the file (129).

19. 19. The system (100) of claim 16, wherein the host processor (112) is configured to send the mapping update command to cause the memory controller (106) to update the L2P address mapping table (4271, 4273) according to new consecutive logical addresses of the merged LBA segments of the file (129).

20. 20. The system (100) of claim 16, wherein the host processor (112) is configured to receive an indication from the memory controller (106) confirming that the L2P address mapping table (4271, 4273) has been updated.

21. 21. The system (100) of claim 20, wherein the host processor (112) is configured to update an index node (127) of the file (129) after verifying that the L2P address mapping table (4271, 4273) has been updated.

22. 22. The system (100) of claim 21, wherein the host processor (112) is configured to update the index node (127) of the file (129) by pointing a new LBA segment to the new contiguous logical address of the merged LBA segment.

23. receiving a mapping update command from a host (108); replacing the original logical addresses of the LBA segments of the file (129) with new contiguous logical addresses of the merged LBA segments of the file (129); changing an original mapping relationship between the original logical addresses of the LBA segments of the file (129) and the physical addresses of the file (129) to a new mapping relationship between the new contiguous logical addresses of the merged LBA segments of the file (129) and the physical addresses of the file (129); updating a logical-physical (L2P) address mapping table (4271, 4273) corresponding to said file (129) according to said mapping update command by A method (900) for operating a memory controller (106), comprising:

24. sending an indication to said host (108) confirming that said L2P address mapping tables (4271, 4273) have been updated; 24. The method (900) of claim 23, further comprising:

25. recording the new mapping relationship between the new consecutive logical addresses of the merged LBA segments of the file (129) and the physical addresses of the file (129) in a merge log (4251, 4253); in response to a sudden power loss, rebuilding the L2P address mapping tables (4271, 4273) according to the merge logs (4251, 4253) after the memory system (102) is resumed; 25. The method (900) of claim 23 or 24, further comprising:

26. The step of reconstructing the L2P address mapping table (4271, 4273) scanning a physical-to-logical (P2L) address mapping table (435) of a metadata block (433) and said merge logs (4251, 4253); 26. The method (900) of claim 25, further comprising a step of reconstructing the L2P address mapping table (4271, 4273) in accordance with the merge log (4251, 4253) in response to determining that the merge log (4251, 4253) has been updated.

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