Display device

Abstract

To provide a semiconductor device which prevents delay or distortion of a signal output to a gate signal line in a selection period.SOLUTION: A semiconductor device comprises: a gate signal line; a first gate driver circuit and a second gate driver circuit for outputting a selection signal and a non-selection signal to the gate signal line; and a plurality of pixels connected electrically to the gate signal line and receiving the selection signal and the non-selection signal. In a period where the gate signal line is selected, both of the first and second gate driver circuits output the selection signal to the gate signal line. In a period where the gate signal line is not selected, one of the first and second gate driver circuits outputs the non-selection signal to the gate signal line and the other of the first and second gate driver circuits does not output the selection signal or the non-selection signal to the gate signal line.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The technical field relates to a semiconductor device having a gate driver circuit. [Background technology]

[0002] A display device driven by the active matrix method has elements that function as switches (transistors). A pixel portion having a plurality of pixels each having a source driver circuit and a gate driver and a driver circuit including a source driver circuit. The source driver circuit functions as a switch. When an element that functions as a gate driver is turned on, it outputs a video signal to the pixel in which it is located. The driver circuit controls the switching of an element that functions as a switch.

[0003] The gate driver circuit is provided adjacent to the pixel section. When a driver circuit is provided, the area occupied by the pixel portion may be biased toward one side of the display device. For this reason, a display device with a gate driver circuit divided into the left and right sides of the pixel area has been proposed. It has been done.

[0004] As an example, the configuration of a display device disclosed in Patent Document 1 is shown in FIG. In the device, a first gate driver circuit 5108 and a second gate driver circuit 5109 are provided in the left and right peripheral regions of the display area. The light driver circuits 5110 are arranged symmetrically on the left and right.

[0005] The first gate driver circuit 5108 is disposed in the left peripheral region of the display area. The first gate driver circuit 5108 drives the odd-numbered gate lines (GL1, GL3 to GL n+1 ) are connected to multiple shift registers (SRC1, SRC3) whose output terminals are connected to each other. , to SRCn+1 The second gate driver circuit 5110 is configured by The second gate driver circuit 5110 is disposed in the right peripheral region of the even-numbered pixel region. Gate lines (GL2, GL4, ..., GL n ) with each output terminal connected A number of shift registers (SRC2, SRC4, ..., SRC n )

[0006] The first gate driver circuit 5108 drives the pixels arranged in the odd-numbered rows of the pixel section 5102. The electrical connection between the pixel and the source driver circuit 5112 is controlled, and the second gate driver circuit 5110, pixels arranged in even-numbered rows of the pixel section 5102 and the source driver circuit 51 Twelve electrical connections are controlled. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] JP 2003-076346 A Summary of the Invention [Problem to be solved by the invention]

[0008] As in the display device described with reference to FIG. 58, the gate driver circuits are separated to the left and right of the pixel section. In a display device having a divided configuration, a gate line (also called a "gate signal line") is selected. During a period in which the first gate driver circuit and the second gate driver circuit are turned on (also referred to as a "selection period"). A signal is output to the gate line from one of the gate driver circuits. During the non-selection period (also referred to as the "non-selection period"), the first gate driver circuit and the second gate driver Therefore, no signal is output to the gate line from either driver circuit.

[0009] In one embodiment of the present invention, a signal output to a gate signal line during a selection period is delayed or undelayed. It is an object of the present invention to provide a semiconductor device with reduced leakage.

[0010] Alternatively, in one aspect of the present invention, a first gate driver circuit and a second gate driver circuit It is an object of the present invention to provide a semiconductor device in which deterioration of a transistor included in a circuit is suppressed.

[0011] Alternatively, in one embodiment of the present invention, the rise time or fall time of the potential of the gate signal line It is an object of the present invention to provide a semiconductor device with a short time. [Means for solving the problem]

[0012] One embodiment of the present invention is a gate signal line and a gate driver for outputting a selection signal and a non-selection signal to the gate signal line. The first gate driver circuit and the second gate driver circuit are electrically connected to the gate signal lines. and a plurality of pixels to which a selection signal and a non-selection signal are input, During a period in which a gate signal line is selected, the first gate driver circuit and the second gate driver circuit Both gate driver circuits output a selection signal to the gate signal line, and when the gate signal line is selected, During the period when the first gate driver circuit and the second gate driver circuit are not in operation, , a non-selection signal is output to the gate signal line, and the first gate driver circuit and the second gate driver The other driver circuit does not output a selection signal or a non-selection signal to the gate signal line.

[0013] The first gate driver circuit and the second gate driver circuit each have a plurality of pixels. The second insulating film 11 may be disposed with the pixel unit 11 sandwiched therebetween.

[0014] The semiconductor device also supplies a video signal to a pixel corresponding to the gate signal line to which the selection signal is output. The pixel may have a source driver circuit for writing the pixel data. Effect of the Invention

[0015] One aspect of the present invention is to provide a method for detecting a delay or distortion of a signal output to a gate signal line during a selection period. It is possible to provide a semiconductor device in which the above-mentioned problems are reduced.

[0016] Alternatively, one aspect of the present invention is a first gate driver circuit and a second gate driver circuit. It is possible to provide a semiconductor device in which deterioration of a transistor included therein is suppressed.

[0017] Alternatively, one embodiment of the present invention is a method for determining a rise time or a fall time of a potential of a gate signal line. It is possible to provide a semiconductor device having a short length. [Brief description of the drawings]

[0018] [Figure 1] 1A to 1C are a diagram illustrating an example of a configuration of a semiconductor device and a timing chart illustrating an example of the operation of the semiconductor device. [Diagram 2] 1A to 1C are diagrams illustrating an example of the operation of a semiconductor device. [Diagram 3] 1A to 1C are diagrams illustrating an example of the operation of a semiconductor device. [Figure 4] 1A to 1C are diagrams illustrating an example of the configuration and an example of the operation of a gate driver circuit. [Diagram 5] 5A to 5C are schematic diagrams showing examples of operations performed by a gate driver circuit. [Figure 6] 4 is a timing chart showing an example of the operation of the gate driver circuit. [Figure 7] 4 is a timing chart showing an example of the operation of the gate driver circuit. [Figure 8] 4 is a timing chart showing an example of the operation of the gate driver circuit. [Figure 9]1A to 1C are diagrams illustrating an example of the configuration and an example of the operation of a gate driver circuit. [Figure 10] 1A to 1C are diagrams illustrating an example of the configuration and an example of the operation of a gate driver circuit. [Figure 11] FIG. 2 is a diagram illustrating an example of the configuration of a gate driver circuit. [Figure 12] FIG. 4 is a diagram for explaining an example of the operation of a gate driver circuit. [Figure 13] FIG. 4 is a diagram for explaining an example of the operation of a gate driver circuit. [Figure 14] 1A to 1C are diagrams illustrating an example of the configuration and an example of the operation of a gate driver circuit. [Figure 15] FIG. 4 is a diagram for explaining an example of the operation of a gate driver circuit. [Figure 16] FIG. 1 is a diagram illustrating an example of a circuit diagram of a semiconductor device. [Figure 17] 1 is a timing chart showing an example of an operation of a semiconductor device. [Figure 18] 1A to 1C are diagrams illustrating an example of the operation of a semiconductor device. [Figure 19] 1A to 1C are diagrams illustrating an example of the operation of a semiconductor device. [Figure 20] 1A to 1C are diagrams illustrating an example of the operation of a semiconductor device. [Figure 21] 1A to 1C are diagrams illustrating an example of the operation of a semiconductor device. [Figure 22] 1 is a timing chart showing an example of an operation of a semiconductor device. [Figure 23] 1 is a timing chart showing an example of an operation of a semiconductor device. [Figure 24] FIG. 1 is a diagram illustrating an example of a circuit diagram of a semiconductor device. [Diagram 25] FIG. 1 is a diagram illustrating an example of a circuit diagram of a semiconductor device. [Figure 26] FIG. 1 is a diagram illustrating an example of a circuit diagram of a semiconductor device. [Figure 27] 1 is a timing chart showing an example of an operation of a semiconductor device. [Figure 28] 1A to 1C are diagrams illustrating an example of the operation of a semiconductor device. [Figure 29]1A to 1C are diagrams illustrating an example of the operation of a semiconductor device. [Diagram 30] 1 is a timing chart showing an example of an operation of a semiconductor device. [Diagram 31] FIG. 1 is a diagram illustrating an example of a circuit diagram of a semiconductor device. [Diagram 32] 1A to 1C are diagrams illustrating an example of the operation of a semiconductor device. [Diagram 33] 1A to 1C are diagrams illustrating an example of the operation of a semiconductor device. [Diagram 34] 1A to 1C are diagrams illustrating an example of the operation of a semiconductor device. [Diagram 35] 1A to 1C are diagrams illustrating an example of the operation of a semiconductor device. [Diagram 36] FIG. 1 is a diagram illustrating an example of a circuit diagram of a semiconductor device. [Figure 37] FIG. 1 is a diagram illustrating an example of a circuit diagram of a semiconductor device. [Figure 38] FIG. 1 is a diagram illustrating an example of a circuit diagram of a semiconductor device. [Figure 39] FIG. 1 is a diagram illustrating an example of a circuit diagram of a semiconductor device. [Diagram 40] FIG. 1 is a diagram illustrating an example of a circuit diagram of a semiconductor device. [Diagram 41] FIG. 1 is a diagram illustrating an example of a circuit diagram of a semiconductor device. [Diagram 42] 1A to 1C are diagrams illustrating an example of the operation of a semiconductor device. [Diagram 43] 1A to 1C are diagrams illustrating an example of the operation of a semiconductor device. [Diagram 44] 1A to 1C are diagrams illustrating an example of the operation of a semiconductor device. [Diagram 45] 1A to 1C are diagrams illustrating an example of the operation of a semiconductor device. [Figure 46] 1A and 1B are diagrams illustrating an example of a configuration of a display device and an example of a configuration of a pixel. [Figure 47] FIG. 1 is a diagram showing an example of a circuit diagram of a shift register. [Figure 48] FIG. 1 is a diagram showing an example of a circuit diagram of a shift register. [Figure 49] 11 is a timing chart showing an example of an operation of a shift register. [Figure 50]1A and 1B are a diagram showing an example of a configuration of a source driver circuit and a timing chart showing an example of an operation of the source driver circuit; [Figure 51] FIG. 2 is a diagram showing an example of a circuit diagram of a protection circuit. [Figure 52] FIG. 1 illustrates an example of a configuration of a semiconductor device provided with a protection circuit. [Diagram 53] 1A to 1C illustrate an example of a structure of a display device and an example of a structure of a transistor. [Figure 54] FIG. 1 illustrates an example of a configuration of a display device. [Figure 55] FIG. 1 is a diagram showing a layout of a semiconductor device. [Figure 56] 1A to 1C are diagrams illustrating examples of electronic devices. [Figure 57] 1A to 1C are diagrams illustrating an example of an electric device and an application example of a semiconductor device. [Figure 58] FIG. 1 is a diagram showing a configuration of a display device. [Figure 59] FIG. 13 is a circuit diagram of a semiconductor device of a comparative example. [Figure 60] FIG. 13 is a diagram showing calculation results by circuit simulation. [Figure 61] FIG. 13 is a diagram showing calculation results by circuit simulation. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] An embodiment of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following description, and the present invention is not limited to the following description without departing from the spirit and scope of the present invention. It will be easily understood by those skilled in the art that various modifications may be made to the form and details of the present invention. Therefore, the present invention should not be construed as being limited to the description of the following embodiments. In addition, when referring to the drawings, symbols indicating the same things in different drawings will be used. In addition, when indicating similar items between different drawings, Use the same hatch pattern and may not be signed.

[0020] The contents of each embodiment can be appropriately combined with each other. The contents of the embodiments can be substituted for each other as appropriate.

[0021] In addition, the term "kth" (k is a natural number) used in this specification is intended to avoid confusion of the components. The numbers are added to avoid confusion and are not intended to be limiting.

[0022] Generally, the difference in electric potential between two points (also called potential difference) is called voltage. However, In electronic circuits, the potential of a certain point and the reference potential (also called the reference potential) are The unit of voltage and potential is the difference in potential between the object and the object. V) may be used. Therefore, in this specification, unless otherwise specified, The potential difference between the potential and a reference potential may be used as the voltage at that point.

[0023] In this specification, a transistor has at least three terminals (source, drain, and gate), and the potential of one terminal controls the conduction between the other two terminals. In addition, the source and drain of a transistor may be different depending on the transistor structure and operating conditions. Rains may be interchangeable.

[0024] The source may refer to a part or the whole of a source electrode, or a part or the whole of a source wiring. In addition, the source electrode and the source wiring are not differentiated from each other. A conductive layer that functions both as a drain and a drain line is sometimes called a source. This refers to all or a part of the drain electrode, or all or a part of the drain wiring. In addition, the drain electrode and the drain wiring are not distinguished from each other, and both the drain electrode and the drain wiring are treated as the same. A conductive layer having a function of forming a gate electrode is sometimes called a drain. It refers to a part or the whole of the gate wiring. A conductive layer that functions as both a gate electrode and a gate wiring without distinguishing between the electrode and the gate wiring is sometimes called a gate.

[0025] In this specification, "A and B are connected" means that A and B are directly connected. In addition to those that are connected to the power source, those that are electrically connected to the power source are also included. A and B are connected via an element that functions as a switch, such as a transistor, and the switch When an element that functions as a resistor is in a conductive state, A and B have approximately the same potential. A and B are connected through a resistor, and the potential difference generated across the resistor element is In cases where the level of the circuitry is such that it does not affect the intended operation of the circuit, If the part between A and B can be regarded as the same node, It is said that the two are connected.

[0026] In this specification, the term "generally" refers to errors due to noise and process variations. This includes various errors such as errors due to variations in the manufacturing process of the elements, and measurement errors. It shall be so.

[0027] In this specification, the potential of an L level signal (also called an "L signal") is defined as V1. The potential of the H-level signal (also called the "H signal") is V2 (V2>V1). When describing "potential of L signal", "potential of L level", or "voltage V1", The potential is assumed to be approximately V1, and the term "potential of the H signal," "potential of the H level," or "voltage V When "2" is written, it is assumed that these potentials are approximately V2.

[0028] (Embodiment 1) In this embodiment, a semiconductor device having a gate driver circuit (also called a "gate driver") is The semiconductor device will be described with reference to Figs. 1(A) to 3(C).

[0029] FIG. 1A shows an example of the structure of a semiconductor device having a gate driver circuit. 1(B) is a timing chart showing an example of the operation of the semiconductor device. In addition to the gate driver circuit, the device also has a source driver circuit (also called a "source driver"). . ), a control circuit, etc.

[0030] In FIG. 1A, the semiconductor device includes a pixel section 50 and a first gate driver circuit 51. , a second gate driver circuit 52, and a first gate driver circuit 51 and a second gate driver The driver circuit 52 has a gate line 54 (also called a "gate signal line"). In FIG. 1(A), a semiconductor device includes a plurality of gate lines G1 to G m (m is a natural number) Of these, gate line G i ~Gate line G i+2 (i is one of 1 to m-2) .

[0031] When the gate line 54 is selected, the gate driver circuit 51 and the gate driver circuit 52 Thus, the gate driver circuit 51 and the gate When an H signal is input from both the gate driver circuits 52, the potential of the gate line 54 The rise time or fall time of the signal can be shortened, and the signal output to the gate line 54 can be This can reduce delay or distortion of the signal being transmitted.

[0032] On the other hand, when the gate line 54 is not selected, the gate driver circuit 51 and the gate driver An L signal is output from one side of the circuit 52 to the gate line 54, and a signal Therefore, some or all of the transistors in the other gate driver circuit are not output. can turn everything off.

[0033] An example of the operation of the semiconductor device shown in FIG. 2(C) show the half-frames in the kth frame, and Fig. 3(A) to Fig. 3(C) show the half-frames in the k+1th frame. 1 shows an example of the operation of a conductor device.

[0034] In addition, in FIG. 2(A) to FIG. 3(C), the arrows indicate the gate driver circuit (the first gate The driver circuit 51 or the second gate driver circuit 52 outputs a signal to the gate line 54. The cross mark indicates that the gate driver circuit does not output a signal to the gate line 54. Taste.

[0035] Here, the direction of the arrow depends on the type of signal that the gate driver circuit outputs to the gate line 54. The gate driver circuit outputs a signal (for example, a non-selection signal) to the gate line 54. When outputting, the direction of the arrow is from the gate line 54 to the gate driver circuit. On the other hand, the gate driver circuit supplies a signal other than the above signal (for example, a non-selection signal) to the gate line 54. When outputting a signal (e.g., a selection signal), the direction of the arrow should be oriented from the gate driver circuit to the gate The direction is toward line 54.

[0036] As shown in FIG. 2A, in the kth frame, the gate line G i is selected and the gate line G i+1 and gate line G i+2 If is not selected (period k_ i ), The gate driver circuit 51 and the gate driver circuit 52 are connected to the gate line G i The H signal is output. In addition, the gate driver circuit 51 supplies the gate line G i+1 and gate line G i+2 L letter A signal is output from the gate driver circuit 52 to the gate line G i+1 and gate line G i+2 To believe Therefore, some or all of the transistors in the gate driver circuit 52 are not output. You can turn it off.

[0037] Next, as shown in FIG. 3A, in the k+1th frame, the gate line G i is selected , gate line G i+1 and gate line G i+2 If is not selected (period k+1 in Figure 1(B) _ i ), the gate driver circuit 51 and the gate driver circuit 52 are connected to the gate line G i To The gate driver circuit 51 outputs a gate line G i+1 and gate line G i+2 No signal is output from the gate driver circuit 52 to the gate line G i+1 and Gate line G i+2 Therefore, the transistor of the gate driver circuit 51 Some or all of the controllers may be turned off.

[0038] Similarly, as shown in FIG. 2B, in the k-th frame, the gate line G i+1 is selected The gate line G i and gate line G i+2 When not selected, the gate driver circuit 51 and and the gate driver circuit 52 to the gate line G i+1 A high signal is output to the gate driver. Driver circuit 51 to gate line G i and gate line G i+2 The L signal is output to the gate driver. From the driver circuit 52 to the gate line G i and gate line G i+2 Therefore, no signal is output to the Some or all of the transistors in the gate driver circuit 52 can be turned off.

[0039] Next, as shown in FIG. 3B, in the k+1th frame, the gate line G i+1 Selected The gate line G i and gate line G i+2 When the gate driver circuit 51 is not selected, and from the gate driver circuit 52 to the gate line G i+1 An H signal is output to the gate. From the driver circuit 51 to the gate line G i and gate line G i+2 No signal is output to the gated Driver circuit 52 to gate line G i and gate line G i+2 Therefore, an L signal is output to Some or all of the transistors in the gate driver circuit 51 can be turned off. .

[0040] Similarly, as shown in FIG. 2C, in the kth frame, the gate line G i+2 is selected The gate line G i and gate line G i+1 When not selected, the gate driver circuit 51 and and the gate driver circuit 52 to the gate line G i+2 A high signal is output to the gate driver. Driver circuit 51 to gate line G i and gate line G i+1 The L signal is output to the gate driver. From the driver circuit 52 to the gate line G i and gate line G i+1 Therefore, no signal is output to the Some or all of the transistors in the gate driver circuit 52 can be turned off.

[0041] Next, as shown in FIG. 3C, in the k+1th frame, the gate line G i+2 Selected The gate line G i and gate line G i+1 When the gate driver circuit 51 is not selected, and from the gate driver circuit 52 to the gate line G i+2 An H signal is output to the gate. From the driver circuit 51 to the gate line G i and gate line G i+1 No signal is output to the gated Driver circuit 52 to gate line G i and gate line G i+1 Therefore, an L signal is output to Some or all of the transistors in the gate driver circuit 51 can be turned off. .

[0042] In this manner, the unselected gate lines 54 are connected to the gate driver circuit 51 and the gate Since no signal is output from one of the driver circuits 52, the gate driver circuit It is possible to turn off some or all of the transistors in the This can suppress deterioration of the star.

[0043] (Embodiment 2) In this embodiment, the configuration and operation of a gate driver circuit will be described.

[0044] <Gate driver circuit configuration> The configuration of the gate driver circuit will be described with reference to FIG.

[0045] FIG. 4A shows an example of the configuration of a gate driver circuit. In FIG. 4A, the gate driver circuit includes a circuit 10A and a circuit 10B. The figure shows a case in which the gate driver circuit has two circuits, circuit 10A and circuit 10B. The circuit may have three or more circuits including circuit 10A and circuit 10B.

[0046] The circuit 10A is connected to a wiring 11, and the circuit 10B is connected to a wiring 11.

[0047] A signal is input to the wiring 11 from the circuit 10A or the circuit 10B. The wiring 11 serves as a signal line. Note that a signal is input to the wiring 11 from a circuit other than the circuit 10A and the circuit 10B. may be input.

[0048] When the gate driver circuit of FIG. 4A is used in a display device having a pixel portion, The line 11 is arranged to extend to the pixel portion, and is connected to the transistors (e.g., In this case, the wiring 11 has a function as a gate line (also called a "gate signal line"), a scanning line, or a power supply line. do.

[0049] Alternatively, a constant voltage is supplied to the wiring 11 from the circuit 10A or the circuit 10B. 10A and 10B. A voltage may be input to line 11 .

[0050] Next, the functions of the circuits 10A and 10B will be described.

[0051] The circuit 10A determines the timing for outputting a signal (for example, a selection signal or a non-selection signal) to the wiring 11. Alternatively, the circuit 10A has a function of controlling the switching of the wiring 11. Alternatively, the circuit 10A may have a function of controlling the timing of a signal being transmitted to the wiring 11 for a certain period of time. In another period, a different signal (e.g., a selection signal) is output to the wiring 11. Alternatively, the circuit 10A has a function of outputting a signal to the wiring 11 during a certain period. (for example, a selection signal or a non-selection signal) and outputs a signal to the wiring 11 in another period. It has the function of not

[0052] In this way, the circuit 10A has a function as a driver circuit or a control circuit. The circuit 10A may output a further signal to the wiring 11. In this case, the circuit 10A may Three or more types of signals can be output on line 11.

[0053] The circuit 10B determines the timing for outputting a signal (for example, a selection signal or a non-selection signal) to the wiring 11. Alternatively, the circuit 10B has a function of controlling the switching of the wiring 11. Alternatively, the circuit 10B has a function of controlling the timing of a signal supplied to the wiring 11 for a certain period of time. In another period, a different signal (e.g., a selection signal) is output to the wiring 11. Alternatively, the circuit 10B has a function of outputting a signal to the wiring 11 for a certain period. (for example, a selection signal or a non-selection signal) and outputs a signal to the wiring 11 in another period. It has the function of not

[0054] In this way, the circuit 10B has a function as a driver circuit or a control circuit. The circuit 10B may output a further signal to the wiring 11. In this case, the circuit 10B Three or more types of signals can be output on line 11.

[0055] <Gate driver circuit operation> The operation of the gate driver circuit in FIG. 4(A) will be described with reference to FIG. 4(B) and FIG. 5(A) to FIG. This will be explained with reference to I).

[0056] FIG. 4B shows an example of the operation of the gate driver circuit. In each operation performed by the driver circuit, the output signal OUTA of the circuit 10A and the output signal OUTB of the circuit 10B are 5(A) to 5(I) show the gate driver circuit of FIG. 1A to 1C are schematic diagrams corresponding to examples of operations performed by the

[0057] In the gate driver circuit of FIG. 4A, each of the circuit 10A and the circuit 10B is When a signal (e.g., a non-selection signal) is output to line 11, the same applies to the circuits 10A and 10B. In each case, a signal other than the signal in question (for example, a selection signal) is output to the wiring 11. Each of the circuits 10A and 10B transmits a signal (for example, a non-selection signal and a selection signal) to the wiring 11. By combining with and without output, the nine operations shown in Figure 4(B) can be performed. It can be done.

[0058] In this embodiment, the above nine operations will be described. The driver circuit does not need to perform all nine operations, but can select some of the nine operations. In addition, the gate driver circuit in FIG. 4(A) can perform operations other than these nine operations. This is also fine.

[0059] In FIG. 4B, a circle indicates that a circuit (the circuit 10A or the circuit 10B) is connected to the wiring 11. The symbol "◎" indicates that the circuit is connected to the wiring 11. It means that a signal other than the signal in question (for example, a selection signal) is output. "X" indicates that the circuit This means that no signal (for example, a non-selection signal or a selection signal) is output to the wiring 11.

[0060] In the schematic diagrams of FIG. 5(A) to FIG. 5(I), the arrows indicate a circuit (circuit 10A or circuit 10B) means that the circuit outputs a signal to wire 11, and the cross means that the circuit outputs a signal to wire 11. Here, the arrows indicate the type of signal that the circuit outputs to the wiring 11. When the circuit outputs a signal (for example, a non-selection signal) to the wiring 11, The direction of the arrow is the direction from the wiring 11 to the circuit. On the other hand, the circuit transmits the above signal ( If you want to output a signal (e.g., a selection signal) different from the non-selection signal, the direction of the arrow is defined as the direction from the circuit to the wiring 11.

[0061] In the schematic diagrams of FIG. 5(A) to FIG. 5(I), the direction of the arrows indicates the direction of the current and the current This does not mean that a signal is generated from the circuit (circuit 10A or circuit 10B) to the wiring 11. The direction of the current is determined by the potential of the wiring 11. In addition, when the potential of the signal output from the circuit is approximately equal to the potential of the wiring 11, a current is generated. The current may not be accurate or may be very small.

[0062] An example of the operation of the gate driver circuit in FIG. 4(A) will be described below.

[0063] In operation 1 of FIG. 5A, the circuit 10A outputs a signal (for example, a non-selection signal) to the wiring 11. Meanwhile, the circuit 10B outputs a signal (for example, a non-selection signal) to the wiring 11. In FIG. 2, the circuit 10A outputs a signal (e.g., a non-selection signal) to the wiring 11, and the circuit 10B outputs a non-selection signal to the wiring 12. In operation 3 of FIG. 5C, the circuit 10A does not output a signal to the wiring 11. Instead, the circuit 10B outputs a signal (for example, a non-selection signal) to the wiring 11. In operation 4, the circuit 10A does not output a signal to the wiring 11, and the circuit 10B outputs a signal to the wiring 11. Don't force it.

[0064] In operation 5 of FIG. 5(E), the circuit 10A outputs another signal (e.g., a selection signal) to the wiring 11. The circuit 10B outputs another signal (for example, a selection signal) to the wiring 11. In operation 6, circuit 10A outputs another signal (e.g., a select signal) on line 11, and circuit 10 In operation 7 of FIG. 5G, the circuit 10A does not output a signal to the wiring 11. Instead, the circuit 10B outputs a different signal (for example, a selection signal) to the wiring 11. In operation 8 of (H), the circuit 10A outputs a signal (for example, a non-selection signal) to the wiring 11. The line 10B outputs another signal (for example, a selection signal) to the wiring 11. The circuit 10A outputs another signal (e.g., a selection signal) to the wiring 11, and the circuit 10B outputs a 11 (for example, a non-selection signal).

[0065] As described above, the gate driver circuit in FIG. 4A can perform various operations. Next, the advantages of each operation will be described.

[0066] In the operations 1 and 5, the circuit 10A and the circuit 10B output the same signal to the wiring 11. This allows the potential of the wiring 11 to be a stable value with less noise. For example, A signal that should not be written to the pixel connected to the wiring 11 (for example, a signal that should not be written to a pixel in another row) It is possible to prevent the input video signal from being written. It is possible to prevent the potential of the video signal held by the connected pixel from changing. As a result, the display quality of the display device can be improved.

[0067] In addition, in the operations 1 and 5, the circuit 10A and the circuit 10B output the same signal to the wiring 11. By applying a voltage to the wiring 11, the change in the potential of the wiring 11 is made steeper (for example, the rise time is made shorter). Therefore, the potential of the wiring 11 can be prevented from becoming dull. For example, a pixel connected to the wiring 11 may be written with a voltage that should not be written. This prevents a new signal (e.g., a video signal input to the pixels of the previous row) from being written. As a result, crosstalk can be reduced, improving the display quality of the display device. It is possible to improve the

[0068] In operations 8 and 9, the circuit 10A and the circuit 10B supply different signals (e.g. , a selection signal, and a non-selection signal), the potential of the wiring 11 is changed by the output of the circuit 10A. The potential of the signal input from the input terminal 10B can be set to a potential between the potential of the signal output from the circuit 10B. Therefore, the potential of the wiring 11 can be controlled with high precision.

[0069] In operations 2, 3, 6, and 7, one of the circuits 10A and 10B By outputting a signal to the wiring 11, the other of the circuit 10A and the circuit 10B does not output a signal. Therefore, the transistors in the circuits that do not output the signal can be turned off. As a result, deterioration of the transistor can be suppressed.

[0070] In the operation 4, since no signal is output from the circuit 10A and the circuit 10B to the wiring 11, The transistors in the circuit 10A and the circuit 10B can be turned off. This makes it possible to suppress deterioration of the transistor.

[0071] As described above, in the operations 2, 3, 4, 6, and 7, the transistors are degraded. Since the oxidization can be suppressed, an amorphous semiconductor or Materials that are prone to deterioration, such as non-single crystal semiconductors such as microcrystalline semiconductors, organic semiconductors, or oxide semiconductors Therefore, the number of steps can be reduced and the yield can be improved when manufacturing a semiconductor device. In addition, the manufacturing method of the semiconductor device can be easily performed. Therefore, the display device can be made larger.

[0072] In addition, the degradation of the transistors is suppressed in operations 2, 3, 4, 6, and 7. Therefore, the channel width of the transistor can be increased to prevent degradation of the transistor. This allows the transistor channel width to be made smaller. In particular, the gate driver circuit of this embodiment When the above-mentioned is used in a display device, the layout area of ​​the gate driver circuit can be reduced. Therefore, the pixel resolution can be increased.

[0073] As described above, in the operations 2, 3, 4, 6, and 7, the transistor The channel width of the gate driver can be reduced, reducing the load on the gate driver circuit. Therefore, a circuit ( For example, the current supply capacity of the external circuit can be reduced. The size of the circuit that supplies the signal is reduced, or the signal is used as a circuit that supplies the signal. This reduces the number of IC chips required and reduces the load on the gate driver circuit. This allows the power consumption of the gate driver circuit to be reduced.

[0074] Next, the operation of the gate driver circuit of FIG. 4(A) is shown in FIG. 5(A) to FIG. 5(I). Timing chart for combining some of the operations 1 to 9 This is explained below.

[0075] Here, the timing chart showing the operation of the gate driver circuit in FIG. 4A includes a plurality of In each period, or in the transition from one period to another, The gate driver circuit of FIG. 5 performs one of the operations 1 to 9 shown in FIG. 5(A) to FIG. 5(I). The gate driver circuit of FIG. 4(A) can be implemented as shown in FIG. 5(A) to FIG. 5(I). Operations other than operations 1 to 9 shown in the above may be performed.

[0076] 6(A) to 6(L) are timing charts showing an example of the operation of the gate driver circuit. In the timing charts of FIG. 6(A) to FIG. 6(L), the period a, the period b, and the period c In addition, there is a period d. Periods a to d are arranged in this order, but the order of Periods a to d is not limited to this. Furthermore, the timing chart may include periods other than periods a to d.

[0077] In the timing charts of FIG. 6(A) to FIG. 6(L), the solid lines indicate the circuit (circuit 10 A or circuit 10B) outputs a signal to wiring 11, and the dotted line indicates that the circuit is This means that no signal is being output to 1.

[0078] With reference to the timing chart shown in FIG. 6(A), the period a and the transition from the period a to the period b Figure 4 shows the period a, the period b transitioning from period b to period c, period c, and period d. The operation of the gate driver circuit (A) will now be described.

[0079] In period a, the period from period b to period c, period c, and period d, as shown in FIG. 4(A), The gate driver circuit performs operation 2 in FIG. 5B. That is, from period a, period b to period c During the period when the signal is changed to the reference signal, the period c, and the period d, the circuit 10A outputs a signal (e.g., The circuit 10B outputs a non-selection signal, and the circuit 10B does not output a signal to the wiring 11.

[0080] During the transition from period a to period b and during period b, the gate driver The circuit performs operation 6 in FIG. 5(F). That is, during the period from period a to period b, and during the period In FIG. 1B, the circuit 10A outputs another signal (e.g., a selection signal) to the wiring 11, and the circuit 10 B does not output a signal to wire 11.

[0081] In this way, there is period a, the transition from period a to period b, period b, and the transition from period b to period c. During the transition period, period c, and period d, the circuit 10B does not output a signal to the wiring 11. Therefore, deterioration of the transistor included in the circuit 10B can be suppressed. In the circuit 10B, a switch for not outputting a signal is provided, or a transistor is By simply designing the circuit, such as by turning off the .

[0082] In the timing chart shown in FIG. 6A, during a period a, period b, period b transitioning to period c, period c, and period d At least one of the circuits 10A does not need to output a signal to the wiring 11.

[0083] As shown in FIG. 6B, in the period from period a to period b, the circuit 10B In this case, a different signal (for example, a selection signal) may be output to the wiring 11. This makes it possible to make the change in potential of 1 steeper.

[0084] As shown in FIG. 6C, the circuit 10B supplies a signal (e.g., For example, a non-selection signal is output, and during the period from period a to period b, a different signal is output to the wiring 11. In this way, the potential of the wiring 11 can be rapidly changed. It can be made steeper.

[0085] As shown in FIG. 6D, the circuit 10B is in a state where the period a is changed to the period b, and During the period b, another signal (for example, a selection signal) may be output to the wiring 11. This allows the change in potential of the wiring 11 to be made steeper.

[0086] As shown in FIG. 6E, the circuit 10B supplies a signal (e.g., For example, a non-selection signal is output, and during the period from period a to period b and during period b, Another signal (for example, a selection signal) may be output to the wiring 11. This allows the change in position to be made steeper.

[0087] Also, as shown in FIG. 6(F), in the period from period b to period c, the circuit 10B In this case, a signal (for example, a non-selection signal) may be output to the wiring 11. This makes it possible to make the change in potential of the electrode sharper.

[0088] As shown in FIG. 6G, in the period from period b to period c, the circuit 10B In the period b, a signal (for example, a non-selection signal) is output to the wiring 11. In this way, the potential of the wiring 11 can be rapidly changed. It can be made steeper.

[0089] As shown in FIG. 6H, the circuit 10B is in a state where the period b is changed to the period c, and During the period c, a signal (for example, a non-selection signal) may be output to the wiring 11. This allows the change in potential of the wiring 11 to be made steeper.

[0090] As shown in FIG. 6(I), the circuit 10B is in a state where the period b is changed to the period c, and During period c, a signal (for example, a non-selection signal) is output to the wiring 11, and during period b, Another signal (for example, a selection signal) may be output to the wiring 11. This allows the change in position to be made steeper.

[0091] Also, as shown in FIG. 6(J), in the period from period a to period b, the circuit 10B Then, another signal (for example, a selection signal) is output to the wiring 11, and the period b is changed to the period c. During this period, a signal (for example, a non-selection signal) may be output to the wiring 11. This allows the change in potential of the wiring 11 to be made steeper.

[0092] As shown in FIG. 6K, the circuit 10B transitions from period a and period b to period c. During the period a to b, a signal (for example, a non-selection signal) is output to the wiring 11. During the period b when the signal is changed to the first signal, another signal (e.g., a selection signal) is output to the wiring 11. This allows the change in potential of the wiring 11 to be made steeper.

[0093] As shown in FIG. 6(L), the circuit 10B transitions from period a and period b to period c. During periods a and c, a signal (for example, a non-selection signal) is output to the wiring 11. During the period from period a to period b, and during period b, another signal (e.g., a selection signal ) may be output. This allows the change in potential of the wiring 11 to be made steeper.

[0094] In the above description, the selection signal and the non-selection signal are These are just examples of signals to be output, and may be different from each other.

[0095] Next, the operation of the gate driver circuit of FIG. 4(A) is shown in FIG. 5(A) to FIG. 5(I). 6(A) to 6(L) when some of the operations 1 to 9 are performed in combination. The different timing diagrams are explained below.

[0096] 7(A) to 7(L) are timing charts showing an example of the operation of the gate driver circuit. It is.

[0097] With reference to the timing chart shown in FIG. 7(A), the period a, the transition from the period a to the period b, Figure 4 shows the period a, the period b transitioning from period b to period c, period c, and period d. The operation of the gate driver circuit (A) will now be described.

[0098] In period a, the period from period b to period c, period c, and period d, as shown in FIG. 4(A), The gate driver circuit performs operation 3 of FIG. 5(C). That is, from period a, period b to period c During the period from the time when the signal is changed to ... The circuit 10B outputs a signal (for example, a non-selection signal) to the wiring 11.

[0099] During the transition from period a to period b and during period b, the gate driver The circuit performs operation 7 in FIG. 5(G). That is, during the period from period a to period b, and during the period In FIG. 1B, the circuit 10A does not output a signal to the wiring 11, and the circuit 10B outputs a different signal to the wiring 11. (e.g., a selection signal).

[0100] In this way, there is period a, the transition from period a to period b, period b, and the transition from period b to period c. During the transition period, period c, and period d, the circuit 10A does not output a signal to the wiring 11. Therefore, deterioration of the transistor included in the circuit 10A can be suppressed. In the circuit 10A, a switch is provided to prevent a signal from being output, or a transistor is provided. By simply designing the circuit, such as by turning off the .

[0101] In the timing chart shown in FIG. 7A, during a period a, during a transition from period a to period b, period b, period b transitioning to period c, period c, and period d At least one of the circuits 10B does not need to output a signal to the wiring 11.

[0102] As shown in FIG. 7B, in the period from period a to period b, the circuit 10A In this case, a different signal (for example, a selection signal) may be output to the wiring 11. This makes it possible to make the change in potential of 1 steeper.

[0103] As shown in FIG. 7C, the circuit 10A supplies a signal (e.g., For example, a non-selection signal is output, and during the period from period a to period b, a different signal is output to the wiring 11. In this way, the potential of the wiring 11 can be rapidly changed. It can be made steeper.

[0104] As shown in FIG. 7D, the circuit 10A is in a state where the period a is changed to the period b, and During the period b, another signal (for example, a selection signal) may be output to the wiring 11. This allows the change in potential of the wiring 11 to be made steeper.

[0105] As shown in FIG. 7E, the circuit 10A supplies a signal (e.g., For example, a non-selection signal is output, and during the period from period a to period b and during period b, Another signal (for example, a selection signal) may be output to the wiring 11. This allows the change in position to be made steeper.

[0106] Also, as shown in FIG. 7(F), in the period from period b to period c, the circuit 10A In this case, a signal (for example, a non-selection signal) may be output to the wiring 11. This makes it possible to make the change in potential of the electrode sharper.

[0107] Furthermore, as shown in FIG. 7G, in the period from period b to period c, the circuit 10A In the period b, a signal (for example, a non-selection signal) is output to the wiring 11. In this way, the potential of the wiring 11 can be rapidly changed. It can be made steeper.

[0108] As shown in FIG. 7H, the circuit 10A is in a state where the period b is changed to the period c, and During the period c, a signal (for example, a non-selection signal) may be output to the wiring 11. This allows the change in potential of the wiring 11 to be made steeper.

[0109] As shown in FIG. 7(I), the circuit 10A is in a state where the period b is changed to the period c, and During period c, a signal (for example, a non-selection signal) is output to the wiring 11, and during period b, Another signal (for example, a selection signal) may be output to the wiring 11. This allows the change in position to be made steeper.

[0110] Also, as shown in FIG. 7(J), in the period from period a to period b, the circuit 10A Then, another signal (for example, a selection signal) is output to the wiring 11, and the period b is changed to the period c. During this period, a signal (for example, a non-selection signal) may be output to the wiring 11. This allows the change in potential of the wiring 11 to be made steeper.

[0111] Also, as shown in FIG. 7(K), the circuit 10A transitions from period a and period b to period c. During the period a to b, a signal (for example, a non-selection signal) is output to the wiring 11. During the period b when the signal is changed to the first signal, another signal (e.g., a selection signal) is output to the wiring 11. This allows the change in potential of the wiring 11 to be made steeper.

[0112] Also, as shown in FIG. 7(L), the circuit 10A transitions from period a and period b to period c. During periods a and c, a signal (for example, a non-selection signal) is output to the wiring 11. During the period from period a to period b, and during period b, another signal (e.g., a selection signal ) may be output. This allows the change in potential of the wiring 11 to be made steeper.

[0113] In the above description, the selection signal and the non-selection signal are These are just examples of signals to be output, and may be different from each other.

[0114] Next, the operation of the gate driver circuit of FIG. 4(A) is shown in FIG. 5(A) to FIG. 5(I). 6(A) to 6(L) and the case where some of the operations 1 to 9 are performed in combination. Timing charts different from those in FIGS. 7(A) to 7(L) will be described below.

[0115] 8(A) to 8(E) are timing charts showing an example of the operation of the gate driver circuit. It is.

[0116] The timing charts of FIG. 8(A) to FIG. 8(C) have a period T1 and a period T2. In addition, in FIG. 8(A) and FIG. 8(C), the periods T1 and T2 are alternately arranged. As shown in FIG. 8B, even if multiple periods T1 and multiple periods T2 are arranged alternately, In addition, there may be periods other than the period T1 and the period T2.

[0117] With reference to the timing chart of FIG. 8(A), the timing of the period T1 and the period T2 in FIG. The operation of the gate driver circuit of the MOSFET is explained below.

[0118] In the period T1, the timing chart shown in FIG. In the case of the circuit 10B, the deterioration of the transistors in the circuit 10B can be suppressed. In the example shown in FIG. 2, the timing chart shown in FIG. 7(A) is used. Therefore, in the period T2, This makes it possible to suppress deterioration of the transistors included in the circuit 10A.

[0119] In this manner, in FIG. 8A, the deterioration of the transistor included in the circuit 10B can be suppressed. and a period T1 during which deterioration of the transistor in the circuit 10A can be suppressed. The gaps T1 and T2 are arranged alternately.

[0120] Here, when the circuit 10A and the circuit 10B have the same configuration, the period T1 and the period T2 By making the lengths of the transistors in the circuit 10A and the circuit 10B approximately equal, The degree of deterioration of the transistors in the period T By alternately arranging periods T1 and T2, the operation of the circuit 10A and the circuit 10B is switched. Even if the potential of the wiring 11 is changed, the change in potential of the wiring 11 can be made substantially uniform.

[0121] Therefore, the gate driver circuit of FIG. 4A is When used in a display device, the video signal changes depending on the potential of the wiring 11 (for example, Even if the operation of the circuit 10A and the circuit 10B is switched, the wiring 11 is connected. The change in the video signal held by the connected pixels can be made approximately equal. Since the brightness or transmittance of the two types of display can be made substantially equal, the display quality can be improved. Cut.

[0122] In addition, in the period T1, any one of the timing charts shown in FIG. 6(A) to FIG. 6(L) is used. In the period T2, any one of the timing charts shown in FIG. 7(A) to FIG. 7(L) may be used. For example, as shown in FIG. 8C, in the period T1, the timing of FIG. 6K may be used. In the period T1, the timing chart of FIG. 7(K) may be used.

[0123] Next, Figs. 6(A) to 6(L), 7(A) to 7(L), 8(A), and 8(C) 4(A) in the period d shown in FIG. 4(A) shows an example of the operation of the gate driver circuit. The graph chart will be described with reference to FIG.

[0124] FIG. 8D is a timing chart showing an example of the operation of the gate driver circuit during period d. It is.

[0125] As shown in Figs. 6(A) to 6(L), 7(A) to 7(L), 8(A), and 8(C), In the timing chart, the period d is divided into multiple periods. For example, in FIG. As shown, the period d is divided into two periods, period d1 and period d2. However, in the period d, The number of divisions is not limited to this, and the period d may be divided into three or more periods. In (D), the periods d1 and d2 are alternately arranged, but multiple periods d1 and multiple The periods d1 and d2 may be arranged alternately.

[0126] With reference to the timing chart of FIG. 8(D), the timing of the period d1 and the period d2 in FIG. The operation of the gate driver circuit of the MOSFET is explained below.

[0127] During the period d1, the gate driver circuit performs the operation 2 in FIG. In FIG. 1, a circuit 10A outputs a signal to a wiring 11, and a circuit 10B outputs a signal to the wiring 11. During the period d2, the gate driver circuit performs operation 3 in FIG. That is, in the period d2, the circuit 10A does not output a signal to the wiring 11, and the circuit 10B does not output a signal to the wiring 1 Outputs a signal to 1.

[0128] In this way, the signal is applied to the gate of the transistor in each of the circuits 10A and 10B. Since it is possible to input the above, it is possible to suppress the degradation of each transistor. Therefore, even when the operation of the circuit 10A and the circuit 10B is switched, the change in the potential of the wiring 11 is suppressed. It is possible to make the breasts equal.

[0129] Therefore, the gate driver circuit of FIG. 4A is When used in a display device, the video signal changes depending on the potential of the wiring 11 (for example, Even if the operation of the circuit 10A and the circuit 10B is switched, the wiring 11 is connected. The change in the video signal held by the connected pixels can be made approximately equal. Since the brightness or transmittance of the two types of display can be made substantially equal, the display quality can be improved. Cut.

[0130] Next, a timing chart showing another example of the operation of the gate driver circuit of FIG. We will explain about this.

[0131] 6(A) to 6(L), 7(A) to 7(L), 8(A), 8(C), and In FIG. 8(D), the potential of the output signal OUTA of the circuit 10A and the potential of the output signal OU of the circuit 10B are The potential of TB is constant in each period. Or, in a certain period, the output signal For example, as shown in FIG. 8(E), in the period d, In this case, the potential of the output signal OUTA of the circuit 10A and the potential of the output signal OUTB of the circuit 10B are Each may have two values ​​that are repeated alternately.

[0132] In addition, the potentials of the output signals OUTA and OUTB in the period d are may be changed in an analog manner.

[0133] As described above, the gate driver circuit in FIG. 4A can perform various operations.

[0134] <Other configurations of the gate driver circuit> Next, referring to FIG. 9(A), a gate driver circuit configuration different from that in FIG. 4(A) will be described. He explains.

[0135] FIG. 9A shows an example of the configuration of a gate driver circuit. The circuit 10A, the circuit 10B, the circuit 10C, and the circuit 10D. 0D may have the same function as the circuit 10A or the circuit 10B, respectively.

[0136] In the gate driver circuit of FIG. 9A, the circuits 10A to 10D are each connected to the wiring When a signal (for example, a non-selection signal) is output to the output terminal 11, the circuits 10A to 10D each In addition, a signal other than the signal (for example, a selection signal) may be output to the wiring 11. The circuits 10A to 10D each output a signal (for example, a non-selection signal and a selection signal) to the wiring 11. By appropriately combining "on" and "off," various operations can be performed.

[0137] In FIG. 9A, the gate driver circuit is connected to four circuits (circuits In the above, the case where the gate driver of the present embodiment has the circuits 10A to 10D has been described. The circuit configuration is not limited to this. The gate driver circuit of this embodiment is N (N is a natural number). Each of the N circuits may be the circuit 10A or the circuit It may have the same function as 10B.

[0138] <Gate driver circuit operation> The operation of the gate driver circuit of FIG. 9(A) will be described with reference to FIG. 9(B). 9(B) shows an example of the operation of the gate driver circuit.

[0139] In operation 1, the circuit 10A outputs a signal (e.g., a non-selection signal) to the wiring 11, and the circuit 1 0B, the circuit 10C, and the circuit 10D do not output a signal to the wiring 11. 10B outputs a signal (for example, a non-selection signal) to the wiring 11, and the circuits 10A, 10C, In operation 3, the circuit 10C does not output a signal to the wiring 11. The circuit 10A, the circuit 10B, and the circuit 10D output a signal (e.g., a non-selection signal) to In operation 4, the circuit 10D outputs no signal to the wire 11. selection signal), and the circuit 10A, the circuit 10B, and the circuit 10C output signals to the wiring 11. Don't force it.

[0140] In operation 5, the circuit 10A and the circuit 10C apply a signal (e.g., a non-selection signal) to the wiring 11. In operation 6, the circuit 10B and the circuit 10D do not output a signal to the wiring 11. The circuit 10B and the circuit 10D output a signal (for example, a non-selection signal) to the wiring 11. In operation 7, the circuit 10A and the circuit 10B do not output a signal to the wiring 11. The circuit 10C and the circuit 10D output a signal (for example, a non-selection signal) to the wiring 11. In operation 8, the circuit 10A, the circuit 10B, the circuit 10C, and the circuit 10D transmit a signal to the wiring 11. Do not output.

[0141] In operation 9, circuit 10A outputs another signal (e.g., a select signal) on line 11, 10B, the circuit 10C, and the circuit 10D do not output a signal to the wiring 11. The circuit 10B outputs another signal (for example, a selection signal) to the wiring 11, and the circuit 10A and the circuit 1 In operation 11, the circuit 10C and the circuit 10D do not output a signal to the wiring 11. Another signal (for example, a selection signal) is output to the wiring 11, and the circuits 10A, 10B, and In operation 12, circuit 10D outputs no signal to wire 11. The circuit 10A, the circuit 10B, and the circuit 10C output a signal (for example, a selection signal). No signal is output to 11.

[0142] In operation 13, circuit 10A and circuit 10C apply another signal (e.g., a select signal ), and the circuit 10B and the circuit 10D do not output a signal to the wiring 11. The circuit 10B and the circuit 10D output another signal (for example, a selection signal) to the wiring 11. Circuit 10A and circuit 10C do not output a signal to wiring 11. In operation 15, circuit 10A, The circuit 10B, the circuit 10C, and the circuit 10D each transmit another signal (e.g., a selection signal) to the wiring 11. Output.

[0143] As described above, the gate driver circuit in FIG. 9A can perform various operations.

[0144] The circuits included in the gate driver circuit of this embodiment (circuit 10A, circuit 10B, etc.) The larger the number of circuits, i.e., the larger the number of circuits, the greater the number of signals each circuit can output. This reduces the number of times the transistors in each circuit are turned on. However, if N is too large, the circuit size becomes large. It is also preferable to make N smaller than 4, and more preferably, N=2. .

[0145] In addition, when the gate driver circuit of the present embodiment is used in a display device, the frame of the display device is In order to make the left and right sides approximately equal, it is preferable that N is an even number. It is preferable that N is an even number in order to have equal numbers of circuits placed on each side.

[0146] (Embodiment 3) In this embodiment, the configuration and operation of a gate driver circuit will be described.

[0147] <Gate driver circuit configuration> The configuration of the gate driver circuit will be described below.

[0148] FIG. 10(A), FIG. 10(B), FIG. 11(A), and FIG. 11(B) show the gate driver circuit. The gate driver circuit includes a circuit 100A and a circuit 100B. .

[0149] The circuit 100A includes a switch 101A and a switch 102A. is connected between the wiring 112A and the wiring 111. The switch 102A is connected between the wiring 113A and the wiring 111.

[0150] The circuit 100B includes a switch 101B and a switch 102B. is connected between the wiring 112B and the wiring 111. The switch 102B is connected between the wiring 113B and the wiring 111.

[0151] Here, as shown in FIG. 10B and FIG. 11B, the wiring 112A and the wiring 111 A path between the wiring 113A and the wiring 111 is a path 121A, a path between the wiring 113A and the wiring 111 is a path 122A, and a path between the wiring 113A and the wiring 111 is a path 123A. A path between 112B and the wiring 111 is a path 121B, and a path between 113B and the wiring 111 is a path 122B. The route is route 122B.

[0152] When describing a route between A and B, a switch is connected between A and B. In addition to the switch, elements (e.g., transistors, diodes, etc.) may be inserted between A and B. a diode, a resistor, a capacitor, etc.) or a circuit (e.g., a buffer circuit, an inverter A shift register circuit, a shift register circuit, etc. may be connected between A and B. An element (e.g., a resistor or transistor, etc.) is connected in series with the switch or in parallel with the switch. ) may be connected.

[0153] The circuit 100A, the circuit 100B, and the wiring 111 are the same as those in the circuit of the second embodiment. 10A, the circuit 10B, and the wiring 11, and have the same functions.

[0154] Next, the wiring 112A, the wiring 113A, the wiring 112B, and the wiring 113B will be described. do.

[0155] When the clock signal CK1 is input to the wiring 112A and the wiring 112B, and the wiring 112B is a signal line or a clock signal line ("clock line", "clock supply line"). Alternatively, the wiring 112A and the wiring 112B may function as a constant current source. When a voltage is supplied, the wiring 112A and the wiring 112B function as a power supply line.

[0156] When the same signal or voltage is input to the wiring 112A and the wiring 112B, 12A and the wiring 112B may be connected. In this case, as shown in FIG. The same wiring 112 may be used for the wiring 112A and the wiring 112B. Separate signals or separate voltages may be supplied to the wiring 112A and the wiring 112B.

[0157] A power supply voltage, a reference voltage, a ground voltage, an earth, or a negative voltage is applied to the wiring 113A and the wiring 113B. When a voltage V1 having a function such as a power supply potential is supplied, the wiring 113A and the wiring 113B The wiring 113A and the wiring 113B have a function as a power supply line or a ground. When a signal is input, the wiring 113A and the wiring 113B function as a signal line. .

[0158] When the same signal or voltage is supplied to the wiring 113A and the wiring 113B, 13A and the wiring 113B may be connected. In this case, as shown in FIG. The same wiring 113 may be used for the wiring 113A and the wiring 113B. Separate signals or separate voltages may be supplied to the wiring 113A and the wiring 113B.

[0159] Next, the switch 101A, the switch 102A, the switch 101B, and the switch 102 Let me explain about B.

[0160] The switch 101A has a function of controlling the timing at which the wiring 112A and the wiring 111 are electrically connected to each other. Alternatively, the switch 101A has a function of supplying the potential of the wiring 112A to the wiring 111. The switch 101A has a function of controlling the timing. A signal or voltage to be output (for example, a clock signal CK1, a clock signal CK2, or a voltage V 2) to the wiring 111. The wiring 1A has a function of controlling the timing at which a signal, a voltage, or the like is not supplied to the wiring 111 . Alternatively, the switch 101A supplies an H signal (for example, a clock signal CK1) to the wiring 111. Alternatively, the switch 101A has a function of controlling the timing of supplying an L signal (for example, For example, it has a function of controlling the timing of supplying a clock signal CK 1 ) to the wiring 111 . Alternatively, the switch 101A has a function of controlling the timing at which the potential of the wiring 111 is increased. Alternatively, the switch 101A controls the timing at which the potential of the wiring 111 is decreased. Alternatively, the switch 101A has a function of controlling the timing for maintaining the potential of the wiring 111. It has the function of controlling the

[0161] In addition, when the clock signal CK2 corresponds to the inverted signal of the clock signal CK1, The signal CK1 and the clock signal CK2 are mutually inverted signals or are out of phase with each other by approximately 180°. It is advisable to use such a signal.

[0162] In addition, the clock signal CK1 or the clock signal CK2 may be unbalanced even if it is balanced. Equilibrium is the period during which the signal is at the H level and the period during which the signal is at the L level. Non-equilibrium means that the period when the H level is high and the period when the L level is low are roughly equal. This means that the period during which the

[0163] In addition, the clock signals CK1 and CK2 are unbalanced, and If CK2 is not the inverted signal of the clock signal CK1, the H level of the clock signal CK1 The length of the period during which the clock signal CK1 is at the H level may be approximately equal to the length of the period during which the clock signal CK2 is at the H level. stomach.

[0164] The switch 102A has a function of controlling the timing at which the wiring 113A and the wiring 111 are electrically connected to each other. Alternatively, the switch 102A has a function of supplying the potential of the wiring 113A to the wiring 111. The switch 102A has a function of controlling the timing. A signal or voltage to be output (for example, a clock signal CK2 or a voltage V1) is provided to the wiring 111. Alternatively, the switch 102A has a function of controlling the timing of supplying a signal or voltage. The switch 10 has a function of controlling the timing at which the current is not supplied to the wiring 111. 2A has a function of controlling the timing of supplying the voltage V1 to the wiring 111. The switch 102A has a function of controlling the timing at which the potential of the wiring 111 is decreased. Alternatively, the switch 102A has a function of controlling the timing of maintaining the potential of the wiring 111. has.

[0165] The switch 101B has a function of controlling the timing at which the wiring 112B and the wiring 111 are electrically connected to each other. Alternatively, the switch 101B has a function of supplying the potential of the wiring 112B to the wiring 111. The switch 101B has a function of controlling the timing. A signal or voltage to be output (for example, a clock signal CK1, a clock signal CK2, or a voltage V 2) to the wiring 111. The wiring 1B has a function of controlling the timing at which a signal, a voltage, or the like is not supplied to the wiring 111. Alternatively, the switch 101B supplies an H signal (for example, the clock signal CK1) to the wiring 111. Alternatively, the switch 101B has a function of controlling the timing of supplying an L signal (for example, For example, it has a function of controlling the timing of supplying a clock signal CK 1 ) to the wiring 111 . Alternatively, the switch 101B has a function of controlling the timing at which the potential of the wiring 111 is increased. Alternatively, the switch 101B controls the timing at which the potential of the wiring 111 is decreased. Alternatively, the switch 101B has a function of controlling the timing for maintaining the potential of the wiring 111. It has the function of controlling the

[0166] The switch 102B has a function of controlling the timing at which the wiring 113B and the wiring 111 are electrically connected to each other. Alternatively, the switch 102B has a function of supplying the potential of the wiring 113B to the wiring 111. The switch 102B has a function of controlling the timing. A signal or voltage to be output (for example, a clock signal CK2 or a voltage V1) is provided to the wiring 111. Alternatively, the switch 102B has a function of controlling the timing of supplying a signal or voltage. The switch 10 has a function of controlling the timing at which the current is not supplied to the wiring 111. 2B has a function of controlling the timing of supplying the voltage V1 to the wiring 111. The switch 102B has a function of controlling the timing at which the potential of the wiring 111 is decreased. Alternatively, the switch 102B has a function of controlling the timing of maintaining the potential of the wiring 111. has.

[0167] <Gate driver circuit operation> Next, the operation of the gate driver circuit of FIG. 10(A) will be described below.

[0168] FIG. 10C shows an example of the operation of the gate driver circuit of FIG. In (C), the switch 101A, the switch 101B, and the 02A, switch 101B, and switch 102B. By combining these switches on and off, the gate driver in Figure 10(A) can be The buffer circuitry can perform a variety of operations.

[0169] The operations of the gate driver circuit in FIG. 10(A) are shown in FIG. 10(C) and FIG. 5(A) to 13(E) described in the second embodiment. The gate driver circuit shown in FIG. 10A for implementing the operations 1 to 7 shown in FIG. 5G. The operation of the above will be explained.

[0170] First, the operation of the gate driver circuit in FIG. 10(A) to realize the operation 1 in FIG. 5(A) will be described. This article explains the work.

[0171] As shown in operation 1a of FIG. 12(A), the switch 101A is turned on, so that the wiring 11 2A and the wiring 111 are in a conductive state. Therefore, the potential of the wiring 112A (for example, the clock The signal CK1) is supplied to the wiring 111. The switch 102A is turned on, so that the signal CK2 is supplied to the wiring 111. 13A and the wiring 111 are in a conductive state. Therefore, the potential of the wiring 113A (for example, the voltage V 1) is supplied to the wiring 111. Since the switch 101B is turned on, the wiring 112B and The wiring 111 is in a conductive state. Therefore, the potential of the wiring 112B (for example, the potential of the clock signal C K1) is supplied to the wiring 111. Also, the switch 102B is turned on, so that the wiring 1 13B and the wiring 111 are in a conductive state. Therefore, the potential of the wiring 113B (for example, the voltage V 1) is supplied to the wiring 111.

[0172] Therefore, when a potential is supplied from the circuit 100A and the circuit 100B to the wiring 111, , operation 1 in FIG. 5(A) can be realized.

[0173] In addition, in the operation 1a of FIG. 12(A), as shown in the operation 1b of FIG. 12(B), Alternatively, the switch 101A and the switch 101B may be turned off. In the example shown in FIG. 12(C), the switch 102A and the switch 10 Alternatively, in operation 1a of FIG. 12(A), switch 101A may be turned off. , any one of the switches 102A, 101B, and 102B is turned off. Alternatively, in operation 1a of FIG. 12(A), the switch 101A and the switch Alternatively, in operation 1a of FIG. 12(A), switch 10 1B and switch 102A may be turned off.

[0174] Next, the operation of the gate driver circuit in FIG. 10(A) to realize the operation 2 in FIG. 5(B) will be described. This article explains the work.

[0175] As shown in operation 2a of FIG. 12(D), the switch 101A is turned on, so that the wiring 11 2A and the wiring 111 are in a conductive state. Therefore, the potential of the wiring 112A (for example, the clock The signal CK1) is supplied to the wiring 111. The switch 102A is turned on, so that the signal CK2 is supplied to the wiring 111. 13A and the wiring 111 are in a conductive state. Therefore, the potential of the wiring 113A (for example, the voltage V 1) is supplied to the wiring 111. Since the switch 101B is turned off, the wiring 112B and The switch 102B is turned off, and therefore the wiring 111 is not electrically connected to the switch 102B. 3B and the wiring 111 are not electrically connected to each other.

[0176] Therefore, a potential is supplied from the circuit 100A to the wiring 111, and a potential is supplied from the circuit 100B to the wiring 111. By not supplying a potential to the gate, the operation 2 in FIG. 5B can be realized.

[0177] In the operation 2a in FIG. 12(D), as shown in the operation 2b in FIG. 12(E), Alternatively, in the operation 2a of FIG. 12(D), As shown in operation 2c of F), switch 101A may be turned off.

[0178] Next, the operation of the gate driver circuit in FIG. 10(A) to realize the operation 3 in FIG. 5(C) will be described. This article explains the work.

[0179] As shown in operation 3a of FIG. 12(G), the switch 101A is turned off, so that the wiring 11 Since the switch 102A is turned off, the wire 11 3A and the wiring 111 are not in a conductive state. Since the switch 101B is turned on, 2B and the wiring 111 are in a conductive state. Therefore, the potential of the wiring 112B (for example, the clock The signal CK1) is supplied to the wiring 111. Also, the switch 102B is turned on, so that The wiring 113B and the wiring 111 are in a conductive state. Therefore, the potential of the wiring 113B (for example, A voltage V1) is supplied to the line 111.

[0180] Therefore, a potential is not supplied from the circuit 100A to the wiring 111, and a potential is not supplied from the circuit 100B to the wiring 11 By supplying a potential to 1, operation 3 in FIG. 5(C) can be realized.

[0181] In the operation 3a in FIG. 12(G), as shown in the operation 3b in FIG. 12(H), Alternatively, in the operation 3a of FIG. 12(G), the switch 102B of FIG. As shown in operation 3c of A), switch 101B may be turned off.

[0182] Next, the operation of the gate driver circuit in FIG. 10(A) to realize the operation 4 in FIG. 5(D) will be described. This article explains the work.

[0183] As shown in operation 4a of FIG. 13B, the switch 101A is turned off, so that the wiring 11 Since the switch 102A is turned off, the wire 11 3A and the wiring 111 are not in a conductive state. Since the switch 101B is turned off, The switch 102B is turned off, so that the wiring 111 is not electrically connected to the switch 102B. The line 113B and the wiring 111 are not electrically connected to each other.

[0184] Therefore, a potential is not supplied from the circuit 100A and the circuit 100B to the wiring 111. This makes it possible to realize operation 4 in FIG. 5(D).

[0185] Next, the operation of the gate driver circuit in FIG. 10(A) to realize the operation 5 in FIG. 5(E) will be described. This article explains the work.

[0186] As shown in operation 5a of FIG. 13C, the switch 101A is turned on, so that the wiring 11 Therefore, the wiring 112A is electrically connected to the wiring 111. The clock signal CK2 is supplied to the wiring 111. The switch 102A is turned off, so that the wiring The line 113A and the wiring 111 are not electrically connected to each other. The switch 101B is turned on, so that the wiring The line 112B and the wiring 111 are in a conductive state. Therefore, when the wiring 112B has a different potential (for example , the clock signal CK2) is supplied to the wiring 111. Also, the switch 102B is turned off. Therefore, the wiring 113B and the wiring 111 are not electrically connected to each other.

[0187] As a result, different potentials are supplied to the wiring 111 from the circuit 100A and the circuit 100B. As a result, operation 5 in FIG. 5(E) can be realized.

[0188] Next, the operation of the gate driver circuit in FIG. 10(A) to realize the operation 6 in FIG. 5(F) will be described. This article explains the work.

[0189] As shown in operation 6a of FIG. 13(D), the switch 101A is turned on, so that the wiring 11 Therefore, the wiring 112A is electrically connected to the wiring 111. The clock signal CK2 is supplied to the wiring 111. The switch 102A is turned off, so that the wiring The line 113A and the wiring 111 are not electrically connected to each other. The switch 101B is turned off, so the wiring The line 112B and the wiring 111 are not electrically connected to each other. Also, the switch 102B is turned off. Thus, the wiring 113B and the wiring 111 are not electrically connected to each other.

[0190] Therefore, a different potential is supplied from the circuit 100A to the wiring 111, and a different potential is supplied from the circuit 100B to the wiring 1 By not outputting a potential to 11, operation 6 in FIG. 5(F) can be realized.

[0191] Next, the operation of the gate driver circuit in FIG. 10(A) to realize the operation 7 in FIG. 5(G) will be described. This article explains the work.

[0192] As shown in operation 7a of FIG. 13(E), the switch 101A is turned off, so that the wiring 11 Since the switch 102A is turned off, the wire 11 3A and the wiring 111 are not in a conductive state. Since the switch 101B is turned on, Therefore, the wiring 112B is electrically connected to the wiring 111. The clock signal CK2 is supplied to the wiring 111. Also, the switch 102B is turned off. Thus, the wiring 113B and the wiring 111 are not electrically connected to each other.

[0193] Therefore, a potential is not supplied from the circuit 100A to the wiring 111, and a potential is not supplied from the circuit 100B to the wiring 11 By supplying a different potential to 1, operation 7 in FIG. 5(G) can be realized.

[0194] As described above, the switch 101A, the switch 102A, the switch 101B, and the switch By controlling the on and off of the switch 102B, the The operation of the gate driver circuit described with reference to FIG.

[0195] In addition, operation 1a in FIG. 12(A), operation 2a in FIG. 12(D), and operation 3 in FIG. In a, the potentials of the wiring 112A and the wiring 112B are preferably approximately equal. For example, the potentials of the wiring 113A and the wiring 113B are preferably substantially equal to each other. When the voltage V1 is supplied to the wiring 113A and the wiring 113B, the clock signal CK1 is at the L level. It is preferable that

[0196] In addition, operation 5a in FIG. 13(C), operation 6a in FIG. 13(D), and operation 7 in FIG. 13(E) In a, when the potential of the wiring 113A and the wiring 113B is V1, The potential of the wiring 112B is preferably approximately V2. The clock signal CK2 input to 112B is preferably at H level.

[0197] Next, referring to FIGS. 6(A) to 6(L) and 7(A) to 7(L) described in the second embodiment, The operation of the gate driver circuit in FIG. 10(A) to realize the timing chart shown in This article explains:

[0198] In the second embodiment, the operation of the gate driver circuit in FIG. 5(A) to (I), but in order to realize the operation, The gate driver circuit of (A) performs any one of the operations shown in FIG. 10(C) during the arbitrary period. For example, in order to realize the operation 1 shown in FIG. The gate driver circuit of FIG. 10(A) performs operations 1a, 1b, and 1c ( 12(A), 12(B), and 12(C) can be performed. .

[0199] First, in order to realize the timing chart shown in FIG. 6(A), The operation of the driver circuit will now be described.

[0200] As described in the second embodiment, the period a, the period from period b to period c, period c, During the period d, the gate driver circuit of FIG. 10(A) performs the operation 2 shown in FIG. 5(B). Therefore, in order to realize the operation 2, the period a, the period b to the period c, In the periods c and d, the gate driver circuit of FIG. 12(D), 12(E), and 12(C) 2(F)) can be performed.

[0201] In addition, during the period from period a to period b and during period b, The driver circuit performs operation 6 of FIG. 5(F). Therefore, in order to realize operation 6, the period During the period from a to b and during the period b, the gate driver circuit of FIG. For example, the operation 6a shown in FIG. 10(C) (corresponding to FIG. 13(D)) can be performed.

[0202] In this way, the gate driver circuit of FIG. 10(A) operates in the timing diagram of FIG. You can perform actions that correspond to the chart.

[0203] In the timing chart of FIG. 6A, the period a and the period b are changed to the period c. During the period in which the selection is performed, the circuit 100B outputs a signal (for example, a non-selection signal) to the wiring 111. In this case, the gate driver circuit of FIG. 10(A) performs, for example, operation 1a shown in FIG. , operation 1b, and operation 1c (corresponding to Figs. 12(A), 12(B), and 12(C)) You can do either one.

[0204] In the timing chart of FIG. 6A, the period from period a to period b, During the period b, the circuit 100B outputs another signal (for example, a selection signal) to the wiring 111. When the gate driver circuit of FIG. 10A is operated in the manner shown in FIG. 10C, a (corresponding to FIG. 13(C)) can be carried out.

[0205] In this way, the gate driver circuit of FIG. 10(A) operates in the timing shown in FIG. You can perform actions that correspond to the chart.

[0206] Similarly, the gate driver circuit of FIG. 10(A) operates in one of the ways described in FIG. 10(C). By performing either of the above, the timing chart shown in FIG. 6(B) to FIG. 6(J) and FIG. 6(L) can be obtained. This chart can be realized.

[0207] Next, in order to realize the timing chart shown in FIG. 7(A), The operation of the driver circuit will now be described.

[0208] As described in the second embodiment, the period a, the period from period b to period c, period c, During the period d, the gate driver circuit of FIG. 10(A) performs the operation 3 shown in FIG. 5(C). Therefore, in order to realize the operation 3, the period a, the period b to the period c, In the periods c and d, the gate driver circuit of FIG. 12(G), 12(H), and 12(C) 3(A)) can be carried out.

[0209] In addition, during the period from period a to period b and during period b, The driver circuit performs operation 7 of FIG. 5(G). Therefore, in order to realize operation 7, During the period from a to b and during the period b, the gate driver circuit of FIG. For example, the operation 7a shown in FIG. 10(C) (corresponding to FIG. 13(E)) can be performed.

[0210] In this way, the gate driver circuit of FIG. 10A operates in the timing diagram of FIG. You can perform actions that correspond to the chart.

[0211] In the timing chart of FIG. 7A, the period a and the period b are changed to the period c. During the period in which the selection is performed, the circuit 100A outputs a signal (for example, a non-selection signal) to the wiring 111. In this case, the gate driver circuit of FIG. 10(A) performs, for example, operation 1a shown in FIG. , operation 1b, and operation 1c (corresponding to Figs. 12(A), 12(B), and 12(C)) You can do either one.

[0212] In the timing chart of FIG. 7A, the period from period a to period b, During the period b, the circuit 100A outputs another signal (for example, a selection signal) to the wiring 111. When the gate driver circuit of FIG. 10A is operated in the manner shown in FIG. 10C, a (corresponding to FIG. 13(C)) can be carried out.

[0213] In this way, the gate driver circuit of FIG. 10(A) operates as shown in FIG. 7(K). You can perform actions that correspond to the chart.

[0214] Similarly, the gate driver circuit of FIG. 10(A) operates in one of the ways described in FIG. 10(C). By performing either of the above, the timing chart shown in FIG. 7(B) to FIG. 7(J) and FIG. 7(L) can be obtained. This chart can be realized.

[0215] As described above, the gate driver circuit of FIG. 10(A) incorporates the operation shown in FIG. 10(C). By combining the above, the tags shown in Figs. 6(A) to 6(L) and Figs. 7(A) to 7(L) can be obtained. A timing chart can be realized.

[0216] <Gate driver circuit configuration> Next, a configuration of the gate driver circuit that is different from that shown in FIG. 10(A) will be described below. Here, the gate driver circuit has the same function as the circuit 100A or the circuit 100B. A case where there are N (N is a natural number) circuits will be described.

[0217] FIG. 11C shows an example of the configuration of a gate driver circuit. The circuit 100A, the circuit 100B, the circuit 100C, and the circuit 100D. The circuit 100D has a function similar to that of the circuit 100A or the circuit 100B.

[0218] The circuit 100C includes a switch 101C and a switch 102C. The switch 101C is connected between the wiring 112C and the wiring 111, and the switch 102C is connected between the wiring 112C and the wiring 111. The switch 101C is connected between the switch 101A or the switch 101C. The switch 102C has the same function as the switch 102A or the switch 102B. The wiring 112C has the same function as the wiring 112A or the wiring 112B. The wiring 113C has the same function and receives the same signal or voltage. has the same function as the wiring 113B, and receives the same signal or voltage.

[0219] The circuit 100D includes a switch 101D and a switch 102D. The switch 101D is connected between the wiring 112D and the wiring 111, and the switch 102D is connected between the wiring 112D and the wiring 111. The switch 101D is connected between the switch 101A or the switch 101D. The switch 102D has the same function as the switch 102A or the switch 101B. The wiring 112D has the same function as the wiring 112A or the wiring 112B. The wiring 113D has the same function and receives the same signal or voltage. has the same function as the wiring 113B, and receives the same signal or voltage.

[0220] FIG. 14A shows an example of another configuration of the gate driver circuit. , a circuit 100A and a circuit 100B.

[0221] The circuit 100A includes a switch 103A in addition to the switches 101A and 102A. The switch 103A is connected between the wiring 113A and the wiring 111. Switch 103A can perform the same operation as switch 102A.

[0222] The circuit 100B includes a switch 103B in addition to the switches 101B and 102B. The switch 103B is connected between the wiring 113B and the wiring 111. Switch 103B can perform the same operation as switch 102B.

[0223] <Gate driver circuit operation> The operation of the gate driver circuit of FIG. 14(A) will be described with reference to FIG. 14(B) and FIG. 15(A). 5(A) to 5(E) described in the second embodiment. 5(G) of the gate driver circuit of FIG. 14(A) for realizing operations 1 to 7. The operation will be described.

[0224] First, the operation of the gate driver circuit in FIG. 14(A) to realize the operation 1 in FIG. 5(A) will be described. This article explains the work.

[0225] As shown in operation 1d of FIG. 14B, the switch 101A is turned off, so that the wiring 11 2A is not electrically connected to the wiring 111. The switches 102A and 103A are on. Therefore, the wiring 113A and the wiring 111 are in a conductive state. A potential (for example, voltage V1) is supplied to the wiring 111. The switch 101B is turned off. Therefore, the wiring 112B and the wiring 111 are not electrically connected to each other. Since the line 113B is turned on, the line 113B and the line 111 are in a conductive state. The potential of 113B (for example, voltage V1) is supplied to the wiring 111.

[0226] In the operation 1d of FIG. 14(B), as shown in the operation 1e of FIG. 14(B), Alternatively, the switch 103A and the switch 103B may be turned off. In step d, as shown in operation 1f of FIG. 14(B), the switch 102A and the switch 10 2B may be turned off. Alternatively, in the operations 1d, 1e, and 1f in FIG. 14(B), In this case, the switch 101A or the switch 101B may be turned on.

[0227] Next, the operation of the gate driver circuit in FIG. 14(A) to realize the operation 2 in FIG. 5(B) will be described. This article explains the work.

[0228] As shown in operation 2d of FIG. 14B, the switch 101A is turned off, so that the wiring 11 2A is not electrically connected to the wiring 111. The switches 102A and 103A are on. Therefore, the wiring 113A and the wiring 111 are in a conductive state. A potential (for example, voltage V1) is supplied to the wiring 111. The switch 101B is turned off. Therefore, the wiring 112B and the wiring 111 are not electrically connected to each other. Since the output of the transistor 03B is turned off, the wiring 113B and the wiring 111 are not electrically connected to each other.

[0229] In addition, in the operation 2d in FIG. 14(B), the operation 2e in FIG. 14(B) (corresponding to FIG. 15(A)) Alternatively, the switch 103A may be turned off as shown in FIG. In 2d, as shown in operation 2f of FIG. 14(B) (corresponding to FIG. 15(B)), the switch 102A may be turned off. Alternatively, the operation 2d, the operation 2e, and the operation 2 in FIG. 14(B) may be performed. At f, switch 101A may be turned on.

[0230] Next, the operation of the gate driver circuit in FIG. 14(A) to realize the operation 3 in FIG. 5(C) will be described. This article explains the work.

[0231] As shown in operation 3d of FIG. 14B, the switch 101A is turned off, so that the wiring 11 2A is not electrically connected to the wiring 111. The switches 102A and 103A are off. Therefore, the wiring 113A and the wiring 111 are not electrically connected to each other. The switch 101B is turned off. Therefore, the wiring 112B and the wiring 111 are not electrically connected to each other. Since the switch 103B is turned on, the wiring 113B and the wiring 111 are in a conductive state. The potential of the wiring 113B (for example, voltage V1) is supplied to the wiring 111.

[0232] In addition, in the operation 3d in FIG. 14B, the operation 3e in FIG. 14B (corresponding to FIG. 15C) Alternatively, the switch 103B may be turned off as shown in FIG. In 3d, as shown in operation 3f of FIG. 14(B) (corresponding to FIG. 15(D)), the switch 102B may be turned off. Alternatively, operations 3d, 3e, and 3 in FIG. At f, switch 101B may be turned on.

[0233] Next, the operation of the gate driver circuit in FIG. 14(A) to realize the operation 4 in FIG. 5(D) will be described. This article explains the work.

[0234] As shown in operation 4b of FIG. 14B, the switch 101A is turned off, so that the wiring 11 2A is not electrically connected to the wiring 111. The switches 102A and 103A are off. Therefore, the wiring 113A and the wiring 111 are not electrically connected to each other. The switch 101B is turned off. Therefore, the wiring 112B and the wiring 111 are not electrically connected to each other. Since switch 103B is turned off, wiring 113B and wiring 111 are not electrically connected to each other.

[0235] Next, the operation of the gate driver circuit of FIG. 14(A) to realize the operation 5 of FIG. 5(E) will be described. This article explains the work.

[0236] As shown in operation 5b of FIG. 14(B) (corresponding to FIG. 15(E)), the switch 101A is turned on. Therefore, the wiring 112A and the wiring 111 are in a conductive state. A potential (for example, a clock signal CK1) is supplied to the wiring 111. Since the switch 103A is turned off, the wiring 113A and the wiring 111 are not electrically connected to each other. Since the switch 101B is turned on, the wiring 112B and the wiring 111 are brought into a conductive state. Therefore, the potential of the wiring 112B (for example, the clock signal CK1) is supplied to the wiring 111. Since the switch 102B and the switch 103B are turned off, the wiring 113B and the wiring 11 1 is in a non-conductive state.

[0237] Next, the operation of the gate driver circuit in FIG. 14(A) to realize the operation 6 in FIG. 5(F) will be described. This article explains the work.

[0238] As shown in operation 6b of FIG. 14(B), the switch 101A is turned on, so that the wiring 11 2A and the wiring 111 are in a conductive state. Therefore, the potential of the wiring 112A (for example, the clock A signal CK1) is supplied to a wiring 111. The switches 102A and 103A are on. Therefore, the wiring 113A and the wiring 111 are not electrically connected to each other. Therefore, the wiring 112B and the wiring 111 are not electrically connected to each other. Since the switch 103B is turned off, the wiring 113B and the wiring 111 are not electrically connected to each other.

[0239] Next, the operation of the gate driver circuit in FIG. 14(A) to realize the operation 7 in FIG. 5(G) will be described. This article explains the work.

[0240] As shown in operation 7b of FIG. 14B, the switch 101A is turned off, so that the wiring 11 2A is not electrically connected to the wiring 111. The switches 102A and 103A are off. Therefore, the wiring 113A and the wiring 111 are not electrically connected to each other. The switch 101B is turned on. Therefore, the wiring 112B and the wiring 111 are in a conductive state. A clock signal (for example, a clock signal CK1) is supplied to a wiring 111. Since the switch 103B is turned off, the wiring 113B and the wiring 111 are not electrically connected to each other.

[0241] As described above, the switches 101A, 102A, 103A, and 104A are By controlling the on and off of switches 101B, 102B, and 103B, The operation of the gate driver circuit described with reference to FIGS. 5(A) to 5(G) in the second embodiment will be described below. This makes it possible to realize the work.

[0242] (Embodiment 4) In this embodiment, a semiconductor device having the gate driver circuit described in the above embodiment is This article explains:

[0243] <Configuration of Semiconductor Device> An example of the structure of a semiconductor device of this embodiment will be described with reference to FIG. FIG. 16A shows an example of a circuit diagram of a semiconductor device. The circuit 200 includes a circuit 200A and a circuit 200B that configure a light-emitting diode driver.

[0244] The circuit 200A includes a transistor 201A, a transistor 202A, and a circuit 300A. The circuit 200B includes a transistor 201B, a transistor 202B, and a circuit 30 Has 0B.

[0245] In FIG. 16A, the transistor 201A, the transistor 202A, The transistor 201B and the transistor 202B are described as N-channel transistors. In an N-channel transistor, the voltage difference between the gate and source (Vgs) is equal to or greater than the threshold. It turns on when the voltage exceeds the threshold voltage (Vth).

[0246] These transistors may be P-channel transistors. In a gate-source transistor, the potential difference between the gate and source (Vgs) is the threshold voltage (Vth ) turns on.

[0247] The transistor 201A has a first terminal connected to the wiring 112A and a second terminal connected to the wiring 112B. The first terminal of the transistor 202A is connected to the wiring 113A. The second terminal is connected to the wiring 111. The circuit 300A includes a wiring 113A, a wiring 114A, a wiring Line 115A, wiring 116A, the gate of transistor 201A, and transistor 202A The circuit 300A is connected to all of the wirings 113A to 116A. It is not necessary to connect the wiring 113A to the wiring 116A. Good too.

[0248] The connection point between the gate of the transistor 201A and the circuit 300A is node A1. The connection point between the gate of the transistor 202A and the circuit 300A is indicated as a node A2. The potential of node A1 is also referred to as potential Va1, and the potential of node A2 is also referred to as potential Va2.

[0249] A first terminal of the transistor 201B is connected to the wiring 112B, and a second terminal of the transistor 201B is connected to the wiring 112B. The first terminal of the transistor 202B is connected to the wiring 113B. The second terminal is connected to the wiring 111. The circuit 300B includes a wiring 113B, a wiring 114B, and a wiring 115B. Line 115B, wiring 116B, the gate of transistor 201B, and transistor 202B The circuit 300B is connected to all of the wirings 113B to 116B. It is not necessary to connect the wiring 113B to the wiring 116B. Good too.

[0250] The connection point between the gate of the transistor 201B and the circuit 300B is called a node B1. The connection point between the gate of the transistor 202B and the circuit 300B is indicated as node B2. The potential of node B1 is also referred to as potential Vb1, and the potential of node B2 is also referred to as potential Vb2.

[0251] Next, the wiring 111, the wiring 114A, the wiring 115A, the wiring 116A, the wiring 114B, the wiring The wiring 115B and the wiring 116B will now be described.

[0252] A signal OUTA is output from the circuit 200A to the wiring 111, and a signal O is output from the circuit 200B to the wiring 111. UTB is output.

[0253] The wiring 111 is arranged to extend to the pixel portion, and includes a gate signal line (also called a "gate line"). The signal OUTA and the signal OUTB function as a scanning line or a signal line. It corresponds to a gate signal, a scan signal, or a selection signal.

[0254] In addition, when the semiconductor device has a plurality of circuits 200A, the wiring 111 is provided in a different stage (for example, The signal OUTA may be connected to the wiring 114A of the circuit 200A of the next stage. In this case, the signal OUTA is This corresponds to a transfer signal or a start signal. In this case, the wiring 111 is connected to a wiring 116A of a circuit 200A in another stage (for example, the previous stage). In this case, the signal OUTA corresponds to a reset signal.

[0255] In addition, when the semiconductor device has a plurality of circuits 200B, the wiring 111 is provided in a different stage (for example, The signal OUTB may be connected to the wiring 114B of the circuit 200B in the next stage. In this case, the signal OUTB is This corresponds to a transfer signal or a start signal. In this case, the wiring 111 is connected to a wiring 116B of a circuit 200B in another stage (for example, the previous stage). In this case, the signal OUTB corresponds to a reset signal.

[0256] A start signal SP is input to the wiring 114A and the wiring 114B. The wiring 14A and the wiring 114B function as a signal line.

[0257] In addition, when the semiconductor device has a plurality of circuits 200A, the wiring 114A may be provided in another stage (e.g. , the previous stage) of the circuit 200A. In this case, the wiring 114A is It has a function as a gate signal line (also called a "gate line"), a scanning line, or a signal line. Therefore, the start signal SP corresponds to a gate signal, a scanning signal, or a selection signal.

[0258] In addition, when the semiconductor device has a plurality of circuits 200B, the wiring 114B may be provided in another stage (e.g. , the previous stage) of the circuit 200B. In this case, the wiring 114B is The gate signal line (also called a "gate line") functions as a signal line or a scanning line. Therefore, the start signal SP corresponds to a gate signal, a selection signal, or a scanning signal.

[0259] When the same signal is input to the wiring 114A and the wiring 114B, In this case, the wiring 114A and the wiring 114B may be connected to each other. Alternatively, different signals may be input to the wiring 114A and the wiring 114B. Good too.

[0260] A signal SELA is input to the wiring 115A, and a signal SELB is input to the wiring 115B. will be done.

[0261] The signals SELA and SELB are inverted signals or are out of phase with each other by approximately 180°. The signals SELA and SELB may be set to a predetermined value every certain period (for example, When the H level and the L level are repeated every frame period, the signals SELA and SELB corresponds to a control signal, a clock signal, or a clock control signal. and the wiring 115B is a signal line, a control line, or a clock signal line ("clock line", "clock The signals SELA and SELB function as a clock supply line. The H level and L level are repeated every few frames, every time the power is turned on, or randomly. In addition, during the same period, both the signals SELA and SELB may be set to the H level or It may be set to L level.

[0262] A reset signal RE is input to the wiring 116A and the wiring 116B. The wiring 16A and the wiring 116B function as signal lines.

[0263] In addition, when the semiconductor device has a plurality of circuits 200A, the wiring 116A may be provided in another stage (e.g. , the next stage) circuit 200A. In this case, the wiring 116A is The gate signal line (also called a "gate line") functions as a signal line or a scanning line. Therefore, the reset signal RE corresponds to a gate signal, a selection signal, or a scanning signal.

[0264] In addition, when the semiconductor device has a plurality of circuits 200B, the wiring 116B may be provided in another stage (e.g. , the next stage) circuit 200B. In this case, the wiring 116B is The gate signal line (also called a "gate line") functions as a signal line or a scanning line. Therefore, the reset signal RE corresponds to a gate signal, a selection signal, or a scanning signal.

[0265] When the same signal is input to the wiring 116A and the wiring 116B, In this case, the wiring 116A and the wiring 116B may be connected to each other. Alternatively, different signals may be input to the wiring 116A and the wiring 116B. Good too.

[0266] Next, transistor 201A, transistor 202A, circuit 300A, transistor 2 01B, a transistor 202B, and a circuit 300B will be described.

[0267] The transistor 201A has the same function as the switch 101A described in the third embodiment. Alternatively, the transistor 201A may have a function of performing a bootstrap operation. Alternatively, the transistor 201A may be configured to bootstrap the potential of the node A1. Therefore, it may have a function of increasing the concentration.

[0268] In this way, transistor 201A can function as a switch or as a buffer. The transistor 201A is controlled in response to the potential of the node A1. Good too.

[0269] The transistor 202A has a function similar to that of the switch 102A described in the third embodiment. Note that the transistor 202A may be controlled in response to the potential of the node A2.

[0270] The circuit 300A has a function of controlling the potential of the node A1 or the potential of the node A2. Alternatively, the circuit 300A may determine the timing for supplying a signal or a voltage to the node A1 or the node A2. Alternatively, the circuit 300A may have a function of controlling the switching of the node A1 or the node A2. The circuit 300A has a function of controlling the timing at which a signal or voltage is not supplied. controls the timing of supplying the H signal or voltage V2 to the node A1 or the node A2. Alternatively, the circuit 300A may provide an L signal or a voltage to the node A1 or the node A2. The circuit 300A has a function of controlling the timing of supplying V1. The potential of the node A1 or the potential of the node A2 is increased. The circuit 300A controls the timing of decreasing the potential of the node A1 or the potential of the node A2. Alternatively, the circuit 300A has a function of controlling the potential of the node A1 or the potential of the node A2. Alternatively, the circuit 300A has a function of controlling the timing at which the node A1 or has the function of controlling the timing of putting node A2 into a floating state.

[0271] The circuit 300A responds to a start signal SP, a signal SELA, or a reset signal RE. Alternatively, the circuit 300A may be controlled in response to the aforementioned signals (start signal SP, signal SELA, and reset signal RE) are different from other signals (e.g., signal OUTA, clock signal The clock signal CK1, or CK2, may be controlled in response to the clock signal CK2.

[0272] The transistor 201B has a function similar to that of the switch 101B described in the third embodiment. Alternatively, the transistor 201B may have a function of performing a bootstrap operation. Alternatively, the transistor 201B may be configured to bootstrap the potential of the node B1. Therefore, it may have a function of increasing the concentration.

[0273] In this way, transistor 201B can function as a switch or as a buffer. The transistor 201B is controlled in response to the potential of the node B1. Good too.

[0274] The transistor 202B has a function similar to that of the switch 102B described in the third embodiment. Note that the transistor 202B may be controlled in response to the potential of the node B2.

[0275] The circuit 300B has a function of controlling the potential of the node B1 or the potential of the node B2. Alternatively, the circuit 300B may determine the timing for supplying a signal or a voltage to the node B1 or the node B2. Alternatively, the circuit 300B may have a function of controlling the switching of the node B1 or the node B2. The circuit 300B has a function of controlling the timing at which a signal or voltage is not supplied. controls the timing of supplying the H signal or voltage V2 to the node B1 or the node B2. Alternatively, the circuit 300B may provide an L signal or a voltage to the node B1 or the node B2. The circuit 300B has a function of controlling the timing of supplying V1. The timing for increasing the potential of node B1 or the potential of node B2 is controlled. The circuit 300B controls the timing of decreasing the potential of the node B1 or the potential of the node B2. Alternatively, the circuit 300B has a function of controlling the potential of the node B1 or the potential of the node B2. Alternatively, the circuit 300B has a function of controlling the timing of maintaining the node B1 or has a function of controlling the timing of putting node B2 into a floating state.

[0276] In addition, the circuit 300B responds to a start signal SP, a signal SELB, or a reset signal RE. Alternatively, the circuit 300B may be controlled in response to the above-mentioned signals (start signal SP, signal SELB, and reset signal RE) are different from other signals (e.g., signal OUTB, clock signal The clock signal CK1, or CK2, may be controlled in response to the clock signal CK2.

[0277] <Operation of Semiconductor Device> An example of the operation of the semiconductor device in FIG. 16A will be described with reference to a timing chart shown in FIG. 18(A) to 23 are diagrams showing the semiconductor device of FIG. 1 is a diagram for explaining an example of the operation of the embodiment and a timing chart showing the example of the operation. , explanations of points common to those explained in the above embodiment will be omitted.

[0278] First, during a period a1, as shown in FIG. 18(A), the start signal SP goes to H level. At the timing when the start signal SP becomes H level, the circuit 300A outputs a H signal or starts to supply voltage V2 to node A1. Therefore, the potential of node A1 rises. Since the potential at node A1 rises, the circuit 300A applies an L signal or voltage V1 to node A Therefore, the potential of node A2 decreases to the L level. Since the resistor 202A is turned off, the wiring 113A and the wiring 111 are not electrically connected to each other.

[0279] After that, the potential of the node A1 continues to rise. Eventually, the potential of the node A1 becomes V1+Vth 201A (Vth 201A When the voltage rises to the threshold voltage of the transistor 201A, Since the transistor 201A is turned on, the wiring 112A and the wiring 111 are brought into a conductive state. Then, the clock signal CK1 at the L level is input to the wiring 111 via the transistor 201A. As a result, the signal OUTA becomes L level.

[0280] After that, the potential at node A1 further rises. Eventually, the circuit 300A supplies a Since the supply of the signal or voltage to the node A1 is stopped, the circuit 300A and the node A1 are put into a non-conductive state. As a result, node A1 is in a floating state, and the potential of node A1 is V1+Vth 201A +Vx (Vx is a positive number).

[0281] During the period a1, the circuit 300A stops supplying a signal or voltage to the node A1. Instead, V1+Vth 201A The voltage +Vx may continue to be supplied to node A1.

[0282] On the other hand, during the period a1, when the start signal SP becomes H level, the circuit 30 0B starts to supply an H signal or voltage V2 to node B1. Therefore, the potential of node B1 becomes At this time, since the signal SELB is at the L level, the potential of the node B1 rises. Therefore, the circuit 300B supplies an L signal or voltage V1 to the node B2. The potential of 2 decreases to the L level. Then, the transistor 202B turns off. Therefore, the wiring 113B and the wiring 111 are not electrically connected to each other.

[0283] After that, the potential of the node B1 continues to rise. Eventually, the potential of the node B1 becomes equal to V1+Vth 201B (Vth 201B When the voltage rises to the threshold voltage of transistor 201B, Since the transistor 201B is turned on, the wiring 112B and the wiring 111 are brought into a conductive state. Then, the clock signal CK1 at the L level is input to the wiring 111 via the transistor 201B. As a result, the signal OUTB becomes L level.

[0284] After that, the potential at node B1 rises further. Eventually, the circuit 300B supplies a Since the supply of the signal or voltage to the node B1 is stopped, the circuit 300B and the node B1 are put into a non-conductive state. As a result, node B1 is in a floating state, and the potential of node B1 is V1+Vth 201B Maintained at +Vx.

[0285] During the period a1, the circuit 300B stops supplying a signal or voltage to the node B1. Instead, V1+Vth 201B A voltage of +Vx may continue to be supplied to node B1.

[0286] Next, during a period b1, as shown in FIG. 18(B), the start signal SP goes to the L level. Therefore, the circuit 300A is kept in a state where no signal or voltage is provided to the node A1. Therefore, since node A1 is kept floating, the potential of node A1 is V1+Vt h 201A +Vx. That is, the transistor 201A is maintained in the on state. Therefore, the wire 112A and the wire 111 maintain a conductive state.

[0287] In addition, since the potential of the node A1 is maintained at the increased value during the period a1, the circuit 300A is maintained in a state that supplies an L signal or voltage V1 to node A2. Since 202A is maintained in the off state, the wiring 113A and the wiring 111 are maintained in a non-conductive state. do.

[0288] At this time, the clock signal CK1 rises from the L level to the H level. Since the clock signal CK1 is supplied to the wiring 111 via the transistor 201A, The potential of the wiring 111 rises. Then, since the node A1 is kept in a floating state, The potential of the node A1 is increased by the parasitic capacitance between the gate and the second terminal of the transistor 201A. , V2+Vth 202A +Vx(Vth 202A: Threshold voltage of transistor 202A ) This is the so-called bootstrap operation. rises to V2, so that the signal OUTA becomes H level.

[0289] On the other hand, in the period b1, the start signal SP goes to the L level, so that the circuit 300B No signal or voltage is applied to node B1. Therefore, node B1 is floating. Therefore, the potential of node B1 is V1+Vth 201B Maintained at +Vx. In other words, the transistor 201B is maintained in an on state, and therefore the wiring 112B and the wiring 111 The conductive state is maintained.

[0290] Also, since the signal SELB is at the L level, the potential of the node B1 rises during the period a1. Therefore, the circuit 300B is in a state where it provides an L signal or voltage V1 to node B2. Therefore, the transistor 202B is kept in an off state, and the wiring 113 B and the wiring 111 are kept in a non-conductive state.

[0291] At this time, the clock signal CK1 rises from the L level to the H level. Since the clock signal CK1 is supplied to the wiring 111 via the transistor 201B, The potential of the wiring 111 rises. Then, since the node B1 is kept in a floating state, The potential of the node B1 is increased by the parasitic capacitance between the gate and the second terminal of the transistor 201B. , V2+Vth 202B +Vx(Vth 202B : Threshold voltage of transistor 202B ) This is the so-called bootstrap operation. rises to V2, so that the signal OUTB becomes H level.

[0292] Next, during a period c1, as shown in FIG. 19(A), the reset signal RE goes to H level. At the timing when the reset signal RE becomes H level, the circuit 300A outputs an L signal or supplies voltage V1 to node A1. Therefore, the potential of node A1 becomes voltage V1. Then, the transistor 201A is turned off, and the wiring 112A and the wiring 11 On the other hand, since the potential at node A1 decreases, the circuit 300A goes into a non-conductive state with respect to node A1. A signal or voltage V2 is supplied to node A2. Therefore, the potential of node A2 rises. Then, the transistor 202A is turned on, so that the wiring 113A and the wiring 111 are electrically connected to each other. As a result, the voltage V1 is supplied to the wiring 111 via the transistor 202A. Thus, the potential of the wiring 111 decreases, and the signal OUTA goes to the L level.

[0293] In the period c1, the timing at which the clock signal CK1 becomes low is This may occur earlier than the timing at which transistor 201A turns off. The clock signal CK1 at the L level drives the transistor 201A until the transistor 201A is turned off. The current may be supplied to the wiring 111 through a large channel width of the transistor 201A. Increasing this setting can shorten the fall time of the signal OUTA.

[0294] During a period c1, the voltage V1 is applied to the wiring 111 via the transistor 202A. When the clock signal CK1 is supplied to the wiring 111 and when the clock signal CK1 is at an L level, the transistor 201A When the voltage V1 is supplied to the wiring 111 via the transistor 202A, 111, and a clock signal CK1 at a low level is input via a transistor 201A. There are three patterns:

[0295] On the other hand, during the period c1, when the reset signal RE becomes H level, the circuit 30 0B supplies an L signal or voltage V1 to node B1. Therefore, the potential of node B1 becomes Then, the transistor 201B is turned off, so that the line 1 12B and the wiring 111 are in a non-conductive state. On the other hand, the signal SELB is maintained at the L level. Therefore, the circuit 300B is kept in a state supplying an L signal or voltage V1 to node B2. Therefore, the potential of the node B2 is maintained at the L level. Then, the transistor 202B Since the off state is maintained, the wiring 113B and the wiring 111 are maintained in a non-conductive state.

[0296] In the period c1, the timing at which the clock signal CK1 becomes low is This may occur earlier than the timing at which transistor 201B turns off. The clock signal CK1 at the L level drives the transistor 201B until the transistor 201B is turned off. The current may be supplied to the wiring 111 through a large channel width of the transistor 201B. Increasing this setting can shorten the fall time of the signal OUTB.

[0297] Next, in a period d1, as shown in FIG. 19B, the circuit 300A outputs an L signal or Therefore, the potential of the node A1 is kept at the L level. Then, the transistor 201A is kept in an off state, so that the wiring 112A and the wiring 111 are maintained in a non-conductive state.

[0298] Additionally, the circuit 300A remains in a state supplying an H signal or voltage V2 to node A2. Therefore, the potential of the node A2 is maintained at the H level. Then, the transistor 202A is turned on. Since the wiring 113A and the wiring 111 are kept in an on state, the wiring 113A and the wiring 111 are kept in an electrically conductive state. , the voltage V1 is maintained in a state where it is supplied to the wiring 111 via the transistor 202A.

[0299] On the other hand, during the period d1, the circuit 300B supplies an L signal or a voltage V1 to the node B1. Therefore, the potential of the node B1 is maintained at the L level. Since the resistor 201B is kept in the off state, the wiring 112B and the wiring 111 are not electrically connected. Hold.

[0300] Additionally, circuit 300B remains in a state providing an L signal or voltage V1 to node B2. Therefore, the potential of the node B2 is maintained at the L level. Then, the transistor 202B is turned on. Since the wiring 113B and the wiring 111 are kept in the off state, the wiring 113B and the wiring 111 are kept in a non-conductive state.

[0301] Next, the operation of the semiconductor device in the period a2 is as follows: However, when the signal SELA goes to the L level, the signal S The difference is that ELB becomes H level.

[0302] Next, the operation of the semiconductor device in the period b2 is as shown in FIG. However, when the signal SELA goes to the L level, the signal S The difference is that ELB becomes H level.

[0303] Next, the operation of the semiconductor device in the period c2 will be described with reference to FIG. The operation of the semiconductor device in the period c1 is as follows: the signal SELA goes to the L level, and the signal SEL The difference is that B becomes H level.

[0304] Since the signal SELA becomes L level, the circuit 300A applies an L signal or a voltage V1 to the node A. Therefore, the transistor 202A is turned off, and the wiring 113A and the wiring 1 There is no electrical continuity between terminal 11 and terminal 12.

[0305] On the other hand, since the signal SELB becomes H level, the circuit 300B outputs an H signal or a voltage V2. Therefore, the transistor 202B is turned on, and the wiring 113B and This brings the line 111 into electrical continuity. Then, the voltage V1 is applied to the line 111 via the transistor 202B. It is provided on line 111.

[0306] In the period c2, the timing at which the clock signal CK1 becomes low is This may occur earlier than the timing at which transistor 201A turns off. The clock signal CK1 at the L level drives the transistor 201A until the transistor 201A is turned off. The current may be supplied to the wiring 111 through a large channel width of the transistor 201A. Increasing this setting can shorten the fall time of the signal OUTA.

[0307] In the period c2, the timing at which the clock signal CK1 becomes low is This may occur earlier than the timing at which transistor 201B turns off. The clock signal CK1 at the L level drives the transistor 201B until the transistor 201B is turned off. The current may be supplied to the wiring 111 through a large channel width of the transistor 201B. Increasing this setting can shorten the fall time of the signal OUTB.

[0308] During the period c2, the voltage V1 is applied to the wiring 111 via the transistor 202B. When the clock signal CK1 is supplied to the wiring 111 and when the clock signal CK1 is at the L level, the transistor 201B When the voltage V1 is supplied to the wiring 111 via the transistor 202B, 111, and a clock signal CK1 at a low level is input via a transistor 201B. There are three patterns:

[0309] Next, the operation of the semiconductor device in the period d2 will be described with reference to FIG. The operation of the semiconductor device in the period d1 is as follows: the signal SELA goes to the L level, and the signal SEL The difference is that B becomes H level.

[0310] Since the signal SELA becomes L level, the circuit 300A applies an L signal or a voltage V1 to the node A. Therefore, the transistor 202A is turned off, and the wiring 113A and the wiring 1 There is no electrical continuity between terminal 11 and terminal 12.

[0311] On the other hand, since the signal SELB becomes H level, the circuit 300B outputs an H signal or a voltage V2. Therefore, the transistor 202B is turned on, and the wiring 113B and This brings the line 111 into electrical continuity. Then, the voltage V1 is applied to the line 111 via the transistor 202B. It is provided on line 111.

[0312] As described above, the transistors 202A and 202B are alternately turned on. By doing so, it is possible to suppress the deterioration of the characteristics of each transistor. As a semiconductor layer of a transistor, a non-single-crystal semiconductor such as an amorphous semiconductor or a microcrystalline semiconductor is used. Materials that deteriorate easily, such as semiconductors, organic semiconductors, or oxide semiconductors, can be used. In the manufacture of a semiconductor device, the number of steps is reduced, the yield is increased, or the cost is reduced. In addition, when the semiconductor device of the present embodiment is used in a display device, Since the manufacturing method of the device becomes easier, the display device can be made large.

[0313] In addition, the deterioration of transistor characteristics can be suppressed, so the deterioration of transistors can be prevented. Therefore, it is not necessary to increase the channel width of the transistor to take into account the Since the channel width can be reduced, the layout area can be reduced. In addition, when the semiconductor device of this embodiment is used in a display device, the layout of the gate driver circuit is Since the area of ​​the pixel can be reduced, the pixel resolution can be increased. The transistor channel width can be made smaller, reducing the load on the gate driver circuit. Therefore, the power consumption of the driver circuit having the gate driver circuit can be reduced. can be reduced.

[0314] In addition, during periods b1 and b2, the clock signal CK1 at the H level drives the transistor Since the signal is supplied to the wiring 111 via the transistor 201A and the transistor 201B, The rise time or fall time of the supplied signal can be shortened. This prevents the video signal for pixels in a selected row from being written to pixels in another row. As a result, crosstalk can be reduced, and the display device can be The display quality can be improved.

[0315] In addition, the rise time or fall time of the signal supplied to the wiring 111 is shortened. Therefore, when the scanning signal corresponds to a start signal, the driving of the gate driver circuit can be The frequency can be increased. Therefore, when the semiconductor device of this embodiment is used for a display device, In this case, the display device can be made larger or the pixel resolution can be increased.

[0316] The waveforms of the signals OUTA and OUTB during the period T1 correspond to the timing of FIG. The waveforms of the signals OUTA and OUTB in the period T1 are As such, Figs. 6(A) to 6(L) can be used.

[0317] The waveforms of the signals OUTA and OUTB during the period T2 are the same as those shown in FIG. The waveforms of the signals OUTA and OUTB in the period T2 are As such, Figs. 7(A) to 7(L) can be used.

[0318] The clock signal CK1 can be unbalanced. An example of the operation of a semiconductor device when the period during which the signal is at the H level is shorter than the period during which the signal is at the L level is shown in FIG. In the timing chart of FIG. In 2, the clock signal CK1 at the L level can be supplied to the wiring 111, so that The fall times of the signals OUTA and OUTB can be shortened. When the pixel portion is extended, a video signal that should not be written to the pixel may be In addition, the period during one cycle when the signal is at H level can be changed to L level. The period may be longer than the period when the alarm becomes active.

[0319] In addition, a multi-phase clock signal can be used in the semiconductor device. For this purpose, a clock signal with n phases (n is a natural number) can be used. refers to n clock signals whose periods are shifted by 1 / n. 1 is a timing diagram showing an example of the operation of a semiconductor device when a three-phase clock signal is used for the device. This is a chart.

[0320] Note that the larger n is, the lower the clock frequency will be, which will reduce power consumption. However, if n is too large, the number of signals increases, which increases the layout area. Or the scale of the external circuit becomes large. Therefore, n is set to be smaller than 8, and preferably n is set to be smaller than 8. is less than 6, and more preferably n=4 or n=3.

[0321] In addition, during the period c1, the period d1, the period c2, or the period d2, the transistor 202A and transistor 202B can be turned on at the same time. When the signal is supplied to the wiring 111 through the transistors 202A and 202B, Since the noise of 111 can be reduced, a semiconductor device that is less susceptible to noise can be obtained. It is possible.

[0322] In addition, in the period a1, the period b1, the period a2, or the period b2, the transistor 201A and transistor 201B can be turned on. For example, during periods a1 and a2, In b1, transistor 201A is turned on and transistor 201B is turned off. Alternatively, in the period a2 and the period b2, the transistor 201A can be turned off. Therefore, the transistor 201A and the transistor 201B can be turned on. The number of times that transistor 201B and transistor 201B are turned on is reduced, so This can suppress deterioration of the resistor.

[0323] In order to realize such a driving method, for example, in the period T1, In the period T2, the signal input to the wiring 114A is maintained at the L level. As another example, in the circuit 200A, the signal A circuit having a function of maintaining the potential of the node A1 at an L level in response to SELA is provided, In the example shown in FIG. 200B, during a period T2, the potential of the node B1 is set to the L level in response to the signal SELB. It is preferable to provide a circuit having a function of maintaining the same.

[0324] <Transistor size> Next, we will explain the size of a transistor, such as its channel width and length. In addition, when describing the channel width of a transistor, it is expressed as W / L (W is It is sometimes referred to as the ratio of the channel width to the channel length.

[0325] The channel width of the transistor 201A and the channel width of the transistor 201B are approximately Alternatively, the channel width of the transistor 202A and the channel width of the transistor 202B are preferably equal to each other. It is preferable that the channel width of 02B is approximately equal to that of 02B.

[0326] In this way, by making the channel widths of the transistors approximately equal, the current supply capacity The deterioration degree of the transistors can be made approximately equal. Therefore, even if the selected transistor is switched, the waveform of the output signal OUT is kept approximately the same. It can be made easier.

[0327] For the same reason, the channel length of the transistor 201A and the The channel lengths of the transistors 202A and 202B are preferably approximately equal. It is preferable that the length of the transistor 202B be approximately equal to the channel length of the transistor 202B.

[0328] In addition, the negative terminal of the gate signal line connected to the transistor 201A or the transistor 201B When the load is large, the transistor in the circuit 200A is larger than the other transistors in the circuit 200A. The channel width of the transistor 201A is increased, or in the circuit 200B, The channel width of the transistor 201B is made larger than that of the other transistors in the is preferred.

[0329] In addition, the load of the gate signal line driven by the transistor 201A or the transistor 201B When the channel width of the transistor 201A or the transistor 201B is large, Specifically, it is preferable that the channel width of the transistor 201A and the The channel width of 01B is preferably 1000 μm to 30000 μm, more preferably 20 00μm to 20000μm, more preferably 3000μm to 8000μm or 1000 It is recommended to set it to 0μm to 18000μm.

[0330] <Configuration of Semiconductor Device> Next, regarding an example of the configuration of the semiconductor device of this embodiment, a semiconductor device different from that shown in FIG. An example of a circuit diagram of the device will be described with reference to FIG. 16(B) and FIG. 24(A) to FIG. 25(B). Reveal.

[0331] FIG. 16B and FIGS. 24A to 25B show examples of circuit diagrams of semiconductor devices. .

[0332] The semiconductor device shown in FIG. 16B has a transistor which is different from the semiconductor device shown in FIG. This corresponds to a configuration in which a capacitive element 203A is connected between the gate and the second terminal of the capacitor 201A. Alternatively, a capacitor 203B is connected between the gate and the second terminal of the transistor 201B. This corresponds to the configuration.

[0333] By adopting such a configuration, the potential of the node A1 or Therefore, the potential of the node B1 tends to rise. The potential difference (Vgs) between the gate and source of transistor 201B As a result, the transistor 201A or the transistor Alternatively, the channel width of the signal OUTA or the signal OU can be reduced. The fall time or rise time of TB can be shortened.

[0334] For example, a MOS capacitor can be used as the capacitance element 203A and the capacitance element 203B. Note that the material of one electrode of the capacitor 203A and the capacitor 203B is the same as that of the transistor. It is preferable that the material of the gate of the transistor 201A is the same as that of the gate of the transistor 201B. Alternatively, the material of the other electrode of the capacitor 203A and the capacitor 203B may be a transistor. The material is the same as that of the source or drain of the transistor 201A and the transistor 201B. By using such a material, the layout area can be reduced. Alternatively, the capacitance value can be increased.

[0335] It is preferable that the capacitance value of the capacitive element 203A and the capacitance value of the capacitive element 203B are approximately equal. Alternatively, in the capacitor 203A and the capacitor 203B, It is preferable that the areas where the poles overlap are approximately equal. A signal is input from the circuit 200A to the wiring 111, and a signal is input from the circuit 200B to the wiring 111. In the case where a signal is input, the wavelength of the signal input to the wiring 111 can be made approximately equal. can.

[0336] In the semiconductor device shown in FIG. 16A and FIG. 16B, In this way, the transistor 201A is connected to the node A1 at one electrode (for example, the positive electrode). , and the other electrode (for example, the negative electrode) is replaced with a diode 211A connected to the wiring 111. Alternatively, one electrode (for example, a positive electrode) of the transistor 202A may be connected to the wiring 111. and the other electrode (for example, the negative electrode) of a diode 212A connected to node A2. may be substituted.

[0337] In addition, one electrode (for example, a positive electrode) of the transistor 201B is connected to the node B1. , and the other electrode (for example, the negative electrode) is replaced with a diode 211B connected to the wiring 111. Alternatively, one electrode (for example, a positive electrode) of the transistor 202B may be connected to the wiring 111. and the other electrode (for example, the negative electrode) of a diode 212B connected to node B2. may be substituted.

[0338] In the semiconductor device shown in FIG. 16(A) and FIG. 16(B), Thus, the first terminal of the transistor 201A may be connected to the node A1. A first terminal of the transistor 202A is connected to the node A2. The gate may be connected to the wiring 111.

[0339] Alternatively, the first terminal of the transistor 201B may be connected to the node B1. A first terminal of the transistor 202B is connected to a node B2. The gate may be connected to the wiring 111.

[0340] Next, a configuration is provided in which a signal for transfer is generated separately from the signal OUTA, or the signal OUTB An example of a semiconductor device having a configuration for generating a signal for transfer separately is shown in FIG. This will be explained with reference to 25(B).

[0341] When the semiconductor device has multiple circuits (including the circuit 200A and the circuit 200B), The signal to be sent is not input to the wiring 111, but is input to the next stage circuit as a start signal. This makes the delay or distortion of the signal for transfer smaller than that of the signal OUTA or OUTB. Therefore, it is possible to operate the semiconductor device using a signal with reduced delay or distortion. Since the semiconductor device can be driven, the delay of the output signal of the semiconductor device can be reduced. Since the timing of charging the node A1 or the node B1 can be advanced, the operation The range can be widened. In addition, the signal for transfer may be output to the wiring 111.

[0342] For this reason, the semiconductor devices shown in FIGS. 16(A), 16(B), 24(A), and 24(B) In the device, as shown in FIG. 25A, a first terminal of the circuit 200A is connected to a wiring 112. A, a second terminal is connected to the wiring 117A, and a gate is connected to the node A1. In addition, the circuit 200B may be provided with a transistor 204A. 2B, a second terminal is connected to the wiring 117B, and a gate is connected to the node B1. A transistor 204B may be provided.

[0343] Alternatively, the semiconductor device shown in FIG. 16(A), FIG. 16(B), FIG. 24(A), and FIG. 24(B) In the device shown in FIG. 25B, a first terminal of the circuit 200A is connected to a wiring 113A. A transistor having a first terminal connected to the wiring 117A and a gate connected to the node A2. A transistor 205A may be provided. In addition, the first terminal of the circuit 200B is connected to the wiring 113B. a first terminal connected to the wiring 117B, a gate connected to the node B2, A transistor 205B may also be provided.

[0344] The transistor 204A has the same function as the transistor 201A and has the same polarity. In addition, the transistor 205A preferably has the same function as the transistor 202A. It is preferable that the transistor 204B has the same polarity as the transistor 204A. It is preferable that the transistor 201B has the same function and polarity as the transistor 201B. 205B has a similar function to transistor 202B and preferably has the same polarity. In addition, the transistor 204A, the transistor 204B, the transistor 205A, and the transistor The transistor 205B is either an N-channel transistor or a P-channel transistor. This may be used.

[0345] When a plurality of circuits in a semiconductor device are connected, the wiring 117A is connected to another stage (e.g. For example, the wiring 117B may be connected to the wiring 114A of the semiconductor device in the next stage. It may be connected to the wiring 114B of a semiconductor device in another stage (for example, the next stage). By having the above configuration, the wiring 117A and the wiring 117B function as signal lines. .

[0346] When a plurality of circuits in a semiconductor device are connected, the wiring 117A is connected to another stage (e.g. For example, the wiring 117B may be connected to the wiring 116A of the semiconductor device in the previous stage. The wiring 116B may be connected to the wiring 116B of a semiconductor device in another stage (for example, the previous stage). The wiring 117A may be disposed so as to extend to the pixel portion. With such a configuration, the wiring 117A and the wiring 117 B functions as a gate signal line or a scanning line.

[0347] <Configuration of Semiconductor Device> Next, an example of the configuration of the semiconductor device according to the present embodiment will be described with reference to FIGS. 16(A) and 16(B). 24(A) to 25(B) are different from those in FIG. 2. This will be explained with reference to 6.

[0348] The semiconductor device shown in FIG. 26 is the semiconductor device shown in FIG. 16(A) except that transistor 2 This corresponds to a configuration in which transistor 07A and transistor 207B are provided.

[0349] The transistor 207A has a first terminal connected to the wiring 113A and a second terminal connected to the wiring 113B. 11, and its gate is connected to the circuit 300A. The first terminal of the transistor is connected to the wiring 113B, the second terminal of the transistor is connected to the wiring 111, and the gate is connected to the circuit 300B.

[0350] The connection point between the gate of the transistor 207A and the circuit 300A is node A3. The connection point between the gate of transistor 207B and circuit 300B is indicated as node B3.

[0351] It is preferable that the transistor 207A has the same function as the transistor 202A. In addition, the transistor 207B may have the same function as the transistor 202B. preferable.

[0352] <Operation of Semiconductor Device> An example of the operation of the semiconductor device of FIG. 26 will be described with reference to a timing chart shown in FIG. 28(A) to 29(B) show an example of the operation of the semiconductor device of FIG. FIG.

[0353] The transistor 202A and the transistor 207A are in a gate selection period of one gate during the period T1. For example, in the period d1, During the period when the clock signal CK1 is at the H level, as shown in FIG. On the other hand, during the period d1, the transistor 202A is turned on and the transistor 207A is turned off. During the period when the clock signal CK1 is at the L level, as shown in FIG. Transistor 202A turns off and transistor 207A turns on.

[0354] In addition, the transistor 202B and the transistor 207B have one gate in the period T2. The transistors are alternately turned on every selection period or every half cycle of the clock signal CK1. For example, during the period d During the period when the clock signal CK1 is at the H level, as shown in FIG. The transistor 202B is turned on and the transistor 207B is turned off. During the period in which the clock signal CK1 is at the L level, as shown in FIG. Transistor 202B turns off and transistor 207B turns on.

[0355] In this manner, during the period T1, the transistors 202A and 207A are switched. In the period T2, the transistors 202B and 207B are turned on. This allows each transistor to be turned on for a shorter period of time. Therefore, the deterioration of each transistor can be suppressed.

[0356] Alternatively, a clock signal CK2 (for example, a clock signal A wiring to which a signal CK1 (an inverted signal of the signal CK1) is input may be connected. A wiring for inputting the clock signal CK2 may be connected to one side of the node B3.

[0357] Or, in the same period (for example, period b1 or period b2), the transistor 202A, Transistor 207A, transistor 202B, and transistor 207B are off. Alternatively, in the same period (for example, period a1 or period a2), transistor 202A, transistor 207A, transistor 202B, and transistor 207B Two or more of the transistors may be on.

[0358] Alternatively, the order in which the transistors 202A and 207A are turned on can be set arbitrarily. Also, the order in which transistors 202B and 207B are turned on may be arbitrary. may be set to

[0359] Next, regarding an example of the operation of the semiconductor device of FIG. 26, a timing chart different from that of FIG. 27 will be described. The following describes this with reference to FIG.

[0360] Transistor 202A, transistor 207A, transistor 202B, and transistor The first pixel 207B may be turned on every frame period. The period during which the transistor 202A is on is called period T1a, and the period during which the transistor 207A is off is called period T2a. The period during which the transistor 202B is turned on is indicated as a period T1b. The period during which the transistor 207B is turned on is indicated as period T2a, and the period during which the transistor 207B is turned on is indicated as period T2b.

[0361] In the timing chart of FIG. 30, the periods T1a, T2a, T1b, and Although the period T2b is shown to be arranged in sequence, the order of these periods can be arbitrary. For example, the periods T1a, T1b, T2a, and T2b may be arranged in this order. , may be arranged in multiple periods, or may be arranged randomly.

[0362] During the period d1 of the period T1a, the potential of the node A2 becomes H level, and the potential of the node A3 ( The potential of the node A3 is also referred to as a potential Va3), the potential of the node B2, and the potential of the node B3. The potential (the potential of node B3 is also referred to as potential Vb3) becomes L level. As shown in FIG. 28A, transistor 202A is turned on and transistor 207A , transistor 202B, and transistor 207B are turned off.

[0363] During period d1 of period T1b, the potential of node A3 becomes H level, and the potential of node A2 becomes The potentials of the nodes B2 and B3 become L level. As shown in FIG. 1, transistor 207A is turned on, transistor 202A, transistor Then, transistor 202B and transistor 207B are turned off.

[0364] During period d2 of period T2a, the potential of node B2 becomes H level, and the potential of node A2 becomes The potentials of the nodes A3 and B3 become L level. As shown in FIG. 1, transistor 202B is turned on, and transistor 202A, Transistor 207A and transistor 207B are turned off.

[0365] During period d2 of period T2b, the potential of node B3 becomes H level, and the potential of node A2 becomes The potential of the node A3 and the potential of the node B2 become L level. As shown in FIG. 1, transistor 207B is turned on, and transistors 202A and Then, transistor 207A and transistor 202B are turned off.

[0366] When the semiconductor device shown in FIG. 26 performs the above-mentioned operation, the transistor is turned on. The time can be shortened. Or, the signal for controlling the transistor conduction state can be shortened. Since the frequency can be lowered, the power consumption can be reduced.

[0367] Alternatively, the first terminal is connected to the wiring 113A and the second terminal is connected to the wiring 111. A plurality of transistors may be provided. The plurality of transistors may include the transistor 202A or The transistors have the same function as the transistor 207A. They may be turned on in sequence for each gate selection period or for each frame.

[0368] A transistor having a first terminal connected to the wiring 113B and a second terminal connected to the wiring 111 is also provided. A plurality of transistors may be provided. The plurality of transistors may include the transistor 202B or The transistors have the same function as the transistor 207B. They may be turned on in sequence for each gate selection period or for each frame.

[0369] By providing multiple transistors like this, each transistor is turned on. This reduces the time that each transistor is in a negative state, which helps prevent deterioration of the transistors. can.

[0370] (Embodiment 5) In this embodiment, a semiconductor device having the gate driver circuit described in the above embodiment is This article explains:

[0371] <Configuration of Semiconductor Device> The structure of the semiconductor device of this embodiment will be described with reference to FIGS. 31(A) and 31(B). 31A and 31B show examples of circuit diagrams of a semiconductor device.

[0372] In FIG. 31A, a circuit 300A includes a transistor 301A and a transistor 302. The circuit 300B includes a transistor 301B, a transistor 301C, and a circuit 400A. 302B, and circuit 400B.

[0373] Transistor 301A, transistor 302A, circuit 400A, transistor 301B 31A for an example of the configuration of the transistor 302B and the circuit 400B. Here, the transistor 301A, the transistor 302A, and the transistor 3 The transistor 301B and the transistor 302B will be described as N-channel transistors. , these transistors may be P-channel transistors.

[0374] A first terminal of the transistor 301A is connected to the wiring 114A, and a second terminal of the transistor 301A is connected to the node A1 and a gate connected to the wiring 114A. The first terminal is connected to the wiring 113A, the second terminal is connected to the node A1, and the gate is connected to the wiring 11 The circuit 400A is connected to a wiring 115A, a node A1, a wiring 113A, and a It is connected to board A2.

[0375] A first terminal of the transistor 301B is connected to the wiring 114B, and a second terminal of the transistor 301B is connected to the node The transistor 302B has a first gate connected to the first terminal B1 and a gate connected to the wiring 114B. The first terminal is connected to the wiring 113B, the second terminal is connected to the node B1, and the gate is connected to the wiring 11 The circuit 400B is connected to a wiring 115B, a node B1, a wiring 113B, and a It is connected to board B2.

[0376] Next, transistor 301A, transistor 302A, circuit 400A, transistor 3 An example of the functions of the transistor 301B, the transistor 302B, and the circuit 400B will be described.

[0377] The transistor 301A controls the timing at which the wiring 114A and the node A1 are brought into electrical contact with each other. Alternatively, the transistor 301A has a function of applying the potential of the wiring 114A to the node A1. Alternatively, the transistor 301A has a function of controlling the timing of supplying the signal. 14A (e.g., start signal SP, clock signal CK1, A clock signal CK2, a signal SELA, a signal SELB, or a voltage V2) is supplied to node A1. Alternatively, the transistor 301A has a function of controlling the timing at which a signal or a current The transistor has a function of controlling the timing at which the voltage is not supplied to the node A1. The function of the controller 301A is to control the timing of supplying the H signal or the voltage V2 to the node A1. Alternatively, the transistor 301A may control the timing for increasing the potential of the node A1. Alternatively, the transistor 301A has a function of controlling the node A1 to be in a floating state. It has a function to control timing.

[0378] Thus, the transistor 301A may be a switch, a rectifier, a diode, or The transistor 301A functions as a start-connected transistor. The control may be performed in response to the port signal SP.

[0379] The transistor 302A controls the timing at which the wiring 113A and the node A1 are brought into electrical contact with each other. Alternatively, the transistor 302A has a function of applying the potential of the wiring 113A to the node A1. Alternatively, the transistor 302A has a function of controlling the timing of supplying the signal. A signal or voltage (for example, a clock signal CK2 or a voltage V1) supplied to 13A is The transistor 302A has a function of controlling the timing of supplying the voltage to the node A1. The transistor has a function of controlling the timing of supplying the voltage V1 to the node A1. The transistor 302A has a function of controlling the timing of decreasing the potential of the node A1. Alternatively, the transistor 302A controls the timing for maintaining the potential of the node A1. It has functions.

[0380] In this way, the transistor 302A functions as a switch. The resistor 302A may be controlled in response to a reset signal RE.

[0381] The circuit 400A has a function of controlling the potential of the node A2. , and has a function of controlling the timing of supplying a signal, a voltage, or the like to the node A2. The circuit 400A has a function of controlling the timing at which a signal, voltage, etc. is not supplied to the node A2. Alternatively, the circuit 400A may have a timing for supplying an H signal or a voltage V2 to the node A2. Alternatively, the circuit 400A may supply an L signal or a voltage V1 to a node A2. Alternatively, the circuit 400A has a function of controlling the timing of supplying the signal The circuit 400A has a function of controlling the timing of increasing the potential of the node The circuit 400A has a function of controlling the timing of decreasing the potential of A2. The transistor has a function of controlling the timing for maintaining the potential of the node A2.

[0382] In this way, the circuit 400A has a function as a control circuit. , signal SELA, or the potential of node A1.

[0383] The transistor 301B controls the timing at which the wiring 114B and the node B1 are brought into conduction. Alternatively, the transistor 301B has a function of supplying the potential of the wiring 114B to the node B1. Alternatively, the transistor 301B has a function of controlling the timing of supplying the signal. 14B (e.g., start signal SP, clock signal CK1, A clock signal CK2, a signal SELA, a signal SELB, or a voltage V2) is supplied to node B1. Alternatively, the transistor 301B has a function of controlling the timing at which a signal or a current The transistor has a function of controlling the timing at which the voltage or the like is not supplied to the node B1. The function of the controller 301B is to control the timing of supplying the H signal or the voltage V2 to the node B1. Alternatively, the transistor 301B may control the timing for increasing the potential of the node B1. Alternatively, the transistor 301B has a function of controlling the node B1 to be in a floating state. It has a function to control timing.

[0384] Thus, the transistor 301B may be a switch, a rectifier, a diode, or The transistor 301B functions as a start-connected transistor. The control may be performed in response to the port signal SP.

[0385] The transistor 302B controls the timing at which the wiring 113B and the node B1 are brought into conduction. Alternatively, the transistor 302B has a function of supplying the potential of the wiring 113B to the node B1. Alternatively, the transistor 302B has a function of controlling the timing of supplying the signal. A signal or voltage (for example, a clock signal CK2 or a voltage V1) supplied to 13B is The transistor 302B has a function of controlling the timing of supplying the voltage to the node B1. The transistor has a function of controlling the timing of supplying the voltage V1 to the node B1. The transistor 302B has a function of controlling the timing of decreasing the potential of the node B1. Alternatively, the transistor 302B controls the timing for maintaining the potential of the node B1. It has functions.

[0386] In this way, the transistor 302B functions as a switch. The resistor 302B may be controlled in response to a reset signal RE.

[0387] The circuit 400B has a function of controlling the potential of the node B2. , and has a function of controlling the timing of supplying a signal, a voltage, or the like to the node B2. The circuit 400B has a function of controlling the timing at which a signal, voltage, etc. is not supplied to the node B2. Alternatively, the circuit 400B may have a timing for supplying an H signal or a voltage V2 to the node B2. Alternatively, the circuit 400B may supply an L signal or a voltage V1 to a node B2. Alternatively, the circuit 400B has a function of controlling the timing of supplying the signal to the node B2. The circuit 400B has a function of controlling the timing of increasing the potential. The circuit 400B has a function of controlling the timing of decreasing the potential of B2. It has a function of controlling the timing for maintaining the potential of node B2.

[0388] In this way, the circuit 400B has a function as a control circuit. , signal SELB, or the potential of node B1.

[0389] Next, an example of the structure of the circuit 400A and the circuit 400B will be described with reference to FIG. explain.

[0390] The circuit 400A includes a transistor 401A and a transistor 402A. 0B includes a transistor 401B and a transistor 402B.

[0391] Transistor 401A, transistor 402A, transistor 401B, and transistor An example of the configuration of the transceiver 402B will be described with reference to FIG. Transistor 401A, transistor 402A, transistor 401B, and transistor 40 2B will be described as N-channel transistors. Note that these transistors are P It may be a channel type transistor.

[0392] A first terminal of the transistor 401A is connected to the wiring 115A, and a second terminal of the transistor 401A is connected to the node A2 and a gate connected to the wiring 115A. The first terminal is connected to the wiring 113A, the second terminal is connected to the node A2, and the gate is connected to the node A It is connected to 1.

[0393] A first terminal of the transistor 401B is connected to the wiring 115B, and a second terminal of the transistor 401B is connected to the node B2 and a gate connected to the wiring 115B. The first terminal is connected to the wiring 113B, the second terminal is connected to the node B2, and the gate is connected to the node B It is connected to 1.

[0394] Next, transistor 401A, transistor 402A, transistor 401B, and transistor An example of the function of transistor 402B will be described.

[0395] The transistor 401A controls the timing at which the wiring 115A and the node A2 are brought into electrical conduction. Alternatively, the transistor 401A has a function of applying the potential of the wiring 115A to the node A2. Alternatively, the transistor 401A has a function of controlling the timing of supplying the signal. A signal or voltage (e.g., signal SELA or voltage V2) supplied to node 15A is connected to node A. 2. Alternatively, the transistor 401A has a function of controlling the timing of supplying the signal The transistor has a function of controlling the timing at which the signal or voltage is not supplied to the node A2. The transistor 401A controls the timing of supplying an H signal or a voltage V2 to the node A2. Alternatively, the transistor 401A has a function of increasing the potential of the node A2. It has the function of controlling the timing.

[0396] Thus, the transistor 401A may be a switch, a rectifier, a diode, or a The transistor 401A functions as a transistor for a signal It may be controlled according to SELA.

[0397] The transistor 402A controls the timing at which the wiring 113A and the node A2 are brought into electrical conduction. Alternatively, the transistor 402A has a function of supplying the potential of the wiring 113A to the node A2. Alternatively, the transistor 402A has a function of controlling the timing of supplying the signal. A signal or voltage (for example, a clock signal CK2 or a voltage V1) supplied to 13A is The transistor 402A has a function of controlling the timing of supplying the voltage Vcc to the node A2. The transistor has a function of controlling the timing of supplying the voltage V1 to the node A2. The transistor 402A has a function of controlling the timing of decreasing the potential of the node A2. Alternatively, the transistor 402A controls the timing for maintaining the potential of the node A2. It has functions.

[0398] In this way, the transistor 402A functions as a switch. The resistor 402A may be controlled in response to the potential of the node A1 or the potential of the wiring 111.

[0399] The transistor 401B controls the timing at which the wiring 115B and the node B2 are brought into conduction. Alternatively, the transistor 401B has a function of supplying the potential of the wiring 115B to a node B2. Alternatively, the transistor 401B has a function of controlling the timing of supplying the signal. 15B (for example, signal SELB or voltage V2) is supplied to node B 2. Alternatively, the transistor 401B has a function of controlling the timing of supplying the signal The transistor B1 has a function of controlling the timing at which the signal or voltage is not supplied to the node B2. The transistor 401B controls the timing of supplying an H signal or a voltage V2 to the node B2. Alternatively, the transistor 401B has a function of increasing the potential of the node B2. It has the function of controlling the timing.

[0400] Thus, the transistor 401B may function as a switch, a rectifier, a diode, or a The transistor 401B functions as a transistor for a signal It may be controlled according to SELB.

[0401] The transistor 402B controls the timing at which the wiring 113B and the node B2 are brought into conduction. Alternatively, the transistor 402B has a function of supplying the potential of the wiring 113B to the node B2. Alternatively, the transistor 402B has a function of controlling the timing of supplying the signal. A signal or voltage (for example, a clock signal CK2 or a voltage V1) supplied to 13B is The transistor 402B has a function of controlling the timing of supplying the voltage Vcc to the node B2. The transistor has a function of controlling the timing of supplying the voltage V1 to the node B2. The transistor 402B has a function of controlling the timing of decreasing the potential of the node B2. Alternatively, the transistor 402B controls the timing for maintaining the potential of the node B2. It has functions.

[0402] In this way, the transistor 402B functions as a switch. The resistor 402B may be controlled in response to the potential of the node B1 or the potential of the wiring 111.

[0403] <Operation of Semiconductor Device> Next, an example of the operation of the semiconductor device of FIG. 31(B) will be described with reference to FIGS. 32(A) to 35(B). 32(A) to 35(B) are, respectively, the timing charts described in the fourth embodiment. In period a1, period b1, period c1, period d1, period a2, period b2, period c2, and period d2 1 corresponds to a schematic diagram of a semiconductor device in

[0404] In addition, in the semiconductor device of FIG. 31(B), the parts common to the semiconductor device of FIG. The operation will be described with reference to the timing chart of FIG.

[0405] First, as shown in FIG. 32(A), during a period a1, the start signal SP goes to H level. Therefore, the transistor 301A is turned on, and the wiring 114A and the node A1 are Then, the start signal SP at H level is input through the transistor 301A. As a result, the potential at node A1 rises.

[0406] Eventually, the potential of node A1 becomes equal to the potential of the gate of transistor 301A (for example, voltage V 2), the threshold voltage (Vth 301A ) minus (V2-Vt h 301A), the transistor 301A is turned off. Since the node A1 is not electrically connected to the node A4, the potential of the node A1 rises. When the potential of the node A increases, the transistor 402A is turned on, and the 2. Then, the voltage V1 is applied to the node A2 through the transistor 402A. are supplied to.

[0407] During the period a1, the signal SELA is at the H level. Since 1A is turned on, the wiring 115A and the node A2 are in a conductive state. The signal SELA is supplied to node A2 via transistor 401A. Therefore, the current supply capacity of the transistor 402A is set to be larger than the current supply capacity of the transistor 401A. (For example, the channel width of transistor 402A is increased relative to the channel width of transistor 401A. By making the width of the gate line larger than the width of the gate line, the potential of the node A2 becomes L level.

[0408] During the period a1, the reset signal RE is at the L level. Since the node 302A is turned off, there is no electrical continuity between the wiring 113A and the node A1.

[0409] On the other hand, during the period a1, the start signal SP becomes H level. 301B is turned on, so that the wiring 114B and the node B1 are in a conductive state. Then, H The start signal SP of the high level is supplied to the node B1 via the transistor 301B. As a result, the potential at node B1 rises.

[0410] Eventually, the potential at node B1 becomes equal to the potential at the gate of transistor 301B (for example, voltage V 2), the threshold voltage (Vth 301B ) minus (V2-Vt h 301B ), the transistor 301B is turned off. Since the node B1 is not electrically connected to the node B1, the potential of the node B1 rises. When the potential of the node B increases, the transistor 402B is turned on, and the wiring 113B and the node B 2. Then, the voltage V1 is applied to the node B2 through the transistor 402B. are supplied to.

[0411] During the period a1, the signal SELB is at the L level. Since the line 115B is turned off, the line 115B and the node B2 are not electrically connected to each other. The potential of node B2 becomes L level.

[0412] During the period a1, the reset signal RE is at the L level. Since 302B is turned off, there is no electrical continuity between the wiring 113B and the node B1.

[0413] Next, as shown in FIG. 32(B), during a period b1, the start signal SP goes to the L level. Therefore, the transistor 301A is kept off, and the wiring 114A and the node A1 is kept in a non-conductive state.

[0414] During the period b1, the reset signal RE is maintained at the L level. Since the transistor 302A is maintained in the off state, the wiring 113A and the node A1 are not electrically connected. The potential of node A1 rises due to the bootstrap operation. Since the transistor 402A is kept on, the wiring 113A and the node A2 are not electrically connected to each other. The through state is maintained.

[0415] During the period b1, the signal SELA is maintained at the H level. Since the resistor 401A is maintained in the ON state, the wiring 115A and the node A2 are in a conductive state. As a result, the potential of node A2 is maintained at the L level.

[0416] On the other hand, during the period b1, when the start signal SP becomes L level, the transistor 301 Since B remains in the off state, the wiring 114B and the node B1 remain in a non-conducting state.

[0417] During the period b1, the reset signal RE is maintained at the L level. Since the transistor 302B is maintained in the off state, the wiring 113B and the node B1 are not electrically connected to each other. The potential of node B1 rises due to the bootstrap operation. Since the transistor 402B is kept on, the wiring 113B and the node B2 are electrically connected to each other. The through state is maintained.

[0418] During the period b1, the signal SELB is maintained at the L level. Since the resistor 401B is maintained in the off state, the wiring 115B and the node B2 are not in a conductive state. As a result, the potential of the node B2 is maintained at the L level.

[0419] Next, as shown in FIG. 33(A), during a period c1, the start signal SP goes to the L level. Therefore, the transistor 301A is kept off, and the wiring 11 4A and node A1 remain in a non-conductive state.

[0420] During the period c1, the reset signal RE is at the H level. Since the node A1 is turned on, the wiring 113A and the node A1 are electrically connected to each other. Voltage V1 is supplied to node A1 through transistor 302A, so that the voltage at node A1 When the potential at node A1 becomes L level, the transistor 40 Since node 2A is turned off, there is no electrical continuity between the wiring 113A and node A2.

[0421] During the period c1, the signal SELA is maintained at the H level. Since the resistor 401A is maintained in the ON state, the wiring 115A and the node A2 are in a conductive state. Then, the signal SELA at the H level is supplied to the node A via the transistor 401A. 2, the potential at node A2 rises to the H level.

[0422] On the other hand, during the period c1, the start signal SP is maintained at the L level. Since the transistor 301B is maintained in the off state, the wiring 114B and the node B1 are not electrically connected. Hold the state.

[0423] During the period c1, the reset signal RE is at the H level. Since the node B1 is turned on, the wiring 113B and the node B1 are in a conductive state. Voltage V1 is supplied to node B1 through transistor 302B, so that the voltage at node B1 When the potential at node B1 becomes L level, the transistor 40 Since node B2 is turned off, there is no electrical continuity between the wiring 113B and node B2.

[0424] During the period c1, the signal SELB is maintained at the L level. Since the resistor 401B is maintained in the off state, the wiring 115B and the node B2 are not in a conductive state. As a result, node B2 is in a floating state, so the potential of node B2 is at the L level. is maintained.

[0425] Next, as shown in FIG. 33(B), during a period d1, the start signal SP goes to the L level. Therefore, the transistor 301A is kept off, and the wiring 11 4A and node A1 remain in a non-conductive state.

[0426] During the period d1, the reset signal RE is at the L level. Since the node 302A is turned off, the wiring 113A and the node A1 are not electrically connected to each other. The node A1 is in a floating state, and the potential of the node A1 is maintained at the L level. Since the transistor 402A is maintained in the off state, the wiring 113A and the node A2 are not electrically connected. Maintains the state.

[0427] During the period d1, the signal SELA is maintained at the H level. Since the resistor 401A is maintained in the ON state, the wiring 115A and the node A2 are in a conductive state. Then, the signal SELA at the H level is supplied to the node A via the transistor 401A. 2, the potential at node A2 rises to the H level.

[0428] On the other hand, during the period d1, the start signal SP is maintained at the L level. Since the transistor 301B is maintained in the off state, the wiring 114B and the node B1 are not electrically connected. Hold the state.

[0429] During the period d1, the reset signal RE is at the L level. Since 302B is turned off, the wiring 113B and the node B1 are not in a conducting state. The node B1 is in a floating state, and the potential of the node B1 is maintained at the L level. Since the transistor 402B is maintained in the off state, the wiring 113B and the node B2 are not electrically connected to each other. Maintains the state.

[0430] During the period d1, the signal SELB is maintained at the L level. Since the resistor 401B is maintained in the off state, the wiring 115B and the node B2 are not in a conductive state. As a result, the node A2 is held in a floating state, so the potential of the node B2 is held at the L level. Maintained by Bell.

[0431] Next, the operation of the semiconductor device in the period a2 will be described with reference to FIG. The operation of the semiconductor device in the period a1 shown in FIG. A goes to the L level and the signal SELB goes to the H level.

[0432] As a result, the transistor 401A is turned off, and the wiring 115A and the node A2 are not connected to each other. It will be in normal state.

[0433] On the other hand, the transistor 401B is turned on, so that the wiring 115B and the node B2 are in a conductive state. Therefore, the signal SELB at H level is supplied to the node B via the transistor 401B. 2. Here, the current supply capability of the transistor 402B is (For example, the channel width of transistor 402B is set to be larger than the current supply capacity of transistor 402B. By making the channel width of the transistor 401B larger than that of the transistor 401B, the potential of the node B2 is Become Bell.

[0434] Next, the operation of the semiconductor device in the period b2 will be described with reference to FIG. The operation of the semiconductor device in the period b1 shown in FIG. A goes to the L level and the signal SELB goes to the H level.

[0435] Therefore, the transistor 401A is kept off, and the wiring 115A and the node A 2 is in a non-conductive state.

[0436] On the other hand, since the transistor 401B is kept on, the wiring 115B and the node B2 The conductive state is maintained.

[0437] Next, the operation of the semiconductor device in the period c2 will be described with reference to FIG. The operation of the semiconductor device in the period c1 shown in FIG. A goes to the L level and the signal SELB goes to the H level.

[0438] Therefore, the transistor 401A is kept off, and the wiring 115A and the node A Then, node A2 is in a floating state, so its potential is at the L level. The rules are maintained in place.

[0439] On the other hand, since the transistor 401B is kept on, the wiring 115B and the node B2 Therefore, the signal SELB at the H level keeps the transistor 401B in a conductive state. Since the potential at node B2 is supplied to node B2 via

[0440] Next, the operation of the semiconductor device in the period d2 will be described with reference to FIG. The operation of the semiconductor device in the period d1 shown in FIG. A goes to the L level and the signal SELB goes to the H level.

[0441] Therefore, the transistor 401A is kept off, and the wiring 115A and the node A Then, node A2 is in a floating state, so its potential is at the L level. The rules are maintained in place.

[0442] On the other hand, since the transistor 401B is maintained in an on state, the wiring 115B and the node B2 Therefore, the signal SELB at the H level keeps the transistor 401B in a conductive state. Since the potential of node B2 is supplied to node B2 via the high potential, the potential of node B2 is maintained at the high level.

[0443] <Transistor size> Next, let's consider the size of the transistor, such as the channel width and channel length. explain.

[0444] The channel width of the transistor 301A and the channel width of the transistor 301B are approximately Alternatively, the channel width of the transistor 302A and the channel width of the transistor 303B are preferably equal to each other. It is preferable that the channel width of the transistor 401A is approximately equal to that of the transistor 402B. It is preferable that the channel width of the transistor 401B is approximately equal to that of the transistor 401B. Alternatively, the channel width of the transistor 402A and the channel width of the transistor 402B are It is preferable that they are approximately equal.

[0445] In this way, by making the channel widths of the transistors approximately equal, the current supply capacity The deterioration degree of the transistors can be made approximately equal. Therefore, even if the selected transistor is switched, the waveform of the output signal OUT is kept approximately the same. It can be made easier.

[0446] For the same reason, the channel length of the transistor 301A and the The channel length of the transistor 302A is preferably approximately equal to that of the transistor 302B. It is preferable that the channel length of the transistor 302B is approximately equal to the channel length of the transistor 302B. The channel length of the transistor 401A is approximately equal to the channel length of the transistor 401B. Alternatively, it is preferable that the channel length of the transistor 402A and the channel length of the transistor 402 It is preferable that the channel length of B is approximately equal.

[0447] Specifically, the channel width of the transistor 301A and the channel width of the transistor 301B The width is preferably 500 μm to 3000 μm, more preferably 800 μm to 2500 μm. More preferably, the thickness is set to 1000 μm to 2000 μm.

[0448] In addition, the channel width of the transistor 302A and the channel width of the transistor 302B are Preferably, the thickness is 100 μm to 3000 μm, more preferably, 300 μm to 2000 μm, and even more preferably, The thickness is preferably 300 μm to 1000 μm.

[0449] The channel width of the transistor 401A and the channel width of the transistor 401B are Preferably, the thickness is 100 μm to 2000 μm, more preferably, 200 μm to 1500 μm, and even more preferably, The thickness is preferably 300 μm to 700 μm.

[0450] The channel width of the transistor 402A and the channel width of the transistor 402B are Preferably, the thickness is 300 μm to 3000 μm, more preferably, 500 μm to 2000 μm, and even more preferably, The thickness is preferably 700 μm to 1500 μm.

[0451] <Configuration of Semiconductor Device> Next, regarding an example of the circuit of the semiconductor device of this embodiment mode, a semiconductor device different from that shown in FIG. An example of a circuit diagram of the body device will be described with reference to FIG. 36(A) to FIG. 41(B).

[0452] 36(A) to 41(B) show examples of circuit diagrams of semiconductor devices.

[0453] The semiconductor device shown in FIG. 36A has a transistor which is different from the semiconductor device shown in FIG. A first terminal of the transistor 202A, a first terminal of the transistor 302A, and a first terminal of the transistor 402A The first terminal and the second terminal are connected to separate wirings. A first terminal of a transistor 202B and a first terminal of a transistor 302B included in the semiconductor device The terminal and the first terminal of the transistor 402B correspond to a configuration in which they are connected to separate wirings. .

[0454] In FIG. 36(A), the wiring 113A is made up of a plurality of wirings 113A_1 to 113A_3. The wiring 113B is divided into a plurality of wirings 113B_1 to 113B_3. The first terminal of the transistor 202A is connected to the wiring 113A_1. A first terminal of the transistor 302A is connected to the wiring 113A_2, and a second terminal of the transistor 40 A first terminal of the transistor 202B is connected to the wiring 113A_3. The first terminal of the transistor 302B is connected to the wiring 113B_1, and the first terminal of the transistor 302B is connected to the wiring 113B_2. and a first terminal of the transistor 402B is connected to the wiring 113B_3.

[0455] The wiring 113A_1 to wiring 113A_3 have the same function as the wiring 113A. The lines 113B_1 to 113B_3 have the same functions as the line 113B. The wirings 113A_1 to 113A_3 and the wirings 113B_1 to 113B_3 are A voltage such as a voltage V1 can be supplied. 3 may be supplied with different voltages or different signals. 113B_3 may be supplied with a separate voltage or a separate signal.

[0456] In the configurations shown in FIG. 31(B) and FIG. 36(A), as shown in FIG. 37(A), The transistor 302A has one electrode (for example, a positive electrode) connected to the node A1 and the other electrode The electrode (for example, the negative electrode) of the diode 312A connected to the wiring 116A may be replaced with the diode 312A. Alternatively, the transistor 402A may be connected such that one electrode (for example, the positive electrode) is connected to the node A2. and a diode 412A having the other electrode (for example, the negative electrode) connected to node A1. You may replace it.

[0457] In addition, the transistor 302B is connected to the node B1. , and the other electrode (for example, the negative electrode) is replaced with a diode 312B connected to the wiring 116B. Alternatively, the transistor 402B may be configured such that one electrode (e.g., the positive electrode) is connected to the node B 2 and the other electrode (e.g., the negative electrode) of a diode 412 connected to node B1. It may be substituted for B.

[0458] In the configurations shown in FIG. 31(B) and FIG. 36(A), as shown in FIG. 37(B), A first terminal of the transistor 302A is connected to the wiring 116A. The gate of the transistor 402A may be connected to the node A1. The gate of transistor 402A may be connected to node A1, and the gate of transistor 402A may be connected to node A2. stomach.

[0459] A first terminal of the transistor 302B is connected to the wiring 116B. The gate of the first transistor 402B may be connected to node B1. The gate of transistor 402B is connected to node B2. This is also fine.

[0460] In addition, in the configurations shown in FIG. 31(B), FIG. 36(A), FIG. 37(A), and FIG. 37(B), As shown in FIG. 38A, the gate of the transistor 402A is connected to the wiring 111. The gate of the transistor 402B may be connected to the wiring 111.

[0461] In addition, in the configurations shown in FIG. 31(B), FIG. 36(A), and FIG. 37(A) to FIG. 38(A), As shown in FIG. 38B, the first terminal of the transistor 301A is connected to the wiring 118A. The gate of the transistor 301A may be connected to the wiring 114A. A first terminal of the transistor 301B is connected to the wiring 118B. The port may be connected to the wiring 114B.

[0462] Alternatively, the first terminal of the transistor 301A is connected to the wiring 114A. The gate of the transistor 301A may be connected to the wiring 118A. The first terminal of the transistor 301B is connected to the wiring 114B. The gate of the transistor 301B is connected to the wiring 118. It may be connected to B.

[0463] When the voltage V2 is supplied to the wiring 118A and the wiring 118B, The wiring 118B functions as a power supply line. A clock signal CK2 may be input to the wiring 118A and the wiring 118B. , separate voltages or separate signals may be provided.

[0464] When the same voltage is input to the wiring 118A and the wiring 118B, In this case, the wiring 118A and the wiring 118B may be connected to each other. Wiring may also be used.

[0465] In addition, in the configurations shown in FIG. 31(B), FIG. 36(A), and FIG. 37(A) to FIG. 38(B), As shown in FIG. 39A, the transistor 401A is replaced with a resistor element 403A. The resistor 403A is connected between the wiring 115A and the node A2. As shown in FIG. 39B, the transistor 401B may be replaced with a resistor element 403B. The resistive element 403B is connected between the wiring 115B and a node B2.

[0466] By using the configuration shown in FIG. 39(A) and FIG. 39(B), the period c1 and the period d1 In this case, a signal SELB of L level can be supplied to node B2. During the periods c2 and d2, the signal SELA at the L level is supplied to the node A2. Therefore, the potential of the node A2 and the potential of the node B2 can be fixed, A semiconductor device that is less susceptible to the effects of noise can be obtained.

[0467] In addition, in the configurations shown in FIG. 31(B), FIG. 36(A), and FIG. 37(A) to FIG. 38(B), As shown in FIG. 39(C), the first terminal is connected to the wiring 115A, and the second terminal is A transistor 404A is provided, the gate of which is connected to the node A2. As shown in FIG. 39(D), the first terminal is connected to the wiring 115B, and the second terminal is connected to the wiring 115C. A transistor 404B having a terminal connected to node B2 and a gate connected to node B2 may be provided.

[0468] By using the configuration shown in FIG. 39(C) and FIG. 39(D), As in the case of 9(B), the potential of node A2 and the potential of node B2 can be fixed. Therefore, it is possible to obtain a semiconductor device that is less susceptible to the effects of noise.

[0469] In addition, in the configurations shown in FIG. 31(B), FIG. 36(A), and FIG. 37(A) to FIG. 39(D), As shown in FIG. 39E, the first terminal of the circuit 400A is connected to the wiring 115A. a second terminal of the transistor 401A connected to the node A2, and a gate of the transistor 401B connected to the second terminal of the transistor 401A. a transistor 405A connected to a connection point of the second terminal of the transistor 402A; The first terminal is connected to the wiring 113A, the second terminal is connected to the node A2, and the gate is and a transistor 406A connected to the node A1.

[0470] As shown in FIG. 39F, the first terminal of the circuit 400B is connected to the wiring 115B. The second terminal of the transistor 401B is connected to a node B2, and the gate of the transistor 401B is connected to the second terminal of the transistor 401B. and a transistor 405B connected to the connection point of the second terminal of the transistor 402B. , a first terminal is connected to the wiring 113B, a second terminal is connected to the node B2, and a gate is and a transistor 406B coupled to node B1.

[0471] By using the configurations shown in FIG. 39(E) and FIG. 39(F), the potential of the node A2 or Since the potential of node B2 can be set to V2, the amplitude of the signal can be increased. .

[0472] Alternatively, the first terminal of the transistor 401A and the first terminal of the transistor 405A For example, in FIG. 40A, the wiring 115A may be connected to a separate wiring. The wiring 115A_1 and the wiring 115A_2 are divided into a plurality of wirings, and the transistor 401A A first terminal of the transistor 405A is connected to the wiring 115A_1, and a first terminal of the transistor 405A is connected to the wiring In this case, a signal is input to one of the wirings 115A_1 and 115A_2. Simply input SELA and supply voltage V2 to the other side.

[0473] Alternatively, the first terminal of the transistor 401B and the first terminal of the transistor 405B For example, in FIG. 40B, the wiring 115B may be connected to a different wiring. The wiring 115B_1 and the wiring 115B_2 are divided into a plurality of wirings, and the transistor 401B A first terminal of the transistor 405B is connected to the wiring 115B_1, and a first terminal of the transistor 405B is connected to the wiring In this case, a signal is input to one of the wirings 115B_1 and 115B_2. Simply input SELB and supply voltage V2 to the other side.

[0474] By using the configuration shown in FIG. 40(A) and FIG. 40(B), the period c1 and the period d1 In this case, a signal SELB of L level can be supplied to node B2. During the periods c2 and d2, the signal SELA at the L level is supplied to the node A2. Therefore, the potential of the node A2 and the potential of the node B2 can be fixed, A semiconductor device that is less susceptible to the effects of noise can be obtained.

[0475] In addition, in the configurations shown in FIG. 31(B), FIG. 36(A), and FIG. 37(A) to FIG. 39(D), As shown in FIG. 40C, the first terminal of the circuit 400A is connected to the wiring 118A. A transistor having a second terminal connected to the node A2 and a gate connected to the wiring 118A. A first terminal of the capacitor 407A is connected to the wiring 113A, and a second terminal of the capacitor 407A is connected to the node A2. A transistor 408A having a gate connected to the node A1 and a first terminal connected to the wiring 113 A, a second terminal is connected to the node A2, and a gate is connected to the wiring 115A. A transistor 409A may be included.

[0476] As shown in FIG. 40D, the first terminal of the circuit 400B is connected to the wiring 118B. a transistor having a first terminal connected to the node B2 and a gate connected to the wiring 118B; A first terminal of the stator 407B is connected to the wiring 113B, and a second terminal of the stator 407B is connected to the node B2. A transistor 408B having a gate connected to the node B1 and a first terminal connected to the wiring 11 3B, a second terminal is connected to node B2, and a gate is connected to wiring 115B. and a transistor 409B that

[0477] By using the configuration shown in FIG. 40(C) and FIG. 40(D), the period c1 and the period d1 In this case, a signal SELB of L level can be supplied to node B2. During the periods c2 and d2, the signal SELA at the L level is supplied to the node A2. Therefore, the potential of the node A2 and the potential of the node B2 can be fixed, A semiconductor device that is less susceptible to the effects of noise can be obtained.

[0478] In addition, in the configurations shown in FIG. 31(B), FIG. 36(A), and FIG. 37(A) to FIG. 40(D), As shown in FIG. 41A, a transistor 206A and a circuit 500A may be provided. The circuit 500A includes a transistor 501A and a transistor 502A.

[0479] A first terminal of the transistor 206A is connected to the wiring 113A, and a second terminal of the transistor 206A is connected to the node A first terminal of the transistor 501A is connected to the wiring 118A. The second terminal is connected to the gate of the transistor 206A, and the gate is connected to the wiring 118A. A first terminal of the transistor 502A is connected to the wiring 113A, and a second terminal of the transistor 502A is connected to the wiring 113A. The transistor 206A has a gate connected thereto, and the gate is connected to a node A1.

[0480] In addition, as shown in FIG. 41A, a transistor 206B and a circuit 500B may be provided. The circuit 500B includes a transistor 501B and a transistor 502B.

[0481] A first terminal of the transistor 206B is connected to the wiring 113B, and a second terminal of the transistor 206B is connected to the node A first terminal of the transistor 501B is connected to the wiring 118B. The second terminal is connected to the gate of the transistor 206B, and the gate is connected to the wiring 118B. A first terminal of the transistor 502B is connected to the wiring 113B, and a second terminal of the transistor The gate of the transistor 206B is connected to a node B1.

[0482] In FIG. 41A, the gate of the transistor 206A and the gate of the transistor 501 The connection point between the second terminal of A and the second terminal of the transistor 502A is designated as node A3. In addition, the gate of the transistor 206B, the second terminal of the transistor 501B, and the The connection point with the second terminal of the transistor 502B is indicated as node B3.

[0483] A gate of the transistor 502A may be connected to the wiring 111. The gate of the transistor 502B may be connected to the wiring 111.

[0484] As another example, as shown in FIG. 41B, the circuit 500A is omitted and the transistor 20 The gate of transistor 6A may be connected to node A2. The gate of the first 206B may be connected to the node B2. This allows the circuit scale to be reduced, thereby reducing the layout area. Or, power consumption can be reduced.

[0485] Next, transistor 206A, circuit 500A, transistor 501A, and transistor 5 02A, transistor 206B, circuit 500B, transistor 501B, transistor 5 An example of the function of .02B will be described with reference to FIGS. 41(A) and 41(B).

[0486] The transistor 206A controls the timing at which the wiring 113A and the node A1 are brought into electrical contact with each other. Alternatively, the transistor 206A has a function of applying the potential of the wiring 113A to the node A1. Alternatively, the transistor 206A has a function of controlling the timing of supplying the signal. A signal or voltage (for example, a clock signal CK2 or a voltage V1) supplied to 13A is The transistor 206A has a function of controlling the timing of supplying the voltage to the node A1. The transistor has a function of controlling the timing of supplying the voltage V1 to the node A1. The transistor 206A has a function of controlling the timing of decreasing the potential of the node A1. Alternatively, the transistor 206A controls the timing for maintaining the potential of the node A1. It has functions.

[0487] In this way, the transistor 206A functions as a switch. The resistor 206A may be controlled in response to the potential of the node A3.

[0488] The circuit 500A has a function of controlling the potential of the node A3. , and has a function of controlling the timing of supplying a signal, voltage, or the like to the node A3. The circuit 500A has a function of controlling the timing at which a signal or voltage is not supplied to the node A3. Alternatively, the circuit 500A may have a timing for supplying an H signal or a voltage V2 to the node A3. Alternatively, the circuit 500A may supply an L signal or a voltage V1 to a node A3. Alternatively, the circuit 500A has a function of controlling the timing of supplying the signal to the node A3. The circuit 500A has a function of controlling the timing of increasing the potential. The circuit 500A has a function of controlling the timing of decreasing the potential of A3. The circuit 500A has a function of controlling the timing of maintaining the potential of the node A3. has a function of controlling the timing of inverting the potential of node A1 and outputting it to node A3. do.

[0489] In this manner, the circuit 500A has a function as a control circuit or an inverter circuit. The circuit 500A may be controlled in response to the potential of the node A1.

[0490] The transistor 501A controls the timing at which the wiring 118A and the node A3 are brought into electrical conduction. Alternatively, the transistor 501A has a function of applying the potential of the wiring 118A to the node A3. Alternatively, the transistor 501A has a function of controlling the timing of supplying the signal. The timing at which a signal or voltage (for example, voltage V2) supplied to 18A is supplied to node A3. Alternatively, the transistor 501A may be configured to transmit a signal or a voltage to The transistor 501A has a function of controlling the timing at which the signal is not supplied to the node A3. has a function of controlling the timing of supplying an H signal or voltage V2 to node A3. Alternatively, the transistor 501A has a function of controlling the timing of increasing the potential of the node A3. Possesses the ability.

[0491] Thus, the transistor 501A may function as a switch, a rectifier, a diode, or a It functions as a gate-connected transistor, etc.

[0492] The transistor 502A controls the timing at which the wiring 113A and the node A3 are brought into electrical conduction. Alternatively, the transistor 502A has a function of applying the potential of the wiring 113A to the node A3. Alternatively, the transistor 502A has a function of controlling the timing of supplying the signal. A signal or voltage (for example, a clock signal CK2 or a voltage V1) supplied to 13A is The transistor 502A has a function of controlling the timing of supplying the signal to the node A3. The transistor has a function of controlling the timing of supplying the voltage V1 to the node A3. The transistor 502A has a function of controlling the timing of decreasing the potential of the node A3. Alternatively, the transistor 502A controls the timing for maintaining the potential of the node A3. It has functions.

[0493] In this manner, the transistor 502A functions as a switch.

[0494] The transistor 206B controls the timing at which the wiring 113B and the node B1 are brought into conduction. Alternatively, the transistor 206B has a function of supplying the potential of the wiring 113B to the node B1. Alternatively, the transistor 206B has a function of controlling the timing of supplying the signal. A signal or voltage (for example, a clock signal CK2 or a voltage V1) supplied to 13B is The transistor 206B has a function of controlling the timing of supplying the voltage to the node B1. The transistor has a function of controlling the timing of supplying the voltage V1 to the node B1. The transistor 206B has a function of controlling the timing of decreasing the potential of the node B1. Alternatively, the transistor 206B controls the timing for maintaining the potential of the node B1. It has functions.

[0495] In this way, the transistor 206B functions as a switch. The resistor 206B may be controlled in response to the potential at node B3.

[0496] The circuit 500B has a function of controlling the potential of the node B3. , and has a function of controlling the timing of supplying a signal, a voltage, or the like to the node B3. The circuit 500B has a function of controlling the timing at which a signal, voltage, etc. is not supplied to the node B3. Alternatively, the circuit 500B may have a timing for supplying an H signal or voltage V2 to the node B3. Alternatively, the circuit 500B may supply an L signal or a voltage V1 to a node B3. Alternatively, the circuit 500B has a function of controlling the timing of supplying the signal to the node B3. The circuit 500B has a function of controlling the timing of increasing the potential. The circuit 500B has a function of controlling the timing of decreasing the potential of the input terminal B3. The circuit 500B has a function of controlling the timing for maintaining the potential of the node B3. has a function of controlling the timing of inverting the potential of node B1 and outputting it to node B3. do.

[0497] In this manner, the circuit 500B has a function as a control circuit or an inverter circuit. The circuit 500B may be controlled in response to the potential of the node B1.

[0498] The transistor 501B controls the timing at which the wiring 118B and the node B3 are brought into conduction. Alternatively, the transistor 501B has a function of supplying the potential of the wiring 118B to the node B3. Alternatively, the transistor 501B has a function of controlling the timing of supplying the signal. The timing at which a signal or voltage (for example, voltage V2) supplied to node B18B is supplied to node B3. Alternatively, the transistor 501B has a function of transmitting a signal or a voltage to the The transistor 501B has a function of controlling the timing at which the signal is not supplied to the node B3. has a function of controlling the timing of supplying the H signal or voltage V2 to node B3. Alternatively, the transistor 501B has a function of controlling the timing of increasing the potential of the node B3. Possesses the ability.

[0499] Thus, the transistor 501B may function as a switch, a rectifier, a diode, or a It functions as a gate-connected transistor, etc.

[0500] The transistor 502B controls the timing at which the wiring 113B and the node B3 are brought into conduction. Alternatively, the transistor 502B has a function of supplying the potential of the wiring 113B to the node B3. Alternatively, the transistor 502B has a function of controlling the timing of supplying the signal. A signal or voltage (for example, a clock signal CK2 or a voltage V1) supplied to 13B is The transistor 502B has a function of controlling the timing of supplying the signal to the node B3. has a function of controlling the timing of supplying the voltage V1 to the node B3. The transistor 502B has a function of controlling the timing of decreasing the potential of the node B3. Alternatively, the transistor 502B controls the timing for maintaining the potential of the node B3. It has functions.

[0501] In this manner, the transistor 502B functions as a switch.

[0502] <Operation of Semiconductor Device> Next, the operation of the semiconductor device of FIG. 41(A) will be described with reference to FIG. 42(A) to FIG. 45(B). 42(A) to 45(B) are, in order, a period a1, a period b1, a period c1, Schematic diagrams of a semiconductor device in periods d1, a2, b2, c2, and d2 do.

[0503] In the periods a1, b1, a2, and b2, the node A1 is set to an H level potential. Therefore, the circuit 500A outputs an L signal to the node A3, similar to the circuit 400A. Then, the transistor 206A is turned off, and the wiring 113A and the node A1 are non-conductive. It will be in normal state.

[0504] Specifically, in the periods a1, b1, a2, and b2, the transistor 5 Since the node A3 is turned on, the wiring 113A and the node A3 are brought into electrical continuity. V1 is supplied to node A3 via transistor 502A. Since the capacitor 501A is turned on, the wiring 118A and the node A3 are in a conductive state. Voltage V2 is supplied to node A3 through transistor 501A.

[0505] Here, the current supply capacity of the transistor 502A is the current supply capacity of the transistor 501A. (For example, the channel width of transistor 502A is set to be larger than that of transistor 501A. By making the channel width larger than that of the first transistor, the potential of the node A3 becomes L level.

[0506] In addition, in the periods a1, b1, a2, and b2, the node B1 is at the H level. Therefore, the circuit 500B outputs an L signal to the node B3 in the same manner as the circuit 400B. Then, the transistor 206B is turned off, and the wiring 113B and the node B1 becomes non-conducting.

[0507] Specifically, in the periods a1, b1, a2, and b2, the transistor 5 Since the line 113B is turned on, the line 113B and the node B3 are brought into a conductive state. V1 is supplied to node B3 via transistor 502B. Since the capacitor 501B is turned on, the wiring 118B and the node B3 are in a conductive state. Voltage V2 is supplied to node B3 through transistor 501B.

[0508] Here, the current supply capacity of the transistor 502B is the current supply capacity of the transistor 501B. (For example, the channel width of transistor 502B is set to be larger than that of transistor 501B. By making the channel width larger than that of the first transistor, the potential of the node B3 becomes L level.

[0509] In the periods c1, d1, c2, and d2, the node A1 is set to an L level potential. Therefore, the circuit 500A outputs an H signal to the node A3, similar to the circuit 400A. Then, the transistor 206A is turned on, and the wiring 113A and the node A1 are electrically connected to each other. Then, the voltage V1 is supplied to the node A1 through the transistor 206A. do.

[0510] Specifically, in periods c1, d1, c2, and d2, the transistor 5 Since the node A3 is turned off, the wiring 113A and the node A3 are not electrically connected to each other. Since the transistor 501A is turned on, electrical continuity is established between the wiring 118A and the node A3. Thus, voltage V2 is supplied to node A3 through transistor 501A.

[0511] In addition, in the periods c1, d1, c2, and d2, the node B1 is at the L level. Therefore, the circuit 500B outputs an H signal to the node B3 in the same manner as the circuit 400B. Then, the transistor 206B is turned on, and the wiring 113B and the node B1 Then, the voltage V1 is provided to the node B1 through the transistor 206B. will be provided.

[0512] Specifically, in periods c1, d1, c2, and d2, the transistor 5 Since the node B3 is turned off, the wiring 113B and the node B3 are not electrically connected to each other. Since the transistor 501B is turned on, electrical continuity is established between the wiring 118B and the node B3. Thus, voltage V2 is supplied to node B3 via transistor 501B.

[0513] In this manner, during periods c1 and d1, the transistor 206A is turned on. Then, the wiring 113A and the node A1 are brought into a conductive state. 06A to node A1. Therefore, the potential of node A1 can be fixed. Therefore, it is possible to obtain a semiconductor device that is less susceptible to the effects of noise.

[0514] In addition, during periods c2 and d2, the transistor 206B is turned on. 113B and node B1 are in a conductive state. Then, the voltage V1 is This allows the potential of node B1 to be fixed. Thus, a semiconductor device that is less susceptible to the effects of noise can be obtained.

[0515] <Transistor size> Next, let's consider the size of the transistor, such as the channel width and channel length. explain.

[0516] The channel width of the transistor 501A and the channel width of the transistor 501B are approximately Alternatively, the channel width of the transistor 502A and the channel width of the transistor 502B are preferably equal to each other. It is preferable that the channel width of 02B is approximately equal to that of 02B.

[0517] In this way, by making the channel widths of the transistors approximately equal, the current supply capacity The deterioration degree of the transistors can be made approximately equal. Therefore, even if the selected transistor is switched, the waveform of the output signal OUT is kept approximately the same. It can be made easier.

[0518] For the same reason, the channel length of the transistor 501A and the The channel lengths of the transistors 502A and 502B are preferably approximately equal. It is preferable that the length of the transistor 502B be approximately equal to the channel length of the transistor 502B.

[0519] Specifically, the channel width of the transistor 501A and the channel width of the transistor 501B The width is preferably 100 μm to 2000 μm, more preferably 200 μm to 1500 μm. , and more preferably 300 μm to 700 μm.

[0520] The channel width of the transistor 502A and the channel width of the transistor 502B are Preferably, the thickness is 300 μm to 3000 μm, more preferably, 500 μm to 2000 μm, and even more preferably, The thickness is preferably 700 μm to 1500 μm.

[0521] In the configurations shown in FIG. 31(B), FIG. 36(A), and FIG. 37(A) to FIG. 41(B), In addition, the second terminal of the transistor 302A may be connected to the wiring 111. The second terminal of the stator 302B may be connected to the wiring 111. A transistor may be provided to realize the above relationship. , the fall time of the signal OUTA and the fall time of the signal OUTB can be shortened. can.

[0522] Or, in the configurations shown in FIG. 31(B), FIG. 36(A), and FIG. 37(A) to FIG. 41(B), The first terminal of the transistor 302A is connected to the wiring 118A. A second terminal of the transistor 302A is connected to the node A2, and a gate of the transistor 302A is connected to the wiring The first terminal of the transistor 302B may be connected to the wiring 116A. The second terminal of transistor 302B is connected to node B2, and the second terminal of transistor 302B is connected to node B3. The gate of the transistor 302B may be connected to the wiring 116B. In order to realize such a connection, a transistor may be provided. Therefore, a reverse bias can be applied to the transistors 302A and 302B. Therefore, the deterioration of each transistor can be suppressed.

[0523] In the configurations shown in FIG. 31(B), FIG. 36(A), and FIG. 37(A) to FIG. 41(B), As shown in FIG. 36(B), a P-channel transistor is used as the transistor. It's fine.

[0524] In FIG. 36B, a transistor 201pA, a transistor 202pA, a transistor 301pA, transistor 302pA, transistor 401pA, and transistor 402pA is a P-channel transistor, and Transistor 201A, transistor 202A, transistor 301A, transistor 302 A, transistor 401A, and transistor 402A have the same functions.

[0525] In addition, in FIG. 36B, a transistor 201pB, a transistor 202pB, Transistor 301pB, transistor 302pB, transistor 401pB, and The transistor 402pB is a P-channel transistor, The transistor 201B, the transistor 202B, the transistor 301B, The transistors 302B, 401B, and 402B have similar functions.

[0526] In addition, when the transistor is a P-channel transistor, the wiring 113A and the wiring 113 In this case, the signal OUTA, the signal OUTB, and the clock are supplied with a voltage V1. Lock signal CK1, start signal SP, reset signal RE, signal SELA, signal SELB , the potential of node A1, the potential of node A2, the potential of node B1, and the potential of node B2. The timing chart shown in FIG. 17 corresponds to an inverted version of the timing chart shown in FIG.

[0527] (Embodiment 6) In this embodiment, a gate driver circuit (also called a "gate driver") and a gate A display device having a light-emitting driver circuit will be described with reference to FIGS.

[0528] <Display device configuration> An example of the configuration of the display device will be described with reference to FIGS. 46(A) to 46(D). The display devices of FIG. 46(A) to FIG. 46(D) include a circuit 1001, a circuit 1002, a circuit 1003, 1, a circuit 1003_2, a pixel portion 1004, and a terminal 1005.

[0529] The pixel portion 1004 includes a plurality of wirings extending from a circuit 1003_1 and a circuit 1003_2. The multiple wirings include gate lines (also called "gate signal lines"), scanning lines, The pixel portion 1004 has a function as a pixel line or a signal line. The plurality of wirings are arranged. The plurality of wirings may be video signal lines, data lines, signal lines, or The pixel portion 100 has a function as a source line (also called a "source signal line"). In FIG. 4, a plurality of wirings extending from the circuit 1003_1 and the circuit 1003_2 and the circuit 100 A plurality of pixels are arranged corresponding to a plurality of wirings extending from the pixel electrode 2.

[0530] In addition to the above-mentioned wiring, the pixel portion 1004 is provided with a power supply line, a capacitance line, or the like. In addition, wiring may be arranged to

[0531] The circuit 1001 supplies signals, The circuit 1001 has a function of controlling the timing of supplying a voltage or a current. has a function of controlling the circuit 1002, the circuit 1003_1, and the circuit 1003_2. Thus, the circuit 1001 includes a controller, a control circuit, a timing generator, a power supply, It functions as a circuit or regulator.

[0532] The circuit 1002 has a function of controlling the timing of supplying a video signal to a pixel portion 1004. Alternatively, the circuit 1002 may control the luminance or transmittance of a pixel in the pixel portion 1004. In this manner, the circuit 1002 functions as a source driver circuit or a signal line driver circuit. It functions as a drive circuit.

[0533] The circuit 1003_1 is the circuit 10A, the circuit 100A, or the circuit The circuit 1003_2 has the same function as that of the circuit 200A described in the above embodiment. The circuit has the same function as the circuit 10B, the circuit 100B, or the circuit 200B. The circuit 1003_1 and the circuit 1003_2 each function as a gate driver circuit. do.

[0534] As shown in FIG. 46(A) and FIG. 46(B), the circuits 1001 and 1002 A substrate (e.g., a semiconductor substrate or a silicon substrate) other than the substrate 1006 on which the pixel portion 1004 is formed is used. The circuit 1003_1 and the circuit 1003_2 may be formed on a substrate other than the pixel region. It may be formed on the same substrate as 1004 .

[0535] The driving frequencies of the circuits 1003_1 and 1003_2 are 2, the transistors constituting the circuits 1003_1 and 1003_2 A transistor with low mobility may be used as the transistor. The semiconductor layer of the transistor constituting the circuit 1003_2 is made of an amorphous semiconductor or a microcrystalline For example, a non-single-crystal semiconductor such as a crystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like can be used. Therefore, when manufacturing a semiconductor device, the number of steps can be reduced, the yield can be increased, or the cost can be reduced. In addition, since the manufacturing method of the semiconductor device is simplified, the display device can be made large. It can be.

[0536] As shown in FIG. 46(A), FIG. 46(C), and FIG. 46(D), 1 and the circuit 1003_2 may be disposed facing each other with the pixel portion 1004 interposed therebetween. For example, As shown in FIG. 46A, the circuit 1003_1 is disposed on the left side of the pixel portion 1004. The path 1003_2 is disposed on the right side of the pixel portion 1004. Alternatively, as shown in FIG. As shown in FIG. 1, the circuit 1003_1 and the circuit 1003_2 are on the same side (for example, For example, it may be placed on the left or right side.

[0537] In the configuration shown in FIG. 46(A) and FIG. 46(B), as shown in FIG. 46(C), The circuit 1002 may be formed over the same substrate 1006 as the pixel portion 1004 .

[0538] In the configuration shown in FIG. 46(A) to FIG. 46(C), as shown in FIG. 46(D), A part of the circuit 1002 (for example, the circuit 1002a) is attached to the substrate 10 on which the pixel section 1004 is provided. 1006, and another part of the circuit 1002 (for example, the circuit 1002b) is formed on the substrate 1006. In this case, the circuit 1002a may be formed on a different substrate. It is preferable to use a circuit having a relatively low driving frequency, such as a capacitor or a selector.

[0539] Next, the pixel of the pixel portion of the display device will be described with reference to FIG. An example of a pixel configuration is shown in FIG.

[0540] The pixel 3020 includes a transistor 3021, a liquid crystal element 3022, and a capacitor element 3023. A first terminal of the transistor 3021 is connected to a wiring 3031 and a second terminal of the transistor 3021 is connected to a One electrode of the liquid crystal element 3022 and one electrode of the capacitor element 3023 are connected to the gate. The other electrode of the liquid crystal element 3022 is connected to an electrode 3034. The other electrode of the capacitor 3023 is connected to a wiring 3033.

[0541] A video signal is input to the wiring 3031 from the circuit 1002 shown in FIG. Therefore, the wiring 3031 is a signal line, a video signal line, or a source line ("source It also functions as a "signal line."

[0542] The wiring 3032 is connected to the circuit 1003_1 and the circuit 1003_2 shown in FIG. A gate signal, a scanning signal, or a selection signal is input from the wiring 303_2. 2 functions as a gate line (also called a "gate signal line"), a scanning line, or a signal line. do.

[0543] The wiring 3033 and the electrode 3034 are connected to the circuit 1001 shown in FIG. A constant voltage is supplied from the wiring 3033. Therefore, the wiring 3033 functions as a power supply line or a capacitance line. The electrode 3034 also functions as a common electrode or a counter electrode.

[0544] A precharge voltage may be supplied to the wiring 3031. The precharge voltage is The voltage applied to the wiring 303 may be set to a value substantially equal to the voltage applied to the electrode 3034. A signal may be input to the liquid crystal element 3022. By controlling the video signal, the amplitude can be reduced and inversion drive can be realized. Alternatively, a signal can be input to the electrode 3034 to perform frame inversion. The drive can be realized.

[0545] The transistor 3021 is connected to a wiring 3031 and one electrode of the liquid crystal element 3022. It also has the function of controlling the timing of writing video signals to the pixels. In this way, the transistor 3021 functions as a switch. has.

[0546] The capacitor 3023 is connected to the potential of one electrode of the liquid crystal element 3022 and the potential of the wiring 3033. Alternatively, the voltage applied to the liquid crystal element 3022 is kept constant. In this manner, the capacitor 3023 has a function of storing a voltage so that the voltage Vcc is equal to or larger than the voltage Vcc. It has functions.

[0547] <Shift register configuration> Next, the configuration of the gate driver circuit of the display device will be described below. The configuration of the shift register of the gate driver circuit is shown in FIG. 47 and FIG. 48. 47 and 48 are examples of circuit diagrams of a shift register.

[0548] In FIG. 47, a shift register 1100A includes flip-flops 1101A_1 to The circuit has a plurality of flip-flops called flip-flops 1101A_N (N is a natural number). As shown in FIG. 47, flip-flops 1101A_1 to 1101A_N 16A can be used. .

[0549] In addition, the shift register 1100B includes flip-flops 1101B_1 to The flip-flop 1101B_N (N is a natural number) is shown in FIG. The flip-flops 1101B_1 to 1101B_N are In this case, the circuit 200B included in the semiconductor device illustrated in FIG. 16A can be used.

[0550] The shift register 1100A includes wirings 1111_1 to 1111_N and wiring 1112A. , wiring 1113A, wiring 1114A, wiring 1115A, wiring 1116A, and wiring 111 9A. And, the flip-flop 1101A_i (i is one of 1 to N) In one example, the wiring 111, the wiring 112A, the wiring 113A, the wiring 114A, and the wiring 115 A and the wiring 116A correspond to the wiring 1111_i, the wiring 1112A, the wiring 1113, A is connected to wiring 1111_i-1, wiring 1115A, and wiring 1111_i+1.

[0551] When the wiring 112A is connected to one of the wirings 1112A and 1119A, an odd number The flip-flops in the even-numbered stages and the flip-flops in the even-numbered stages are connected to the wiring 112A. They may be different.

[0552] In addition, the shift register 1100B includes wirings 1111_1 to 1111_N and wirings 11 12B, wiring 1113B, wiring 1114B, wiring 1115B, wiring 1116B, and wiring 1119B. And, flip-flop 1101B_i (i is any one of 1 to N) In any one of the above, the wiring 111, the wiring 112B, the wiring 113B, the wiring 114B, The wiring 1111_i, the wiring 1112B, and the wiring 1113_i are connected to the wiring 1114_i. 113B, the wiring 1111_i-1, the wiring 1115B, and the wiring 1111_i+1 are connected. .

[0553] When the wiring 112B is connected to one of the wirings 1112B and 1119B, an odd number The flip-flops in the even-numbered stages and the flip-flops in the even-numbered stages are connected to the wiring 112B. They may be different.

[0554] The shift register 1100A connects signals GOUTA_1 to GOUTA_N to wiring 111. The signals GOUTA_1 to GOUTA_N are output to the wirings 1111_1 to 1111_N. The output signals of the flip-flops 1101A_1 to 1101A_N are respectively and corresponds to the signal OUTA. The shift register 1100B also receives the signal GOUTB Signals GO_1 to GOUTB_N are output to wirings 1111_1 to 1111_N. The signals UTB_1 to GOUTB_N are respectively output from flip-flops 1101B_1 to This is the output signal of the flip-flop 1101B_N and corresponds to the signal OUTB. The wirings 1111_1 to 1111_N have the same function as the wiring 111.

[0555] A signal GCK1 is input to the wiring 1112A and the wiring 1112B, and The signal GCK1 and the signal GCK2 are input to the wiring 1119B. These correspond to the clock signals CK1 and CK2, respectively. The wiring 1112B and the wiring 1119A have the same function as the wiring 112A. The wiring 19B has a function similar to that of the wiring 112B.

[0556] A voltage V1 is supplied to the wiring 1113A and the wiring 1113B. 3A has the same function as the wiring 113A, and the wiring 1113B has the same function as the wiring 113B. Yes.

[0557] A signal GSP is input to the wiring 1114A and the wiring 1114B. Therefore, the wiring 1114A has the same function as the wiring 114A. The wiring 1114B has the same function as the wiring 114B.

[0558] A signal SELA is input to the wiring 1115A, and a signal SELB is input to the wiring 1115B. Therefore, the wiring 1115A has the same function as the wiring 115A, and the wiring 1115 B has the same function as the wiring 115B.

[0559] A signal GRE is input to the wiring 1116A and the wiring 1116B. This corresponds to the set signal RE. Therefore, the wiring 1116A has the same function as the wiring 116A. The wiring 1116B has the same function as the wiring 116B.

[0560] When the same signal is input to the wiring 1112A and the wiring 1112B, Alternatively, in this case, as shown in FIG. The same wiring (wiring 1112) may be used for 1112A and wiring 1112B. Separate signals or separate voltages may be input to wiring 1112A and wiring 1112B.

[0561] In addition, when the same signal is input to the wiring 1113A and the wiring 1113B, Alternatively, in this case, as shown in FIG. The same wiring (wiring 1113) may be used for 1113A and wiring 1113B. Separate signals or separate voltages may be input to wiring 1113A and wiring 1113B.

[0562] In addition, when the same signal is input to the wiring 1114A and the wiring 1114B, Alternatively, in this case, as shown in FIG. The same wiring (wiring 1114) may be used for 1114A and wiring 1114B. Separate signals or separate voltages may be input to wiring 1114A and wiring 1114B.

[0563] In addition, when the same signal is input to the wiring 1116A and the wiring 1116B, Alternatively, in this case, as shown in FIG. The same wiring (wiring 1116) may be used for 1116A and wiring 1116B. Separate signals or voltages may be input to wiring 1116A and wiring 1116B.

[0564] In addition, when the same signal is input to the wiring 1119A and the wiring 1119B, Alternatively, in this case, as shown in FIG. The same wiring (wiring 1119) may be used for 1119A and wiring 1119B. Separate signals or separate voltages may be input to wiring 1119A and wiring 1119B.

[0565] <Shift register operation> An example of the operation of the shift register will be described with reference to FIG. 49 is a timing chart showing an example of the operation of a register. In FIG. No. GCK2, Signal GSP, Signal GRE, Signal SELA, Signal SELB, Signal GOUTA_ 1 through signals GOUTA_N, and signals GOUTB_1 through GOUTB_N are shown.

[0566] First, the operation of the flip-flop 1101A_i in the kth frame (k is a natural number) is , and the operation of the flip-flop 1101B_i in the (k-1)th frame will be described.

[0567] First, the signal GOUTA_i-1 and the signal GOUTB_i become H level. The flip-flops 1101A_i and 1101B_i are the same as those in the fourth embodiment. The operation in the period a1 described above starts. Therefore, the flip-flop 1101A_i The flip-flop 1101B_i outputs an L signal to the wiring 1111_i. Outputs an L signal to i.

[0568] After that, when the signals GCK1 and GCK2 are inverted, the flip-flops 1101A_ i and the flip-flop 1101B_i are the same as those in the operation during the period b1 described in the fourth embodiment. Therefore, the flip-flop 1101A_i outputs a H signal to the wiring 1111_i. The flip-flop 1101B_i outputs an H signal to the wiring 1111_i.

[0569] After that, when the signals GCK1 and GCK2 are inverted again, the signals GOUTA_i+1 and Then, the signal GOUTB_i+1 goes to H level. The flip-flop 1101B_i operates in the period c1 described in the fourth embodiment. Therefore, the flip-flop 1101A_i outputs an L signal to the wiring 1111_i. The flip-flop 1101B_i does not output a signal to the wiring 1111_i.

[0570] After that, the signal GOUTA_i-1 and the signal GOUTB_i are again at the H level. , flip-flop 1101A_i and flip-flop 1101B_i are The flip-flop 1101A_i performs the operation during the period d1 described in 4. The flip-flop 1101B_i outputs an L signal to the wiring 1111_i. No signal is output to i.

[0571] Next, the operation of the flip-flop 1101A_i in the k+1th frame and the kth frame are The operation of the flip-flop 1101B_i in the first block will now be described.

[0572] First, the signal GOUTA_i-1 and the signal GOUTB_i become H level. The flip-flops 1101A_i and 1101B_i are the same as those in the fourth embodiment. The operation in the period a2 described above starts. Therefore, the flip-flop 1101A_i The flip-flop 1101B_i outputs an L signal to the wiring 1111_i. Outputs an L signal to i.

[0573] After that, when the signals GCK1 and GCK2 are inverted, the flip-flops 1101A_ i and the flip-flop 1101B_i are the same as those in the operation during the period b2 described in the fourth embodiment. Therefore, the flip-flop 1101A_i outputs a H signal to the wiring 1111_i. The flip-flop 1101B_i outputs an H signal to the wiring 1111_i.

[0574] After that, when the signals GCK1 and GCK2 are inverted again, the signals GOUTA_i+1 and Then, the signal GOUTB_i+1 goes to H level. The flip-flop 1101B_i operates in the period c2 described in the fourth embodiment. Therefore, the flip-flop 1101A_i outputs a signal to the wiring 1111_i. Instead, the flip-flop 1101B_i outputs an L signal to the wiring 1111_i.

[0575] After that, the signal GOUTA_i-1 and the signal GOUTB_i are again at the H level. , flip-flop 1101A_i and flip-flop 1101B_i are The flip-flop 1101A_i performs the operation during the period d2 described in 4. No signal is output to the wiring 1111_i, and the flip-flop 1101B_i is connected to the wiring 1111_ Outputs an L signal to i.

[0576] (Embodiment 7) In this embodiment, a source driver circuit (also referred to as a "source driver") will be described as follows. The following description will be given with reference to Figs. 50(A) to 50(D).

[0577] FIG. 50(A) shows an example of the configuration of a source driver circuit. The circuit 2002 includes a circuit 2001 and a circuit 2002. The device has multiple circuits, 2_N (N is a natural number). Circuit 2002_1 to circuit 2002_N are transistors 2003_1 to 2003_k (k is a natural number), respectively. The transistor 2003_1 to the transistor 2003_ For k, an N-channel transistor or a P-channel transistor can be used. In addition, the transistors 2003_1 to 2003_k are CMOS type switches. It can be used as a chip.

[0578] Regarding the connection relationship of the circuits 2002_1 to 2002_N in the source driver circuit The circuit 2002_1 will be described as an example. The first terminals of the transistors 2003_1 to 2003_k are connected to the wirings 2004_1 to 2004_k, respectively. 2004_k, and the second terminals are connected to source lines 2008_1 to 20 08_k (shown as S1, S2, and Sk in FIG. 50(B)), and is connected to the wiring 2005_1.

[0579] The circuit 2001 is a type that outputs H signals to the wirings 2005_1 to 2005_N in order. Alternatively, the circuits 2002_1 to 2002_N are sequentially controlled. In this way, the circuit 2001 has a function as a shift register. do.

[0580] Alternatively, the circuit 2001 may transmit H signals to the wirings 2005_1 to 2005_N in various orders. Alternatively, the circuits 2002_1 to 2002_N can be selected in various orders. In this way, the circuit 2001 has a function as a decoder.

[0581] The circuit 2002_1 includes wirings 2004_1 to 2004_k and source lines 2008_1 to The source line 2008_k has a function of controlling the timing of conduction between the source line 2008_k and the The circuit 2002_1 supplies the potentials of the wirings 2004_1 to 2004_k to the source line 2008 _1 to 2008_k. The circuit 2002_1 has a function as a selector. The circuit 2002_N has the same function as the circuit 2002_1.

[0582] The transistors 2003_1 to 2003_N are connected to the wiring 2004_ 1 to the wiring 2004_k and the source line 2008_1 to the source line 2008_k are connected to each other. For example, the transistor 2003_1 has a function of controlling the switching of the wiring 2004_ 1 and the source line 2008_1. The transistors 2003_1 to 2003_N are connected to the wirings 2004_1 to 2004_N, respectively. A type that supplies the potential of the wiring 2004_k to the source lines 2008_1 to 2008_k. For example, the transistor 2003_1 has a function of controlling the switching of the wiring 2004_ The transistor 2008_1 has a function of controlling the timing at which the potential of the transistor 2008_1 is supplied to the source line 2008_1. As shown in FIG. 1, the transistors 2003_1 to 2003_N function as switches. It has the function of

[0583] Each of the wirings 2004_1 to 2004_k is connected to an analog output corresponding to a video signal. When a signal corresponding to a video signal, such as a video signal, is input, the wiring 2004_1 to the wiring 20 04_k has a function as a signal line. Each of k may receive a digital signal, an analog voltage, or an analog current. .

[0584] Next, regarding an example of the operation of the source driver circuit shown in FIG. 50(A), The explanation will be given with reference to a timing chart.

[0585] In FIG. 50(B), signals 2015_1 to 2015_N and signals 2014_1 to 2014_N are shown. 2014_k. Signals 2015_1 to 2015_N are the signals The signals 2014_1 to 2014_k are output signals, and the signals 2014_1 to 2014_k are output from the wirings 2004_1 to 2004_k, respectively. This is a signal input to the wiring 2004_k.

[0586] One operation period of the source driver circuit corresponds to one gate selection period in the display device. One gate selection period is divided into, for example, a period T0 and periods T1 to TN. The period T0 is a period for simultaneously applying a precharge voltage to the pixels in the selected row. Periods T1 to TN are also called precharge periods. This is a period for writing video signals to pixels belonging to the pixel group, and is also called a writing period.

[0587] First, in a period T0, the circuit 2001 outputs an H signal to the wirings 2005_1 to 2005_6. Then, in the circuit 2002_1, the transistors 2003_1 to Transistor 2003_k turns on, so wiring 2004_1 to wiring 2004_k and source At this time, the source lines 2008_1 to 2008_k are each in a conductive state. A precharge voltage Vp is supplied to the wirings 2004_1 to 2004_k. The recharge voltage Vp is supplied via transistors 2003_1 to 2003_k. The precharge voltages are output to the source lines 2008_1 to 2008_k, respectively. Since the voltage Vp is written to the pixels belonging to the selected row, the pixels belonging to the selected row It is precharged.

[0588] In the period T1 to the period TN, the circuit 2001 outputs an H signal to the wirings 2005_1 to 20 For example, in the period T1, the circuit 2001 outputs an H signal to the wiring Then, the transistors 2003_1 to 2003_ Since k is turned on, the wiring 2004_1 to wiring 2004_k and the source line 2008_1 to At this time, the wiring 2004_1 to the wiring 2004_k are electrically connected to the source line 2008_k. Data(S1) to Data(Sk) are input to _k. Data(S1) to Da ta(Sk) is a current through the transistors 2003_1 to 2003_k. Then, among the pixels belonging to the selected row, the pixel values ​​are written to the pixels in the first to kth columns. In this way, in the periods T1 to TN, the pixels in the selected row are sequentially switched to k columns at a time. The video signal is written.

[0589] As described above, the video signal is written to the pixels in multiple columns. This can reduce the number of signals, or the number of wires required to write a video signal to a pixel. This reduces the number of connections between the substrate on which the pixel unit is formed and the external circuit, thereby improving yield. This can improve the accuracy, improve the reliability, reduce the number of parts, and reduce costs.

[0590] In addition, the video signal is written to the pixels in multiple columns at a time, which increases the write time. Therefore, it is possible to prevent insufficient writing of the video signal, The display quality can be improved.

[0591] By increasing k, the number of connections to external circuits can be reduced. However, if k is too large, the writing time to the pixel becomes short. Therefore, it is preferable that k is 6 or less. More preferably, k is 3 or more, and even more preferably, k=2.

[0592] In particular, when the number of color elements of a pixel is n (n is a natural number), k=n or k=n×d (d is For example, if the color components of a pixel are red (R), green (G), and blue (B), In the case where the division is made into three parts, k=3 or k=3×d, it is preferable that k=3 or k=3×d.

[0593] In addition, a pixel has m (m is a natural number) sub-pixels (sub-pixels are also called sub-pixels or sub-pixels). When the vector is divided into k=m or k=m×d, it is preferable that k=m×d. For example, if a pixel is divided into two sub-pixels, then k=2. When the number of primary color elements is n, it is preferable that k=m×n or k=m×n×d.

[0594] Another example of the configuration of the source driver circuit will be described with reference to FIG. When the driving frequency of the circuit 2001 and the driving frequency of the circuit 2002 are low, the circuit 2001 and The circuit 2002 may be formed using a single crystal semiconductor. As shown in FIG. The pixel portion 2007 and the circuit 2001 can be formed on the same substrate as the pixel portion 2007. This reduces the number of connections between the substrate on which the pixel unit is formed and the external circuit, thereby improving yield. This can improve the accuracy, improve the reliability, reduce the number of parts, and reduce costs.

[0595] Furthermore, the gate driver circuit 2006A and the gate driver circuit 2006B are also By forming it on the same substrate as 007, the number of connections to the external circuitry can be further reduced. The gate driver circuit 2006A can be implemented by the circuit 10A described in the above embodiment. The gate driver circuit 2006B corresponds to the circuit 100A or the circuit 200A. This corresponds to the circuit 10B, the circuit 100B, or the circuit 200B described above.

[0596] Another example of the configuration of the source driver circuit will be described with reference to FIG. As shown in FIG. 50(D), the circuit 2001 is formed on a substrate separate from the pixel portion 2007, and the circuit 2 002 may be formed on the same substrate as the pixel portion 2007. This reduces the number of connections between the board and external circuits, improving yield and reliability. It is possible to improve the image quality, reduce the number of parts, and reduce the cost. Since fewer circuits are formed on the same substrate, the frame can be made smaller.

[0597] (Embodiment 8) In a display device, an element provided in a pixel (for example, a transistor, a display element, a capacitance element, The device may be susceptible to electrostatic discharge (ESD) and noise. In order to prevent damage caused by noise, etc., a protection circuit is provided on the gate line or source line. This may happen.

[0598] In this embodiment, a configuration of a protection circuit and a configuration of a semiconductor device using the protection circuit will be described. I will explain it below.

[0599] An example of a circuit diagram of a protection circuit will be described with reference to FIGS. 51(A) to 51(G).

[0600] As the protection circuit, a protection circuit 3000 shown in FIG. In the protective circuit 3000 shown in FIG. 1, an element provided in a pixel connected to a wiring 3011 is electrostatic discharge (ESD). The protection circuit 300 is provided to prevent damage caused by noise, etc. 0 includes a transistor 3001 and a transistor 3002. The transistor 3002 is an N-channel transistor or a P-channel transistor. A data can be used.

[0601] A first terminal of the transistor 3001 is connected to a wiring 3012, and a second terminal of the transistor 3001 is connected to a wiring 3013. The transistor 3002 is connected to a first wiring 3011 and a gate thereof is connected to a wiring 3011. The first terminal is connected to the wiring 3013, the second terminal is connected to the wiring 3011, and the gate is connected to the wiring Connected to 3013.

[0602] The wiring 3011 carries signals (for example, a scanning signal, a video signal, a clock signal, a start signal, signal, reset signal, or selection signal, etc.), and voltage (e.g., negative power supply potential, ground potential, A high power supply potential (VDD) is supplied to the wiring 3012. A low power supply potential (VSS) (or ground voltage) is supplied to the wiring 3013.

[0603] If the potential of the wiring 3011 is between the low power supply potential (VSS) and the high power supply potential (VDD), Therefore, the transistor 3001 and the transistor 3002 are turned off. The signal or voltage supplied to the wiring 3011 is supplied to a pixel connected to the wiring 3011 .

[0604] On the other hand, due to the influence of static electricity or the like, a potential higher than the high power supply potential (VDD) is applied to the wiring 3011. Or a potential lower than the low power supply potential (VSS) may be supplied. In this case, The distribution is interrupted by a potential higher than the power supply potential (VDD) or lower than the low power supply potential (VSS). An element provided in the pixel connected to the line 3011 may be destroyed.

[0605] In order to prevent such electrostatic damage, high voltage is applied to the wiring 3011 due to the influence of static electricity, etc. When a potential higher than the power supply potential (VDD) is applied, the transistor 3001 turns on. Then, the charge in the wiring 3011 moves to the wiring 3012 through the transistor 3001. Therefore, the potential of the wiring 3011 decreases.

[0606] In addition, due to the influence of static electricity or the like, the wiring 3011 may be at a potential lower than the low power supply potential (VSS). When the potential Vcc is supplied to the transistor 3002, the transistor 3002 is turned on. Then, the charge of the wiring 3011 is Since the potential of the wiring 3011 increases, the potential of the wiring 3013 increases. Rise.

[0607] As described above, by providing the protective circuit 3000, the pixel connected to the wiring 3011 This makes it possible to prevent damage to the elements of the substrate due to static electricity or the like.

[0608] As a protection circuit, a protection circuit 3000 shown in FIG. 51(B) or FIG. 51(C) is used. The configuration shown in FIG. 51B may be obtained by adding transistor 3 to the configuration shown in FIG. 51(C) corresponds to the structure shown in FIG. This corresponds to the configuration shown in (A) in which the transistor 3001 and the wiring 3012 are omitted. do.

[0609] As the protection circuit, a protection circuit 3000 shown in FIG. The configuration shown in FIG. 51(D) is the same as the configuration shown in FIG. 51(A), except that the wiring 3011 and the wiring 3012 are A transistor 3003 is connected in series between the wiring 3011 and the wiring 3013. This corresponds to transistors 3004 connected in series.

[0610] In FIG. 51D, a first terminal of a transistor 3003 is connected to a wiring 3012. The second terminal of the transistor 3001 is connected to the first terminal of the transistor 3002, and the gate of the transistor The first terminal of the transistor 3004 is connected to the wiring 3001. 013, and a second terminal thereof is connected to a first terminal of a transistor 3002, and a gate is connected to the wiring 3013.

[0611] As the protection circuit, a protection circuit 3000 shown in FIG. The configuration shown in FIG. 51(E) is the same as the configuration shown in FIG. 51(D), except that the gate of the transistor 3001 is connected to the gate of transistor 3003, and the gate of transistor 3002 is connected to the gate of transistor It corresponds to the one connected to the gate of sta 3004.

[0612] As the protection circuit, a protection circuit 3000 shown in FIG. The configuration shown in FIG. 51(F) is the same as the configuration shown in FIG. 51(A), except that the wiring 3011 and the wiring 3012 are A transistor 3001 and a transistor 3003 are connected in parallel between the wiring 3011 and A transistor 3002 and a transistor 3004 are connected in parallel between the wiring 3013 and the corresponds to something.

[0613] In FIG. 51F, a first terminal of a transistor 3003 is connected to a wiring 3012. The second terminal is connected to a wiring 3011, and the gate is connected to the wiring 3011. In addition, a first terminal of the transistor 3004 is connected to the wiring 3013, and a second terminal of the transistor 3004 is connected to the wiring 3011 and the gate is connected to wiring 3013.

[0614] As the protection circuit, a protection circuit 3000 shown in FIG. The configuration shown in FIG. 51(G) is the configuration shown in FIG. 51(A) in which the gate of the transistor 3001 is A capacitance element 3005 and a resistance element 3006 are connected in parallel between the first terminal and the second terminal. A capacitance element 3007 and a resistance element 3008 are connected between the gate and the first terminal of the transistor 3002. It corresponds to a parallel connection of

[0615] By applying the configuration of FIG. 51(G), the destruction or deterioration of the protection circuit 3000 itself can be prevented. It can be prevented.

[0616] For example, when a voltage higher than a power supply potential is supplied to the wiring 3011, the transistor 30 The potential difference (Vgs) between the gate and source of transistor 01 becomes large. Since the transistor 3011 is turned on, the voltage of the wiring 3011 decreases. Since a large voltage is applied between the gate and the second terminal of transistor 300 In order to prevent this, the transistor 1 is broken or deteriorated by using a capacitance element 3005. The gate voltage of the transistor 3001 is increased, and the gate and source of the transistor 3001 are Reduce the potential difference (Vgs) between the

[0617] Specifically, when the transistor 3001 is turned on, the first The voltage at the terminal of the transistor rises instantaneously. The gate voltage of the transistor 3001 rises. This allows the potential difference (Vgs) between the gate and source of transistor 3 to be reduced. The destruction or deterioration of 001 can be suppressed.

[0618] Similarly, when a voltage lower than the power supply potential is supplied to the wiring 3011, the transistor 30 The voltage at the first terminal of the capacitor 3002 is instantaneously decreased. This causes the gate voltage of transistor 3002 to decrease. Since the potential difference (Vgs) between the gate and source of 002 can be reduced, This makes it possible to suppress damage or deterioration of the transistor 3002.

[0619] Next, the structure of a semiconductor device provided with a protection circuit will be described with reference to FIGS. 52(A) and 52(B). I will use this to explain.

[0620] FIG. 52A shows an example of the structure of a semiconductor device in which a protection circuit is provided for a gate line. In (A), the gate line 3102_1 and the gate line 3102_2 are respectively shown in FIG. A) corresponds to the wiring 3011 in FIG. 51(G).

[0621] The wiring 3012 and the wiring 3013 are wirings connected to the gate driver circuit 3100. By using such a configuration, the protection circuit 3000 is operated. The power supply voltage for the gate driver circuit can be used as the power supply voltage for the This can reduce the number of types of voltage and the number of wires for supplying the power supply voltage to the protection circuit 3000. Cut.

[0622] In Figure 52(B), a protection circuit is provided for a terminal to which a signal or voltage is supplied from an external source such as an FPC. 52B shows an example of the structure of a semiconductor device. 3 is connected to one of the external terminals. For example, the wiring 3012 is connected to the terminal 3101a. In this case, the transistor 3001 is omitted from the protection circuit provided in the terminal 3101a. Similarly, when the wiring 3013 is connected to the terminal 3101b, the terminal 3 In the protection circuit provided in 101b, the transistor 3002 can be omitted. The same applies to the protection circuits provided at the terminals 3101c and 3101d.

[0623] By using such a configuration, the number of transistors can be reduced. This allows for a reduction in the layout area.

[0624] (Embodiment 9) In this embodiment mode, a structure of a display device having a transistor and a display element and a transistor The structure of the capacitor will be described with reference to FIGS. 53(A) to 53(C).

[0625] The transistor may be, for example, a field effect transistor or a bipolar transistor. A thin film transistor (also called "TFT") is used as the field effect transistor. In addition, the field effect transistor may be a top-gate transistor or A bottom gate transistor may be used. The transistors are either channel-etched or bottom-contact (also called "inverted coplanar" type). The field effect transistor may be an N-type or a P-type. The conductivity type may be the same as above.

[0626] A field effect transistor includes, for example, a gate electrode, a source region, a channel region, and a semiconductor layer having a drain region, and a gate electrode and a semiconductor layer provided between the gate electrode and the semiconductor layer in a cross-sectional view. The semiconductor layer is made of a semiconductor film or a semiconductor substrate. It is formed by

[0627] Semiconductor materials used in the semiconductor film or semiconductor substrate include amorphous semiconductors, microcrystalline semiconductors, Examples of semiconductor materials include solid-state, single-crystal, and polycrystalline semiconductors. The body may also be used.

[0628] As oxide semiconductors, quaternary metal oxides (In-Sn-Ga-Zn-O metal oxides) etc.), ternary metal oxides (In-Ga-Zn-O metal oxides, In-Sn-Zn-O metal oxides) Metal oxides, In-Al-Zn-O metal oxides, Sn-Ga-Zn-O metal oxides, Al-Ga-Zn-O metal oxides, Sn-Al-Zn-O metal oxides, etc.) and Element-based metal oxides, etc. (In-Zn-O-based metal oxides, Sn-Zn-O-based metal oxides, Al- Zn-O metal oxide, Zn-Mg-O metal oxide, Sn-Mg-O metal oxide, I n-Mg-O metal oxides, In-Ga-O metal oxides, In-Sn-O metal oxides In addition, examples of oxide semiconductors include In-O-based metal oxides and Sn-O-based metal oxides. In addition, the above oxides, Zn-O-based metal oxides, etc. can also be used as oxide semiconductors. The oxide semiconductor is a metal oxide containing SiO2. can also be used.

[0629] In addition, as an oxide semiconductor, InMO3(ZnO) m Using materials expressed as (m>0) Here, M may be one selected from Ga, Al, Mn, and Co; It indicates multiple metal elements. For example, M is Ga, Ga and Al, Ga and Mn, Ga and Co.

[0630] FIG. 53(A) and FIG. 53(B) show the structure of a display device having a transistor and a display element. As an example, a top-gate transistor is shown in FIG. 53(A) and a In 3(B), a bottom-gate transistor is used.

[0631] In FIG. 53A, a substrate 5260 and an insulating layer 5261 provided on the substrate 5260 A semiconductor layer 5262a to 5262e is provided on the insulating layer 5261. 262, an insulating layer 5263 provided to cover the semiconductor layer 5262, and a semiconductor layer 526 2 and a conductive layer 5264 provided on the insulating layer 5263; 64 and an insulating layer 5265 having an opening; 5 shows a conductive layer 5266 provided in the opening 65.

[0632] In FIG. 53B, a substrate 5300 and a conductive layer 5301 provided on the substrate 5300 An insulating layer 5302 provided to cover the conductive layer 5301; A semiconductor layer 5303a provided on the layer 5302 and a semiconductor layer 5303b provided on the semiconductor layer 5303a A conductor layer 5303b and a conductive layer 53 provided on the semiconductor layer 5303b and the insulating layer 5302 5304, and an insulating layer 530 having an opening provided over the insulating layer 5302 and the conductive layer 5304. 5, and a conductive layer 5306 provided on the insulating layer 5305 and in the opening of the insulating layer 5305. show.

[0633] FIG. 53C shows another example of a transistor structure. A semiconductor substrate 5352 having a region 5353 and a region 5355; an insulating layer 5356 provided on the semiconductor substrate 5352; A conductive layer 5357 provided on an insulating layer 5356, an insulating layer 5354, an insulating layer 5356, and a An insulating layer 5358 having an opening is provided on the conductive layer 5357. 53C shows a conductive layer 5359 provided in an opening of the insulating layer 5358. A transistor is provided in each of the regions 5350 and 5351. The structure of the transistor shown in FIG. 53(A) and FIG. 53(B) is applied to the transistor shown in FIG. This is also fine.

[0634] As shown in FIG. 53A, a conductive layer 5266 and an insulating layer 5265 are provided. An insulating layer 5267 having an opening, and a conductive film provided in the opening of the insulating layer 5267 a conductive layer 5268 having an opening and provided over the insulating layer 5267 and the conductive layer 5268; An insulating layer 5269 and an EL layer provided on the insulating layer 5269 and in the opening of the insulating layer 5269. 5270, and a conductive layer 5271 provided on the insulating layer 5269 and the EL layer 5270. The same applies to the display device in FIG 53(B).

[0635] As shown in FIG. 53B, a conductive layer 5306 is disposed over the insulating layer 5305. The display device includes a liquid crystal layer 5307 and a conductive layer 5308 provided on the liquid crystal layer 5307. The same applies to the display device in FIG.

[0636] The insulating layer 5261 functions as a base film. The insulating layer 5354 serves as an element isolation layer (for example , a field oxide film). The conductive layer 5264, the conductive layer 5301, and the conductive layer 356 function as a gate insulating film. The insulating layer 5265, the insulating layer 5267, and the insulating layer 5357 function as a gate electrode. The conductive layer 5266 and the insulating layer 5358 function as an interlayer film or a planarization film. The conductive layer 5304 and the conductive layer 5359 are wirings, electrodes of a transistor, or electrodes of a capacitor. The conductive layer 5268 and the conductive layer 5306 function as a pixel electrode or a reflective electrode. The insulating layer 5269 functions as a partition. The conductive layer 5271 and the conductive layer 5308 , which functions as a counter electrode or a common electrode.

[0637] The substrate 5260 and the substrate 5300 may be a glass substrate, a quartz substrate, a semiconductor substrate (e.g. , silicon substrate, or single crystal substrate), SOI substrate, plastic substrate, metal substrate, stainless substrate, substrate with stainless steel foil, tungsten substrate, tungsten Substrates with foils or flexible substrates etc. may be used.

[0638] Barium borosilicate glass, aluminoborosilicate glass, etc. are used as the glass substrate. Flexible substrates include polyethylene terephthalate (PET), polyethylene naphtha Plastics such as polyether phthalate (PEN) and polyethersulfone (PES), Alternatively, a flexible synthetic resin such as acrylic may be used. Films (polypropylene, polyester, vinyl, polyvinyl fluoride, polyvinyl chloride, etc.), fibers Paper containing fibrous materials, base film (polyester, polyamide, polyimide, inorganic vapor deposition) Films, papers, etc. may also be used.

[0639] The semiconductor substrate 5352 is a single crystal silicon substrate having n-type or p-type conductivity. Alternatively, a part or the whole of the single crystal silicon substrate may be used as the semiconductor substrate 5352. The region 5353 is a region where an impurity element is added to the semiconductor substrate 5352. For example, when the semiconductor substrate 5352 has a p-type conductivity, The region 5353 has an n-type conductivity and functions as an n-well. When 52 has an n-type conductivity, region 5353 has a p-type conductivity and serves as a p-well. The region 5355 is a region where an impurity element is added to the semiconductor substrate 5352. It functions as a source region or a drain region. A well doped drain region may be provided.

[0640] The insulating layer 5261 may be a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (SiO x N y )( x>y>0) film, silicon oxynitride (SiN x O y ) (x>y>0) film, etc. When the insulating layer 5261 has a two-layer structure, For example, a silicon nitride film is used as the first insulating layer, and a silicon oxide film is used as the second insulating layer. An example of the insulating layer 5261 having a three-layer structure is The first insulating layer is a silicon oxide film, the second insulating layer is a silicon nitride film, and the third insulating layer is a silicon nitride film. An example of the insulating layer is an insulating layer provided with a silicon oxide film.

[0641] The semiconductor layer 5262, the semiconductor layer 5303a, and the semiconductor layer 5303b are each made of a non-single crystal. Semiconductors (e.g., amorphous silicon, polycrystalline silicon, microcrystalline silicon, etc.) ), single crystal semiconductor, compound semiconductor or oxide semiconductor (e.g., ZnO, InGaZn O, SiGe, GaAs, IZO (indium zinc oxide), ITO (indium tin oxide) materials), SnO, TiO, AlZnSnO(AZTO)), organic semiconductors, or carbon nanotubes A tube or the like can be used.

[0642] The region 5262a is in an intrinsic state where no impurity element is added to the semiconductor layer 5262. The region 5262a is in a state where an impurity element is added, and functions as a channel region. The impurity element added to the region 5262a may be the same as that added to the region 5262b and the region 5262c. The concentration of the impurity element added to the region 5262d or the region 5262e is lower than that of the impurity element added to the region 5262e. It is preferable that the regions 5262b and 5262d are closer to each other than the regions 5262c and 5262e. A lower concentration of impurity element is added to the semiconductor layer 5262. The region 5262b and the region 5262c function as a tally doped drain region. Region 5262c and region 5262e are regions containing high concentration impurity sources. The semiconductor layer 5262 is doped with silicon, and functions as a source region or a drain region. do.

[0643] The semiconductor layer 5303b is a semiconductor layer to which phosphorus or the like is added as an impurity element. The semiconductor layer 5303a has n-type conductivity. When a thin film is used, the semiconductor layer 5303b may be omitted.

[0644] The insulating layer 5263 and the insulating layer 5356 may be formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like. SiO x N y ) (x>y>0) film, silicon oxynitride (SiN x O y )(x>y>0) Membrane etc. A film containing oxygen or nitrogen, or a laminated structure of these may be used.

[0645] Conductive layer 5264, conductive layer 5266, conductive layer 5268, conductive layer 5271, conductive layer 5301 , a conductive layer 5304, a conductive layer 5306, a conductive layer 5308, a conductive layer 5357, and a conductive layer 53 As the conductive film 59, a single-layer conductive film or a laminated structure thereof may be used. Aluminum (Al), Tantalum (Ta), Titanium (Ti), Molybdenum (Mo) , Tungsten (W), Neodymium (Nd), Chromium (Cr), Nickel (Ni), Platinum ( Pt), gold (Au), silver (Ag), copper (Cu), manganese (Mn), cobalt (Co), Niobium (Nb), silicon (Si), iron (Fe), palladium (Pd), carbon (C), Candium (Sc), Zinc (Zn), Gallium (Ga), Indium (In), Tin (Sn ), zirconium (Zr), and cerium (Ce); A film of a single element, or a film containing one or more elements selected from this group. It is preferable to use a film made of a compound such as phosphorus (P). , boron (B), arsenic (As), oxygen (O), or the like.

[0646] The compound may be one or more elements selected from the above-mentioned elements. Compounds (e.g., alloys) containing one or more elements selected from the above-mentioned elements. Compounds of several elements with nitrogen (e.g., nitride film), Compounds of an element or elements with silicon (e.g., silicide films), or nanotubes Examples of alloys include indium tin oxide (ITO) and indium zinc oxide (ITO). (IZO), indium tin oxide with silicon oxide (ITSO), zinc oxide (ZnO), acid Tin oxide (SnO), cadmium tin oxide (CTO), aluminum neodymium (Al-Nd), Aluminum tungsten (Al-W), aluminum zirconium (Al-Zr), Aluminum titanium (Al-Ti), aluminum cerium (Al-Ce), magnesium Silver (Mg-Ag), Molybdenum Niobium (Mo-Nb), Molybdenum Tungsten (Mo- Examples of nitride films include titanium nitride, Examples of silicide films include tantalum nitride and molybdenum nitride. titanium silicide, nickel silicide, aluminum silicon, or molybdenum silicon Nanotube materials include carbon nanotubes and organic nanotubes. , inorganic nanotubes, or metallic nanotubes.

[0647] The insulating layer 5265, the insulating layer 5267, the insulating layer 5269, the insulating layer 5305, and the insulating layer 53 The insulating layer 58 may be a single-layer insulating layer or a laminated structure thereof. The insulating layer may be a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (SiO x N y )(x>y> 0) film, silicon oxynitride (SiN x O y )(x>y>0) film, etc. , DLC (Diamond-Like Carbon) or other carbon-containing films, siloxane resins, etc. Polyoxy, polyimide, polyamide, polyvinylphenol, benzocyclobutene, or Examples of the film include a film made of an organic material such as acrylic.

[0648] The EL layer 5270 has a light-emitting layer made of a light-emitting material. a hole injection layer made of a hole transport material; a hole transport layer made of an electron transport material; a layer, an electron injection layer made of an electron injection material, or a layer made of a mixture of a plurality of these materials The conductive layer 5268, the EL layer 5270, and the conductive layer 5271 may include An organic EL element is constructed.

[0649] The liquid crystal layer 5307 has liquid crystal containing a plurality of liquid crystal molecules. The state of the liquid crystal molecules is mainly determined by the pixel The light transmittance of the liquid crystal changes depending on the voltage applied between the electrode and the counter electrode. As the liquid crystal, for example, electrically controlled birefringent liquid crystal (also called ECB type liquid crystal) and dichroic dye are used. Using doped liquid crystal (also called GH liquid crystal), polymer dispersed liquid crystal, discotic liquid crystal, etc. In addition, a liquid crystal exhibiting a blue phase may be used as the liquid crystal. The liquid crystal is, for example, a liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent. Liquid crystals that exhibit a blue phase have a short response time of less than 1 msec and are optically isotropic. No alignment treatment is required and viewing angle dependency is small. Therefore, liquid crystals that exhibit a blue phase are used. This makes it possible to improve the operation speed.

[0650] Note that an insulating layer functioning as an alignment film, a protrusion layer, and a conductive layer are provided over the insulating layer 5305 and the conductive layer 5306. An insulating layer or the like that functions as a rising portion may be provided.

[0651] Note that a color filter, a black matrix, or a protrusion is provided on the conductive layer 5308. An insulating layer or the like functioning as an alignment film may be formed under the conductive layer 5308. An insulating layer may be formed.

[0652] The display device of this embodiment is provided with the gate driver circuit and the semiconductor device described in the above embodiment. In addition, the transistor described in this embodiment can be applied to the semiconductor device. The present invention can be applied to the gate driver circuit and the semiconductor device described in the embodiment. A non-single-crystal semiconductor such as an amorphous semiconductor or a microcrystalline semiconductor is used as a semiconductor layer of a transistor. Even when an organic semiconductor, an oxide semiconductor, or the like is used, the same as described in the above embodiment is used. By having the configuration of the gate driver circuit and the semiconductor device, the deterioration of the transistor is suppressed. It is possible to obtain effects such as suppression.

[0653] (Embodiment 10) In this embodiment, the configuration of the display device will be described with reference to FIGS. 54(A) to 54(C). As an example of the configuration of the display device, FIG. 54(A) shows a top view of the display device, 54(B) and 54(C) are cross-sectional views taken along the line AB in FIG. 54(A), respectively.

[0654] In FIG. 54A, a driver circuit 5392 and a pixel portion 5393 are provided on a substrate 5400. The driver circuit 5392 includes a gate driver circuit, a source driver circuit, or the like. do.

[0655] FIG. 54B shows a substrate 5400, a conductive layer 5401 provided over the substrate 5400, An insulating layer 5402 provided to cover the conductive layer 5401, and a conductive layer 5401 and an insulating layer 5402 A semiconductor layer 5403a provided on the semiconductor layer 5403a and a semiconductor A conductive layer 5404 provided over the semiconductor layer 5403b and the insulating layer 5402 an insulating layer 5405 having an opening and provided over the insulating layer 5402 and the conductive layer 5404; A conductive layer 5406 is provided on the insulating layer 5405 and in the opening of the insulating layer 5405. An insulating layer 5408 is disposed on the insulating layer 5405 and the conductive layer 5406. A liquid crystal layer 5407 is formed on the insulating layer 5408. A conductive layer 540 is formed on the liquid crystal layer 5407 and the insulating layer 5408. 9 and a substrate 5410 disposed on a conductive layer 5409.

[0656] The conductive layer 5401 functions as a gate electrode. The insulating layer 5402 functions as a gate insulating film. The conductive layer 5404 functions as a wiring, an electrode of a transistor, or an electrode of a capacitor. The insulating layer 5405 functions as an interlayer film or a planarizing film. The conductive layer 5406 The insulating layer 5408 functions as a sealing material. The conductive layer 5409 functions as a counter electrode or a common electrode.

[0657] Here, a parasitic capacitance may occur between the driver circuit 5392 and the conductive layer 5409. As a result, the output signal of the driver circuit 5392 or the potential of each node may be rounded or delayed. In addition, the power consumption of the driving circuit 5392 increases.

[0658] On the other hand, as shown in FIG. 54(B), a sealing material is provided on the driver circuit 5392. By providing an insulating layer 5408 having a dielectric constant lower than that of the liquid crystal layer, It is possible to reduce the parasitic capacitance generated between the conductive layer 5409 and the driver circuit. It is possible to reduce the distortion or delay of the output signal of 5392 or the potential of each node. Alternatively, the power consumption of the driver circuit 5392 can be reduced.

[0659] Also, as shown in FIG. 54(C), a film serving as a sealant is provided on a part of the driver circuit 5392. The same effect can be obtained by providing an insulating layer 5408 that functions as a parasitic capacitance. If there is no concern about the influence of the insulating layer 5408, the insulating layer 5408 does not need to be provided.

[0660] In this embodiment mode, a display device provided with a liquid crystal element having a liquid crystal layer will be described. However, in addition to liquid crystal elements, EL elements or electrophoretic elements are also used as display elements for display devices. There can be.

[0661] In the display device of this embodiment, the parasitic capacitance of the driver circuit can be reduced. The delay or distortion of the potential of each node can be reduced. Since there is no need to increase the current supply capacity, the channel width of the transistor can be reduced. Therefore, the layout area of ​​the drive circuit can be reduced, and the frame of the display device can be narrowed or Higher definition can be achieved.

[0662] (Embodiment 11) In this embodiment mode, a layout diagram (also referred to as a top view) of a semiconductor device will be described. As an example, a layout diagram of the semiconductor device shown in FIG.

[0663] The semiconductor device shown in FIG. 55 includes a conductive layer 901, a semiconductor layer 902, a conductive layer 903, and a conductive layer 904. 04 and a contact hole 905. Note that other conductive layers or contact holes, Alternatively, an insulating film or the like may be provided. For example, A contact hole may be formed for this purpose.

[0664] The conductive layer 901 includes a portion that functions as a gate electrode or a wiring. The conductive layer 903 includes a portion that functions as a semiconductor layer of a transistor. The conductive layer 904 includes a portion that functions as a drain. The conductive layer 901 and the conductive layer 902 are connected to each other through the contact hole 905. 904 or the conductive layer 903 and the conductive layer 904 can be connected.

[0665] In addition, a semiconductor layer 902 is formed in a portion where the conductive layer 901 and the conductive layer 903 overlap each other. Therefore, the parasitic capacitance between the conductive layer 901 and the conductive layer 903 can be reduced. For the same reason, when the conductive layer 901 and the conductive layer 904 overlap each other, A semiconductor layer 902 may be provided in a portion where the conductive layer 903 and the conductive layer 904 overlap each other. good.

[0666] A conductive layer 904 is formed on a part of the conductive layer 901, and a contact hole 905 is formed thereon. By connecting the conductive layer 901 and the conductive layer 904, the wiring resistance can be reduced. can be done.

[0667] In addition, a conductive layer 903 and a conductive layer 904 are formed on a part of the conductive layer 901, and a contact The conductive layer 901 and the conductive layer 904 are connected through a hole 905, and another contact hole The conductive layer 903 and the conductive layer 904 are connected via the wire 905, so that the wiring resistance can be further reduced.

[0668] A conductive layer 904 is formed on a part of the conductive layer 903, and a contact hole 905 is formed on the conductive layer 904. In addition, the conductive layer 903 and the conductive layer 904 are connected to each other, thereby reducing the wiring resistance. can be done.

[0669] In addition, the conductive layer 901 or the conductive layer 903 is formed under a part of the conductive layer 904, and a contact The conductive layer 904 is connected to the conductive layer 901 or the conductive layer 903 through the hole 905. This makes it possible to reduce the wiring resistance.

[0670] (Embodiment 12) In this embodiment, the gate driver circuit and the semiconductor device described in the above embodiment are FIG. 56A shows an example of an electronic device using a display device and an application example of a semiconductor device. - Explanation will be given with reference to Figure 57 (H).

[0671] 56(A) to 56(H) and 57(A) to 57(D) show examples of electronic devices. These electronic devices are made up of a housing 5000, a display unit 5001, and a speaker 5003. , LED lamp 5004, operation key 5005, connection terminal 5006, sensor 5007, The operation keys 5005 include a power switch or an operation switch. The sensor 5007 includes a force, a displacement, a position, a velocity, an acceleration, an angular velocity, a rotation speed, etc. ,distance, light, liquid, magnetic, temperature, chemical, sound, time, hardness, electric field, current, voltage, power, It has the ability to measure radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays.

[0672] FIG. 56(A) shows a mobile computer, which includes, in addition to the above, a switch 5009. , an infrared port 5010, etc. FIG. 56(B) shows a portable image reproducing device equipped with a recording medium. In addition to the above, the device may include a display unit 5002, a recording medium, FIG. 56(C) shows a goggle-type display, which is similar to the above-mentioned one. In addition to the above, the device has a display unit 5002, a support unit 5012, and earphones 5013. D) is a portable gaming machine, which in addition to the above-mentioned components, has a recording medium reading unit 5011 and the like.

[0673] FIG. 56(E) shows a projector, which includes, in addition to the above, a light source 5033, a projection lens, FIG. 56(F) shows a portable gaming machine, which, in addition to the above, has a display unit 5002, a recording medium reading unit 5011, etc. FIG. 56(G) shows a television receiver. In addition to the above, it has a tuner, an image processor, etc. Figure 56(H) shows a portable television. In addition to the above, the receiver also includes a charger 5017 capable of transmitting and receiving signals.

[0674] FIG. 57(A) shows a display, which includes a support base 5018 and the like in addition to the above. FIG. 57(B) shows a camera, which, in addition to the above, has an external connection port 5019, a shutter The touch panel 5015 and the image receiving unit 5016 are shown in FIG. 57(C). In addition to the above, a pointing device 5020, an external connection port 5019, a reader FIG. 57D shows a mobile phone, which includes the above-mentioned components. The company has antennas, tuners for one-segment partial reception services for mobile phones and mobile terminals, etc. do.

[0675] Also, the electronic devices shown in FIGS. 56(A) to 56(H) and 57(A) to 57(D) may have various functions other than those described above.

[0676] For example, functions to display information (still images, videos, text images, etc.) on the display unit, touch panel Functions that display calendars, dates, or times, software (programs, etc.) A function for controlling processing by wireless communication, a function for wireless communication using a computer network A function to connect to a network, a function to transmit or receive data using wireless communication, It has the function of reading out the programs or data recorded in the body and displaying them on the display unit, etc. It may be possible.

[0677] Furthermore, in an electronic device having a plurality of display units, it is possible to display mainly video information on one display unit. and another display unit that mainly displays text information, or The device may have a function of displaying a stereoscopic image by displaying an image taking into account parallax. .

[0678] Furthermore, in electronic devices having an image receiving unit, a function for taking still images and a function for taking moving images are provided. Functions for automatically or manually correcting captured images, and for storing captured images on a recording medium (externally set The function of storing the captured image on a display unit, etc. It may have.

[0679] The electronic device described in this embodiment has a display unit for displaying some information. The display unit of the electronic device of this embodiment mode is provided with the gate driver circuit described in the above embodiment mode. By applying the semiconductor device or display device, the reliability and yield can be improved. This makes it possible to reduce costs, increase the size of the display unit, and increase the resolution of the display unit.

[0680] Next, application examples of the semiconductor device will be described with reference to FIGS. 57(E) to 57(H).

[0681] An example of a semiconductor device installed in a building is shown in FIG. 57(E) and FIG. 57(F). In addition, an example in which a semiconductor device is integrated with a moving object will be described with reference to FIG. This will be described with reference to FIG.

[0682] In FIG. 57(E), the semiconductor device is integrated with the wall of the building. In FIG. 7(E), the semiconductor device includes a housing 5022, a display unit 5023, and a remote control as an operation unit. The semiconductor device includes a speaker 5025 and the like. The semiconductor device is integrated with the wall of the building. Therefore, the semiconductor device can be installed without requiring a large space for installation.

[0683] In FIG. 57(F), the semiconductor device is integrated with a unit bathroom 5027, which is a building. A display panel 5026 constituting a semiconductor device is provided in a unit bathroom 5027. It is attached integrally to the bathtub, allowing bathers to watch the display panel 5026.

[0684] In addition, in Figure 57(E) and Figure 57(F), walls and a unit bath are listed as structures. However, semiconductor devices can be installed in a variety of other structures.

[0685] In FIG. 57G, the semiconductor device is mounted on a display panel 5028 of a vehicle body 5029. It is installed and displays on demand the operation of the vehicle or information input from inside and outside the vehicle. The semiconductor device may have a navigation function.

[0686] In FIG. 57(H), the semiconductor device is integrated into a passenger airplane. 57(H) shows that a display panel 5031 is provided on the ceiling 5030 above the seats of a passenger aircraft. The display panel 5031 is attached to a hinge portion 5032. The hinge part 5032 is attached to the ceiling 5030 via the The display panel 5031 can be operated by the passenger. It has the function of displaying information.

[0687] In addition, although automobiles and airplanes are shown as moving objects in Figures 57(G) and 57(H), Other vehicles include motorcycles, automobiles, buses, etc., trains (monorails, railways, etc.) The semiconductor device can be installed in various moving objects such as aircraft, ships, etc. EXAMPLES

[0688] In this embodiment, in a semiconductor device having two gate driver circuits, It was verified by circuit simulation that the delay or distortion of the signal output to the I testify.

[0689] In the circuit simulation, the semiconductor device described in FIG. 31(B) of the fifth embodiment was In the semiconductor device shown in FIG. 31B, the wiring 111 is a gate signal line, a circuit 20 Circuit 200A and circuit 200B each correspond to a gate driver circuit.

[0690] FIG. 59 is a circuit diagram of a semiconductor device used as a comparative example. The circuit 6200 includes a transistor 6201, a transistor 6202, a transistor 6301, The semiconductor memory device includes a transistor 6302, a transistor 6401, and a transistor 6402.

[0691] A first terminal of the transistor 6201 is connected to the wiring 6112, and a second terminal of the transistor 6201 is connected to the wiring 6112. 111 and a gate connected to a node C1. The first terminal is connected to the wiring 6113, the second terminal is connected to the wiring 6111, and the gate is a node Connected to C2.

[0692] A first terminal of the transistor 6301 is connected to the wiring 6114 and a second terminal of the transistor 6301 is connected to the node The transistor 6302 is connected to C1 and has a gate connected to a wiring 6114. The first terminal is connected to the wiring 6113, the second terminal is connected to the node C1, and the gate is connected to the wiring 61 A first terminal of the transistor 6401 is connected to the wiring 6115. The terminal of transistor 6 is connected to node C2, and the gate is connected to a wiring 6115. 402 has a first terminal connected to the wiring 6113 and a second terminal connected to the node C2. The gate is connected to the gate of transistor 6201 .

[0693] 60(A) to 61 show the results of calculations by circuit simulation. The threshold voltage of the transistor was set to 5 V, and the field effect Mobility 1cm 2 / Vs. In addition, the voltage amplitude of the clock signal CK1 is set to 30V ( The H level potential was assumed to be 30V, the L level potential was assumed to be 0V, and the ground potential was assumed to be 0V.

[0694] Here, the transistor 201A and the transistor 201B in FIG. The transistor 6201 in 59 has the same characteristics as the transistor 6201 in 59. The transistor 202A, the transistor 202B, the transistor 6202, the transistor 301A, Transistor 301B and transistor 6301, transistor 302A and transistor 30 2B and transistor 6302, transistor 401A and transistor 401B and transistor 6401, transistor 402A, transistor 402B, and transistor 6402, The same characteristics were used for each.

[0695] 31B and the wiring 6 in FIG. The same voltage was input to the wiring 114A, the wiring 114B, and the wiring 6114. The same start pulse (SP) is input to the wiring 116A, the wiring 116B, and the wiring 611. The same reset signal (RE) was input to the wiring 115A. A signal SELB was input to the wiring 115B. A constant voltage was input to the wiring 6115. did.

[0696] FIG. 60(A) shows a calculation result by a circuit simulation using the circuit diagram shown in FIG. 31(B). FIG. 60(B) shows the results of a circuit simulation using the circuit diagram shown in FIG. This is a calculation result. In FIG. 60(A), the potential Va1 of the node A1 and the potential V a2, Vb1 of node B1, Vb2 of node B2, and the voltage of the output signal (OUT) of the wiring 111. In FIG. 60B, the potential Vc1 of the node C1 and the potential V c2 indicates the potential of the output signal (OUT) of the signal line 6111.

[0697] 61, the potential of the output signal (OUT) of the wiring 111 in FIG. is compared with the potential of the output signal (OUT) of the signal line 6111 in FIG.

[0698] As shown in FIG. 61, the output signal (OUT) output to the wiring 111 in FIG. 60(A) However, the delay is reduced compared to the output signal (OUT) output to the signal line 6111 in FIG. 60(B). It was confirmed that this would be the case. [Explanation of symbols]

[0699] 10A circuit 10B circuit 10C circuit 10D Circuit 11 Wiring 50 Pixel section 51 Gate driver circuit 52 Gate driver circuit 54 Gate Line 100A circuit 100B Circuit 100C circuit 100D Circuit 101A Switch 101B Switch 101C Switch 101D Switch 102A Switch 102B Switch 102C Switch 102D Switch 103A Switch 103B Switch 111 Wiring 112 Wiring 112A Wiring 112B Wiring 112C Wiring 112D Wiring 113 Wiring 113A Wiring 113B Wiring 113C Wiring 113D Wiring 114A Wiring 114B Wiring 115A Wiring 115B Wiring 116A Wiring 116B Wiring 117A wiring 117B Wiring 118A Wiring 118B Wiring Route 121A Route 121B Route 122A Route 122B 200A circuit 200B circuit 201A Transistor 201B Transistor 201pA transistor 201pB transistor 202A Transistor 202B Transistor 202pA transistor 202pB transistor 203A Capacitive element 203B Capacitive element 204A Transistor 204B Transistor 205A Transistor 205B Transistor 206A Transistor 206B Transistor 207A Transistor 207B Transistor 211A Diode 211B Diode 212A Diode 212B Diode 300A circuit 300B circuit 301A Transistor 301B Transistor 301pA transistor 301pB transistor 302A Transistor 302B Transistor 302pA transistor 302pB transistor 312A Diode 312B Diode 400A circuit 400B Circuit 401A Transistor 401B Transistor 401pA transistor 401pB transistor 402A Transistor 402B Transistor 402pA transistor 402pB transistor 403A Resistance element 403B Resistance element 404A Transistor 404B Transistor 405A Transistor 405B Transistor 406A Transistor 406B Transistor 407A Transistor 407B Transistor 408A Transistor 408B Transistor 409A Transistor 409B Transistor 412A Diode 412B Diode 500A circuit 500B circuit 501A Transistor 501B Transistor 502A Transistor 502B Transistor 901 Conductive layer 902 Semiconductor layer 903 Conductive layer 904 Conductive layer 905 Contact Hole 1001 Circuit 1002 Circuit 1002a Circuit 1002b Circuit 1003 Circuit 1004 Pixel section 1005 Terminal 1006 Board 1100A Shift Register 1100B Shift Register 1101A Flip-Flop 1101B Flip-flop 1111 Wiring 1112 Wiring 1112A Wiring 1112B Wiring 1113 Wiring 1113A Wiring 1113B Wiring 1114 Wiring 1114A Wiring 1114B Wiring 1115A Wiring 1115B Wiring 1116 Wiring 1116A Wiring 1116B Wiring 1119 Wiring 1119A Wiring 1119B Wiring 2001 Circuit 2002 Circuit 2003 Transistor 2004 Wiring 2005 Wiring 2006A Gate driver circuit 2006B Gate driver circuit 2007 Pixel section 2008 Source Line 2014 signal 2015 signal 3000 protection circuit 3001 Transistor 3002 Transistor 3003 Transistor 3004 Transistor 3005 Capacitive element 3006 Resistance element 3007 Capacitive element 3008 Resistance element 3011 Wiring 3012 Wiring 3013 Wiring 3020 pixels 3021 Transistor 3022 Liquid crystal element 3023 Capacitive element 3031 Wiring 3032 Wiring 3033 Wiring 3034 Electrode 3100 Gate driver circuit 3101a terminal 3101b terminal 3101c terminal 3101d Terminal 3102 Gate line 5000 cabinet 5001 Display section 5002 Display section 5003 Speaker 5004 LED Lamp 5005 Operation key 5006 Connection terminal 5007 Sensor 5008 Microphone 5009 Switch 5010 Infrared port 5011 Recording medium reading unit 5012 Support part 5013 Earphones 5015 Shutter button 5016 Image receiving unit 5017 charger 5018 Support stand 5019 External connection port 5020 Pointing Device 5021 Reader / Writer 5022 Case 5023 Display section 5024 Remote control device 5025 Speaker 5026 Display Panel 5027 Unit Bath 5028 Display Panel 5029 Body 5030 Ceiling 5031 Display Panel 5032 Hinge part 5033 Light source 5034 Projection Lens 5102 Pixel unit 5108 Gate driver circuit 5110 Gate driver circuit 5112 Source driver circuit 5260 PCB 5261 Insulation layer 5262 Semiconductor layer 5262a area 5262b area 5262c area 5262d area 5262e area 5263 Insulation layer 5264 Conductive layer 5265 Insulation layer 5266 Conductive layer 5267 Insulating layer 5268 Conductive layer 5269 Insulation layer 5270 EL layer 5271 Conductive layer 5300 Board 5301 Conductive layer 5302 Insulating layer 5303a Semiconductor layer 5303b Semiconductor layer 5304 Conductive layer 5305 Insulation layer 5306 Conductive layer 5307 Liquid crystal layer 5308 Conductive layer 5350 area 5351 area 5352 Semiconductor substrate 5353 area 5354 Insulation layer 5355 area 5356 Insulation layer 5357 Conductive layer 5358 Insulation layer 5359 Conductive layer 5392 Drive circuit 5393 Pixel section 5400 Board 5401 Conductive layer 5402 Insulating layer 5403a Semiconductor layer 5403b Semiconductor layer 5404 Conductive layer 5405 Insulating layer 5406 Conductive layer 5407 Liquid crystal layer 5408 Insulating layer 5409 Conductive layer 5410 Substrate 6111 Wiring 6112 Wiring 6113 Wiring 6114 Wiring 6115 Wiring 6116 Wiring 6200 Circuit 6201 Transistor 6202 Transistor 6301 Transistor 6302 Transistor 6401 Transistor 6402 Transistor

Claims

1. a first transistor to a tenth transistor and a first wiring to a seventh wiring; one of a source and a drain of the first transistor is electrically connected to the first wiring; the other of the source and the drain of the first transistor is electrically connected to the second wiring; one of a source and a drain of the second transistor is electrically connected to the third wiring; the other of the source and the drain of the second transistor is electrically connected to the first wiring; one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor; a gate of the third transistor is electrically connected to the seventh wiring; one of a source and a drain of the fourth transistor is electrically connected to the third wiring; the other of the source and the drain of the fourth transistor is electrically connected to the gate of the first transistor; one of a source and a drain of the fifth transistor is electrically connected to a gate of the second transistor; the other of the source and the drain of the fifth transistor is electrically connected to the fourth wiring; a gate of the fifth transistor is electrically connected to the fourth wiring; one of a source and a drain of the sixth transistor is electrically connected to a gate of the second transistor; the other of the source and the drain of the sixth transistor is electrically connected to the fourth wiring; a gate of the sixth transistor is electrically connected to a gate of the second transistor; one of a source and a drain of the seventh transistor is electrically connected to the third wiring; the other of the source and the drain of the seventh transistor is electrically connected to the gate of the second transistor; a gate of the seventh transistor is electrically connected to a gate of the first transistor; one of a source and a drain of the eighth transistor is electrically connected to a gate of the fourth transistor; the other of the source and the drain of the eighth transistor is electrically connected to the fifth wiring; a gate of the eighth transistor is electrically connected to the fifth wiring; one of a source and a drain of the ninth transistor is electrically connected to the third wiring, the other of the source and the drain of the ninth transistor is electrically connected to the gate of the fourth transistor; a gate of the ninth transistor is electrically connected to a gate of the first transistor; one of a source and a drain of the tenth transistor is electrically connected to the third wiring; the other of the source and the drain of the tenth transistor is electrically connected to the gate of the first transistor; a gate of the tenth transistor is electrically connected to the sixth wiring; The fourth wiring has a function as a clock signal line. Display device.

2. a first transistor to a tenth transistor and a first wiring to a seventh wiring; one of a source and a drain of the first transistor is electrically connected to the first wiring; the other of the source and the drain of the first transistor is electrically connected to the second wiring; one of a source and a drain of the second transistor is electrically connected to the third wiring; the other of the source and the drain of the second transistor is electrically connected to the first wiring; one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor; a gate of the third transistor is electrically connected to the seventh wiring; one of a source and a drain of the fourth transistor is electrically connected to the third wiring; the other of the source and the drain of the fourth transistor is electrically connected to the gate of the first transistor; one of a source and a drain of the fifth transistor is electrically connected to a gate of the second transistor; the other of the source and the drain of the fifth transistor is electrically connected to the fourth wiring; a gate of the fifth transistor is electrically connected to the fourth wiring; one of a source and a drain of the sixth transistor is electrically connected to a gate of the second transistor; the other of the source and the drain of the sixth transistor is electrically connected to the fourth wiring; a gate of the sixth transistor is electrically connected to a gate of the second transistor; one of a source and a drain of the seventh transistor is electrically connected to the third wiring; the other of the source and the drain of the seventh transistor is electrically connected to the gate of the second transistor; a gate of the seventh transistor is electrically connected to a gate of the first transistor; one of a source and a drain of the eighth transistor is electrically connected to a gate of the fourth transistor; the other of the source and the drain of the eighth transistor is electrically connected to the fifth wiring; a gate of the eighth transistor is electrically connected to the fifth wiring; one of a source and a drain of the ninth transistor is electrically connected to the third wiring, the other of the source and the drain of the ninth transistor is electrically connected to the gate of the fourth transistor; a gate of the ninth transistor is electrically connected to a gate of the first transistor; one of a source and a drain of the tenth transistor is electrically connected to the third wiring; the other of the source and the drain of the tenth transistor is electrically connected to the gate of the first transistor; a gate of the tenth transistor is electrically connected to the sixth wiring; the first wiring has a function of outputting a signal; the second wiring has a function as a first clock signal line, the third wiring has a function as a first power supply line, the fourth wiring has a function as a second clock signal line, The fifth wiring has a function as a second power supply line. Display device.

3. a first transistor to a tenth transistor and a first wiring to a seventh wiring; one of a source and a drain of the first transistor is electrically connected to the first wiring; the other of the source and the drain of the first transistor is electrically connected to the second wiring; one of a source and a drain of the second transistor is electrically connected to the third wiring; the other of the source and the drain of the second transistor is electrically connected to the first wiring; one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor; a gate of the third transistor is electrically connected to the seventh wiring; one of a source and a drain of the fourth transistor is electrically connected to the third wiring; the other of the source and the drain of the fourth transistor is electrically connected to the gate of the first transistor; one of a source and a drain of the fifth transistor is electrically connected to a gate of the second transistor; the other of the source and the drain of the fifth transistor is electrically connected to the fourth wiring; a gate of the fifth transistor is electrically connected to the fourth wiring; one of a source and a drain of the sixth transistor is electrically connected to a gate of the second transistor; the other of the source and the drain of the sixth transistor is electrically connected to the fourth wiring; a gate of the sixth transistor is electrically connected to a gate of the second transistor; one of a source and a drain of the seventh transistor is electrically connected to the third wiring; the other of the source and the drain of the seventh transistor is electrically connected to the gate of the second transistor; a gate of the seventh transistor is electrically connected to a gate of the first transistor; one of a source and a drain of the eighth transistor is electrically connected to a gate of the fourth transistor; the other of the source and the drain of the eighth transistor is electrically connected to the fifth wiring; a gate of the eighth transistor is electrically connected to the fifth wiring; one of a source and a drain of the ninth transistor is electrically connected to the third wiring, the other of the source and the drain of the ninth transistor is electrically connected to the gate of the fourth transistor; a gate of the ninth transistor is electrically connected to a gate of the first transistor; one of a source and a drain of the tenth transistor is electrically connected to the third wiring; the other of the source and the drain of the tenth transistor is electrically connected to the gate of the first transistor; a gate of the tenth transistor is electrically connected to the sixth wiring; a channel width of the seventh transistor is larger than a channel width of the fifth transistor; The fourth wiring has a function as a clock signal line. Display device.

4. a first transistor to a tenth transistor and a first wiring to a seventh wiring; one of a source and a drain of the first transistor is electrically connected to the first wiring; the other of the source and the drain of the first transistor is electrically connected to the second wiring; one of a source and a drain of the second transistor is electrically connected to the third wiring; the other of the source and the drain of the second transistor is electrically connected to the first wiring; one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor; a gate of the third transistor is electrically connected to the seventh wiring; one of a source and a drain of the fourth transistor is electrically connected to the third wiring; the other of the source and the drain of the fourth transistor is electrically connected to the gate of the first transistor; one of a source and a drain of the fifth transistor is electrically connected to a gate of the second transistor; the other of the source and the drain of the fifth transistor is electrically connected to the fourth wiring; a gate of the fifth transistor is electrically connected to the fourth wiring; one of a source and a drain of the sixth transistor is electrically connected to a gate of the second transistor; the other of the source and the drain of the sixth transistor is electrically connected to the fourth wiring; a gate of the sixth transistor is electrically connected to a gate of the second transistor; one of a source and a drain of the seventh transistor is electrically connected to the third wiring; the other of the source and the drain of the seventh transistor is electrically connected to the gate of the second transistor; a gate of the seventh transistor is electrically connected to a gate of the first transistor; one of a source and a drain of the eighth transistor is electrically connected to a gate of the fourth transistor; the other of the source and the drain of the eighth transistor is electrically connected to the fifth wiring; a gate of the eighth transistor is electrically connected to the fifth wiring; one of a source and a drain of the ninth transistor is electrically connected to the third wiring, the other of the source and the drain of the ninth transistor is electrically connected to the gate of the fourth transistor; a gate of the ninth transistor is electrically connected to a gate of the first transistor; one of a source and a drain of the tenth transistor is electrically connected to the third wiring; the other of the source and the drain of the tenth transistor is electrically connected to the gate of the first transistor; a gate of the tenth transistor is electrically connected to the sixth wiring; the ninth transistor has a channel width greater than the eighth transistor; The fourth wiring has a function as a clock signal line. Display device.

5. a first transistor to a tenth transistor and a first wiring to a seventh wiring; one of a source and a drain of the first transistor is electrically connected to the first wiring; the other of the source and the drain of the first transistor is electrically connected to the second wiring; one of a source and a drain of the second transistor is electrically connected to the third wiring; the other of the source and the drain of the second transistor is electrically connected to the first wiring; one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor; a gate of the third transistor is electrically connected to the seventh wiring; one of a source and a drain of the fourth transistor is electrically connected to the third wiring; the other of the source and the drain of the fourth transistor is electrically connected to the gate of the first transistor; one of a source and a drain of the fifth transistor is electrically connected to a gate of the second transistor; the other of the source and the drain of the fifth transistor is electrically connected to the fourth wiring; a gate of the fifth transistor is electrically connected to the fourth wiring; one of a source and a drain of the sixth transistor is electrically connected to a gate of the second transistor; the other of the source and the drain of the sixth transistor is electrically connected to the fourth wiring; a gate of the sixth transistor is electrically connected to a gate of the second transistor; one of a source and a drain of the seventh transistor is electrically connected to the third wiring; the other of the source and the drain of the seventh transistor is electrically connected to the gate of the second transistor; a gate of the seventh transistor is electrically connected to a gate of the first transistor; one of a source and a drain of the eighth transistor is electrically connected to a gate of the fourth transistor; the other of the source and the drain of the eighth transistor is electrically connected to the fifth wiring; a gate of the eighth transistor is electrically connected to the fifth wiring; one of a source and a drain of the ninth transistor is electrically connected to the third wiring, the other of the source and the drain of the ninth transistor is electrically connected to the gate of the fourth transistor; a gate of the ninth transistor is electrically connected to a gate of the first transistor; one of a source and a drain of the tenth transistor is electrically connected to the third wiring; the other of the source and the drain of the tenth transistor is electrically connected to the gate of the first transistor; a gate of the tenth transistor is electrically connected to the sixth wiring; a channel width of the seventh transistor is larger than a channel width of the fifth transistor; the ninth transistor has a channel width greater than the eighth transistor; the first wiring has a function of outputting a signal; the second wiring has a function as a first clock signal line, the third wiring has a function as a first power supply line, the fourth wiring has a function as a second clock signal line, The fifth wiring has a function as a second power supply line. Display device.

Images