Method for manufacturing semiconductor device

Abstract

To provide a method for manufacturing a semiconductor device with a high yield rate.SOLUTION: A method for manufacturing a semiconductor device of the embodiment comprises: a step for forming a first insulating film on the annular convex portion and on the inclined portion of a semiconductor wafer having a first surface and a second surface on the opposite side of the first surface, an annular convex portion on the periphery of the first surface, a concave portion on the center side, and an inclined portion connecting the annular convex portion and the concave portion; a step for installing a dicing tape on the semiconductor wafer on the first side; a step for cutting the semiconductor wafer to separate the annular convex and inclined portions from the concave portions; and a step for separating the separated annular convex and inclined portions from the dicing tape.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] An embodiment of the present invention relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] Power semiconductor devices designed for power control, including semiconductor elements such as MOSFETs (Metal-Oxide-Semiconductor Field-Effect-Transistors) and IGBTs (Insulated Gate Bipolar Transistors), are being developed for a wide range of applications, including power generation and transmission, rotating machines such as pumps and blowers, power supply devices for communication systems and factories, railways using AC motors, electric vehicles, and home appliances.

[0003] Normally, semiconductor devices are manufactured by thinning a semiconductor wafer to a desired thickness using a method such as the TAIKO process, wet etching, or dry etching. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2007-335659 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a method for manufacturing a semiconductor device with a high yield. [Means for solving the problem]

[0006] A semiconductor device of an embodiment and a manufacturing method of a semiconductor device of an embodiment include a step of forming a first insulating film on the annular convex portion and the inclined portion of a semiconductor wafer having a first surface and a second surface opposite to the first surface, the semiconductor wafer having an annular convex portion on the outer periphery of the first surface, a concave portion toward the center, and an inclined portion connecting the annular convex portion and the concave portion, a step of providing a dicing tape on the semiconductor wafer on the first surface side, a step of cutting the semiconductor wafer and separating the annular convex portion and the inclined portion from the concave portion, and a step of separating the separated annular convex portion and the inclined portion from the dicing tape. [Brief description of the drawings]

[0007] [Figure 1] 3 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment. [Diagram 2] 5A to 5C are schematic cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to an embodiment. [Diagram 3] 3A to 3C are schematic top views illustrating steps of a method for manufacturing a semiconductor device according to an embodiment. [Figure 4] 5A to 5C are schematic cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to an embodiment. [Diagram 5] 5A to 5C are schematic cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to an embodiment. [Figure 6] 5A to 5C are schematic cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to an embodiment. [Figure 7] 5A to 5C are schematic cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to an embodiment. [Figure 8] 3 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment. [Figure 9] 5A to 5C are schematic cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to an embodiment. [Figure 10] 5A to 5C are schematic cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to an embodiment. [Figure 11] 5A to 5C are schematic cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to an embodiment. [Figure 12] 5A to 5C are schematic cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to an embodiment. [Figure 13] 5A to 5C are schematic cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to an embodiment. [Figure 14] 5A to 5C are schematic cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to an embodiment. [Figure 15] 5A to 5C are schematic cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to an embodiment. [Figure 16] 5A to 5C are schematic cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to an embodiment. [Figure 17] 5A to 5C are schematic cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to an embodiment. [Figure 18] 5A to 5C are schematic cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to an embodiment. [Figure 19] 5A to 5C are schematic cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to an embodiment. [Figure 20] 5A to 5C are schematic cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to an embodiment. [Figure 21] FIG. 2 is a partial schematic cross-sectional view of a semiconductor wafer and a first insulating film according to the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same or similar components are denoted by the same reference numerals, and the description of components that have already been described may be omitted.

[0009] (First embodiment) A manufacturing method for a semiconductor device of a first embodiment includes a step (first step) of forming a first insulating film on the annular convex portion and the inclined portion of a semiconductor wafer having a first surface and a second surface opposite to the first surface, the semiconductor wafer having an annular convex portion on the outer periphery of the first surface, a concave portion toward the center, and an inclined surface connecting the annular convex portion and the concave portion, a step (second step) of providing a dicing tape on the semiconductor wafer on the first surface side, a step (third step) of cutting the semiconductor wafer and separating the annular convex portion and the inclined portion from the concave portion, and a step (fourth step) of separating the separated annular convex portion and the inclined portion from the dicing tape.

[0010] The specific type and structure of the semiconductor device in the embodiment are not limited. The semiconductor device in the embodiment is, for example, an integrated circuit, a diode, or a transistor. The semiconductor device in the embodiment is, for example, a FET (field effect transistor), a MOSFET, an IGBT, a HEMT (high electron mobility transistor), or a Schottky barrier diode.

[0011] FIG. 1 is a flow chart of a method for manufacturing a semiconductor device according to the first embodiment. 1A and 1B are schematic cross-sectional views and schematic top plan views illustrating steps of a method for manufacturing a semiconductor device according to a first embodiment;

[0012] 2, the process schematic top view of Fig. 3, and the process schematic cross-sectional view of Fig. 4, a process (first process) of forming a first insulating film 2 on the annular convex portion C and the inclined portion B of a semiconductor wafer 1 having a first surface X and a second surface Y on the opposite side of the first surface X, and having an annular convex portion C on the outer periphery of the first surface X, a concave portion A on the central side, and an inclined portion B connecting the annular convex portion C and the concave portion A will be described. In the first embodiment and other embodiments, each process schematic cross-sectional view is, for example, a cross-sectional view of a-a' in the process schematic top view of Fig. 3.

[0013] A first insulating film 2 is formed on the annular convex portion C and the inclined portion B of the first surface X of the semiconductor wafer 1 .

[0014] The semiconductor wafer 1 is a member in which a semiconductor element region is formed on a substrate whose center side has been thinned by, for example, a TAIKO process, wet etching, dry etching, etc. The semiconductor wafer 1 is, for example, a circular wafer.

[0015] The semiconductor wafer 1 has, from the center toward the outer periphery, a recess A, an inclined portion B, and an annular protrusion C. The inclined portion B connects the recess A and the annular protrusion C.

[0016] The side of the semiconductor wafer 1 on which the recess A exists is defined as a first side X (rear side). The surface of the semiconductor wafer 1 opposite to the first side X is defined as a second side Y (front side).

[0017] A semiconductor element region is formed in the recess A of the semiconductor wafer 1. The semiconductor wafer 1 is not particularly limited to Si, SiC, GaN, etc. The recess A has a flat or nearly flat surface. It is preferable that the recess A has no protrusions on the outer periphery (the connection side F between the recess A and the inclined portion B is circular or nearly circular).

[0018] Because the outer periphery is thick, the strength is high even if the recess A on the central side is thin. The high strength makes it easy to process for forming semiconductor element regions, electrode pads, etc.

[0019] In the first embodiment, electrodes of the semiconductor device are not illustrated on the first surface X side and the second surface Y side of the semiconductor wafer 1, but some of the electrodes may be formed on the first surface X side and / or the second surface Y side of the semiconductor wafer 1 before the first step, or some of the electrodes may be formed on the first surface X side and / or the second surface Y side of the semiconductor wafer 1 before the first step between the first and second steps.

[0020] An annular convex portion C that is thicker than the recessed portion A is present on the outer periphery of the semiconductor wafer 1. The semiconductor wafer 1 has a so-called rim shape. A flat surface D and / or an approximately flat surface D are present on the side of the inclined portion B of the annular convex portion C. It is preferable that the annular convex portion C has no protrusions on the center side (the boundary portion (connecting edge) E between the annular convex portion C and the inclined portion B is circular or approximately circular). The flat surface D and / or the approximately flat surface D of the annular convex portion C is a surface excluding the curved portion on the outer periphery side of the annular convex portion C. The flat surface D and / or the approximately flat surface D of the annular convex portion C may have unevenness due to the formation of the recessed portion A, etc.

[0021] The center side of inclined portion B connects to recess A. The outer periphery side of inclined portion B connects to annular convex portion C. It is inclined with respect to the surface of recess A. The inclination angle R (taper angle) of inclined portion B is the angle of the surface of inclined portion B with respect to the surface of recess A. The inclination angle R is adjusted when recess A is formed.

[0022] The inclination angle R is preferably 20° or more and 75° or less, and more preferably 30° or more and 60° or less. If the inclination angle R is small, the volume of the recess A tends to be small, and the ineffective area is likely to increase. If the inclination angle R is large, the effective area can be increased. If the inclination angle R is close to a right angle, it is not preferable because it becomes difficult to form the first insulating film 2.

[0023] The inclined portion B has a surface resembling the side surface of a truncated cone. The surface of the inclined portion B is an inclined surface having minute irregularities. The inclined portion B may have a curved surface or a surface having steps from the annular convex portion C side to the concave portion A side.

[0024] A first insulating film 2 is formed on a semiconductor wafer 1 in the process schematic cross-sectional view of FIG. 1 to obtain a member shown in the process schematic cross-sectional view of FIG. 2. The first insulating film 2 can be formed by forming it entirely on the first surface X by low-temperature plasma-enhanced chemical vapor deposition (CVD), and then processing it by performing lithography using a mask. The first insulating film 2 can also be an inkjet printed film, a thermosetting resin film, a seal and a coating film processed into the shape of the first insulating film 2, etc. When an inkjet printed film, a thermosetting resin film, a seal and a coating film processed into the shape of the first insulating film 2 are used as the first insulating film 2, it is preferable that these films are heated or baked.

[0025] The temperature of the semiconductor wafer 1 when the first insulating film 2 is formed by low-temperature plasma CVD is preferably 200° C. or less.

[0026] The first insulating film 2 is preferably an inorganic insulating film. The first insulating film 2 is preferably a SiO2 film, a SiN film, or a SiON film. The first insulating film 2 may be a laminated film of two or more films selected from the group consisting of a SiO2 film, a SiN film, and a SiON film. The first insulating film 2 may contain an organic material such as a resin.

[0027] The first insulating film 2 is formed on the surface of the annular convex portion C on the first surface X side of the semiconductor wafer 1 and on the inclined portion B. The first insulating film 2 is preferably formed on a boundary portion E (edge ​​or corner) between the surface of the annular convex portion C on the first surface X side of the semiconductor wafer 1 and the inclined portion B.

[0028] The first insulating film 2 is bonded to the dicing tape 3 with a bonding force weaker than that of the first surface X of the semiconductor wafer 1. Therefore, the portion on which the first insulating film 2 is formed has good separability from the dicing tape 3.

[0029] It is preferable that the first insulating film 2 is formed on 40% to 100% of the area of ​​the surface of the annular convex portion C on the first surface X side of the semiconductor wafer 1. The outer circumferential side of the annular convex portion C is curved, and the first insulating film 2 does not have to be formed on this portion. It is preferable that the first insulating film 2 is formed on 50% to 100% of the area of ​​the flat surface D and / or the approximately flat surface D of the surface of the annular convex portion C on the first surface X side of the semiconductor wafer 1, more preferably, the first insulating film 2 is formed on 60% to 100% and preferably, the first insulating film 2 is formed on 70% to 100%.

[0030] 2, the flat surface D or / and the substantially flat surface D of the annular convex portion C are exposed. In this case, the first insulating film 2 is preferably formed on 50% to 90% of the area of ​​the flat surface D or / and the substantially flat surface D of the surface of the annular convex portion C on the first surface X side of the semiconductor wafer 1, more preferably on 60% to 90% of the area of ​​the flat surface D or / and the substantially flat surface D of the surface of the annular convex portion C on the first surface X side of the semiconductor wafer 1, and more preferably on 70% to 90% of the area of ​​the first insulating film 2. In this case, the first insulating film 2 is preferably formed on 50% to 80% of the area of ​​the flat surface D or / and the substantially flat surface D of the surface of the annular convex portion C on the first surface X side of the semiconductor wafer 1, more preferably on 60% to 80% of the area of ​​the first insulating film 2, and more preferably on 70% to 80% of the area of ​​the first insulating film 2.

[0031] The thickness of the first insulating film 2 on the annular convex portion C (the distance between E and G in FIG. 4) is preferably 10 nm or more and 3 μm or less.

[0032] The thickness of the first insulating film 2 on the inclined portion B (the thickness of the first insulating film 2 on the inclined portion B, which is the average thickness of the first insulating film 2 in the vertical direction from the surface of the inclined portion B) is preferably 10 nm or more and 3 μm or less.

[0033] The thickness of the first insulating film 2 on the annular convex portion C is preferably at least 1.0 times the thickness of the first insulating film 2 on the inclined portion B, and more preferably at least 1.2 times and at most 3 times the thickness of the first insulating film 2 on the inclined portion B.

[0034] The first insulating film 2 is preferably a continuous film from the annular convex portion C side toward the inclined portion B side. The thickness of the first insulating film 2 at the boundary portion E between the surface of the annular convex portion C and the inclined portion B is preferably 10 nm or more.

[0035] The first insulating film 2 is preferably formed to occupy 1% to 100% of the area of ​​the inclined portion B, more preferably 5% to 80%, and even more preferably 10% to 50%.

[0036] When the inclination angle R is 20° or more and less than 30°, the first insulating film 2 is preferably formed to cover 1% to 80% of the area of ​​the inclined portion B, more preferably 5% to 50%, and even more preferably 10% to 30%.

[0037] When the inclination angle R is 30° or more and 75° or less, the first insulating film 2 is preferably formed to cover 1% or more and 100% or less of the area of ​​the inclined portion B, more preferably 20% or more and 80% or less, and even more preferably 30% or more and 50% or less.

[0038] Next, a process (second process) of providing a dicing tape 3 on the semiconductor wafer 1 on the first surface X side will be described with reference to the schematic cross-sectional view of Fig. 5. The second process is carried out between the first process and the third process.

[0039] A dicing tape is provided on the first surface X side of the semiconductor wafer 1 of the member having the first insulating film 2 formed on the first surface X side of the semiconductor wafer 1 shown in FIG.

[0040] An appropriate material is selected depending on the cutting method to be adopted in the subsequent cutting step for the dicing tape 3. The dicing tape 3 is a tape that protects and fixes the semiconductor wafer 1 during the subsequent cutting step.

[0041] The dicing tape 3 contacts the first insulating film 2 and the semiconductor wafer 1. When an insulating film or conductive film (not shown) is provided on the first surface X side of the semiconductor wafer 1, the dicing tape 3 contacts these insulating films or conductive films. The dicing tape 3 is preferably in direct contact with the first insulating film 2. The connection form between the member on which the first insulating film 2 is formed on the first surface X side of the semiconductor wafer 1 and the dicing tape 3 is not limited to the form shown in the process schematic cross-sectional view of FIG. 5, including the case where an insulating film or conductive film (not shown) is provided on the first surface X side of the semiconductor wafer 1.

[0042] The area of ​​direct contact between the flat surface D and / or the approximately flat surface D of the annular convex portion C and the dicing tape 3 is preferably 0% or more and 20% or less of the area of ​​the flat surface D and / or the approximately flat surface D of the annular convex portion C, more preferably 0% or more and 10% or less, more preferably 0% or more and 5% or less, and even more preferably 0% or more and 3% or less.

[0043] The area of ​​direct contact between the flat surface D and / or the approximately flat surface D of the annular convex portion C and the dicing tape 3 is preferably 1% or more and 20% or less of the area of ​​the flat surface D and / or the approximately flat surface D of the annular convex portion C, more preferably 1% or more and 10% or less, and even more preferably 1% or more and 5% or less.

[0044] 6, a process (third process) of cutting the semiconductor wafer 1 to separate the annular convex portion C and the inclined portion B from the concave portion A will be described. The third process is carried out between the second process and the fourth process.

[0045] For example, the semiconductor wafer 1 is cut by blade dicing or laser dicing. The cutting in the third step is not singulation in which the semiconductor device is cut into individual chips. In the third step, the position of the recess A on the side of the inclined portion B is cut into a circular shape (circular or approximately circular). By cutting the semiconductor wafer 1, it is separated into a doughnut-shaped member 1B in which the annular convex portion C and the inclined portion B are integrated, and a disk-shaped member 1A including the recess A of the semiconductor wafer 1.

[0046] 5 and 6, a process (fourth process) of separating the separated annular convex portion C and inclined portion B from the dicing tape 3 will be described. The fourth process is carried out after the third process.

[0047] The donut-shaped member (rim portion) 1B of the cut member in FIG. 5 is lifted in the direction of the arrow, and the separated annular convex portion C and inclined portion B, which are the donut-shaped member 1B, are separated from the dicing tape 3.

[0048] By forming the first insulating film 2 on the flat surface D and / or the approximately flat surface D and the inclined portion B of the annular convex portion C, the separated annular convex portion C and the inclined portion B, which are the doughnut-shaped member 1B, can be separated with a weak force when they are separated from the dicing tape 3. By performing the separation with a weak force, damage such as cracking of the semiconductor wafer 1 in the recessed portion A portion, which is the disk-shaped member 1A, during separation can be reduced.

[0049] In order to reduce damage to the semiconductor wafer 1 on the recess A side when peeling off the annular convex portion C and the inclined portion B of the semiconductor wafer 1 on which the first insulating film is formed from the die attach film, the inclination angle R is preferably 20° or more and 75° or less, and more preferably 30° or more and 60° or less.

[0050] From the viewpoint of reducing damage to the semiconductor wafer 1 on the recess A side when peeling off the annular convex portion C and the inclined portion B of the semiconductor wafer 1 on which the first insulating film is formed from the die attach film, it is preferable that the thickness of the first insulating film 2 on the annular convex portion C be 10 nm or more and 3 μm or less.

[0051] From the viewpoint of reducing damage to the semiconductor wafer 1 on the recessed portion A side when peeling off the annular convex portion C and the inclined portion B of the semiconductor wafer 1 on which the first insulating film is formed from the dicing tape 3, it is preferable that the thickness of the first insulating film 2 on the inclined portion B be 10 nm or more and 3 μm or less.

[0052] The higher the average unevenness height on the first surface X side of the annular convex portion C, the stronger the bonding strength between the dicing tape 3 and the semiconductor wafer 1.

[0053] When the average unevenness height on the first surface X side of the annular convex portion C is 5 [nm] or more and 30 [nm] or less, from the viewpoint of reducing damage to the semiconductor wafer 1 on the recess A side when peeling off the annular convex portion C and the inclined portion B of the semiconductor wafer 1 on which the first insulating film is formed from the dicing tape 3, when the average unevenness height on the first surface X side of the annular convex portion C is 5 [nm] or more and 30 [nm] or less, the thickness of the first insulating film 2 on the annular convex portion C is preferably 50 [nm] or more and 3 [μm] or less, more preferably 100 [nm] or more and 2 [μm] or less, and even more preferably 200 [nm] or more and 1 [μm] or less.

[0054] When the average unevenness height on the first surface X side of the annular convex portion C is 5 [nm] or more and 30 [nm] or less, from the viewpoint of reducing damage to the semiconductor wafer 1 on the recess A side when peeling off the annular convex portion C and the inclined portion B of the semiconductor wafer 1 on which the first insulating film is formed from the dicing tape 3, when the average unevenness height on the first surface X side of the annular convex portion C is 5 [nm] or more and 30 [nm] or less, the thickness of the first insulating film 2 on the inclined portion B is preferably 50 [nm] or more and 3 [μm] or less, more preferably 100 [nm] or more and 2 [μm] or less, and even more preferably 200 [nm] or more and 1 [μm] or less.

[0055] When the average unevenness height on the first surface X side of the annular convex portion C is 5 [nm] or more and 30 [nm] or less, from the viewpoint of reducing damage to the semiconductor wafer 1 on the recess A side when peeling off the annular convex portion C and the inclined portion B of the semiconductor wafer 1 on which the first insulating film is formed from the dicing tape 3, when the average unevenness height on the first surface X side of the annular convex portion C is 5 [nm] or more and 30 [nm] or less, the thickness of the first insulating film 2 on the annular convex portion C is preferably 50 [nm] or more and 3 [μm] or less, more preferably 100 [nm] or more and 2 [μm] or less, and even more preferably 200 [nm] or more and 1 [μm] or less.

[0056] When the average unevenness height on the first surface X side of the annular convex portion C is 5 [nm] or more and 30 [nm] or less, from the viewpoint of reducing damage to the semiconductor wafer 1 on the recess A side when peeling off the annular convex portion C and the inclined portion B of the semiconductor wafer 1 on which the first insulating film is formed from the dicing tape 3, when the average unevenness height on the first surface X side of the annular convex portion C is 5 [nm] or more and 30 [nm] or less, the thickness of the first insulating film 2 on the inclined portion B is preferably 50 [nm] or more and 3 [μm] or less, more preferably 100 [nm] or more and 2 [μm] or less, and even more preferably 200 [nm] or more and 1 [μm] or less.

[0057] After the fourth step, a semiconductor device (for example, a bare chip) can be manufactured through any steps.

[0058] By adopting the semiconductor device manufacturing method of the embodiment, the separation ability of the dicing tape 3 is improved and damage to the semiconductor wafer 1, including the recess A in which the semiconductor element region is formed, can be reduced, thereby contributing to improving the yield in the manufacture of semiconductor devices.

[0059] Second embodiment A method for manufacturing a semiconductor device according to a second embodiment includes a step of forming a first insulating film on an annular convex portion and an inclined portion of a semiconductor wafer having a first surface and a second surface opposite to the first surface, the semiconductor wafer having an annular convex portion on the outer periphery of the first surface, a concave portion on the central side, and an inclined portion connecting the annular convex portion and the concave portion (first step), a step of forming a first conductive film on the first surface on the inner periphery side of the first insulating film (fifth step), a step of forming a second insulating film on the first insulating film and the first conductive film (sixth step), a step of forming a second conductive film on the second surface side (seventh step), a step of removing the second insulating film (eighth step), a step of providing a dicing tape on the semiconductor wafer on the first surface side (second step), a step of cutting the semiconductor wafer and separating the annular convex portion and the inclined portion from the concave portion (third step), and a step of separating the separated annular convex portion and the inclined portion from the dicing tape (fourth step).

[0060] The second embodiment relates to a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device of the second embodiment is a modified example of the method for manufacturing a semiconductor device of the first embodiment. The method for manufacturing a semiconductor device of the second embodiment is a more specific method of the method for manufacturing a semiconductor device of the first embodiment. Descriptions of contents common to the first and second embodiments will be omitted.

[0061] 8 is a flowchart of the method for manufacturing the semiconductor device according to the second embodiment. 1A and 1B are schematic cross-sectional views and schematic top plan views illustrating steps of a method for manufacturing a semiconductor device according to a first embodiment;

[0062] 9 to 13, a process (first process) of forming a first insulating film 2 on annular convex portion C and on inclined portion B of a semiconductor wafer 1 having a first surface X and a second surface Y on the opposite side of the first surface X, and having an annular convex portion C on the outer periphery of the first surface X, a concave portion A on the central side, and an inclined portion B connecting the annular convex portion C and the concave portion A will be described.

[0063] In the first step of the second embodiment, the first insulating film 2 is formed over the entire first surface X of the semiconductor wafer 1, and then processed to form the first insulating film 2 on the annular convex portion C and the inclined portion B.

[0064] First, a first insulating film 2 is formed over the entire first surface X of a member shown in the process schematic cross-sectional view of Fig. 9 to obtain a member shown in the process schematic cross-sectional view of Fig. 10. The member shown in the process schematic cross-sectional view of Fig. 9 has an electrode pad 4 and a protective film 5 provided on the second surface Y side.

[0065] The electrode pad 4 is, for example, a conductive metal film that is electrically connected to the semiconductor device. The electrode pad 4 is an electrode of the semiconductor device.

[0066] The protective film 5 is an insulating film that covers the electrode pads 4. It is preferable that the electrode pads 4 are not exposed on the surface of the protective film 5. The protective film 5 is an insulating film mainly composed of an insulating resin such as polyethylene, naphthalene, polyolefin, or polyethylene terephthalate.

[0067] After forming the first insulating film 2 over the entire first surface X of the semiconductor wafer 1, a resist (mask) 6 is formed to obtain a member shown in the process schematic cross-sectional view of Fig. 11. The first insulating film 2 is formed by depositing SiO2 by plasma CVD, for example. The deposition temperature is, for example, 200°C, taking into account the heat resistance of the protective film 5.

[0068] Next, the first insulating film 2 is processed using the resist 6 of the process schematic member in Fig. 11 to remove the second insulating film 2 formed in part of the recess A and the inclined portion B of the semiconductor wafer 1, thereby obtaining the member shown in the process schematic cross-sectional view in Fig. 12. For example, the first insulating film 2, which is a SiO2 film, is treated by wet etching to remove the first insulating film 2 in the part where the resist 6 is not formed.

[0069] Next, the resist 6 of the member shown in the process schematic cross-sectional view of FIG. 12 is removed to obtain the member shown in the process schematic cross-sectional view of FIG.

[0070] The step (fifth step) of forming the first conductive film 7 on the first surface X on the inner periphery side of the first insulating film 2 will be described with reference to the process schematic cross-sectional views of FIGS.

[0071] The fifth step is a step of forming a first conductive film 7 on the first surface X on the inner periphery side of the first insulating film 2, where the first insulating film 2 is not formed. The fifth step is performed between the first step and the sixth step.

[0072] As shown in the process schematic cross-sectional view of Fig. 14, the protective film 5 of the member in the process schematic cross-sectional view of Fig. 13 is removed. The protective film 5 is removed by peeling it off, for example. After removing the protective film 5, it is preferable to perform furnace annealing.

[0073] Next, a first conductive film 7 is formed on the member shown in the process schematic cross-sectional view of FIG. 14 by a sputtering method or the like on the first surface X on the inner side of the first insulating film 2 where the first insulating film 2 is not formed, to obtain a member shown in the process schematic cross-sectional view of FIG. 15.

[0074] The first conductive film 7 is formed so as not to overlap with the first insulating film 2. The first insulating film 2 and the first conductive film 7 may be in direct contact with each other in the surface direction of the first surface X, or may be spaced apart from each other. It is preferable that the first conductive film 7 and the first insulating film 2 are not laminated in the lamination direction of the first insulating film 2 and the semiconductor wafer 1 (the lamination direction of the first insulating film 2 and the semiconductor wafer 1 in FIG. 15), including the case where the first insulating film 2 and the first conductive film 7 are in direct contact with each other in the surface direction of the first surface X. If the first conductive film 7 is laminated on the first insulating film 2, it is undesirable that the first conductive film 7 is easily peeled off from the interface of the laminated portion.

[0075] It is preferable that the first conductive film 7 is not in direct contact with a surface of the first insulating film 2 formed on the annular convex portion C opposite to the surface facing the semiconductor wafer 1. In addition, it is preferable that the first conductive film 7 is not in direct contact with a surface of the first insulating film 2 formed on the inclined portion B opposite to the surface facing the semiconductor wafer 1.

[0076] The distance between the first insulating film 2 and the first conductive film 7 in the planar direction of the first surface X is preferably 0.0 mm or more and 2.0 mm or less, and more preferably 0.0 mm or more and 1.0 mm or less.

[0077] From the viewpoint of forming the first conductive film 7 so as not to be stacked on the first insulating film 2, the distance between the first insulating film 2 and the first conductive film 7 in the planar direction of the first surface X is preferably 0.1 mm or more and 2.0 mm or less, and more preferably 0.2 mm or more and 1.0 mm or less.

[0078] It is preferable to use an outer periphery cover that covers the first insulating film 2 so that the first conductive film 7 is not stacked on the first insulating film 2. The outer periphery cover has a circular opening, and a metal film is deposited in the area inside the opening. The outer periphery cover is, for example, a susceptor or a clamp.

[0079] The first conductive film 7 is preferably a continuous film without any openings and without divisions.

[0080] The process (sixth process) of forming the second insulating film 8 on the first insulating film 2 and the first conductive film 7 will be described with reference to the process schematic cross-sectional views of FIG.

[0081] The sixth step is a step of forming a second insulating film 8 over the entire first surface X side of the semiconductor wafer 1, which is on the first insulating film 2 and the first conductive film 7. The sixth step is performed between the fifth step and the seventh step.

[0082] A second insulating film 8 is formed on a member shown in the process schematic cross-sectional view of Fig. 15. Before the sixth process, the first insulating film 2 has been formed on the annular convex portion C in the first process, and the annular convex portion C is already sufficiently covered with the insulating film. Therefore, the second insulating film 8 can be formed without worrying too much about the coverage of the first insulating film 2 and the first conductive film 7.

[0083] Since the boundary portion E between the flat surface D and / or the approximately flat surface D of the annular convex portion C and the inclined portion B is covered with the first insulating film 2, it is preferable that the second insulating film 8 is formed so that the surface of the first conductive film 7 is not exposed.

[0084] Since the boundary portion E between the flat surface D and / or the approximately flat surface D of the annular convex portion C and the inclined portion B is covered with the first insulating film 2, the second insulating film 8 is preferably formed so as to cover the surface of the semiconductor wafer 1 in the gap portion between the first insulating film 2 and the first conductive film 7. As shown in the process schematic cross-sectional view of FIG. 15, the second insulating film 8 may be filled in the gap portion between the first insulating film 2 and the first conductive film 7.

[0085] The second insulating film 8 is preferably an inorganic insulating film, a resin insulating film, or an insulating film containing an inorganic insulator and a resin.

[0086] The second insulating film 8 is, for example, a coating film, but may be a film formed by other methods.

[0087] The first surface X side of the semiconductor wafer 1 is entirely covered with the first insulating film 2 and the second insulating film 8. Then, it is preferable that abnormal deposition of metal on the semiconductor wafer 1 and / or the first conductive film 7 can be reduced or eliminated in the next eighth step. When the eighth step is omitted, the seventh step can be omitted.

[0088] When the fifth step is omitted, the second insulating film 8 is formed on the open surface on the first surface X side of the semiconductor wafer 1.

[0089] If electrodes are not formed on both sides of the semiconductor wafer 1 after the first insulating film 2 is formed, the fifth, sixth, seventh and eighth steps are omitted.

[0090] The step (seventh step) of forming the second conductive film 9 on the second surface Y side will be described with reference to the process schematic cross-sectional views of FIG.

[0091] The seventh step is a step of forming a second conductive film 9 on the electrode pad 4 on the second surface Y side by electroless plating or the like. The seventh step is performed between the sixth step and the eighth step.

[0092] The step of removing the second insulating film 8 (eighth step) will be described with reference to the process schematic cross-sectional views of FIGS.

[0093] The eighth step is a step of removing the second insulating film 8 on the first surface X side by peeling or the like. The eighth step is carried out between the seventh step and the second step.

[0094] When the second insulating film 8 is formed in the gap portion between the first insulating film 2 and the first conductive film 7 at the time when the sixth step is performed, the second insulating film 8 may remain in the gap portion between the first insulating film 2 and the first conductive film 7 as shown in the process schematic cross-sectional view of FIG. 18, or the second insulating film 8 may be removed in the gap portion between the first insulating film 2 and the first conductive film 7 as shown in the process schematic cross-sectional view of FIG. 19.

[0095] Next, a step (second step) of providing a dicing tape 3 on the semiconductor wafer 1 on the first surface X side will be described with reference to the schematic cross-sectional view of Figure 20. The second step is carried out between the eighth step and the third step.

[0096] As in the first embodiment, the dicing tape 3 is attached to the semiconductor wafer 1 on the first surface X. Then, the third and fourth steps are performed as in the first embodiment, thereby manufacturing the semiconductor device.

[0097] By adopting the semiconductor device manufacturing method of the embodiment, the separation property of the dicing tape 3 is improved and damage to the semiconductor wafer 1 including the recess A where the semiconductor element region is formed can be reduced, which contributes to improving the yield of the semiconductor device manufacturing. In addition, abnormal precipitation during plating of the second conductive film 9 can be reduced, which contributes to improving the yield of the semiconductor device manufacturing.

[0098] Third embodiment A method for manufacturing a semiconductor device according to a third embodiment includes a step of forming a first insulating film on an annular convex portion and an inclined portion of a semiconductor wafer having a first surface and a second surface opposite to the first surface, the semiconductor wafer having an annular convex portion on the outer periphery of the first surface, a concave portion on the central side, and an inclined portion connecting the annular convex portion and the concave portion (first step), a step of forming a first conductive film on the first surface on the inner periphery side of the first insulating film (fifth step), a step of forming a second insulating film on the first insulating film and the first conductive film (sixth step), a step of forming a second conductive film on the second surface side (seventh step), a step of removing the second insulating film (eighth step), a step of providing a dicing tape on the semiconductor wafer on the first surface side (second step), a step of cutting the semiconductor wafer and separating the annular convex portion and the inclined portion from the concave portion (third step), and a step of separating the separated annular convex portion and the inclined portion from the dicing tape (fourth step).

[0099] The third embodiment relates to a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device of the third embodiment is a modified example of the method for manufacturing a semiconductor device of the first embodiment and / or the second embodiment. The method for manufacturing a semiconductor device of the third embodiment is a more specific method of the method for manufacturing a semiconductor device of the first embodiment. Descriptions of contents common to the first to third embodiments will be omitted.

[0100] The method for manufacturing the semiconductor device according to the third embodiment will be described with reference to a flow chart and schematic cross-sectional views of the process of the method for manufacturing the semiconductor device according to the second embodiment.

[0101] 9 and 13, a process (first process) of forming a first insulating film 2 on annular convex portion C and on inclined portion B of a semiconductor wafer 1 having a first surface X and a second surface Y on the opposite side of the first surface X, and having an annular convex portion C on the outer periphery of the first surface X, a concave portion A on the central side, and an inclined portion B connecting the annular convex portion C and the concave portion A will be described.

[0102] A first insulating film 2 is formed by inkjet on the member shown in the process schematic cross-sectional view of FIG. 9, to obtain the member shown in the process schematic cross-sectional view of FIG.

[0103] The step (fifth step) of forming a first conductive film on the first surface on the inner periphery side of the first insulating film will be described with reference to the process schematic cross-sectional views of FIGS.

[0104] As shown in the process schematic cross-sectional view of Fig. 14, the protective film 5 of the member in the process schematic cross-sectional view of Fig. 13 is removed. The protective film 5 is removed by peeling it off, etc. After removing the protective film 5, it is preferable to perform furnace annealing to bake (harden) the first insulating film 2.

[0105] Then, a first conductive film 7 is formed by sputtering on the member shown in the process schematic cross-sectional view of FIG. 14, to obtain the member shown in the process schematic cross-sectional view of FIG.

[0106] Then, the sixth to eighth steps and the second to fourth steps, etc. are carried out to suitably manufacture the semiconductor device.

[0107] Here, the unevenness of the flat surface D and / or the substantially flat surface D of the annular convex portion C common to the first, second and third embodiments will be described with reference to the partial schematic cross-sectional view of the semiconductor wafer 1 in Fig. 21. Fig. 21 is a schematic cross-sectional view of a portion of the b-b' cross section in Fig. 3.

[0108] 21, the unevenness height (average value) of the flat surface D and / or the approximately flat surface D of the annular convex portion C of the semiconductor wafer 1 itself is indicated by H1, and the unevenness height (average value) of the flat surface D and / or the approximately flat surface D of the annular convex portion C after the formation of the first insulating film 2 is indicated by H2. The unevenness height H1 becomes large when the inclined portion B and the concave portion A are formed by wet etching.

[0109] The unevenness height H2 is reduced compared to the unevenness height H1. This is because, even if the thickness of the first insulating film 2 formed on the inclined surface of the unevenness is the same, the cross section becomes arc-shaped (the center of the arc is in a direction from the semiconductor wafer 1 toward the first insulating film 2 than the arc) so that the first insulating film 2 at the bottom of the recess is thicker regardless of the shape of the upper and lower ends of the unevenness, and the cross section becomes arc-shaped (the center of the arc is in a direction from the first insulating film 2 toward the semiconductor wafer 1 than the arc) so that the first insulating film 2 at the upper part of the protrusion is thinner. When the dicing tape 3 is provided over the entire annular protrusion C of the semiconductor wafer 1, the high H1 increases the adhesion with the dicing tape 3, and the semiconductor wafer 1 at the recess A is more likely to crack during separation in the fourth step.

[0110] After the first insulating film 2 is formed, even if a portion of the uneven surface of the annular convex portion C of the semiconductor wafer 1 is exposed, the unevenness height H2 of the flat surface D and / or the approximately flat surface D of the annular convex portion C is reduced compared to the unevenness height H1, thereby reducing the adhesion to the dicing tape 3 and reducing cracks in the semiconductor wafer 1 at the concave portion A during separation in the fourth step.

[0111] In the embodiment, since the inclined portion B is present, the first insulating film 2 is also formed at the boundary portion E between the annular convex portion C and the inclined portion B, and therefore it is preferable that the adhesion with the dicing tape 3 can be reduced at the boundary portion E between the annular convex portion C and the inclined portion B.

[0112] In this embodiment, since the inclined portion B is present, the first insulating film 2 is also formed at the boundary portion E between the annular convex portion C and the inclined portion B, so that it is preferable to be able to prevent abnormal precipitation in the seventh step.

[0113] In addition, it is preferable that by forming a second insulating film 8 on the surface in which the unevenness of the flat surface D and / or the approximately flat surface D of the annular convex portion C has been reduced by the first insulating film 2, the unevenness of the surface can be further reduced and the adhesion to the dicing tape 3 can be reduced.

[0114] If the inclination angle R is made small, it is possible that the second insulating film 8 can suitably alleviate the above-mentioned unevenness without forming the first insulating film 2 due to the gentle inclination. However, if the inclination angle R is made small, the area of ​​the inclined portion B when the semiconductor wafer 1 is viewed from the first surface X side increases. This reduces the effective element area of ​​the semiconductor wafer 1, which is economically undesirable. In this case, the effective element area of ​​the semiconductor wafer 1 can be increased by reducing the area of ​​the flat surface D and / or the approximately flat surface D of the annular convex portion C, but in this case, the annular convex portion C becomes small and the strength of the semiconductor wafer 1 decreases due to the rim shape, which is undesirable and not practical.

[0115] From the above viewpoints, the inclination angle R is preferably 20° or more and 75° or less, and more preferably 30° or more and 60° or less.

[0116] It is preferable that by adopting the configuration of the embodiment, a good balance can be achieved between the strength of the semiconductor wafer 1, a large effective element area of ​​the semiconductor wafer 1, and reduced cracking of the semiconductor wafer 1 when peeled off from the dicing tape 3.

[0117] By adopting the configuration of the embodiment, it is preferable that abnormal precipitation during the formation of the second conductive film 9 can be reduced while obtaining the above-mentioned effects.

[0118] The technical proposal of the specification is appended below. Technical proposal 1 a step of forming a first insulating film on the annular convex portion and the inclined portion of a semiconductor wafer having a first surface and a second surface on the opposite side to the first surface, the first surface having an annular convex portion on the outer periphery thereof, a concave portion on the center side thereof, and an inclined portion connecting the annular convex portion and the inclined portion; providing a dicing tape on the first surface of the semiconductor wafer; cutting the semiconductor wafer to separate the annular protrusion and the inclined portion from the recess; separating the separated annular convex portion and the inclined portion from the dicing tape; A method for manufacturing a semiconductor device having the above structure. Technical proposal 2 The method for manufacturing a semiconductor device according to Technical Proposal 1, wherein the first insulating film is an inorganic film. Technical proposal 3 The method for manufacturing a semiconductor device according to Technical Scheme 1 or 2, wherein the thickness of the first insulating film on the annular convex portion is 10 nm or more and 3 μm or less. Technical proposal 4 A method for manufacturing a semiconductor device according to any one of Technical Schemes 1 to 3, wherein the thickness of the first insulating film on the inclined portion is 10 nm or more and 3 μm or less. Technical proposal 5 a flat surface or / and a substantially flat surface is present on the annular convex portion on the first surface side of the semiconductor wafer; The method for manufacturing a semiconductor device according to any one of Technical Schemes 1 to 4, wherein the first insulating film is formed so as to cover 50% to 100% of the area of ​​the flat surface and / or the approximately flat surface. Technical proposal 6 a flat surface or / and a substantially flat surface is present on the annular convex portion on the first surface side of the semiconductor wafer; The method for manufacturing a semiconductor device according to any one of Technical Schemes 1 to 5, wherein the first insulating film is formed on 50% to 90% of the area of ​​the flat surface and / or the approximately flat surface. Technical proposal 7 A method for manufacturing a semiconductor device described in any one of technical proposals 1 to 6, wherein the thickness of the first insulating film on the annular convex portion is 1.2 to 3 times the thickness of the first insulating film on the inclined portion. Technical proposal 8 The method for manufacturing a semiconductor device according to any one of Technical Schemes 1 to 7, wherein the first insulating film is formed to occupy 1% to 100% of the area of ​​the inclined portion. Technical proposal 9 A method for manufacturing a semiconductor device according to any one of technical proposals 1 to 8, wherein the inclination angle of the inclined portion is 20° or more and 75° or less. Technical proposal 10 A method for manufacturing a semiconductor device described in any one of technical proposals 1 to 9, wherein when the inclination angle of the inclined portion is 20° or more and less than 30°, the first insulating film is formed to be 1% or more and 80% or less of the area of ​​the inclined portion B. Technical proposal 11 A method for manufacturing a semiconductor device described in any one of technical proposals 1 to 10, wherein when the inclination angle of the inclined portion is 30° or more and 75° or less, the first insulating film is formed at 1% or more and 100% or less of the area of ​​the inclined portion B. Technical proposal 12 A method for manufacturing a semiconductor device described in any one of Technical Proposals 1 to 11, wherein when the average unevenness height on the first surface side of the annular convex portion is 5 nm or more and 30 nm or less, the thickness of the first insulating film on the annular convex portion is 50 nm or more and 3 μm or less. Technical proposal 13 A method for manufacturing a semiconductor device described in any one of technical proposals 1 to 12, wherein when the average unevenness height on the first surface side of the annular convex portion is 5 nm or more and 30 nm or less, the thickness of the first insulating film on the inclined portion is 50 nm or more and 3 μm or less. Technical proposal 14 A method for manufacturing a semiconductor device described in any one of Technical Proposals 1 to 14, wherein when the average unevenness height on the first surface side of the annular convex portion is 5 nm or more and 30 nm or less, the thickness of the first insulating film on the annular convex portion is 50 nm or more and 3 μm or less, and the thickness of the first insulating film on the inclined portion is 50 nm or more and 3 μm or less. Technical proposal 15 the first insulating film is formed on the entire surface of the semiconductor wafer on the first surface side by plasma CVD; the temperature of the semiconductor wafer when the first insulating film is formed by the plasma CVD is 200° C. or less; A method for manufacturing a semiconductor device according to any one of technical proposals 1 to 14, wherein the first insulating film formed overall is processed by wet etching using a resist. Technical proposal 16 forming a first conductive film on the first surface on an inner periphery side of the first insulating film; forming a second insulating film on the first insulating film and the first conductive film; forming a second conductive film on the second surface side; removing the second insulating film; 16. The method for manufacturing a semiconductor device according to any one of Technical Solutions 1 to 15, comprising the steps of: between the step of forming the first insulating film and the step of providing the dicing tape. Technical proposal 17 The method for manufacturing a semiconductor device according to Technical Proposal 16, wherein the first conductive film is formed by a sputtering method so as not to be stacked on the first insulating film. Technical proposal 18 The method for manufacturing a semiconductor device according to Technical Scheme 16 or 17, wherein the second conductive film is formed by electroless plating. Technical proposal 19 A method for manufacturing a semiconductor device described in any one of technical proposals 16 to 18, wherein the distance between the first insulating film and the first conductive film in the surface direction of the inclined portion is 0.0 mm or more and 2.0 mm or less. Technical proposal 20 A method for manufacturing a semiconductor device described in any one of technical proposals 16 to 19, wherein the distance between the first insulating film and the first conductive film in the surface direction of the inclined portion is 0.1 mm or more and 2.0 mm or less.

[0119] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or changed with components of another embodiment. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0120] 1: Semiconductor wafer 1A: Materials 1B: Materials 2: First insulating film 3: Dicing tape 4: Electrode pads 5:Protective film 6: Resist 7: First conductive film 8: Second insulating film 9: Second conductive film A: Concave B: Inclined part C: Circular convex part D: Flat surface E: Boundary part F: Connection edge H1: Height of unevenness H2: Height of unevenness R: Tilt angle X: 1st page Y: 2nd side

Claims

1. a step of forming a first insulating film on the annular convex portion and the inclined portion of a semiconductor wafer having a first surface and a second surface on an opposite side to the first surface, the first surface having an annular convex portion on an outer periphery thereof, a concave portion on a central side thereof, and an inclined portion connecting the annular convex portion and the inclined portion; providing a dicing tape on the first surface of the semiconductor wafer; cutting the semiconductor wafer to separate the annular protrusion and the inclined portion from the recess; separating the separated annular convex portion and the inclined portion from the dicing tape; A method for manufacturing a semiconductor device having the above structure.

2. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the first insulating film is an inorganic film.

3. 2. The method for manufacturing a semiconductor device according to claim 1, wherein a thickness of the first insulating film on the annular convex portion is 10 nm or more and 3 μm or less.

4. 2. The method for manufacturing a semiconductor device according to claim 1, wherein a thickness of the first insulating film on the inclined portion is 10 nm or more and 3 μm or less.

5. a flat surface or / and a substantially flat surface is present on the annular convex portion on the first surface side of the semiconductor wafer; 2. The method for manufacturing a semiconductor device according to claim 1, wherein the first insulating film is formed so as to occupy 50% to 100% of an area of ​​the flat surface or / and the substantially flat surface.

6. a flat surface or / and a substantially flat surface is present on the annular convex portion on the first surface side of the semiconductor wafer; 2. The method for manufacturing a semiconductor device according to claim 1, wherein the first insulating film is formed so as to occupy 50% to 90% of an area of ​​the flat surface and / or the substantially flat surface.

7. 2 . The method for manufacturing a semiconductor device according to claim 1 , wherein the thickness of the first insulating film on the annular convex portion is 1.2 to 3 times the thickness of the first insulating film on the inclined portion.

8. 2 . The method for manufacturing a semiconductor device according to claim 1 , wherein the first insulating film is formed to cover 1% to 100% of the area of ​​the inclined portion.

9. 2. The method for manufacturing a semiconductor device according to claim 1, wherein an inclination angle of the inclined portion is equal to or greater than 20[°] and equal to or less than 75[°].

10. 2. The method for manufacturing a semiconductor device according to claim 1, wherein when the inclination angle of the inclined portion is 20° or more and less than 30°, the first insulating film is formed to cover 1% to 80% of the area of ​​the inclined portion B.

11. 2. The method for manufacturing a semiconductor device according to claim 1, wherein when the inclination angle of the inclined portion is 30° or more and 75° or less, the first insulating film is formed to be 1% or more and 100% or less of the area of ​​the inclined portion B.

12. 2. The method for manufacturing a semiconductor device according to claim 1, wherein when the average unevenness height on the first surface side of the annular convex portion is 5 nm or more and 30 nm or less, the thickness of the first insulating film on the annular convex portion is 50 nm or more and 3 μm or less.

13. 2. The method for manufacturing a semiconductor device according to claim 1, wherein when the average unevenness height on the first surface side of the annular convex portion is 5 nm or more and 30 nm or less, the thickness of the first insulating film on the inclined portion is 50 nm or more and 3 μm or less.

14. 2. The method for manufacturing a semiconductor device according to claim 1, wherein when the average unevenness height on the first surface side of the annular convex portion is 5 nm or more and 30 nm or less, the thickness of the first insulating film on the annular convex portion is 50 nm or more and 3 μm or less, and the thickness of the first insulating film on the inclined portion is 50 nm or more and 3 μm or less.

15. the first insulating film is formed on the entire surface of the semiconductor wafer on the first surface side by plasma CVD; the temperature of the semiconductor wafer when the first insulating film is formed by the plasma CVD is 200° C. or less; 2. The method of claim 1, wherein the first insulating film formed on the entire surface is processed by wet etching using a resist.

16. forming a first conductive film on the first surface on an inner periphery side of the first insulating film; forming a second insulating film on the first insulating film and the first conductive film; forming a second conductive film on the second surface side; removing the second insulating film; 16. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of: providing a first insulating film on the first insulating film and a step of providing a dicing tape on the first insulating film.

17. 17. The method for manufacturing a semiconductor device according to claim 16, wherein the first conductive film is formed by a sputtering method so as not to be laminated on the first insulating film.

18. The method for manufacturing a semiconductor device according to claim 16 , wherein the second conductive film is formed by electroless plating.

19. 17. The method for manufacturing a semiconductor device according to claim 16, wherein a distance between the first insulating film and the first conductive film in a surface direction of the inclined portion is 0.0 mm or more and 2.0 mm or less.

20. 17. The method for manufacturing a semiconductor device according to claim 16, wherein a distance between the first insulating film and the first conductive film in a surface direction of the inclined portion is 0.1 mm or more and 2.0 mm or less.

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